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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / kernel / linux / v4.14 / drivers / regulator / ab8500.c
blob: c9f20e1394e3b233306f5902f5d1d823fecaac2b [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
9 *
10 * AB8500 peripheral regulators
11 *
12 * AB8500 supports the following regulators:
13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
14 *
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
17 */
18#include <linux/init.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/err.h>
22#include <linux/platform_device.h>
23#include <linux/mfd/abx500.h>
24#include <linux/mfd/abx500/ab8500.h>
25#include <linux/of.h>
26#include <linux/regulator/of_regulator.h>
27#include <linux/regulator/driver.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/ab8500.h>
30#include <linux/slab.h>
31
32/**
33 * struct ab8500_shared_mode - is used when mode is shared between
34 * two regulators.
35 * @shared_regulator: pointer to the other sharing regulator
36 * @lp_mode_req: low power mode requested by this regulator
37 */
38struct ab8500_shared_mode {
39 struct ab8500_regulator_info *shared_regulator;
40 bool lp_mode_req;
41};
42
43/**
44 * struct ab8500_regulator_info - ab8500 regulator information
45 * @dev: device pointer
46 * @desc: regulator description
47 * @regulator_dev: regulator device
48 * @shared_mode: used when mode is shared between two regulators
49 * @load_lp_uA: maximum load in idle (low power) mode
50 * @update_bank: bank to control on/off
51 * @update_reg: register to control on/off
52 * @update_mask: mask to enable/disable and set mode of regulator
53 * @update_val: bits holding the regulator current mode
54 * @update_val_idle: bits to enable the regulator in idle (low power) mode
55 * @update_val_normal: bits to enable the regulator in normal (high power) mode
56 * @mode_bank: bank with location of mode register
57 * @mode_reg: mode register
58 * @mode_mask: mask for setting mode
59 * @mode_val_idle: mode setting for low power
60 * @mode_val_normal: mode setting for normal power
61 * @voltage_bank: bank to control regulator voltage
62 * @voltage_reg: register to control regulator voltage
63 * @voltage_mask: mask to control regulator voltage
64 */
65struct ab8500_regulator_info {
66 struct device *dev;
67 struct regulator_desc desc;
68 struct regulator_dev *regulator;
69 struct ab8500_shared_mode *shared_mode;
70 int load_lp_uA;
71 u8 update_bank;
72 u8 update_reg;
73 u8 update_mask;
74 u8 update_val;
75 u8 update_val_idle;
76 u8 update_val_normal;
77 u8 mode_bank;
78 u8 mode_reg;
79 u8 mode_mask;
80 u8 mode_val_idle;
81 u8 mode_val_normal;
82 u8 voltage_bank;
83 u8 voltage_reg;
84 u8 voltage_mask;
85 struct {
86 u8 voltage_limit;
87 u8 voltage_bank;
88 u8 voltage_reg;
89 u8 voltage_mask;
90 } expand_register;
91};
92
93/* voltage tables for the vauxn/vintcore supplies */
94static const unsigned int ldo_vauxn_voltages[] = {
95 1100000,
96 1200000,
97 1300000,
98 1400000,
99 1500000,
100 1800000,
101 1850000,
102 1900000,
103 2500000,
104 2650000,
105 2700000,
106 2750000,
107 2800000,
108 2900000,
109 3000000,
110 3300000,
111};
112
113static const unsigned int ldo_vaux3_voltages[] = {
114 1200000,
115 1500000,
116 1800000,
117 2100000,
118 2500000,
119 2750000,
120 2790000,
121 2910000,
122};
123
124static const unsigned int ldo_vaux56_voltages[] = {
125 1800000,
126 1050000,
127 1100000,
128 1200000,
129 1500000,
130 2200000,
131 2500000,
132 2790000,
133};
134
135static const unsigned int ldo_vaux3_ab8540_voltages[] = {
136 1200000,
137 1500000,
138 1800000,
139 2100000,
140 2500000,
141 2750000,
142 2790000,
143 2910000,
144 3050000,
145};
146
147static const unsigned int ldo_vaux56_ab8540_voltages[] = {
148 750000, 760000, 770000, 780000, 790000, 800000,
149 810000, 820000, 830000, 840000, 850000, 860000,
150 870000, 880000, 890000, 900000, 910000, 920000,
151 930000, 940000, 950000, 960000, 970000, 980000,
152 990000, 1000000, 1010000, 1020000, 1030000,
153 1040000, 1050000, 1060000, 1070000, 1080000,
154 1090000, 1100000, 1110000, 1120000, 1130000,
155 1140000, 1150000, 1160000, 1170000, 1180000,
156 1190000, 1200000, 1210000, 1220000, 1230000,
157 1240000, 1250000, 1260000, 1270000, 1280000,
158 1290000, 1300000, 1310000, 1320000, 1330000,
159 1340000, 1350000, 1360000, 1800000, 2790000,
160};
161
162static const unsigned int ldo_vintcore_voltages[] = {
163 1200000,
164 1225000,
165 1250000,
166 1275000,
167 1300000,
168 1325000,
169 1350000,
170};
171
172static const unsigned int ldo_sdio_voltages[] = {
173 1160000,
174 1050000,
175 1100000,
176 1500000,
177 1800000,
178 2200000,
179 2910000,
180 3050000,
181};
182
183static const unsigned int fixed_1200000_voltage[] = {
184 1200000,
185};
186
187static const unsigned int fixed_1800000_voltage[] = {
188 1800000,
189};
190
191static const unsigned int fixed_2000000_voltage[] = {
192 2000000,
193};
194
195static const unsigned int fixed_2050000_voltage[] = {
196 2050000,
197};
198
199static const unsigned int fixed_3300000_voltage[] = {
200 3300000,
201};
202
203static const unsigned int ldo_vana_voltages[] = {
204 1050000,
205 1075000,
206 1100000,
207 1125000,
208 1150000,
209 1175000,
210 1200000,
211 1225000,
212};
213
214static const unsigned int ldo_vaudio_voltages[] = {
215 2000000,
216 2100000,
217 2200000,
218 2300000,
219 2400000,
220 2500000,
221 2600000,
222 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
223};
224
225static const unsigned int ldo_vdmic_voltages[] = {
226 1800000,
227 1900000,
228 2000000,
229 2850000,
230};
231
232static DEFINE_MUTEX(shared_mode_mutex);
233static struct ab8500_shared_mode ldo_anamic1_shared;
234static struct ab8500_shared_mode ldo_anamic2_shared;
235static struct ab8500_shared_mode ab8540_ldo_anamic1_shared;
236static struct ab8500_shared_mode ab8540_ldo_anamic2_shared;
237
238static int ab8500_regulator_enable(struct regulator_dev *rdev)
239{
240 int ret;
241 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
242
243 if (info == NULL) {
244 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
245 return -EINVAL;
246 }
247
248 ret = abx500_mask_and_set_register_interruptible(info->dev,
249 info->update_bank, info->update_reg,
250 info->update_mask, info->update_val);
251 if (ret < 0) {
252 dev_err(rdev_get_dev(rdev),
253 "couldn't set enable bits for regulator\n");
254 return ret;
255 }
256
257 dev_vdbg(rdev_get_dev(rdev),
258 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
259 info->desc.name, info->update_bank, info->update_reg,
260 info->update_mask, info->update_val);
261
262 return ret;
263}
264
265static int ab8500_regulator_disable(struct regulator_dev *rdev)
266{
267 int ret;
268 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
269
270 if (info == NULL) {
271 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
272 return -EINVAL;
273 }
274
275 ret = abx500_mask_and_set_register_interruptible(info->dev,
276 info->update_bank, info->update_reg,
277 info->update_mask, 0x0);
278 if (ret < 0) {
279 dev_err(rdev_get_dev(rdev),
280 "couldn't set disable bits for regulator\n");
281 return ret;
282 }
283
284 dev_vdbg(rdev_get_dev(rdev),
285 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
286 info->desc.name, info->update_bank, info->update_reg,
287 info->update_mask, 0x0);
288
289 return ret;
290}
291
292static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
293{
294 int ret;
295 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
296 u8 regval;
297
298 if (info == NULL) {
299 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
300 return -EINVAL;
301 }
302
303 ret = abx500_get_register_interruptible(info->dev,
304 info->update_bank, info->update_reg, &regval);
305 if (ret < 0) {
306 dev_err(rdev_get_dev(rdev),
307 "couldn't read 0x%x register\n", info->update_reg);
308 return ret;
309 }
310
311 dev_vdbg(rdev_get_dev(rdev),
312 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
313 " 0x%x\n",
314 info->desc.name, info->update_bank, info->update_reg,
315 info->update_mask, regval);
316
317 if (regval & info->update_mask)
318 return 1;
319 else
320 return 0;
321}
322
323static unsigned int ab8500_regulator_get_optimum_mode(
324 struct regulator_dev *rdev, int input_uV,
325 int output_uV, int load_uA)
326{
327 unsigned int mode;
328
329 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
330
331 if (info == NULL) {
332 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
333 return -EINVAL;
334 }
335
336 if (load_uA <= info->load_lp_uA)
337 mode = REGULATOR_MODE_IDLE;
338 else
339 mode = REGULATOR_MODE_NORMAL;
340
341 return mode;
342}
343
344static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
345 unsigned int mode)
346{
347 int ret = 0;
348 u8 bank, reg, mask, val;
349 bool lp_mode_req = false;
350 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
351
352 if (info == NULL) {
353 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
354 return -EINVAL;
355 }
356
357 if (info->mode_mask) {
358 bank = info->mode_bank;
359 reg = info->mode_reg;
360 mask = info->mode_mask;
361 } else {
362 bank = info->update_bank;
363 reg = info->update_reg;
364 mask = info->update_mask;
365 }
366
367 if (info->shared_mode)
368 mutex_lock(&shared_mode_mutex);
369
370 switch (mode) {
371 case REGULATOR_MODE_NORMAL:
372 if (info->shared_mode)
373 lp_mode_req = false;
374
375 if (info->mode_mask)
376 val = info->mode_val_normal;
377 else
378 val = info->update_val_normal;
379 break;
380 case REGULATOR_MODE_IDLE:
381 if (info->shared_mode) {
382 struct ab8500_regulator_info *shared_regulator;
383
384 shared_regulator = info->shared_mode->shared_regulator;
385 if (!shared_regulator->shared_mode->lp_mode_req) {
386 /* Other regulator prevent LP mode */
387 info->shared_mode->lp_mode_req = true;
388 goto out_unlock;
389 }
390
391 lp_mode_req = true;
392 }
393
394 if (info->mode_mask)
395 val = info->mode_val_idle;
396 else
397 val = info->update_val_idle;
398 break;
399 default:
400 ret = -EINVAL;
401 goto out_unlock;
402 }
403
404 if (info->mode_mask || ab8500_regulator_is_enabled(rdev)) {
405 ret = abx500_mask_and_set_register_interruptible(info->dev,
406 bank, reg, mask, val);
407 if (ret < 0) {
408 dev_err(rdev_get_dev(rdev),
409 "couldn't set regulator mode\n");
410 goto out_unlock;
411 }
412
413 dev_vdbg(rdev_get_dev(rdev),
414 "%s-set_mode (bank, reg, mask, value): "
415 "0x%x, 0x%x, 0x%x, 0x%x\n",
416 info->desc.name, bank, reg,
417 mask, val);
418 }
419
420 if (!info->mode_mask)
421 info->update_val = val;
422
423 if (info->shared_mode)
424 info->shared_mode->lp_mode_req = lp_mode_req;
425
426out_unlock:
427 if (info->shared_mode)
428 mutex_unlock(&shared_mode_mutex);
429
430 return ret;
431}
432
433static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
434{
435 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
436 int ret;
437 u8 val;
438 u8 val_normal;
439 u8 val_idle;
440
441 if (info == NULL) {
442 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
443 return -EINVAL;
444 }
445
446 /* Need special handling for shared mode */
447 if (info->shared_mode) {
448 if (info->shared_mode->lp_mode_req)
449 return REGULATOR_MODE_IDLE;
450 else
451 return REGULATOR_MODE_NORMAL;
452 }
453
454 if (info->mode_mask) {
455 /* Dedicated register for handling mode */
456 ret = abx500_get_register_interruptible(info->dev,
457 info->mode_bank, info->mode_reg, &val);
458 val = val & info->mode_mask;
459
460 val_normal = info->mode_val_normal;
461 val_idle = info->mode_val_idle;
462 } else {
463 /* Mode register same as enable register */
464 val = info->update_val;
465 val_normal = info->update_val_normal;
466 val_idle = info->update_val_idle;
467 }
468
469 if (val == val_normal)
470 ret = REGULATOR_MODE_NORMAL;
471 else if (val == val_idle)
472 ret = REGULATOR_MODE_IDLE;
473 else
474 ret = -EINVAL;
475
476 return ret;
477}
478
479static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
480{
481 int ret, voltage_shift;
482 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
483 u8 regval;
484
485 if (info == NULL) {
486 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
487 return -EINVAL;
488 }
489
490 voltage_shift = ffs(info->voltage_mask) - 1;
491
492 ret = abx500_get_register_interruptible(info->dev,
493 info->voltage_bank, info->voltage_reg, &regval);
494 if (ret < 0) {
495 dev_err(rdev_get_dev(rdev),
496 "couldn't read voltage reg for regulator\n");
497 return ret;
498 }
499
500 dev_vdbg(rdev_get_dev(rdev),
501 "%s-get_voltage (bank, reg, mask, shift, value): "
502 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
503 info->desc.name, info->voltage_bank,
504 info->voltage_reg, info->voltage_mask,
505 voltage_shift, regval);
506
507 return (regval & info->voltage_mask) >> voltage_shift;
508}
509
510static int ab8540_aux3_regulator_get_voltage_sel(struct regulator_dev *rdev)
511{
512 int ret, voltage_shift;
513 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
514 u8 regval, regval_expand;
515
516 if (info == NULL) {
517 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
518 return -EINVAL;
519 }
520
521 ret = abx500_get_register_interruptible(info->dev,
522 info->expand_register.voltage_bank,
523 info->expand_register.voltage_reg, &regval_expand);
524 if (ret < 0) {
525 dev_err(rdev_get_dev(rdev),
526 "couldn't read voltage expand reg for regulator\n");
527 return ret;
528 }
529
530 dev_vdbg(rdev_get_dev(rdev),
531 "%s-get_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
532 info->desc.name, info->expand_register.voltage_bank,
533 info->expand_register.voltage_reg,
534 info->expand_register.voltage_mask, regval_expand);
535
536 if (regval_expand & info->expand_register.voltage_mask)
537 return info->expand_register.voltage_limit;
538
539 ret = abx500_get_register_interruptible(info->dev,
540 info->voltage_bank, info->voltage_reg, &regval);
541 if (ret < 0) {
542 dev_err(rdev_get_dev(rdev),
543 "couldn't read voltage reg for regulator\n");
544 return ret;
545 }
546
547 dev_vdbg(rdev_get_dev(rdev),
548 "%s-get_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
549 info->desc.name, info->voltage_bank, info->voltage_reg,
550 info->voltage_mask, regval);
551
552 voltage_shift = ffs(info->voltage_mask) - 1;
553
554 return (regval & info->voltage_mask) >> voltage_shift;
555}
556
557static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
558 unsigned selector)
559{
560 int ret, voltage_shift;
561 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
562 u8 regval;
563
564 if (info == NULL) {
565 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
566 return -EINVAL;
567 }
568
569 voltage_shift = ffs(info->voltage_mask) - 1;
570
571 /* set the registers for the request */
572 regval = (u8)selector << voltage_shift;
573 ret = abx500_mask_and_set_register_interruptible(info->dev,
574 info->voltage_bank, info->voltage_reg,
575 info->voltage_mask, regval);
576 if (ret < 0)
577 dev_err(rdev_get_dev(rdev),
578 "couldn't set voltage reg for regulator\n");
579
580 dev_vdbg(rdev_get_dev(rdev),
581 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
582 " 0x%x\n",
583 info->desc.name, info->voltage_bank, info->voltage_reg,
584 info->voltage_mask, regval);
585
586 return ret;
587}
588
589static int ab8540_aux3_regulator_set_voltage_sel(struct regulator_dev *rdev,
590 unsigned selector)
591{
592 int ret;
593 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
594 u8 regval, regval_expand;
595
596 if (info == NULL) {
597 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
598 return -EINVAL;
599 }
600
601 if (selector < info->expand_register.voltage_limit) {
602 int voltage_shift = ffs(info->voltage_mask) - 1;
603
604 regval = (u8)selector << voltage_shift;
605 ret = abx500_mask_and_set_register_interruptible(info->dev,
606 info->voltage_bank, info->voltage_reg,
607 info->voltage_mask, regval);
608 if (ret < 0) {
609 dev_err(rdev_get_dev(rdev),
610 "couldn't set voltage reg for regulator\n");
611 return ret;
612 }
613
614 dev_vdbg(rdev_get_dev(rdev),
615 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
616 info->desc.name, info->voltage_bank, info->voltage_reg,
617 info->voltage_mask, regval);
618
619 regval_expand = 0;
620 } else {
621 regval_expand = info->expand_register.voltage_mask;
622 }
623
624 ret = abx500_mask_and_set_register_interruptible(info->dev,
625 info->expand_register.voltage_bank,
626 info->expand_register.voltage_reg,
627 info->expand_register.voltage_mask,
628 regval_expand);
629 if (ret < 0) {
630 dev_err(rdev_get_dev(rdev),
631 "couldn't set expand voltage reg for regulator\n");
632 return ret;
633 }
634
635 dev_vdbg(rdev_get_dev(rdev),
636 "%s-set_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
637 info->desc.name, info->expand_register.voltage_bank,
638 info->expand_register.voltage_reg,
639 info->expand_register.voltage_mask, regval_expand);
640
641 return 0;
642}
643
644static struct regulator_ops ab8500_regulator_volt_mode_ops = {
645 .enable = ab8500_regulator_enable,
646 .disable = ab8500_regulator_disable,
647 .is_enabled = ab8500_regulator_is_enabled,
648 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
649 .set_mode = ab8500_regulator_set_mode,
650 .get_mode = ab8500_regulator_get_mode,
651 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
652 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
653 .list_voltage = regulator_list_voltage_table,
654};
655
656static struct regulator_ops ab8540_aux3_regulator_volt_mode_ops = {
657 .enable = ab8500_regulator_enable,
658 .disable = ab8500_regulator_disable,
659 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
660 .set_mode = ab8500_regulator_set_mode,
661 .get_mode = ab8500_regulator_get_mode,
662 .is_enabled = ab8500_regulator_is_enabled,
663 .get_voltage_sel = ab8540_aux3_regulator_get_voltage_sel,
664 .set_voltage_sel = ab8540_aux3_regulator_set_voltage_sel,
665 .list_voltage = regulator_list_voltage_table,
666};
667
668static struct regulator_ops ab8500_regulator_volt_ops = {
669 .enable = ab8500_regulator_enable,
670 .disable = ab8500_regulator_disable,
671 .is_enabled = ab8500_regulator_is_enabled,
672 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
673 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
674 .list_voltage = regulator_list_voltage_table,
675};
676
677static struct regulator_ops ab8500_regulator_mode_ops = {
678 .enable = ab8500_regulator_enable,
679 .disable = ab8500_regulator_disable,
680 .is_enabled = ab8500_regulator_is_enabled,
681 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
682 .set_mode = ab8500_regulator_set_mode,
683 .get_mode = ab8500_regulator_get_mode,
684 .list_voltage = regulator_list_voltage_table,
685};
686
687static struct regulator_ops ab8500_regulator_ops = {
688 .enable = ab8500_regulator_enable,
689 .disable = ab8500_regulator_disable,
690 .is_enabled = ab8500_regulator_is_enabled,
691 .list_voltage = regulator_list_voltage_table,
692};
693
694static struct regulator_ops ab8500_regulator_anamic_mode_ops = {
695 .enable = ab8500_regulator_enable,
696 .disable = ab8500_regulator_disable,
697 .is_enabled = ab8500_regulator_is_enabled,
698 .set_mode = ab8500_regulator_set_mode,
699 .get_mode = ab8500_regulator_get_mode,
700 .list_voltage = regulator_list_voltage_table,
701};
702
703/* AB8500 regulator information */
704static struct ab8500_regulator_info
705 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
706 /*
707 * Variable Voltage Regulators
708 * name, min mV, max mV,
709 * update bank, reg, mask, enable val
710 * volt bank, reg, mask
711 */
712 [AB8500_LDO_AUX1] = {
713 .desc = {
714 .name = "LDO-AUX1",
715 .ops = &ab8500_regulator_volt_mode_ops,
716 .type = REGULATOR_VOLTAGE,
717 .id = AB8500_LDO_AUX1,
718 .owner = THIS_MODULE,
719 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
720 .volt_table = ldo_vauxn_voltages,
721 .enable_time = 200,
722 .supply_name = "vin",
723 },
724 .load_lp_uA = 5000,
725 .update_bank = 0x04,
726 .update_reg = 0x09,
727 .update_mask = 0x03,
728 .update_val = 0x01,
729 .update_val_idle = 0x03,
730 .update_val_normal = 0x01,
731 .voltage_bank = 0x04,
732 .voltage_reg = 0x1f,
733 .voltage_mask = 0x0f,
734 },
735 [AB8500_LDO_AUX2] = {
736 .desc = {
737 .name = "LDO-AUX2",
738 .ops = &ab8500_regulator_volt_mode_ops,
739 .type = REGULATOR_VOLTAGE,
740 .id = AB8500_LDO_AUX2,
741 .owner = THIS_MODULE,
742 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
743 .volt_table = ldo_vauxn_voltages,
744 .enable_time = 200,
745 .supply_name = "vin",
746 },
747 .load_lp_uA = 5000,
748 .update_bank = 0x04,
749 .update_reg = 0x09,
750 .update_mask = 0x0c,
751 .update_val = 0x04,
752 .update_val_idle = 0x0c,
753 .update_val_normal = 0x04,
754 .voltage_bank = 0x04,
755 .voltage_reg = 0x20,
756 .voltage_mask = 0x0f,
757 },
758 [AB8500_LDO_AUX3] = {
759 .desc = {
760 .name = "LDO-AUX3",
761 .ops = &ab8500_regulator_volt_mode_ops,
762 .type = REGULATOR_VOLTAGE,
763 .id = AB8500_LDO_AUX3,
764 .owner = THIS_MODULE,
765 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
766 .volt_table = ldo_vaux3_voltages,
767 .enable_time = 450,
768 .supply_name = "vin",
769 },
770 .load_lp_uA = 5000,
771 .update_bank = 0x04,
772 .update_reg = 0x0a,
773 .update_mask = 0x03,
774 .update_val = 0x01,
775 .update_val_idle = 0x03,
776 .update_val_normal = 0x01,
777 .voltage_bank = 0x04,
778 .voltage_reg = 0x21,
779 .voltage_mask = 0x07,
780 },
781 [AB8500_LDO_INTCORE] = {
782 .desc = {
783 .name = "LDO-INTCORE",
784 .ops = &ab8500_regulator_volt_mode_ops,
785 .type = REGULATOR_VOLTAGE,
786 .id = AB8500_LDO_INTCORE,
787 .owner = THIS_MODULE,
788 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
789 .volt_table = ldo_vintcore_voltages,
790 .enable_time = 750,
791 },
792 .load_lp_uA = 5000,
793 .update_bank = 0x03,
794 .update_reg = 0x80,
795 .update_mask = 0x44,
796 .update_val = 0x44,
797 .update_val_idle = 0x44,
798 .update_val_normal = 0x04,
799 .voltage_bank = 0x03,
800 .voltage_reg = 0x80,
801 .voltage_mask = 0x38,
802 },
803
804 /*
805 * Fixed Voltage Regulators
806 * name, fixed mV,
807 * update bank, reg, mask, enable val
808 */
809 [AB8500_LDO_TVOUT] = {
810 .desc = {
811 .name = "LDO-TVOUT",
812 .ops = &ab8500_regulator_mode_ops,
813 .type = REGULATOR_VOLTAGE,
814 .id = AB8500_LDO_TVOUT,
815 .owner = THIS_MODULE,
816 .n_voltages = 1,
817 .volt_table = fixed_2000000_voltage,
818 .enable_time = 500,
819 },
820 .load_lp_uA = 1000,
821 .update_bank = 0x03,
822 .update_reg = 0x80,
823 .update_mask = 0x82,
824 .update_val = 0x02,
825 .update_val_idle = 0x82,
826 .update_val_normal = 0x02,
827 },
828 [AB8500_LDO_AUDIO] = {
829 .desc = {
830 .name = "LDO-AUDIO",
831 .ops = &ab8500_regulator_ops,
832 .type = REGULATOR_VOLTAGE,
833 .id = AB8500_LDO_AUDIO,
834 .owner = THIS_MODULE,
835 .n_voltages = 1,
836 .enable_time = 140,
837 .volt_table = fixed_2000000_voltage,
838 },
839 .update_bank = 0x03,
840 .update_reg = 0x83,
841 .update_mask = 0x02,
842 .update_val = 0x02,
843 },
844 [AB8500_LDO_ANAMIC1] = {
845 .desc = {
846 .name = "LDO-ANAMIC1",
847 .ops = &ab8500_regulator_ops,
848 .type = REGULATOR_VOLTAGE,
849 .id = AB8500_LDO_ANAMIC1,
850 .owner = THIS_MODULE,
851 .n_voltages = 1,
852 .enable_time = 500,
853 .volt_table = fixed_2050000_voltage,
854 },
855 .update_bank = 0x03,
856 .update_reg = 0x83,
857 .update_mask = 0x08,
858 .update_val = 0x08,
859 },
860 [AB8500_LDO_ANAMIC2] = {
861 .desc = {
862 .name = "LDO-ANAMIC2",
863 .ops = &ab8500_regulator_ops,
864 .type = REGULATOR_VOLTAGE,
865 .id = AB8500_LDO_ANAMIC2,
866 .owner = THIS_MODULE,
867 .n_voltages = 1,
868 .enable_time = 500,
869 .volt_table = fixed_2050000_voltage,
870 },
871 .update_bank = 0x03,
872 .update_reg = 0x83,
873 .update_mask = 0x10,
874 .update_val = 0x10,
875 },
876 [AB8500_LDO_DMIC] = {
877 .desc = {
878 .name = "LDO-DMIC",
879 .ops = &ab8500_regulator_ops,
880 .type = REGULATOR_VOLTAGE,
881 .id = AB8500_LDO_DMIC,
882 .owner = THIS_MODULE,
883 .n_voltages = 1,
884 .enable_time = 420,
885 .volt_table = fixed_1800000_voltage,
886 },
887 .update_bank = 0x03,
888 .update_reg = 0x83,
889 .update_mask = 0x04,
890 .update_val = 0x04,
891 },
892
893 /*
894 * Regulators with fixed voltage and normal/idle modes
895 */
896 [AB8500_LDO_ANA] = {
897 .desc = {
898 .name = "LDO-ANA",
899 .ops = &ab8500_regulator_mode_ops,
900 .type = REGULATOR_VOLTAGE,
901 .id = AB8500_LDO_ANA,
902 .owner = THIS_MODULE,
903 .n_voltages = 1,
904 .enable_time = 140,
905 .volt_table = fixed_1200000_voltage,
906 },
907 .load_lp_uA = 1000,
908 .update_bank = 0x04,
909 .update_reg = 0x06,
910 .update_mask = 0x0c,
911 .update_val = 0x04,
912 .update_val_idle = 0x0c,
913 .update_val_normal = 0x04,
914 },
915};
916
917/* AB8505 regulator information */
918static struct ab8500_regulator_info
919 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
920 /*
921 * Variable Voltage Regulators
922 * name, min mV, max mV,
923 * update bank, reg, mask, enable val
924 * volt bank, reg, mask
925 */
926 [AB8505_LDO_AUX1] = {
927 .desc = {
928 .name = "LDO-AUX1",
929 .ops = &ab8500_regulator_volt_mode_ops,
930 .type = REGULATOR_VOLTAGE,
931 .id = AB8505_LDO_AUX1,
932 .owner = THIS_MODULE,
933 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
934 .volt_table = ldo_vauxn_voltages,
935 },
936 .load_lp_uA = 5000,
937 .update_bank = 0x04,
938 .update_reg = 0x09,
939 .update_mask = 0x03,
940 .update_val = 0x01,
941 .update_val_idle = 0x03,
942 .update_val_normal = 0x01,
943 .voltage_bank = 0x04,
944 .voltage_reg = 0x1f,
945 .voltage_mask = 0x0f,
946 },
947 [AB8505_LDO_AUX2] = {
948 .desc = {
949 .name = "LDO-AUX2",
950 .ops = &ab8500_regulator_volt_mode_ops,
951 .type = REGULATOR_VOLTAGE,
952 .id = AB8505_LDO_AUX2,
953 .owner = THIS_MODULE,
954 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
955 .volt_table = ldo_vauxn_voltages,
956 },
957 .load_lp_uA = 5000,
958 .update_bank = 0x04,
959 .update_reg = 0x09,
960 .update_mask = 0x0c,
961 .update_val = 0x04,
962 .update_val_idle = 0x0c,
963 .update_val_normal = 0x04,
964 .voltage_bank = 0x04,
965 .voltage_reg = 0x20,
966 .voltage_mask = 0x0f,
967 },
968 [AB8505_LDO_AUX3] = {
969 .desc = {
970 .name = "LDO-AUX3",
971 .ops = &ab8500_regulator_volt_mode_ops,
972 .type = REGULATOR_VOLTAGE,
973 .id = AB8505_LDO_AUX3,
974 .owner = THIS_MODULE,
975 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
976 .volt_table = ldo_vaux3_voltages,
977 },
978 .load_lp_uA = 5000,
979 .update_bank = 0x04,
980 .update_reg = 0x0a,
981 .update_mask = 0x03,
982 .update_val = 0x01,
983 .update_val_idle = 0x03,
984 .update_val_normal = 0x01,
985 .voltage_bank = 0x04,
986 .voltage_reg = 0x21,
987 .voltage_mask = 0x07,
988 },
989 [AB8505_LDO_AUX4] = {
990 .desc = {
991 .name = "LDO-AUX4",
992 .ops = &ab8500_regulator_volt_mode_ops,
993 .type = REGULATOR_VOLTAGE,
994 .id = AB8505_LDO_AUX4,
995 .owner = THIS_MODULE,
996 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
997 .volt_table = ldo_vauxn_voltages,
998 },
999 .load_lp_uA = 5000,
1000 /* values for Vaux4Regu register */
1001 .update_bank = 0x04,
1002 .update_reg = 0x2e,
1003 .update_mask = 0x03,
1004 .update_val = 0x01,
1005 .update_val_idle = 0x03,
1006 .update_val_normal = 0x01,
1007 /* values for Vaux4SEL register */
1008 .voltage_bank = 0x04,
1009 .voltage_reg = 0x2f,
1010 .voltage_mask = 0x0f,
1011 },
1012 [AB8505_LDO_AUX5] = {
1013 .desc = {
1014 .name = "LDO-AUX5",
1015 .ops = &ab8500_regulator_volt_mode_ops,
1016 .type = REGULATOR_VOLTAGE,
1017 .id = AB8505_LDO_AUX5,
1018 .owner = THIS_MODULE,
1019 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
1020 .volt_table = ldo_vaux56_voltages,
1021 },
1022 .load_lp_uA = 2000,
1023 /* values for CtrlVaux5 register */
1024 .update_bank = 0x01,
1025 .update_reg = 0x55,
1026 .update_mask = 0x18,
1027 .update_val = 0x10,
1028 .update_val_idle = 0x18,
1029 .update_val_normal = 0x10,
1030 .voltage_bank = 0x01,
1031 .voltage_reg = 0x55,
1032 .voltage_mask = 0x07,
1033 },
1034 [AB8505_LDO_AUX6] = {
1035 .desc = {
1036 .name = "LDO-AUX6",
1037 .ops = &ab8500_regulator_volt_mode_ops,
1038 .type = REGULATOR_VOLTAGE,
1039 .id = AB8505_LDO_AUX6,
1040 .owner = THIS_MODULE,
1041 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
1042 .volt_table = ldo_vaux56_voltages,
1043 },
1044 .load_lp_uA = 2000,
1045 /* values for CtrlVaux6 register */
1046 .update_bank = 0x01,
1047 .update_reg = 0x56,
1048 .update_mask = 0x18,
1049 .update_val = 0x10,
1050 .update_val_idle = 0x18,
1051 .update_val_normal = 0x10,
1052 .voltage_bank = 0x01,
1053 .voltage_reg = 0x56,
1054 .voltage_mask = 0x07,
1055 },
1056 [AB8505_LDO_INTCORE] = {
1057 .desc = {
1058 .name = "LDO-INTCORE",
1059 .ops = &ab8500_regulator_volt_mode_ops,
1060 .type = REGULATOR_VOLTAGE,
1061 .id = AB8505_LDO_INTCORE,
1062 .owner = THIS_MODULE,
1063 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1064 .volt_table = ldo_vintcore_voltages,
1065 },
1066 .load_lp_uA = 5000,
1067 .update_bank = 0x03,
1068 .update_reg = 0x80,
1069 .update_mask = 0x44,
1070 .update_val = 0x04,
1071 .update_val_idle = 0x44,
1072 .update_val_normal = 0x04,
1073 .voltage_bank = 0x03,
1074 .voltage_reg = 0x80,
1075 .voltage_mask = 0x38,
1076 },
1077
1078 /*
1079 * Fixed Voltage Regulators
1080 * name, fixed mV,
1081 * update bank, reg, mask, enable val
1082 */
1083 [AB8505_LDO_ADC] = {
1084 .desc = {
1085 .name = "LDO-ADC",
1086 .ops = &ab8500_regulator_mode_ops,
1087 .type = REGULATOR_VOLTAGE,
1088 .id = AB8505_LDO_ADC,
1089 .owner = THIS_MODULE,
1090 .n_voltages = 1,
1091 .volt_table = fixed_2000000_voltage,
1092 .enable_time = 10000,
1093 },
1094 .load_lp_uA = 1000,
1095 .update_bank = 0x03,
1096 .update_reg = 0x80,
1097 .update_mask = 0x82,
1098 .update_val = 0x02,
1099 .update_val_idle = 0x82,
1100 .update_val_normal = 0x02,
1101 },
1102 [AB8505_LDO_AUDIO] = {
1103 .desc = {
1104 .name = "LDO-AUDIO",
1105 .ops = &ab8500_regulator_volt_ops,
1106 .type = REGULATOR_VOLTAGE,
1107 .id = AB8505_LDO_AUDIO,
1108 .owner = THIS_MODULE,
1109 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
1110 .volt_table = ldo_vaudio_voltages,
1111 },
1112 .update_bank = 0x03,
1113 .update_reg = 0x83,
1114 .update_mask = 0x02,
1115 .update_val = 0x02,
1116 .voltage_bank = 0x01,
1117 .voltage_reg = 0x57,
1118 .voltage_mask = 0x70,
1119 },
1120 [AB8505_LDO_ANAMIC1] = {
1121 .desc = {
1122 .name = "LDO-ANAMIC1",
1123 .ops = &ab8500_regulator_anamic_mode_ops,
1124 .type = REGULATOR_VOLTAGE,
1125 .id = AB8505_LDO_ANAMIC1,
1126 .owner = THIS_MODULE,
1127 .n_voltages = 1,
1128 .volt_table = fixed_2050000_voltage,
1129 },
1130 .shared_mode = &ldo_anamic1_shared,
1131 .update_bank = 0x03,
1132 .update_reg = 0x83,
1133 .update_mask = 0x08,
1134 .update_val = 0x08,
1135 .mode_bank = 0x01,
1136 .mode_reg = 0x54,
1137 .mode_mask = 0x04,
1138 .mode_val_idle = 0x04,
1139 .mode_val_normal = 0x00,
1140 },
1141 [AB8505_LDO_ANAMIC2] = {
1142 .desc = {
1143 .name = "LDO-ANAMIC2",
1144 .ops = &ab8500_regulator_anamic_mode_ops,
1145 .type = REGULATOR_VOLTAGE,
1146 .id = AB8505_LDO_ANAMIC2,
1147 .owner = THIS_MODULE,
1148 .n_voltages = 1,
1149 .volt_table = fixed_2050000_voltage,
1150 },
1151 .shared_mode = &ldo_anamic2_shared,
1152 .update_bank = 0x03,
1153 .update_reg = 0x83,
1154 .update_mask = 0x10,
1155 .update_val = 0x10,
1156 .mode_bank = 0x01,
1157 .mode_reg = 0x54,
1158 .mode_mask = 0x04,
1159 .mode_val_idle = 0x04,
1160 .mode_val_normal = 0x00,
1161 },
1162 [AB8505_LDO_AUX8] = {
1163 .desc = {
1164 .name = "LDO-AUX8",
1165 .ops = &ab8500_regulator_ops,
1166 .type = REGULATOR_VOLTAGE,
1167 .id = AB8505_LDO_AUX8,
1168 .owner = THIS_MODULE,
1169 .n_voltages = 1,
1170 .volt_table = fixed_1800000_voltage,
1171 },
1172 .update_bank = 0x03,
1173 .update_reg = 0x83,
1174 .update_mask = 0x04,
1175 .update_val = 0x04,
1176 },
1177 /*
1178 * Regulators with fixed voltage and normal/idle modes
1179 */
1180 [AB8505_LDO_ANA] = {
1181 .desc = {
1182 .name = "LDO-ANA",
1183 .ops = &ab8500_regulator_volt_mode_ops,
1184 .type = REGULATOR_VOLTAGE,
1185 .id = AB8505_LDO_ANA,
1186 .owner = THIS_MODULE,
1187 .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
1188 .volt_table = ldo_vana_voltages,
1189 },
1190 .load_lp_uA = 1000,
1191 .update_bank = 0x04,
1192 .update_reg = 0x06,
1193 .update_mask = 0x0c,
1194 .update_val = 0x04,
1195 .update_val_idle = 0x0c,
1196 .update_val_normal = 0x04,
1197 .voltage_bank = 0x04,
1198 .voltage_reg = 0x29,
1199 .voltage_mask = 0x7,
1200 },
1201};
1202
1203/* AB9540 regulator information */
1204static struct ab8500_regulator_info
1205 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
1206 /*
1207 * Variable Voltage Regulators
1208 * name, min mV, max mV,
1209 * update bank, reg, mask, enable val
1210 * volt bank, reg, mask
1211 */
1212 [AB9540_LDO_AUX1] = {
1213 .desc = {
1214 .name = "LDO-AUX1",
1215 .ops = &ab8500_regulator_volt_mode_ops,
1216 .type = REGULATOR_VOLTAGE,
1217 .id = AB9540_LDO_AUX1,
1218 .owner = THIS_MODULE,
1219 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1220 .volt_table = ldo_vauxn_voltages,
1221 },
1222 .load_lp_uA = 5000,
1223 .update_bank = 0x04,
1224 .update_reg = 0x09,
1225 .update_mask = 0x03,
1226 .update_val = 0x01,
1227 .update_val_idle = 0x03,
1228 .update_val_normal = 0x01,
1229 .voltage_bank = 0x04,
1230 .voltage_reg = 0x1f,
1231 .voltage_mask = 0x0f,
1232 },
1233 [AB9540_LDO_AUX2] = {
1234 .desc = {
1235 .name = "LDO-AUX2",
1236 .ops = &ab8500_regulator_volt_mode_ops,
1237 .type = REGULATOR_VOLTAGE,
1238 .id = AB9540_LDO_AUX2,
1239 .owner = THIS_MODULE,
1240 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1241 .volt_table = ldo_vauxn_voltages,
1242 },
1243 .load_lp_uA = 5000,
1244 .update_bank = 0x04,
1245 .update_reg = 0x09,
1246 .update_mask = 0x0c,
1247 .update_val = 0x04,
1248 .update_val_idle = 0x0c,
1249 .update_val_normal = 0x04,
1250 .voltage_bank = 0x04,
1251 .voltage_reg = 0x20,
1252 .voltage_mask = 0x0f,
1253 },
1254 [AB9540_LDO_AUX3] = {
1255 .desc = {
1256 .name = "LDO-AUX3",
1257 .ops = &ab8500_regulator_volt_mode_ops,
1258 .type = REGULATOR_VOLTAGE,
1259 .id = AB9540_LDO_AUX3,
1260 .owner = THIS_MODULE,
1261 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
1262 .volt_table = ldo_vaux3_voltages,
1263 },
1264 .load_lp_uA = 5000,
1265 .update_bank = 0x04,
1266 .update_reg = 0x0a,
1267 .update_mask = 0x03,
1268 .update_val = 0x01,
1269 .update_val_idle = 0x03,
1270 .update_val_normal = 0x01,
1271 .voltage_bank = 0x04,
1272 .voltage_reg = 0x21,
1273 .voltage_mask = 0x07,
1274 },
1275 [AB9540_LDO_AUX4] = {
1276 .desc = {
1277 .name = "LDO-AUX4",
1278 .ops = &ab8500_regulator_volt_mode_ops,
1279 .type = REGULATOR_VOLTAGE,
1280 .id = AB9540_LDO_AUX4,
1281 .owner = THIS_MODULE,
1282 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1283 .volt_table = ldo_vauxn_voltages,
1284 },
1285 .load_lp_uA = 5000,
1286 /* values for Vaux4Regu register */
1287 .update_bank = 0x04,
1288 .update_reg = 0x2e,
1289 .update_mask = 0x03,
1290 .update_val = 0x01,
1291 .update_val_idle = 0x03,
1292 .update_val_normal = 0x01,
1293 /* values for Vaux4SEL register */
1294 .voltage_bank = 0x04,
1295 .voltage_reg = 0x2f,
1296 .voltage_mask = 0x0f,
1297 },
1298 [AB9540_LDO_INTCORE] = {
1299 .desc = {
1300 .name = "LDO-INTCORE",
1301 .ops = &ab8500_regulator_volt_mode_ops,
1302 .type = REGULATOR_VOLTAGE,
1303 .id = AB9540_LDO_INTCORE,
1304 .owner = THIS_MODULE,
1305 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1306 .volt_table = ldo_vintcore_voltages,
1307 },
1308 .load_lp_uA = 5000,
1309 .update_bank = 0x03,
1310 .update_reg = 0x80,
1311 .update_mask = 0x44,
1312 .update_val = 0x44,
1313 .update_val_idle = 0x44,
1314 .update_val_normal = 0x04,
1315 .voltage_bank = 0x03,
1316 .voltage_reg = 0x80,
1317 .voltage_mask = 0x38,
1318 },
1319
1320 /*
1321 * Fixed Voltage Regulators
1322 * name, fixed mV,
1323 * update bank, reg, mask, enable val
1324 */
1325 [AB9540_LDO_TVOUT] = {
1326 .desc = {
1327 .name = "LDO-TVOUT",
1328 .ops = &ab8500_regulator_mode_ops,
1329 .type = REGULATOR_VOLTAGE,
1330 .id = AB9540_LDO_TVOUT,
1331 .owner = THIS_MODULE,
1332 .n_voltages = 1,
1333 .volt_table = fixed_2000000_voltage,
1334 .enable_time = 10000,
1335 },
1336 .load_lp_uA = 1000,
1337 .update_bank = 0x03,
1338 .update_reg = 0x80,
1339 .update_mask = 0x82,
1340 .update_val = 0x02,
1341 .update_val_idle = 0x82,
1342 .update_val_normal = 0x02,
1343 },
1344 [AB9540_LDO_USB] = {
1345 .desc = {
1346 .name = "LDO-USB",
1347 .ops = &ab8500_regulator_ops,
1348 .type = REGULATOR_VOLTAGE,
1349 .id = AB9540_LDO_USB,
1350 .owner = THIS_MODULE,
1351 .n_voltages = 1,
1352 .volt_table = fixed_3300000_voltage,
1353 },
1354 .update_bank = 0x03,
1355 .update_reg = 0x82,
1356 .update_mask = 0x03,
1357 .update_val = 0x01,
1358 .update_val_idle = 0x03,
1359 .update_val_normal = 0x01,
1360 },
1361 [AB9540_LDO_AUDIO] = {
1362 .desc = {
1363 .name = "LDO-AUDIO",
1364 .ops = &ab8500_regulator_ops,
1365 .type = REGULATOR_VOLTAGE,
1366 .id = AB9540_LDO_AUDIO,
1367 .owner = THIS_MODULE,
1368 .n_voltages = 1,
1369 .volt_table = fixed_2000000_voltage,
1370 },
1371 .update_bank = 0x03,
1372 .update_reg = 0x83,
1373 .update_mask = 0x02,
1374 .update_val = 0x02,
1375 },
1376 [AB9540_LDO_ANAMIC1] = {
1377 .desc = {
1378 .name = "LDO-ANAMIC1",
1379 .ops = &ab8500_regulator_ops,
1380 .type = REGULATOR_VOLTAGE,
1381 .id = AB9540_LDO_ANAMIC1,
1382 .owner = THIS_MODULE,
1383 .n_voltages = 1,
1384 .volt_table = fixed_2050000_voltage,
1385 },
1386 .update_bank = 0x03,
1387 .update_reg = 0x83,
1388 .update_mask = 0x08,
1389 .update_val = 0x08,
1390 },
1391 [AB9540_LDO_ANAMIC2] = {
1392 .desc = {
1393 .name = "LDO-ANAMIC2",
1394 .ops = &ab8500_regulator_ops,
1395 .type = REGULATOR_VOLTAGE,
1396 .id = AB9540_LDO_ANAMIC2,
1397 .owner = THIS_MODULE,
1398 .n_voltages = 1,
1399 .volt_table = fixed_2050000_voltage,
1400 },
1401 .update_bank = 0x03,
1402 .update_reg = 0x83,
1403 .update_mask = 0x10,
1404 .update_val = 0x10,
1405 },
1406 [AB9540_LDO_DMIC] = {
1407 .desc = {
1408 .name = "LDO-DMIC",
1409 .ops = &ab8500_regulator_ops,
1410 .type = REGULATOR_VOLTAGE,
1411 .id = AB9540_LDO_DMIC,
1412 .owner = THIS_MODULE,
1413 .n_voltages = 1,
1414 .volt_table = fixed_1800000_voltage,
1415 },
1416 .update_bank = 0x03,
1417 .update_reg = 0x83,
1418 .update_mask = 0x04,
1419 .update_val = 0x04,
1420 },
1421
1422 /*
1423 * Regulators with fixed voltage and normal/idle modes
1424 */
1425 [AB9540_LDO_ANA] = {
1426 .desc = {
1427 .name = "LDO-ANA",
1428 .ops = &ab8500_regulator_mode_ops,
1429 .type = REGULATOR_VOLTAGE,
1430 .id = AB9540_LDO_ANA,
1431 .owner = THIS_MODULE,
1432 .n_voltages = 1,
1433 .volt_table = fixed_1200000_voltage,
1434 },
1435 .load_lp_uA = 1000,
1436 .update_bank = 0x04,
1437 .update_reg = 0x06,
1438 .update_mask = 0x0c,
1439 .update_val = 0x08,
1440 .update_val_idle = 0x0c,
1441 .update_val_normal = 0x08,
1442 },
1443};
1444
1445/* AB8540 regulator information */
1446static struct ab8500_regulator_info
1447 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1448 /*
1449 * Variable Voltage Regulators
1450 * name, min mV, max mV,
1451 * update bank, reg, mask, enable val
1452 * volt bank, reg, mask
1453 */
1454 [AB8540_LDO_AUX1] = {
1455 .desc = {
1456 .name = "LDO-AUX1",
1457 .ops = &ab8500_regulator_volt_mode_ops,
1458 .type = REGULATOR_VOLTAGE,
1459 .id = AB8540_LDO_AUX1,
1460 .owner = THIS_MODULE,
1461 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1462 .volt_table = ldo_vauxn_voltages,
1463 },
1464 .load_lp_uA = 5000,
1465 .update_bank = 0x04,
1466 .update_reg = 0x09,
1467 .update_mask = 0x03,
1468 .update_val = 0x01,
1469 .update_val_idle = 0x03,
1470 .update_val_normal = 0x01,
1471 .voltage_bank = 0x04,
1472 .voltage_reg = 0x1f,
1473 .voltage_mask = 0x0f,
1474 },
1475 [AB8540_LDO_AUX2] = {
1476 .desc = {
1477 .name = "LDO-AUX2",
1478 .ops = &ab8500_regulator_volt_mode_ops,
1479 .type = REGULATOR_VOLTAGE,
1480 .id = AB8540_LDO_AUX2,
1481 .owner = THIS_MODULE,
1482 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1483 .volt_table = ldo_vauxn_voltages,
1484 },
1485 .load_lp_uA = 5000,
1486 .update_bank = 0x04,
1487 .update_reg = 0x09,
1488 .update_mask = 0x0c,
1489 .update_val = 0x04,
1490 .update_val_idle = 0x0c,
1491 .update_val_normal = 0x04,
1492 .voltage_bank = 0x04,
1493 .voltage_reg = 0x20,
1494 .voltage_mask = 0x0f,
1495 },
1496 [AB8540_LDO_AUX3] = {
1497 .desc = {
1498 .name = "LDO-AUX3",
1499 .ops = &ab8540_aux3_regulator_volt_mode_ops,
1500 .type = REGULATOR_VOLTAGE,
1501 .id = AB8540_LDO_AUX3,
1502 .owner = THIS_MODULE,
1503 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
1504 .volt_table = ldo_vaux3_ab8540_voltages,
1505 },
1506 .load_lp_uA = 5000,
1507 .update_bank = 0x04,
1508 .update_reg = 0x0a,
1509 .update_mask = 0x03,
1510 .update_val = 0x01,
1511 .update_val_idle = 0x03,
1512 .update_val_normal = 0x01,
1513 .voltage_bank = 0x04,
1514 .voltage_reg = 0x21,
1515 .voltage_mask = 0x07,
1516 .expand_register = {
1517 .voltage_limit = 8,
1518 .voltage_bank = 0x04,
1519 .voltage_reg = 0x01,
1520 .voltage_mask = 0x10,
1521 }
1522 },
1523 [AB8540_LDO_AUX4] = {
1524 .desc = {
1525 .name = "LDO-AUX4",
1526 .ops = &ab8500_regulator_volt_mode_ops,
1527 .type = REGULATOR_VOLTAGE,
1528 .id = AB8540_LDO_AUX4,
1529 .owner = THIS_MODULE,
1530 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1531 .volt_table = ldo_vauxn_voltages,
1532 },
1533 .load_lp_uA = 5000,
1534 /* values for Vaux4Regu register */
1535 .update_bank = 0x04,
1536 .update_reg = 0x2e,
1537 .update_mask = 0x03,
1538 .update_val = 0x01,
1539 .update_val_idle = 0x03,
1540 .update_val_normal = 0x01,
1541 /* values for Vaux4SEL register */
1542 .voltage_bank = 0x04,
1543 .voltage_reg = 0x2f,
1544 .voltage_mask = 0x0f,
1545 },
1546 [AB8540_LDO_AUX5] = {
1547 .desc = {
1548 .name = "LDO-AUX5",
1549 .ops = &ab8500_regulator_volt_mode_ops,
1550 .type = REGULATOR_VOLTAGE,
1551 .id = AB8540_LDO_AUX5,
1552 .owner = THIS_MODULE,
1553 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
1554 .volt_table = ldo_vaux56_ab8540_voltages,
1555 },
1556 .load_lp_uA = 20000,
1557 /* values for Vaux5Regu register */
1558 .update_bank = 0x04,
1559 .update_reg = 0x32,
1560 .update_mask = 0x03,
1561 .update_val = 0x01,
1562 .update_val_idle = 0x03,
1563 .update_val_normal = 0x01,
1564 /* values for Vaux5SEL register */
1565 .voltage_bank = 0x04,
1566 .voltage_reg = 0x33,
1567 .voltage_mask = 0x3f,
1568 },
1569 [AB8540_LDO_AUX6] = {
1570 .desc = {
1571 .name = "LDO-AUX6",
1572 .ops = &ab8500_regulator_volt_mode_ops,
1573 .type = REGULATOR_VOLTAGE,
1574 .id = AB8540_LDO_AUX6,
1575 .owner = THIS_MODULE,
1576 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
1577 .volt_table = ldo_vaux56_ab8540_voltages,
1578 },
1579 .load_lp_uA = 20000,
1580 /* values for Vaux6Regu register */
1581 .update_bank = 0x04,
1582 .update_reg = 0x35,
1583 .update_mask = 0x03,
1584 .update_val = 0x01,
1585 .update_val_idle = 0x03,
1586 .update_val_normal = 0x01,
1587 /* values for Vaux6SEL register */
1588 .voltage_bank = 0x04,
1589 .voltage_reg = 0x36,
1590 .voltage_mask = 0x3f,
1591 },
1592 [AB8540_LDO_INTCORE] = {
1593 .desc = {
1594 .name = "LDO-INTCORE",
1595 .ops = &ab8500_regulator_volt_mode_ops,
1596 .type = REGULATOR_VOLTAGE,
1597 .id = AB8540_LDO_INTCORE,
1598 .owner = THIS_MODULE,
1599 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1600 .volt_table = ldo_vintcore_voltages,
1601 },
1602 .load_lp_uA = 5000,
1603 .update_bank = 0x03,
1604 .update_reg = 0x80,
1605 .update_mask = 0x44,
1606 .update_val = 0x44,
1607 .update_val_idle = 0x44,
1608 .update_val_normal = 0x04,
1609 .voltage_bank = 0x03,
1610 .voltage_reg = 0x80,
1611 .voltage_mask = 0x38,
1612 },
1613
1614 /*
1615 * Fixed Voltage Regulators
1616 * name, fixed mV,
1617 * update bank, reg, mask, enable val
1618 */
1619 [AB8540_LDO_TVOUT] = {
1620 .desc = {
1621 .name = "LDO-TVOUT",
1622 .ops = &ab8500_regulator_mode_ops,
1623 .type = REGULATOR_VOLTAGE,
1624 .id = AB8540_LDO_TVOUT,
1625 .owner = THIS_MODULE,
1626 .n_voltages = 1,
1627 .volt_table = fixed_2000000_voltage,
1628 .enable_time = 10000,
1629 },
1630 .load_lp_uA = 1000,
1631 .update_bank = 0x03,
1632 .update_reg = 0x80,
1633 .update_mask = 0x82,
1634 .update_val = 0x02,
1635 .update_val_idle = 0x82,
1636 .update_val_normal = 0x02,
1637 },
1638 [AB8540_LDO_AUDIO] = {
1639 .desc = {
1640 .name = "LDO-AUDIO",
1641 .ops = &ab8500_regulator_ops,
1642 .type = REGULATOR_VOLTAGE,
1643 .id = AB8540_LDO_AUDIO,
1644 .owner = THIS_MODULE,
1645 .n_voltages = 1,
1646 .volt_table = fixed_2000000_voltage,
1647 },
1648 .update_bank = 0x03,
1649 .update_reg = 0x83,
1650 .update_mask = 0x02,
1651 .update_val = 0x02,
1652 },
1653 [AB8540_LDO_ANAMIC1] = {
1654 .desc = {
1655 .name = "LDO-ANAMIC1",
1656 .ops = &ab8500_regulator_anamic_mode_ops,
1657 .type = REGULATOR_VOLTAGE,
1658 .id = AB8540_LDO_ANAMIC1,
1659 .owner = THIS_MODULE,
1660 .n_voltages = 1,
1661 .volt_table = fixed_2050000_voltage,
1662 },
1663 .shared_mode = &ab8540_ldo_anamic1_shared,
1664 .update_bank = 0x03,
1665 .update_reg = 0x83,
1666 .update_mask = 0x08,
1667 .update_val = 0x08,
1668 .mode_bank = 0x03,
1669 .mode_reg = 0x83,
1670 .mode_mask = 0x20,
1671 .mode_val_idle = 0x20,
1672 .mode_val_normal = 0x00,
1673 },
1674 [AB8540_LDO_ANAMIC2] = {
1675 .desc = {
1676 .name = "LDO-ANAMIC2",
1677 .ops = &ab8500_regulator_anamic_mode_ops,
1678 .type = REGULATOR_VOLTAGE,
1679 .id = AB8540_LDO_ANAMIC2,
1680 .owner = THIS_MODULE,
1681 .n_voltages = 1,
1682 .volt_table = fixed_2050000_voltage,
1683 },
1684 .shared_mode = &ab8540_ldo_anamic2_shared,
1685 .update_bank = 0x03,
1686 .update_reg = 0x83,
1687 .update_mask = 0x10,
1688 .update_val = 0x10,
1689 .mode_bank = 0x03,
1690 .mode_reg = 0x83,
1691 .mode_mask = 0x20,
1692 .mode_val_idle = 0x20,
1693 .mode_val_normal = 0x00,
1694 },
1695 [AB8540_LDO_DMIC] = {
1696 .desc = {
1697 .name = "LDO-DMIC",
1698 .ops = &ab8500_regulator_volt_mode_ops,
1699 .type = REGULATOR_VOLTAGE,
1700 .id = AB8540_LDO_DMIC,
1701 .owner = THIS_MODULE,
1702 .n_voltages = ARRAY_SIZE(ldo_vdmic_voltages),
1703 .volt_table = ldo_vdmic_voltages,
1704 },
1705 .load_lp_uA = 1000,
1706 .update_bank = 0x03,
1707 .update_reg = 0x83,
1708 .update_mask = 0x04,
1709 .update_val = 0x04,
1710 .voltage_bank = 0x03,
1711 .voltage_reg = 0x83,
1712 .voltage_mask = 0xc0,
1713 },
1714
1715 /*
1716 * Regulators with fixed voltage and normal/idle modes
1717 */
1718 [AB8540_LDO_ANA] = {
1719 .desc = {
1720 .name = "LDO-ANA",
1721 .ops = &ab8500_regulator_mode_ops,
1722 .type = REGULATOR_VOLTAGE,
1723 .id = AB8540_LDO_ANA,
1724 .owner = THIS_MODULE,
1725 .n_voltages = 1,
1726 .volt_table = fixed_1200000_voltage,
1727 },
1728 .load_lp_uA = 1000,
1729 .update_bank = 0x04,
1730 .update_reg = 0x06,
1731 .update_mask = 0x0c,
1732 .update_val = 0x04,
1733 .update_val_idle = 0x0c,
1734 .update_val_normal = 0x04,
1735 },
1736 [AB8540_LDO_SDIO] = {
1737 .desc = {
1738 .name = "LDO-SDIO",
1739 .ops = &ab8500_regulator_volt_mode_ops,
1740 .type = REGULATOR_VOLTAGE,
1741 .id = AB8540_LDO_SDIO,
1742 .owner = THIS_MODULE,
1743 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1744 .volt_table = ldo_sdio_voltages,
1745 },
1746 .load_lp_uA = 5000,
1747 .update_bank = 0x03,
1748 .update_reg = 0x88,
1749 .update_mask = 0x30,
1750 .update_val = 0x10,
1751 .update_val_idle = 0x30,
1752 .update_val_normal = 0x10,
1753 .voltage_bank = 0x03,
1754 .voltage_reg = 0x88,
1755 .voltage_mask = 0x07,
1756 },
1757};
1758
1759static struct ab8500_shared_mode ldo_anamic1_shared = {
1760 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
1761};
1762
1763static struct ab8500_shared_mode ldo_anamic2_shared = {
1764 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
1765};
1766
1767static struct ab8500_shared_mode ab8540_ldo_anamic1_shared = {
1768 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC2],
1769};
1770
1771static struct ab8500_shared_mode ab8540_ldo_anamic2_shared = {
1772 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC1],
1773};
1774
1775struct ab8500_reg_init {
1776 u8 bank;
1777 u8 addr;
1778 u8 mask;
1779};
1780
1781#define REG_INIT(_id, _bank, _addr, _mask) \
1782 [_id] = { \
1783 .bank = _bank, \
1784 .addr = _addr, \
1785 .mask = _mask, \
1786 }
1787
1788/* AB8500 register init */
1789static struct ab8500_reg_init ab8500_reg_init[] = {
1790 /*
1791 * 0x30, VanaRequestCtrl
1792 * 0xc0, VextSupply1RequestCtrl
1793 */
1794 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
1795 /*
1796 * 0x03, VextSupply2RequestCtrl
1797 * 0x0c, VextSupply3RequestCtrl
1798 * 0x30, Vaux1RequestCtrl
1799 * 0xc0, Vaux2RequestCtrl
1800 */
1801 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1802 /*
1803 * 0x03, Vaux3RequestCtrl
1804 * 0x04, SwHPReq
1805 */
1806 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1807 /*
1808 * 0x08, VanaSysClkReq1HPValid
1809 * 0x20, Vaux1SysClkReq1HPValid
1810 * 0x40, Vaux2SysClkReq1HPValid
1811 * 0x80, Vaux3SysClkReq1HPValid
1812 */
1813 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
1814 /*
1815 * 0x10, VextSupply1SysClkReq1HPValid
1816 * 0x20, VextSupply2SysClkReq1HPValid
1817 * 0x40, VextSupply3SysClkReq1HPValid
1818 */
1819 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
1820 /*
1821 * 0x08, VanaHwHPReq1Valid
1822 * 0x20, Vaux1HwHPReq1Valid
1823 * 0x40, Vaux2HwHPReq1Valid
1824 * 0x80, Vaux3HwHPReq1Valid
1825 */
1826 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
1827 /*
1828 * 0x01, VextSupply1HwHPReq1Valid
1829 * 0x02, VextSupply2HwHPReq1Valid
1830 * 0x04, VextSupply3HwHPReq1Valid
1831 */
1832 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
1833 /*
1834 * 0x08, VanaHwHPReq2Valid
1835 * 0x20, Vaux1HwHPReq2Valid
1836 * 0x40, Vaux2HwHPReq2Valid
1837 * 0x80, Vaux3HwHPReq2Valid
1838 */
1839 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
1840 /*
1841 * 0x01, VextSupply1HwHPReq2Valid
1842 * 0x02, VextSupply2HwHPReq2Valid
1843 * 0x04, VextSupply3HwHPReq2Valid
1844 */
1845 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
1846 /*
1847 * 0x20, VanaSwHPReqValid
1848 * 0x80, Vaux1SwHPReqValid
1849 */
1850 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
1851 /*
1852 * 0x01, Vaux2SwHPReqValid
1853 * 0x02, Vaux3SwHPReqValid
1854 * 0x04, VextSupply1SwHPReqValid
1855 * 0x08, VextSupply2SwHPReqValid
1856 * 0x10, VextSupply3SwHPReqValid
1857 */
1858 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
1859 /*
1860 * 0x02, SysClkReq2Valid1
1861 * 0x04, SysClkReq3Valid1
1862 * 0x08, SysClkReq4Valid1
1863 * 0x10, SysClkReq5Valid1
1864 * 0x20, SysClkReq6Valid1
1865 * 0x40, SysClkReq7Valid1
1866 * 0x80, SysClkReq8Valid1
1867 */
1868 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1869 /*
1870 * 0x02, SysClkReq2Valid2
1871 * 0x04, SysClkReq3Valid2
1872 * 0x08, SysClkReq4Valid2
1873 * 0x10, SysClkReq5Valid2
1874 * 0x20, SysClkReq6Valid2
1875 * 0x40, SysClkReq7Valid2
1876 * 0x80, SysClkReq8Valid2
1877 */
1878 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1879 /*
1880 * 0x02, VTVoutEna
1881 * 0x04, Vintcore12Ena
1882 * 0x38, Vintcore12Sel
1883 * 0x40, Vintcore12LP
1884 * 0x80, VTVoutLP
1885 */
1886 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1887 /*
1888 * 0x02, VaudioEna
1889 * 0x04, VdmicEna
1890 * 0x08, Vamic1Ena
1891 * 0x10, Vamic2Ena
1892 */
1893 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1894 /*
1895 * 0x01, Vamic1_dzout
1896 * 0x02, Vamic2_dzout
1897 */
1898 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
1899 /*
1900 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1901 * 0x0c, VanaRegu
1902 */
1903 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1904 /*
1905 * 0x01, VrefDDREna
1906 * 0x02, VrefDDRSleepMode
1907 */
1908 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1909 /*
1910 * 0x03, VextSupply1Regu
1911 * 0x0c, VextSupply2Regu
1912 * 0x30, VextSupply3Regu
1913 * 0x40, ExtSupply2Bypass
1914 * 0x80, ExtSupply3Bypass
1915 */
1916 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1917 /*
1918 * 0x03, Vaux1Regu
1919 * 0x0c, Vaux2Regu
1920 */
1921 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1922 /*
1923 * 0x03, Vaux3Regu
1924 */
1925 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
1926 /*
1927 * 0x0f, Vaux1Sel
1928 */
1929 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1930 /*
1931 * 0x0f, Vaux2Sel
1932 */
1933 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1934 /*
1935 * 0x07, Vaux3Sel
1936 */
1937 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
1938 /*
1939 * 0x01, VextSupply12LP
1940 */
1941 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1942 /*
1943 * 0x04, Vaux1Disch
1944 * 0x08, Vaux2Disch
1945 * 0x10, Vaux3Disch
1946 * 0x20, Vintcore12Disch
1947 * 0x40, VTVoutDisch
1948 * 0x80, VaudioDisch
1949 */
1950 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
1951 /*
1952 * 0x02, VanaDisch
1953 * 0x04, VdmicPullDownEna
1954 * 0x10, VdmicDisch
1955 */
1956 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
1957};
1958
1959/* AB8505 register init */
1960static struct ab8500_reg_init ab8505_reg_init[] = {
1961 /*
1962 * 0x03, VarmRequestCtrl
1963 * 0x0c, VsmpsCRequestCtrl
1964 * 0x30, VsmpsARequestCtrl
1965 * 0xc0, VsmpsBRequestCtrl
1966 */
1967 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1968 /*
1969 * 0x03, VsafeRequestCtrl
1970 * 0x0c, VpllRequestCtrl
1971 * 0x30, VanaRequestCtrl
1972 */
1973 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
1974 /*
1975 * 0x30, Vaux1RequestCtrl
1976 * 0xc0, Vaux2RequestCtrl
1977 */
1978 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
1979 /*
1980 * 0x03, Vaux3RequestCtrl
1981 * 0x04, SwHPReq
1982 */
1983 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1984 /*
1985 * 0x01, VsmpsASysClkReq1HPValid
1986 * 0x02, VsmpsBSysClkReq1HPValid
1987 * 0x04, VsafeSysClkReq1HPValid
1988 * 0x08, VanaSysClkReq1HPValid
1989 * 0x10, VpllSysClkReq1HPValid
1990 * 0x20, Vaux1SysClkReq1HPValid
1991 * 0x40, Vaux2SysClkReq1HPValid
1992 * 0x80, Vaux3SysClkReq1HPValid
1993 */
1994 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
1995 /*
1996 * 0x01, VsmpsCSysClkReq1HPValid
1997 * 0x02, VarmSysClkReq1HPValid
1998 * 0x04, VbbSysClkReq1HPValid
1999 * 0x08, VsmpsMSysClkReq1HPValid
2000 */
2001 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
2002 /*
2003 * 0x01, VsmpsAHwHPReq1Valid
2004 * 0x02, VsmpsBHwHPReq1Valid
2005 * 0x04, VsafeHwHPReq1Valid
2006 * 0x08, VanaHwHPReq1Valid
2007 * 0x10, VpllHwHPReq1Valid
2008 * 0x20, Vaux1HwHPReq1Valid
2009 * 0x40, Vaux2HwHPReq1Valid
2010 * 0x80, Vaux3HwHPReq1Valid
2011 */
2012 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2013 /*
2014 * 0x08, VsmpsMHwHPReq1Valid
2015 */
2016 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
2017 /*
2018 * 0x01, VsmpsAHwHPReq2Valid
2019 * 0x02, VsmpsBHwHPReq2Valid
2020 * 0x04, VsafeHwHPReq2Valid
2021 * 0x08, VanaHwHPReq2Valid
2022 * 0x10, VpllHwHPReq2Valid
2023 * 0x20, Vaux1HwHPReq2Valid
2024 * 0x40, Vaux2HwHPReq2Valid
2025 * 0x80, Vaux3HwHPReq2Valid
2026 */
2027 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2028 /*
2029 * 0x08, VsmpsMHwHPReq2Valid
2030 */
2031 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
2032 /*
2033 * 0x01, VsmpsCSwHPReqValid
2034 * 0x02, VarmSwHPReqValid
2035 * 0x04, VsmpsASwHPReqValid
2036 * 0x08, VsmpsBSwHPReqValid
2037 * 0x10, VsafeSwHPReqValid
2038 * 0x20, VanaSwHPReqValid
2039 * 0x40, VpllSwHPReqValid
2040 * 0x80, Vaux1SwHPReqValid
2041 */
2042 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2043 /*
2044 * 0x01, Vaux2SwHPReqValid
2045 * 0x02, Vaux3SwHPReqValid
2046 * 0x20, VsmpsMSwHPReqValid
2047 */
2048 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
2049 /*
2050 * 0x02, SysClkReq2Valid1
2051 * 0x04, SysClkReq3Valid1
2052 * 0x08, SysClkReq4Valid1
2053 */
2054 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
2055 /*
2056 * 0x02, SysClkReq2Valid2
2057 * 0x04, SysClkReq3Valid2
2058 * 0x08, SysClkReq4Valid2
2059 */
2060 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
2061 /*
2062 * 0x01, Vaux4SwHPReqValid
2063 * 0x02, Vaux4HwHPReq2Valid
2064 * 0x04, Vaux4HwHPReq1Valid
2065 * 0x08, Vaux4SysClkReq1HPValid
2066 */
2067 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2068 /*
2069 * 0x02, VadcEna
2070 * 0x04, VintCore12Ena
2071 * 0x38, VintCore12Sel
2072 * 0x40, VintCore12LP
2073 * 0x80, VadcLP
2074 */
2075 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
2076 /*
2077 * 0x02, VaudioEna
2078 * 0x04, VdmicEna
2079 * 0x08, Vamic1Ena
2080 * 0x10, Vamic2Ena
2081 */
2082 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2083 /*
2084 * 0x01, Vamic1_dzout
2085 * 0x02, Vamic2_dzout
2086 */
2087 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2088 /*
2089 * 0x03, VsmpsARegu
2090 * 0x0c, VsmpsASelCtrl
2091 * 0x10, VsmpsAAutoMode
2092 * 0x20, VsmpsAPWMMode
2093 */
2094 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
2095 /*
2096 * 0x03, VsmpsBRegu
2097 * 0x0c, VsmpsBSelCtrl
2098 * 0x10, VsmpsBAutoMode
2099 * 0x20, VsmpsBPWMMode
2100 */
2101 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
2102 /*
2103 * 0x03, VsafeRegu
2104 * 0x0c, VsafeSelCtrl
2105 * 0x10, VsafeAutoMode
2106 * 0x20, VsafePWMMode
2107 */
2108 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
2109 /*
2110 * 0x03, VpllRegu (NOTE! PRCMU register bits)
2111 * 0x0c, VanaRegu
2112 */
2113 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2114 /*
2115 * 0x03, VextSupply1Regu
2116 * 0x0c, VextSupply2Regu
2117 * 0x30, VextSupply3Regu
2118 * 0x40, ExtSupply2Bypass
2119 * 0x80, ExtSupply3Bypass
2120 */
2121 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2122 /*
2123 * 0x03, Vaux1Regu
2124 * 0x0c, Vaux2Regu
2125 */
2126 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
2127 /*
2128 * 0x0f, Vaux3Regu
2129 */
2130 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2131 /*
2132 * 0x3f, VsmpsASel1
2133 */
2134 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
2135 /*
2136 * 0x3f, VsmpsASel2
2137 */
2138 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
2139 /*
2140 * 0x3f, VsmpsASel3
2141 */
2142 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
2143 /*
2144 * 0x3f, VsmpsBSel1
2145 */
2146 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
2147 /*
2148 * 0x3f, VsmpsBSel2
2149 */
2150 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
2151 /*
2152 * 0x3f, VsmpsBSel3
2153 */
2154 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
2155 /*
2156 * 0x7f, VsafeSel1
2157 */
2158 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
2159 /*
2160 * 0x3f, VsafeSel2
2161 */
2162 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
2163 /*
2164 * 0x3f, VsafeSel3
2165 */
2166 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
2167 /*
2168 * 0x0f, Vaux1Sel
2169 */
2170 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
2171 /*
2172 * 0x0f, Vaux2Sel
2173 */
2174 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
2175 /*
2176 * 0x07, Vaux3Sel
2177 * 0x30, VRF1Sel
2178 */
2179 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2180 /*
2181 * 0x03, Vaux4RequestCtrl
2182 */
2183 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2184 /*
2185 * 0x03, Vaux4Regu
2186 */
2187 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
2188 /*
2189 * 0x0f, Vaux4Sel
2190 */
2191 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
2192 /*
2193 * 0x04, Vaux1Disch
2194 * 0x08, Vaux2Disch
2195 * 0x10, Vaux3Disch
2196 * 0x20, Vintcore12Disch
2197 * 0x40, VTVoutDisch
2198 * 0x80, VaudioDisch
2199 */
2200 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
2201 /*
2202 * 0x02, VanaDisch
2203 * 0x04, VdmicPullDownEna
2204 * 0x10, VdmicDisch
2205 */
2206 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
2207 /*
2208 * 0x01, Vaux4Disch
2209 */
2210 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2211 /*
2212 * 0x07, Vaux5Sel
2213 * 0x08, Vaux5LP
2214 * 0x10, Vaux5Ena
2215 * 0x20, Vaux5Disch
2216 * 0x40, Vaux5DisSfst
2217 * 0x80, Vaux5DisPulld
2218 */
2219 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
2220 /*
2221 * 0x07, Vaux6Sel
2222 * 0x08, Vaux6LP
2223 * 0x10, Vaux6Ena
2224 * 0x80, Vaux6DisPulld
2225 */
2226 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
2227};
2228
2229/* AB9540 register init */
2230static struct ab8500_reg_init ab9540_reg_init[] = {
2231 /*
2232 * 0x03, VarmRequestCtrl
2233 * 0x0c, VapeRequestCtrl
2234 * 0x30, Vsmps1RequestCtrl
2235 * 0xc0, Vsmps2RequestCtrl
2236 */
2237 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2238 /*
2239 * 0x03, Vsmps3RequestCtrl
2240 * 0x0c, VpllRequestCtrl
2241 * 0x30, VanaRequestCtrl
2242 * 0xc0, VextSupply1RequestCtrl
2243 */
2244 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2245 /*
2246 * 0x03, VextSupply2RequestCtrl
2247 * 0x0c, VextSupply3RequestCtrl
2248 * 0x30, Vaux1RequestCtrl
2249 * 0xc0, Vaux2RequestCtrl
2250 */
2251 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2252 /*
2253 * 0x03, Vaux3RequestCtrl
2254 * 0x04, SwHPReq
2255 */
2256 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2257 /*
2258 * 0x01, Vsmps1SysClkReq1HPValid
2259 * 0x02, Vsmps2SysClkReq1HPValid
2260 * 0x04, Vsmps3SysClkReq1HPValid
2261 * 0x08, VanaSysClkReq1HPValid
2262 * 0x10, VpllSysClkReq1HPValid
2263 * 0x20, Vaux1SysClkReq1HPValid
2264 * 0x40, Vaux2SysClkReq1HPValid
2265 * 0x80, Vaux3SysClkReq1HPValid
2266 */
2267 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2268 /*
2269 * 0x01, VapeSysClkReq1HPValid
2270 * 0x02, VarmSysClkReq1HPValid
2271 * 0x04, VbbSysClkReq1HPValid
2272 * 0x08, VmodSysClkReq1HPValid
2273 * 0x10, VextSupply1SysClkReq1HPValid
2274 * 0x20, VextSupply2SysClkReq1HPValid
2275 * 0x40, VextSupply3SysClkReq1HPValid
2276 */
2277 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
2278 /*
2279 * 0x01, Vsmps1HwHPReq1Valid
2280 * 0x02, Vsmps2HwHPReq1Valid
2281 * 0x04, Vsmps3HwHPReq1Valid
2282 * 0x08, VanaHwHPReq1Valid
2283 * 0x10, VpllHwHPReq1Valid
2284 * 0x20, Vaux1HwHPReq1Valid
2285 * 0x40, Vaux2HwHPReq1Valid
2286 * 0x80, Vaux3HwHPReq1Valid
2287 */
2288 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2289 /*
2290 * 0x01, VextSupply1HwHPReq1Valid
2291 * 0x02, VextSupply2HwHPReq1Valid
2292 * 0x04, VextSupply3HwHPReq1Valid
2293 * 0x08, VmodHwHPReq1Valid
2294 */
2295 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
2296 /*
2297 * 0x01, Vsmps1HwHPReq2Valid
2298 * 0x02, Vsmps2HwHPReq2Valid
2299 * 0x03, Vsmps3HwHPReq2Valid
2300 * 0x08, VanaHwHPReq2Valid
2301 * 0x10, VpllHwHPReq2Valid
2302 * 0x20, Vaux1HwHPReq2Valid
2303 * 0x40, Vaux2HwHPReq2Valid
2304 * 0x80, Vaux3HwHPReq2Valid
2305 */
2306 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2307 /*
2308 * 0x01, VextSupply1HwHPReq2Valid
2309 * 0x02, VextSupply2HwHPReq2Valid
2310 * 0x04, VextSupply3HwHPReq2Valid
2311 * 0x08, VmodHwHPReq2Valid
2312 */
2313 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
2314 /*
2315 * 0x01, VapeSwHPReqValid
2316 * 0x02, VarmSwHPReqValid
2317 * 0x04, Vsmps1SwHPReqValid
2318 * 0x08, Vsmps2SwHPReqValid
2319 * 0x10, Vsmps3SwHPReqValid
2320 * 0x20, VanaSwHPReqValid
2321 * 0x40, VpllSwHPReqValid
2322 * 0x80, Vaux1SwHPReqValid
2323 */
2324 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2325 /*
2326 * 0x01, Vaux2SwHPReqValid
2327 * 0x02, Vaux3SwHPReqValid
2328 * 0x04, VextSupply1SwHPReqValid
2329 * 0x08, VextSupply2SwHPReqValid
2330 * 0x10, VextSupply3SwHPReqValid
2331 * 0x20, VmodSwHPReqValid
2332 */
2333 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
2334 /*
2335 * 0x02, SysClkReq2Valid1
2336 * ...
2337 * 0x80, SysClkReq8Valid1
2338 */
2339 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2340 /*
2341 * 0x02, SysClkReq2Valid2
2342 * ...
2343 * 0x80, SysClkReq8Valid2
2344 */
2345 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2346 /*
2347 * 0x01, Vaux4SwHPReqValid
2348 * 0x02, Vaux4HwHPReq2Valid
2349 * 0x04, Vaux4HwHPReq1Valid
2350 * 0x08, Vaux4SysClkReq1HPValid
2351 */
2352 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2353 /*
2354 * 0x02, VTVoutEna
2355 * 0x04, Vintcore12Ena
2356 * 0x38, Vintcore12Sel
2357 * 0x40, Vintcore12LP
2358 * 0x80, VTVoutLP
2359 */
2360 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2361 /*
2362 * 0x02, VaudioEna
2363 * 0x04, VdmicEna
2364 * 0x08, Vamic1Ena
2365 * 0x10, Vamic2Ena
2366 */
2367 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2368 /*
2369 * 0x01, Vamic1_dzout
2370 * 0x02, Vamic2_dzout
2371 */
2372 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2373 /*
2374 * 0x03, Vsmps1Regu
2375 * 0x0c, Vsmps1SelCtrl
2376 * 0x10, Vsmps1AutoMode
2377 * 0x20, Vsmps1PWMMode
2378 */
2379 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2380 /*
2381 * 0x03, Vsmps2Regu
2382 * 0x0c, Vsmps2SelCtrl
2383 * 0x10, Vsmps2AutoMode
2384 * 0x20, Vsmps2PWMMode
2385 */
2386 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2387 /*
2388 * 0x03, Vsmps3Regu
2389 * 0x0c, Vsmps3SelCtrl
2390 * NOTE! PRCMU register
2391 */
2392 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2393 /*
2394 * 0x03, VpllRegu
2395 * 0x0c, VanaRegu
2396 */
2397 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2398 /*
2399 * 0x03, VextSupply1Regu
2400 * 0x0c, VextSupply2Regu
2401 * 0x30, VextSupply3Regu
2402 * 0x40, ExtSupply2Bypass
2403 * 0x80, ExtSupply3Bypass
2404 */
2405 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2406 /*
2407 * 0x03, Vaux1Regu
2408 * 0x0c, Vaux2Regu
2409 */
2410 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2411 /*
2412 * 0x0c, Vrf1Regu
2413 * 0x03, Vaux3Regu
2414 */
2415 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2416 /*
2417 * 0x3f, Vsmps1Sel1
2418 */
2419 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2420 /*
2421 * 0x3f, Vsmps1Sel2
2422 */
2423 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2424 /*
2425 * 0x3f, Vsmps1Sel3
2426 */
2427 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2428 /*
2429 * 0x3f, Vsmps2Sel1
2430 */
2431 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2432 /*
2433 * 0x3f, Vsmps2Sel2
2434 */
2435 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2436 /*
2437 * 0x3f, Vsmps2Sel3
2438 */
2439 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2440 /*
2441 * 0x7f, Vsmps3Sel1
2442 * NOTE! PRCMU register
2443 */
2444 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2445 /*
2446 * 0x7f, Vsmps3Sel2
2447 * NOTE! PRCMU register
2448 */
2449 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2450 /*
2451 * 0x0f, Vaux1Sel
2452 */
2453 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2454 /*
2455 * 0x0f, Vaux2Sel
2456 */
2457 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2458 /*
2459 * 0x07, Vaux3Sel
2460 * 0x30, Vrf1Sel
2461 */
2462 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2463 /*
2464 * 0x01, VextSupply12LP
2465 */
2466 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2467 /*
2468 * 0x03, Vaux4RequestCtrl
2469 */
2470 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2471 /*
2472 * 0x03, Vaux4Regu
2473 */
2474 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2475 /*
2476 * 0x08, Vaux4Sel
2477 */
2478 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2479 /*
2480 * 0x01, VpllDisch
2481 * 0x02, Vrf1Disch
2482 * 0x04, Vaux1Disch
2483 * 0x08, Vaux2Disch
2484 * 0x10, Vaux3Disch
2485 * 0x20, Vintcore12Disch
2486 * 0x40, VTVoutDisch
2487 * 0x80, VaudioDisch
2488 */
2489 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2490 /*
2491 * 0x01, VsimDisch
2492 * 0x02, VanaDisch
2493 * 0x04, VdmicPullDownEna
2494 * 0x08, VpllPullDownEna
2495 * 0x10, VdmicDisch
2496 */
2497 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2498 /*
2499 * 0x01, Vaux4Disch
2500 */
2501 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2502};
2503
2504/* AB8540 register init */
2505static struct ab8500_reg_init ab8540_reg_init[] = {
2506 /*
2507 * 0x01, VSimSycClkReq1Valid
2508 * 0x02, VSimSycClkReq2Valid
2509 * 0x04, VSimSycClkReq3Valid
2510 * 0x08, VSimSycClkReq4Valid
2511 * 0x10, VSimSycClkReq5Valid
2512 * 0x20, VSimSycClkReq6Valid
2513 * 0x40, VSimSycClkReq7Valid
2514 * 0x80, VSimSycClkReq8Valid
2515 */
2516 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2517 /*
2518 * 0x03, VarmRequestCtrl
2519 * 0x0c, VapeRequestCtrl
2520 * 0x30, Vsmps1RequestCtrl
2521 * 0xc0, Vsmps2RequestCtrl
2522 */
2523 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2524 /*
2525 * 0x03, Vsmps3RequestCtrl
2526 * 0x0c, VpllRequestCtrl
2527 * 0x30, VanaRequestCtrl
2528 * 0xc0, VextSupply1RequestCtrl
2529 */
2530 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2531 /*
2532 * 0x03, VextSupply2RequestCtrl
2533 * 0x0c, VextSupply3RequestCtrl
2534 * 0x30, Vaux1RequestCtrl
2535 * 0xc0, Vaux2RequestCtrl
2536 */
2537 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2538 /*
2539 * 0x03, Vaux3RequestCtrl
2540 * 0x04, SwHPReq
2541 */
2542 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2543 /*
2544 * 0x01, Vsmps1SysClkReq1HPValid
2545 * 0x02, Vsmps2SysClkReq1HPValid
2546 * 0x04, Vsmps3SysClkReq1HPValid
2547 * 0x08, VanaSysClkReq1HPValid
2548 * 0x10, VpllSysClkReq1HPValid
2549 * 0x20, Vaux1SysClkReq1HPValid
2550 * 0x40, Vaux2SysClkReq1HPValid
2551 * 0x80, Vaux3SysClkReq1HPValid
2552 */
2553 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2554 /*
2555 * 0x01, VapeSysClkReq1HPValid
2556 * 0x02, VarmSysClkReq1HPValid
2557 * 0x04, VbbSysClkReq1HPValid
2558 * 0x10, VextSupply1SysClkReq1HPValid
2559 * 0x20, VextSupply2SysClkReq1HPValid
2560 * 0x40, VextSupply3SysClkReq1HPValid
2561 */
2562 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2563 /*
2564 * 0x01, Vsmps1HwHPReq1Valid
2565 * 0x02, Vsmps2HwHPReq1Valid
2566 * 0x04, Vsmps3HwHPReq1Valid
2567 * 0x08, VanaHwHPReq1Valid
2568 * 0x10, VpllHwHPReq1Valid
2569 * 0x20, Vaux1HwHPReq1Valid
2570 * 0x40, Vaux2HwHPReq1Valid
2571 * 0x80, Vaux3HwHPReq1Valid
2572 */
2573 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2574 /*
2575 * 0x01, VextSupply1HwHPReq1Valid
2576 * 0x02, VextSupply2HwHPReq1Valid
2577 * 0x04, VextSupply3HwHPReq1Valid
2578 */
2579 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2580 /*
2581 * 0x01, Vsmps1HwHPReq2Valid
2582 * 0x02, Vsmps2HwHPReq2Valid
2583 * 0x03, Vsmps3HwHPReq2Valid
2584 * 0x08, VanaHwHPReq2Valid
2585 * 0x10, VpllHwHPReq2Valid
2586 * 0x20, Vaux1HwHPReq2Valid
2587 * 0x40, Vaux2HwHPReq2Valid
2588 * 0x80, Vaux3HwHPReq2Valid
2589 */
2590 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2591 /*
2592 * 0x01, VextSupply1HwHPReq2Valid
2593 * 0x02, VextSupply2HwHPReq2Valid
2594 * 0x04, VextSupply3HwHPReq2Valid
2595 */
2596 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2597 /*
2598 * 0x01, VapeSwHPReqValid
2599 * 0x02, VarmSwHPReqValid
2600 * 0x04, Vsmps1SwHPReqValid
2601 * 0x08, Vsmps2SwHPReqValid
2602 * 0x10, Vsmps3SwHPReqValid
2603 * 0x20, VanaSwHPReqValid
2604 * 0x40, VpllSwHPReqValid
2605 * 0x80, Vaux1SwHPReqValid
2606 */
2607 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2608 /*
2609 * 0x01, Vaux2SwHPReqValid
2610 * 0x02, Vaux3SwHPReqValid
2611 * 0x04, VextSupply1SwHPReqValid
2612 * 0x08, VextSupply2SwHPReqValid
2613 * 0x10, VextSupply3SwHPReqValid
2614 */
2615 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2616 /*
2617 * 0x02, SysClkReq2Valid1
2618 * ...
2619 * 0x80, SysClkReq8Valid1
2620 */
2621 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2622 /*
2623 * 0x02, SysClkReq2Valid2
2624 * ...
2625 * 0x80, SysClkReq8Valid2
2626 */
2627 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2628 /*
2629 * 0x01, Vaux4SwHPReqValid
2630 * 0x02, Vaux4HwHPReq2Valid
2631 * 0x04, Vaux4HwHPReq1Valid
2632 * 0x08, Vaux4SysClkReq1HPValid
2633 */
2634 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2635 /*
2636 * 0x01, Vaux5SwHPReqValid
2637 * 0x02, Vaux5HwHPReq2Valid
2638 * 0x04, Vaux5HwHPReq1Valid
2639 * 0x08, Vaux5SysClkReq1HPValid
2640 */
2641 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2642 /*
2643 * 0x01, Vaux6SwHPReqValid
2644 * 0x02, Vaux6HwHPReq2Valid
2645 * 0x04, Vaux6HwHPReq1Valid
2646 * 0x08, Vaux6SysClkReq1HPValid
2647 */
2648 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2649 /*
2650 * 0x01, VclkbSwHPReqValid
2651 * 0x02, VclkbHwHPReq2Valid
2652 * 0x04, VclkbHwHPReq1Valid
2653 * 0x08, VclkbSysClkReq1HPValid
2654 */
2655 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2656 /*
2657 * 0x01, Vrf1SwHPReqValid
2658 * 0x02, Vrf1HwHPReq2Valid
2659 * 0x04, Vrf1HwHPReq1Valid
2660 * 0x08, Vrf1SysClkReq1HPValid
2661 */
2662 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2663 /*
2664 * 0x02, VTVoutEna
2665 * 0x04, Vintcore12Ena
2666 * 0x38, Vintcore12Sel
2667 * 0x40, Vintcore12LP
2668 * 0x80, VTVoutLP
2669 */
2670 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2671 /*
2672 * 0x02, VaudioEna
2673 * 0x04, VdmicEna
2674 * 0x08, Vamic1Ena
2675 * 0x10, Vamic2Ena
2676 * 0x20, Vamic12LP
2677 * 0xC0, VdmicSel
2678 */
2679 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2680 /*
2681 * 0x01, Vamic1_dzout
2682 * 0x02, Vamic2_dzout
2683 */
2684 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2685 /*
2686 * 0x07, VHSICSel
2687 * 0x08, VHSICOffState
2688 * 0x10, VHSIEna
2689 * 0x20, VHSICLP
2690 */
2691 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2692 /*
2693 * 0x07, VSDIOSel
2694 * 0x08, VSDIOOffState
2695 * 0x10, VSDIOEna
2696 * 0x20, VSDIOLP
2697 */
2698 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2699 /*
2700 * 0x03, Vsmps1Regu
2701 * 0x0c, Vsmps1SelCtrl
2702 * 0x10, Vsmps1AutoMode
2703 * 0x20, Vsmps1PWMMode
2704 */
2705 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2706 /*
2707 * 0x03, Vsmps2Regu
2708 * 0x0c, Vsmps2SelCtrl
2709 * 0x10, Vsmps2AutoMode
2710 * 0x20, Vsmps2PWMMode
2711 */
2712 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2713 /*
2714 * 0x03, Vsmps3Regu
2715 * 0x0c, Vsmps3SelCtrl
2716 * 0x10, Vsmps3AutoMode
2717 * 0x20, Vsmps3PWMMode
2718 * NOTE! PRCMU register
2719 */
2720 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2721 /*
2722 * 0x03, VpllRegu
2723 * 0x0c, VanaRegu
2724 */
2725 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2726 /*
2727 * 0x03, VextSupply1Regu
2728 * 0x0c, VextSupply2Regu
2729 * 0x30, VextSupply3Regu
2730 * 0x40, ExtSupply2Bypass
2731 * 0x80, ExtSupply3Bypass
2732 */
2733 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2734 /*
2735 * 0x03, Vaux1Regu
2736 * 0x0c, Vaux2Regu
2737 */
2738 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2739 /*
2740 * 0x0c, VRF1Regu
2741 * 0x03, Vaux3Regu
2742 */
2743 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2744 /*
2745 * 0x3f, Vsmps1Sel1
2746 */
2747 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2748 /*
2749 * 0x3f, Vsmps1Sel2
2750 */
2751 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2752 /*
2753 * 0x3f, Vsmps1Sel3
2754 */
2755 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2756 /*
2757 * 0x3f, Vsmps2Sel1
2758 */
2759 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2760 /*
2761 * 0x3f, Vsmps2Sel2
2762 */
2763 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2764 /*
2765 * 0x3f, Vsmps2Sel3
2766 */
2767 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2768 /*
2769 * 0x7f, Vsmps3Sel1
2770 * NOTE! PRCMU register
2771 */
2772 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2773 /*
2774 * 0x7f, Vsmps3Sel2
2775 * NOTE! PRCMU register
2776 */
2777 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2778 /*
2779 * 0x0f, Vaux1Sel
2780 */
2781 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2782 /*
2783 * 0x0f, Vaux2Sel
2784 */
2785 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2786 /*
2787 * 0x07, Vaux3Sel
2788 * 0x70, Vrf1Sel
2789 */
2790 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2791 /*
2792 * 0x01, VextSupply12LP
2793 */
2794 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2795 /*
2796 * 0x07, Vanasel
2797 * 0x30, Vpllsel
2798 */
2799 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2800 /*
2801 * 0x03, Vaux4RequestCtrl
2802 */
2803 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2804 /*
2805 * 0x03, Vaux4Regu
2806 */
2807 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2808 /*
2809 * 0x0f, Vaux4Sel
2810 */
2811 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2812 /*
2813 * 0x03, Vaux5RequestCtrl
2814 */
2815 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2816 /*
2817 * 0x03, Vaux5Regu
2818 */
2819 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2820 /*
2821 * 0x3f, Vaux5Sel
2822 */
2823 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2824 /*
2825 * 0x03, Vaux6RequestCtrl
2826 */
2827 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2828 /*
2829 * 0x03, Vaux6Regu
2830 */
2831 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2832 /*
2833 * 0x3f, Vaux6Sel
2834 */
2835 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2836 /*
2837 * 0x03, VCLKBRequestCtrl
2838 */
2839 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2840 /*
2841 * 0x03, VCLKBRegu
2842 */
2843 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2844 /*
2845 * 0x07, VCLKBSel
2846 */
2847 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2848 /*
2849 * 0x03, Vrf1RequestCtrl
2850 */
2851 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2852 /*
2853 * 0x01, VpllDisch
2854 * 0x02, Vrf1Disch
2855 * 0x04, Vaux1Disch
2856 * 0x08, Vaux2Disch
2857 * 0x10, Vaux3Disch
2858 * 0x20, Vintcore12Disch
2859 * 0x40, VTVoutDisch
2860 * 0x80, VaudioDisch
2861 */
2862 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2863 /*
2864 * 0x02, VanaDisch
2865 * 0x04, VdmicPullDownEna
2866 * 0x08, VpllPullDownEna
2867 * 0x10, VdmicDisch
2868 */
2869 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2870 /*
2871 * 0x01, Vaux4Disch
2872 */
2873 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2874 /*
2875 * 0x01, Vaux5Disch
2876 * 0x02, Vaux6Disch
2877 * 0x04, VCLKBDisch
2878 */
2879 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2880};
2881
2882static struct of_regulator_match ab8500_regulator_match[] = {
2883 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
2884 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
2885 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
2886 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
2887 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
2888 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
2889 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
2890 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
2891 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
2892 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
2893};
2894
2895static struct of_regulator_match ab8505_regulator_match[] = {
2896 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
2897 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
2898 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
2899 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
2900 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
2901 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
2902 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
2903 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2904 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2905 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2906 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2907 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2908 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2909};
2910
2911static struct of_regulator_match ab8540_regulator_match[] = {
2912 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
2913 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
2914 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
2915 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
2916 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8540_LDO_AUX5, },
2917 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8540_LDO_AUX6, },
2918 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
2919 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
2920 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
2921 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
2922 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
2923 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
2924 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
2925 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
2926};
2927
2928static struct of_regulator_match ab9540_regulator_match[] = {
2929 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
2930 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
2931 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
2932 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
2933 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
2934 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
2935 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
2936 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
2937 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
2938 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
2939 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
2940};
2941
2942static struct {
2943 struct ab8500_regulator_info *info;
2944 int info_size;
2945 struct ab8500_reg_init *init;
2946 int init_size;
2947 struct of_regulator_match *match;
2948 int match_size;
2949} abx500_regulator;
2950
2951static void abx500_get_regulator_info(struct ab8500 *ab8500)
2952{
2953 if (is_ab9540(ab8500)) {
2954 abx500_regulator.info = ab9540_regulator_info;
2955 abx500_regulator.info_size = ARRAY_SIZE(ab9540_regulator_info);
2956 abx500_regulator.init = ab9540_reg_init;
2957 abx500_regulator.init_size = AB9540_NUM_REGULATOR_REGISTERS;
2958 abx500_regulator.match = ab9540_regulator_match;
2959 abx500_regulator.match_size = ARRAY_SIZE(ab9540_regulator_match);
2960 } else if (is_ab8505(ab8500)) {
2961 abx500_regulator.info = ab8505_regulator_info;
2962 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info);
2963 abx500_regulator.init = ab8505_reg_init;
2964 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS;
2965 abx500_regulator.match = ab8505_regulator_match;
2966 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match);
2967 } else if (is_ab8540(ab8500)) {
2968 abx500_regulator.info = ab8540_regulator_info;
2969 abx500_regulator.info_size = ARRAY_SIZE(ab8540_regulator_info);
2970 abx500_regulator.init = ab8540_reg_init;
2971 abx500_regulator.init_size = AB8540_NUM_REGULATOR_REGISTERS;
2972 abx500_regulator.match = ab8540_regulator_match;
2973 abx500_regulator.match_size = ARRAY_SIZE(ab8540_regulator_match);
2974 } else {
2975 abx500_regulator.info = ab8500_regulator_info;
2976 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info);
2977 abx500_regulator.init = ab8500_reg_init;
2978 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS;
2979 abx500_regulator.match = ab8500_regulator_match;
2980 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match);
2981 }
2982}
2983
2984static int ab8500_regulator_register(struct platform_device *pdev,
2985 struct regulator_init_data *init_data,
2986 int id, struct device_node *np)
2987{
2988 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
2989 struct ab8500_regulator_info *info = NULL;
2990 struct regulator_config config = { };
2991
2992 /* assign per-regulator data */
2993 info = &abx500_regulator.info[id];
2994 info->dev = &pdev->dev;
2995
2996 config.dev = &pdev->dev;
2997 config.init_data = init_data;
2998 config.driver_data = info;
2999 config.of_node = np;
3000
3001 /* fix for hardware before ab8500v2.0 */
3002 if (is_ab8500_1p1_or_earlier(ab8500)) {
3003 if (info->desc.id == AB8500_LDO_AUX3) {
3004 info->desc.n_voltages =
3005 ARRAY_SIZE(ldo_vauxn_voltages);
3006 info->desc.volt_table = ldo_vauxn_voltages;
3007 info->voltage_mask = 0xf;
3008 }
3009 }
3010
3011 /* register regulator with framework */
3012 info->regulator = devm_regulator_register(&pdev->dev, &info->desc,
3013 &config);
3014 if (IS_ERR(info->regulator)) {
3015 dev_err(&pdev->dev, "failed to register regulator %s\n",
3016 info->desc.name);
3017 return PTR_ERR(info->regulator);
3018 }
3019
3020 return 0;
3021}
3022
3023static int ab8500_regulator_probe(struct platform_device *pdev)
3024{
3025 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3026 struct device_node *np = pdev->dev.of_node;
3027 struct of_regulator_match *match;
3028 int err, i;
3029
3030 if (!ab8500) {
3031 dev_err(&pdev->dev, "null mfd parent\n");
3032 return -EINVAL;
3033 }
3034
3035 abx500_get_regulator_info(ab8500);
3036
3037 err = of_regulator_match(&pdev->dev, np,
3038 abx500_regulator.match,
3039 abx500_regulator.match_size);
3040 if (err < 0) {
3041 dev_err(&pdev->dev,
3042 "Error parsing regulator init data: %d\n", err);
3043 return err;
3044 }
3045
3046 match = abx500_regulator.match;
3047 for (i = 0; i < abx500_regulator.info_size; i++) {
3048 err = ab8500_regulator_register(pdev, match[i].init_data, i,
3049 match[i].of_node);
3050 if (err)
3051 return err;
3052 }
3053
3054 return 0;
3055}
3056
3057static struct platform_driver ab8500_regulator_driver = {
3058 .probe = ab8500_regulator_probe,
3059 .driver = {
3060 .name = "ab8500-regulator",
3061 },
3062};
3063
3064static int __init ab8500_regulator_init(void)
3065{
3066 int ret;
3067
3068 ret = platform_driver_register(&ab8500_regulator_driver);
3069 if (ret != 0)
3070 pr_err("Failed to register ab8500 regulator: %d\n", ret);
3071
3072 return ret;
3073}
3074subsys_initcall(ab8500_regulator_init);
3075
3076static void __exit ab8500_regulator_exit(void)
3077{
3078 platform_driver_unregister(&ab8500_regulator_driver);
3079}
3080module_exit(ab8500_regulator_exit);
3081
3082MODULE_LICENSE("GPL v2");
3083MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
3084MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
3085MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
3086MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
3087MODULE_ALIAS("platform:ab8500-regulator");