blob: 670efddf29fc84a940337f53769a1a329efbf529 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (C) 2018 MediaTek, Inc.
3 * Author: Wilma Wu <wilma.wu@mediatek.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <asm/div64.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm.h>
21#include <linux/pm_wakeup.h>
22#include <linux/reboot.h>
23#include <linux/regmap.h>
24#include <linux/rtc.h>
25#include <linux/sched/clock.h>
26#include <linux/spinlock.h>
27#include <linux/types.h>
28#include <linux/bitops.h>
29#include <linux/mfd/mt6358/core.h>
30#include <linux/irqdomain.h>
31#include <linux/platform_device.h>
32#include <linux/of_address.h>
33#include <linux/of_irq.h>
34#include <linux/io.h>
35#include <asm/div64.h>
36/* For KPOC alarm */
37#include <linux/notifier.h>
38#include <linux/suspend.h>
39#include "../misc/mediatek/include/mt-plat/mtk_boot_common.h"
40
41#ifdef pr_fmt
42#undef pr_fmt
43#endif
44#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45
46#define RTC_NAME "mt-rtc"
47#define IPIMB
48
49
50/* we map HW YEA 0 (2000) to 1968 not 1970 because 2000 is the leap year */
51#define RTC_MIN_YEAR 1968
52#define RTC_BASE_YEAR 1900
53#define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR)
54
55/* Min, Hour, Dom... register offset to RTC_TC_SEC */
56#define RTC_OFFSET_SEC 0
57#define RTC_OFFSET_MIN 1
58#define RTC_OFFSET_HOUR 2
59#define RTC_OFFSET_DOM 3
60#define RTC_OFFSET_DOW 4
61#define RTC_OFFSET_MTH 5
62#define RTC_OFFSET_YEAR 6
63#define RTC_OFFSET_COUNT 7
64
65#define RTC_DSN_ID 0x580
66#define RTC_BBPU 0x8
67#define RTC_IRQ_STA 0xa
68#define RTC_IRQ_EN 0xc
69#define RTC_AL_MASK 0x10
70#define RTC_TC_SEC 0x12
71#define RTC_AL_SEC 0x20
72#define RTC_AL_MIN 0x22
73#define RTC_AL_HOU 0x24
74#define RTC_AL_DOM 0x26
75#define RTC_AL_DOW 0x28
76#define RTC_AL_MTH 0x2a
77#define RTC_AL_YEA 0x2c
78#define RTC_OSC32CON 0x2e
79#define RTC_POWERKEY1 0x30
80#define RTC_POWERKEY2 0x32
81#define RTC_PDN1 0x34
82#define RTC_PDN2 0x36
83#define RTC_SPAR0 0x38
84#define RTC_SPAR1 0x3a
85#define RTC_PROT 0x3c
86#define RTC_WRTGR 0x42
87#define RTC_CON 0x44
88
89#define RTC_TC_SEC_MASK 0x3f
90#define RTC_TC_MIN_MASK 0x3f
91#define RTC_TC_HOU_MASK 0x1f
92#define RTC_TC_DOM_MASK 0x1f
93#define RTC_TC_DOW_MASK 0x7
94#define RTC_TC_MTH_MASK 0xf
95#define RTC_TC_YEA_MASK 0x7f
96
97#define RTC_AL_SEC_MASK 0x3f
98#define RTC_AL_MIN_MASK 0x3f
99#define RTC_AL_HOU_MASK 0x1f
100#define RTC_AL_DOM_MASK 0x1f
101#define RTC_AL_DOW_MASK 0x7
102#define RTC_AL_MTH_MASK 0xf
103#define RTC_AL_YEA_MASK 0x7f
104
105#define RTC_PWRON_SEC_SHIFT 0x0
106#define RTC_PWRON_MIN_SHIFT 0x0
107#define RTC_PWRON_HOU_SHIFT 0x6
108#define RTC_PWRON_DOM_SHIFT 0xb
109#define RTC_PWRON_MTH_SHIFT 0x0
110#define RTC_PWRON_YEA_SHIFT 0x8
111
112#define RTC_PWRON_SEC_MASK (RTC_AL_SEC_MASK << RTC_PWRON_SEC_SHIFT)
113#define RTC_PWRON_MIN_MASK (RTC_AL_MIN_MASK << RTC_PWRON_MIN_SHIFT)
114#define RTC_PWRON_HOU_MASK (RTC_AL_HOU_MASK << RTC_PWRON_HOU_SHIFT)
115#define RTC_PWRON_DOM_MASK (RTC_AL_DOM_MASK << RTC_PWRON_DOM_SHIFT)
116#define RTC_PWRON_MTH_MASK (RTC_AL_MTH_MASK << RTC_PWRON_MTH_SHIFT)
117#define RTC_PWRON_YEA_MASK (RTC_AL_YEA_MASK << RTC_PWRON_YEA_SHIFT)
118
119#define RTC_BBPU_KEY 0x4300
120#define RTC_BBPU_CBUSY BIT(6)
121#define RTC_BBPU_RELOAD BIT(5)
122#define RTC_BBPU_AUTO BIT(3)
123#define RTC_BBPU_CLR BIT(1)
124#define RTC_BBPU_PWREN BIT(0)
125#define RTC_BBPU_AL_STA BIT(7)
126#define RTC_BBPU_RESET_AL BIT(3)
127#define RTC_BBPU_RESET_SPAR BIT(2)
128
129#define RTC_AL_MASK_DOW BIT(4)
130
131#define RTC_IRQ_EN_LP BIT(3)
132#define RTC_IRQ_EN_ONESHOT BIT(2)
133#define RTC_IRQ_EN_AL BIT(0)
134#define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL)
135
136#define RTC_IRQ_STA_LP BIT(3)
137#define RTC_IRQ_STA_AL BIT(0)
138
139#define RTC_PDN1_PWRON_TIME BIT(7)
140#define RTC_PDN2_PWRON_LOGO BIT(15)
141#define RTC_PDN2_PWRON_ALARM BIT(4)
142
143
144static u16 rtc_alarm_reg[RTC_OFFSET_COUNT][3] = {
145 {RTC_AL_SEC, RTC_AL_SEC_MASK, 0},
146 {RTC_AL_MIN, RTC_AL_MIN_MASK, 0},
147 {RTC_AL_HOU, RTC_AL_HOU_MASK, 0},
148 {RTC_AL_DOM, RTC_AL_DOM_MASK, 0},
149 {RTC_AL_DOW, RTC_AL_DOW_MASK, 0},
150 {RTC_AL_MTH, RTC_AL_MTH_MASK, 0},
151 {RTC_AL_YEA, RTC_AL_YEA_MASK, 0},
152};
153
154static u16 rtc_pwron_reg[RTC_OFFSET_COUNT][3] = {
155 {RTC_SPAR0, RTC_PWRON_SEC_MASK, RTC_PWRON_SEC_SHIFT},
156 {RTC_SPAR1, RTC_PWRON_MIN_MASK, RTC_PWRON_MIN_SHIFT},
157 {RTC_SPAR1, RTC_PWRON_HOU_MASK, RTC_PWRON_HOU_SHIFT},
158 {RTC_SPAR1, RTC_PWRON_DOM_MASK, RTC_PWRON_DOM_SHIFT},
159 {0, 0, 0},
160 {RTC_PDN2, RTC_PWRON_MTH_MASK, RTC_PWRON_MTH_SHIFT},
161 {RTC_PDN2, RTC_PWRON_YEA_MASK, RTC_PWRON_YEA_SHIFT},
162};
163
164enum rtc_reg_set {
165 RTC_REG,
166 RTC_MASK,
167 RTC_SHIFT
168};
169
170struct mt6358_rtc {
171 struct device *dev;
172 struct rtc_device *rtc_dev;
173 spinlock_t lock;
174 struct regmap *regmap;
175 int irq;
176 u32 addr_base;
177};
178static struct mt6358_rtc *mt_rtc;
179
180static int rtc_show_time;
181static int rtc_show_alarm = 1;
182static int apply_lpsd_solution;
183/*for KPOC alarm*/
184static bool rtc_pm_notifier_registered;
185static unsigned long rtc_pm_status;
186
187module_param(rtc_show_time, int, 0644);
188module_param(rtc_show_alarm, int, 0644);
189
190static int rtc_read(unsigned int reg, unsigned int *val)
191{
192 return regmap_read(mt_rtc->regmap, mt_rtc->addr_base + reg, val);
193}
194
195static int rtc_write(unsigned int reg, unsigned int val)
196{
197 return regmap_write(mt_rtc->regmap, mt_rtc->addr_base + reg, val);
198}
199
200static int rtc_update_bits(unsigned int reg,
201 unsigned int mask, unsigned int val)
202{
203 return regmap_update_bits(mt_rtc->regmap,
204 mt_rtc->addr_base + reg, mask, val);
205}
206
207static int rtc_field_read(unsigned int reg,
208 unsigned int mask, unsigned int shift, unsigned int *val)
209{
210 int ret;
211 unsigned int reg_val;
212
213 ret = rtc_read(reg, &reg_val);
214 if (ret != 0)
215 return ret;
216
217 reg_val &= mask;
218 reg_val >>= shift;
219 *val = reg_val;
220
221 return ret;
222}
223
224#define BULK_WRITE 0
225#define BULK_READ 1
226
227static int rtc_bulk_access(int mode, unsigned int reg, void *val,
228 size_t val_count)
229{
230 if (mode == BULK_WRITE) {
231 return regmap_bulk_write(mt_rtc->regmap,
232 mt_rtc->addr_base + reg, val, val_count);
233 } else if (mode == BULK_READ) {
234 return regmap_bulk_read(mt_rtc->regmap,
235 mt_rtc->addr_base + reg, val, val_count);
236 } else
237 return -EPERM;
238}
239
240static int rtc_write_trigger(void)
241{
242 int ret, bbpu;
243 unsigned long long timeout = sched_clock() + 500000000;
244 u32 pwrkey1, pwrkey2, sec;
245
246 ret = rtc_write(RTC_WRTGR, 1);
247 if (ret < 0)
248 return ret;
249
250 do {
251 ret = rtc_read(RTC_BBPU, &bbpu);
252 if (ret < 0)
253 break;
254 if ((bbpu & RTC_BBPU_CBUSY) == 0)
255 break;
256 else if (sched_clock() > timeout) {
257 rtc_read(RTC_BBPU, &bbpu);
258 rtc_read(RTC_POWERKEY1, &pwrkey1);
259 rtc_read(RTC_POWERKEY2, &pwrkey2);
260 rtc_read(RTC_TC_SEC, &sec);
261 pr_err("%s, wait cbusy timeout, %x, %x, %x, %d\n",
262 __func__, bbpu, pwrkey1, pwrkey2, sec);
263 ret = -ETIMEDOUT;
264 break;
265 }
266 } while (1);
267
268 return ret;
269}
270
271static int mtk_rtc_read_time(struct rtc_time *tm)
272{
273 u16 data[RTC_OFFSET_COUNT];
274 int ret;
275 u32 sec;
276
277 do {
278
279 ret = rtc_bulk_access(BULK_READ, RTC_TC_SEC,
280 data, RTC_OFFSET_COUNT);
281 if (ret < 0)
282 goto exit;
283 tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_TC_SEC_MASK;
284 tm->tm_min = data[RTC_OFFSET_MIN] & RTC_TC_MIN_MASK;
285 tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_TC_HOU_MASK;
286 tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_TC_DOM_MASK;
287 tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_TC_MTH_MASK;
288 tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_TC_YEA_MASK;
289
290 ret = rtc_read(RTC_TC_SEC, &sec);
291 if (ret < 0)
292 goto exit;
293
294 } while (sec < tm->tm_sec);
295
296 return ret;
297
298exit:
299 pr_err("%s error\n", __func__);
300 return ret;
301}
302
303static int mtk_rtc_set_alarm(struct rtc_time *tm)
304{
305 int ret, i;
306 u16 data[RTC_OFFSET_COUNT];
307
308 data[RTC_OFFSET_SEC] = tm->tm_sec & RTC_AL_SEC_MASK;
309 data[RTC_OFFSET_MIN] = tm->tm_min & RTC_AL_MIN_MASK;
310 data[RTC_OFFSET_HOUR] = tm->tm_hour & RTC_AL_HOU_MASK;
311 data[RTC_OFFSET_DOM] = tm->tm_mday & RTC_AL_DOM_MASK;
312 data[RTC_OFFSET_MTH] = tm->tm_mon & RTC_AL_MTH_MASK;
313 data[RTC_OFFSET_YEAR] = tm->tm_year & RTC_AL_YEA_MASK;
314
315 for (i = RTC_OFFSET_SEC; i < RTC_OFFSET_COUNT; i++) {
316 if (i == RTC_OFFSET_DOW)
317 continue;
318 ret = rtc_update_bits(rtc_alarm_reg[i][RTC_REG],
319 rtc_alarm_reg[i][RTC_MASK], data[i]);
320 if (ret < 0)
321 goto exit;
322 }
323 ret = rtc_write(RTC_AL_MASK, RTC_AL_MASK_DOW); /* mask DOW */
324 if (ret < 0)
325 goto exit;
326 ret = rtc_write_trigger();
327 if (ret < 0)
328 goto exit;
329
330 ret = rtc_update_bits(RTC_IRQ_EN,
331 RTC_IRQ_EN_ONESHOT_AL,
332 RTC_IRQ_EN_ONESHOT_AL);
333 if (ret < 0)
334 goto exit;
335 ret = rtc_write_trigger();
336 if (ret < 0)
337 goto exit;
338
339 return ret;
340exit:
341 pr_err("%s error\n", __func__);
342 return ret;
343}
344
345bool mtk_rtc_is_pwron_alarm(struct rtc_time *nowtm, struct rtc_time *tm)
346{
347 u32 pdn1;
348 u32 data[RTC_OFFSET_COUNT];
349 int ret, i;
350
351 ret = rtc_read(RTC_PDN1, &pdn1);
352 if (ret < 0)
353 goto exit;
354 pr_notice("pdn1 = 0x%4x\n", pdn1);
355
356 if (pdn1 & RTC_PDN1_PWRON_TIME) { /* power-on time is available */
357
358 ret = mtk_rtc_read_time(nowtm);
359 if (ret < 0)
360 goto exit;
361
362 for (i = RTC_OFFSET_SEC; i < RTC_OFFSET_COUNT; i++) {
363 if (i == RTC_OFFSET_DOW)
364 continue;
365 ret = rtc_field_read(rtc_pwron_reg[i][RTC_REG],
366 rtc_pwron_reg[i][RTC_MASK],
367 rtc_pwron_reg[i][RTC_SHIFT], &data[i]);
368 if (ret < 0)
369 goto exit;
370 }
371 tm->tm_sec = data[RTC_OFFSET_SEC];
372 tm->tm_min = data[RTC_OFFSET_MIN];
373 tm->tm_hour = data[RTC_OFFSET_HOUR];
374 tm->tm_mday = data[RTC_OFFSET_DOM];
375 tm->tm_mon = data[RTC_OFFSET_MTH];
376 tm->tm_year = data[RTC_OFFSET_YEAR];
377
378 return true;
379 }
380 return false;
381exit:
382 pr_err("%s error\n", __func__);
383 return false;
384}
385
386static int mtk_rtc_set_pwron_alarm_time(struct rtc_time *tm)
387{
388 u16 data[RTC_OFFSET_COUNT];
389 int ret, i;
390
391 pr_err("%s\n", __func__);
392
393 data[RTC_OFFSET_SEC] =
394 ((tm->tm_sec << RTC_PWRON_SEC_SHIFT) & RTC_PWRON_SEC_MASK);
395 data[RTC_OFFSET_MIN] =
396 ((tm->tm_min << RTC_PWRON_MIN_SHIFT) & RTC_PWRON_MIN_MASK);
397 data[RTC_OFFSET_HOUR] =
398 ((tm->tm_hour << RTC_PWRON_HOU_SHIFT) & RTC_PWRON_HOU_MASK);
399 data[RTC_OFFSET_DOM] =
400 ((tm->tm_mday << RTC_PWRON_DOM_SHIFT) & RTC_PWRON_DOM_MASK);
401 data[RTC_OFFSET_MTH] =
402 ((tm->tm_mon << RTC_PWRON_MTH_SHIFT) & RTC_PWRON_MTH_MASK);
403 data[RTC_OFFSET_YEAR] =
404 ((tm->tm_year << RTC_PWRON_YEA_SHIFT) & RTC_PWRON_YEA_MASK);
405
406 for (i = RTC_OFFSET_SEC; i < RTC_OFFSET_COUNT; i++) {
407 if (i == RTC_OFFSET_DOW)
408 continue;
409 ret = rtc_update_bits(rtc_pwron_reg[i][RTC_REG],
410 rtc_pwron_reg[i][RTC_MASK], data[i]);
411 if (ret < 0)
412 goto exit;
413 ret = rtc_write_trigger();
414 if (ret < 0)
415 goto exit;
416 }
417 return ret;
418exit:
419 pr_err("%s error\n", __func__);
420 return ret;
421}
422
423static int mtk_rtc_set_pwron_alarm(bool enable, struct rtc_time *tm, bool logo)
424{
425 u16 pdn1 = 0, pdn2 = 0;
426 int ret;
427
428 ret = mtk_rtc_set_pwron_alarm_time(tm);
429 if (ret < 0)
430 goto exit;
431
432 if (enable)
433 pdn1 = RTC_PDN1_PWRON_TIME;
434 ret = rtc_update_bits(RTC_PDN1, RTC_PDN1_PWRON_TIME, pdn1);
435 if (ret < 0)
436 goto exit;
437
438 if (logo)
439 pdn2 = RTC_PDN2_PWRON_LOGO;
440 ret = rtc_update_bits(RTC_PDN2, RTC_PDN2_PWRON_LOGO, pdn2);
441 if (ret < 0)
442 goto exit;
443
444 ret = rtc_write_trigger();
445 if (ret < 0)
446 goto exit;
447
448 return ret;
449
450exit:
451 pr_err("%s error\n", __func__);
452 return ret;
453}
454
455#ifdef CONFIG_PM
456
457#define PM_DUMMY 0xFFFF
458
459static int rtc_pm_event(struct notifier_block *notifier, unsigned long pm_event,
460 void *unused)
461{
462 switch (pm_event) {
463 case PM_SUSPEND_PREPARE:
464 rtc_pm_status = PM_SUSPEND_PREPARE;
465 break;
466 case PM_POST_SUSPEND:
467 rtc_pm_status = PM_POST_SUSPEND;
468 break;
469 default:
470 rtc_pm_status = PM_DUMMY;
471 break;
472 }
473 return NOTIFY_DONE;
474}
475
476static struct notifier_block rtc_pm_notifier_func = {
477 .notifier_call = rtc_pm_event,
478 .priority = 0,
479};
480#endif /* CONFIG_PM */
481
482static bool mtk_rtc_check_pm_valid(void)
483{
484 pr_notice("%s = %lu\n", __func__, rtc_pm_status);
485
486 if (rtc_pm_status != PM_SUSPEND_PREPARE)
487 return true;
488 return false;
489}
490
491static void mtk_rtc_reboot(void)
492{
493 unsigned long long timeout = sched_clock() + (30000000000ULL);
494
495 if (rtc_pm_notifier_registered) {
496 do {
497 if (sched_clock() > timeout) {
498 pr_notice("%s timeout\n", __func__);
499 WARN_ON(1);
500 }
501
502 if (mtk_rtc_check_pm_valid())
503 break;
504
505 mdelay(500);
506 cpu_relax();
507 } while (1);
508 }
509
510 kernel_restart("kpoc");
511}
512
513#ifndef USER_BUILD_KERNEL
514void mtk_rtc_lp_exception(void)
515{
516 u32 bbpu, irqsta, irqen, osc32;
517 u32 pwrkey1, pwrkey2, prot, con, sec1, sec2;
518
519 rtc_read(RTC_BBPU, &bbpu);
520 rtc_read(RTC_IRQ_STA, &irqsta);
521 rtc_read(RTC_IRQ_EN, &irqen);
522 rtc_read(RTC_OSC32CON, &osc32);
523 rtc_read(RTC_POWERKEY1, &pwrkey1);
524 rtc_read(RTC_POWERKEY2, &pwrkey2);
525 rtc_read(RTC_PROT, &prot);
526 rtc_read(RTC_CON, &con);
527 rtc_read(RTC_TC_SEC, &sec1);
528 mdelay(2000);
529 rtc_read(RTC_TC_SEC, &sec2);
530
531 pr_emerg("!!! 32K WAS STOPPED !!!\n"
532 "RTC_BBPU = 0x%x\n"
533 "RTC_IRQ_STA = 0x%x\n"
534 "RTC_IRQ_EN = 0x%x\n"
535 "RTC_OSC32CON = 0x%x\n"
536 "RTC_POWERKEY1 = 0x%x\n"
537 "RTC_POWERKEY2 = 0x%x\n"
538 "RTC_PROT = 0x%x\n"
539 "RTC_CON = 0x%x\n"
540 "RTC_TC_SEC = %02d\n"
541 "RTC_TC_SEC = %02d\n",
542 bbpu, irqsta, irqen, osc32, pwrkey1, pwrkey2, prot, con, sec1,
543 sec2);
544}
545#endif
546
547static bool mtk_rtc_is_alarm_irq(void)
548{
549 u32 irqsta, bbpu;
550 int ret, val;
551
552 ret = rtc_read(RTC_IRQ_STA, &irqsta); /* read clear */
553
554#ifndef USER_BUILD_KERNEL
555 if ((ret == 0) && (irqsta & RTC_IRQ_STA_LP))
556 mtk_rtc_lp_exception();
557#endif
558
559 if ((ret == 0) && (irqsta & RTC_IRQ_STA_AL))
560 return true;
561
562 return false;
563}
564
565static void mtk_rtc_update_pwron_alarm_flag(void)
566{
567 int ret;
568
569 ret = rtc_update_bits(RTC_PDN1, RTC_PDN1_PWRON_TIME, 0);
570 if (ret < 0)
571 goto exit;
572 ret = rtc_update_bits(RTC_PDN2,
573 RTC_PDN2_PWRON_ALARM,
574 RTC_PDN2_PWRON_ALARM);
575 if (ret < 0)
576 goto exit;
577 ret = rtc_write_trigger();
578 if (ret < 0)
579 goto exit;
580
581 return;
582exit:
583 pr_err("%s error\n", __func__);
584}
585
586static void mtk_rtc_reset_bbpu_alarm_status(void)
587{
588 u32 bbpu;
589 int ret;
590
591
592 if (apply_lpsd_solution) {
593 pr_notice("%s:lpsd\n", __func__);
594 return;
595 }
596
597 bbpu = RTC_BBPU_KEY | RTC_BBPU_PWREN | RTC_BBPU_RESET_AL;
598 rtc_write(RTC_BBPU, bbpu);
599 ret = rtc_write_trigger();
600 if (ret < 0)
601 pr_err("%s error\n", __func__);
602
603 return;
604
605}
606
607static irqreturn_t mtk_rtc_irq_handler(int irq, void *data)
608{
609 bool pwron_alm = false, isAlarmIrq = false, pwron_alarm = false;
610 struct rtc_time nowtm, tm;
611 unsigned long flags;
612
613 pr_notice("%s\n", __func__);
614
615 spin_lock_irqsave(&mt_rtc->lock, flags);
616 isAlarmIrq = mtk_rtc_is_alarm_irq();
617 if (!isAlarmIrq) {
618 spin_unlock_irqrestore(&mt_rtc->lock, flags);
619 return IRQ_HANDLED;
620 }
621
622 mtk_rtc_reset_bbpu_alarm_status();
623 spin_unlock_irqrestore(&mt_rtc->lock, flags);
624
625 if (mt_rtc->rtc_dev != NULL)
626 rtc_update_irq(mt_rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
627
628 if (rtc_show_alarm)
629 pr_notice("%s time is up\n", pwron_alm ? "power-on" : "alarm");
630
631 return IRQ_NONE;
632}
633
634static int rtc_ops_read_time(struct device *dev, struct rtc_time *tm)
635{
636 unsigned long long time;
637 unsigned long flags;
638 struct mt6358_rtc *rtc = dev_get_drvdata(dev);
639 int ret;
640
641 spin_lock_irqsave(&rtc->lock, flags);
642 ret = mtk_rtc_read_time(tm);
643 if (ret < 0)
644 goto exit;
645 spin_unlock_irqrestore(&rtc->lock, flags);
646
647 tm->tm_year += RTC_MIN_YEAR_OFFSET;
648 tm->tm_mon--;
649 time = rtc_tm_to_time64(tm);
650
651 do_div(time, 86400);
652 time += 4;
653 tm->tm_wday = do_div(time, 7); /* 1970/01/01 is Thursday */
654
655 if (rtc_show_time) {
656 pr_notice("read tc time = %04d/%02d/%02d (%d) %02d:%02d:%02d\n",
657 tm->tm_year + RTC_BASE_YEAR, tm->tm_mon + 1,
658 tm->tm_mday, tm->tm_wday, tm->tm_hour,
659 tm->tm_min, tm->tm_sec);
660 }
661
662 return ret;
663
664exit:
665 spin_unlock_irqrestore(&rtc->lock, flags);
666 pr_err("%s error\n", __func__);
667 return ret;
668}
669
670static int rtc_ops_set_time(struct device *dev, struct rtc_time *tm)
671{
672 struct mt6358_rtc *rtc = dev_get_drvdata(dev);
673 unsigned long flags;
674 u16 data[RTC_OFFSET_COUNT];
675 int ret;
676
677 if (tm->tm_year > 195) {
678 pr_err("%s: invalid year %04d > 2095\n",
679 __func__, tm->tm_year + RTC_BASE_YEAR);
680 return -EINVAL;
681 }
682
683 pr_notice("set tc time = %04d/%02d/%02d %02d:%02d:%02d\n",
684 tm->tm_year + RTC_BASE_YEAR, tm->tm_mon + 1, tm->tm_mday,
685 tm->tm_hour, tm->tm_min, tm->tm_sec);
686
687 tm->tm_year -= RTC_MIN_YEAR_OFFSET;
688 tm->tm_mon++;
689
690 data[RTC_OFFSET_SEC] = tm->tm_sec;
691 data[RTC_OFFSET_MIN] = tm->tm_min;
692 data[RTC_OFFSET_HOUR] = tm->tm_hour;
693 data[RTC_OFFSET_DOM] = tm->tm_mday;
694 data[RTC_OFFSET_MTH] = tm->tm_mon;
695 data[RTC_OFFSET_YEAR] = tm->tm_year;
696
697 spin_lock_irqsave(&rtc->lock, flags);
698 ret = rtc_bulk_access(BULK_WRITE, RTC_TC_SEC, data, RTC_OFFSET_COUNT);
699 if (ret < 0)
700 goto exit;
701
702 ret = rtc_write_trigger();
703 if (ret < 0)
704 goto exit;
705 spin_unlock_irqrestore(&rtc->lock, flags);
706
707 return ret;
708
709exit:
710 spin_unlock_irqrestore(&rtc->lock, flags);
711 pr_err("%s error\n", __func__);
712 return ret;
713}
714
715static int rtc_ops_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
716{
717 unsigned long flags;
718 struct rtc_time *tm = &alm->time;
719 struct mt6358_rtc *rtc = dev_get_drvdata(dev);
720 u32 irqen, pdn2;
721 u16 data[RTC_OFFSET_COUNT];
722 int ret;
723
724 spin_lock_irqsave(&rtc->lock, flags);
725
726 ret = rtc_read(RTC_IRQ_EN, &irqen);
727 if (ret < 0)
728 goto exit;
729 alm->enabled = !!(irqen & RTC_IRQ_EN_AL);
730
731 /* return Power-On Alarm bit */
732 ret = rtc_read(RTC_PDN2, &pdn2);
733 if (ret < 0)
734 goto exit;
735 alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM);
736
737 ret = rtc_bulk_access(BULK_READ, RTC_AL_SEC, data, RTC_OFFSET_COUNT);
738 if (ret < 0)
739 goto exit;
740
741 tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK;
742 tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK;
743 tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK;
744 tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK;
745 tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK;
746 tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK;
747
748 spin_unlock_irqrestore(&rtc->lock, flags);
749
750 tm->tm_year += RTC_MIN_YEAR_OFFSET;
751 tm->tm_mon--;
752
753 pr_notice("read al time = %04d/%02d/%02d %02d:%02d:%02d (%d)\n",
754 tm->tm_year + RTC_BASE_YEAR, tm->tm_mon + 1, tm->tm_mday,
755 tm->tm_hour, tm->tm_min, tm->tm_sec, alm->enabled);
756
757 return ret;
758
759exit:
760 spin_unlock_irqrestore(&rtc->lock, flags);
761 pr_err("%s error\n", __func__);
762 return ret;
763}
764
765static int rtc_ops_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
766{
767 unsigned long flags;
768 struct rtc_time tm = alm->time;
769 ktime_t target;
770 struct mt6358_rtc *rtc = dev_get_drvdata(dev);
771 u32 irqsta;
772 int ret = 0;
773
774 if (tm.tm_year > 195) {
775 pr_err("%s: invalid year %04d > 2095\n",
776 __func__, tm.tm_year + RTC_BASE_YEAR);
777 return -EINVAL;
778 }
779
780 if (alm->enabled == 1) {
781 /* Add one more second to postpone wake time. */
782 target = rtc_tm_to_ktime(tm);
783 target = ktime_add_ns(target, NSEC_PER_SEC);
784 tm = rtc_ktime_to_tm(target);
785 }
786
787 tm.tm_year -= RTC_MIN_YEAR_OFFSET;
788 tm.tm_mon++;
789
790 pr_notice("set al time = %04d/%02d/%02d %02d:%02d:%02d (%d)\n",
791 tm.tm_year + RTC_MIN_YEAR, tm.tm_mon, tm.tm_mday,
792 tm.tm_hour, tm.tm_min, tm.tm_sec, alm->enabled);
793
794 spin_lock_irqsave(&rtc->lock, flags);
795 if (alm->enabled == 2) { /* enable power-on alarm */
796 ret = mtk_rtc_set_pwron_alarm(true, &tm, false);
797 } else if (alm->enabled == 3) { /* enable power-on alarm with logo */
798 ret = mtk_rtc_set_pwron_alarm(true, &tm, true);
799 } else if (alm->enabled == 4) { /* disable power-on alarm */
800 ret = mtk_rtc_set_pwron_alarm(false, &tm, false);
801 }
802 if (ret < 0)
803 goto exit;
804
805 /* disable alarm and clear Power-On Alarm bit */
806 ret = rtc_update_bits(RTC_IRQ_EN, RTC_IRQ_EN_AL, 0);
807 if (ret < 0)
808 goto exit;
809 ret = rtc_update_bits(RTC_PDN2, RTC_PDN2_PWRON_ALARM, 0);
810 if (ret < 0)
811 goto exit;
812 ret = rtc_write_trigger();
813 if (ret < 0)
814 goto exit;
815 ret = rtc_read(RTC_IRQ_STA, &irqsta); /* read clear */
816 if (ret < 0)
817 goto exit;
818
819 if (alm->enabled)
820 ret = mtk_rtc_set_alarm(&tm);
821 spin_unlock_irqrestore(&rtc->lock, flags);
822
823 return ret;
824exit:
825 spin_unlock_irqrestore(&rtc->lock, flags);
826 pr_err("%s error\n", __func__);
827 return ret;
828}
829
830static const struct rtc_class_ops rtc_ops = {
831 .read_time = rtc_ops_read_time,
832 .set_time = rtc_ops_set_time,
833 .read_alarm = rtc_ops_read_alarm,
834 .set_alarm = rtc_ops_set_alarm,
835};
836
837static void mtk_rtc_set_lp_irq(void)
838{
839 unsigned int irqen = 0;
840 int ret;
841
842#ifndef USER_BUILD_KERNEL
843 irqen = RTC_IRQ_EN_LP;
844#endif
845 ret = rtc_update_bits(RTC_IRQ_EN, RTC_IRQ_EN_LP, irqen);
846 if (ret < 0)
847 goto exit;
848
849 ret = rtc_write_trigger();
850 if (ret < 0)
851 goto exit;
852
853 return;
854exit:
855 pr_err("%s error\n", __func__);
856}
857
858static int mtk_rtc_pdrv_probe(struct platform_device *pdev)
859{
860#ifndef IPIMB
861 struct mt6358_chip *mt6358_chip = dev_get_drvdata(pdev->dev.parent);
862#endif
863 struct mt6358_rtc *rtc;
864 unsigned long flags;
865 int ret;
866
867 rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6358_rtc), GFP_KERNEL);
868 if (!rtc)
869 return -ENOMEM;
870
871 rtc->irq = platform_get_irq(pdev, 0);
872 if (rtc->irq <= 0)
873 return -EINVAL;
874 pr_notice("%s: rtc->irq = %d(%d)\n", __func__, rtc->irq,
875 platform_get_irq_byname(pdev, "rtc"));
876
877#ifndef IPIMB
878 rtc->regmap = mt6358_chip->regmap;
879#else
880 rtc->regmap = dev_get_regmap(pdev->dev.parent->parent, NULL);
881#endif
882 if (!rtc->regmap) {
883 pr_err("%s: get regmap failed\n", __func__);
884 return -ENODEV;
885 }
886
887 rtc->dev = &pdev->dev;
888 spin_lock_init(&rtc->lock);
889
890 mt_rtc = rtc;
891 platform_set_drvdata(pdev, rtc);
892
893 if (of_property_read_u32(pdev->dev.of_node, "base", &rtc->addr_base))
894 rtc->addr_base = RTC_DSN_ID;
895 pr_notice("%s: rtc->addr_base =0x%x\n", __func__, rtc->addr_base);
896
897 spin_lock_irqsave(&rtc->lock, flags);
898 mtk_rtc_set_lp_irq();
899 spin_unlock_irqrestore(&rtc->lock, flags);
900
901 ret = request_threaded_irq(rtc->irq, NULL,
902 mtk_rtc_irq_handler,
903 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
904 "mt6358-rtc", rtc);
905 if (ret) {
906 dev_dbg(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
907 rtc->irq, ret);
908 goto out_dispose_irq;
909 }
910
911 device_init_wakeup(&pdev->dev, 1);
912
913 /* register rtc device (/dev/rtc0) */
914 rtc->rtc_dev = rtc_device_register(RTC_NAME,
915 &pdev->dev, &rtc_ops, THIS_MODULE);
916 if (IS_ERR(rtc->rtc_dev)) {
917 dev_dbg(&pdev->dev, "register rtc device failed\n");
918 ret = PTR_ERR(rtc->rtc_dev);
919 goto out_free_irq;
920 }
921
922 if (of_property_read_bool(pdev->dev.of_node, "apply-lpsd-solution")) {
923 apply_lpsd_solution = 1;
924 pr_notice("%s: apply_lpsd_solution\n", __func__);
925 }
926
927#ifdef CONFIG_PM
928 if (register_pm_notifier(&rtc_pm_notifier_func))
929 pr_notice("rtc pm failed\n");
930 else
931 rtc_pm_notifier_registered = true;
932#endif /* CONFIG_PM */
933 return 0;
934out_free_irq:
935 free_irq(rtc->irq, rtc->rtc_dev);
936out_dispose_irq:
937 irq_dispose_mapping(rtc->irq);
938 return ret;
939}
940
941static int mtk_rtc_pdrv_remove(struct platform_device *pdev)
942{
943 struct mt6358_rtc *rtc = platform_get_drvdata(pdev);
944
945 rtc_device_unregister(rtc->rtc_dev);
946
947 return 0;
948}
949
950static const struct of_device_id mt6358_rtc_of_match[] = {
951 { .compatible = "mediatek,mt6358-rtc", },
952 { .compatible = "mediatek,mt6359-rtc", },
953 { .compatible = "mediatek,mt6389-rtc", },
954 { }
955};
956MODULE_DEVICE_TABLE(of, mt6358_rtc_of_match);
957
958static struct platform_driver mtk_rtc_pdrv = {
959 .probe = mtk_rtc_pdrv_probe,
960 .remove = mtk_rtc_pdrv_remove,
961 .driver = {
962 .name = RTC_NAME,
963 .owner = THIS_MODULE,
964 .of_match_table = mt6358_rtc_of_match,
965 },
966};
967
968module_platform_driver(mtk_rtc_pdrv);
969
970
971MODULE_LICENSE("GPL v2");
972MODULE_AUTHOR("Wilma Wu <wilma.wu@mediatek.com>");
973MODULE_DESCRIPTION("RTC Driver for MediaTek MT6358 PMIC");