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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / kernel / linux / v4.14 / drivers / soc / mediatek / mtk-pmic-wrap.c
blob: d14f13b70a248642c9194ecdcad32fdf428ae3d0 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <linux/clk.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/reset.h>
23#include <linux/sched/clock.h>
24/* TBD #include <mt-plat/aee.h> */
25
26#define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
27#define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
28#define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
29#define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
30#define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
31#define PWRAP_MT8135_BRIDGE_INT_EN 0x38
32#define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
33#define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
34#define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
35
36/* macro for wrapper status */
37#define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
38#define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
39#define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
40#define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
41/* MT3967 and later should be (1 << 22) */
42#define PWRAP_STATE_INIT_DONE0 (1 << 21)
43
44/* macro for WACS FSM */
45#define PWRAP_WACS_FSM_IDLE 0x00
46#define PWRAP_WACS_FSM_REQ 0x02
47#define PWRAP_WACS_FSM_WFDLE 0x04
48#define PWRAP_WACS_FSM_WFVLDCLR 0x06
49#define PWRAP_WACS_INIT_DONE 0x01
50#define PWRAP_WACS_WACS_SYNC_IDLE 0x01
51#define PWRAP_WACS_SYNC_BUSY 0x00
52
53/* macro for device wrapper default value */
54#define PWRAP_DEW_READ_TEST_VAL 0x5aa5
55#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
56
57/* macro for manual command */
58#define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
59#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
60#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
61#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
62#define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
63#define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
64#define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
65#define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
66
67/* macro for Watch Dog Timer Source */
68#define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)
69#define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)
70#define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)
71#define PWRAP_WDT_SRC_MASK_ALL 0xffffffff
72#define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
73 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
74 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
75
76/* Group of bits used for shown slave capability */
77#define PWRAP_SLV_CAP_SPI BIT(0)
78#define PWRAP_SLV_CAP_DUALIO BIT(1)
79#define PWRAP_SLV_CAP_SECURITY BIT(2)
80#define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
81
82/* Group of bits used for shown pwrap capability */
83#define PWRAP_CAP_BRIDGE BIT(0)
84#define PWRAP_CAP_RESET BIT(1)
85#define PWRAP_CAP_DCM BIT(2)
86#define PWRAP_CAP_PRIORITY_SEL BIT(3)
87#define PWRAP_CAP_INT1_EN BIT(4)
88#define PWRAP_CAP_WDT_SRC1 BIT(5)
89#define PWRAP_CAP_MON_V1 BIT(6)
90#define PWRAP_CAP_MON_V2 BIT(7)
91
92static char pwrap_log_buf[1280];
93
94/* defines for slave device wrapper registers */
95enum dew_regs {
96 PWRAP_DEW_BASE,
97 PWRAP_DEW_DIO_EN,
98 PWRAP_DEW_READ_TEST,
99 PWRAP_DEW_WRITE_TEST,
100 PWRAP_DEW_CRC_EN,
101 PWRAP_DEW_CRC_VAL,
102 PWRAP_DEW_MON_GRP_SEL,
103 PWRAP_DEW_CIPHER_KEY_SEL,
104 PWRAP_DEW_CIPHER_IV_SEL,
105 PWRAP_DEW_CIPHER_RDY,
106 PWRAP_DEW_CIPHER_MODE,
107 PWRAP_DEW_CIPHER_SWRST,
108
109 /* MT6397 only regs */
110 PWRAP_DEW_EVENT_OUT_EN,
111 PWRAP_DEW_EVENT_SRC_EN,
112 PWRAP_DEW_EVENT_SRC,
113 PWRAP_DEW_EVENT_FLAG,
114 PWRAP_DEW_MON_FLAG_SEL,
115 PWRAP_DEW_EVENT_TEST,
116 PWRAP_DEW_CIPHER_LOAD,
117 PWRAP_DEW_CIPHER_START,
118
119 /* MT6323 only regs */
120 PWRAP_DEW_CIPHER_EN,
121 PWRAP_DEW_RDDMY_NO,
122
123 /* MT6358 only regs */
124 PWRAP_SMT_CON1,
125 PWRAP_DRV_CON1,
126 PWRAP_FILTER_CON0,
127 PWRAP_GPIO_PULLEN0_CLR,
128 PWRAP_RG_SPI_CON0,
129 PWRAP_RG_SPI_RECORD0,
130 PWRAP_RG_SPI_CON2,
131 PWRAP_RG_SPI_CON3,
132 PWRAP_RG_SPI_CON4,
133 PWRAP_RG_SPI_CON5,
134 PWRAP_RG_SPI_CON6,
135 PWRAP_RG_SPI_CON7,
136 PWRAP_RG_SPI_CON8,
137 PWRAP_RG_SPI_CON13,
138 PWRAP_SPISLV_KEY,
139
140 PWRAP_DEW_CRC_SWRST,
141 PWRAP_DEW_RG_EN_RECORD,
142 PWRAP_DEW_RECORD_CMD0,
143 PWRAP_DEW_RECORD_CMD1,
144 PWRAP_DEW_RECORD_CMD2,
145 PWRAP_DEW_RECORD_CMD3,
146 PWRAP_DEW_RECORD_CMD4,
147 PWRAP_DEW_RECORD_CMD5,
148 PWRAP_DEW_RECORD_WDATA0,
149 PWRAP_DEW_RECORD_WDATA1,
150 PWRAP_DEW_RECORD_WDATA2,
151 PWRAP_DEW_RECORD_WDATA3,
152 PWRAP_DEW_RECORD_WDATA4,
153 PWRAP_DEW_RECORD_WDATA5,
154 PWRAP_DEW_RG_ADDR_TARGET,
155 PWRAP_DEW_RG_ADDR_MASK,
156 PWRAP_DEW_RG_WDATA_TARGET,
157 PWRAP_DEW_RG_WDATA_MASK,
158 PWRAP_DEW_RG_SPI_RECORD_CLR,
159 PWRAP_DEW_RG_CMD_ALERT_CLR,
160 PWRAP_DEW_SPISLV_KEY,
161};
162
163static const u32 mt6323_regs[] = {
164 [PWRAP_DEW_BASE] = 0x0000,
165 [PWRAP_DEW_DIO_EN] = 0x018a,
166 [PWRAP_DEW_READ_TEST] = 0x018c,
167 [PWRAP_DEW_WRITE_TEST] = 0x018e,
168 [PWRAP_DEW_CRC_EN] = 0x0192,
169 [PWRAP_DEW_CRC_VAL] = 0x0194,
170 [PWRAP_DEW_MON_GRP_SEL] = 0x0196,
171 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,
172 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
173 [PWRAP_DEW_CIPHER_EN] = 0x019c,
174 [PWRAP_DEW_CIPHER_RDY] = 0x019e,
175 [PWRAP_DEW_CIPHER_MODE] = 0x01a0,
176 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2,
177 [PWRAP_DEW_RDDMY_NO] = 0x01a4,
178};
179
180static const u32 mt6356_regs[] = {
181 [PWRAP_SMT_CON1] = 0x002e,
182 [PWRAP_DRV_CON1] = 0x0036,
183 [PWRAP_FILTER_CON0] = 0x003c,
184 [PWRAP_GPIO_PULLEN0_CLR] = 0x0056,
185 [PWRAP_DEW_RG_EN_RECORD] = 0x0246,
186 [PWRAP_DEW_DIO_EN] = 0x0248,
187 [PWRAP_DEW_READ_TEST] = 0x024a,
188 [PWRAP_DEW_WRITE_TEST] = 0x024c,
189 [PWRAP_DEW_CRC_EN] = 0x0250,
190 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0256,
191 [PWRAP_DEW_CIPHER_IV_SEL] = 0x0258,
192 [PWRAP_DEW_CIPHER_EN] = 0x025a,
193 [PWRAP_DEW_CIPHER_RDY] = 0x025c,
194 [PWRAP_DEW_CIPHER_MODE] = 0x025e,
195 [PWRAP_DEW_CIPHER_SWRST] = 0x0260,
196 [PWRAP_RG_SPI_CON2] = 0x0292,
197 [PWRAP_DEW_RECORD_CMD0] = 0x0294,
198 [PWRAP_DEW_RECORD_CMD1] = 0x0296,
199 [PWRAP_DEW_RECORD_CMD2] = 0x0298,
200 [PWRAP_DEW_RECORD_WDATA0] = 0x029a,
201 [PWRAP_DEW_RECORD_WDATA1] = 0x029c,
202 [PWRAP_DEW_RECORD_WDATA2] = 0x029e,
203 [PWRAP_DEW_RG_ADDR_TARGET] = 0x02a0,
204 [PWRAP_DEW_RG_ADDR_MASK] = 0x02a2,
205 [PWRAP_DEW_RG_WDATA_TARGET] = 0x02a4,
206 [PWRAP_DEW_RG_WDATA_MASK] = 0x02a6,
207 [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x02a8,
208 [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x02a8,
209};
210
211static const u32 mt6358_regs[] = {
212 [PWRAP_SMT_CON1] = 0x0030,
213 [PWRAP_DRV_CON1] = 0x0038,
214 [PWRAP_FILTER_CON0] = 0x0040,
215 [PWRAP_GPIO_PULLEN0_CLR] = 0x0098,
216 [PWRAP_RG_SPI_CON0] = 0x0408,
217 [PWRAP_RG_SPI_RECORD0] = 0x040a,
218 [PWRAP_DEW_DIO_EN] = 0x040c,
219 [PWRAP_DEW_READ_TEST] = 0x040e,
220 [PWRAP_DEW_WRITE_TEST] = 0x0410,
221 [PWRAP_DEW_CRC_EN] = 0x0414,
222 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a,
223 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c,
224 [PWRAP_DEW_CIPHER_EN] = 0x041e,
225 [PWRAP_DEW_CIPHER_RDY] = 0x0420,
226 [PWRAP_DEW_CIPHER_MODE] = 0x0422,
227 [PWRAP_DEW_CIPHER_SWRST] = 0x0424,
228 [PWRAP_RG_SPI_CON2] = 0x0432,
229 [PWRAP_RG_SPI_CON3] = 0x0434,
230 [PWRAP_RG_SPI_CON4] = 0x0436,
231 [PWRAP_RG_SPI_CON5] = 0x0438,
232 [PWRAP_RG_SPI_CON6] = 0x043a,
233 [PWRAP_RG_SPI_CON7] = 0x043c,
234 [PWRAP_RG_SPI_CON8] = 0x043e,
235 [PWRAP_RG_SPI_CON13] = 0x0448,
236 [PWRAP_SPISLV_KEY] = 0x044a,
237};
238
239static const u32 mt6389_regs[] = {
240 [PWRAP_SMT_CON1] = 0x0032,
241 [PWRAP_DRV_CON1] = 0x003a,
242 [PWRAP_FILTER_CON0] = 0x0042,
243 [PWRAP_GPIO_PULLEN0_CLR] = 0x0098,
244 [PWRAP_DEW_RG_EN_RECORD] = 0x040a,
245 [PWRAP_DEW_DIO_EN] = 0x040c,
246 [PWRAP_DEW_READ_TEST] = 0x040e,
247 [PWRAP_DEW_WRITE_TEST] = 0x0410,
248 [PWRAP_DEW_CRC_EN] = 0x0414,
249 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
250 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a,
251 [PWRAP_DEW_CIPHER_EN] = 0x041c,
252 [PWRAP_DEW_CIPHER_RDY] = 0x041e,
253 [PWRAP_DEW_CIPHER_MODE] = 0x0420,
254 [PWRAP_DEW_CIPHER_SWRST] = 0x0422,
255 [PWRAP_RG_SPI_CON2] = 0x0426,
256 [PWRAP_DEW_RECORD_CMD0] = 0x0428,
257 [PWRAP_DEW_RECORD_CMD1] = 0x042a,
258 [PWRAP_DEW_RECORD_CMD2] = 0x042c,
259 [PWRAP_DEW_RECORD_WDATA0] = 0x0434,
260 [PWRAP_DEW_RECORD_WDATA1] = 0x0436,
261 [PWRAP_DEW_RECORD_WDATA2] = 0x0438,
262 [PWRAP_DEW_RG_ADDR_TARGET] = 0x0440,
263 [PWRAP_DEW_RG_ADDR_MASK] = 0x0442,
264 [PWRAP_DEW_RG_WDATA_TARGET] = 0x0444,
265 [PWRAP_DEW_RG_WDATA_MASK] = 0x0446,
266 [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,
267 [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448,
268};
269
270static const u32 mt6397_regs[] = {
271 [PWRAP_DEW_BASE] = 0xbc00,
272 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
273 [PWRAP_DEW_DIO_EN] = 0xbc02,
274 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
275 [PWRAP_DEW_EVENT_SRC] = 0xbc06,
276 [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
277 [PWRAP_DEW_READ_TEST] = 0xbc0a,
278 [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
279 [PWRAP_DEW_CRC_EN] = 0xbc0e,
280 [PWRAP_DEW_CRC_VAL] = 0xbc10,
281 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
282 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
283 [PWRAP_DEW_EVENT_TEST] = 0xbc16,
284 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
285 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
286 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
287 [PWRAP_DEW_CIPHER_START] = 0xbc1e,
288 [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
289 [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
290 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
291};
292
293enum pwrap_regs {
294 PWRAP_MUX_SEL,
295 PWRAP_WRAP_EN,
296 PWRAP_DIO_EN,
297 PWRAP_SIDLY,
298 PWRAP_CSHEXT_WRITE,
299 PWRAP_CSHEXT_READ,
300 PWRAP_CSLEXT_START,
301 PWRAP_CSLEXT_END,
302 PWRAP_STAUPD_PRD,
303 PWRAP_STAUPD_GRPEN,
304 PWRAP_STAUPD_MAN_TRIG,
305 PWRAP_STAUPD_STA,
306 PWRAP_WRAP_STA,
307 PWRAP_HARB_INIT,
308 PWRAP_HARB_HPRIO,
309 PWRAP_HIPRIO_ARB_EN,
310 PWRAP_HARB_STA0,
311 PWRAP_HARB_STA1,
312 PWRAP_MAN_EN,
313 PWRAP_MAN_CMD,
314 PWRAP_MAN_RDATA,
315 PWRAP_MAN_VLDCLR,
316 PWRAP_WACS0_EN,
317 PWRAP_INIT_DONE0,
318 PWRAP_WACS0_CMD,
319 PWRAP_WACS0_RDATA,
320 PWRAP_WACS0_VLDCLR,
321 PWRAP_WACS1_EN,
322 PWRAP_INIT_DONE1,
323 PWRAP_WACS1_CMD,
324 PWRAP_WACS1_RDATA,
325 PWRAP_WACS1_VLDCLR,
326 PWRAP_WACS2_EN,
327 PWRAP_INIT_DONE2,
328 PWRAP_WACS2_CMD,
329 PWRAP_WACS2_RDATA,
330 PWRAP_WACS2_VLDCLR,
331 PWRAP_WACS3_EN,
332 PWRAP_INIT_DONE3,
333 PWRAP_WACS3_CMD,
334 PWRAP_WACS3_RDATA,
335 PWRAP_WACS3_VLDCLR,
336 PWRAP_INT_EN,
337 PWRAP_INT_FLG_RAW,
338 PWRAP_INT_FLG,
339 PWRAP_INT_CLR,
340 PWRAP_SIG_ADR,
341 PWRAP_SIG_MODE,
342 PWRAP_SIG_VALUE,
343 PWRAP_SIG_ERRVAL,
344 PWRAP_CRC_EN,
345 PWRAP_TIMER_EN,
346 PWRAP_TIMER_STA,
347 PWRAP_WDT_UNIT,
348 PWRAP_WDT_SRC_EN,
349 PWRAP_WDT_FLG,
350 PWRAP_DEBUG_INT_SEL,
351 PWRAP_CIPHER_KEY_SEL,
352 PWRAP_CIPHER_IV_SEL,
353 PWRAP_CIPHER_RDY,
354 PWRAP_CIPHER_MODE,
355 PWRAP_CIPHER_SWRST,
356 PWRAP_DCM_EN,
357 PWRAP_DCM_DBC_PRD,
358
359 /* MT2701 only regs */
360 PWRAP_ADC_CMD_ADDR,
361 PWRAP_PWRAP_ADC_CMD,
362 PWRAP_ADC_RDY_ADDR,
363 PWRAP_ADC_RDATA_ADDR1,
364 PWRAP_ADC_RDATA_ADDR2,
365
366 /* MT7622 only regs */
367 PWRAP_STA,
368 PWRAP_CLR,
369 PWRAP_DVFS_ADR8,
370 PWRAP_DVFS_WDATA8,
371 PWRAP_DVFS_ADR9,
372 PWRAP_DVFS_WDATA9,
373 PWRAP_DVFS_ADR10,
374 PWRAP_DVFS_WDATA10,
375 PWRAP_DVFS_ADR11,
376 PWRAP_DVFS_WDATA11,
377 PWRAP_DVFS_ADR12,
378 PWRAP_DVFS_WDATA12,
379 PWRAP_DVFS_ADR13,
380 PWRAP_DVFS_WDATA13,
381 PWRAP_DVFS_ADR14,
382 PWRAP_DVFS_WDATA14,
383 PWRAP_DVFS_ADR15,
384 PWRAP_DVFS_WDATA15,
385 PWRAP_EXT_CK,
386 PWRAP_ADC_RDATA_ADDR,
387 PWRAP_GPS_STA,
388 PWRAP_SW_RST,
389 PWRAP_DVFS_STEP_CTRL0,
390 PWRAP_DVFS_STEP_CTRL1,
391 PWRAP_DVFS_STEP_CTRL2,
392 PWRAP_SPI2_CTRL,
393
394 /* MT8135 only regs */
395 PWRAP_CSHEXT,
396 PWRAP_EVENT_IN_EN,
397 PWRAP_EVENT_DST_EN,
398 PWRAP_RRARB_INIT,
399 PWRAP_RRARB_EN,
400 PWRAP_RRARB_STA0,
401 PWRAP_RRARB_STA1,
402 PWRAP_EVENT_STA,
403 PWRAP_EVENT_STACLR,
404 PWRAP_CIPHER_LOAD,
405 PWRAP_CIPHER_START,
406
407 /* MT8173 only regs */
408 PWRAP_RDDMY,
409 PWRAP_SI_CK_CON,
410 PWRAP_DVFS_ADR0,
411 PWRAP_DVFS_WDATA0,
412 PWRAP_DVFS_ADR1,
413 PWRAP_DVFS_WDATA1,
414 PWRAP_DVFS_ADR2,
415 PWRAP_DVFS_WDATA2,
416 PWRAP_DVFS_ADR3,
417 PWRAP_DVFS_WDATA3,
418 PWRAP_DVFS_ADR4,
419 PWRAP_DVFS_WDATA4,
420 PWRAP_DVFS_ADR5,
421 PWRAP_DVFS_WDATA5,
422 PWRAP_DVFS_ADR6,
423 PWRAP_DVFS_WDATA6,
424 PWRAP_DVFS_ADR7,
425 PWRAP_DVFS_WDATA7,
426 PWRAP_SPMINF_STA,
427 PWRAP_CIPHER_EN,
428
429 /* MT8183 only regs */
430 PWRAP_SI_SAMPLE_CTRL,
431 PWRAP_CSLEXT_WRITE,
432 PWRAP_CSLEXT_READ,
433 PWRAP_EXT_CK_WRITE,
434 PWRAP_STAUPD_CTRL,
435 PWRAP_WACS_P2P_EN,
436 PWRAP_INIT_DONE_P2P,
437 PWRAP_WACS_MD32_EN,
438 PWRAP_INIT_DONE_MD32,
439 PWRAP_INT0_EN,
440 PWRAP_INT0_FLG_RAW,
441 PWRAP_INT0_FLG,
442 PWRAP_INT0_CLR,
443 PWRAP_INT1_EN,
444 PWRAP_INT1_FLG_RAW,
445 PWRAP_INT1_FLG,
446 PWRAP_INT1_CLR,
447 PWRAP_EINT_STA0_ADR,
448 PWRAP_EINT_STA1_ADR,
449
450 PWRAP_EINT_STA,
451 PWRAP_EINT_CLR,
452 PWRAP_HPRIO_ARB_EN,
453 PWRAP_WDT_SRC_EN_1,
454 PWRAP_WDT_FLG_1,
455 PWRAP_INT_GPS_AUXADC_CMD_ADDR,
456 PWRAP_INT_GPS_AUXADC_CMD,
457 PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
458 PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
459 PWRAP_DCXO_CONN_ADR0,
460 PWRAP_DCXO_CONN_WDATA0,
461 PWRAP_DCXO_CONN_ADR1,
462 PWRAP_DCXO_CONN_WDATA1,
463 PWRAP_DCXO_NFC_ADR0,
464 PWRAP_DCXO_NFC_WDATA0,
465 PWRAP_DCXO_NFC_ADR1,
466 PWRAP_DCXO_NFC_WDATA1,
467 PWRAP_SPMINF_STA_1,
468 PWRAP_SPMINF_BACKUP_STA,
469 PWRAP_SCPINF_STA,
470 PWRAP_SRCLKEN_RCINF_STA_0,
471 PWRAP_SRCLKEN_RCINF_STA_1,
472 PWRAP_CONNINF_STA_0,
473 PWRAP_CONNINF_STA_1,
474 PWRAP_MCU_PMINF_STA_0,
475 PWRAP_MCU_PMINF_STA_1,
476 PWRAP_GPSINF_0_STA,
477 PWRAP_GPSINF_1_STA,
478 PWRAP_MD_ADCINF_0_STA_0,
479 PWRAP_MD_ADCINF_0_STA_1,
480 PWRAP_MD_ADCINF_1_STA_0,
481 PWRAP_MD_ADCINF_1_STA_1,
482 PWRAP_BUSY_STA,
483 PWRAP_BUSY_STA_LATCHED_WDT,
484 PWRAP_PRIORITY_USER_SEL_0,
485 PWRAP_PRIORITY_USER_SEL_1,
486 PWRAP_ARBITER_OUT_SEL_0,
487 PWRAP_ARBITER_OUT_SEL_1,
488 PWRAP_MD_AUXADC_RDATA_LATEST_ADDR,
489 PWRAP_MD_AUXADC_RDATA_WP_ADDR,
490 PWRAP_MD_AUXADC_RDATA_0_ADDR,
491 PWRAP_MD_AUXADC_RDATA_1_ADDR,
492 PWRAP_MD_AUXADC_RDATA_2_ADDR,
493 PWRAP_MD_AUXADC_RDATA_3_ADDR,
494 PWRAP_MD_AUXADC_RDATA_4_ADDR,
495 PWRAP_MD_AUXADC_RDATA_5_ADDR,
496 PWRAP_MD_AUXADC_RDATA_6_ADDR,
497 PWRAP_MD_AUXADC_RDATA_7_ADDR,
498 PWRAP_MD_AUXADC_RDATA_8_ADDR,
499 PWRAP_MD_AUXADC_RDATA_9_ADDR,
500 PWRAP_MD_AUXADC_RDATA_10_ADDR,
501 PWRAP_MD_AUXADC_RDATA_11_ADDR,
502 PWRAP_MD_AUXADC_RDATA_12_ADDR,
503 PWRAP_MD_AUXADC_RDATA_13_ADDR,
504 PWRAP_MD_AUXADC_RDATA_14_ADDR,
505 PWRAP_MD_AUXADC_RDATA_15_ADDR,
506 PWRAP_MD_AUXADC_RDATA_16_ADDR,
507 PWRAP_MD_AUXADC_RDATA_17_ADDR,
508 PWRAP_MD_AUXADC_RDATA_18_ADDR,
509 PWRAP_MD_AUXADC_RDATA_19_ADDR,
510 PWRAP_MD_AUXADC_RDATA_20_ADDR,
511 PWRAP_MD_AUXADC_RDATA_21_ADDR,
512 PWRAP_MD_AUXADC_RDATA_22_ADDR,
513 PWRAP_MD_AUXADC_RDATA_23_ADDR,
514 PWRAP_MD_AUXADC_RDATA_24_ADDR,
515 PWRAP_MD_AUXADC_RDATA_25_ADDR,
516 PWRAP_MD_AUXADC_RDATA_26_ADDR,
517 PWRAP_MD_AUXADC_RDATA_27_ADDR,
518 PWRAP_MD_AUXADC_RDATA_28_ADDR,
519 PWRAP_MD_AUXADC_RDATA_29_ADDR,
520 PWRAP_MD_AUXADC_RDATA_30_ADDR,
521 PWRAP_MD_AUXADC_RDATA_31_ADDR,
522 PWRAP_PRIORITY_USER_SEL_2,
523 PWRAP_ARBITER_OUT_SEL_2,
524 PWRAP_STARV_COUNTER_0,
525 PWRAP_STARV_COUNTER_1,
526 PWRAP_STARV_COUNTER_2,
527 PWRAP_STARV_COUNTER_3,
528 PWRAP_STARV_COUNTER_4,
529 PWRAP_STARV_COUNTER_5,
530 PWRAP_STARV_COUNTER_6,
531 PWRAP_STARV_COUNTER_7,
532 PWRAP_STARV_COUNTER_8,
533 PWRAP_STARV_COUNTER_9,
534 PWRAP_STARV_COUNTER_10,
535 PWRAP_STARV_COUNTER_11,
536 PWRAP_STARV_COUNTER_12,
537 PWRAP_STARV_COUNTER_13,
538 PWRAP_STARV_COUNTER_14,
539 PWRAP_STARV_COUNTER_15,
540 PWRAP_STARV_COUNTER_16,
541 PWRAP_MONITOR_CTRL_0,
542 PWRAP_MONITOR_CTRL_1,
543 PWRAP_MONITOR_CTRL_2,
544 PWRAP_MONITOR_CTRL_3,
545 PWRAP_CHANNEL_SEQUENCE_0,
546 PWRAP_CHANNEL_SEQUENCE_1,
547 PWRAP_CHANNEL_SEQUENCE_2,
548 PWRAP_CHANNEL_SEQUENCE_3,
549 PWRAP_CHANNEL_SEQUENCE_4,
550 PWRAP_CHANNEL_SEQUENCE_5,
551 PWRAP_CHANNEL_SEQUENCE_6,
552 PWRAP_CHANNEL_SEQUENCE_7,
553 PWRAP_WRITE_SEQUENCE,
554 PWRAP_CMD_SEQUENCE_0,
555 PWRAP_CMD_SEQUENCE_1,
556 PWRAP_CMD_SEQUENCE_2,
557 PWRAP_CMD_SEQUENCE_3,
558 PWRAP_CMD_SEQUENCE_4,
559 PWRAP_CMD_SEQUENCE_5,
560 PWRAP_CMD_SEQUENCE_6,
561 PWRAP_CMD_SEQUENCE_7,
562 PWRAP_CMD_SEQUENCE_8,
563 PWRAP_CMD_SEQUENCE_9,
564 PWRAP_CMD_SEQUENCE_10,
565 PWRAP_CMD_SEQUENCE_11,
566 PWRAP_CMD_SEQUENCE_12,
567 PWRAP_CMD_SEQUENCE_13,
568 PWRAP_CMD_SEQUENCE_14,
569 PWRAP_CMD_SEQUENCE_15,
570 PWRAP_WDATA_SEQUENCE_0,
571 PWRAP_WDATA_SEQUENCE_1,
572 PWRAP_WDATA_SEQUENCE_2,
573 PWRAP_WDATA_SEQUENCE_3,
574 PWRAP_WDATA_SEQUENCE_4,
575 PWRAP_WDATA_SEQUENCE_5,
576 PWRAP_WDATA_SEQUENCE_6,
577 PWRAP_WDATA_SEQUENCE_7,
578 PWRAP_WDATA_SEQUENCE_8,
579 PWRAP_WDATA_SEQUENCE_9,
580 PWRAP_WDATA_SEQUENCE_10,
581 PWRAP_WDATA_SEQUENCE_11,
582 PWRAP_WDATA_SEQUENCE_12,
583 PWRAP_WDATA_SEQUENCE_13,
584 PWRAP_WDATA_SEQUENCE_14,
585 PWRAP_WDATA_SEQUENCE_15,
586
587 /* MPU regs */
588 PWRAP_MPU_PMIC_ACC_VIO_INFO_0,
589 PWRAP_MPU_PMIC_ACC_VIO_INFO_1,
590 PWRAP_MPU_PMIC_ACC_VIO_INFO_2,
591 PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_0,
592 PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_1,
593 PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_2,
594 PWRAP_MPU_PWRAP_ACC_VIO_INFO_0,
595 PWRAP_MPU_PWRAP_ACC_VIO_INFO_1,
596
597};
598
599static int mt2701_regs[] = {
600 [PWRAP_MUX_SEL] = 0x0,
601 [PWRAP_WRAP_EN] = 0x4,
602 [PWRAP_DIO_EN] = 0x8,
603 [PWRAP_SIDLY] = 0xc,
604 [PWRAP_RDDMY] = 0x18,
605 [PWRAP_SI_CK_CON] = 0x1c,
606 [PWRAP_CSHEXT_WRITE] = 0x20,
607 [PWRAP_CSHEXT_READ] = 0x24,
608 [PWRAP_CSLEXT_START] = 0x28,
609 [PWRAP_CSLEXT_END] = 0x2c,
610 [PWRAP_STAUPD_PRD] = 0x30,
611 [PWRAP_STAUPD_GRPEN] = 0x34,
612 [PWRAP_STAUPD_MAN_TRIG] = 0x38,
613 [PWRAP_STAUPD_STA] = 0x3c,
614 [PWRAP_WRAP_STA] = 0x44,
615 [PWRAP_HARB_INIT] = 0x48,
616 [PWRAP_HARB_HPRIO] = 0x4c,
617 [PWRAP_HIPRIO_ARB_EN] = 0x50,
618 [PWRAP_HARB_STA0] = 0x54,
619 [PWRAP_HARB_STA1] = 0x58,
620 [PWRAP_MAN_EN] = 0x5c,
621 [PWRAP_MAN_CMD] = 0x60,
622 [PWRAP_MAN_RDATA] = 0x64,
623 [PWRAP_MAN_VLDCLR] = 0x68,
624 [PWRAP_WACS0_EN] = 0x6c,
625 [PWRAP_INIT_DONE0] = 0x70,
626 [PWRAP_WACS0_CMD] = 0x74,
627 [PWRAP_WACS0_RDATA] = 0x78,
628 [PWRAP_WACS0_VLDCLR] = 0x7c,
629 [PWRAP_WACS1_EN] = 0x80,
630 [PWRAP_INIT_DONE1] = 0x84,
631 [PWRAP_WACS1_CMD] = 0x88,
632 [PWRAP_WACS1_RDATA] = 0x8c,
633 [PWRAP_WACS1_VLDCLR] = 0x90,
634 [PWRAP_WACS2_EN] = 0x94,
635 [PWRAP_INIT_DONE2] = 0x98,
636 [PWRAP_WACS2_CMD] = 0x9c,
637 [PWRAP_WACS2_RDATA] = 0xa0,
638 [PWRAP_WACS2_VLDCLR] = 0xa4,
639 [PWRAP_INT_EN] = 0xa8,
640 [PWRAP_INT_FLG_RAW] = 0xac,
641 [PWRAP_INT_FLG] = 0xb0,
642 [PWRAP_INT_CLR] = 0xb4,
643 [PWRAP_SIG_ADR] = 0xb8,
644 [PWRAP_SIG_MODE] = 0xbc,
645 [PWRAP_SIG_VALUE] = 0xc0,
646 [PWRAP_SIG_ERRVAL] = 0xc4,
647 [PWRAP_CRC_EN] = 0xc8,
648 [PWRAP_TIMER_EN] = 0xcc,
649 [PWRAP_TIMER_STA] = 0xd0,
650 [PWRAP_WDT_UNIT] = 0xd4,
651 [PWRAP_WDT_SRC_EN] = 0xd8,
652 [PWRAP_WDT_FLG] = 0xdc,
653 [PWRAP_DEBUG_INT_SEL] = 0xe0,
654 [PWRAP_DVFS_ADR0] = 0xe4,
655 [PWRAP_DVFS_WDATA0] = 0xe8,
656 [PWRAP_DVFS_ADR1] = 0xec,
657 [PWRAP_DVFS_WDATA1] = 0xf0,
658 [PWRAP_DVFS_ADR2] = 0xf4,
659 [PWRAP_DVFS_WDATA2] = 0xf8,
660 [PWRAP_DVFS_ADR3] = 0xfc,
661 [PWRAP_DVFS_WDATA3] = 0x100,
662 [PWRAP_DVFS_ADR4] = 0x104,
663 [PWRAP_DVFS_WDATA4] = 0x108,
664 [PWRAP_DVFS_ADR5] = 0x10c,
665 [PWRAP_DVFS_WDATA5] = 0x110,
666 [PWRAP_DVFS_ADR6] = 0x114,
667 [PWRAP_DVFS_WDATA6] = 0x118,
668 [PWRAP_DVFS_ADR7] = 0x11c,
669 [PWRAP_DVFS_WDATA7] = 0x120,
670 [PWRAP_CIPHER_KEY_SEL] = 0x124,
671 [PWRAP_CIPHER_IV_SEL] = 0x128,
672 [PWRAP_CIPHER_EN] = 0x12c,
673 [PWRAP_CIPHER_RDY] = 0x130,
674 [PWRAP_CIPHER_MODE] = 0x134,
675 [PWRAP_CIPHER_SWRST] = 0x138,
676 [PWRAP_DCM_EN] = 0x13c,
677 [PWRAP_DCM_DBC_PRD] = 0x140,
678 [PWRAP_ADC_CMD_ADDR] = 0x144,
679 [PWRAP_PWRAP_ADC_CMD] = 0x148,
680 [PWRAP_ADC_RDY_ADDR] = 0x14c,
681 [PWRAP_ADC_RDATA_ADDR1] = 0x150,
682 [PWRAP_ADC_RDATA_ADDR2] = 0x154,
683};
684
685static int mt2731_regs[] = {
686 [PWRAP_MUX_SEL] = 0x0,
687 [PWRAP_WRAP_EN] = 0x4,
688 [PWRAP_DIO_EN] = 0x8,
689 [PWRAP_SI_SAMPLE_CTRL] = 0xC,
690 [PWRAP_RDDMY] = 0x20,
691 [PWRAP_CSHEXT_WRITE] = 0x24,
692 [PWRAP_CSHEXT_READ] = 0x28,
693 [PWRAP_CSLEXT_WRITE] = 0x2C,
694 [PWRAP_CSLEXT_READ] = 0x30,
695 [PWRAP_EXT_CK_WRITE] = 0x34,
696 [PWRAP_STAUPD_CTRL] = 0x3C,
697 [PWRAP_STAUPD_GRPEN] = 0x40,
698 [PWRAP_EINT_STA0_ADR] = 0x44,
699 [PWRAP_HARB_HPRIO] = 0x68,
700 [PWRAP_HIPRIO_ARB_EN] = 0x6C,
701 [PWRAP_MAN_EN] = 0x7C,
702 [PWRAP_MAN_CMD] = 0x80,
703 [PWRAP_WACS0_EN] = 0x8C,
704 [PWRAP_INIT_DONE0] = 0x90,
705 [PWRAP_WACS1_EN] = 0x94,
706 [PWRAP_INIT_DONE1] = 0x98,
707 [PWRAP_WACS2_EN] = 0x9C,
708 [PWRAP_INIT_DONE2] = 0xA0,
709 [PWRAP_WACS_P2P_EN] = 0xA4,
710 [PWRAP_INIT_DONE_P2P] = 0xA8,
711 [PWRAP_WACS_MD32_EN] = 0xAC,
712 [PWRAP_INIT_DONE_MD32] = 0xB0,
713 [PWRAP_INT_EN] = 0xB4,
714 [PWRAP_INT_FLG] = 0xBC,
715 [PWRAP_INT_CLR] = 0xC0,
716 [PWRAP_INT0_EN] = 0xB4,
717 [PWRAP_INT0_FLG] = 0xBC,
718 [PWRAP_INT0_CLR] = 0xC0,
719 [PWRAP_INT1_EN] = 0xC4,
720 [PWRAP_INT1_FLG] = 0xCC,
721 [PWRAP_INT1_CLR] = 0xD0,
722 [PWRAP_SIG_ADR] = 0xD4,
723 [PWRAP_CRC_EN] = 0xE4,
724 [PWRAP_TIMER_EN] = 0xE8,
725 [PWRAP_WDT_UNIT] = 0xF0,
726 [PWRAP_WDT_SRC_EN] = 0xF4,
727 [PWRAP_WDT_SRC_EN_1] = 0xF8,
728 [PWRAP_DCXO_CONN_ADR0] = 0x18C,
729 [PWRAP_DCXO_CONN_WDATA0] = 0x190,
730 [PWRAP_DCXO_CONN_ADR1] = 0x194,
731 [PWRAP_DCXO_CONN_WDATA1] = 0x198,
732 [PWRAP_DCXO_NFC_ADR0] = 0x19C,
733 [PWRAP_DCXO_NFC_WDATA0] = 0x1A0,
734 [PWRAP_DCXO_NFC_ADR1] = 0x1A4,
735 [PWRAP_DCXO_NFC_WDATA1] = 0x1A8,
736 [PWRAP_SPMINF_STA] = 0x1AC,
737 [PWRAP_SPMINF_STA_1] = 0x1B0,
738 [PWRAP_SPMINF_BACKUP_STA] = 0x1B4,
739 [PWRAP_MCU_PMINF_STA_0] = 0x1B8,
740 [PWRAP_MCU_PMINF_STA_1] = 0x1BC,
741 [PWRAP_SCPINF_STA] = 0x1C0,
742 [PWRAP_DCM_EN] = 0x1DC,
743 [PWRAP_DCM_DBC_PRD] = 0x1E0,
744 [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1E4,
745 [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E8,
746 [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1EC,
747 [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1F0,
748 [PWRAP_GPSINF_0_STA] = 0x1F4,
749 [PWRAP_GPSINF_1_STA] = 0x1F8,
750 [PWRAP_MD_AUXADC_RDATA_LATEST_ADDR] = 0x200,
751 [PWRAP_MD_AUXADC_RDATA_WP_ADDR] = 0x204,
752 [PWRAP_MD_AUXADC_RDATA_0_ADDR] = 0x208,
753 [PWRAP_MD_AUXADC_RDATA_1_ADDR] = 0x20C,
754 [PWRAP_MD_AUXADC_RDATA_2_ADDR] = 0x210,
755 [PWRAP_MD_AUXADC_RDATA_3_ADDR] = 0x214,
756 [PWRAP_MD_AUXADC_RDATA_4_ADDR] = 0x218,
757 [PWRAP_MD_AUXADC_RDATA_5_ADDR] = 0x21C,
758 [PWRAP_MD_AUXADC_RDATA_6_ADDR] = 0x220,
759 [PWRAP_MD_AUXADC_RDATA_7_ADDR] = 0x224,
760 [PWRAP_MD_AUXADC_RDATA_8_ADDR] = 0x228,
761 [PWRAP_MD_AUXADC_RDATA_9_ADDR] = 0x22C,
762 [PWRAP_MD_AUXADC_RDATA_10_ADDR] = 0x230,
763 [PWRAP_MD_AUXADC_RDATA_11_ADDR] = 0x234,
764 [PWRAP_MD_AUXADC_RDATA_12_ADDR] = 0x238,
765 [PWRAP_MD_AUXADC_RDATA_13_ADDR] = 0x23C,
766 [PWRAP_MD_AUXADC_RDATA_14_ADDR] = 0x240,
767 [PWRAP_MD_AUXADC_RDATA_15_ADDR] = 0x244,
768 [PWRAP_MD_AUXADC_RDATA_16_ADDR] = 0x248,
769 [PWRAP_MD_AUXADC_RDATA_17_ADDR] = 0x24C,
770 [PWRAP_MD_AUXADC_RDATA_18_ADDR] = 0x250,
771 [PWRAP_MD_AUXADC_RDATA_19_ADDR] = 0x254,
772 [PWRAP_MD_AUXADC_RDATA_20_ADDR] = 0x258,
773 [PWRAP_MD_AUXADC_RDATA_21_ADDR] = 0x25C,
774 [PWRAP_MD_AUXADC_RDATA_22_ADDR] = 0x260,
775 [PWRAP_MD_AUXADC_RDATA_23_ADDR] = 0x264,
776 [PWRAP_MD_AUXADC_RDATA_24_ADDR] = 0x268,
777 [PWRAP_MD_AUXADC_RDATA_25_ADDR] = 0x26C,
778 [PWRAP_MD_AUXADC_RDATA_26_ADDR] = 0x270,
779 [PWRAP_MD_AUXADC_RDATA_27_ADDR] = 0x274,
780 [PWRAP_MD_AUXADC_RDATA_28_ADDR] = 0x278,
781 [PWRAP_MD_AUXADC_RDATA_29_ADDR] = 0x27C,
782 [PWRAP_MD_AUXADC_RDATA_30_ADDR] = 0x280,
783 [PWRAP_MD_AUXADC_RDATA_31_ADDR] = 0x284,
784 [PWRAP_MD_ADCINF_0_STA_0] = 0x288,
785 [PWRAP_MD_ADCINF_0_STA_1] = 0x28C,
786 [PWRAP_MD_ADCINF_1_STA_0] = 0x290,
787 [PWRAP_MD_ADCINF_1_STA_1] = 0x294,
788 [PWRAP_PRIORITY_USER_SEL_2] = 0x2B0,
789 [PWRAP_ARBITER_OUT_SEL_2] = 0x2C4,
790 [PWRAP_STARV_COUNTER_0] = 0x2D0,
791 [PWRAP_STARV_COUNTER_1] = 0x2D4,
792 [PWRAP_STARV_COUNTER_2] = 0x2D8,
793 [PWRAP_STARV_COUNTER_3] = 0x2DC,
794 [PWRAP_STARV_COUNTER_4] = 0x2E0,
795 [PWRAP_STARV_COUNTER_5] = 0x2E4,
796 [PWRAP_STARV_COUNTER_6] = 0x2E8,
797 [PWRAP_STARV_COUNTER_7] = 0x2EC,
798 [PWRAP_STARV_COUNTER_8] = 0x2F0,
799 [PWRAP_STARV_COUNTER_9] = 0x2F4,
800 [PWRAP_STARV_COUNTER_10] = 0x2F8,
801 [PWRAP_STARV_COUNTER_11] = 0x2FC,
802 [PWRAP_STARV_COUNTER_12] = 0x300,
803 [PWRAP_STARV_COUNTER_13] = 0x304,
804 [PWRAP_STARV_COUNTER_14] = 0x308,
805 [PWRAP_STARV_COUNTER_15] = 0x30C,
806 [PWRAP_STARV_COUNTER_16] = 0x310,
807 [PWRAP_MONITOR_CTRL_0] = 0x364,
808 [PWRAP_MONITOR_CTRL_1] = 0x368,
809 [PWRAP_MONITOR_CTRL_2] = 0x36C,
810 [PWRAP_MONITOR_CTRL_3] = 0x370,
811 [PWRAP_CHANNEL_SEQUENCE_0] = 0x374,
812 [PWRAP_CHANNEL_SEQUENCE_1] = 0x378,
813 [PWRAP_CHANNEL_SEQUENCE_2] = 0x37C,
814 [PWRAP_CHANNEL_SEQUENCE_3] = 0x380,
815 [PWRAP_CMD_SEQUENCE_0] = 0x384,
816 [PWRAP_CMD_SEQUENCE_1] = 0x388,
817 [PWRAP_CMD_SEQUENCE_2] = 0x38C,
818 [PWRAP_CMD_SEQUENCE_3] = 0x390,
819 [PWRAP_CMD_SEQUENCE_4] = 0x394,
820 [PWRAP_CMD_SEQUENCE_5] = 0x398,
821 [PWRAP_CMD_SEQUENCE_6] = 0x39C,
822 [PWRAP_CMD_SEQUENCE_7] = 0x3A0,
823 [PWRAP_WDATA_SEQUENCE_0] = 0x3A4,
824 [PWRAP_WDATA_SEQUENCE_1] = 0x3A8,
825 [PWRAP_WDATA_SEQUENCE_2] = 0x3AC,
826 [PWRAP_WDATA_SEQUENCE_3] = 0x3B0,
827 [PWRAP_WDATA_SEQUENCE_4] = 0x3B4,
828 [PWRAP_WDATA_SEQUENCE_5] = 0x3B8,
829 [PWRAP_WDATA_SEQUENCE_6] = 0x3BC,
830 [PWRAP_WDATA_SEQUENCE_7] = 0x3C0,
831 [PWRAP_WACS2_CMD] = 0xC20,
832 [PWRAP_WACS2_RDATA] = 0xC24,
833 [PWRAP_WACS2_VLDCLR] = 0xC28,
834 [PWRAP_MPU_PMIC_ACC_VIO_INFO_0] = 0xF44,
835 [PWRAP_MPU_PMIC_ACC_VIO_INFO_1] = 0xF48,
836 [PWRAP_MPU_PMIC_ACC_VIO_INFO_2] = 0xF4C,
837 [PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_0] = 0xF50,
838 [PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_1] = 0xF54,
839 [PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_2] = 0xF58,
840 [PWRAP_MPU_PWRAP_ACC_VIO_INFO_0] = 0xF5C,
841 [PWRAP_MPU_PWRAP_ACC_VIO_INFO_1] = 0xF60,
842};
843
844static int mt7622_regs[] = {
845 [PWRAP_MUX_SEL] = 0x0,
846 [PWRAP_WRAP_EN] = 0x4,
847 [PWRAP_DIO_EN] = 0x8,
848 [PWRAP_SIDLY] = 0xC,
849 [PWRAP_RDDMY] = 0x10,
850 [PWRAP_SI_CK_CON] = 0x14,
851 [PWRAP_CSHEXT_WRITE] = 0x18,
852 [PWRAP_CSHEXT_READ] = 0x1C,
853 [PWRAP_CSLEXT_START] = 0x20,
854 [PWRAP_CSLEXT_END] = 0x24,
855 [PWRAP_STAUPD_PRD] = 0x28,
856 [PWRAP_STAUPD_GRPEN] = 0x2C,
857 [PWRAP_EINT_STA0_ADR] = 0x30,
858 [PWRAP_EINT_STA1_ADR] = 0x34,
859 [PWRAP_STA] = 0x38,
860 [PWRAP_CLR] = 0x3C,
861 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
862 [PWRAP_STAUPD_STA] = 0x44,
863 [PWRAP_WRAP_STA] = 0x48,
864 [PWRAP_HARB_INIT] = 0x4C,
865 [PWRAP_HARB_HPRIO] = 0x50,
866 [PWRAP_HIPRIO_ARB_EN] = 0x54,
867 [PWRAP_HARB_STA0] = 0x58,
868 [PWRAP_HARB_STA1] = 0x5C,
869 [PWRAP_MAN_EN] = 0x60,
870 [PWRAP_MAN_CMD] = 0x64,
871 [PWRAP_MAN_RDATA] = 0x68,
872 [PWRAP_MAN_VLDCLR] = 0x6C,
873 [PWRAP_WACS0_EN] = 0x70,
874 [PWRAP_INIT_DONE0] = 0x74,
875 [PWRAP_WACS0_CMD] = 0x78,
876 [PWRAP_WACS0_RDATA] = 0x7C,
877 [PWRAP_WACS0_VLDCLR] = 0x80,
878 [PWRAP_WACS1_EN] = 0x84,
879 [PWRAP_INIT_DONE1] = 0x88,
880 [PWRAP_WACS1_CMD] = 0x8C,
881 [PWRAP_WACS1_RDATA] = 0x90,
882 [PWRAP_WACS1_VLDCLR] = 0x94,
883 [PWRAP_WACS2_EN] = 0x98,
884 [PWRAP_INIT_DONE2] = 0x9C,
885 [PWRAP_WACS2_CMD] = 0xA0,
886 [PWRAP_WACS2_RDATA] = 0xA4,
887 [PWRAP_WACS2_VLDCLR] = 0xA8,
888 [PWRAP_INT_EN] = 0xAC,
889 [PWRAP_INT_FLG_RAW] = 0xB0,
890 [PWRAP_INT_FLG] = 0xB4,
891 [PWRAP_INT_CLR] = 0xB8,
892 [PWRAP_SIG_ADR] = 0xBC,
893 [PWRAP_SIG_MODE] = 0xC0,
894 [PWRAP_SIG_VALUE] = 0xC4,
895 [PWRAP_SIG_ERRVAL] = 0xC8,
896 [PWRAP_CRC_EN] = 0xCC,
897 [PWRAP_TIMER_EN] = 0xD0,
898 [PWRAP_TIMER_STA] = 0xD4,
899 [PWRAP_WDT_UNIT] = 0xD8,
900 [PWRAP_WDT_SRC_EN] = 0xDC,
901 [PWRAP_WDT_FLG] = 0xE0,
902 [PWRAP_DEBUG_INT_SEL] = 0xE4,
903 [PWRAP_DVFS_ADR0] = 0xE8,
904 [PWRAP_DVFS_WDATA0] = 0xEC,
905 [PWRAP_DVFS_ADR1] = 0xF0,
906 [PWRAP_DVFS_WDATA1] = 0xF4,
907 [PWRAP_DVFS_ADR2] = 0xF8,
908 [PWRAP_DVFS_WDATA2] = 0xFC,
909 [PWRAP_DVFS_ADR3] = 0x100,
910 [PWRAP_DVFS_WDATA3] = 0x104,
911 [PWRAP_DVFS_ADR4] = 0x108,
912 [PWRAP_DVFS_WDATA4] = 0x10C,
913 [PWRAP_DVFS_ADR5] = 0x110,
914 [PWRAP_DVFS_WDATA5] = 0x114,
915 [PWRAP_DVFS_ADR6] = 0x118,
916 [PWRAP_DVFS_WDATA6] = 0x11C,
917 [PWRAP_DVFS_ADR7] = 0x120,
918 [PWRAP_DVFS_WDATA7] = 0x124,
919 [PWRAP_DVFS_ADR8] = 0x128,
920 [PWRAP_DVFS_WDATA8] = 0x12C,
921 [PWRAP_DVFS_ADR9] = 0x130,
922 [PWRAP_DVFS_WDATA9] = 0x134,
923 [PWRAP_DVFS_ADR10] = 0x138,
924 [PWRAP_DVFS_WDATA10] = 0x13C,
925 [PWRAP_DVFS_ADR11] = 0x140,
926 [PWRAP_DVFS_WDATA11] = 0x144,
927 [PWRAP_DVFS_ADR12] = 0x148,
928 [PWRAP_DVFS_WDATA12] = 0x14C,
929 [PWRAP_DVFS_ADR13] = 0x150,
930 [PWRAP_DVFS_WDATA13] = 0x154,
931 [PWRAP_DVFS_ADR14] = 0x158,
932 [PWRAP_DVFS_WDATA14] = 0x15C,
933 [PWRAP_DVFS_ADR15] = 0x160,
934 [PWRAP_DVFS_WDATA15] = 0x164,
935 [PWRAP_SPMINF_STA] = 0x168,
936 [PWRAP_CIPHER_KEY_SEL] = 0x16C,
937 [PWRAP_CIPHER_IV_SEL] = 0x170,
938 [PWRAP_CIPHER_EN] = 0x174,
939 [PWRAP_CIPHER_RDY] = 0x178,
940 [PWRAP_CIPHER_MODE] = 0x17C,
941 [PWRAP_CIPHER_SWRST] = 0x180,
942 [PWRAP_DCM_EN] = 0x184,
943 [PWRAP_DCM_DBC_PRD] = 0x188,
944 [PWRAP_EXT_CK] = 0x18C,
945 [PWRAP_ADC_CMD_ADDR] = 0x190,
946 [PWRAP_PWRAP_ADC_CMD] = 0x194,
947 [PWRAP_ADC_RDATA_ADDR] = 0x198,
948 [PWRAP_GPS_STA] = 0x19C,
949 [PWRAP_SW_RST] = 0x1A0,
950 [PWRAP_DVFS_STEP_CTRL0] = 0x238,
951 [PWRAP_DVFS_STEP_CTRL1] = 0x23C,
952 [PWRAP_DVFS_STEP_CTRL2] = 0x240,
953 [PWRAP_SPI2_CTRL] = 0x244,
954};
955
956static int mt8183_regs[] = {
957 [PWRAP_MUX_SEL] = 0x0,
958 [PWRAP_WRAP_EN] = 0x4,
959 [PWRAP_DIO_EN] = 0x8,
960 [PWRAP_SI_SAMPLE_CTRL] = 0xC,
961 [PWRAP_RDDMY] = 0x14,
962 [PWRAP_CSHEXT_WRITE] = 0x18,
963 [PWRAP_CSHEXT_READ] = 0x1C,
964 [PWRAP_CSLEXT_WRITE] = 0x20,
965 [PWRAP_CSLEXT_READ] = 0x24,
966 [PWRAP_EXT_CK_WRITE] = 0x28,
967 [PWRAP_STAUPD_CTRL] = 0x30,
968 [PWRAP_STAUPD_GRPEN] = 0x34,
969 [PWRAP_EINT_STA0_ADR] = 0x38,
970 [PWRAP_HARB_HPRIO] = 0x5C,
971 [PWRAP_HIPRIO_ARB_EN] = 0x60,
972 [PWRAP_MAN_EN] = 0x70,
973 [PWRAP_MAN_CMD] = 0x74,
974 [PWRAP_WACS0_EN] = 0x80,
975 [PWRAP_INIT_DONE0] = 0x84,
976 [PWRAP_WACS1_EN] = 0x88,
977 [PWRAP_INIT_DONE1] = 0x8C,
978 [PWRAP_WACS2_EN] = 0x90,
979 [PWRAP_INIT_DONE2] = 0x94,
980 [PWRAP_WACS_P2P_EN] = 0xA0,
981 [PWRAP_INIT_DONE_P2P] = 0xA4,
982 [PWRAP_WACS_MD32_EN] = 0xA8,
983 [PWRAP_INIT_DONE_MD32] = 0xAC,
984 [PWRAP_INT_EN] = 0xB0,
985 [PWRAP_INT_FLG] = 0xB8,
986 [PWRAP_INT_CLR] = 0xBC,
987 [PWRAP_INT1_EN] = 0xC0,
988 [PWRAP_INT1_FLG] = 0xC8,
989 [PWRAP_INT1_CLR] = 0xCC,
990 [PWRAP_SIG_ADR] = 0xD0,
991 [PWRAP_CRC_EN] = 0xE0,
992 [PWRAP_TIMER_EN] = 0xE4,
993 [PWRAP_WDT_UNIT] = 0xEC,
994 [PWRAP_WDT_SRC_EN] = 0xF0,
995 [PWRAP_WDT_SRC_EN_1] = 0xF4,
996 [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC,
997 [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0,
998 [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4,
999 [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8,
1000 [PWRAP_GPSINF_0_STA] = 0x1EC,
1001 [PWRAP_GPSINF_1_STA] = 0x1F0,
1002 [PWRAP_MD_AUXADC_RDATA_LATEST_ADDR] = 0x1F8,
1003 [PWRAP_MD_AUXADC_RDATA_WP_ADDR] = 0x1FC,
1004 [PWRAP_MD_AUXADC_RDATA_0_ADDR] = 0x200,
1005 [PWRAP_MD_AUXADC_RDATA_1_ADDR] = 0x204,
1006 [PWRAP_MD_AUXADC_RDATA_2_ADDR] = 0x208,
1007 [PWRAP_MD_AUXADC_RDATA_3_ADDR] = 0x20C,
1008 [PWRAP_MD_AUXADC_RDATA_4_ADDR] = 0x210,
1009 [PWRAP_MD_AUXADC_RDATA_5_ADDR] = 0x214,
1010 [PWRAP_MD_AUXADC_RDATA_6_ADDR] = 0x218,
1011 [PWRAP_MD_AUXADC_RDATA_7_ADDR] = 0x21C,
1012 [PWRAP_MD_AUXADC_RDATA_8_ADDR] = 0x220,
1013 [PWRAP_MD_AUXADC_RDATA_9_ADDR] = 0x224,
1014 [PWRAP_MD_AUXADC_RDATA_10_ADDR] = 0x228,
1015 [PWRAP_MD_AUXADC_RDATA_11_ADDR] = 0x22C,
1016 [PWRAP_MD_AUXADC_RDATA_12_ADDR] = 0x230,
1017 [PWRAP_MD_AUXADC_RDATA_13_ADDR] = 0x234,
1018 [PWRAP_MD_AUXADC_RDATA_14_ADDR] = 0x238,
1019 [PWRAP_MD_AUXADC_RDATA_15_ADDR] = 0x23C,
1020 [PWRAP_MD_AUXADC_RDATA_16_ADDR] = 0x240,
1021 [PWRAP_MD_AUXADC_RDATA_17_ADDR] = 0x244,
1022 [PWRAP_MD_AUXADC_RDATA_18_ADDR] = 0x248,
1023 [PWRAP_MD_AUXADC_RDATA_19_ADDR] = 0x24C,
1024 [PWRAP_MD_AUXADC_RDATA_20_ADDR] = 0x250,
1025 [PWRAP_MD_AUXADC_RDATA_21_ADDR] = 0x254,
1026 [PWRAP_MD_AUXADC_RDATA_22_ADDR] = 0x258,
1027 [PWRAP_MD_AUXADC_RDATA_23_ADDR] = 0x25C,
1028 [PWRAP_MD_AUXADC_RDATA_24_ADDR] = 0x260,
1029 [PWRAP_MD_AUXADC_RDATA_25_ADDR] = 0x264,
1030 [PWRAP_MD_AUXADC_RDATA_26_ADDR] = 0x268,
1031 [PWRAP_MD_AUXADC_RDATA_27_ADDR] = 0x26C,
1032 [PWRAP_MD_AUXADC_RDATA_28_ADDR] = 0x270,
1033 [PWRAP_MD_AUXADC_RDATA_29_ADDR] = 0x274,
1034 [PWRAP_MD_AUXADC_RDATA_30_ADDR] = 0x278,
1035 [PWRAP_MD_AUXADC_RDATA_31_ADDR] = 0x27C,
1036 [PWRAP_PRIORITY_USER_SEL_2] = 0x2A4,
1037 [PWRAP_ARBITER_OUT_SEL_2] = 0x2B8,
1038 [PWRAP_STARV_COUNTER_0] = 0x2C4,
1039 [PWRAP_STARV_COUNTER_1] = 0x2C8,
1040 [PWRAP_STARV_COUNTER_2] = 0x2CC,
1041 [PWRAP_STARV_COUNTER_3] = 0x2D0,
1042 [PWRAP_STARV_COUNTER_4] = 0x2D4,
1043 [PWRAP_STARV_COUNTER_5] = 0x2D8,
1044 [PWRAP_STARV_COUNTER_6] = 0x2DC,
1045 [PWRAP_STARV_COUNTER_7] = 0x2E0,
1046 [PWRAP_STARV_COUNTER_8] = 0x2E4,
1047 [PWRAP_STARV_COUNTER_9] = 0x2E8,
1048 [PWRAP_STARV_COUNTER_10] = 0x2EC,
1049 [PWRAP_STARV_COUNTER_11] = 0x2F0,
1050 [PWRAP_STARV_COUNTER_12] = 0x2F4,
1051 [PWRAP_STARV_COUNTER_13] = 0x2F8,
1052 [PWRAP_STARV_COUNTER_16] = 0x304,
1053 [PWRAP_WACS2_CMD] = 0xC20,
1054 [PWRAP_WACS2_RDATA] = 0xC24,
1055 [PWRAP_WACS2_VLDCLR] = 0xC28,
1056};
1057
1058static int mt8173_regs[] = {
1059 [PWRAP_MUX_SEL] = 0x0,
1060 [PWRAP_WRAP_EN] = 0x4,
1061 [PWRAP_DIO_EN] = 0x8,
1062 [PWRAP_SIDLY] = 0xc,
1063 [PWRAP_RDDMY] = 0x10,
1064 [PWRAP_SI_CK_CON] = 0x14,
1065 [PWRAP_CSHEXT_WRITE] = 0x18,
1066 [PWRAP_CSHEXT_READ] = 0x1c,
1067 [PWRAP_CSLEXT_START] = 0x20,
1068 [PWRAP_CSLEXT_END] = 0x24,
1069 [PWRAP_STAUPD_PRD] = 0x28,
1070 [PWRAP_STAUPD_GRPEN] = 0x2c,
1071 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
1072 [PWRAP_STAUPD_STA] = 0x44,
1073 [PWRAP_WRAP_STA] = 0x48,
1074 [PWRAP_HARB_INIT] = 0x4c,
1075 [PWRAP_HARB_HPRIO] = 0x50,
1076 [PWRAP_HIPRIO_ARB_EN] = 0x54,
1077 [PWRAP_HARB_STA0] = 0x58,
1078 [PWRAP_HARB_STA1] = 0x5c,
1079 [PWRAP_MAN_EN] = 0x60,
1080 [PWRAP_MAN_CMD] = 0x64,
1081 [PWRAP_MAN_RDATA] = 0x68,
1082 [PWRAP_MAN_VLDCLR] = 0x6c,
1083 [PWRAP_WACS0_EN] = 0x70,
1084 [PWRAP_INIT_DONE0] = 0x74,
1085 [PWRAP_WACS0_CMD] = 0x78,
1086 [PWRAP_WACS0_RDATA] = 0x7c,
1087 [PWRAP_WACS0_VLDCLR] = 0x80,
1088 [PWRAP_WACS1_EN] = 0x84,
1089 [PWRAP_INIT_DONE1] = 0x88,
1090 [PWRAP_WACS1_CMD] = 0x8c,
1091 [PWRAP_WACS1_RDATA] = 0x90,
1092 [PWRAP_WACS1_VLDCLR] = 0x94,
1093 [PWRAP_WACS2_EN] = 0x98,
1094 [PWRAP_INIT_DONE2] = 0x9c,
1095 [PWRAP_WACS2_CMD] = 0xa0,
1096 [PWRAP_WACS2_RDATA] = 0xa4,
1097 [PWRAP_WACS2_VLDCLR] = 0xa8,
1098 [PWRAP_INT_EN] = 0xac,
1099 [PWRAP_INT_FLG_RAW] = 0xb0,
1100 [PWRAP_INT_FLG] = 0xb4,
1101 [PWRAP_INT_CLR] = 0xb8,
1102 [PWRAP_SIG_ADR] = 0xbc,
1103 [PWRAP_SIG_MODE] = 0xc0,
1104 [PWRAP_SIG_VALUE] = 0xc4,
1105 [PWRAP_SIG_ERRVAL] = 0xc8,
1106 [PWRAP_CRC_EN] = 0xcc,
1107 [PWRAP_TIMER_EN] = 0xd0,
1108 [PWRAP_TIMER_STA] = 0xd4,
1109 [PWRAP_WDT_UNIT] = 0xd8,
1110 [PWRAP_WDT_SRC_EN] = 0xdc,
1111 [PWRAP_WDT_FLG] = 0xe0,
1112 [PWRAP_DEBUG_INT_SEL] = 0xe4,
1113 [PWRAP_DVFS_ADR0] = 0xe8,
1114 [PWRAP_DVFS_WDATA0] = 0xec,
1115 [PWRAP_DVFS_ADR1] = 0xf0,
1116 [PWRAP_DVFS_WDATA1] = 0xf4,
1117 [PWRAP_DVFS_ADR2] = 0xf8,
1118 [PWRAP_DVFS_WDATA2] = 0xfc,
1119 [PWRAP_DVFS_ADR3] = 0x100,
1120 [PWRAP_DVFS_WDATA3] = 0x104,
1121 [PWRAP_DVFS_ADR4] = 0x108,
1122 [PWRAP_DVFS_WDATA4] = 0x10c,
1123 [PWRAP_DVFS_ADR5] = 0x110,
1124 [PWRAP_DVFS_WDATA5] = 0x114,
1125 [PWRAP_DVFS_ADR6] = 0x118,
1126 [PWRAP_DVFS_WDATA6] = 0x11c,
1127 [PWRAP_DVFS_ADR7] = 0x120,
1128 [PWRAP_DVFS_WDATA7] = 0x124,
1129 [PWRAP_SPMINF_STA] = 0x128,
1130 [PWRAP_CIPHER_KEY_SEL] = 0x12c,
1131 [PWRAP_CIPHER_IV_SEL] = 0x130,
1132 [PWRAP_CIPHER_EN] = 0x134,
1133 [PWRAP_CIPHER_RDY] = 0x138,
1134 [PWRAP_CIPHER_MODE] = 0x13c,
1135 [PWRAP_CIPHER_SWRST] = 0x140,
1136 [PWRAP_DCM_EN] = 0x144,
1137 [PWRAP_DCM_DBC_PRD] = 0x148,
1138};
1139
1140static int mt8135_regs[] = {
1141 [PWRAP_MUX_SEL] = 0x0,
1142 [PWRAP_WRAP_EN] = 0x4,
1143 [PWRAP_DIO_EN] = 0x8,
1144 [PWRAP_SIDLY] = 0xc,
1145 [PWRAP_CSHEXT] = 0x10,
1146 [PWRAP_CSHEXT_WRITE] = 0x14,
1147 [PWRAP_CSHEXT_READ] = 0x18,
1148 [PWRAP_CSLEXT_START] = 0x1c,
1149 [PWRAP_CSLEXT_END] = 0x20,
1150 [PWRAP_STAUPD_PRD] = 0x24,
1151 [PWRAP_STAUPD_GRPEN] = 0x28,
1152 [PWRAP_STAUPD_MAN_TRIG] = 0x2c,
1153 [PWRAP_STAUPD_STA] = 0x30,
1154 [PWRAP_EVENT_IN_EN] = 0x34,
1155 [PWRAP_EVENT_DST_EN] = 0x38,
1156 [PWRAP_WRAP_STA] = 0x3c,
1157 [PWRAP_RRARB_INIT] = 0x40,
1158 [PWRAP_RRARB_EN] = 0x44,
1159 [PWRAP_RRARB_STA0] = 0x48,
1160 [PWRAP_RRARB_STA1] = 0x4c,
1161 [PWRAP_HARB_INIT] = 0x50,
1162 [PWRAP_HARB_HPRIO] = 0x54,
1163 [PWRAP_HIPRIO_ARB_EN] = 0x58,
1164 [PWRAP_HARB_STA0] = 0x5c,
1165 [PWRAP_HARB_STA1] = 0x60,
1166 [PWRAP_MAN_EN] = 0x64,
1167 [PWRAP_MAN_CMD] = 0x68,
1168 [PWRAP_MAN_RDATA] = 0x6c,
1169 [PWRAP_MAN_VLDCLR] = 0x70,
1170 [PWRAP_WACS0_EN] = 0x74,
1171 [PWRAP_INIT_DONE0] = 0x78,
1172 [PWRAP_WACS0_CMD] = 0x7c,
1173 [PWRAP_WACS0_RDATA] = 0x80,
1174 [PWRAP_WACS0_VLDCLR] = 0x84,
1175 [PWRAP_WACS1_EN] = 0x88,
1176 [PWRAP_INIT_DONE1] = 0x8c,
1177 [PWRAP_WACS1_CMD] = 0x90,
1178 [PWRAP_WACS1_RDATA] = 0x94,
1179 [PWRAP_WACS1_VLDCLR] = 0x98,
1180 [PWRAP_WACS2_EN] = 0x9c,
1181 [PWRAP_INIT_DONE2] = 0xa0,
1182 [PWRAP_WACS2_CMD] = 0xa4,
1183 [PWRAP_WACS2_RDATA] = 0xa8,
1184 [PWRAP_WACS2_VLDCLR] = 0xac,
1185 [PWRAP_INT_EN] = 0xb0,
1186 [PWRAP_INT_FLG_RAW] = 0xb4,
1187 [PWRAP_INT_FLG] = 0xb8,
1188 [PWRAP_INT_CLR] = 0xbc,
1189 [PWRAP_SIG_ADR] = 0xc0,
1190 [PWRAP_SIG_MODE] = 0xc4,
1191 [PWRAP_SIG_VALUE] = 0xc8,
1192 [PWRAP_SIG_ERRVAL] = 0xcc,
1193 [PWRAP_CRC_EN] = 0xd0,
1194 [PWRAP_EVENT_STA] = 0xd4,
1195 [PWRAP_EVENT_STACLR] = 0xd8,
1196 [PWRAP_TIMER_EN] = 0xdc,
1197 [PWRAP_TIMER_STA] = 0xe0,
1198 [PWRAP_WDT_UNIT] = 0xe4,
1199 [PWRAP_WDT_SRC_EN] = 0xe8,
1200 [PWRAP_WDT_FLG] = 0xec,
1201 [PWRAP_DEBUG_INT_SEL] = 0xf0,
1202 [PWRAP_CIPHER_KEY_SEL] = 0x134,
1203 [PWRAP_CIPHER_IV_SEL] = 0x138,
1204 [PWRAP_CIPHER_LOAD] = 0x13c,
1205 [PWRAP_CIPHER_START] = 0x140,
1206 [PWRAP_CIPHER_RDY] = 0x144,
1207 [PWRAP_CIPHER_MODE] = 0x148,
1208 [PWRAP_CIPHER_SWRST] = 0x14c,
1209 [PWRAP_DCM_EN] = 0x15c,
1210 [PWRAP_DCM_DBC_PRD] = 0x160,
1211};
1212
1213enum pmic_type {
1214 PMIC_MT6323,
1215 PMIC_MT6356,
1216 PMIC_MT6358,
1217 PMIC_MT6380,
1218 PMIC_MT6389,
1219 PMIC_MT6397,
1220};
1221
1222enum pwrap_type {
1223 PWRAP_MT2701,
1224 PWRAP_MT2731,
1225 PWRAP_MT7622,
1226 PWRAP_MT8135,
1227 PWRAP_MT8173,
1228 PWRAP_MT8183,
1229};
1230
1231struct pmic_wrapper;
1232struct pwrap_slv_type {
1233 const u32 *dew_regs;
1234 enum pmic_type type;
1235 const struct regmap_config *regmap;
1236 /* Flags indicating the capability for the target slave */
1237 u32 caps;
1238 /*
1239 * pwrap operations are highly associated with the PMIC types,
1240 * so the pointers added increases flexibility allowing determination
1241 * which type is used by the detection through device tree.
1242 */
1243 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
1244 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
1245};
1246
1247struct pmic_wrapper {
1248 struct device *dev;
1249 void __iomem *base;
1250 struct regmap *regmap;
1251 const struct pmic_wrapper_type *master;
1252 const struct pwrap_slv_type *slave;
1253 struct clk *clk_spi;
1254 struct clk *clk_wrap;
1255 struct reset_control *rstc;
1256
1257 struct reset_control *rstc_bridge;
1258 void __iomem *bridge_base;
1259};
1260
1261struct pmic_wrapper_type {
1262 int *regs;
1263 enum pwrap_type type;
1264 u32 arb_en_all;
1265 u32 int_en_all;
1266 u32 int1_en_all;
1267 u32 spi_w;
1268 u32 wdt_src;
1269 unsigned int has_bridge:1;
1270 /* Flags indicating the capability for the target pwrap */
1271 u32 caps;
1272 int (*init_reg_clock)(struct pmic_wrapper *wrp);
1273 int (*init_soc_specific)(struct pmic_wrapper *wrp);
1274};
1275
1276static struct pmic_wrapper *wrp;
1277
1278static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg);
1279static void pwrap_writel(struct pmic_wrapper *wrp, u32 val,
1280 enum pwrap_regs reg);
1281static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
1282static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
1283
1284inline void pwrap_dump_ap_cmd_logging_register(void)
1285{
1286 unsigned int i = 0, offset = 0, log_size = 0;
1287 unsigned int ch[16] = {0}, rw[16] = {0}, cmd[16] = {0}, dat[16] = {0};
1288 unsigned int j = 0, s = 0, e = 0, tmp_dat = 0;
1289 unsigned int *reg_addr;
1290
1291 log_size += sprintf(pwrap_log_buf, "\npwrap ");
1292 s = wrp->master->regs[PWRAP_CHANNEL_SEQUENCE_0]/4;
1293 e = wrp->master->regs[PWRAP_CHANNEL_SEQUENCE_3]/4;
1294 for (i = s; i <= e; i++) {
1295 reg_addr = wrp->base + (i * 4);
1296 tmp_dat = readl(reg_addr);
1297 ch[j] = tmp_dat & 0xff;
1298 ch[j+1] = (tmp_dat & 0xff00) >> 8;
1299 ch[j+2] = (tmp_dat & 0xff0000) >> 16;
1300 ch[j+3] = (tmp_dat & 0xff000000) >> 24;
1301 j += 4;
1302 }
1303 j = 0;
1304 s = wrp->master->regs[PWRAP_CMD_SEQUENCE_0]/4;
1305 e = wrp->master->regs[PWRAP_CMD_SEQUENCE_7]/4;
1306 for (i = s; i <= e; i++) {
1307 reg_addr = wrp->base + (i * 4);
1308 tmp_dat = readl(reg_addr);
1309 rw[j] = (tmp_dat >> 15) & 0x1;
1310 cmd[j] = (tmp_dat & 0x7fff) << 1;
1311 rw[j+1] = (tmp_dat >> 31);
1312 cmd[j+1] = ((tmp_dat & 0x7fff0000) >> 16) << 1;
1313 j += 2;
1314 }
1315 j = 0;
1316 s = wrp->master->regs[PWRAP_WDATA_SEQUENCE_0]/4;
1317 e = wrp->master->regs[PWRAP_WDATA_SEQUENCE_7]/4;
1318 for (i = s; i <= e; i++) {
1319 reg_addr = wrp->base + (i * 4);
1320 tmp_dat = readl(reg_addr);
1321 dat[j] = tmp_dat & 0xffff;
1322 dat[j+1] = (tmp_dat & 0xffff0000) >> 16;
1323 j += 2;
1324 }
1325 for (i = 0; i < 16; i++) {
1326 log_size += sprintf(pwrap_log_buf + log_size,
1327 "[ch:%x, w:%d, adr:0x%04x, dat:0x%04x]",
1328 ch[i], rw[i], cmd[i], dat[i]);
1329 if (i == 0)
1330 continue;
1331
1332 if (i % 2 == 0) {
1333 log_size += sprintf(pwrap_log_buf + log_size,
1334 "log_size:%d\npwrap ", log_size);
1335 }
1336 }
1337 dev_dbg(wrp->dev, "\npwrap %s %d\n", pwrap_log_buf, log_size);
1338 log_size = 0;
1339 for (i = 0; i <= 14; i++) {
1340 offset = 0xc00 + i * 4;
1341 reg_addr = wrp->base + offset;
1342 log_size += sprintf(pwrap_log_buf + log_size,
1343 "(0x%x) = 0x%x ", offset, readl(reg_addr));
1344 }
1345 dev_dbg(wrp->dev, "\npwrap %s %d\n", pwrap_log_buf, log_size);
1346
1347 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MON_V1)) {
1348 pwrap_writel(wrp, 0x8, PWRAP_MONITOR_CTRL_0);
1349 pwrap_writel(wrp, 0x5, PWRAP_MONITOR_CTRL_0);
1350 } else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MON_V2)) {
1351 pwrap_writel(wrp, 0x800, PWRAP_MONITOR_CTRL_0);
1352 pwrap_writel(wrp, 0x5, PWRAP_MONITOR_CTRL_0);
1353 }
1354}
1355static inline void pwrap_dump_sta_register(unsigned int st, unsigned int nd)
1356{
1357 unsigned int i = 0, log_size = 0, start = 0, end = 0;
1358 unsigned int *reg_addr;
1359
1360 start = st/4;
1361 end = nd/4;
1362
1363 for (i = start; i <= end; i++) {
1364 reg_addr = wrp->base + (i * 4);
1365 log_size += sprintf(pwrap_log_buf + log_size,
1366 "(0x%x)=0x%x ", i * 4, readl(reg_addr));
1367
1368 if (i == 0)
1369 continue;
1370 if (i % 8 == 0) {
1371 log_size += sprintf(pwrap_log_buf + log_size,
1372 "log_size:%d\npwrap ", log_size);
1373 }
1374 if (i % 0x28 == 0) {
1375 dev_dbg(wrp->dev, "\npwrap %s %d\n",
1376 pwrap_log_buf, log_size);
1377 log_size = 0;
1378 }
1379 }
1380 dev_dbg(wrp->dev, "\npwrap %s %d\n", pwrap_log_buf, log_size);
1381 log_size = 0;
1382 pwrap_dump_ap_cmd_logging_register();
1383}
1384
1385static inline void pwrap_dump_busy_register(void)
1386{
1387 unsigned int log_size = 0;
1388
1389 log_size += sprintf(pwrap_log_buf,
1390 "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x\n",
1391 wrp->master->regs[PWRAP_DCXO_CONN_ADR0],
1392 pwrap_readl(wrp, PWRAP_DCXO_CONN_ADR0),
1393 wrp->master->regs[PWRAP_DCXO_CONN_WDATA0],
1394 pwrap_readl(wrp, PWRAP_DCXO_CONN_WDATA0),
1395 wrp->master->regs[PWRAP_DCXO_CONN_ADR1],
1396 pwrap_readl(wrp, PWRAP_DCXO_CONN_ADR1),
1397 wrp->master->regs[PWRAP_DCXO_CONN_WDATA1],
1398 pwrap_readl(wrp, PWRAP_DCXO_CONN_WDATA1));
1399
1400 log_size += sprintf(pwrap_log_buf + log_size,
1401 "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x",
1402 wrp->master->regs[PWRAP_DCXO_NFC_ADR0],
1403 pwrap_readl(wrp, PWRAP_DCXO_NFC_ADR0),
1404 wrp->master->regs[PWRAP_DCXO_NFC_WDATA0],
1405 pwrap_readl(wrp, PWRAP_DCXO_NFC_WDATA0),
1406 wrp->master->regs[PWRAP_DCXO_NFC_ADR1],
1407 pwrap_readl(wrp, PWRAP_DCXO_NFC_ADR1),
1408 wrp->master->regs[PWRAP_DCXO_NFC_WDATA1],
1409 pwrap_readl(wrp, PWRAP_DCXO_NFC_WDATA1));
1410
1411 log_size += sprintf(pwrap_log_buf + log_size,
1412 "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x\n",
1413 wrp->master->regs[PWRAP_SPMINF_STA],
1414 pwrap_readl(wrp, PWRAP_SPMINF_STA),
1415 wrp->master->regs[PWRAP_SPMINF_STA_1],
1416 pwrap_readl(wrp, PWRAP_SPMINF_STA_1),
1417 wrp->master->regs[PWRAP_SPMINF_BACKUP_STA],
1418 pwrap_readl(wrp, PWRAP_SPMINF_BACKUP_STA),
1419 wrp->master->regs[PWRAP_SCPINF_STA],
1420 pwrap_readl(wrp, PWRAP_SCPINF_STA));
1421
1422 log_size += sprintf(pwrap_log_buf + log_size,
1423 "pwrap (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x",
1424 wrp->master->regs[PWRAP_CONNINF_STA_0],
1425 pwrap_readl(wrp, PWRAP_CONNINF_STA_0),
1426 wrp->master->regs[PWRAP_CONNINF_STA_1],
1427 pwrap_readl(wrp, PWRAP_CONNINF_STA_1),
1428 wrp->master->regs[PWRAP_MCU_PMINF_STA_0],
1429 pwrap_readl(wrp, PWRAP_MCU_PMINF_STA_0),
1430 wrp->master->regs[PWRAP_MCU_PMINF_STA_1],
1431 pwrap_readl(wrp, PWRAP_MCU_PMINF_STA_1));
1432
1433 log_size += sprintf(pwrap_log_buf + log_size,
1434 "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x\n",
1435 wrp->master->regs[PWRAP_GPSINF_0_STA],
1436 pwrap_readl(wrp, PWRAP_GPSINF_0_STA),
1437 wrp->master->regs[PWRAP_GPSINF_1_STA],
1438 pwrap_readl(wrp, PWRAP_GPSINF_1_STA),
1439 wrp->master->regs[PWRAP_MD_ADCINF_0_STA_0],
1440 pwrap_readl(wrp, PWRAP_MD_ADCINF_0_STA_0),
1441 wrp->master->regs[PWRAP_MD_ADCINF_0_STA_1],
1442 pwrap_readl(wrp, PWRAP_MD_ADCINF_0_STA_1));
1443
1444 log_size += sprintf(pwrap_log_buf + log_size,
1445 "pwrap (0x%x)=0x%x (0x%x)=0x%x",
1446 wrp->master->regs[PWRAP_MD_ADCINF_1_STA_0],
1447 pwrap_readl(wrp, PWRAP_MD_ADCINF_1_STA_0),
1448 wrp->master->regs[PWRAP_MD_ADCINF_1_STA_1],
1449 pwrap_readl(wrp, PWRAP_MD_ADCINF_1_STA_1));
1450
1451 log_size += sprintf(pwrap_log_buf + log_size,
1452 "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x\n",
1453 wrp->master->regs[PWRAP_WACS2_CMD],
1454 pwrap_readl(wrp, PWRAP_WACS2_CMD),
1455 wrp->master->regs[PWRAP_WACS2_RDATA],
1456 pwrap_readl(wrp, PWRAP_WACS2_RDATA),
1457 wrp->master->regs[PWRAP_WACS2_VLDCLR],
1458 pwrap_readl(wrp, PWRAP_WACS2_VLDCLR),
1459 wrp->master->regs[PWRAP_WACS0_RDATA],
1460 pwrap_readl(wrp, PWRAP_WACS0_RDATA));
1461
1462 dev_dbg(wrp->dev, "\npwrap %s %d\n", pwrap_log_buf, log_size);
1463 log_size = 0;
1464
1465 pwrap_dump_sta_register(wrp->master->regs[PWRAP_STARV_COUNTER_0],
1466 wrp->master->regs[PWRAP_MONITOR_CTRL_3]);
1467}
1468
1469static inline void pwrap_dump_ap_register(void)
1470{
1471 pwrap_dump_sta_register(0x0, 0x48c);
1472}
1473
1474static inline void pwrap_dump_pmic_register(void)
1475{
1476 unsigned int rdata = 0;
1477
1478 dev_dbg(wrp->dev, "dump PMIC register\n");
1479 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], &rdata);
1480 dev_dbg(wrp->dev, "[REG]0x%x=0x%x\n",
1481 wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], rdata);
1482 /* Write Test */
1483 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1484 PWRAP_DEW_WRITE_TEST_VAL) ||
1485 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1486 &rdata) ||
1487 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
1488 dev_dbg(wrp->dev, "pwrap rdata=0x%04X\n", rdata);
1489 }
1490}
1491
1492static void pwrap_mpu_info(void)
1493{
1494 unsigned int log_size = 0;
1495
1496 log_size += sprintf(pwrap_log_buf,
1497 "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x",
1498 wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_INFO_0],
1499 pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_INFO_0),
1500 wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_INFO_1],
1501 pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_INFO_1),
1502 wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_INFO_2],
1503 pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_INFO_2),
1504 wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_0],
1505 pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_0));
1506
1507 log_size += sprintf(pwrap_log_buf + log_size,
1508 "(0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x (0x%x)=0x%x",
1509 wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_1],
1510 pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_1),
1511 wrp->master->regs[PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_2],
1512 pwrap_readl(wrp, PWRAP_MPU_PMIC_ACC_VIO_P2P_INFO_2),
1513 wrp->master->regs[PWRAP_MPU_PWRAP_ACC_VIO_INFO_0],
1514 pwrap_readl(wrp, PWRAP_MPU_PWRAP_ACC_VIO_INFO_0),
1515 wrp->master->regs[PWRAP_MPU_PWRAP_ACC_VIO_INFO_1],
1516 pwrap_readl(wrp, PWRAP_MPU_PWRAP_ACC_VIO_INFO_1));
1517
1518 dev_dbg(wrp->dev, "\npwrap %s %d\n", pwrap_log_buf, log_size);
1519}
1520
1521static void pwrap_dump_pmic_cmd_logging_register(void)
1522{
1523 unsigned int rdata = 0, sub_return = 0;
1524
1525 /* Read Last three command */
1526 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_CMD0], &rdata);
1527 dev_dbg(wrp->dev,
1528 "REC_CMD0:0x%x (The last cmd addr)\n", rdata & 0x3fff);
1529 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_WDATA0], &rdata);
1530 dev_dbg(wrp->dev,
1531 "REC_WDATA0:0x%x (The last cmd wdata)\n", rdata);
1532 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_CMD1], &rdata);
1533 dev_dbg(wrp->dev,
1534 "REC_CMD1:0x%x (The sec-last cmd addr)\n", rdata & 0x3fff);
1535 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_WDATA1], &rdata);
1536 dev_dbg(wrp->dev,
1537 "REC_WDATA1:0x%x (The second-last cmd wdata)\n", rdata);
1538 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_CMD2], &rdata);
1539 dev_dbg(wrp->dev,
1540 "REC_CMD2:0x%x (The third cmd addr)\n", rdata & 0x3fff);
1541 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_RECORD_WDATA2], &rdata);
1542 dev_dbg(wrp->dev,
1543 "REC_WDATA2:0x%x (The third-last cmd wdata)\n", rdata);
1544
1545 /* Enable Command Recording */
1546 sub_return = pwrap_write(wrp,
1547 wrp->slave->dew_regs[PWRAP_DEW_RG_EN_RECORD], 0x3);
1548 if (sub_return != 0)
1549 dev_dbg(wrp->dev, "en spi debug fail, ret=%x\n", sub_return);
1550 dev_dbg(wrp->dev, "enable spi debug ok\n");
1551
1552 /* Clear Last three command */
1553 sub_return = pwrap_write(wrp,
1554 wrp->slave->dew_regs[PWRAP_DEW_RG_SPI_RECORD_CLR], 0x1);
1555 if (sub_return != 0)
1556 dev_dbg(wrp->dev, "clr rec cmd fail, ret=%x\n", sub_return);
1557 sub_return = pwrap_write(wrp,
1558 wrp->slave->dew_regs[PWRAP_DEW_RG_SPI_RECORD_CLR], 0x0);
1559 if (sub_return != 0)
1560 dev_dbg(wrp->dev, "clr rec cmd fail, ret=%x\n", sub_return);
1561 dev_dbg(wrp->dev, "clear record command ok\n");
1562
1563}
1564
1565void pwrap_dump_all_register(void)
1566{
1567 unsigned int rdata = 0;
1568
1569 /* add tsx/dcxo temperture log support */
1570 rdata = pwrap_readl(wrp, PWRAP_SPMINF_STA);
1571 dev_dbg(wrp->dev, "tsx dump reg_addr:0x%x = 0%x\n",
1572 wrp->master->regs[PWRAP_SPMINF_STA], rdata);
1573 rdata = pwrap_readl(wrp, PWRAP_MD_ADCINF_0_STA_0);
1574 dev_dbg(wrp->dev, "tsx dump reg_addr:0x%x = 0%x\n",
1575 wrp->master->regs[PWRAP_MD_ADCINF_0_STA_0], rdata);
1576 rdata = pwrap_readl(wrp, PWRAP_MD_ADCINF_0_STA_1);
1577 dev_dbg(wrp->dev, "tsx dump reg_addr:0x%x = 0%x\n",
1578 wrp->master->regs[PWRAP_MD_ADCINF_0_STA_1], rdata);
1579 rdata = pwrap_readl(wrp, PWRAP_MD_ADCINF_1_STA_0);
1580 dev_dbg(wrp->dev, "tsx dump reg_addr:0x%x = 0%x\n",
1581 wrp->master->regs[PWRAP_MD_ADCINF_1_STA_0], rdata);
1582 rdata = pwrap_readl(wrp, PWRAP_MD_ADCINF_1_STA_1);
1583 dev_dbg(wrp->dev, "tsx dump reg_addr:0x%x = 0%x\n",
1584 wrp->master->regs[PWRAP_MD_ADCINF_1_STA_1], rdata);
1585}
1586
1587void pwrap_dump_and_recovery(void)
1588{
1589 pwrap_dump_sta_register(0x0, 0x48c);
1590 pwrap_dump_pmic_register();
1591
1592 pwrap_writel(wrp, 0x0, PWRAP_WACS2_EN);
1593 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
1594}
1595static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
1596{
1597 return readl(wrp->base + wrp->master->regs[reg]);
1598}
1599
1600static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
1601{
1602 writel(val, wrp->base + wrp->master->regs[reg]);
1603}
1604
1605static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
1606{
1607 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1608
1609 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
1610}
1611
1612static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
1613{
1614 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1615
1616 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
1617}
1618
1619/*
1620 * Timeout issue sometimes caused by the last read command
1621 * failed because pmic wrap could not got the FSM_VLDCLR
1622 * in time after finishing WACS2_CMD. It made state machine
1623 * still on FSM_VLDCLR and timeout next time.
1624 * Check the status of FSM and clear the vldclr to recovery the
1625 * error.
1626 */
1627static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
1628{
1629 if (pwrap_is_fsm_vldclr(wrp))
1630 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1631}
1632
1633static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
1634{
1635 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
1636}
1637
1638static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
1639{
1640 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1641
1642 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
1643 (val & PWRAP_STATE_SYNC_IDLE0);
1644}
1645
1646static int pwrap_timeout_ns(unsigned long long start_time_ns,
1647 unsigned long long timeout_time_ns)
1648{
1649 unsigned long long cur_time = 0;
1650 unsigned long long elapse_time = 0;
1651
1652 /* get current tick */
1653 cur_time = sched_clock(); /* ns */
1654
1655 /* avoid timer over flow exiting in FPGA env */
1656 if (cur_time < start_time_ns)
1657 start_time_ns = cur_time;
1658
1659 elapse_time = cur_time - start_time_ns;
1660
1661 /* check if timeout */
1662 if (timeout_time_ns <= elapse_time) {
1663 dev_notice(wrp->dev,
1664 "[PWRAP] Timeout start time: %lld\n", start_time_ns);
1665 dev_notice(wrp->dev,
1666 "[PWRAP] Timeout cur time: %lld\n", cur_time);
1667 dev_notice(wrp->dev,
1668 "[PWRAP] Timeout elapse time: %lld\n", elapse_time);
1669 dev_notice(wrp->dev,
1670 "[PWRAP] Timeout set timeout: %lld\n", timeout_time_ns);
1671 return 1;
1672 }
1673 return 0;
1674}
1675
1676static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
1677 bool (*fp)(struct pmic_wrapper *))
1678{
1679 unsigned long long start_time_ns = 0, timeout_ns = 0;
1680
1681 start_time_ns = sched_clock();
1682 timeout_ns = 10000 * 1000; /* 10000us */
1683
1684 do {
1685 if (pwrap_timeout_ns(start_time_ns, timeout_ns)) {
1686 if (fp(wrp))
1687 return 0;
1688 else if ((pwrap_readl(wrp,
1689 PWRAP_MPU_PMIC_ACC_VIO_INFO_0)
1690 & 0x20000000) != 0) {
1691 /* check if timeout is caused by mpu vio */
1692 dev_dbg(wrp->dev,
1693 "[PWRAP] FSM Timeout MPU Violation\n");
1694 return 1;
1695 } else if (fp(wrp) == 0) {
1696 dev_notice(wrp->dev, "[PWRAP] FSM Timeout\n");
1697 pwrap_dump_busy_register();
1698 /* TBD
1699 * aee_kernel_warning("PWRAP:FSM Timeout",
1700 * "PWRAP");
1701 */
1702 return -ETIMEDOUT;
1703 }
1704 }
1705 if (fp(wrp))
1706 return 0;
1707 } while (1);
1708}
1709
1710static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1711{
1712 int ret = 0;
1713
1714 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1715 if (ret) {
1716 pwrap_leave_fsm_vldclr(wrp);
1717 return ret;
1718 }
1719
1720 pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
1721
1722 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1723 if (ret)
1724 return ret;
1725
1726 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
1727
1728 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1729
1730 return 0;
1731}
1732
1733static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1734{
1735 int ret, msb;
1736
1737 *rdata = 0;
1738 for (msb = 0; msb < 2; msb++) {
1739 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1740 if (ret) {
1741 pwrap_leave_fsm_vldclr(wrp);
1742 return ret;
1743 }
1744
1745 pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
1746 PWRAP_WACS2_CMD);
1747
1748 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1749 if (ret)
1750 return ret;
1751
1752 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
1753 PWRAP_WACS2_RDATA)) << (16 * msb));
1754
1755 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1756 }
1757
1758 return 0;
1759}
1760
1761static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1762{
1763 return wrp->slave->pwrap_read(wrp, adr, rdata);
1764}
1765
1766static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1767{
1768 int ret = 0;
1769
1770 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1771 if (ret) {
1772 pwrap_leave_fsm_vldclr(wrp);
1773 return ret;
1774 }
1775
1776 pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
1777 PWRAP_WACS2_CMD);
1778
1779 return 0;
1780}
1781
1782static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1783{
1784 int ret, msb, rdata;
1785
1786 for (msb = 0; msb < 2; msb++) {
1787 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1788 if (ret) {
1789 pwrap_leave_fsm_vldclr(wrp);
1790 return ret;
1791 }
1792
1793 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
1794 ((wdata >> (msb * 16)) & 0xffff),
1795 PWRAP_WACS2_CMD);
1796
1797 /*
1798 * The pwrap_read operation is the requirement of hardware used
1799 * for the synchronization between two successive 16-bit
1800 * pwrap_writel operations composing one 32-bit bus writing.
1801 * Otherwise, we'll find the result fails on the lower 16-bit
1802 * pwrap writing.
1803 */
1804 if (!msb)
1805 pwrap_read(wrp, adr, &rdata);
1806 }
1807
1808 return 0;
1809}
1810
1811static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1812{
1813 return wrp->slave->pwrap_write(wrp, adr, wdata);
1814}
1815
1816static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
1817{
1818 return pwrap_read(context, adr, rdata);
1819}
1820
1821static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
1822{
1823 return pwrap_write(context, adr, wdata);
1824}
1825
1826static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
1827{
1828 int ret = 0, i = 0;
1829
1830 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
1831 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
1832 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
1833 pwrap_writel(wrp, 1, PWRAP_MAN_EN);
1834 pwrap_writel(wrp, 0, PWRAP_DIO_EN);
1835
1836 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
1837 PWRAP_MAN_CMD);
1838 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1839 PWRAP_MAN_CMD);
1840 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
1841 PWRAP_MAN_CMD);
1842
1843 for (i = 0; i < 4; i++)
1844 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1845 PWRAP_MAN_CMD);
1846
1847 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
1848 if (ret) {
1849 dev_dbg(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1850 return ret;
1851 }
1852
1853 pwrap_writel(wrp, 0, PWRAP_MAN_EN);
1854 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
1855
1856 return 0;
1857}
1858
1859/*
1860 * pwrap_init_sidly - configure serial input delay
1861 *
1862 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
1863 * delay. Do a read test with all possible values and chose the best delay.
1864 */
1865static int pwrap_init_sidly(struct pmic_wrapper *wrp)
1866{
1867 u32 rdata = 0;
1868 u32 i = 0;
1869 u32 pass = 0;
1870 signed char dly[16] = {
1871 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
1872 };
1873
1874 for (i = 0; i < 4; i++) {
1875 pwrap_writel(wrp, i, PWRAP_SIDLY);
1876 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
1877 &rdata);
1878 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
1879 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
1880 pass |= 1 << i;
1881 }
1882 }
1883
1884 if (dly[pass] < 0) {
1885 dev_dbg(wrp->dev, "sidly pass range 0x%x not continuous\n",
1886 pass);
1887 return -EIO;
1888 }
1889
1890 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
1891
1892 return 0;
1893}
1894
1895static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
1896{
1897 int ret = 0;
1898 u32 rdata = 0;
1899
1900 /* Enable dual IO mode */
1901 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
1902
1903 /* Check IDLE & INIT_DONE in advance */
1904 ret = pwrap_wait_for_state(wrp,
1905 pwrap_is_fsm_idle_and_sync_idle);
1906 if (ret) {
1907 dev_dbg(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1908 return ret;
1909 }
1910
1911 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
1912
1913 /* Read Test */
1914 pwrap_read(wrp,
1915 wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
1916 if (rdata != PWRAP_DEW_READ_TEST_VAL) {
1917 dev_dbg(wrp->dev,
1918 "Read failed on DIO mode: 0x%04x!=0x%04x\n",
1919 PWRAP_DEW_READ_TEST_VAL, rdata);
1920 return -EFAULT;
1921 }
1922
1923 return 0;
1924}
1925
1926/*
1927 * pwrap_init_chip_select_ext is used to configure CS extension time for each
1928 * phase during data transactions on the pwrap bus.
1929 */
1930static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
1931 u8 hext_read, u8 lext_start,
1932 u8 lext_end)
1933{
1934 /*
1935 * After finishing a write and read transaction, extends CS high time
1936 * to be at least xT of BUS CLK as hext_write and hext_read specifies
1937 * respectively.
1938 */
1939 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
1940 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
1941
1942 /*
1943 * Extends CS low time after CSL and before CSH command to be at
1944 * least xT of BUS CLK as lext_start and lext_end specifies
1945 * respectively.
1946 */
1947 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
1948 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
1949}
1950
1951static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
1952{
1953 switch (wrp->master->type) {
1954
1955 case PWRAP_MT2731:
1956 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1957 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
1958 pwrap_init_chip_select_ext(wrp, 0x88, 0x55, 3, 0);
1959 break;
1960 case PWRAP_MT8173:
1961 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
1962 break;
1963 case PWRAP_MT8135:
1964 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1965 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
1966 break;
1967 default:
1968 break;
1969 }
1970
1971 return 0;
1972}
1973
1974static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
1975{
1976 switch (wrp->slave->type) {
1977 case PMIC_MT6397:
1978 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
1979 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
1980 break;
1981
1982 case PMIC_MT6323:
1983 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1984 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
1985 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
1986 break;
1987 default:
1988 break;
1989 }
1990
1991 return 0;
1992}
1993
1994static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
1995{
1996 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
1997}
1998
1999static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
2000{
2001 u32 rdata = 0;
2002 int ret = 0;
2003
2004 ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
2005 &rdata);
2006 if (ret)
2007 return 0;
2008
2009 return rdata == 1;
2010}
2011
2012static int pwrap_init_cipher(struct pmic_wrapper *wrp)
2013{
2014 int ret = 0;
2015 u32 rdata = 0;
2016
2017 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
2018 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
2019 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
2020 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
2021
2022 switch (wrp->master->type) {
2023 case PWRAP_MT8135:
2024 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
2025 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
2026 break;
2027 case PWRAP_MT2701:
2028 case PWRAP_MT2731:
2029 case PWRAP_MT8173:
2030 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
2031 break;
2032 case PWRAP_MT7622:
2033 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
2034 break;
2035 default:
2036 break;
2037 }
2038
2039 /* Config cipher mode @PMIC */
2040 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
2041 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
2042 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
2043 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
2044
2045 switch (wrp->slave->type) {
2046 case PMIC_MT6397:
2047 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
2048 0x1);
2049 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
2050 0x1);
2051 break;
2052 case PMIC_MT6323:
2053 case PMIC_MT6356:
2054 case PMIC_MT6389:
2055 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
2056 0x1);
2057 break;
2058 default:
2059 break;
2060 }
2061
2062 /* wait for cipher data ready@AP */
2063 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
2064 if (ret) {
2065 dev_dbg(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
2066 return ret;
2067 }
2068
2069 /* wait for cipher data ready@PMIC */
2070 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
2071 if (ret) {
2072 dev_dbg(wrp->dev,
2073 "timeout waiting for cipher data ready@PMIC\n");
2074 return ret;
2075 }
2076
2077 /* wait for cipher mode idle */
2078 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
2079 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
2080 if (ret) {
2081 dev_dbg(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
2082 return ret;
2083 }
2084
2085 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
2086
2087 /* Write Test */
2088 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
2089 PWRAP_DEW_WRITE_TEST_VAL) ||
2090 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
2091 &rdata) ||
2092 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
2093 dev_dbg(wrp->dev, "rdata=0x%04X\n", rdata);
2094 return -EFAULT;
2095 }
2096
2097 return 0;
2098}
2099
2100static int pwrap_init_security(struct pmic_wrapper *wrp)
2101{
2102 int ret = 0;
2103
2104 /* Enable encryption */
2105 ret = pwrap_init_cipher(wrp);
2106 if (ret)
2107 return ret;
2108
2109 /* Signature checking - using CRC */
2110 if (pwrap_write(wrp,
2111 wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
2112 return -EFAULT;
2113
2114 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
2115 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
2116 pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
2117 PWRAP_SIG_ADR);
2118 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
2119
2120 return 0;
2121}
2122
2123static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
2124{
2125 /* enable pwrap events and pwrap bridge in AP side */
2126 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
2127 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
2128 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
2129 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
2130 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
2131 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
2132 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
2133 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
2134 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
2135
2136 /* enable PMIC event out and sources */
2137 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
2138 0x1) ||
2139 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
2140 0xffff)) {
2141 dev_dbg(wrp->dev, "enable dewrap fail\n");
2142 return -EFAULT;
2143 }
2144
2145 return 0;
2146}
2147
2148static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
2149{
2150 /* PMIC_DEWRAP enables */
2151 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
2152 0x1) ||
2153 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
2154 0xffff)) {
2155 dev_dbg(wrp->dev, "enable dewrap fail\n");
2156 return -EFAULT;
2157 }
2158
2159 return 0;
2160}
2161
2162static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
2163{
2164 /* GPS_INTF initialization */
2165 switch (wrp->slave->type) {
2166 case PMIC_MT6323:
2167 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
2168 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
2169 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
2170 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
2171 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
2172 break;
2173 default:
2174 break;
2175 }
2176
2177 return 0;
2178}
2179
2180static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
2181{
2182 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
2183 /* enable 2wire SPI master */
2184 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
2185
2186 return 0;
2187}
2188
2189static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
2190{
2191 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
2192
2193 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
2194 pwrap_writel(wrp, 1, PWRAP_CRC_EN);
2195 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
2196 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
2197
2198 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
2199 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
2200 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
2201 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
2202
2203 return 0;
2204}
2205
2206/*
2207 * pwrap_set_starvation is used to configure starvation counter for dynamic
2208 * adjust channel arbiter priority.
2209 */
2210static int pwrap_set_starvation(struct pmic_wrapper *wrp)
2211{
2212 pwrap_writel(wrp, 0xf, PWRAP_HARB_HPRIO);
2213 pwrap_writel(wrp, 0x402, PWRAP_STARV_COUNTER_0);
2214 pwrap_writel(wrp, 0x403, PWRAP_STARV_COUNTER_1);
2215 pwrap_writel(wrp, 0x403, PWRAP_STARV_COUNTER_2);
2216 pwrap_writel(wrp, 0x403, PWRAP_STARV_COUNTER_3);
2217 pwrap_writel(wrp, 0x40f, PWRAP_STARV_COUNTER_4);
2218 pwrap_writel(wrp, 0x420, PWRAP_STARV_COUNTER_5);
2219 pwrap_writel(wrp, 0x428, PWRAP_STARV_COUNTER_6);
2220 pwrap_writel(wrp, 0x428, PWRAP_STARV_COUNTER_7);
2221 pwrap_writel(wrp, 0x413, PWRAP_STARV_COUNTER_8);
2222 pwrap_writel(wrp, 0x417, PWRAP_STARV_COUNTER_9);
2223 pwrap_writel(wrp, 0x417, PWRAP_STARV_COUNTER_10);
2224 pwrap_writel(wrp, 0x47c, PWRAP_STARV_COUNTER_11);
2225 pwrap_writel(wrp, 0x47c, PWRAP_STARV_COUNTER_12);
2226 pwrap_writel(wrp, 0x740, PWRAP_STARV_COUNTER_13);
2227 pwrap_writel(wrp, 0x740, PWRAP_STARV_COUNTER_16);
2228
2229 return 0;
2230}
2231
2232static int pwrap_init(struct pmic_wrapper *wrp)
2233{
2234 int ret;
2235
2236 reset_control_reset(wrp->rstc);
2237 if (wrp->rstc_bridge)
2238 reset_control_reset(wrp->rstc_bridge);
2239
2240 if (wrp->master->type == PWRAP_MT8173) {
2241 /* Enable DCM */
2242 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
2243 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2244 }
2245
2246 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
2247 /* Reset SPI slave */
2248 ret = pwrap_reset_spislave(wrp);
2249 if (ret)
2250 return ret;
2251 }
2252
2253 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
2254
2255 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
2256
2257 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
2258
2259 ret = wrp->master->init_reg_clock(wrp);
2260 if (ret)
2261 return ret;
2262
2263 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
2264 /* Setup serial input delay */
2265 ret = pwrap_init_sidly(wrp);
2266 if (ret)
2267 return ret;
2268 }
2269
2270 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
2271 /* Enable dual I/O mode */
2272 ret = pwrap_init_dual_io(wrp);
2273 if (ret)
2274 return ret;
2275 }
2276
2277 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
2278 /* Enable security on bus */
2279 ret = pwrap_init_security(wrp);
2280 if (ret)
2281 return ret;
2282 }
2283
2284 if (wrp->master->type == PWRAP_MT8135)
2285 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
2286
2287 /* Add priority adjust setting, it used to avoid starvation */
2288 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_PRIORITY_SEL)) {
2289 pwrap_writel(wrp, 0x0b09080a, PWRAP_PRIORITY_USER_SEL_2);
2290 pwrap_writel(wrp, 0x0b080a09, PWRAP_ARBITER_OUT_SEL_2);
2291 pwrap_set_starvation(wrp);
2292 }
2293
2294 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
2295 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
2296 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
2297 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
2298 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
2299
2300 if (wrp->master->init_soc_specific) {
2301 ret = wrp->master->init_soc_specific(wrp);
2302 if (ret)
2303 return ret;
2304 }
2305
2306 /* Setup the init done registers */
2307 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
2308 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
2309 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
2310
2311 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
2312 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
2313 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
2314 }
2315
2316 return 0;
2317}
2318
2319static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
2320{
2321 u32 rdata = 0, int0_flg = 0, int1_flg = 0, ret = 0;
2322 u32 wdt0_src_en = 0, wdt0_flg = 0, wdt1_src_en = 0, wdt1_flg = 0;
2323 struct pmic_wrapper *wrp = dev_id;
2324 const struct pwrap_slv_type *slv = wrp->slave;
2325
2326 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
2327 int0_flg = pwrap_readl(wrp, PWRAP_INT0_FLG);
2328 if ((int0_flg & 0xffffffff) != 0) {
2329 dev_notice(wrp->dev,
2330 "[PWRAP] INT0 error:0x%x\n", int0_flg);
2331 pwrap_writel(wrp, int0_flg, PWRAP_INT0_CLR);
2332 /* need to enable after SQC debug
2333 *if ((int0_flg & 0x02) == 0x02)
2334 * exec_ccci_kern_func_by_md_id
2335 * (MD_SYS1, ID_FORCE_MD_ASSERT, NULL, 0);
2336 */
2337 }
2338 int1_flg = pwrap_readl(wrp, PWRAP_INT1_FLG);
2339 if ((int1_flg & 0xffffffff) != 0) {
2340 dev_notice(wrp->dev,
2341 "[PWRAP] INT1 error:0x%x\n", int1_flg);
2342
2343 if ((int1_flg & (0x3 << 11)) != 0) {
2344 dev_dbg(wrp->dev,
2345 "[PWRAP] MPU Access Violation\n");
2346 pwrap_mpu_info();
2347 pwrap_dump_ap_cmd_logging_register();
2348 pwrap_dump_pmic_cmd_logging_register();
2349 /* TBD
2350 * aee_kernel_warning("PWRAP:MPU Violation",
2351 * "PWRAP");
2352 */
2353 pwrap_writel(wrp, int1_flg, PWRAP_INT1_CLR);
2354 } else {
2355 pwrap_dump_busy_register();
2356 pwrap_writel(wrp, 0xffffe7ff, PWRAP_INT1_CLR);
2357 }
2358 }
2359
2360 if ((int0_flg & 0x01) == 0x01) {
2361 wdt0_src_en = pwrap_readl(wrp, PWRAP_WDT_SRC_EN);
2362 wdt1_src_en = pwrap_readl(wrp, PWRAP_WDT_SRC_EN_1);
2363 wdt0_flg = pwrap_readl(wrp, PWRAP_WDT_FLG);
2364 wdt1_flg = pwrap_readl(wrp, PWRAP_WDT_FLG_1);
2365 dev_notice(wrp->dev, "[PWRAP] WDT Timeout\n");
2366 dev_notice(wrp->dev,
2367 "[PWRAP] WDT_SRC_EN_0=0x%x\n", wdt0_src_en);
2368 dev_notice(wrp->dev,
2369 "[PWRAP] WDT_SRC_EN_1=0x%x\n", wdt1_src_en);
2370 dev_notice(wrp->dev,
2371 "[PWRAP] WDT_FLG_0=0x%x\n", wdt0_flg);
2372 dev_notice(wrp->dev,
2373 "[PWRAP] WDT_FLG_1=0x%x\n", wdt1_flg);
2374 if ((wdt0_flg & 0x4000) == 0x4000) {
2375 dev_notice(wrp->dev,
2376 "[PWRAP] MD DVFS HW Timeout\n");
2377 pwrap_dump_ap_register();
2378 pwrap_dump_pmic_cmd_logging_register();
2379 /* TBD
2380 * aee_kernel_warning("PWRAP:WDT MD DVFS HW Timeout",
2381 * "PWRAP:WDT MD DVFS HW Timeout");
2382 */
2383 }
2384 } else if ((int0_flg & 0x02) == 0x02) {
2385 dev_dbg(wrp->dev, "[PWRAP] CRC Error\n");
2386 pwrap_dump_ap_cmd_logging_register();
2387 pwrap_dump_pmic_cmd_logging_register();
2388 /* TBD
2389 *snprintf(str, 50, "PWRAP CRC=0x%x",
2390 * pwrap_readl(wrp, PWRAP_SIG_ERRVAL));
2391 *aee_kernel_warning(str, str);
2392 */
2393 pwrap_writel(wrp, wrp->master->int_en_all,
2394 PWRAP_INT_EN);
2395 /* Clear spislv CRC sta */
2396 ret = pwrap_write(wrp,
2397 slv->dew_regs[PWRAP_DEW_CRC_SWRST], 0x1);
2398 if (ret != 0)
2399 dev_dbg(wrp->dev, "clr fail, ret=%x\n", ret);
2400 ret = pwrap_write(wrp,
2401 slv->dew_regs[PWRAP_DEW_CRC_SWRST], 0x0);
2402 if (ret != 0)
2403 dev_dbg(wrp->dev, "clr fail, ret=%x\n", ret);
2404 pwrap_write(wrp, slv->dew_regs[PWRAP_DEW_CRC_EN], 0x0);
2405 pwrap_writel(wrp, 0x0, PWRAP_CRC_EN);
2406 pwrap_writel(wrp,
2407 pwrap_readl(wrp, PWRAP_STAUPD_GRPEN) & 0x1fe,
2408 PWRAP_STAUPD_GRPEN);
2409 }
2410 } else {
2411 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
2412
2413 dev_dbg(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
2414
2415 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
2416 }
2417 return IRQ_HANDLED;
2418}
2419
2420static const struct regmap_config pwrap_regmap_config16 = {
2421 .reg_bits = 16,
2422 .val_bits = 16,
2423 .reg_stride = 2,
2424 .reg_read = pwrap_regmap_read,
2425 .reg_write = pwrap_regmap_write,
2426 .max_register = 0xffff,
2427 .fast_io = true,
2428};
2429
2430static const struct regmap_config pwrap_regmap_config32 = {
2431 .reg_bits = 32,
2432 .val_bits = 32,
2433 .reg_stride = 4,
2434 .reg_read = pwrap_regmap_read,
2435 .reg_write = pwrap_regmap_write,
2436 .max_register = 0xffff,
2437 .fast_io = true,
2438};
2439
2440static const struct pwrap_slv_type pmic_mt6323 = {
2441 .dew_regs = mt6323_regs,
2442 .type = PMIC_MT6323,
2443 .regmap = &pwrap_regmap_config16,
2444 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
2445 PWRAP_SLV_CAP_SECURITY,
2446 .pwrap_read = pwrap_read16,
2447 .pwrap_write = pwrap_write16,
2448};
2449
2450static const struct pwrap_slv_type pmic_mt6356 = {
2451 .dew_regs = mt6356_regs,
2452 .type = PMIC_MT6356,
2453 .regmap = &pwrap_regmap_config16,
2454 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
2455 .pwrap_read = pwrap_read16,
2456 .pwrap_write = pwrap_write16,
2457};
2458
2459static const struct pwrap_slv_type pmic_mt6358 = {
2460 .dew_regs = mt6358_regs,
2461 .type = PMIC_MT6358,
2462 .regmap = &pwrap_regmap_config16,
2463 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
2464 .pwrap_read = pwrap_read16,
2465 .pwrap_write = pwrap_write16,
2466};
2467
2468static const struct pwrap_slv_type pmic_mt6380 = {
2469 .dew_regs = NULL,
2470 .type = PMIC_MT6380,
2471 .regmap = &pwrap_regmap_config32,
2472 .caps = 0,
2473 .pwrap_read = pwrap_read32,
2474 .pwrap_write = pwrap_write32,
2475};
2476
2477static const struct pwrap_slv_type pmic_mt6389 = {
2478 .dew_regs = mt6389_regs,
2479 .type = PMIC_MT6389,
2480 .regmap = &pwrap_regmap_config16,
2481 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
2482 .pwrap_read = pwrap_read16,
2483 .pwrap_write = pwrap_write16,
2484};
2485
2486static const struct pwrap_slv_type pmic_mt6397 = {
2487 .dew_regs = mt6397_regs,
2488 .type = PMIC_MT6397,
2489 .regmap = &pwrap_regmap_config16,
2490 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
2491 PWRAP_SLV_CAP_SECURITY,
2492 .pwrap_read = pwrap_read16,
2493 .pwrap_write = pwrap_write16,
2494};
2495
2496static const struct of_device_id of_slave_match_tbl[] = {
2497 {
2498 .compatible = "mediatek,mt6323",
2499 .data = &pmic_mt6323,
2500 }, {
2501 .compatible = "mediatek,mt6356-pmic",
2502 .data = &pmic_mt6356,
2503 }, {
2504 .compatible = "mediatek,mt6358-pmic",
2505 .data = &pmic_mt6358,
2506 }, {
2507 /* The MT6380 PMIC only implements a regulator, so we bind it
2508 * directly instead of using a MFD.
2509 */
2510 .compatible = "mediatek,mt6380-regulator",
2511 .data = &pmic_mt6380,
2512 }, {
2513 .compatible = "mediatek,mt6389-pmic",
2514 .data = &pmic_mt6389,
2515 }, {
2516 .compatible = "mediatek,mt6397",
2517 .data = &pmic_mt6397,
2518 /* sentinel */
2519 }
2520};
2521MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
2522
2523static const struct pmic_wrapper_type pwrap_mt2701 = {
2524 .regs = mt2701_regs,
2525 .type = PWRAP_MT2701,
2526 .arb_en_all = 0x3f,
2527 .int_en_all = ~(u32)(BIT(31) | BIT(2)),
2528 .int1_en_all = 0,
2529 .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
2530 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2531 .has_bridge = 0,
2532 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2533 .init_reg_clock = pwrap_mt2701_init_reg_clock,
2534 .init_soc_specific = pwrap_mt2701_init_soc_specific,
2535};
2536
2537static const struct pmic_wrapper_type pwrap_mt2731 = {
2538 .regs = mt2731_regs,
2539 .type = PWRAP_MT2731,
2540 .arb_en_all = 0x67D37,
2541 .int_en_all = 0xffffffff,
2542 .int1_en_all = 0x000017ff,
2543 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2544 .wdt_src = 0x00000000,
2545 .has_bridge = 0,
2546 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_MON_V1,
2547 .init_reg_clock = pwrap_common_init_reg_clock,
2548 .init_soc_specific = NULL,
2549};
2550
2551static const struct pmic_wrapper_type pwrap_mt7622 = {
2552 .regs = mt7622_regs,
2553 .type = PWRAP_MT7622,
2554 .arb_en_all = 0xff,
2555 .int_en_all = ~(u32)BIT(31),
2556 .int1_en_all = 0,
2557 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2558 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2559 .has_bridge = 0,
2560 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2561 .init_reg_clock = pwrap_common_init_reg_clock,
2562 .init_soc_specific = pwrap_mt7622_init_soc_specific,
2563};
2564
2565static const struct pmic_wrapper_type pwrap_mt8135 = {
2566 .regs = mt8135_regs,
2567 .type = PWRAP_MT8135,
2568 .arb_en_all = 0x1ff,
2569 .int_en_all = ~(u32)(BIT(31) | BIT(1)),
2570 .int1_en_all = 0,
2571 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2572 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2573 .has_bridge = 1,
2574 .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2575 .init_reg_clock = pwrap_common_init_reg_clock,
2576 .init_soc_specific = pwrap_mt8135_init_soc_specific,
2577};
2578
2579static const struct pmic_wrapper_type pwrap_mt8173 = {
2580 .regs = mt8173_regs,
2581 .type = PWRAP_MT8173,
2582 .arb_en_all = 0x3f,
2583 .int_en_all = ~(u32)(BIT(31) | BIT(1)),
2584 .int1_en_all = 0,
2585 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2586 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
2587 .has_bridge = 0,
2588 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2589 .init_reg_clock = pwrap_common_init_reg_clock,
2590 .init_soc_specific = pwrap_mt8173_init_soc_specific,
2591};
2592
2593static const struct pmic_wrapper_type pwrap_mt8183 = {
2594 .regs = mt8183_regs,
2595 .type = PWRAP_MT8183,
2596 .arb_en_all = 0x3fa75,
2597 .int_en_all = 0xffffffff,
2598 .int1_en_all = 0xeef7ffff,
2599 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2600 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2601 .has_bridge = 0,
2602 .caps = PWRAP_CAP_PRIORITY_SEL | PWRAP_CAP_INT1_EN |
2603 PWRAP_CAP_WDT_SRC1,
2604 .init_reg_clock = pwrap_common_init_reg_clock,
2605 .init_soc_specific = pwrap_mt8183_init_soc_specific,
2606};
2607
2608static const struct of_device_id of_pwrap_match_tbl[] = {
2609 {
2610 .compatible = "mediatek,mt2701-pwrap",
2611 .data = &pwrap_mt2701,
2612 }, {
2613 .compatible = "mediatek,mt2731-pwrap",
2614 .data = &pwrap_mt2731,
2615 }, {
2616 .compatible = "mediatek,mt7622-pwrap",
2617 .data = &pwrap_mt7622,
2618 }, {
2619 .compatible = "mediatek,mt8135-pwrap",
2620 .data = &pwrap_mt8135,
2621 }, {
2622 .compatible = "mediatek,mt8173-pwrap",
2623 .data = &pwrap_mt8173,
2624 }, {
2625 .compatible = "mediatek,mt8183-pwrap",
2626 .data = &pwrap_mt8183,
2627 }, {
2628 /* sentinel */
2629 }
2630};
2631MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
2632
2633struct regmap *pwrap_node_to_regmap(struct device_node *np)
2634{
2635 struct platform_device *pdev;
2636 struct pmic_wrapper *wrp;
2637
2638 pdev = of_find_device_by_node(np);
2639
2640 if (!pdev)
2641 return ERR_PTR(-ENODEV);
2642
2643 wrp = platform_get_drvdata(pdev);
2644
2645 if (!wrp)
2646 return ERR_PTR(-ENODEV);
2647
2648 return wrp->regmap;
2649}
2650EXPORT_SYMBOL_GPL(pwrap_node_to_regmap);
2651
2652/********************************************************************/
2653/* return value : EINT_STA: [0]: CPU IRQ status in PMIC1 */
2654/* [1]: MD32 IRQ status in PMIC1 */
2655/* [2]: CPU IRQ status in PMIC2 */
2656/* [3]: RESERVED */
2657/********************************************************************/
2658u32 pmic_wrap_eint_status(void)
2659{
2660 dev_dbg(wrp->dev,
2661 "%s:0x%x\n", __func__,
2662 pwrap_readl(wrp, PWRAP_EINT_STA));
2663 return pwrap_readl(wrp, PWRAP_EINT_STA);
2664}
2665EXPORT_SYMBOL(pmic_wrap_eint_status);
2666
2667/********************************************************************/
2668/* set value(W1C) : EINT_CLR: [0]: CPU IRQ status in PMIC1 */
2669/* [1]: MD32 IRQ status in PMIC1 */
2670/* [2]: CPU IRQ status in PMIC2 */
2671/* [3]: RESERVED */
2672/* para: offset is shift of clear bit which needs to clear */
2673/********************************************************************/
2674void pmic_wrap_eint_clr(int offset)
2675{
2676 dev_dbg(wrp->dev, "%s\n", __func__);
2677 pwrap_writel(wrp, offset, PWRAP_EINT_CLR);
2678}
2679EXPORT_SYMBOL(pmic_wrap_eint_clr);
2680static int pwrap_probe(struct platform_device *pdev)
2681{
2682 int ret = 0, irq = 0;
2683 u32 rdata = 0;
2684 struct device_node *np = pdev->dev.of_node;
2685 const struct of_device_id *of_slave_id = NULL;
2686 struct resource *res;
2687
2688 if (np->child)
2689 of_slave_id = of_match_node(of_slave_match_tbl, np->child);
2690
2691 if (!of_slave_id) {
2692 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
2693 return -EINVAL;
2694 }
2695
2696 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
2697 if (!wrp)
2698 return -ENOMEM;
2699
2700 platform_set_drvdata(pdev, wrp);
2701
2702 wrp->master = of_device_get_match_data(&pdev->dev);
2703 wrp->slave = of_slave_id->data;
2704 wrp->dev = &pdev->dev;
2705
2706 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
2707 wrp->base = devm_ioremap_resource(wrp->dev, res);
2708 if (IS_ERR(wrp->base))
2709 return PTR_ERR(wrp->base);
2710
2711 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
2712 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
2713 if (IS_ERR(wrp->rstc)) {
2714 ret = PTR_ERR(wrp->rstc);
2715 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
2716 return ret;
2717 }
2718 }
2719
2720 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
2721 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2722 "pwrap-bridge");
2723 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
2724 if (IS_ERR(wrp->bridge_base))
2725 return PTR_ERR(wrp->bridge_base);
2726
2727 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
2728 "pwrap-bridge");
2729 if (IS_ERR(wrp->rstc_bridge)) {
2730 ret = PTR_ERR(wrp->rstc_bridge);
2731 dev_dbg(wrp->dev,
2732 "cannot get pwrap-bridge reset: %d\n", ret);
2733 return ret;
2734 }
2735 }
2736
2737 wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
2738 if (IS_ERR(wrp->clk_spi)) {
2739 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2740 PTR_ERR(wrp->clk_spi));
2741 return PTR_ERR(wrp->clk_spi);
2742 }
2743
2744 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
2745 if (IS_ERR(wrp->clk_wrap)) {
2746 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2747 PTR_ERR(wrp->clk_wrap));
2748 return PTR_ERR(wrp->clk_wrap);
2749 }
2750
2751 ret = clk_prepare_enable(wrp->clk_spi);
2752 if (ret)
2753 return ret;
2754
2755 ret = clk_prepare_enable(wrp->clk_wrap);
2756 if (ret)
2757 goto err_out1;
2758
2759 /*
2760 * add dcm capability check
2761 */
2762 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
2763 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
2764 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2765 }
2766
2767 /*
2768 * The PMIC could already be initialized by the bootloader.
2769 * Skip initialization here in this case.
2770 */
2771 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
2772 ret = pwrap_init(wrp);
2773 if (ret) {
2774 dev_dbg(wrp->dev, "init failed with %d\n", ret);
2775 goto err_out2;
2776 }
2777 }
2778
2779 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
2780 dev_dbg(wrp->dev, "initialization isn't finished\n");
2781 ret = -ENODEV;
2782 goto err_out2;
2783 }
2784
2785 /* Initialize watchdog, may not be done by the bootloader */
2786 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MON_V1))
2787 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
2788 /*
2789 * Since STAUPD was not used on mt8173 platform,
2790 * so STAUPD of WDT_SRC which should be turned off
2791 */
2792 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
2793
2794 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_MON_V1))
2795 pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN);
2796 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
2797 /*
2798 * We add INT1 interrupt to handle starvation and request exception
2799 * If we support it, we should enable them here.
2800 */
2801 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
2802 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
2803
2804 irq = platform_get_irq(pdev, 0);
2805 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
2806 IRQF_TRIGGER_HIGH, "mt-pmic-pwrap", wrp);
2807 if (ret)
2808 goto err_out2;
2809
2810 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
2811 if (IS_ERR(wrp->regmap)) {
2812 ret = PTR_ERR(wrp->regmap);
2813 goto err_out2;
2814 }
2815
2816 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
2817 if (ret) {
2818 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
2819 np);
2820 goto err_out2;
2821 }
2822
2823 /* Write Test */
2824 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
2825 PWRAP_DEW_WRITE_TEST_VAL) ||
2826 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
2827 &rdata) ||
2828 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
2829 dev_dbg(wrp->dev, "pwrap rdata=0x%04X\n", rdata);
2830 goto err_out2;
2831 } else {
2832 dev_dbg(wrp->dev, "[PWRAP] R/W PASS rdata=0x%04X\n", rdata);
2833 }
2834
2835
2836 return 0;
2837
2838err_out2:
2839 clk_disable_unprepare(wrp->clk_wrap);
2840err_out1:
2841 clk_disable_unprepare(wrp->clk_spi);
2842
2843 return ret;
2844}
2845
2846static int pwrap_remove(struct platform_device *pdev)
2847{
2848 return 0;
2849}
2850
2851static struct platform_driver pwrap_drv = {
2852 .driver = {
2853 .name = "mt-pmic-pwrap",
2854 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
2855 },
2856 .probe = pwrap_probe,
2857 .remove = pwrap_remove,
2858};
2859
2860static int __init pwrap_soc_init(void)
2861{
2862 int ret = 0;
2863
2864 ret = platform_driver_register(&pwrap_drv);
2865 if (ret)
2866 return -ENODEV;
2867 return 0;
2868}
2869postcore_initcall(pwrap_soc_init);
2870
2871MODULE_AUTHOR("Flora Fu, MediaTek");
2872MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
2873MODULE_LICENSE("GPL v2");