| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | if ARCH_TEGRA |
| 2 | |
| 3 | # 32-bit ARM SoCs |
| 4 | if ARM |
| 5 | |
| 6 | config ARCH_TEGRA_2x_SOC |
| 7 | bool "Enable support for Tegra20 family" |
| 8 | select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP |
| 9 | select ARM_ERRATA_720789 |
| 10 | select ARM_ERRATA_754327 if SMP |
| 11 | select ARM_ERRATA_764369 if SMP |
| 12 | select PINCTRL_TEGRA20 |
| 13 | select PL310_ERRATA_727915 if CACHE_L2X0 |
| 14 | select PL310_ERRATA_769419 if CACHE_L2X0 |
| 15 | select SOC_TEGRA_FLOWCTRL |
| 16 | select SOC_TEGRA_PMC |
| 17 | select TEGRA_TIMER |
| 18 | help |
| 19 | Support for NVIDIA Tegra AP20 and T20 processors, based on the |
| 20 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |
| 21 | |
| 22 | config ARCH_TEGRA_3x_SOC |
| 23 | bool "Enable support for Tegra30 family" |
| 24 | select ARM_ERRATA_754322 |
| 25 | select ARM_ERRATA_764369 if SMP |
| 26 | select PINCTRL_TEGRA30 |
| 27 | select PL310_ERRATA_769419 if CACHE_L2X0 |
| 28 | select SOC_TEGRA_FLOWCTRL |
| 29 | select SOC_TEGRA_PMC |
| 30 | select TEGRA_TIMER |
| 31 | help |
| 32 | Support for NVIDIA Tegra T30 processor family, based on the |
| 33 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |
| 34 | |
| 35 | config ARCH_TEGRA_114_SOC |
| 36 | bool "Enable support for Tegra114 family" |
| 37 | select ARM_ERRATA_798181 if SMP |
| 38 | select HAVE_ARM_ARCH_TIMER |
| 39 | select PINCTRL_TEGRA114 |
| 40 | select SOC_TEGRA_FLOWCTRL |
| 41 | select SOC_TEGRA_PMC |
| 42 | select TEGRA_TIMER |
| 43 | help |
| 44 | Support for NVIDIA Tegra T114 processor family, based on the |
| 45 | ARM CortexA15MP CPU |
| 46 | |
| 47 | config ARCH_TEGRA_124_SOC |
| 48 | bool "Enable support for Tegra124 family" |
| 49 | select HAVE_ARM_ARCH_TIMER |
| 50 | select PINCTRL_TEGRA124 |
| 51 | select SOC_TEGRA_FLOWCTRL |
| 52 | select SOC_TEGRA_PMC |
| 53 | select TEGRA_TIMER |
| 54 | help |
| 55 | Support for NVIDIA Tegra T124 processor family, based on the |
| 56 | ARM CortexA15MP CPU |
| 57 | |
| 58 | endif |
| 59 | |
| 60 | # 64-bit ARM SoCs |
| 61 | if ARM64 |
| 62 | |
| 63 | config ARCH_TEGRA_132_SOC |
| 64 | bool "NVIDIA Tegra132 SoC" |
| 65 | select PINCTRL_TEGRA124 |
| 66 | select SOC_TEGRA_FLOWCTRL |
| 67 | select SOC_TEGRA_PMC |
| 68 | help |
| 69 | Enable support for NVIDIA Tegra132 SoC, based on the Denver |
| 70 | ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, |
| 71 | but contains an NVIDIA Denver CPU complex in place of |
| 72 | Tegra124's "4+1" Cortex-A15 CPU complex. |
| 73 | |
| 74 | config ARCH_TEGRA_210_SOC |
| 75 | bool "NVIDIA Tegra210 SoC" |
| 76 | select PINCTRL_TEGRA210 |
| 77 | select SOC_TEGRA_FLOWCTRL |
| 78 | select SOC_TEGRA_PMC |
| 79 | help |
| 80 | Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, |
| 81 | the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 |
| 82 | cores in a switched configuration. It features a GPU of the Maxwell |
| 83 | architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 |
| 84 | and providing 256 CUDA cores. It supports hardware-accelerated en- |
| 85 | and decoding of various video standards including H.265, H.264 and |
| 86 | VP8 at 4K resolution and up to 60 fps. |
| 87 | |
| 88 | Besides the multimedia features it also comes with a variety of I/O |
| 89 | controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to |
| 90 | name only a few. |
| 91 | |
| 92 | config ARCH_TEGRA_186_SOC |
| 93 | bool "NVIDIA Tegra186 SoC" |
| 94 | select MAILBOX |
| 95 | select TEGRA_BPMP |
| 96 | select TEGRA_HSP_MBOX |
| 97 | select TEGRA_IVC |
| 98 | select SOC_TEGRA_PMC_TEGRA186 |
| 99 | help |
| 100 | Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a |
| 101 | combination of Denver and Cortex-A57 CPU cores and a GPU based on |
| 102 | the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU |
| 103 | used for audio processing, hardware video encoders/decoders with |
| 104 | multi-format support, ISP for image capture processing and BPMP for |
| 105 | power management. |
| 106 | |
| 107 | endif |
| 108 | endif |
| 109 | |
| 110 | config SOC_TEGRA_FUSE |
| 111 | def_bool y |
| 112 | depends on ARCH_TEGRA |
| 113 | select SOC_BUS |
| 114 | |
| 115 | config SOC_TEGRA_FLOWCTRL |
| 116 | bool |
| 117 | |
| 118 | config SOC_TEGRA_PMC |
| 119 | bool |
| 120 | |
| 121 | config SOC_TEGRA_PMC_TEGRA186 |
| 122 | bool |
| 123 | |
| 124 | config SOC_TEGRA_POWERGATE_BPMP |
| 125 | def_bool y |
| 126 | depends on PM_GENERIC_DOMAINS |
| 127 | depends on TEGRA_BPMP |