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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / kernel / linux / v4.14 / drivers / tty / synclink_gt.c
blob: 9d68f89a2bf8dac451c452445c70f513ec7645c2 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/*
2 * Device driver for Microgate SyncLink GT serial adapters.
3 *
4 * written by Paul Fulghum for Microgate Corporation
5 * paulkf@microgate.com
6 *
7 * Microgate and SyncLink are trademarks of Microgate Corporation
8 *
9 * This code is released under the GNU General Public License (GPL)
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
22 */
23
24/*
25 * DEBUG OUTPUT DEFINITIONS
26 *
27 * uncomment lines below to enable specific types of debug output
28 *
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
36 */
37
38#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43/*#define DBGTBUF(info) dump_tbufs(info)*/
44/*#define DBGRBUF(info) dump_rbufs(info)*/
45
46
47#include <linux/module.h>
48#include <linux/errno.h>
49#include <linux/signal.h>
50#include <linux/sched.h>
51#include <linux/timer.h>
52#include <linux/interrupt.h>
53#include <linux/pci.h>
54#include <linux/tty.h>
55#include <linux/tty_flip.h>
56#include <linux/serial.h>
57#include <linux/major.h>
58#include <linux/string.h>
59#include <linux/fcntl.h>
60#include <linux/ptrace.h>
61#include <linux/ioport.h>
62#include <linux/mm.h>
63#include <linux/seq_file.h>
64#include <linux/slab.h>
65#include <linux/netdevice.h>
66#include <linux/vmalloc.h>
67#include <linux/init.h>
68#include <linux/delay.h>
69#include <linux/ioctl.h>
70#include <linux/termios.h>
71#include <linux/bitops.h>
72#include <linux/workqueue.h>
73#include <linux/hdlc.h>
74#include <linux/synclink.h>
75
76#include <asm/io.h>
77#include <asm/irq.h>
78#include <asm/dma.h>
79#include <asm/types.h>
80#include <linux/uaccess.h>
81
82#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
83#define SYNCLINK_GENERIC_HDLC 1
84#else
85#define SYNCLINK_GENERIC_HDLC 0
86#endif
87
88/*
89 * module identification
90 */
91static char *driver_name = "SyncLink GT";
92static char *slgt_driver_name = "synclink_gt";
93static char *tty_dev_prefix = "ttySLG";
94MODULE_LICENSE("GPL");
95#define MGSL_MAGIC 0x5401
96#define MAX_DEVICES 32
97
98static const struct pci_device_id pci_table[] = {
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {0,}, /* terminate list */
104};
105MODULE_DEVICE_TABLE(pci, pci_table);
106
107static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
108static void remove_one(struct pci_dev *dev);
109static struct pci_driver pci_driver = {
110 .name = "synclink_gt",
111 .id_table = pci_table,
112 .probe = init_one,
113 .remove = remove_one,
114};
115
116static bool pci_registered;
117
118/*
119 * module configuration and status
120 */
121static struct slgt_info *slgt_device_list;
122static int slgt_device_count;
123
124static int ttymajor;
125static int debug_level;
126static int maxframe[MAX_DEVICES];
127
128module_param(ttymajor, int, 0);
129module_param(debug_level, int, 0);
130module_param_array(maxframe, int, NULL, 0);
131
132MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
133MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
134MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
135
136/*
137 * tty support and callbacks
138 */
139static struct tty_driver *serial_driver;
140
141static int open(struct tty_struct *tty, struct file * filp);
142static void close(struct tty_struct *tty, struct file * filp);
143static void hangup(struct tty_struct *tty);
144static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
145
146static int write(struct tty_struct *tty, const unsigned char *buf, int count);
147static int put_char(struct tty_struct *tty, unsigned char ch);
148static void send_xchar(struct tty_struct *tty, char ch);
149static void wait_until_sent(struct tty_struct *tty, int timeout);
150static int write_room(struct tty_struct *tty);
151static void flush_chars(struct tty_struct *tty);
152static void flush_buffer(struct tty_struct *tty);
153static void tx_hold(struct tty_struct *tty);
154static void tx_release(struct tty_struct *tty);
155
156static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
157static int chars_in_buffer(struct tty_struct *tty);
158static void throttle(struct tty_struct * tty);
159static void unthrottle(struct tty_struct * tty);
160static int set_break(struct tty_struct *tty, int break_state);
161
162/*
163 * generic HDLC support and callbacks
164 */
165#if SYNCLINK_GENERIC_HDLC
166#define dev_to_port(D) (dev_to_hdlc(D)->priv)
167static void hdlcdev_tx_done(struct slgt_info *info);
168static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
169static int hdlcdev_init(struct slgt_info *info);
170static void hdlcdev_exit(struct slgt_info *info);
171#endif
172
173
174/*
175 * device specific structures, macros and functions
176 */
177
178#define SLGT_MAX_PORTS 4
179#define SLGT_REG_SIZE 256
180
181/*
182 * conditional wait facility
183 */
184struct cond_wait {
185 struct cond_wait *next;
186 wait_queue_head_t q;
187 wait_queue_entry_t wait;
188 unsigned int data;
189};
190static void init_cond_wait(struct cond_wait *w, unsigned int data);
191static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
192static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
193static void flush_cond_wait(struct cond_wait **head);
194
195/*
196 * DMA buffer descriptor and access macros
197 */
198struct slgt_desc
199{
200 __le16 count;
201 __le16 status;
202 __le32 pbuf; /* physical address of data buffer */
203 __le32 next; /* physical address of next descriptor */
204
205 /* driver book keeping */
206 char *buf; /* virtual address of data buffer */
207 unsigned int pdesc; /* physical address of this descriptor */
208 dma_addr_t buf_dma_addr;
209 unsigned short buf_count;
210};
211
212#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
213#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
214#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
215#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
216#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
217#define desc_count(a) (le16_to_cpu((a).count))
218#define desc_status(a) (le16_to_cpu((a).status))
219#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
220#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
221#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
222#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
223#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
224
225struct _input_signal_events {
226 int ri_up;
227 int ri_down;
228 int dsr_up;
229 int dsr_down;
230 int dcd_up;
231 int dcd_down;
232 int cts_up;
233 int cts_down;
234};
235
236/*
237 * device instance data structure
238 */
239struct slgt_info {
240 void *if_ptr; /* General purpose pointer (used by SPPP) */
241 struct tty_port port;
242
243 struct slgt_info *next_device; /* device list link */
244
245 int magic;
246
247 char device_name[25];
248 struct pci_dev *pdev;
249
250 int port_count; /* count of ports on adapter */
251 int adapter_num; /* adapter instance number */
252 int port_num; /* port instance number */
253
254 /* array of pointers to port contexts on this adapter */
255 struct slgt_info *port_array[SLGT_MAX_PORTS];
256
257 int line; /* tty line instance number */
258
259 struct mgsl_icount icount;
260
261 int timeout;
262 int x_char; /* xon/xoff character */
263 unsigned int read_status_mask;
264 unsigned int ignore_status_mask;
265
266 wait_queue_head_t status_event_wait_q;
267 wait_queue_head_t event_wait_q;
268 struct timer_list tx_timer;
269 struct timer_list rx_timer;
270
271 unsigned int gpio_present;
272 struct cond_wait *gpio_wait_q;
273
274 spinlock_t lock; /* spinlock for synchronizing with ISR */
275
276 struct work_struct task;
277 u32 pending_bh;
278 bool bh_requested;
279 bool bh_running;
280
281 int isr_overflow;
282 bool irq_requested; /* true if IRQ requested */
283 bool irq_occurred; /* for diagnostics use */
284
285 /* device configuration */
286
287 unsigned int bus_type;
288 unsigned int irq_level;
289 unsigned long irq_flags;
290
291 unsigned char __iomem * reg_addr; /* memory mapped registers address */
292 u32 phys_reg_addr;
293 bool reg_addr_requested;
294
295 MGSL_PARAMS params; /* communications parameters */
296 u32 idle_mode;
297 u32 max_frame_size; /* as set by device config */
298
299 unsigned int rbuf_fill_level;
300 unsigned int rx_pio;
301 unsigned int if_mode;
302 unsigned int base_clock;
303 unsigned int xsync;
304 unsigned int xctrl;
305
306 /* device status */
307
308 bool rx_enabled;
309 bool rx_restart;
310
311 bool tx_enabled;
312 bool tx_active;
313
314 unsigned char signals; /* serial signal states */
315 int init_error; /* initialization error */
316
317 unsigned char *tx_buf;
318 int tx_count;
319
320 char *flag_buf;
321 bool drop_rts_on_tx_done;
322 struct _input_signal_events input_signal_events;
323
324 int dcd_chkcount; /* check counts to prevent */
325 int cts_chkcount; /* too many IRQs if a signal */
326 int dsr_chkcount; /* is floating */
327 int ri_chkcount;
328
329 char *bufs; /* virtual address of DMA buffer lists */
330 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
331
332 unsigned int rbuf_count;
333 struct slgt_desc *rbufs;
334 unsigned int rbuf_current;
335 unsigned int rbuf_index;
336 unsigned int rbuf_fill_index;
337 unsigned short rbuf_fill_count;
338
339 unsigned int tbuf_count;
340 struct slgt_desc *tbufs;
341 unsigned int tbuf_current;
342 unsigned int tbuf_start;
343
344 unsigned char *tmp_rbuf;
345 unsigned int tmp_rbuf_count;
346
347 /* SPPP/Cisco HDLC device parts */
348
349 int netcount;
350 spinlock_t netlock;
351#if SYNCLINK_GENERIC_HDLC
352 struct net_device *netdev;
353#endif
354
355};
356
357static MGSL_PARAMS default_params = {
358 .mode = MGSL_MODE_HDLC,
359 .loopback = 0,
360 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
361 .encoding = HDLC_ENCODING_NRZI_SPACE,
362 .clock_speed = 0,
363 .addr_filter = 0xff,
364 .crc_type = HDLC_CRC_16_CCITT,
365 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
366 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
367 .data_rate = 9600,
368 .data_bits = 8,
369 .stop_bits = 1,
370 .parity = ASYNC_PARITY_NONE
371};
372
373
374#define BH_RECEIVE 1
375#define BH_TRANSMIT 2
376#define BH_STATUS 4
377#define IO_PIN_SHUTDOWN_LIMIT 100
378
379#define DMABUFSIZE 256
380#define DESC_LIST_SIZE 4096
381
382#define MASK_PARITY BIT1
383#define MASK_FRAMING BIT0
384#define MASK_BREAK BIT14
385#define MASK_OVERRUN BIT4
386
387#define GSR 0x00 /* global status */
388#define JCR 0x04 /* JTAG control */
389#define IODR 0x08 /* GPIO direction */
390#define IOER 0x0c /* GPIO interrupt enable */
391#define IOVR 0x10 /* GPIO value */
392#define IOSR 0x14 /* GPIO interrupt status */
393#define TDR 0x80 /* tx data */
394#define RDR 0x80 /* rx data */
395#define TCR 0x82 /* tx control */
396#define TIR 0x84 /* tx idle */
397#define TPR 0x85 /* tx preamble */
398#define RCR 0x86 /* rx control */
399#define VCR 0x88 /* V.24 control */
400#define CCR 0x89 /* clock control */
401#define BDR 0x8a /* baud divisor */
402#define SCR 0x8c /* serial control */
403#define SSR 0x8e /* serial status */
404#define RDCSR 0x90 /* rx DMA control/status */
405#define TDCSR 0x94 /* tx DMA control/status */
406#define RDDAR 0x98 /* rx DMA descriptor address */
407#define TDDAR 0x9c /* tx DMA descriptor address */
408#define XSR 0x40 /* extended sync pattern */
409#define XCR 0x44 /* extended control */
410
411#define RXIDLE BIT14
412#define RXBREAK BIT14
413#define IRQ_TXDATA BIT13
414#define IRQ_TXIDLE BIT12
415#define IRQ_TXUNDER BIT11 /* HDLC */
416#define IRQ_RXDATA BIT10
417#define IRQ_RXIDLE BIT9 /* HDLC */
418#define IRQ_RXBREAK BIT9 /* async */
419#define IRQ_RXOVER BIT8
420#define IRQ_DSR BIT7
421#define IRQ_CTS BIT6
422#define IRQ_DCD BIT5
423#define IRQ_RI BIT4
424#define IRQ_ALL 0x3ff0
425#define IRQ_MASTER BIT0
426
427#define slgt_irq_on(info, mask) \
428 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
429#define slgt_irq_off(info, mask) \
430 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
431
432static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
433static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
434static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
435static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
436static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
437static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
438
439static void msc_set_vcr(struct slgt_info *info);
440
441static int startup(struct slgt_info *info);
442static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
443static void shutdown(struct slgt_info *info);
444static void program_hw(struct slgt_info *info);
445static void change_params(struct slgt_info *info);
446
447static int register_test(struct slgt_info *info);
448static int irq_test(struct slgt_info *info);
449static int loopback_test(struct slgt_info *info);
450static int adapter_test(struct slgt_info *info);
451
452static void reset_adapter(struct slgt_info *info);
453static void reset_port(struct slgt_info *info);
454static void async_mode(struct slgt_info *info);
455static void sync_mode(struct slgt_info *info);
456
457static void rx_stop(struct slgt_info *info);
458static void rx_start(struct slgt_info *info);
459static void reset_rbufs(struct slgt_info *info);
460static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
461static void rdma_reset(struct slgt_info *info);
462static bool rx_get_frame(struct slgt_info *info);
463static bool rx_get_buf(struct slgt_info *info);
464
465static void tx_start(struct slgt_info *info);
466static void tx_stop(struct slgt_info *info);
467static void tx_set_idle(struct slgt_info *info);
468static unsigned int free_tbuf_count(struct slgt_info *info);
469static unsigned int tbuf_bytes(struct slgt_info *info);
470static void reset_tbufs(struct slgt_info *info);
471static void tdma_reset(struct slgt_info *info);
472static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
473
474static void get_signals(struct slgt_info *info);
475static void set_signals(struct slgt_info *info);
476static void enable_loopback(struct slgt_info *info);
477static void set_rate(struct slgt_info *info, u32 data_rate);
478
479static int bh_action(struct slgt_info *info);
480static void bh_handler(struct work_struct *work);
481static void bh_transmit(struct slgt_info *info);
482static void isr_serial(struct slgt_info *info);
483static void isr_rdma(struct slgt_info *info);
484static void isr_txeom(struct slgt_info *info, unsigned short status);
485static void isr_tdma(struct slgt_info *info);
486
487static int alloc_dma_bufs(struct slgt_info *info);
488static void free_dma_bufs(struct slgt_info *info);
489static int alloc_desc(struct slgt_info *info);
490static void free_desc(struct slgt_info *info);
491static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
493
494static int alloc_tmp_rbuf(struct slgt_info *info);
495static void free_tmp_rbuf(struct slgt_info *info);
496
497static void tx_timeout(unsigned long context);
498static void rx_timeout(unsigned long context);
499
500/*
501 * ioctl handlers
502 */
503static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
504static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
506static int get_txidle(struct slgt_info *info, int __user *idle_mode);
507static int set_txidle(struct slgt_info *info, int idle_mode);
508static int tx_enable(struct slgt_info *info, int enable);
509static int tx_abort(struct slgt_info *info);
510static int rx_enable(struct slgt_info *info, int enable);
511static int modem_input_wait(struct slgt_info *info,int arg);
512static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
513static int tiocmget(struct tty_struct *tty);
514static int tiocmset(struct tty_struct *tty,
515 unsigned int set, unsigned int clear);
516static int set_break(struct tty_struct *tty, int break_state);
517static int get_interface(struct slgt_info *info, int __user *if_mode);
518static int set_interface(struct slgt_info *info, int if_mode);
519static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
522static int get_xsync(struct slgt_info *info, int __user *if_mode);
523static int set_xsync(struct slgt_info *info, int if_mode);
524static int get_xctrl(struct slgt_info *info, int __user *if_mode);
525static int set_xctrl(struct slgt_info *info, int if_mode);
526
527/*
528 * driver functions
529 */
530static void add_device(struct slgt_info *info);
531static void device_init(int adapter_num, struct pci_dev *pdev);
532static int claim_resources(struct slgt_info *info);
533static void release_resources(struct slgt_info *info);
534
535/*
536 * DEBUG OUTPUT CODE
537 */
538#ifndef DBGINFO
539#define DBGINFO(fmt)
540#endif
541#ifndef DBGERR
542#define DBGERR(fmt)
543#endif
544#ifndef DBGBH
545#define DBGBH(fmt)
546#endif
547#ifndef DBGISR
548#define DBGISR(fmt)
549#endif
550
551#ifdef DBGDATA
552static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
553{
554 int i;
555 int linecount;
556 printk("%s %s data:\n",info->device_name, label);
557 while(count) {
558 linecount = (count > 16) ? 16 : count;
559 for(i=0; i < linecount; i++)
560 printk("%02X ",(unsigned char)data[i]);
561 for(;i<17;i++)
562 printk(" ");
563 for(i=0;i<linecount;i++) {
564 if (data[i]>=040 && data[i]<=0176)
565 printk("%c",data[i]);
566 else
567 printk(".");
568 }
569 printk("\n");
570 data += linecount;
571 count -= linecount;
572 }
573}
574#else
575#define DBGDATA(info, buf, size, label)
576#endif
577
578#ifdef DBGTBUF
579static void dump_tbufs(struct slgt_info *info)
580{
581 int i;
582 printk("tbuf_current=%d\n", info->tbuf_current);
583 for (i=0 ; i < info->tbuf_count ; i++) {
584 printk("%d: count=%04X status=%04X\n",
585 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
586 }
587}
588#else
589#define DBGTBUF(info)
590#endif
591
592#ifdef DBGRBUF
593static void dump_rbufs(struct slgt_info *info)
594{
595 int i;
596 printk("rbuf_current=%d\n", info->rbuf_current);
597 for (i=0 ; i < info->rbuf_count ; i++) {
598 printk("%d: count=%04X status=%04X\n",
599 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
600 }
601}
602#else
603#define DBGRBUF(info)
604#endif
605
606static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
607{
608#ifdef SANITY_CHECK
609 if (!info) {
610 printk("null struct slgt_info for (%s) in %s\n", devname, name);
611 return 1;
612 }
613 if (info->magic != MGSL_MAGIC) {
614 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
615 return 1;
616 }
617#else
618 if (!info)
619 return 1;
620#endif
621 return 0;
622}
623
624/**
625 * line discipline callback wrappers
626 *
627 * The wrappers maintain line discipline references
628 * while calling into the line discipline.
629 *
630 * ldisc_receive_buf - pass receive data to line discipline
631 */
632static void ldisc_receive_buf(struct tty_struct *tty,
633 const __u8 *data, char *flags, int count)
634{
635 struct tty_ldisc *ld;
636 if (!tty)
637 return;
638 ld = tty_ldisc_ref(tty);
639 if (ld) {
640 if (ld->ops->receive_buf)
641 ld->ops->receive_buf(tty, data, flags, count);
642 tty_ldisc_deref(ld);
643 }
644}
645
646/* tty callbacks */
647
648static int open(struct tty_struct *tty, struct file *filp)
649{
650 struct slgt_info *info;
651 int retval, line;
652 unsigned long flags;
653
654 line = tty->index;
655 if (line >= slgt_device_count) {
656 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
657 return -ENODEV;
658 }
659
660 info = slgt_device_list;
661 while(info && info->line != line)
662 info = info->next_device;
663 if (sanity_check(info, tty->name, "open"))
664 return -ENODEV;
665 if (info->init_error) {
666 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
667 return -ENODEV;
668 }
669
670 tty->driver_data = info;
671 info->port.tty = tty;
672
673 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
674
675 mutex_lock(&info->port.mutex);
676 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
677
678 spin_lock_irqsave(&info->netlock, flags);
679 if (info->netcount) {
680 retval = -EBUSY;
681 spin_unlock_irqrestore(&info->netlock, flags);
682 mutex_unlock(&info->port.mutex);
683 goto cleanup;
684 }
685 info->port.count++;
686 spin_unlock_irqrestore(&info->netlock, flags);
687
688 if (info->port.count == 1) {
689 /* 1st open on this device, init hardware */
690 retval = startup(info);
691 if (retval < 0) {
692 mutex_unlock(&info->port.mutex);
693 goto cleanup;
694 }
695 }
696 mutex_unlock(&info->port.mutex);
697 retval = block_til_ready(tty, filp, info);
698 if (retval) {
699 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
700 goto cleanup;
701 }
702
703 retval = 0;
704
705cleanup:
706 if (retval) {
707 if (tty->count == 1)
708 info->port.tty = NULL; /* tty layer will release tty struct */
709 if(info->port.count)
710 info->port.count--;
711 }
712
713 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
714 return retval;
715}
716
717static void close(struct tty_struct *tty, struct file *filp)
718{
719 struct slgt_info *info = tty->driver_data;
720
721 if (sanity_check(info, tty->name, "close"))
722 return;
723 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
724
725 if (tty_port_close_start(&info->port, tty, filp) == 0)
726 goto cleanup;
727
728 mutex_lock(&info->port.mutex);
729 if (tty_port_initialized(&info->port))
730 wait_until_sent(tty, info->timeout);
731 flush_buffer(tty);
732 tty_ldisc_flush(tty);
733
734 shutdown(info);
735 mutex_unlock(&info->port.mutex);
736
737 tty_port_close_end(&info->port, tty);
738 info->port.tty = NULL;
739cleanup:
740 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
741}
742
743static void hangup(struct tty_struct *tty)
744{
745 struct slgt_info *info = tty->driver_data;
746 unsigned long flags;
747
748 if (sanity_check(info, tty->name, "hangup"))
749 return;
750 DBGINFO(("%s hangup\n", info->device_name));
751
752 flush_buffer(tty);
753
754 mutex_lock(&info->port.mutex);
755 shutdown(info);
756
757 spin_lock_irqsave(&info->port.lock, flags);
758 info->port.count = 0;
759 info->port.tty = NULL;
760 spin_unlock_irqrestore(&info->port.lock, flags);
761 tty_port_set_active(&info->port, 0);
762 mutex_unlock(&info->port.mutex);
763
764 wake_up_interruptible(&info->port.open_wait);
765}
766
767static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
768{
769 struct slgt_info *info = tty->driver_data;
770 unsigned long flags;
771
772 DBGINFO(("%s set_termios\n", tty->driver->name));
773
774 change_params(info);
775
776 /* Handle transition to B0 status */
777 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
778 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
779 spin_lock_irqsave(&info->lock,flags);
780 set_signals(info);
781 spin_unlock_irqrestore(&info->lock,flags);
782 }
783
784 /* Handle transition away from B0 status */
785 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
786 info->signals |= SerialSignal_DTR;
787 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
788 info->signals |= SerialSignal_RTS;
789 spin_lock_irqsave(&info->lock,flags);
790 set_signals(info);
791 spin_unlock_irqrestore(&info->lock,flags);
792 }
793
794 /* Handle turning off CRTSCTS */
795 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
796 tty->hw_stopped = 0;
797 tx_release(tty);
798 }
799}
800
801static void update_tx_timer(struct slgt_info *info)
802{
803 /*
804 * use worst case speed of 1200bps to calculate transmit timeout
805 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
806 */
807 if (info->params.mode == MGSL_MODE_HDLC) {
808 int timeout = (tbuf_bytes(info) * 7) + 1000;
809 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
810 }
811}
812
813static int write(struct tty_struct *tty,
814 const unsigned char *buf, int count)
815{
816 int ret = 0;
817 struct slgt_info *info = tty->driver_data;
818 unsigned long flags;
819
820 if (sanity_check(info, tty->name, "write"))
821 return -EIO;
822
823 DBGINFO(("%s write count=%d\n", info->device_name, count));
824
825 if (!info->tx_buf || (count > info->max_frame_size))
826 return -EIO;
827
828 if (!count || tty->stopped || tty->hw_stopped)
829 return 0;
830
831 spin_lock_irqsave(&info->lock, flags);
832
833 if (info->tx_count) {
834 /* send accumulated data from send_char() */
835 if (!tx_load(info, info->tx_buf, info->tx_count))
836 goto cleanup;
837 info->tx_count = 0;
838 }
839
840 if (tx_load(info, buf, count))
841 ret = count;
842
843cleanup:
844 spin_unlock_irqrestore(&info->lock, flags);
845 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
846 return ret;
847}
848
849static int put_char(struct tty_struct *tty, unsigned char ch)
850{
851 struct slgt_info *info = tty->driver_data;
852 unsigned long flags;
853 int ret = 0;
854
855 if (sanity_check(info, tty->name, "put_char"))
856 return 0;
857 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
858 if (!info->tx_buf)
859 return 0;
860 spin_lock_irqsave(&info->lock,flags);
861 if (info->tx_count < info->max_frame_size) {
862 info->tx_buf[info->tx_count++] = ch;
863 ret = 1;
864 }
865 spin_unlock_irqrestore(&info->lock,flags);
866 return ret;
867}
868
869static void send_xchar(struct tty_struct *tty, char ch)
870{
871 struct slgt_info *info = tty->driver_data;
872 unsigned long flags;
873
874 if (sanity_check(info, tty->name, "send_xchar"))
875 return;
876 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
877 info->x_char = ch;
878 if (ch) {
879 spin_lock_irqsave(&info->lock,flags);
880 if (!info->tx_enabled)
881 tx_start(info);
882 spin_unlock_irqrestore(&info->lock,flags);
883 }
884}
885
886static void wait_until_sent(struct tty_struct *tty, int timeout)
887{
888 struct slgt_info *info = tty->driver_data;
889 unsigned long orig_jiffies, char_time;
890
891 if (!info )
892 return;
893 if (sanity_check(info, tty->name, "wait_until_sent"))
894 return;
895 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
896 if (!tty_port_initialized(&info->port))
897 goto exit;
898
899 orig_jiffies = jiffies;
900
901 /* Set check interval to 1/5 of estimated time to
902 * send a character, and make it at least 1. The check
903 * interval should also be less than the timeout.
904 * Note: use tight timings here to satisfy the NIST-PCTS.
905 */
906
907 if (info->params.data_rate) {
908 char_time = info->timeout/(32 * 5);
909 if (!char_time)
910 char_time++;
911 } else
912 char_time = 1;
913
914 if (timeout)
915 char_time = min_t(unsigned long, char_time, timeout);
916
917 while (info->tx_active) {
918 msleep_interruptible(jiffies_to_msecs(char_time));
919 if (signal_pending(current))
920 break;
921 if (timeout && time_after(jiffies, orig_jiffies + timeout))
922 break;
923 }
924exit:
925 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
926}
927
928static int write_room(struct tty_struct *tty)
929{
930 struct slgt_info *info = tty->driver_data;
931 int ret;
932
933 if (sanity_check(info, tty->name, "write_room"))
934 return 0;
935 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
936 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
937 return ret;
938}
939
940static void flush_chars(struct tty_struct *tty)
941{
942 struct slgt_info *info = tty->driver_data;
943 unsigned long flags;
944
945 if (sanity_check(info, tty->name, "flush_chars"))
946 return;
947 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
948
949 if (info->tx_count <= 0 || tty->stopped ||
950 tty->hw_stopped || !info->tx_buf)
951 return;
952
953 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
954
955 spin_lock_irqsave(&info->lock,flags);
956 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
957 info->tx_count = 0;
958 spin_unlock_irqrestore(&info->lock,flags);
959}
960
961static void flush_buffer(struct tty_struct *tty)
962{
963 struct slgt_info *info = tty->driver_data;
964 unsigned long flags;
965
966 if (sanity_check(info, tty->name, "flush_buffer"))
967 return;
968 DBGINFO(("%s flush_buffer\n", info->device_name));
969
970 spin_lock_irqsave(&info->lock, flags);
971 info->tx_count = 0;
972 spin_unlock_irqrestore(&info->lock, flags);
973
974 tty_wakeup(tty);
975}
976
977/*
978 * throttle (stop) transmitter
979 */
980static void tx_hold(struct tty_struct *tty)
981{
982 struct slgt_info *info = tty->driver_data;
983 unsigned long flags;
984
985 if (sanity_check(info, tty->name, "tx_hold"))
986 return;
987 DBGINFO(("%s tx_hold\n", info->device_name));
988 spin_lock_irqsave(&info->lock,flags);
989 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
990 tx_stop(info);
991 spin_unlock_irqrestore(&info->lock,flags);
992}
993
994/*
995 * release (start) transmitter
996 */
997static void tx_release(struct tty_struct *tty)
998{
999 struct slgt_info *info = tty->driver_data;
1000 unsigned long flags;
1001
1002 if (sanity_check(info, tty->name, "tx_release"))
1003 return;
1004 DBGINFO(("%s tx_release\n", info->device_name));
1005 spin_lock_irqsave(&info->lock, flags);
1006 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1007 info->tx_count = 0;
1008 spin_unlock_irqrestore(&info->lock, flags);
1009}
1010
1011/*
1012 * Service an IOCTL request
1013 *
1014 * Arguments
1015 *
1016 * tty pointer to tty instance data
1017 * cmd IOCTL command code
1018 * arg command argument/context
1019 *
1020 * Return 0 if success, otherwise error code
1021 */
1022static int ioctl(struct tty_struct *tty,
1023 unsigned int cmd, unsigned long arg)
1024{
1025 struct slgt_info *info = tty->driver_data;
1026 void __user *argp = (void __user *)arg;
1027 int ret;
1028
1029 if (sanity_check(info, tty->name, "ioctl"))
1030 return -ENODEV;
1031 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1032
1033 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1034 (cmd != TIOCMIWAIT)) {
1035 if (tty_io_error(tty))
1036 return -EIO;
1037 }
1038
1039 switch (cmd) {
1040 case MGSL_IOCWAITEVENT:
1041 return wait_mgsl_event(info, argp);
1042 case TIOCMIWAIT:
1043 return modem_input_wait(info,(int)arg);
1044 case MGSL_IOCSGPIO:
1045 return set_gpio(info, argp);
1046 case MGSL_IOCGGPIO:
1047 return get_gpio(info, argp);
1048 case MGSL_IOCWAITGPIO:
1049 return wait_gpio(info, argp);
1050 case MGSL_IOCGXSYNC:
1051 return get_xsync(info, argp);
1052 case MGSL_IOCSXSYNC:
1053 return set_xsync(info, (int)arg);
1054 case MGSL_IOCGXCTRL:
1055 return get_xctrl(info, argp);
1056 case MGSL_IOCSXCTRL:
1057 return set_xctrl(info, (int)arg);
1058 }
1059 mutex_lock(&info->port.mutex);
1060 switch (cmd) {
1061 case MGSL_IOCGPARAMS:
1062 ret = get_params(info, argp);
1063 break;
1064 case MGSL_IOCSPARAMS:
1065 ret = set_params(info, argp);
1066 break;
1067 case MGSL_IOCGTXIDLE:
1068 ret = get_txidle(info, argp);
1069 break;
1070 case MGSL_IOCSTXIDLE:
1071 ret = set_txidle(info, (int)arg);
1072 break;
1073 case MGSL_IOCTXENABLE:
1074 ret = tx_enable(info, (int)arg);
1075 break;
1076 case MGSL_IOCRXENABLE:
1077 ret = rx_enable(info, (int)arg);
1078 break;
1079 case MGSL_IOCTXABORT:
1080 ret = tx_abort(info);
1081 break;
1082 case MGSL_IOCGSTATS:
1083 ret = get_stats(info, argp);
1084 break;
1085 case MGSL_IOCGIF:
1086 ret = get_interface(info, argp);
1087 break;
1088 case MGSL_IOCSIF:
1089 ret = set_interface(info,(int)arg);
1090 break;
1091 default:
1092 ret = -ENOIOCTLCMD;
1093 }
1094 mutex_unlock(&info->port.mutex);
1095 return ret;
1096}
1097
1098static int get_icount(struct tty_struct *tty,
1099 struct serial_icounter_struct *icount)
1100
1101{
1102 struct slgt_info *info = tty->driver_data;
1103 struct mgsl_icount cnow; /* kernel counter temps */
1104 unsigned long flags;
1105
1106 spin_lock_irqsave(&info->lock,flags);
1107 cnow = info->icount;
1108 spin_unlock_irqrestore(&info->lock,flags);
1109
1110 icount->cts = cnow.cts;
1111 icount->dsr = cnow.dsr;
1112 icount->rng = cnow.rng;
1113 icount->dcd = cnow.dcd;
1114 icount->rx = cnow.rx;
1115 icount->tx = cnow.tx;
1116 icount->frame = cnow.frame;
1117 icount->overrun = cnow.overrun;
1118 icount->parity = cnow.parity;
1119 icount->brk = cnow.brk;
1120 icount->buf_overrun = cnow.buf_overrun;
1121
1122 return 0;
1123}
1124
1125/*
1126 * support for 32 bit ioctl calls on 64 bit systems
1127 */
1128#ifdef CONFIG_COMPAT
1129static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1130{
1131 struct MGSL_PARAMS32 tmp_params;
1132
1133 DBGINFO(("%s get_params32\n", info->device_name));
1134 memset(&tmp_params, 0, sizeof(tmp_params));
1135 tmp_params.mode = (compat_ulong_t)info->params.mode;
1136 tmp_params.loopback = info->params.loopback;
1137 tmp_params.flags = info->params.flags;
1138 tmp_params.encoding = info->params.encoding;
1139 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1140 tmp_params.addr_filter = info->params.addr_filter;
1141 tmp_params.crc_type = info->params.crc_type;
1142 tmp_params.preamble_length = info->params.preamble_length;
1143 tmp_params.preamble = info->params.preamble;
1144 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1145 tmp_params.data_bits = info->params.data_bits;
1146 tmp_params.stop_bits = info->params.stop_bits;
1147 tmp_params.parity = info->params.parity;
1148 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1149 return -EFAULT;
1150 return 0;
1151}
1152
1153static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1154{
1155 struct MGSL_PARAMS32 tmp_params;
1156
1157 DBGINFO(("%s set_params32\n", info->device_name));
1158 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1159 return -EFAULT;
1160
1161 spin_lock(&info->lock);
1162 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1163 info->base_clock = tmp_params.clock_speed;
1164 } else {
1165 info->params.mode = tmp_params.mode;
1166 info->params.loopback = tmp_params.loopback;
1167 info->params.flags = tmp_params.flags;
1168 info->params.encoding = tmp_params.encoding;
1169 info->params.clock_speed = tmp_params.clock_speed;
1170 info->params.addr_filter = tmp_params.addr_filter;
1171 info->params.crc_type = tmp_params.crc_type;
1172 info->params.preamble_length = tmp_params.preamble_length;
1173 info->params.preamble = tmp_params.preamble;
1174 info->params.data_rate = tmp_params.data_rate;
1175 info->params.data_bits = tmp_params.data_bits;
1176 info->params.stop_bits = tmp_params.stop_bits;
1177 info->params.parity = tmp_params.parity;
1178 }
1179 spin_unlock(&info->lock);
1180
1181 program_hw(info);
1182
1183 return 0;
1184}
1185
1186static long slgt_compat_ioctl(struct tty_struct *tty,
1187 unsigned int cmd, unsigned long arg)
1188{
1189 struct slgt_info *info = tty->driver_data;
1190 int rc;
1191
1192 if (sanity_check(info, tty->name, "compat_ioctl"))
1193 return -ENODEV;
1194 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1195
1196 switch (cmd) {
1197 case MGSL_IOCSPARAMS32:
1198 rc = set_params32(info, compat_ptr(arg));
1199 break;
1200
1201 case MGSL_IOCGPARAMS32:
1202 rc = get_params32(info, compat_ptr(arg));
1203 break;
1204
1205 case MGSL_IOCGPARAMS:
1206 case MGSL_IOCSPARAMS:
1207 case MGSL_IOCGTXIDLE:
1208 case MGSL_IOCGSTATS:
1209 case MGSL_IOCWAITEVENT:
1210 case MGSL_IOCGIF:
1211 case MGSL_IOCSGPIO:
1212 case MGSL_IOCGGPIO:
1213 case MGSL_IOCWAITGPIO:
1214 case MGSL_IOCGXSYNC:
1215 case MGSL_IOCGXCTRL:
1216 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1217 break;
1218 default:
1219 rc = ioctl(tty, cmd, arg);
1220 }
1221 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1222 return rc;
1223}
1224#else
1225#define slgt_compat_ioctl NULL
1226#endif /* ifdef CONFIG_COMPAT */
1227
1228/*
1229 * proc fs support
1230 */
1231static inline void line_info(struct seq_file *m, struct slgt_info *info)
1232{
1233 char stat_buf[30];
1234 unsigned long flags;
1235
1236 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1237 info->device_name, info->phys_reg_addr,
1238 info->irq_level, info->max_frame_size);
1239
1240 /* output current serial signal states */
1241 spin_lock_irqsave(&info->lock,flags);
1242 get_signals(info);
1243 spin_unlock_irqrestore(&info->lock,flags);
1244
1245 stat_buf[0] = 0;
1246 stat_buf[1] = 0;
1247 if (info->signals & SerialSignal_RTS)
1248 strcat(stat_buf, "|RTS");
1249 if (info->signals & SerialSignal_CTS)
1250 strcat(stat_buf, "|CTS");
1251 if (info->signals & SerialSignal_DTR)
1252 strcat(stat_buf, "|DTR");
1253 if (info->signals & SerialSignal_DSR)
1254 strcat(stat_buf, "|DSR");
1255 if (info->signals & SerialSignal_DCD)
1256 strcat(stat_buf, "|CD");
1257 if (info->signals & SerialSignal_RI)
1258 strcat(stat_buf, "|RI");
1259
1260 if (info->params.mode != MGSL_MODE_ASYNC) {
1261 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1262 info->icount.txok, info->icount.rxok);
1263 if (info->icount.txunder)
1264 seq_printf(m, " txunder:%d", info->icount.txunder);
1265 if (info->icount.txabort)
1266 seq_printf(m, " txabort:%d", info->icount.txabort);
1267 if (info->icount.rxshort)
1268 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1269 if (info->icount.rxlong)
1270 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1271 if (info->icount.rxover)
1272 seq_printf(m, " rxover:%d", info->icount.rxover);
1273 if (info->icount.rxcrc)
1274 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1275 } else {
1276 seq_printf(m, "\tASYNC tx:%d rx:%d",
1277 info->icount.tx, info->icount.rx);
1278 if (info->icount.frame)
1279 seq_printf(m, " fe:%d", info->icount.frame);
1280 if (info->icount.parity)
1281 seq_printf(m, " pe:%d", info->icount.parity);
1282 if (info->icount.brk)
1283 seq_printf(m, " brk:%d", info->icount.brk);
1284 if (info->icount.overrun)
1285 seq_printf(m, " oe:%d", info->icount.overrun);
1286 }
1287
1288 /* Append serial signal status to end */
1289 seq_printf(m, " %s\n", stat_buf+1);
1290
1291 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1292 info->tx_active,info->bh_requested,info->bh_running,
1293 info->pending_bh);
1294}
1295
1296/* Called to print information about devices
1297 */
1298static int synclink_gt_proc_show(struct seq_file *m, void *v)
1299{
1300 struct slgt_info *info;
1301
1302 seq_puts(m, "synclink_gt driver\n");
1303
1304 info = slgt_device_list;
1305 while( info ) {
1306 line_info(m, info);
1307 info = info->next_device;
1308 }
1309 return 0;
1310}
1311
1312static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1313{
1314 return single_open(file, synclink_gt_proc_show, NULL);
1315}
1316
1317static const struct file_operations synclink_gt_proc_fops = {
1318 .owner = THIS_MODULE,
1319 .open = synclink_gt_proc_open,
1320 .read = seq_read,
1321 .llseek = seq_lseek,
1322 .release = single_release,
1323};
1324
1325/*
1326 * return count of bytes in transmit buffer
1327 */
1328static int chars_in_buffer(struct tty_struct *tty)
1329{
1330 struct slgt_info *info = tty->driver_data;
1331 int count;
1332 if (sanity_check(info, tty->name, "chars_in_buffer"))
1333 return 0;
1334 count = tbuf_bytes(info);
1335 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1336 return count;
1337}
1338
1339/*
1340 * signal remote device to throttle send data (our receive data)
1341 */
1342static void throttle(struct tty_struct * tty)
1343{
1344 struct slgt_info *info = tty->driver_data;
1345 unsigned long flags;
1346
1347 if (sanity_check(info, tty->name, "throttle"))
1348 return;
1349 DBGINFO(("%s throttle\n", info->device_name));
1350 if (I_IXOFF(tty))
1351 send_xchar(tty, STOP_CHAR(tty));
1352 if (C_CRTSCTS(tty)) {
1353 spin_lock_irqsave(&info->lock,flags);
1354 info->signals &= ~SerialSignal_RTS;
1355 set_signals(info);
1356 spin_unlock_irqrestore(&info->lock,flags);
1357 }
1358}
1359
1360/*
1361 * signal remote device to stop throttling send data (our receive data)
1362 */
1363static void unthrottle(struct tty_struct * tty)
1364{
1365 struct slgt_info *info = tty->driver_data;
1366 unsigned long flags;
1367
1368 if (sanity_check(info, tty->name, "unthrottle"))
1369 return;
1370 DBGINFO(("%s unthrottle\n", info->device_name));
1371 if (I_IXOFF(tty)) {
1372 if (info->x_char)
1373 info->x_char = 0;
1374 else
1375 send_xchar(tty, START_CHAR(tty));
1376 }
1377 if (C_CRTSCTS(tty)) {
1378 spin_lock_irqsave(&info->lock,flags);
1379 info->signals |= SerialSignal_RTS;
1380 set_signals(info);
1381 spin_unlock_irqrestore(&info->lock,flags);
1382 }
1383}
1384
1385/*
1386 * set or clear transmit break condition
1387 * break_state -1=set break condition, 0=clear
1388 */
1389static int set_break(struct tty_struct *tty, int break_state)
1390{
1391 struct slgt_info *info = tty->driver_data;
1392 unsigned short value;
1393 unsigned long flags;
1394
1395 if (sanity_check(info, tty->name, "set_break"))
1396 return -EINVAL;
1397 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1398
1399 spin_lock_irqsave(&info->lock,flags);
1400 value = rd_reg16(info, TCR);
1401 if (break_state == -1)
1402 value |= BIT6;
1403 else
1404 value &= ~BIT6;
1405 wr_reg16(info, TCR, value);
1406 spin_unlock_irqrestore(&info->lock,flags);
1407 return 0;
1408}
1409
1410#if SYNCLINK_GENERIC_HDLC
1411
1412/**
1413 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1414 * set encoding and frame check sequence (FCS) options
1415 *
1416 * dev pointer to network device structure
1417 * encoding serial encoding setting
1418 * parity FCS setting
1419 *
1420 * returns 0 if success, otherwise error code
1421 */
1422static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1423 unsigned short parity)
1424{
1425 struct slgt_info *info = dev_to_port(dev);
1426 unsigned char new_encoding;
1427 unsigned short new_crctype;
1428
1429 /* return error if TTY interface open */
1430 if (info->port.count)
1431 return -EBUSY;
1432
1433 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1434
1435 switch (encoding)
1436 {
1437 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1438 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1439 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1440 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1441 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1442 default: return -EINVAL;
1443 }
1444
1445 switch (parity)
1446 {
1447 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1448 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1449 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1450 default: return -EINVAL;
1451 }
1452
1453 info->params.encoding = new_encoding;
1454 info->params.crc_type = new_crctype;
1455
1456 /* if network interface up, reprogram hardware */
1457 if (info->netcount)
1458 program_hw(info);
1459
1460 return 0;
1461}
1462
1463/**
1464 * called by generic HDLC layer to send frame
1465 *
1466 * skb socket buffer containing HDLC frame
1467 * dev pointer to network device structure
1468 */
1469static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1470 struct net_device *dev)
1471{
1472 struct slgt_info *info = dev_to_port(dev);
1473 unsigned long flags;
1474
1475 DBGINFO(("%s hdlc_xmit\n", dev->name));
1476
1477 if (!skb->len)
1478 return NETDEV_TX_OK;
1479
1480 /* stop sending until this frame completes */
1481 netif_stop_queue(dev);
1482
1483 /* update network statistics */
1484 dev->stats.tx_packets++;
1485 dev->stats.tx_bytes += skb->len;
1486
1487 /* save start time for transmit timeout detection */
1488 netif_trans_update(dev);
1489
1490 spin_lock_irqsave(&info->lock, flags);
1491 tx_load(info, skb->data, skb->len);
1492 spin_unlock_irqrestore(&info->lock, flags);
1493
1494 /* done with socket buffer, so free it */
1495 dev_kfree_skb(skb);
1496
1497 return NETDEV_TX_OK;
1498}
1499
1500/**
1501 * called by network layer when interface enabled
1502 * claim resources and initialize hardware
1503 *
1504 * dev pointer to network device structure
1505 *
1506 * returns 0 if success, otherwise error code
1507 */
1508static int hdlcdev_open(struct net_device *dev)
1509{
1510 struct slgt_info *info = dev_to_port(dev);
1511 int rc;
1512 unsigned long flags;
1513
1514 if (!try_module_get(THIS_MODULE))
1515 return -EBUSY;
1516
1517 DBGINFO(("%s hdlcdev_open\n", dev->name));
1518
1519 /* generic HDLC layer open processing */
1520 rc = hdlc_open(dev);
1521 if (rc)
1522 return rc;
1523
1524 /* arbitrate between network and tty opens */
1525 spin_lock_irqsave(&info->netlock, flags);
1526 if (info->port.count != 0 || info->netcount != 0) {
1527 DBGINFO(("%s hdlc_open busy\n", dev->name));
1528 spin_unlock_irqrestore(&info->netlock, flags);
1529 return -EBUSY;
1530 }
1531 info->netcount=1;
1532 spin_unlock_irqrestore(&info->netlock, flags);
1533
1534 /* claim resources and init adapter */
1535 if ((rc = startup(info)) != 0) {
1536 spin_lock_irqsave(&info->netlock, flags);
1537 info->netcount=0;
1538 spin_unlock_irqrestore(&info->netlock, flags);
1539 return rc;
1540 }
1541
1542 /* assert RTS and DTR, apply hardware settings */
1543 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1544 program_hw(info);
1545
1546 /* enable network layer transmit */
1547 netif_trans_update(dev);
1548 netif_start_queue(dev);
1549
1550 /* inform generic HDLC layer of current DCD status */
1551 spin_lock_irqsave(&info->lock, flags);
1552 get_signals(info);
1553 spin_unlock_irqrestore(&info->lock, flags);
1554 if (info->signals & SerialSignal_DCD)
1555 netif_carrier_on(dev);
1556 else
1557 netif_carrier_off(dev);
1558 return 0;
1559}
1560
1561/**
1562 * called by network layer when interface is disabled
1563 * shutdown hardware and release resources
1564 *
1565 * dev pointer to network device structure
1566 *
1567 * returns 0 if success, otherwise error code
1568 */
1569static int hdlcdev_close(struct net_device *dev)
1570{
1571 struct slgt_info *info = dev_to_port(dev);
1572 unsigned long flags;
1573
1574 DBGINFO(("%s hdlcdev_close\n", dev->name));
1575
1576 netif_stop_queue(dev);
1577
1578 /* shutdown adapter and release resources */
1579 shutdown(info);
1580
1581 hdlc_close(dev);
1582
1583 spin_lock_irqsave(&info->netlock, flags);
1584 info->netcount=0;
1585 spin_unlock_irqrestore(&info->netlock, flags);
1586
1587 module_put(THIS_MODULE);
1588 return 0;
1589}
1590
1591/**
1592 * called by network layer to process IOCTL call to network device
1593 *
1594 * dev pointer to network device structure
1595 * ifr pointer to network interface request structure
1596 * cmd IOCTL command code
1597 *
1598 * returns 0 if success, otherwise error code
1599 */
1600static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1601{
1602 const size_t size = sizeof(sync_serial_settings);
1603 sync_serial_settings new_line;
1604 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1605 struct slgt_info *info = dev_to_port(dev);
1606 unsigned int flags;
1607
1608 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1609
1610 /* return error if TTY interface open */
1611 if (info->port.count)
1612 return -EBUSY;
1613
1614 if (cmd != SIOCWANDEV)
1615 return hdlc_ioctl(dev, ifr, cmd);
1616
1617 memset(&new_line, 0, sizeof(new_line));
1618
1619 switch(ifr->ifr_settings.type) {
1620 case IF_GET_IFACE: /* return current sync_serial_settings */
1621
1622 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1623 if (ifr->ifr_settings.size < size) {
1624 ifr->ifr_settings.size = size; /* data size wanted */
1625 return -ENOBUFS;
1626 }
1627
1628 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1629 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1630 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1631 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1632
1633 switch (flags){
1634 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1635 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1636 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1637 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1638 default: new_line.clock_type = CLOCK_DEFAULT;
1639 }
1640
1641 new_line.clock_rate = info->params.clock_speed;
1642 new_line.loopback = info->params.loopback ? 1:0;
1643
1644 if (copy_to_user(line, &new_line, size))
1645 return -EFAULT;
1646 return 0;
1647
1648 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1649
1650 if(!capable(CAP_NET_ADMIN))
1651 return -EPERM;
1652 if (copy_from_user(&new_line, line, size))
1653 return -EFAULT;
1654
1655 switch (new_line.clock_type)
1656 {
1657 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1658 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1659 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1660 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1661 case CLOCK_DEFAULT: flags = info->params.flags &
1662 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1663 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1664 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1665 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1666 default: return -EINVAL;
1667 }
1668
1669 if (new_line.loopback != 0 && new_line.loopback != 1)
1670 return -EINVAL;
1671
1672 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1673 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1674 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1675 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1676 info->params.flags |= flags;
1677
1678 info->params.loopback = new_line.loopback;
1679
1680 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1681 info->params.clock_speed = new_line.clock_rate;
1682 else
1683 info->params.clock_speed = 0;
1684
1685 /* if network interface up, reprogram hardware */
1686 if (info->netcount)
1687 program_hw(info);
1688 return 0;
1689
1690 default:
1691 return hdlc_ioctl(dev, ifr, cmd);
1692 }
1693}
1694
1695/**
1696 * called by network layer when transmit timeout is detected
1697 *
1698 * dev pointer to network device structure
1699 */
1700static void hdlcdev_tx_timeout(struct net_device *dev)
1701{
1702 struct slgt_info *info = dev_to_port(dev);
1703 unsigned long flags;
1704
1705 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1706
1707 dev->stats.tx_errors++;
1708 dev->stats.tx_aborted_errors++;
1709
1710 spin_lock_irqsave(&info->lock,flags);
1711 tx_stop(info);
1712 spin_unlock_irqrestore(&info->lock,flags);
1713
1714 netif_wake_queue(dev);
1715}
1716
1717/**
1718 * called by device driver when transmit completes
1719 * reenable network layer transmit if stopped
1720 *
1721 * info pointer to device instance information
1722 */
1723static void hdlcdev_tx_done(struct slgt_info *info)
1724{
1725 if (netif_queue_stopped(info->netdev))
1726 netif_wake_queue(info->netdev);
1727}
1728
1729/**
1730 * called by device driver when frame received
1731 * pass frame to network layer
1732 *
1733 * info pointer to device instance information
1734 * buf pointer to buffer contianing frame data
1735 * size count of data bytes in buf
1736 */
1737static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1738{
1739 struct sk_buff *skb = dev_alloc_skb(size);
1740 struct net_device *dev = info->netdev;
1741
1742 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1743
1744 if (skb == NULL) {
1745 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1746 dev->stats.rx_dropped++;
1747 return;
1748 }
1749
1750 skb_put_data(skb, buf, size);
1751
1752 skb->protocol = hdlc_type_trans(skb, dev);
1753
1754 dev->stats.rx_packets++;
1755 dev->stats.rx_bytes += size;
1756
1757 netif_rx(skb);
1758}
1759
1760static const struct net_device_ops hdlcdev_ops = {
1761 .ndo_open = hdlcdev_open,
1762 .ndo_stop = hdlcdev_close,
1763 .ndo_start_xmit = hdlc_start_xmit,
1764 .ndo_do_ioctl = hdlcdev_ioctl,
1765 .ndo_tx_timeout = hdlcdev_tx_timeout,
1766};
1767
1768/**
1769 * called by device driver when adding device instance
1770 * do generic HDLC initialization
1771 *
1772 * info pointer to device instance information
1773 *
1774 * returns 0 if success, otherwise error code
1775 */
1776static int hdlcdev_init(struct slgt_info *info)
1777{
1778 int rc;
1779 struct net_device *dev;
1780 hdlc_device *hdlc;
1781
1782 /* allocate and initialize network and HDLC layer objects */
1783
1784 dev = alloc_hdlcdev(info);
1785 if (!dev) {
1786 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1787 return -ENOMEM;
1788 }
1789
1790 /* for network layer reporting purposes only */
1791 dev->mem_start = info->phys_reg_addr;
1792 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1793 dev->irq = info->irq_level;
1794
1795 /* network layer callbacks and settings */
1796 dev->netdev_ops = &hdlcdev_ops;
1797 dev->watchdog_timeo = 10 * HZ;
1798 dev->tx_queue_len = 50;
1799
1800 /* generic HDLC layer callbacks and settings */
1801 hdlc = dev_to_hdlc(dev);
1802 hdlc->attach = hdlcdev_attach;
1803 hdlc->xmit = hdlcdev_xmit;
1804
1805 /* register objects with HDLC layer */
1806 rc = register_hdlc_device(dev);
1807 if (rc) {
1808 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1809 free_netdev(dev);
1810 return rc;
1811 }
1812
1813 info->netdev = dev;
1814 return 0;
1815}
1816
1817/**
1818 * called by device driver when removing device instance
1819 * do generic HDLC cleanup
1820 *
1821 * info pointer to device instance information
1822 */
1823static void hdlcdev_exit(struct slgt_info *info)
1824{
1825 unregister_hdlc_device(info->netdev);
1826 free_netdev(info->netdev);
1827 info->netdev = NULL;
1828}
1829
1830#endif /* ifdef CONFIG_HDLC */
1831
1832/*
1833 * get async data from rx DMA buffers
1834 */
1835static void rx_async(struct slgt_info *info)
1836{
1837 struct mgsl_icount *icount = &info->icount;
1838 unsigned int start, end;
1839 unsigned char *p;
1840 unsigned char status;
1841 struct slgt_desc *bufs = info->rbufs;
1842 int i, count;
1843 int chars = 0;
1844 int stat;
1845 unsigned char ch;
1846
1847 start = end = info->rbuf_current;
1848
1849 while(desc_complete(bufs[end])) {
1850 count = desc_count(bufs[end]) - info->rbuf_index;
1851 p = bufs[end].buf + info->rbuf_index;
1852
1853 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1854 DBGDATA(info, p, count, "rx");
1855
1856 for(i=0 ; i < count; i+=2, p+=2) {
1857 ch = *p;
1858 icount->rx++;
1859
1860 stat = 0;
1861
1862 status = *(p + 1) & (BIT1 + BIT0);
1863 if (status) {
1864 if (status & BIT1)
1865 icount->parity++;
1866 else if (status & BIT0)
1867 icount->frame++;
1868 /* discard char if tty control flags say so */
1869 if (status & info->ignore_status_mask)
1870 continue;
1871 if (status & BIT1)
1872 stat = TTY_PARITY;
1873 else if (status & BIT0)
1874 stat = TTY_FRAME;
1875 }
1876 tty_insert_flip_char(&info->port, ch, stat);
1877 chars++;
1878 }
1879
1880 if (i < count) {
1881 /* receive buffer not completed */
1882 info->rbuf_index += i;
1883 mod_timer(&info->rx_timer, jiffies + 1);
1884 break;
1885 }
1886
1887 info->rbuf_index = 0;
1888 free_rbufs(info, end, end);
1889
1890 if (++end == info->rbuf_count)
1891 end = 0;
1892
1893 /* if entire list searched then no frame available */
1894 if (end == start)
1895 break;
1896 }
1897
1898 if (chars)
1899 tty_flip_buffer_push(&info->port);
1900}
1901
1902/*
1903 * return next bottom half action to perform
1904 */
1905static int bh_action(struct slgt_info *info)
1906{
1907 unsigned long flags;
1908 int rc;
1909
1910 spin_lock_irqsave(&info->lock,flags);
1911
1912 if (info->pending_bh & BH_RECEIVE) {
1913 info->pending_bh &= ~BH_RECEIVE;
1914 rc = BH_RECEIVE;
1915 } else if (info->pending_bh & BH_TRANSMIT) {
1916 info->pending_bh &= ~BH_TRANSMIT;
1917 rc = BH_TRANSMIT;
1918 } else if (info->pending_bh & BH_STATUS) {
1919 info->pending_bh &= ~BH_STATUS;
1920 rc = BH_STATUS;
1921 } else {
1922 /* Mark BH routine as complete */
1923 info->bh_running = false;
1924 info->bh_requested = false;
1925 rc = 0;
1926 }
1927
1928 spin_unlock_irqrestore(&info->lock,flags);
1929
1930 return rc;
1931}
1932
1933/*
1934 * perform bottom half processing
1935 */
1936static void bh_handler(struct work_struct *work)
1937{
1938 struct slgt_info *info = container_of(work, struct slgt_info, task);
1939 int action;
1940
1941 info->bh_running = true;
1942
1943 while((action = bh_action(info))) {
1944 switch (action) {
1945 case BH_RECEIVE:
1946 DBGBH(("%s bh receive\n", info->device_name));
1947 switch(info->params.mode) {
1948 case MGSL_MODE_ASYNC:
1949 rx_async(info);
1950 break;
1951 case MGSL_MODE_HDLC:
1952 while(rx_get_frame(info));
1953 break;
1954 case MGSL_MODE_RAW:
1955 case MGSL_MODE_MONOSYNC:
1956 case MGSL_MODE_BISYNC:
1957 case MGSL_MODE_XSYNC:
1958 while(rx_get_buf(info));
1959 break;
1960 }
1961 /* restart receiver if rx DMA buffers exhausted */
1962 if (info->rx_restart)
1963 rx_start(info);
1964 break;
1965 case BH_TRANSMIT:
1966 bh_transmit(info);
1967 break;
1968 case BH_STATUS:
1969 DBGBH(("%s bh status\n", info->device_name));
1970 info->ri_chkcount = 0;
1971 info->dsr_chkcount = 0;
1972 info->dcd_chkcount = 0;
1973 info->cts_chkcount = 0;
1974 break;
1975 default:
1976 DBGBH(("%s unknown action\n", info->device_name));
1977 break;
1978 }
1979 }
1980 DBGBH(("%s bh_handler exit\n", info->device_name));
1981}
1982
1983static void bh_transmit(struct slgt_info *info)
1984{
1985 struct tty_struct *tty = info->port.tty;
1986
1987 DBGBH(("%s bh_transmit\n", info->device_name));
1988 if (tty)
1989 tty_wakeup(tty);
1990}
1991
1992static void dsr_change(struct slgt_info *info, unsigned short status)
1993{
1994 if (status & BIT3) {
1995 info->signals |= SerialSignal_DSR;
1996 info->input_signal_events.dsr_up++;
1997 } else {
1998 info->signals &= ~SerialSignal_DSR;
1999 info->input_signal_events.dsr_down++;
2000 }
2001 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2002 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2003 slgt_irq_off(info, IRQ_DSR);
2004 return;
2005 }
2006 info->icount.dsr++;
2007 wake_up_interruptible(&info->status_event_wait_q);
2008 wake_up_interruptible(&info->event_wait_q);
2009 info->pending_bh |= BH_STATUS;
2010}
2011
2012static void cts_change(struct slgt_info *info, unsigned short status)
2013{
2014 if (status & BIT2) {
2015 info->signals |= SerialSignal_CTS;
2016 info->input_signal_events.cts_up++;
2017 } else {
2018 info->signals &= ~SerialSignal_CTS;
2019 info->input_signal_events.cts_down++;
2020 }
2021 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2022 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2023 slgt_irq_off(info, IRQ_CTS);
2024 return;
2025 }
2026 info->icount.cts++;
2027 wake_up_interruptible(&info->status_event_wait_q);
2028 wake_up_interruptible(&info->event_wait_q);
2029 info->pending_bh |= BH_STATUS;
2030
2031 if (tty_port_cts_enabled(&info->port)) {
2032 if (info->port.tty) {
2033 if (info->port.tty->hw_stopped) {
2034 if (info->signals & SerialSignal_CTS) {
2035 info->port.tty->hw_stopped = 0;
2036 info->pending_bh |= BH_TRANSMIT;
2037 return;
2038 }
2039 } else {
2040 if (!(info->signals & SerialSignal_CTS))
2041 info->port.tty->hw_stopped = 1;
2042 }
2043 }
2044 }
2045}
2046
2047static void dcd_change(struct slgt_info *info, unsigned short status)
2048{
2049 if (status & BIT1) {
2050 info->signals |= SerialSignal_DCD;
2051 info->input_signal_events.dcd_up++;
2052 } else {
2053 info->signals &= ~SerialSignal_DCD;
2054 info->input_signal_events.dcd_down++;
2055 }
2056 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2057 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2058 slgt_irq_off(info, IRQ_DCD);
2059 return;
2060 }
2061 info->icount.dcd++;
2062#if SYNCLINK_GENERIC_HDLC
2063 if (info->netcount) {
2064 if (info->signals & SerialSignal_DCD)
2065 netif_carrier_on(info->netdev);
2066 else
2067 netif_carrier_off(info->netdev);
2068 }
2069#endif
2070 wake_up_interruptible(&info->status_event_wait_q);
2071 wake_up_interruptible(&info->event_wait_q);
2072 info->pending_bh |= BH_STATUS;
2073
2074 if (tty_port_check_carrier(&info->port)) {
2075 if (info->signals & SerialSignal_DCD)
2076 wake_up_interruptible(&info->port.open_wait);
2077 else {
2078 if (info->port.tty)
2079 tty_hangup(info->port.tty);
2080 }
2081 }
2082}
2083
2084static void ri_change(struct slgt_info *info, unsigned short status)
2085{
2086 if (status & BIT0) {
2087 info->signals |= SerialSignal_RI;
2088 info->input_signal_events.ri_up++;
2089 } else {
2090 info->signals &= ~SerialSignal_RI;
2091 info->input_signal_events.ri_down++;
2092 }
2093 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2094 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2095 slgt_irq_off(info, IRQ_RI);
2096 return;
2097 }
2098 info->icount.rng++;
2099 wake_up_interruptible(&info->status_event_wait_q);
2100 wake_up_interruptible(&info->event_wait_q);
2101 info->pending_bh |= BH_STATUS;
2102}
2103
2104static void isr_rxdata(struct slgt_info *info)
2105{
2106 unsigned int count = info->rbuf_fill_count;
2107 unsigned int i = info->rbuf_fill_index;
2108 unsigned short reg;
2109
2110 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2111 reg = rd_reg16(info, RDR);
2112 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2113 if (desc_complete(info->rbufs[i])) {
2114 /* all buffers full */
2115 rx_stop(info);
2116 info->rx_restart = 1;
2117 continue;
2118 }
2119 info->rbufs[i].buf[count++] = (unsigned char)reg;
2120 /* async mode saves status byte to buffer for each data byte */
2121 if (info->params.mode == MGSL_MODE_ASYNC)
2122 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2123 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2124 /* buffer full or end of frame */
2125 set_desc_count(info->rbufs[i], count);
2126 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2127 info->rbuf_fill_count = count = 0;
2128 if (++i == info->rbuf_count)
2129 i = 0;
2130 info->pending_bh |= BH_RECEIVE;
2131 }
2132 }
2133
2134 info->rbuf_fill_index = i;
2135 info->rbuf_fill_count = count;
2136}
2137
2138static void isr_serial(struct slgt_info *info)
2139{
2140 unsigned short status = rd_reg16(info, SSR);
2141
2142 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2143
2144 wr_reg16(info, SSR, status); /* clear pending */
2145
2146 info->irq_occurred = true;
2147
2148 if (info->params.mode == MGSL_MODE_ASYNC) {
2149 if (status & IRQ_TXIDLE) {
2150 if (info->tx_active)
2151 isr_txeom(info, status);
2152 }
2153 if (info->rx_pio && (status & IRQ_RXDATA))
2154 isr_rxdata(info);
2155 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2156 info->icount.brk++;
2157 /* process break detection if tty control allows */
2158 if (info->port.tty) {
2159 if (!(status & info->ignore_status_mask)) {
2160 if (info->read_status_mask & MASK_BREAK) {
2161 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2162 if (info->port.flags & ASYNC_SAK)
2163 do_SAK(info->port.tty);
2164 }
2165 }
2166 }
2167 }
2168 } else {
2169 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2170 isr_txeom(info, status);
2171 if (info->rx_pio && (status & IRQ_RXDATA))
2172 isr_rxdata(info);
2173 if (status & IRQ_RXIDLE) {
2174 if (status & RXIDLE)
2175 info->icount.rxidle++;
2176 else
2177 info->icount.exithunt++;
2178 wake_up_interruptible(&info->event_wait_q);
2179 }
2180
2181 if (status & IRQ_RXOVER)
2182 rx_start(info);
2183 }
2184
2185 if (status & IRQ_DSR)
2186 dsr_change(info, status);
2187 if (status & IRQ_CTS)
2188 cts_change(info, status);
2189 if (status & IRQ_DCD)
2190 dcd_change(info, status);
2191 if (status & IRQ_RI)
2192 ri_change(info, status);
2193}
2194
2195static void isr_rdma(struct slgt_info *info)
2196{
2197 unsigned int status = rd_reg32(info, RDCSR);
2198
2199 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2200
2201 /* RDCSR (rx DMA control/status)
2202 *
2203 * 31..07 reserved
2204 * 06 save status byte to DMA buffer
2205 * 05 error
2206 * 04 eol (end of list)
2207 * 03 eob (end of buffer)
2208 * 02 IRQ enable
2209 * 01 reset
2210 * 00 enable
2211 */
2212 wr_reg32(info, RDCSR, status); /* clear pending */
2213
2214 if (status & (BIT5 + BIT4)) {
2215 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2216 info->rx_restart = true;
2217 }
2218 info->pending_bh |= BH_RECEIVE;
2219}
2220
2221static void isr_tdma(struct slgt_info *info)
2222{
2223 unsigned int status = rd_reg32(info, TDCSR);
2224
2225 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2226
2227 /* TDCSR (tx DMA control/status)
2228 *
2229 * 31..06 reserved
2230 * 05 error
2231 * 04 eol (end of list)
2232 * 03 eob (end of buffer)
2233 * 02 IRQ enable
2234 * 01 reset
2235 * 00 enable
2236 */
2237 wr_reg32(info, TDCSR, status); /* clear pending */
2238
2239 if (status & (BIT5 + BIT4 + BIT3)) {
2240 // another transmit buffer has completed
2241 // run bottom half to get more send data from user
2242 info->pending_bh |= BH_TRANSMIT;
2243 }
2244}
2245
2246/*
2247 * return true if there are unsent tx DMA buffers, otherwise false
2248 *
2249 * if there are unsent buffers then info->tbuf_start
2250 * is set to index of first unsent buffer
2251 */
2252static bool unsent_tbufs(struct slgt_info *info)
2253{
2254 unsigned int i = info->tbuf_current;
2255 bool rc = false;
2256
2257 /*
2258 * search backwards from last loaded buffer (precedes tbuf_current)
2259 * for first unsent buffer (desc_count > 0)
2260 */
2261
2262 do {
2263 if (i)
2264 i--;
2265 else
2266 i = info->tbuf_count - 1;
2267 if (!desc_count(info->tbufs[i]))
2268 break;
2269 info->tbuf_start = i;
2270 rc = true;
2271 } while (i != info->tbuf_current);
2272
2273 return rc;
2274}
2275
2276static void isr_txeom(struct slgt_info *info, unsigned short status)
2277{
2278 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2279
2280 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2281 tdma_reset(info);
2282 if (status & IRQ_TXUNDER) {
2283 unsigned short val = rd_reg16(info, TCR);
2284 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2285 wr_reg16(info, TCR, val); /* clear reset bit */
2286 }
2287
2288 if (info->tx_active) {
2289 if (info->params.mode != MGSL_MODE_ASYNC) {
2290 if (status & IRQ_TXUNDER)
2291 info->icount.txunder++;
2292 else if (status & IRQ_TXIDLE)
2293 info->icount.txok++;
2294 }
2295
2296 if (unsent_tbufs(info)) {
2297 tx_start(info);
2298 update_tx_timer(info);
2299 return;
2300 }
2301 info->tx_active = false;
2302
2303 del_timer(&info->tx_timer);
2304
2305 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2306 info->signals &= ~SerialSignal_RTS;
2307 info->drop_rts_on_tx_done = false;
2308 set_signals(info);
2309 }
2310
2311#if SYNCLINK_GENERIC_HDLC
2312 if (info->netcount)
2313 hdlcdev_tx_done(info);
2314 else
2315#endif
2316 {
2317 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2318 tx_stop(info);
2319 return;
2320 }
2321 info->pending_bh |= BH_TRANSMIT;
2322 }
2323 }
2324}
2325
2326static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2327{
2328 struct cond_wait *w, *prev;
2329
2330 /* wake processes waiting for specific transitions */
2331 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2332 if (w->data & changed) {
2333 w->data = state;
2334 wake_up_interruptible(&w->q);
2335 if (prev != NULL)
2336 prev->next = w->next;
2337 else
2338 info->gpio_wait_q = w->next;
2339 } else
2340 prev = w;
2341 }
2342}
2343
2344/* interrupt service routine
2345 *
2346 * irq interrupt number
2347 * dev_id device ID supplied during interrupt registration
2348 */
2349static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2350{
2351 struct slgt_info *info = dev_id;
2352 unsigned int gsr;
2353 unsigned int i;
2354
2355 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2356
2357 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2358 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2359 info->irq_occurred = true;
2360 for(i=0; i < info->port_count ; i++) {
2361 if (info->port_array[i] == NULL)
2362 continue;
2363 spin_lock(&info->port_array[i]->lock);
2364 if (gsr & (BIT8 << i))
2365 isr_serial(info->port_array[i]);
2366 if (gsr & (BIT16 << (i*2)))
2367 isr_rdma(info->port_array[i]);
2368 if (gsr & (BIT17 << (i*2)))
2369 isr_tdma(info->port_array[i]);
2370 spin_unlock(&info->port_array[i]->lock);
2371 }
2372 }
2373
2374 if (info->gpio_present) {
2375 unsigned int state;
2376 unsigned int changed;
2377 spin_lock(&info->lock);
2378 while ((changed = rd_reg32(info, IOSR)) != 0) {
2379 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2380 /* read latched state of GPIO signals */
2381 state = rd_reg32(info, IOVR);
2382 /* clear pending GPIO interrupt bits */
2383 wr_reg32(info, IOSR, changed);
2384 for (i=0 ; i < info->port_count ; i++) {
2385 if (info->port_array[i] != NULL)
2386 isr_gpio(info->port_array[i], changed, state);
2387 }
2388 }
2389 spin_unlock(&info->lock);
2390 }
2391
2392 for(i=0; i < info->port_count ; i++) {
2393 struct slgt_info *port = info->port_array[i];
2394 if (port == NULL)
2395 continue;
2396 spin_lock(&port->lock);
2397 if ((port->port.count || port->netcount) &&
2398 port->pending_bh && !port->bh_running &&
2399 !port->bh_requested) {
2400 DBGISR(("%s bh queued\n", port->device_name));
2401 schedule_work(&port->task);
2402 port->bh_requested = true;
2403 }
2404 spin_unlock(&port->lock);
2405 }
2406
2407 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2408 return IRQ_HANDLED;
2409}
2410
2411static int startup(struct slgt_info *info)
2412{
2413 DBGINFO(("%s startup\n", info->device_name));
2414
2415 if (tty_port_initialized(&info->port))
2416 return 0;
2417
2418 if (!info->tx_buf) {
2419 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2420 if (!info->tx_buf) {
2421 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2422 return -ENOMEM;
2423 }
2424 }
2425
2426 info->pending_bh = 0;
2427
2428 memset(&info->icount, 0, sizeof(info->icount));
2429
2430 /* program hardware for current parameters */
2431 change_params(info);
2432
2433 if (info->port.tty)
2434 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2435
2436 tty_port_set_initialized(&info->port, 1);
2437
2438 return 0;
2439}
2440
2441/*
2442 * called by close() and hangup() to shutdown hardware
2443 */
2444static void shutdown(struct slgt_info *info)
2445{
2446 unsigned long flags;
2447
2448 if (!tty_port_initialized(&info->port))
2449 return;
2450
2451 DBGINFO(("%s shutdown\n", info->device_name));
2452
2453 /* clear status wait queue because status changes */
2454 /* can't happen after shutting down the hardware */
2455 wake_up_interruptible(&info->status_event_wait_q);
2456 wake_up_interruptible(&info->event_wait_q);
2457
2458 del_timer_sync(&info->tx_timer);
2459 del_timer_sync(&info->rx_timer);
2460
2461 kfree(info->tx_buf);
2462 info->tx_buf = NULL;
2463
2464 spin_lock_irqsave(&info->lock,flags);
2465
2466 tx_stop(info);
2467 rx_stop(info);
2468
2469 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2470
2471 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2472 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2473 set_signals(info);
2474 }
2475
2476 flush_cond_wait(&info->gpio_wait_q);
2477
2478 spin_unlock_irqrestore(&info->lock,flags);
2479
2480 if (info->port.tty)
2481 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2482
2483 tty_port_set_initialized(&info->port, 0);
2484}
2485
2486static void program_hw(struct slgt_info *info)
2487{
2488 unsigned long flags;
2489
2490 spin_lock_irqsave(&info->lock,flags);
2491
2492 rx_stop(info);
2493 tx_stop(info);
2494
2495 if (info->params.mode != MGSL_MODE_ASYNC ||
2496 info->netcount)
2497 sync_mode(info);
2498 else
2499 async_mode(info);
2500
2501 set_signals(info);
2502
2503 info->dcd_chkcount = 0;
2504 info->cts_chkcount = 0;
2505 info->ri_chkcount = 0;
2506 info->dsr_chkcount = 0;
2507
2508 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2509 get_signals(info);
2510
2511 if (info->netcount ||
2512 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2513 rx_start(info);
2514
2515 spin_unlock_irqrestore(&info->lock,flags);
2516}
2517
2518/*
2519 * reconfigure adapter based on new parameters
2520 */
2521static void change_params(struct slgt_info *info)
2522{
2523 unsigned cflag;
2524 int bits_per_char;
2525
2526 if (!info->port.tty)
2527 return;
2528 DBGINFO(("%s change_params\n", info->device_name));
2529
2530 cflag = info->port.tty->termios.c_cflag;
2531
2532 /* if B0 rate (hangup) specified then negate RTS and DTR */
2533 /* otherwise assert RTS and DTR */
2534 if (cflag & CBAUD)
2535 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2536 else
2537 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2538
2539 /* byte size and parity */
2540
2541 switch (cflag & CSIZE) {
2542 case CS5: info->params.data_bits = 5; break;
2543 case CS6: info->params.data_bits = 6; break;
2544 case CS7: info->params.data_bits = 7; break;
2545 case CS8: info->params.data_bits = 8; break;
2546 default: info->params.data_bits = 7; break;
2547 }
2548
2549 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2550
2551 if (cflag & PARENB)
2552 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2553 else
2554 info->params.parity = ASYNC_PARITY_NONE;
2555
2556 /* calculate number of jiffies to transmit a full
2557 * FIFO (32 bytes) at specified data rate
2558 */
2559 bits_per_char = info->params.data_bits +
2560 info->params.stop_bits + 1;
2561
2562 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2563
2564 if (info->params.data_rate) {
2565 info->timeout = (32*HZ*bits_per_char) /
2566 info->params.data_rate;
2567 }
2568 info->timeout += HZ/50; /* Add .02 seconds of slop */
2569
2570 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2571 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2572
2573 /* process tty input control flags */
2574
2575 info->read_status_mask = IRQ_RXOVER;
2576 if (I_INPCK(info->port.tty))
2577 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2578 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2579 info->read_status_mask |= MASK_BREAK;
2580 if (I_IGNPAR(info->port.tty))
2581 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2582 if (I_IGNBRK(info->port.tty)) {
2583 info->ignore_status_mask |= MASK_BREAK;
2584 /* If ignoring parity and break indicators, ignore
2585 * overruns too. (For real raw support).
2586 */
2587 if (I_IGNPAR(info->port.tty))
2588 info->ignore_status_mask |= MASK_OVERRUN;
2589 }
2590
2591 program_hw(info);
2592}
2593
2594static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2595{
2596 DBGINFO(("%s get_stats\n", info->device_name));
2597 if (!user_icount) {
2598 memset(&info->icount, 0, sizeof(info->icount));
2599 } else {
2600 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2601 return -EFAULT;
2602 }
2603 return 0;
2604}
2605
2606static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2607{
2608 DBGINFO(("%s get_params\n", info->device_name));
2609 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2610 return -EFAULT;
2611 return 0;
2612}
2613
2614static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2615{
2616 unsigned long flags;
2617 MGSL_PARAMS tmp_params;
2618
2619 DBGINFO(("%s set_params\n", info->device_name));
2620 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2621 return -EFAULT;
2622
2623 spin_lock_irqsave(&info->lock, flags);
2624 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2625 info->base_clock = tmp_params.clock_speed;
2626 else
2627 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2628 spin_unlock_irqrestore(&info->lock, flags);
2629
2630 program_hw(info);
2631
2632 return 0;
2633}
2634
2635static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2636{
2637 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2638 if (put_user(info->idle_mode, idle_mode))
2639 return -EFAULT;
2640 return 0;
2641}
2642
2643static int set_txidle(struct slgt_info *info, int idle_mode)
2644{
2645 unsigned long flags;
2646 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2647 spin_lock_irqsave(&info->lock,flags);
2648 info->idle_mode = idle_mode;
2649 if (info->params.mode != MGSL_MODE_ASYNC)
2650 tx_set_idle(info);
2651 spin_unlock_irqrestore(&info->lock,flags);
2652 return 0;
2653}
2654
2655static int tx_enable(struct slgt_info *info, int enable)
2656{
2657 unsigned long flags;
2658 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2659 spin_lock_irqsave(&info->lock,flags);
2660 if (enable) {
2661 if (!info->tx_enabled)
2662 tx_start(info);
2663 } else {
2664 if (info->tx_enabled)
2665 tx_stop(info);
2666 }
2667 spin_unlock_irqrestore(&info->lock,flags);
2668 return 0;
2669}
2670
2671/*
2672 * abort transmit HDLC frame
2673 */
2674static int tx_abort(struct slgt_info *info)
2675{
2676 unsigned long flags;
2677 DBGINFO(("%s tx_abort\n", info->device_name));
2678 spin_lock_irqsave(&info->lock,flags);
2679 tdma_reset(info);
2680 spin_unlock_irqrestore(&info->lock,flags);
2681 return 0;
2682}
2683
2684static int rx_enable(struct slgt_info *info, int enable)
2685{
2686 unsigned long flags;
2687 unsigned int rbuf_fill_level;
2688 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2689 spin_lock_irqsave(&info->lock,flags);
2690 /*
2691 * enable[31..16] = receive DMA buffer fill level
2692 * 0 = noop (leave fill level unchanged)
2693 * fill level must be multiple of 4 and <= buffer size
2694 */
2695 rbuf_fill_level = ((unsigned int)enable) >> 16;
2696 if (rbuf_fill_level) {
2697 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2698 spin_unlock_irqrestore(&info->lock, flags);
2699 return -EINVAL;
2700 }
2701 info->rbuf_fill_level = rbuf_fill_level;
2702 if (rbuf_fill_level < 128)
2703 info->rx_pio = 1; /* PIO mode */
2704 else
2705 info->rx_pio = 0; /* DMA mode */
2706 rx_stop(info); /* restart receiver to use new fill level */
2707 }
2708
2709 /*
2710 * enable[1..0] = receiver enable command
2711 * 0 = disable
2712 * 1 = enable
2713 * 2 = enable or force hunt mode if already enabled
2714 */
2715 enable &= 3;
2716 if (enable) {
2717 if (!info->rx_enabled)
2718 rx_start(info);
2719 else if (enable == 2) {
2720 /* force hunt mode (write 1 to RCR[3]) */
2721 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2722 }
2723 } else {
2724 if (info->rx_enabled)
2725 rx_stop(info);
2726 }
2727 spin_unlock_irqrestore(&info->lock,flags);
2728 return 0;
2729}
2730
2731/*
2732 * wait for specified event to occur
2733 */
2734static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2735{
2736 unsigned long flags;
2737 int s;
2738 int rc=0;
2739 struct mgsl_icount cprev, cnow;
2740 int events;
2741 int mask;
2742 struct _input_signal_events oldsigs, newsigs;
2743 DECLARE_WAITQUEUE(wait, current);
2744
2745 if (get_user(mask, mask_ptr))
2746 return -EFAULT;
2747
2748 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2749
2750 spin_lock_irqsave(&info->lock,flags);
2751
2752 /* return immediately if state matches requested events */
2753 get_signals(info);
2754 s = info->signals;
2755
2756 events = mask &
2757 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2758 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2759 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2760 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2761 if (events) {
2762 spin_unlock_irqrestore(&info->lock,flags);
2763 goto exit;
2764 }
2765
2766 /* save current irq counts */
2767 cprev = info->icount;
2768 oldsigs = info->input_signal_events;
2769
2770 /* enable hunt and idle irqs if needed */
2771 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2772 unsigned short val = rd_reg16(info, SCR);
2773 if (!(val & IRQ_RXIDLE))
2774 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2775 }
2776
2777 set_current_state(TASK_INTERRUPTIBLE);
2778 add_wait_queue(&info->event_wait_q, &wait);
2779
2780 spin_unlock_irqrestore(&info->lock,flags);
2781
2782 for(;;) {
2783 schedule();
2784 if (signal_pending(current)) {
2785 rc = -ERESTARTSYS;
2786 break;
2787 }
2788
2789 /* get current irq counts */
2790 spin_lock_irqsave(&info->lock,flags);
2791 cnow = info->icount;
2792 newsigs = info->input_signal_events;
2793 set_current_state(TASK_INTERRUPTIBLE);
2794 spin_unlock_irqrestore(&info->lock,flags);
2795
2796 /* if no change, wait aborted for some reason */
2797 if (newsigs.dsr_up == oldsigs.dsr_up &&
2798 newsigs.dsr_down == oldsigs.dsr_down &&
2799 newsigs.dcd_up == oldsigs.dcd_up &&
2800 newsigs.dcd_down == oldsigs.dcd_down &&
2801 newsigs.cts_up == oldsigs.cts_up &&
2802 newsigs.cts_down == oldsigs.cts_down &&
2803 newsigs.ri_up == oldsigs.ri_up &&
2804 newsigs.ri_down == oldsigs.ri_down &&
2805 cnow.exithunt == cprev.exithunt &&
2806 cnow.rxidle == cprev.rxidle) {
2807 rc = -EIO;
2808 break;
2809 }
2810
2811 events = mask &
2812 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2813 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2814 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2815 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2816 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2817 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2818 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2819 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2820 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2821 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2822 if (events)
2823 break;
2824
2825 cprev = cnow;
2826 oldsigs = newsigs;
2827 }
2828
2829 remove_wait_queue(&info->event_wait_q, &wait);
2830 set_current_state(TASK_RUNNING);
2831
2832
2833 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2834 spin_lock_irqsave(&info->lock,flags);
2835 if (!waitqueue_active(&info->event_wait_q)) {
2836 /* disable enable exit hunt mode/idle rcvd IRQs */
2837 wr_reg16(info, SCR,
2838 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2839 }
2840 spin_unlock_irqrestore(&info->lock,flags);
2841 }
2842exit:
2843 if (rc == 0)
2844 rc = put_user(events, mask_ptr);
2845 return rc;
2846}
2847
2848static int get_interface(struct slgt_info *info, int __user *if_mode)
2849{
2850 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2851 if (put_user(info->if_mode, if_mode))
2852 return -EFAULT;
2853 return 0;
2854}
2855
2856static int set_interface(struct slgt_info *info, int if_mode)
2857{
2858 unsigned long flags;
2859 unsigned short val;
2860
2861 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2862 spin_lock_irqsave(&info->lock,flags);
2863 info->if_mode = if_mode;
2864
2865 msc_set_vcr(info);
2866
2867 /* TCR (tx control) 07 1=RTS driver control */
2868 val = rd_reg16(info, TCR);
2869 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2870 val |= BIT7;
2871 else
2872 val &= ~BIT7;
2873 wr_reg16(info, TCR, val);
2874
2875 spin_unlock_irqrestore(&info->lock,flags);
2876 return 0;
2877}
2878
2879static int get_xsync(struct slgt_info *info, int __user *xsync)
2880{
2881 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2882 if (put_user(info->xsync, xsync))
2883 return -EFAULT;
2884 return 0;
2885}
2886
2887/*
2888 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2889 *
2890 * sync pattern is contained in least significant bytes of value
2891 * most significant byte of sync pattern is oldest (1st sent/detected)
2892 */
2893static int set_xsync(struct slgt_info *info, int xsync)
2894{
2895 unsigned long flags;
2896
2897 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2898 spin_lock_irqsave(&info->lock, flags);
2899 info->xsync = xsync;
2900 wr_reg32(info, XSR, xsync);
2901 spin_unlock_irqrestore(&info->lock, flags);
2902 return 0;
2903}
2904
2905static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2906{
2907 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2908 if (put_user(info->xctrl, xctrl))
2909 return -EFAULT;
2910 return 0;
2911}
2912
2913/*
2914 * set extended control options
2915 *
2916 * xctrl[31:19] reserved, must be zero
2917 * xctrl[18:17] extended sync pattern length in bytes
2918 * 00 = 1 byte in xsr[7:0]
2919 * 01 = 2 bytes in xsr[15:0]
2920 * 10 = 3 bytes in xsr[23:0]
2921 * 11 = 4 bytes in xsr[31:0]
2922 * xctrl[16] 1 = enable terminal count, 0=disabled
2923 * xctrl[15:0] receive terminal count for fixed length packets
2924 * value is count minus one (0 = 1 byte packet)
2925 * when terminal count is reached, receiver
2926 * automatically returns to hunt mode and receive
2927 * FIFO contents are flushed to DMA buffers with
2928 * end of frame (EOF) status
2929 */
2930static int set_xctrl(struct slgt_info *info, int xctrl)
2931{
2932 unsigned long flags;
2933
2934 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2935 spin_lock_irqsave(&info->lock, flags);
2936 info->xctrl = xctrl;
2937 wr_reg32(info, XCR, xctrl);
2938 spin_unlock_irqrestore(&info->lock, flags);
2939 return 0;
2940}
2941
2942/*
2943 * set general purpose IO pin state and direction
2944 *
2945 * user_gpio fields:
2946 * state each bit indicates a pin state
2947 * smask set bit indicates pin state to set
2948 * dir each bit indicates a pin direction (0=input, 1=output)
2949 * dmask set bit indicates pin direction to set
2950 */
2951static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2952{
2953 unsigned long flags;
2954 struct gpio_desc gpio;
2955 __u32 data;
2956
2957 if (!info->gpio_present)
2958 return -EINVAL;
2959 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2960 return -EFAULT;
2961 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2962 info->device_name, gpio.state, gpio.smask,
2963 gpio.dir, gpio.dmask));
2964
2965 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2966 if (gpio.dmask) {
2967 data = rd_reg32(info, IODR);
2968 data |= gpio.dmask & gpio.dir;
2969 data &= ~(gpio.dmask & ~gpio.dir);
2970 wr_reg32(info, IODR, data);
2971 }
2972 if (gpio.smask) {
2973 data = rd_reg32(info, IOVR);
2974 data |= gpio.smask & gpio.state;
2975 data &= ~(gpio.smask & ~gpio.state);
2976 wr_reg32(info, IOVR, data);
2977 }
2978 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2979
2980 return 0;
2981}
2982
2983/*
2984 * get general purpose IO pin state and direction
2985 */
2986static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2987{
2988 struct gpio_desc gpio;
2989 if (!info->gpio_present)
2990 return -EINVAL;
2991 gpio.state = rd_reg32(info, IOVR);
2992 gpio.smask = 0xffffffff;
2993 gpio.dir = rd_reg32(info, IODR);
2994 gpio.dmask = 0xffffffff;
2995 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2996 return -EFAULT;
2997 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2998 info->device_name, gpio.state, gpio.dir));
2999 return 0;
3000}
3001
3002/*
3003 * conditional wait facility
3004 */
3005static void init_cond_wait(struct cond_wait *w, unsigned int data)
3006{
3007 init_waitqueue_head(&w->q);
3008 init_waitqueue_entry(&w->wait, current);
3009 w->data = data;
3010}
3011
3012static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3013{
3014 set_current_state(TASK_INTERRUPTIBLE);
3015 add_wait_queue(&w->q, &w->wait);
3016 w->next = *head;
3017 *head = w;
3018}
3019
3020static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3021{
3022 struct cond_wait *w, *prev;
3023 remove_wait_queue(&cw->q, &cw->wait);
3024 set_current_state(TASK_RUNNING);
3025 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3026 if (w == cw) {
3027 if (prev != NULL)
3028 prev->next = w->next;
3029 else
3030 *head = w->next;
3031 break;
3032 }
3033 }
3034}
3035
3036static void flush_cond_wait(struct cond_wait **head)
3037{
3038 while (*head != NULL) {
3039 wake_up_interruptible(&(*head)->q);
3040 *head = (*head)->next;
3041 }
3042}
3043
3044/*
3045 * wait for general purpose I/O pin(s) to enter specified state
3046 *
3047 * user_gpio fields:
3048 * state - bit indicates target pin state
3049 * smask - set bit indicates watched pin
3050 *
3051 * The wait ends when at least one watched pin enters the specified
3052 * state. When 0 (no error) is returned, user_gpio->state is set to the
3053 * state of all GPIO pins when the wait ends.
3054 *
3055 * Note: Each pin may be a dedicated input, dedicated output, or
3056 * configurable input/output. The number and configuration of pins
3057 * varies with the specific adapter model. Only input pins (dedicated
3058 * or configured) can be monitored with this function.
3059 */
3060static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3061{
3062 unsigned long flags;
3063 int rc = 0;
3064 struct gpio_desc gpio;
3065 struct cond_wait wait;
3066 u32 state;
3067
3068 if (!info->gpio_present)
3069 return -EINVAL;
3070 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3071 return -EFAULT;
3072 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3073 info->device_name, gpio.state, gpio.smask));
3074 /* ignore output pins identified by set IODR bit */
3075 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3076 return -EINVAL;
3077 init_cond_wait(&wait, gpio.smask);
3078
3079 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3080 /* enable interrupts for watched pins */
3081 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3082 /* get current pin states */
3083 state = rd_reg32(info, IOVR);
3084
3085 if (gpio.smask & ~(state ^ gpio.state)) {
3086 /* already in target state */
3087 gpio.state = state;
3088 } else {
3089 /* wait for target state */
3090 add_cond_wait(&info->gpio_wait_q, &wait);
3091 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3092 schedule();
3093 if (signal_pending(current))
3094 rc = -ERESTARTSYS;
3095 else
3096 gpio.state = wait.data;
3097 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3098 remove_cond_wait(&info->gpio_wait_q, &wait);
3099 }
3100
3101 /* disable all GPIO interrupts if no waiting processes */
3102 if (info->gpio_wait_q == NULL)
3103 wr_reg32(info, IOER, 0);
3104 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3105
3106 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3107 rc = -EFAULT;
3108 return rc;
3109}
3110
3111static int modem_input_wait(struct slgt_info *info,int arg)
3112{
3113 unsigned long flags;
3114 int rc;
3115 struct mgsl_icount cprev, cnow;
3116 DECLARE_WAITQUEUE(wait, current);
3117
3118 /* save current irq counts */
3119 spin_lock_irqsave(&info->lock,flags);
3120 cprev = info->icount;
3121 add_wait_queue(&info->status_event_wait_q, &wait);
3122 set_current_state(TASK_INTERRUPTIBLE);
3123 spin_unlock_irqrestore(&info->lock,flags);
3124
3125 for(;;) {
3126 schedule();
3127 if (signal_pending(current)) {
3128 rc = -ERESTARTSYS;
3129 break;
3130 }
3131
3132 /* get new irq counts */
3133 spin_lock_irqsave(&info->lock,flags);
3134 cnow = info->icount;
3135 set_current_state(TASK_INTERRUPTIBLE);
3136 spin_unlock_irqrestore(&info->lock,flags);
3137
3138 /* if no change, wait aborted for some reason */
3139 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3140 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3141 rc = -EIO;
3142 break;
3143 }
3144
3145 /* check for change in caller specified modem input */
3146 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3147 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3148 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3149 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3150 rc = 0;
3151 break;
3152 }
3153
3154 cprev = cnow;
3155 }
3156 remove_wait_queue(&info->status_event_wait_q, &wait);
3157 set_current_state(TASK_RUNNING);
3158 return rc;
3159}
3160
3161/*
3162 * return state of serial control and status signals
3163 */
3164static int tiocmget(struct tty_struct *tty)
3165{
3166 struct slgt_info *info = tty->driver_data;
3167 unsigned int result;
3168 unsigned long flags;
3169
3170 spin_lock_irqsave(&info->lock,flags);
3171 get_signals(info);
3172 spin_unlock_irqrestore(&info->lock,flags);
3173
3174 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3175 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3176 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3177 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3178 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3179 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3180
3181 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3182 return result;
3183}
3184
3185/*
3186 * set modem control signals (DTR/RTS)
3187 *
3188 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3189 * TIOCMSET = set/clear signal values
3190 * value bit mask for command
3191 */
3192static int tiocmset(struct tty_struct *tty,
3193 unsigned int set, unsigned int clear)
3194{
3195 struct slgt_info *info = tty->driver_data;
3196 unsigned long flags;
3197
3198 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3199
3200 if (set & TIOCM_RTS)
3201 info->signals |= SerialSignal_RTS;
3202 if (set & TIOCM_DTR)
3203 info->signals |= SerialSignal_DTR;
3204 if (clear & TIOCM_RTS)
3205 info->signals &= ~SerialSignal_RTS;
3206 if (clear & TIOCM_DTR)
3207 info->signals &= ~SerialSignal_DTR;
3208
3209 spin_lock_irqsave(&info->lock,flags);
3210 set_signals(info);
3211 spin_unlock_irqrestore(&info->lock,flags);
3212 return 0;
3213}
3214
3215static int carrier_raised(struct tty_port *port)
3216{
3217 unsigned long flags;
3218 struct slgt_info *info = container_of(port, struct slgt_info, port);
3219
3220 spin_lock_irqsave(&info->lock,flags);
3221 get_signals(info);
3222 spin_unlock_irqrestore(&info->lock,flags);
3223 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3224}
3225
3226static void dtr_rts(struct tty_port *port, int on)
3227{
3228 unsigned long flags;
3229 struct slgt_info *info = container_of(port, struct slgt_info, port);
3230
3231 spin_lock_irqsave(&info->lock,flags);
3232 if (on)
3233 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3234 else
3235 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3236 set_signals(info);
3237 spin_unlock_irqrestore(&info->lock,flags);
3238}
3239
3240
3241/*
3242 * block current process until the device is ready to open
3243 */
3244static int block_til_ready(struct tty_struct *tty, struct file *filp,
3245 struct slgt_info *info)
3246{
3247 DECLARE_WAITQUEUE(wait, current);
3248 int retval;
3249 bool do_clocal = false;
3250 unsigned long flags;
3251 int cd;
3252 struct tty_port *port = &info->port;
3253
3254 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3255
3256 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3257 /* nonblock mode is set or port is not enabled */
3258 tty_port_set_active(port, 1);
3259 return 0;
3260 }
3261
3262 if (C_CLOCAL(tty))
3263 do_clocal = true;
3264
3265 /* Wait for carrier detect and the line to become
3266 * free (i.e., not in use by the callout). While we are in
3267 * this loop, port->count is dropped by one, so that
3268 * close() knows when to free things. We restore it upon
3269 * exit, either normal or abnormal.
3270 */
3271
3272 retval = 0;
3273 add_wait_queue(&port->open_wait, &wait);
3274
3275 spin_lock_irqsave(&info->lock, flags);
3276 port->count--;
3277 spin_unlock_irqrestore(&info->lock, flags);
3278 port->blocked_open++;
3279
3280 while (1) {
3281 if (C_BAUD(tty) && tty_port_initialized(port))
3282 tty_port_raise_dtr_rts(port);
3283
3284 set_current_state(TASK_INTERRUPTIBLE);
3285
3286 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3287 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3288 -EAGAIN : -ERESTARTSYS;
3289 break;
3290 }
3291
3292 cd = tty_port_carrier_raised(port);
3293 if (do_clocal || cd)
3294 break;
3295
3296 if (signal_pending(current)) {
3297 retval = -ERESTARTSYS;
3298 break;
3299 }
3300
3301 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3302 tty_unlock(tty);
3303 schedule();
3304 tty_lock(tty);
3305 }
3306
3307 set_current_state(TASK_RUNNING);
3308 remove_wait_queue(&port->open_wait, &wait);
3309
3310 if (!tty_hung_up_p(filp))
3311 port->count++;
3312 port->blocked_open--;
3313
3314 if (!retval)
3315 tty_port_set_active(port, 1);
3316
3317 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3318 return retval;
3319}
3320
3321/*
3322 * allocate buffers used for calling line discipline receive_buf
3323 * directly in synchronous mode
3324 * note: add 5 bytes to max frame size to allow appending
3325 * 32-bit CRC and status byte when configured to do so
3326 */
3327static int alloc_tmp_rbuf(struct slgt_info *info)
3328{
3329 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3330 if (info->tmp_rbuf == NULL)
3331 return -ENOMEM;
3332 /* unused flag buffer to satisfy receive_buf calling interface */
3333 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3334 if (!info->flag_buf) {
3335 kfree(info->tmp_rbuf);
3336 info->tmp_rbuf = NULL;
3337 return -ENOMEM;
3338 }
3339 return 0;
3340}
3341
3342static void free_tmp_rbuf(struct slgt_info *info)
3343{
3344 kfree(info->tmp_rbuf);
3345 info->tmp_rbuf = NULL;
3346 kfree(info->flag_buf);
3347 info->flag_buf = NULL;
3348}
3349
3350/*
3351 * allocate DMA descriptor lists.
3352 */
3353static int alloc_desc(struct slgt_info *info)
3354{
3355 unsigned int i;
3356 unsigned int pbufs;
3357
3358 /* allocate memory to hold descriptor lists */
3359 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3360 &info->bufs_dma_addr);
3361 if (info->bufs == NULL)
3362 return -ENOMEM;
3363
3364 info->rbufs = (struct slgt_desc*)info->bufs;
3365 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3366
3367 pbufs = (unsigned int)info->bufs_dma_addr;
3368
3369 /*
3370 * Build circular lists of descriptors
3371 */
3372
3373 for (i=0; i < info->rbuf_count; i++) {
3374 /* physical address of this descriptor */
3375 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3376
3377 /* physical address of next descriptor */
3378 if (i == info->rbuf_count - 1)
3379 info->rbufs[i].next = cpu_to_le32(pbufs);
3380 else
3381 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3382 set_desc_count(info->rbufs[i], DMABUFSIZE);
3383 }
3384
3385 for (i=0; i < info->tbuf_count; i++) {
3386 /* physical address of this descriptor */
3387 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3388
3389 /* physical address of next descriptor */
3390 if (i == info->tbuf_count - 1)
3391 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3392 else
3393 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3394 }
3395
3396 return 0;
3397}
3398
3399static void free_desc(struct slgt_info *info)
3400{
3401 if (info->bufs != NULL) {
3402 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3403 info->bufs = NULL;
3404 info->rbufs = NULL;
3405 info->tbufs = NULL;
3406 }
3407}
3408
3409static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3410{
3411 int i;
3412 for (i=0; i < count; i++) {
3413 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3414 return -ENOMEM;
3415 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3416 }
3417 return 0;
3418}
3419
3420static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3421{
3422 int i;
3423 for (i=0; i < count; i++) {
3424 if (bufs[i].buf == NULL)
3425 continue;
3426 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3427 bufs[i].buf = NULL;
3428 }
3429}
3430
3431static int alloc_dma_bufs(struct slgt_info *info)
3432{
3433 info->rbuf_count = 32;
3434 info->tbuf_count = 32;
3435
3436 if (alloc_desc(info) < 0 ||
3437 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3438 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3439 alloc_tmp_rbuf(info) < 0) {
3440 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3441 return -ENOMEM;
3442 }
3443 reset_rbufs(info);
3444 return 0;
3445}
3446
3447static void free_dma_bufs(struct slgt_info *info)
3448{
3449 if (info->bufs) {
3450 free_bufs(info, info->rbufs, info->rbuf_count);
3451 free_bufs(info, info->tbufs, info->tbuf_count);
3452 free_desc(info);
3453 }
3454 free_tmp_rbuf(info);
3455}
3456
3457static int claim_resources(struct slgt_info *info)
3458{
3459 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3460 DBGERR(("%s reg addr conflict, addr=%08X\n",
3461 info->device_name, info->phys_reg_addr));
3462 info->init_error = DiagStatus_AddressConflict;
3463 goto errout;
3464 }
3465 else
3466 info->reg_addr_requested = true;
3467
3468 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3469 if (!info->reg_addr) {
3470 DBGERR(("%s can't map device registers, addr=%08X\n",
3471 info->device_name, info->phys_reg_addr));
3472 info->init_error = DiagStatus_CantAssignPciResources;
3473 goto errout;
3474 }
3475 return 0;
3476
3477errout:
3478 release_resources(info);
3479 return -ENODEV;
3480}
3481
3482static void release_resources(struct slgt_info *info)
3483{
3484 if (info->irq_requested) {
3485 free_irq(info->irq_level, info);
3486 info->irq_requested = false;
3487 }
3488
3489 if (info->reg_addr_requested) {
3490 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3491 info->reg_addr_requested = false;
3492 }
3493
3494 if (info->reg_addr) {
3495 iounmap(info->reg_addr);
3496 info->reg_addr = NULL;
3497 }
3498}
3499
3500/* Add the specified device instance data structure to the
3501 * global linked list of devices and increment the device count.
3502 */
3503static void add_device(struct slgt_info *info)
3504{
3505 char *devstr;
3506
3507 info->next_device = NULL;
3508 info->line = slgt_device_count;
3509 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3510
3511 if (info->line < MAX_DEVICES) {
3512 if (maxframe[info->line])
3513 info->max_frame_size = maxframe[info->line];
3514 }
3515
3516 slgt_device_count++;
3517
3518 if (!slgt_device_list)
3519 slgt_device_list = info;
3520 else {
3521 struct slgt_info *current_dev = slgt_device_list;
3522 while(current_dev->next_device)
3523 current_dev = current_dev->next_device;
3524 current_dev->next_device = info;
3525 }
3526
3527 if (info->max_frame_size < 4096)
3528 info->max_frame_size = 4096;
3529 else if (info->max_frame_size > 65535)
3530 info->max_frame_size = 65535;
3531
3532 switch(info->pdev->device) {
3533 case SYNCLINK_GT_DEVICE_ID:
3534 devstr = "GT";
3535 break;
3536 case SYNCLINK_GT2_DEVICE_ID:
3537 devstr = "GT2";
3538 break;
3539 case SYNCLINK_GT4_DEVICE_ID:
3540 devstr = "GT4";
3541 break;
3542 case SYNCLINK_AC_DEVICE_ID:
3543 devstr = "AC";
3544 info->params.mode = MGSL_MODE_ASYNC;
3545 break;
3546 default:
3547 devstr = "(unknown model)";
3548 }
3549 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3550 devstr, info->device_name, info->phys_reg_addr,
3551 info->irq_level, info->max_frame_size);
3552
3553#if SYNCLINK_GENERIC_HDLC
3554 hdlcdev_init(info);
3555#endif
3556}
3557
3558static const struct tty_port_operations slgt_port_ops = {
3559 .carrier_raised = carrier_raised,
3560 .dtr_rts = dtr_rts,
3561};
3562
3563/*
3564 * allocate device instance structure, return NULL on failure
3565 */
3566static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3567{
3568 struct slgt_info *info;
3569
3570 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3571
3572 if (!info) {
3573 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3574 driver_name, adapter_num, port_num));
3575 } else {
3576 tty_port_init(&info->port);
3577 info->port.ops = &slgt_port_ops;
3578 info->magic = MGSL_MAGIC;
3579 INIT_WORK(&info->task, bh_handler);
3580 info->max_frame_size = 4096;
3581 info->base_clock = 14745600;
3582 info->rbuf_fill_level = DMABUFSIZE;
3583 info->port.close_delay = 5*HZ/10;
3584 info->port.closing_wait = 30*HZ;
3585 init_waitqueue_head(&info->status_event_wait_q);
3586 init_waitqueue_head(&info->event_wait_q);
3587 spin_lock_init(&info->netlock);
3588 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3589 info->idle_mode = HDLC_TXIDLE_FLAGS;
3590 info->adapter_num = adapter_num;
3591 info->port_num = port_num;
3592
3593 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3594 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3595
3596 /* Copy configuration info to device instance data */
3597 info->pdev = pdev;
3598 info->irq_level = pdev->irq;
3599 info->phys_reg_addr = pci_resource_start(pdev,0);
3600
3601 info->bus_type = MGSL_BUS_TYPE_PCI;
3602 info->irq_flags = IRQF_SHARED;
3603
3604 info->init_error = -1; /* assume error, set to 0 on successful init */
3605 }
3606
3607 return info;
3608}
3609
3610static void device_init(int adapter_num, struct pci_dev *pdev)
3611{
3612 struct slgt_info *port_array[SLGT_MAX_PORTS];
3613 int i;
3614 int port_count = 1;
3615
3616 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3617 port_count = 2;
3618 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3619 port_count = 4;
3620
3621 /* allocate device instances for all ports */
3622 for (i=0; i < port_count; ++i) {
3623 port_array[i] = alloc_dev(adapter_num, i, pdev);
3624 if (port_array[i] == NULL) {
3625 for (--i; i >= 0; --i) {
3626 tty_port_destroy(&port_array[i]->port);
3627 kfree(port_array[i]);
3628 }
3629 return;
3630 }
3631 }
3632
3633 /* give copy of port_array to all ports and add to device list */
3634 for (i=0; i < port_count; ++i) {
3635 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3636 add_device(port_array[i]);
3637 port_array[i]->port_count = port_count;
3638 spin_lock_init(&port_array[i]->lock);
3639 }
3640
3641 /* Allocate and claim adapter resources */
3642 if (!claim_resources(port_array[0])) {
3643
3644 alloc_dma_bufs(port_array[0]);
3645
3646 /* copy resource information from first port to others */
3647 for (i = 1; i < port_count; ++i) {
3648 port_array[i]->irq_level = port_array[0]->irq_level;
3649 port_array[i]->reg_addr = port_array[0]->reg_addr;
3650 alloc_dma_bufs(port_array[i]);
3651 }
3652
3653 if (request_irq(port_array[0]->irq_level,
3654 slgt_interrupt,
3655 port_array[0]->irq_flags,
3656 port_array[0]->device_name,
3657 port_array[0]) < 0) {
3658 DBGERR(("%s request_irq failed IRQ=%d\n",
3659 port_array[0]->device_name,
3660 port_array[0]->irq_level));
3661 } else {
3662 port_array[0]->irq_requested = true;
3663 adapter_test(port_array[0]);
3664 for (i=1 ; i < port_count ; i++) {
3665 port_array[i]->init_error = port_array[0]->init_error;
3666 port_array[i]->gpio_present = port_array[0]->gpio_present;
3667 }
3668 }
3669 }
3670
3671 for (i = 0; i < port_count; ++i) {
3672 struct slgt_info *info = port_array[i];
3673 tty_port_register_device(&info->port, serial_driver, info->line,
3674 &info->pdev->dev);
3675 }
3676}
3677
3678static int init_one(struct pci_dev *dev,
3679 const struct pci_device_id *ent)
3680{
3681 if (pci_enable_device(dev)) {
3682 printk("error enabling pci device %p\n", dev);
3683 return -EIO;
3684 }
3685 pci_set_master(dev);
3686 device_init(slgt_device_count, dev);
3687 return 0;
3688}
3689
3690static void remove_one(struct pci_dev *dev)
3691{
3692}
3693
3694static const struct tty_operations ops = {
3695 .open = open,
3696 .close = close,
3697 .write = write,
3698 .put_char = put_char,
3699 .flush_chars = flush_chars,
3700 .write_room = write_room,
3701 .chars_in_buffer = chars_in_buffer,
3702 .flush_buffer = flush_buffer,
3703 .ioctl = ioctl,
3704 .compat_ioctl = slgt_compat_ioctl,
3705 .throttle = throttle,
3706 .unthrottle = unthrottle,
3707 .send_xchar = send_xchar,
3708 .break_ctl = set_break,
3709 .wait_until_sent = wait_until_sent,
3710 .set_termios = set_termios,
3711 .stop = tx_hold,
3712 .start = tx_release,
3713 .hangup = hangup,
3714 .tiocmget = tiocmget,
3715 .tiocmset = tiocmset,
3716 .get_icount = get_icount,
3717 .proc_fops = &synclink_gt_proc_fops,
3718};
3719
3720static void slgt_cleanup(void)
3721{
3722 int rc;
3723 struct slgt_info *info;
3724 struct slgt_info *tmp;
3725
3726 printk(KERN_INFO "unload %s\n", driver_name);
3727
3728 if (serial_driver) {
3729 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3730 tty_unregister_device(serial_driver, info->line);
3731 rc = tty_unregister_driver(serial_driver);
3732 if (rc)
3733 DBGERR(("tty_unregister_driver error=%d\n", rc));
3734 put_tty_driver(serial_driver);
3735 }
3736
3737 /* reset devices */
3738 info = slgt_device_list;
3739 while(info) {
3740 reset_port(info);
3741 info = info->next_device;
3742 }
3743
3744 /* release devices */
3745 info = slgt_device_list;
3746 while(info) {
3747#if SYNCLINK_GENERIC_HDLC
3748 hdlcdev_exit(info);
3749#endif
3750 free_dma_bufs(info);
3751 free_tmp_rbuf(info);
3752 if (info->port_num == 0)
3753 release_resources(info);
3754 tmp = info;
3755 info = info->next_device;
3756 tty_port_destroy(&tmp->port);
3757 kfree(tmp);
3758 }
3759
3760 if (pci_registered)
3761 pci_unregister_driver(&pci_driver);
3762}
3763
3764/*
3765 * Driver initialization entry point.
3766 */
3767static int __init slgt_init(void)
3768{
3769 int rc;
3770
3771 printk(KERN_INFO "%s\n", driver_name);
3772
3773 serial_driver = alloc_tty_driver(MAX_DEVICES);
3774 if (!serial_driver) {
3775 printk("%s can't allocate tty driver\n", driver_name);
3776 return -ENOMEM;
3777 }
3778
3779 /* Initialize the tty_driver structure */
3780
3781 serial_driver->driver_name = slgt_driver_name;
3782 serial_driver->name = tty_dev_prefix;
3783 serial_driver->major = ttymajor;
3784 serial_driver->minor_start = 64;
3785 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3786 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3787 serial_driver->init_termios = tty_std_termios;
3788 serial_driver->init_termios.c_cflag =
3789 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3790 serial_driver->init_termios.c_ispeed = 9600;
3791 serial_driver->init_termios.c_ospeed = 9600;
3792 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3793 tty_set_operations(serial_driver, &ops);
3794 if ((rc = tty_register_driver(serial_driver)) < 0) {
3795 DBGERR(("%s can't register serial driver\n", driver_name));
3796 put_tty_driver(serial_driver);
3797 serial_driver = NULL;
3798 goto error;
3799 }
3800
3801 printk(KERN_INFO "%s, tty major#%d\n",
3802 driver_name, serial_driver->major);
3803
3804 slgt_device_count = 0;
3805 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3806 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3807 goto error;
3808 }
3809 pci_registered = true;
3810
3811 if (!slgt_device_list)
3812 printk("%s no devices found\n",driver_name);
3813
3814 return 0;
3815
3816error:
3817 slgt_cleanup();
3818 return rc;
3819}
3820
3821static void __exit slgt_exit(void)
3822{
3823 slgt_cleanup();
3824}
3825
3826module_init(slgt_init);
3827module_exit(slgt_exit);
3828
3829/*
3830 * register access routines
3831 */
3832
3833#define CALC_REGADDR() \
3834 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3835 if (addr >= 0x80) \
3836 reg_addr += (info->port_num) * 32; \
3837 else if (addr >= 0x40) \
3838 reg_addr += (info->port_num) * 16;
3839
3840static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3841{
3842 CALC_REGADDR();
3843 return readb((void __iomem *)reg_addr);
3844}
3845
3846static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3847{
3848 CALC_REGADDR();
3849 writeb(value, (void __iomem *)reg_addr);
3850}
3851
3852static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3853{
3854 CALC_REGADDR();
3855 return readw((void __iomem *)reg_addr);
3856}
3857
3858static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3859{
3860 CALC_REGADDR();
3861 writew(value, (void __iomem *)reg_addr);
3862}
3863
3864static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3865{
3866 CALC_REGADDR();
3867 return readl((void __iomem *)reg_addr);
3868}
3869
3870static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3871{
3872 CALC_REGADDR();
3873 writel(value, (void __iomem *)reg_addr);
3874}
3875
3876static void rdma_reset(struct slgt_info *info)
3877{
3878 unsigned int i;
3879
3880 /* set reset bit */
3881 wr_reg32(info, RDCSR, BIT1);
3882
3883 /* wait for enable bit cleared */
3884 for(i=0 ; i < 1000 ; i++)
3885 if (!(rd_reg32(info, RDCSR) & BIT0))
3886 break;
3887}
3888
3889static void tdma_reset(struct slgt_info *info)
3890{
3891 unsigned int i;
3892
3893 /* set reset bit */
3894 wr_reg32(info, TDCSR, BIT1);
3895
3896 /* wait for enable bit cleared */
3897 for(i=0 ; i < 1000 ; i++)
3898 if (!(rd_reg32(info, TDCSR) & BIT0))
3899 break;
3900}
3901
3902/*
3903 * enable internal loopback
3904 * TxCLK and RxCLK are generated from BRG
3905 * and TxD is looped back to RxD internally.
3906 */
3907static void enable_loopback(struct slgt_info *info)
3908{
3909 /* SCR (serial control) BIT2=loopback enable */
3910 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3911
3912 if (info->params.mode != MGSL_MODE_ASYNC) {
3913 /* CCR (clock control)
3914 * 07..05 tx clock source (010 = BRG)
3915 * 04..02 rx clock source (010 = BRG)
3916 * 01 auxclk enable (0 = disable)
3917 * 00 BRG enable (1 = enable)
3918 *
3919 * 0100 1001
3920 */
3921 wr_reg8(info, CCR, 0x49);
3922
3923 /* set speed if available, otherwise use default */
3924 if (info->params.clock_speed)
3925 set_rate(info, info->params.clock_speed);
3926 else
3927 set_rate(info, 3686400);
3928 }
3929}
3930
3931/*
3932 * set baud rate generator to specified rate
3933 */
3934static void set_rate(struct slgt_info *info, u32 rate)
3935{
3936 unsigned int div;
3937 unsigned int osc = info->base_clock;
3938
3939 /* div = osc/rate - 1
3940 *
3941 * Round div up if osc/rate is not integer to
3942 * force to next slowest rate.
3943 */
3944
3945 if (rate) {
3946 div = osc/rate;
3947 if (!(osc % rate) && div)
3948 div--;
3949 wr_reg16(info, BDR, (unsigned short)div);
3950 }
3951}
3952
3953static void rx_stop(struct slgt_info *info)
3954{
3955 unsigned short val;
3956
3957 /* disable and reset receiver */
3958 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3959 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3960 wr_reg16(info, RCR, val); /* clear reset bit */
3961
3962 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3963
3964 /* clear pending rx interrupts */
3965 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3966
3967 rdma_reset(info);
3968
3969 info->rx_enabled = false;
3970 info->rx_restart = false;
3971}
3972
3973static void rx_start(struct slgt_info *info)
3974{
3975 unsigned short val;
3976
3977 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3978
3979 /* clear pending rx overrun IRQ */
3980 wr_reg16(info, SSR, IRQ_RXOVER);
3981
3982 /* reset and disable receiver */
3983 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3984 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3985 wr_reg16(info, RCR, val); /* clear reset bit */
3986
3987 rdma_reset(info);
3988 reset_rbufs(info);
3989
3990 if (info->rx_pio) {
3991 /* rx request when rx FIFO not empty */
3992 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3993 slgt_irq_on(info, IRQ_RXDATA);
3994 if (info->params.mode == MGSL_MODE_ASYNC) {
3995 /* enable saving of rx status */
3996 wr_reg32(info, RDCSR, BIT6);
3997 }
3998 } else {
3999 /* rx request when rx FIFO half full */
4000 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4001 /* set 1st descriptor address */
4002 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4003
4004 if (info->params.mode != MGSL_MODE_ASYNC) {
4005 /* enable rx DMA and DMA interrupt */
4006 wr_reg32(info, RDCSR, (BIT2 + BIT0));
4007 } else {
4008 /* enable saving of rx status, rx DMA and DMA interrupt */
4009 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4010 }
4011 }
4012
4013 slgt_irq_on(info, IRQ_RXOVER);
4014
4015 /* enable receiver */
4016 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4017
4018 info->rx_restart = false;
4019 info->rx_enabled = true;
4020}
4021
4022static void tx_start(struct slgt_info *info)
4023{
4024 if (!info->tx_enabled) {
4025 wr_reg16(info, TCR,
4026 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4027 info->tx_enabled = true;
4028 }
4029
4030 if (desc_count(info->tbufs[info->tbuf_start])) {
4031 info->drop_rts_on_tx_done = false;
4032
4033 if (info->params.mode != MGSL_MODE_ASYNC) {
4034 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4035 get_signals(info);
4036 if (!(info->signals & SerialSignal_RTS)) {
4037 info->signals |= SerialSignal_RTS;
4038 set_signals(info);
4039 info->drop_rts_on_tx_done = true;
4040 }
4041 }
4042
4043 slgt_irq_off(info, IRQ_TXDATA);
4044 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4045 /* clear tx idle and underrun status bits */
4046 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4047 } else {
4048 slgt_irq_off(info, IRQ_TXDATA);
4049 slgt_irq_on(info, IRQ_TXIDLE);
4050 /* clear tx idle status bit */
4051 wr_reg16(info, SSR, IRQ_TXIDLE);
4052 }
4053 /* set 1st descriptor address and start DMA */
4054 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4055 wr_reg32(info, TDCSR, BIT2 + BIT0);
4056 info->tx_active = true;
4057 }
4058}
4059
4060static void tx_stop(struct slgt_info *info)
4061{
4062 unsigned short val;
4063
4064 del_timer(&info->tx_timer);
4065
4066 tdma_reset(info);
4067
4068 /* reset and disable transmitter */
4069 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4070 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4071
4072 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4073
4074 /* clear tx idle and underrun status bit */
4075 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4076
4077 reset_tbufs(info);
4078
4079 info->tx_enabled = false;
4080 info->tx_active = false;
4081}
4082
4083static void reset_port(struct slgt_info *info)
4084{
4085 if (!info->reg_addr)
4086 return;
4087
4088 tx_stop(info);
4089 rx_stop(info);
4090
4091 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4092 set_signals(info);
4093
4094 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4095}
4096
4097static void reset_adapter(struct slgt_info *info)
4098{
4099 int i;
4100 for (i=0; i < info->port_count; ++i) {
4101 if (info->port_array[i])
4102 reset_port(info->port_array[i]);
4103 }
4104}
4105
4106static void async_mode(struct slgt_info *info)
4107{
4108 unsigned short val;
4109
4110 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4111 tx_stop(info);
4112 rx_stop(info);
4113
4114 /* TCR (tx control)
4115 *
4116 * 15..13 mode, 010=async
4117 * 12..10 encoding, 000=NRZ
4118 * 09 parity enable
4119 * 08 1=odd parity, 0=even parity
4120 * 07 1=RTS driver control
4121 * 06 1=break enable
4122 * 05..04 character length
4123 * 00=5 bits
4124 * 01=6 bits
4125 * 10=7 bits
4126 * 11=8 bits
4127 * 03 0=1 stop bit, 1=2 stop bits
4128 * 02 reset
4129 * 01 enable
4130 * 00 auto-CTS enable
4131 */
4132 val = 0x4000;
4133
4134 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4135 val |= BIT7;
4136
4137 if (info->params.parity != ASYNC_PARITY_NONE) {
4138 val |= BIT9;
4139 if (info->params.parity == ASYNC_PARITY_ODD)
4140 val |= BIT8;
4141 }
4142
4143 switch (info->params.data_bits)
4144 {
4145 case 6: val |= BIT4; break;
4146 case 7: val |= BIT5; break;
4147 case 8: val |= BIT5 + BIT4; break;
4148 }
4149
4150 if (info->params.stop_bits != 1)
4151 val |= BIT3;
4152
4153 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4154 val |= BIT0;
4155
4156 wr_reg16(info, TCR, val);
4157
4158 /* RCR (rx control)
4159 *
4160 * 15..13 mode, 010=async
4161 * 12..10 encoding, 000=NRZ
4162 * 09 parity enable
4163 * 08 1=odd parity, 0=even parity
4164 * 07..06 reserved, must be 0
4165 * 05..04 character length
4166 * 00=5 bits
4167 * 01=6 bits
4168 * 10=7 bits
4169 * 11=8 bits
4170 * 03 reserved, must be zero
4171 * 02 reset
4172 * 01 enable
4173 * 00 auto-DCD enable
4174 */
4175 val = 0x4000;
4176
4177 if (info->params.parity != ASYNC_PARITY_NONE) {
4178 val |= BIT9;
4179 if (info->params.parity == ASYNC_PARITY_ODD)
4180 val |= BIT8;
4181 }
4182
4183 switch (info->params.data_bits)
4184 {
4185 case 6: val |= BIT4; break;
4186 case 7: val |= BIT5; break;
4187 case 8: val |= BIT5 + BIT4; break;
4188 }
4189
4190 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4191 val |= BIT0;
4192
4193 wr_reg16(info, RCR, val);
4194
4195 /* CCR (clock control)
4196 *
4197 * 07..05 011 = tx clock source is BRG/16
4198 * 04..02 010 = rx clock source is BRG
4199 * 01 0 = auxclk disabled
4200 * 00 1 = BRG enabled
4201 *
4202 * 0110 1001
4203 */
4204 wr_reg8(info, CCR, 0x69);
4205
4206 msc_set_vcr(info);
4207
4208 /* SCR (serial control)
4209 *
4210 * 15 1=tx req on FIFO half empty
4211 * 14 1=rx req on FIFO half full
4212 * 13 tx data IRQ enable
4213 * 12 tx idle IRQ enable
4214 * 11 rx break on IRQ enable
4215 * 10 rx data IRQ enable
4216 * 09 rx break off IRQ enable
4217 * 08 overrun IRQ enable
4218 * 07 DSR IRQ enable
4219 * 06 CTS IRQ enable
4220 * 05 DCD IRQ enable
4221 * 04 RI IRQ enable
4222 * 03 0=16x sampling, 1=8x sampling
4223 * 02 1=txd->rxd internal loopback enable
4224 * 01 reserved, must be zero
4225 * 00 1=master IRQ enable
4226 */
4227 val = BIT15 + BIT14 + BIT0;
4228 /* JCR[8] : 1 = x8 async mode feature available */
4229 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4230 ((info->base_clock < (info->params.data_rate * 16)) ||
4231 (info->base_clock % (info->params.data_rate * 16)))) {
4232 /* use 8x sampling */
4233 val |= BIT3;
4234 set_rate(info, info->params.data_rate * 8);
4235 } else {
4236 /* use 16x sampling */
4237 set_rate(info, info->params.data_rate * 16);
4238 }
4239 wr_reg16(info, SCR, val);
4240
4241 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4242
4243 if (info->params.loopback)
4244 enable_loopback(info);
4245}
4246
4247static void sync_mode(struct slgt_info *info)
4248{
4249 unsigned short val;
4250
4251 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4252 tx_stop(info);
4253 rx_stop(info);
4254
4255 /* TCR (tx control)
4256 *
4257 * 15..13 mode
4258 * 000=HDLC/SDLC
4259 * 001=raw bit synchronous
4260 * 010=asynchronous/isochronous
4261 * 011=monosync byte synchronous
4262 * 100=bisync byte synchronous
4263 * 101=xsync byte synchronous
4264 * 12..10 encoding
4265 * 09 CRC enable
4266 * 08 CRC32
4267 * 07 1=RTS driver control
4268 * 06 preamble enable
4269 * 05..04 preamble length
4270 * 03 share open/close flag
4271 * 02 reset
4272 * 01 enable
4273 * 00 auto-CTS enable
4274 */
4275 val = BIT2;
4276
4277 switch(info->params.mode) {
4278 case MGSL_MODE_XSYNC:
4279 val |= BIT15 + BIT13;
4280 break;
4281 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4282 case MGSL_MODE_BISYNC: val |= BIT15; break;
4283 case MGSL_MODE_RAW: val |= BIT13; break;
4284 }
4285 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4286 val |= BIT7;
4287
4288 switch(info->params.encoding)
4289 {
4290 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4291 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4292 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4293 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4294 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4295 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4296 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4297 }
4298
4299 switch (info->params.crc_type & HDLC_CRC_MASK)
4300 {
4301 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4302 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4303 }
4304
4305 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4306 val |= BIT6;
4307
4308 switch (info->params.preamble_length)
4309 {
4310 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4311 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4312 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4313 }
4314
4315 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4316 val |= BIT0;
4317
4318 wr_reg16(info, TCR, val);
4319
4320 /* TPR (transmit preamble) */
4321
4322 switch (info->params.preamble)
4323 {
4324 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4325 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4326 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4327 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4328 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4329 default: val = 0x7e; break;
4330 }
4331 wr_reg8(info, TPR, (unsigned char)val);
4332
4333 /* RCR (rx control)
4334 *
4335 * 15..13 mode
4336 * 000=HDLC/SDLC
4337 * 001=raw bit synchronous
4338 * 010=asynchronous/isochronous
4339 * 011=monosync byte synchronous
4340 * 100=bisync byte synchronous
4341 * 101=xsync byte synchronous
4342 * 12..10 encoding
4343 * 09 CRC enable
4344 * 08 CRC32
4345 * 07..03 reserved, must be 0
4346 * 02 reset
4347 * 01 enable
4348 * 00 auto-DCD enable
4349 */
4350 val = 0;
4351
4352 switch(info->params.mode) {
4353 case MGSL_MODE_XSYNC:
4354 val |= BIT15 + BIT13;
4355 break;
4356 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4357 case MGSL_MODE_BISYNC: val |= BIT15; break;
4358 case MGSL_MODE_RAW: val |= BIT13; break;
4359 }
4360
4361 switch(info->params.encoding)
4362 {
4363 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4364 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4365 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4366 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4367 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4368 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4369 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4370 }
4371
4372 switch (info->params.crc_type & HDLC_CRC_MASK)
4373 {
4374 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4375 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4376 }
4377
4378 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4379 val |= BIT0;
4380
4381 wr_reg16(info, RCR, val);
4382
4383 /* CCR (clock control)
4384 *
4385 * 07..05 tx clock source
4386 * 04..02 rx clock source
4387 * 01 auxclk enable
4388 * 00 BRG enable
4389 */
4390 val = 0;
4391
4392 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4393 {
4394 // when RxC source is DPLL, BRG generates 16X DPLL
4395 // reference clock, so take TxC from BRG/16 to get
4396 // transmit clock at actual data rate
4397 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4398 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4399 else
4400 val |= BIT6; /* 010, txclk = BRG */
4401 }
4402 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4403 val |= BIT7; /* 100, txclk = DPLL Input */
4404 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4405 val |= BIT5; /* 001, txclk = RXC Input */
4406
4407 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4408 val |= BIT3; /* 010, rxclk = BRG */
4409 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4410 val |= BIT4; /* 100, rxclk = DPLL */
4411 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4412 val |= BIT2; /* 001, rxclk = TXC Input */
4413
4414 if (info->params.clock_speed)
4415 val |= BIT1 + BIT0;
4416
4417 wr_reg8(info, CCR, (unsigned char)val);
4418
4419 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4420 {
4421 // program DPLL mode
4422 switch(info->params.encoding)
4423 {
4424 case HDLC_ENCODING_BIPHASE_MARK:
4425 case HDLC_ENCODING_BIPHASE_SPACE:
4426 val = BIT7; break;
4427 case HDLC_ENCODING_BIPHASE_LEVEL:
4428 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4429 val = BIT7 + BIT6; break;
4430 default: val = BIT6; // NRZ encodings
4431 }
4432 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4433
4434 // DPLL requires a 16X reference clock from BRG
4435 set_rate(info, info->params.clock_speed * 16);
4436 }
4437 else
4438 set_rate(info, info->params.clock_speed);
4439
4440 tx_set_idle(info);
4441
4442 msc_set_vcr(info);
4443
4444 /* SCR (serial control)
4445 *
4446 * 15 1=tx req on FIFO half empty
4447 * 14 1=rx req on FIFO half full
4448 * 13 tx data IRQ enable
4449 * 12 tx idle IRQ enable
4450 * 11 underrun IRQ enable
4451 * 10 rx data IRQ enable
4452 * 09 rx idle IRQ enable
4453 * 08 overrun IRQ enable
4454 * 07 DSR IRQ enable
4455 * 06 CTS IRQ enable
4456 * 05 DCD IRQ enable
4457 * 04 RI IRQ enable
4458 * 03 reserved, must be zero
4459 * 02 1=txd->rxd internal loopback enable
4460 * 01 reserved, must be zero
4461 * 00 1=master IRQ enable
4462 */
4463 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4464
4465 if (info->params.loopback)
4466 enable_loopback(info);
4467}
4468
4469/*
4470 * set transmit idle mode
4471 */
4472static void tx_set_idle(struct slgt_info *info)
4473{
4474 unsigned char val;
4475 unsigned short tcr;
4476
4477 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4478 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4479 */
4480 tcr = rd_reg16(info, TCR);
4481 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4482 /* disable preamble, set idle size to 16 bits */
4483 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4484 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4485 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4486 } else if (!(tcr & BIT6)) {
4487 /* preamble is disabled, set idle size to 8 bits */
4488 tcr &= ~(BIT5 + BIT4);
4489 }
4490 wr_reg16(info, TCR, tcr);
4491
4492 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4493 /* LSB of custom tx idle specified in tx idle register */
4494 val = (unsigned char)(info->idle_mode & 0xff);
4495 } else {
4496 /* standard 8 bit idle patterns */
4497 switch(info->idle_mode)
4498 {
4499 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4500 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4501 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4502 case HDLC_TXIDLE_ZEROS:
4503 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4504 default: val = 0xff;
4505 }
4506 }
4507
4508 wr_reg8(info, TIR, val);
4509}
4510
4511/*
4512 * get state of V24 status (input) signals
4513 */
4514static void get_signals(struct slgt_info *info)
4515{
4516 unsigned short status = rd_reg16(info, SSR);
4517
4518 /* clear all serial signals except RTS and DTR */
4519 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4520
4521 if (status & BIT3)
4522 info->signals |= SerialSignal_DSR;
4523 if (status & BIT2)
4524 info->signals |= SerialSignal_CTS;
4525 if (status & BIT1)
4526 info->signals |= SerialSignal_DCD;
4527 if (status & BIT0)
4528 info->signals |= SerialSignal_RI;
4529}
4530
4531/*
4532 * set V.24 Control Register based on current configuration
4533 */
4534static void msc_set_vcr(struct slgt_info *info)
4535{
4536 unsigned char val = 0;
4537
4538 /* VCR (V.24 control)
4539 *
4540 * 07..04 serial IF select
4541 * 03 DTR
4542 * 02 RTS
4543 * 01 LL
4544 * 00 RL
4545 */
4546
4547 switch(info->if_mode & MGSL_INTERFACE_MASK)
4548 {
4549 case MGSL_INTERFACE_RS232:
4550 val |= BIT5; /* 0010 */
4551 break;
4552 case MGSL_INTERFACE_V35:
4553 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4554 break;
4555 case MGSL_INTERFACE_RS422:
4556 val |= BIT6; /* 0100 */
4557 break;
4558 }
4559
4560 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4561 val |= BIT4;
4562 if (info->signals & SerialSignal_DTR)
4563 val |= BIT3;
4564 if (info->signals & SerialSignal_RTS)
4565 val |= BIT2;
4566 if (info->if_mode & MGSL_INTERFACE_LL)
4567 val |= BIT1;
4568 if (info->if_mode & MGSL_INTERFACE_RL)
4569 val |= BIT0;
4570 wr_reg8(info, VCR, val);
4571}
4572
4573/*
4574 * set state of V24 control (output) signals
4575 */
4576static void set_signals(struct slgt_info *info)
4577{
4578 unsigned char val = rd_reg8(info, VCR);
4579 if (info->signals & SerialSignal_DTR)
4580 val |= BIT3;
4581 else
4582 val &= ~BIT3;
4583 if (info->signals & SerialSignal_RTS)
4584 val |= BIT2;
4585 else
4586 val &= ~BIT2;
4587 wr_reg8(info, VCR, val);
4588}
4589
4590/*
4591 * free range of receive DMA buffers (i to last)
4592 */
4593static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4594{
4595 int done = 0;
4596
4597 while(!done) {
4598 /* reset current buffer for reuse */
4599 info->rbufs[i].status = 0;
4600 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4601 if (i == last)
4602 done = 1;
4603 if (++i == info->rbuf_count)
4604 i = 0;
4605 }
4606 info->rbuf_current = i;
4607}
4608
4609/*
4610 * mark all receive DMA buffers as free
4611 */
4612static void reset_rbufs(struct slgt_info *info)
4613{
4614 free_rbufs(info, 0, info->rbuf_count - 1);
4615 info->rbuf_fill_index = 0;
4616 info->rbuf_fill_count = 0;
4617}
4618
4619/*
4620 * pass receive HDLC frame to upper layer
4621 *
4622 * return true if frame available, otherwise false
4623 */
4624static bool rx_get_frame(struct slgt_info *info)
4625{
4626 unsigned int start, end;
4627 unsigned short status;
4628 unsigned int framesize = 0;
4629 unsigned long flags;
4630 struct tty_struct *tty = info->port.tty;
4631 unsigned char addr_field = 0xff;
4632 unsigned int crc_size = 0;
4633
4634 switch (info->params.crc_type & HDLC_CRC_MASK) {
4635 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4636 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4637 }
4638
4639check_again:
4640
4641 framesize = 0;
4642 addr_field = 0xff;
4643 start = end = info->rbuf_current;
4644
4645 for (;;) {
4646 if (!desc_complete(info->rbufs[end]))
4647 goto cleanup;
4648
4649 if (framesize == 0 && info->params.addr_filter != 0xff)
4650 addr_field = info->rbufs[end].buf[0];
4651
4652 framesize += desc_count(info->rbufs[end]);
4653
4654 if (desc_eof(info->rbufs[end]))
4655 break;
4656
4657 if (++end == info->rbuf_count)
4658 end = 0;
4659
4660 if (end == info->rbuf_current) {
4661 if (info->rx_enabled){
4662 spin_lock_irqsave(&info->lock,flags);
4663 rx_start(info);
4664 spin_unlock_irqrestore(&info->lock,flags);
4665 }
4666 goto cleanup;
4667 }
4668 }
4669
4670 /* status
4671 *
4672 * 15 buffer complete
4673 * 14..06 reserved
4674 * 05..04 residue
4675 * 02 eof (end of frame)
4676 * 01 CRC error
4677 * 00 abort
4678 */
4679 status = desc_status(info->rbufs[end]);
4680
4681 /* ignore CRC bit if not using CRC (bit is undefined) */
4682 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4683 status &= ~BIT1;
4684
4685 if (framesize == 0 ||
4686 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4687 free_rbufs(info, start, end);
4688 goto check_again;
4689 }
4690
4691 if (framesize < (2 + crc_size) || status & BIT0) {
4692 info->icount.rxshort++;
4693 framesize = 0;
4694 } else if (status & BIT1) {
4695 info->icount.rxcrc++;
4696 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4697 framesize = 0;
4698 }
4699
4700#if SYNCLINK_GENERIC_HDLC
4701 if (framesize == 0) {
4702 info->netdev->stats.rx_errors++;
4703 info->netdev->stats.rx_frame_errors++;
4704 }
4705#endif
4706
4707 DBGBH(("%s rx frame status=%04X size=%d\n",
4708 info->device_name, status, framesize));
4709 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4710
4711 if (framesize) {
4712 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4713 framesize -= crc_size;
4714 crc_size = 0;
4715 }
4716
4717 if (framesize > info->max_frame_size + crc_size)
4718 info->icount.rxlong++;
4719 else {
4720 /* copy dma buffer(s) to contiguous temp buffer */
4721 int copy_count = framesize;
4722 int i = start;
4723 unsigned char *p = info->tmp_rbuf;
4724 info->tmp_rbuf_count = framesize;
4725
4726 info->icount.rxok++;
4727
4728 while(copy_count) {
4729 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4730 memcpy(p, info->rbufs[i].buf, partial_count);
4731 p += partial_count;
4732 copy_count -= partial_count;
4733 if (++i == info->rbuf_count)
4734 i = 0;
4735 }
4736
4737 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4738 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4739 framesize++;
4740 }
4741
4742#if SYNCLINK_GENERIC_HDLC
4743 if (info->netcount)
4744 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4745 else
4746#endif
4747 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4748 }
4749 }
4750 free_rbufs(info, start, end);
4751 return true;
4752
4753cleanup:
4754 return false;
4755}
4756
4757/*
4758 * pass receive buffer (RAW synchronous mode) to tty layer
4759 * return true if buffer available, otherwise false
4760 */
4761static bool rx_get_buf(struct slgt_info *info)
4762{
4763 unsigned int i = info->rbuf_current;
4764 unsigned int count;
4765
4766 if (!desc_complete(info->rbufs[i]))
4767 return false;
4768 count = desc_count(info->rbufs[i]);
4769 switch(info->params.mode) {
4770 case MGSL_MODE_MONOSYNC:
4771 case MGSL_MODE_BISYNC:
4772 case MGSL_MODE_XSYNC:
4773 /* ignore residue in byte synchronous modes */
4774 if (desc_residue(info->rbufs[i]))
4775 count--;
4776 break;
4777 }
4778 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4779 DBGINFO(("rx_get_buf size=%d\n", count));
4780 if (count)
4781 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4782 info->flag_buf, count);
4783 free_rbufs(info, i, i);
4784 return true;
4785}
4786
4787static void reset_tbufs(struct slgt_info *info)
4788{
4789 unsigned int i;
4790 info->tbuf_current = 0;
4791 for (i=0 ; i < info->tbuf_count ; i++) {
4792 info->tbufs[i].status = 0;
4793 info->tbufs[i].count = 0;
4794 }
4795}
4796
4797/*
4798 * return number of free transmit DMA buffers
4799 */
4800static unsigned int free_tbuf_count(struct slgt_info *info)
4801{
4802 unsigned int count = 0;
4803 unsigned int i = info->tbuf_current;
4804
4805 do
4806 {
4807 if (desc_count(info->tbufs[i]))
4808 break; /* buffer in use */
4809 ++count;
4810 if (++i == info->tbuf_count)
4811 i=0;
4812 } while (i != info->tbuf_current);
4813
4814 /* if tx DMA active, last zero count buffer is in use */
4815 if (count && (rd_reg32(info, TDCSR) & BIT0))
4816 --count;
4817
4818 return count;
4819}
4820
4821/*
4822 * return number of bytes in unsent transmit DMA buffers
4823 * and the serial controller tx FIFO
4824 */
4825static unsigned int tbuf_bytes(struct slgt_info *info)
4826{
4827 unsigned int total_count = 0;
4828 unsigned int i = info->tbuf_current;
4829 unsigned int reg_value;
4830 unsigned int count;
4831 unsigned int active_buf_count = 0;
4832
4833 /*
4834 * Add descriptor counts for all tx DMA buffers.
4835 * If count is zero (cleared by DMA controller after read),
4836 * the buffer is complete or is actively being read from.
4837 *
4838 * Record buf_count of last buffer with zero count starting
4839 * from current ring position. buf_count is mirror
4840 * copy of count and is not cleared by serial controller.
4841 * If DMA controller is active, that buffer is actively
4842 * being read so add to total.
4843 */
4844 do {
4845 count = desc_count(info->tbufs[i]);
4846 if (count)
4847 total_count += count;
4848 else if (!total_count)
4849 active_buf_count = info->tbufs[i].buf_count;
4850 if (++i == info->tbuf_count)
4851 i = 0;
4852 } while (i != info->tbuf_current);
4853
4854 /* read tx DMA status register */
4855 reg_value = rd_reg32(info, TDCSR);
4856
4857 /* if tx DMA active, last zero count buffer is in use */
4858 if (reg_value & BIT0)
4859 total_count += active_buf_count;
4860
4861 /* add tx FIFO count = reg_value[15..8] */
4862 total_count += (reg_value >> 8) & 0xff;
4863
4864 /* if transmitter active add one byte for shift register */
4865 if (info->tx_active)
4866 total_count++;
4867
4868 return total_count;
4869}
4870
4871/*
4872 * load data into transmit DMA buffer ring and start transmitter if needed
4873 * return true if data accepted, otherwise false (buffers full)
4874 */
4875static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4876{
4877 unsigned short count;
4878 unsigned int i;
4879 struct slgt_desc *d;
4880
4881 /* check required buffer space */
4882 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4883 return false;
4884
4885 DBGDATA(info, buf, size, "tx");
4886
4887 /*
4888 * copy data to one or more DMA buffers in circular ring
4889 * tbuf_start = first buffer for this data
4890 * tbuf_current = next free buffer
4891 *
4892 * Copy all data before making data visible to DMA controller by
4893 * setting descriptor count of the first buffer.
4894 * This prevents an active DMA controller from reading the first DMA
4895 * buffers of a frame and stopping before the final buffers are filled.
4896 */
4897
4898 info->tbuf_start = i = info->tbuf_current;
4899
4900 while (size) {
4901 d = &info->tbufs[i];
4902
4903 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4904 memcpy(d->buf, buf, count);
4905
4906 size -= count;
4907 buf += count;
4908
4909 /*
4910 * set EOF bit for last buffer of HDLC frame or
4911 * for every buffer in raw mode
4912 */
4913 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4914 info->params.mode == MGSL_MODE_RAW)
4915 set_desc_eof(*d, 1);
4916 else
4917 set_desc_eof(*d, 0);
4918
4919 /* set descriptor count for all but first buffer */
4920 if (i != info->tbuf_start)
4921 set_desc_count(*d, count);
4922 d->buf_count = count;
4923
4924 if (++i == info->tbuf_count)
4925 i = 0;
4926 }
4927
4928 info->tbuf_current = i;
4929
4930 /* set first buffer count to make new data visible to DMA controller */
4931 d = &info->tbufs[info->tbuf_start];
4932 set_desc_count(*d, d->buf_count);
4933
4934 /* start transmitter if needed and update transmit timeout */
4935 if (!info->tx_active)
4936 tx_start(info);
4937 update_tx_timer(info);
4938
4939 return true;
4940}
4941
4942static int register_test(struct slgt_info *info)
4943{
4944 static unsigned short patterns[] =
4945 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4946 static unsigned int count = ARRAY_SIZE(patterns);
4947 unsigned int i;
4948 int rc = 0;
4949
4950 for (i=0 ; i < count ; i++) {
4951 wr_reg16(info, TIR, patterns[i]);
4952 wr_reg16(info, BDR, patterns[(i+1)%count]);
4953 if ((rd_reg16(info, TIR) != patterns[i]) ||
4954 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4955 rc = -ENODEV;
4956 break;
4957 }
4958 }
4959 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4960 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4961 return rc;
4962}
4963
4964static int irq_test(struct slgt_info *info)
4965{
4966 unsigned long timeout;
4967 unsigned long flags;
4968 struct tty_struct *oldtty = info->port.tty;
4969 u32 speed = info->params.data_rate;
4970
4971 info->params.data_rate = 921600;
4972 info->port.tty = NULL;
4973
4974 spin_lock_irqsave(&info->lock, flags);
4975 async_mode(info);
4976 slgt_irq_on(info, IRQ_TXIDLE);
4977
4978 /* enable transmitter */
4979 wr_reg16(info, TCR,
4980 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4981
4982 /* write one byte and wait for tx idle */
4983 wr_reg16(info, TDR, 0);
4984
4985 /* assume failure */
4986 info->init_error = DiagStatus_IrqFailure;
4987 info->irq_occurred = false;
4988
4989 spin_unlock_irqrestore(&info->lock, flags);
4990
4991 timeout=100;
4992 while(timeout-- && !info->irq_occurred)
4993 msleep_interruptible(10);
4994
4995 spin_lock_irqsave(&info->lock,flags);
4996 reset_port(info);
4997 spin_unlock_irqrestore(&info->lock,flags);
4998
4999 info->params.data_rate = speed;
5000 info->port.tty = oldtty;
5001
5002 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5003 return info->irq_occurred ? 0 : -ENODEV;
5004}
5005
5006static int loopback_test_rx(struct slgt_info *info)
5007{
5008 unsigned char *src, *dest;
5009 int count;
5010
5011 if (desc_complete(info->rbufs[0])) {
5012 count = desc_count(info->rbufs[0]);
5013 src = info->rbufs[0].buf;
5014 dest = info->tmp_rbuf;
5015
5016 for( ; count ; count-=2, src+=2) {
5017 /* src=data byte (src+1)=status byte */
5018 if (!(*(src+1) & (BIT9 + BIT8))) {
5019 *dest = *src;
5020 dest++;
5021 info->tmp_rbuf_count++;
5022 }
5023 }
5024 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5025 return 1;
5026 }
5027 return 0;
5028}
5029
5030static int loopback_test(struct slgt_info *info)
5031{
5032#define TESTFRAMESIZE 20
5033
5034 unsigned long timeout;
5035 u16 count = TESTFRAMESIZE;
5036 unsigned char buf[TESTFRAMESIZE];
5037 int rc = -ENODEV;
5038 unsigned long flags;
5039
5040 struct tty_struct *oldtty = info->port.tty;
5041 MGSL_PARAMS params;
5042
5043 memcpy(&params, &info->params, sizeof(params));
5044
5045 info->params.mode = MGSL_MODE_ASYNC;
5046 info->params.data_rate = 921600;
5047 info->params.loopback = 1;
5048 info->port.tty = NULL;
5049
5050 /* build and send transmit frame */
5051 for (count = 0; count < TESTFRAMESIZE; ++count)
5052 buf[count] = (unsigned char)count;
5053
5054 info->tmp_rbuf_count = 0;
5055 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5056
5057 /* program hardware for HDLC and enabled receiver */
5058 spin_lock_irqsave(&info->lock,flags);
5059 async_mode(info);
5060 rx_start(info);
5061 tx_load(info, buf, count);
5062 spin_unlock_irqrestore(&info->lock, flags);
5063
5064 /* wait for receive complete */
5065 for (timeout = 100; timeout; --timeout) {
5066 msleep_interruptible(10);
5067 if (loopback_test_rx(info)) {
5068 rc = 0;
5069 break;
5070 }
5071 }
5072
5073 /* verify received frame length and contents */
5074 if (!rc && (info->tmp_rbuf_count != count ||
5075 memcmp(buf, info->tmp_rbuf, count))) {
5076 rc = -ENODEV;
5077 }
5078
5079 spin_lock_irqsave(&info->lock,flags);
5080 reset_adapter(info);
5081 spin_unlock_irqrestore(&info->lock,flags);
5082
5083 memcpy(&info->params, &params, sizeof(info->params));
5084 info->port.tty = oldtty;
5085
5086 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5087 return rc;
5088}
5089
5090static int adapter_test(struct slgt_info *info)
5091{
5092 DBGINFO(("testing %s\n", info->device_name));
5093 if (register_test(info) < 0) {
5094 printk("register test failure %s addr=%08X\n",
5095 info->device_name, info->phys_reg_addr);
5096 } else if (irq_test(info) < 0) {
5097 printk("IRQ test failure %s IRQ=%d\n",
5098 info->device_name, info->irq_level);
5099 } else if (loopback_test(info) < 0) {
5100 printk("loopback test failure %s\n", info->device_name);
5101 }
5102 return info->init_error;
5103}
5104
5105/*
5106 * transmit timeout handler
5107 */
5108static void tx_timeout(unsigned long context)
5109{
5110 struct slgt_info *info = (struct slgt_info*)context;
5111 unsigned long flags;
5112
5113 DBGINFO(("%s tx_timeout\n", info->device_name));
5114 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5115 info->icount.txtimeout++;
5116 }
5117 spin_lock_irqsave(&info->lock,flags);
5118 tx_stop(info);
5119 spin_unlock_irqrestore(&info->lock,flags);
5120
5121#if SYNCLINK_GENERIC_HDLC
5122 if (info->netcount)
5123 hdlcdev_tx_done(info);
5124 else
5125#endif
5126 bh_transmit(info);
5127}
5128
5129/*
5130 * receive buffer polling timer
5131 */
5132static void rx_timeout(unsigned long context)
5133{
5134 struct slgt_info *info = (struct slgt_info*)context;
5135 unsigned long flags;
5136
5137 DBGINFO(("%s rx_timeout\n", info->device_name));
5138 spin_lock_irqsave(&info->lock, flags);
5139 info->pending_bh |= BH_RECEIVE;
5140 spin_unlock_irqrestore(&info->lock, flags);
5141 bh_handler(&info->task);
5142}
5143