blob: 4a42368734644b4622010ec8e16862cbe5703580 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
33#include "debug.h"
34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
38/**
39 * dwc3_gadget_set_test_mode - enables usb2 test modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will return 0 on
44 * success or -EINVAL if wrong Test Selector is passed.
45 */
46int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
47{
48 u32 reg;
49
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
52
53 switch (mode) {
54 case TEST_J:
55 case TEST_K:
56 case TEST_SE0_NAK:
57 case TEST_PACKET:
58 case TEST_FORCE_EN:
59 reg |= mode << 1;
60 break;
61 default:
62 return -EINVAL;
63 }
64
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66
67 return 0;
68}
69
70/**
71 * dwc3_gadget_get_link_state - gets current state of usb link
72 * @dwc: pointer to our context structure
73 *
74 * Caller should take care of locking. This function will
75 * return the link state on success (>= 0) or -ETIMEDOUT.
76 */
77int dwc3_gadget_get_link_state(struct dwc3 *dwc)
78{
79 u32 reg;
80
81 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
82
83 return DWC3_DSTS_USBLNKST(reg);
84}
85
86/**
87 * dwc3_gadget_set_link_state - sets usb link to a particular state
88 * @dwc: pointer to our context structure
89 * @state: the state to put link into
90 *
91 * Caller should take care of locking. This function will
92 * return 0 on success or -ETIMEDOUT.
93 */
94int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95{
96 int retries = 10000;
97 u32 reg;
98
99 /*
100 * Wait until device controller is ready. Only applies to 1.94a and
101 * later RTL.
102 */
103 if (dwc->revision >= DWC3_REVISION_194A) {
104 while (--retries) {
105 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
106 if (reg & DWC3_DSTS_DCNRD)
107 udelay(5);
108 else
109 break;
110 }
111
112 if (retries <= 0)
113 return -ETIMEDOUT;
114 }
115
116 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
118
119 /* set requested state */
120 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
121 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122
123 /*
124 * The following code is racy when called from dwc3_gadget_wakeup,
125 * and is not needed, at least on newer versions
126 */
127 if (dwc->revision >= DWC3_REVISION_194A)
128 return 0;
129
130 /* wait for a change in DSTS */
131 retries = 10000;
132 while (--retries) {
133 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
134
135 if (DWC3_DSTS_USBLNKST(reg) == state)
136 return 0;
137
138 udelay(5);
139 }
140
141 return -ETIMEDOUT;
142}
143
144/**
145 * dwc3_ep_inc_trb - increment a trb index.
146 * @index: Pointer to the TRB index to increment.
147 *
148 * The index should never point to the link TRB. After incrementing,
149 * if it is point to the link TRB, wrap around to the beginning. The
150 * link TRB is always at the last TRB entry.
151 */
152static void dwc3_ep_inc_trb(u8 *index)
153{
154 (*index)++;
155 if (*index == (DWC3_TRB_NUM - 1))
156 *index = 0;
157}
158
159/**
160 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
161 * @dep: The endpoint whose enqueue pointer we're incrementing
162 */
163static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
164{
165 dwc3_ep_inc_trb(&dep->trb_enqueue);
166}
167
168/**
169 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
170 * @dep: The endpoint whose enqueue pointer we're incrementing
171 */
172static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
173{
174 dwc3_ep_inc_trb(&dep->trb_dequeue);
175}
176
177void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
178 struct dwc3_request *req, int status)
179{
180 struct dwc3 *dwc = dep->dwc;
181
182 req->started = false;
183 list_del(&req->list);
184 req->remaining = 0;
185 req->unaligned = false;
186 req->zero = false;
187
188 if (req->request.status == -EINPROGRESS)
189 req->request.status = status;
190
191 if (req->trb)
192 usb_gadget_unmap_request_by_dev(dwc->sysdev,
193 &req->request, req->direction);
194
195 req->trb = NULL;
196 trace_dwc3_gadget_giveback(req);
197
198 if (dep->number > 1)
199 pm_runtime_put(dwc->dev);
200}
201
202/**
203 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
204 * @dep: The endpoint to whom the request belongs to
205 * @req: The request we're giving back
206 * @status: completion code for the request
207 *
208 * Must be called with controller's lock held and interrupts disabled. This
209 * function will unmap @req and call its ->complete() callback to notify upper
210 * layers that it has completed.
211 */
212void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
213 int status)
214{
215 struct dwc3 *dwc = dep->dwc;
216
217 dwc3_gadget_del_and_unmap_request(dep, req, status);
218
219 spin_unlock(&dwc->lock);
220 usb_gadget_giveback_request(&dep->endpoint, &req->request);
221 spin_lock(&dwc->lock);
222}
223
224/**
225 * dwc3_send_gadget_generic_command - issue a generic command for the controller
226 * @dwc: pointer to the controller context
227 * @cmd: the command to be issued
228 * @param: command parameter
229 *
230 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
231 * and wait for its completion.
232 */
233int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
234{
235 u32 timeout = 500;
236 int status = 0;
237 int ret = 0;
238 u32 reg;
239
240 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
241 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
242
243 do {
244 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
245 if (!(reg & DWC3_DGCMD_CMDACT)) {
246 status = DWC3_DGCMD_STATUS(reg);
247 if (status)
248 ret = -EINVAL;
249 break;
250 }
251 } while (--timeout);
252
253 if (!timeout) {
254 ret = -ETIMEDOUT;
255 status = -ETIMEDOUT;
256 }
257
258 trace_dwc3_gadget_generic_cmd(cmd, param, status);
259
260 return ret;
261}
262
263static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
264
265/**
266 * dwc3_send_gadget_ep_cmd - issue an endpoint command
267 * @dep: the endpoint to which the command is going to be issued
268 * @cmd: the command to be issued
269 * @params: parameters to the command
270 *
271 * Caller should handle locking. This function will issue @cmd with given
272 * @params to @dep and wait for its completion.
273 */
274int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
275 struct dwc3_gadget_ep_cmd_params *params)
276{
277 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
278 struct dwc3 *dwc = dep->dwc;
279 u32 timeout = 5000;
280 u32 saved_config = 0;
281 u32 reg;
282
283 int cmd_status = 0;
284 int ret = -EINVAL;
285
286 /*
287 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
288 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
289 * endpoint command.
290 *
291 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
292 * settings. Restore them after the command is completed.
293 *
294 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
295 */
296 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
297 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
298 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
299 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
300 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
301 }
302
303 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
304 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
305 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
306 }
307
308 if (saved_config)
309 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
310 }
311
312 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
313 int needs_wakeup;
314
315 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
316 dwc->link_state == DWC3_LINK_STATE_U2 ||
317 dwc->link_state == DWC3_LINK_STATE_U3);
318
319 if (unlikely(needs_wakeup)) {
320 ret = __dwc3_gadget_wakeup(dwc);
321 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
322 ret);
323 }
324 }
325
326 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
327 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
328 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
329
330 /*
331 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
332 * not relying on XferNotReady, we can make use of a special "No
333 * Response Update Transfer" command where we should clear both CmdAct
334 * and CmdIOC bits.
335 *
336 * With this, we don't need to wait for command completion and can
337 * straight away issue further commands to the endpoint.
338 *
339 * NOTICE: We're making an assumption that control endpoints will never
340 * make use of Update Transfer command. This is a safe assumption
341 * because we can never have more than one request at a time with
342 * Control Endpoints. If anybody changes that assumption, this chunk
343 * needs to be updated accordingly.
344 */
345 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
346 !usb_endpoint_xfer_isoc(desc))
347 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
348 else
349 cmd |= DWC3_DEPCMD_CMDACT;
350
351 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
352 do {
353 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
354 if (!(reg & DWC3_DEPCMD_CMDACT)) {
355 cmd_status = DWC3_DEPCMD_STATUS(reg);
356
357 switch (cmd_status) {
358 case 0:
359 ret = 0;
360 break;
361 case DEPEVT_TRANSFER_NO_RESOURCE:
362 ret = -EINVAL;
363 break;
364 case DEPEVT_TRANSFER_BUS_EXPIRY:
365 /*
366 * SW issues START TRANSFER command to
367 * isochronous ep with future frame interval. If
368 * future interval time has already passed when
369 * core receives the command, it will respond
370 * with an error status of 'Bus Expiry'.
371 *
372 * Instead of always returning -EINVAL, let's
373 * give a hint to the gadget driver that this is
374 * the case by returning -EAGAIN.
375 */
376 ret = -EAGAIN;
377 break;
378 default:
379 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
380 }
381
382 break;
383 }
384 } while (--timeout);
385
386 if (timeout == 0) {
387 ret = -ETIMEDOUT;
388 cmd_status = -ETIMEDOUT;
389 }
390
391 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
392
393 if (ret == 0) {
394 switch (DWC3_DEPCMD_CMD(cmd)) {
395 case DWC3_DEPCMD_STARTTRANSFER:
396 dep->flags |= DWC3_EP_TRANSFER_STARTED;
397 break;
398 case DWC3_DEPCMD_ENDTRANSFER:
399 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
400 break;
401 default:
402 /* nothing */
403 break;
404 }
405 }
406
407 if (saved_config) {
408 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
409 reg |= saved_config;
410 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
411 }
412
413 return ret;
414}
415
416static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
417{
418 struct dwc3 *dwc = dep->dwc;
419 struct dwc3_gadget_ep_cmd_params params;
420 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
421
422 /*
423 * As of core revision 2.60a the recommended programming model
424 * is to set the ClearPendIN bit when issuing a Clear Stall EP
425 * command for IN endpoints. This is to prevent an issue where
426 * some (non-compliant) hosts may not send ACK TPs for pending
427 * IN transfers due to a mishandled error condition. Synopsys
428 * STAR 9000614252.
429 */
430 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
431 (dwc->gadget.speed >= USB_SPEED_SUPER))
432 cmd |= DWC3_DEPCMD_CLEARPENDIN;
433
434 memset(&params, 0, sizeof(params));
435
436 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
437}
438
439static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
440 struct dwc3_trb *trb)
441{
442 u32 offset = (char *) trb - (char *) dep->trb_pool;
443
444 return dep->trb_pool_dma + offset;
445}
446
447static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
448{
449 struct dwc3 *dwc = dep->dwc;
450
451 if (dep->trb_pool)
452 return 0;
453
454 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
455 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
456 &dep->trb_pool_dma, GFP_KERNEL);
457 if (!dep->trb_pool) {
458 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
459 dep->name);
460 return -ENOMEM;
461 }
462
463 return 0;
464}
465
466static void dwc3_free_trb_pool(struct dwc3_ep *dep)
467{
468 struct dwc3 *dwc = dep->dwc;
469
470 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
471 dep->trb_pool, dep->trb_pool_dma);
472
473 dep->trb_pool = NULL;
474 dep->trb_pool_dma = 0;
475}
476
477static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
478
479/**
480 * dwc3_gadget_start_config - configure ep resources
481 * @dwc: pointer to our controller context structure
482 * @dep: endpoint that is being enabled
483 *
484 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
485 * completion, it will set Transfer Resource for all available endpoints.
486 *
487 * The assignment of transfer resources cannot perfectly follow the data book
488 * due to the fact that the controller driver does not have all knowledge of the
489 * configuration in advance. It is given this information piecemeal by the
490 * composite gadget framework after every SET_CONFIGURATION and
491 * SET_INTERFACE. Trying to follow the databook programming model in this
492 * scenario can cause errors. For two reasons:
493 *
494 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
495 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
496 * incorrect in the scenario of multiple interfaces.
497 *
498 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
499 * endpoint on alt setting (8.1.6).
500 *
501 * The following simplified method is used instead:
502 *
503 * All hardware endpoints can be assigned a transfer resource and this setting
504 * will stay persistent until either a core reset or hibernation. So whenever we
505 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
506 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
507 * guaranteed that there are as many transfer resources as endpoints.
508 *
509 * This function is called for each endpoint when it is being enabled but is
510 * triggered only when called for EP0-out, which always happens first, and which
511 * should only happen in one of the above conditions.
512 */
513static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
514{
515 struct dwc3_gadget_ep_cmd_params params;
516 u32 cmd;
517 int i;
518 int ret;
519
520 if (dep->number)
521 return 0;
522
523 memset(&params, 0x00, sizeof(params));
524 cmd = DWC3_DEPCMD_DEPSTARTCFG;
525
526 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
527 if (ret)
528 return ret;
529
530 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
531 struct dwc3_ep *dep = dwc->eps[i];
532
533 if (!dep)
534 continue;
535
536 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
537 if (ret)
538 return ret;
539 }
540
541 return 0;
542}
543
544static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
545 bool modify, bool restore)
546{
547 const struct usb_ss_ep_comp_descriptor *comp_desc;
548 const struct usb_endpoint_descriptor *desc;
549 struct dwc3_gadget_ep_cmd_params params;
550
551 if (dev_WARN_ONCE(dwc->dev, modify && restore,
552 "Can't modify and restore\n"))
553 return -EINVAL;
554
555 comp_desc = dep->endpoint.comp_desc;
556 desc = dep->endpoint.desc;
557
558 memset(&params, 0x00, sizeof(params));
559
560 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
561 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
562
563 /* Burst size is only needed in SuperSpeed mode */
564 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
565 u32 burst = dep->endpoint.maxburst;
566 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
567 }
568
569 if (modify) {
570 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
571 } else if (restore) {
572 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
573 params.param2 |= dep->saved_state;
574 } else {
575 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
576 }
577
578 if (usb_endpoint_xfer_control(desc))
579 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
580
581 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
582 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
583
584 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
585 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
586 | DWC3_DEPCFG_STREAM_EVENT_EN;
587 dep->stream_capable = true;
588 }
589
590 if (!usb_endpoint_xfer_control(desc))
591 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
592
593 /*
594 * We are doing 1:1 mapping for endpoints, meaning
595 * Physical Endpoints 2 maps to Logical Endpoint 2 and
596 * so on. We consider the direction bit as part of the physical
597 * endpoint number. So USB endpoint 0x81 is 0x03.
598 */
599 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
600
601 /*
602 * We must use the lower 16 TX FIFOs even though
603 * HW might have more
604 */
605 if (dep->direction)
606 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
607
608 if (desc->bInterval) {
609 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
610 dep->interval = 1 << (desc->bInterval - 1);
611 }
612
613 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
614}
615
616static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
617{
618 struct dwc3_gadget_ep_cmd_params params;
619
620 memset(&params, 0x00, sizeof(params));
621
622 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
623
624 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
625 &params);
626}
627
628/**
629 * __dwc3_gadget_ep_enable - initializes a hw endpoint
630 * @dep: endpoint to be initialized
631 * @modify: if true, modify existing endpoint configuration
632 * @restore: if true, restore endpoint configuration from scratch buffer
633 *
634 * Caller should take care of locking. Execute all necessary commands to
635 * initialize a HW endpoint so it can be used by a gadget driver.
636 */
637static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
638 bool modify, bool restore)
639{
640 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
641 struct dwc3 *dwc = dep->dwc;
642
643 u32 reg;
644 int ret;
645
646 if (!(dep->flags & DWC3_EP_ENABLED)) {
647 ret = dwc3_gadget_start_config(dwc, dep);
648 if (ret)
649 return ret;
650 }
651
652 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
653 if (ret)
654 return ret;
655
656 if (!(dep->flags & DWC3_EP_ENABLED)) {
657 struct dwc3_trb *trb_st_hw;
658 struct dwc3_trb *trb_link;
659
660 dep->type = usb_endpoint_type(desc);
661 dep->flags |= DWC3_EP_ENABLED;
662 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
663
664 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
665 reg |= DWC3_DALEPENA_EP(dep->number);
666 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
667
668 init_waitqueue_head(&dep->wait_end_transfer);
669
670 if (usb_endpoint_xfer_control(desc))
671 goto out;
672
673 /* Initialize the TRB ring */
674 dep->trb_dequeue = 0;
675 dep->trb_enqueue = 0;
676 memset(dep->trb_pool, 0,
677 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
678
679 /* Link TRB. The HWO bit is never reset */
680 trb_st_hw = &dep->trb_pool[0];
681
682 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
683 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
684 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
685 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
686 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
687 }
688
689 /*
690 * Issue StartTransfer here with no-op TRB so we can always rely on No
691 * Response Update Transfer command.
692 */
693 if (usb_endpoint_xfer_bulk(desc)) {
694 struct dwc3_gadget_ep_cmd_params params;
695 struct dwc3_trb *trb;
696 dma_addr_t trb_dma;
697 u32 cmd;
698
699 memset(&params, 0, sizeof(params));
700 trb = &dep->trb_pool[0];
701 trb_dma = dwc3_trb_dma_offset(dep, trb);
702
703 params.param0 = upper_32_bits(trb_dma);
704 params.param1 = lower_32_bits(trb_dma);
705
706 cmd = DWC3_DEPCMD_STARTTRANSFER;
707
708 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
709 if (ret < 0)
710 return ret;
711
712 dep->flags |= DWC3_EP_BUSY;
713
714 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
715 WARN_ON_ONCE(!dep->resource_index);
716 }
717
718
719out:
720 trace_dwc3_gadget_ep_enable(dep);
721
722 return 0;
723}
724
725static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
726static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
727{
728 struct dwc3_request *req;
729
730 dwc3_stop_active_transfer(dwc, dep->number, true);
731
732 /* - giveback all requests to gadget driver */
733 while (!list_empty(&dep->started_list)) {
734 req = next_request(&dep->started_list);
735
736 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
737 }
738
739 while (!list_empty(&dep->pending_list)) {
740 req = next_request(&dep->pending_list);
741
742 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
743 }
744}
745
746/**
747 * __dwc3_gadget_ep_disable - disables a hw endpoint
748 * @dep: the endpoint to disable
749 *
750 * This function undoes what __dwc3_gadget_ep_enable did and also removes
751 * requests which are currently being processed by the hardware and those which
752 * are not yet scheduled.
753 *
754 * Caller should take care of locking.
755 */
756static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
757{
758 struct dwc3 *dwc = dep->dwc;
759 u32 reg;
760
761 trace_dwc3_gadget_ep_disable(dep);
762
763 dwc3_remove_requests(dwc, dep);
764
765 /* make sure HW endpoint isn't stalled */
766 if (dep->flags & DWC3_EP_STALL)
767 __dwc3_gadget_ep_set_halt(dep, 0, false);
768
769 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
770 reg &= ~DWC3_DALEPENA_EP(dep->number);
771 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
772
773 dep->stream_capable = false;
774 dep->type = 0;
775 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
776
777 /* Clear out the ep descriptors for non-ep0 */
778 if (dep->number > 1) {
779 dep->endpoint.comp_desc = NULL;
780 dep->endpoint.desc = NULL;
781 }
782
783 return 0;
784}
785
786/* -------------------------------------------------------------------------- */
787
788static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
789 const struct usb_endpoint_descriptor *desc)
790{
791 return -EINVAL;
792}
793
794static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
795{
796 return -EINVAL;
797}
798
799/* -------------------------------------------------------------------------- */
800
801static int dwc3_gadget_ep_enable(struct usb_ep *ep,
802 const struct usb_endpoint_descriptor *desc)
803{
804 struct dwc3_ep *dep;
805 struct dwc3 *dwc;
806 unsigned long flags;
807 int ret;
808
809 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
810 pr_debug("dwc3: invalid parameters\n");
811 return -EINVAL;
812 }
813
814 if (!desc->wMaxPacketSize) {
815 pr_debug("dwc3: missing wMaxPacketSize\n");
816 return -EINVAL;
817 }
818
819 dep = to_dwc3_ep(ep);
820 dwc = dep->dwc;
821
822 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
823 "%s is already enabled\n",
824 dep->name))
825 return 0;
826
827 spin_lock_irqsave(&dwc->lock, flags);
828 ret = __dwc3_gadget_ep_enable(dep, false, false);
829 spin_unlock_irqrestore(&dwc->lock, flags);
830
831 return ret;
832}
833
834static int dwc3_gadget_ep_disable(struct usb_ep *ep)
835{
836 struct dwc3_ep *dep;
837 struct dwc3 *dwc;
838 unsigned long flags;
839 int ret;
840
841 if (!ep) {
842 pr_debug("dwc3: invalid parameters\n");
843 return -EINVAL;
844 }
845
846 dep = to_dwc3_ep(ep);
847 dwc = dep->dwc;
848
849 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
850 "%s is already disabled\n",
851 dep->name))
852 return 0;
853
854 spin_lock_irqsave(&dwc->lock, flags);
855 ret = __dwc3_gadget_ep_disable(dep);
856 spin_unlock_irqrestore(&dwc->lock, flags);
857
858 return ret;
859}
860
861static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
862 gfp_t gfp_flags)
863{
864 struct dwc3_request *req;
865 struct dwc3_ep *dep = to_dwc3_ep(ep);
866
867 req = kzalloc(sizeof(*req), gfp_flags);
868 if (!req)
869 return NULL;
870
871 req->epnum = dep->number;
872 req->dep = dep;
873
874 dep->allocated_requests++;
875
876 trace_dwc3_alloc_request(req);
877
878 return &req->request;
879}
880
881static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
882 struct usb_request *request)
883{
884 struct dwc3_request *req = to_dwc3_request(request);
885 struct dwc3_ep *dep = to_dwc3_ep(ep);
886
887 dep->allocated_requests--;
888 trace_dwc3_free_request(req);
889 kfree(req);
890}
891
892static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
893
894static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
895 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
896 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
897{
898 struct dwc3 *dwc = dep->dwc;
899 struct usb_gadget *gadget = &dwc->gadget;
900 enum usb_device_speed speed = gadget->speed;
901
902 trb->size = DWC3_TRB_SIZE_LENGTH(length);
903 trb->bpl = lower_32_bits(dma);
904 trb->bph = upper_32_bits(dma);
905
906 switch (usb_endpoint_type(dep->endpoint.desc)) {
907 case USB_ENDPOINT_XFER_CONTROL:
908 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
909 break;
910
911 case USB_ENDPOINT_XFER_ISOC:
912 if (!node) {
913 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
914
915 /*
916 * USB Specification 2.0 Section 5.9.2 states that: "If
917 * there is only a single transaction in the microframe,
918 * only a DATA0 data packet PID is used. If there are
919 * two transactions per microframe, DATA1 is used for
920 * the first transaction data packet and DATA0 is used
921 * for the second transaction data packet. If there are
922 * three transactions per microframe, DATA2 is used for
923 * the first transaction data packet, DATA1 is used for
924 * the second, and DATA0 is used for the third."
925 *
926 * IOW, we should satisfy the following cases:
927 *
928 * 1) length <= maxpacket
929 * - DATA0
930 *
931 * 2) maxpacket < length <= (2 * maxpacket)
932 * - DATA1, DATA0
933 *
934 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
935 * - DATA2, DATA1, DATA0
936 */
937 if (speed == USB_SPEED_HIGH) {
938 struct usb_ep *ep = &dep->endpoint;
939 unsigned int mult = ep->mult - 1;
940 unsigned int maxp = usb_endpoint_maxp(ep->desc);
941
942 if (length <= (2 * maxp))
943 mult--;
944
945 if (length <= maxp)
946 mult--;
947
948 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
949 }
950 } else {
951 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
952 }
953
954 /* always enable Interrupt on Missed ISOC */
955 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
956 break;
957
958 case USB_ENDPOINT_XFER_BULK:
959 case USB_ENDPOINT_XFER_INT:
960 trb->ctrl = DWC3_TRBCTL_NORMAL;
961 break;
962 default:
963 /*
964 * This is only possible with faulty memory because we
965 * checked it already :)
966 */
967 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
968 usb_endpoint_type(dep->endpoint.desc));
969 }
970
971 /*
972 * Enable Continue on Short Packet
973 * when endpoint is not a stream capable
974 */
975 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
976 if (!dep->stream_capable)
977 trb->ctrl |= DWC3_TRB_CTRL_CSP;
978
979 if (short_not_ok)
980 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
981 }
982
983 if ((!no_interrupt && !chain) ||
984 (dwc3_calc_trbs_left(dep) == 1))
985 trb->ctrl |= DWC3_TRB_CTRL_IOC;
986
987 if (chain)
988 trb->ctrl |= DWC3_TRB_CTRL_CHN;
989
990 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
991 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
992
993 trb->ctrl |= DWC3_TRB_CTRL_HWO;
994
995 dwc3_ep_inc_enq(dep);
996
997 trace_dwc3_prepare_trb(dep, trb);
998}
999
1000/**
1001 * dwc3_prepare_one_trb - setup one TRB from one request
1002 * @dep: endpoint for which this request is prepared
1003 * @req: dwc3_request pointer
1004 * @chain: should this TRB be chained to the next?
1005 * @node: only for isochronous endpoints. First TRB needs different type.
1006 */
1007static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1008 struct dwc3_request *req, unsigned chain, unsigned node)
1009{
1010 struct dwc3_trb *trb;
1011 unsigned length = req->request.length;
1012 unsigned stream_id = req->request.stream_id;
1013 unsigned short_not_ok = req->request.short_not_ok;
1014 unsigned no_interrupt = req->request.no_interrupt;
1015 dma_addr_t dma = req->request.dma;
1016
1017 trb = &dep->trb_pool[dep->trb_enqueue];
1018
1019 if (!req->trb) {
1020 dwc3_gadget_move_started_request(req);
1021 req->trb = trb;
1022 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1023 dep->queued_requests++;
1024 }
1025
1026 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1027 stream_id, short_not_ok, no_interrupt);
1028}
1029
1030/**
1031 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1032 * @dep: The endpoint with the TRB ring
1033 * @index: The index of the current TRB in the ring
1034 *
1035 * Returns the TRB prior to the one pointed to by the index. If the
1036 * index is 0, we will wrap backwards, skip the link TRB, and return
1037 * the one just before that.
1038 */
1039static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1040{
1041 u8 tmp = index;
1042
1043 if (!tmp)
1044 tmp = DWC3_TRB_NUM - 1;
1045
1046 return &dep->trb_pool[tmp - 1];
1047}
1048
1049static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1050{
1051 struct dwc3_trb *tmp;
1052 u8 trbs_left;
1053
1054 /*
1055 * If enqueue & dequeue are equal than it is either full or empty.
1056 *
1057 * One way to know for sure is if the TRB right before us has HWO bit
1058 * set or not. If it has, then we're definitely full and can't fit any
1059 * more transfers in our ring.
1060 */
1061 if (dep->trb_enqueue == dep->trb_dequeue) {
1062 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1063 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
1064 return 0;
1065
1066 return DWC3_TRB_NUM - 1;
1067 }
1068
1069 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1070 trbs_left &= (DWC3_TRB_NUM - 1);
1071
1072 if (dep->trb_dequeue < dep->trb_enqueue)
1073 trbs_left--;
1074
1075 return trbs_left;
1076}
1077
1078static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1079 struct dwc3_request *req)
1080{
1081 struct scatterlist *sg = req->sg;
1082 struct scatterlist *s;
1083 int i;
1084
1085 for_each_sg(sg, s, req->num_pending_sgs, i) {
1086 unsigned int length = req->request.length;
1087 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1088 unsigned int rem = length % maxp;
1089 unsigned chain = true;
1090
1091 if (sg_is_last(s))
1092 chain = false;
1093
1094 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1095 struct dwc3 *dwc = dep->dwc;
1096 struct dwc3_trb *trb;
1097
1098 req->unaligned = true;
1099
1100 /* prepare normal TRB */
1101 dwc3_prepare_one_trb(dep, req, true, i);
1102
1103 /* Now prepare one extra TRB to align transfer size */
1104 trb = &dep->trb_pool[dep->trb_enqueue];
1105 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1106 maxp - rem, false, 1,
1107 req->request.stream_id,
1108 req->request.short_not_ok,
1109 req->request.no_interrupt);
1110 } else {
1111 dwc3_prepare_one_trb(dep, req, chain, i);
1112 }
1113
1114 if (!dwc3_calc_trbs_left(dep))
1115 break;
1116 }
1117}
1118
1119static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1120 struct dwc3_request *req)
1121{
1122 unsigned int length = req->request.length;
1123 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1124 unsigned int rem = length % maxp;
1125
1126 if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) {
1127 struct dwc3 *dwc = dep->dwc;
1128 struct dwc3_trb *trb;
1129
1130 req->unaligned = true;
1131
1132 /* prepare normal TRB */
1133 dwc3_prepare_one_trb(dep, req, true, 0);
1134
1135 /* Now prepare one extra TRB to align transfer size */
1136 trb = &dep->trb_pool[dep->trb_enqueue];
1137 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1138 false, 1, req->request.stream_id,
1139 req->request.short_not_ok,
1140 req->request.no_interrupt);
1141 } else if (req->request.zero && req->request.length &&
1142 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1143 struct dwc3 *dwc = dep->dwc;
1144 struct dwc3_trb *trb;
1145
1146 req->zero = true;
1147
1148 /* prepare normal TRB */
1149 dwc3_prepare_one_trb(dep, req, true, 0);
1150
1151 /* Now prepare one extra TRB to handle ZLP */
1152 trb = &dep->trb_pool[dep->trb_enqueue];
1153 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1154 false, 1, req->request.stream_id,
1155 req->request.short_not_ok,
1156 req->request.no_interrupt);
1157 } else {
1158 dwc3_prepare_one_trb(dep, req, false, 0);
1159 }
1160}
1161
1162/*
1163 * dwc3_prepare_trbs - setup TRBs from requests
1164 * @dep: endpoint for which requests are being prepared
1165 *
1166 * The function goes through the requests list and sets up TRBs for the
1167 * transfers. The function returns once there are no more TRBs available or
1168 * it runs out of requests.
1169 */
1170static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1171{
1172 struct dwc3_request *req, *n;
1173
1174 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1175
1176 if (!dwc3_calc_trbs_left(dep))
1177 return;
1178
1179 /*
1180 * We can get in a situation where there's a request in the started list
1181 * but there weren't enough TRBs to fully kick it in the first time
1182 * around, so it has been waiting for more TRBs to be freed up.
1183 *
1184 * In that case, we should check if we have a request with pending_sgs
1185 * in the started list and prepare TRBs for that request first,
1186 * otherwise we will prepare TRBs completely out of order and that will
1187 * break things.
1188 */
1189 list_for_each_entry(req, &dep->started_list, list) {
1190 if (req->num_pending_sgs > 0)
1191 dwc3_prepare_one_trb_sg(dep, req);
1192
1193 if (!dwc3_calc_trbs_left(dep))
1194 return;
1195 }
1196
1197 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1198 struct dwc3 *dwc = dep->dwc;
1199 int ret;
1200
1201 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1202 dep->direction);
1203 if (ret)
1204 return;
1205
1206 req->sg = req->request.sg;
1207 req->num_pending_sgs = req->request.num_mapped_sgs;
1208
1209 if (req->num_pending_sgs > 0)
1210 dwc3_prepare_one_trb_sg(dep, req);
1211 else
1212 dwc3_prepare_one_trb_linear(dep, req);
1213
1214 if (!dwc3_calc_trbs_left(dep))
1215 return;
1216 }
1217}
1218
1219static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1220{
1221 struct dwc3_gadget_ep_cmd_params params;
1222 struct dwc3_request *req;
1223 int starting;
1224 int ret;
1225 u32 cmd;
1226
1227 starting = !(dep->flags & DWC3_EP_BUSY);
1228
1229 dwc3_prepare_trbs(dep);
1230 req = next_request(&dep->started_list);
1231 if (!req) {
1232 dep->flags |= DWC3_EP_PENDING_REQUEST;
1233 return 0;
1234 }
1235
1236 memset(&params, 0, sizeof(params));
1237
1238 if (starting) {
1239 params.param0 = upper_32_bits(req->trb_dma);
1240 params.param1 = lower_32_bits(req->trb_dma);
1241 cmd = DWC3_DEPCMD_STARTTRANSFER |
1242 DWC3_DEPCMD_PARAM(cmd_param);
1243 } else {
1244 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1245 DWC3_DEPCMD_PARAM(dep->resource_index);
1246 }
1247
1248 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1249 if (ret < 0) {
1250 /*
1251 * FIXME we need to iterate over the list of requests
1252 * here and stop, unmap, free and del each of the linked
1253 * requests instead of what we do now.
1254 */
1255 if (req->trb)
1256 memset(req->trb, 0, sizeof(struct dwc3_trb));
1257 dep->queued_requests--;
1258 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1259 return ret;
1260 }
1261
1262 dep->flags |= DWC3_EP_BUSY;
1263
1264 if (starting) {
1265 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1266 WARN_ON_ONCE(!dep->resource_index);
1267 }
1268
1269 return 0;
1270}
1271
1272static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1273{
1274 u32 reg;
1275
1276 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1277 return DWC3_DSTS_SOFFN(reg);
1278}
1279
1280static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1281 struct dwc3_ep *dep, u32 cur_uf)
1282{
1283 u32 uf;
1284
1285 if (list_empty(&dep->pending_list)) {
1286 dev_info(dwc->dev, "%s: ran out of requests\n",
1287 dep->name);
1288 dep->flags |= DWC3_EP_PENDING_REQUEST;
1289 return;
1290 }
1291
1292 /*
1293 * Schedule the first trb for one interval in the future or at
1294 * least 4 microframes.
1295 */
1296 uf = cur_uf + max_t(u32, 4, dep->interval);
1297
1298 __dwc3_gadget_kick_transfer(dep, uf);
1299}
1300
1301static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1302 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1303{
1304 u32 cur_uf, mask;
1305
1306 mask = ~(dep->interval - 1);
1307 cur_uf = event->parameters & mask;
1308
1309 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1310}
1311
1312static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1313{
1314 struct dwc3 *dwc = dep->dwc;
1315 int ret = 0;
1316
1317 if (!dep->endpoint.desc) {
1318 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1319 dep->name);
1320 return -ESHUTDOWN;
1321 }
1322
1323 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1324 &req->request, req->dep->name))
1325 return -EINVAL;
1326
1327 pm_runtime_get(dwc->dev);
1328
1329 req->request.actual = 0;
1330 req->request.status = -EINPROGRESS;
1331 req->direction = dep->direction;
1332 req->epnum = dep->number;
1333
1334 trace_dwc3_ep_queue(req);
1335
1336 list_add_tail(&req->list, &dep->pending_list);
1337
1338 /*
1339 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1340 * wait for a XferNotReady event so we will know what's the current
1341 * (micro-)frame number.
1342 *
1343 * Without this trick, we are very, very likely gonna get Bus Expiry
1344 * errors which will force us issue EndTransfer command.
1345 */
1346 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1347 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1348 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1349 dwc3_stop_active_transfer(dwc, dep->number, true);
1350 dep->flags = DWC3_EP_ENABLED;
1351 } else {
1352 u32 cur_uf;
1353
1354 cur_uf = __dwc3_gadget_get_frame(dwc);
1355 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1356 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1357 }
1358 return 0;
1359 }
1360
1361 if ((dep->flags & DWC3_EP_BUSY) &&
1362 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1363 WARN_ON_ONCE(!dep->resource_index);
1364 ret = __dwc3_gadget_kick_transfer(dep,
1365 dep->resource_index);
1366 }
1367
1368 goto out;
1369 }
1370
1371 if (!dwc3_calc_trbs_left(dep))
1372 return 0;
1373
1374 ret = __dwc3_gadget_kick_transfer(dep, 0);
1375out:
1376 if (ret == -EBUSY)
1377 ret = 0;
1378
1379 return ret;
1380}
1381
1382static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1383 gfp_t gfp_flags)
1384{
1385 struct dwc3_request *req = to_dwc3_request(request);
1386 struct dwc3_ep *dep = to_dwc3_ep(ep);
1387 struct dwc3 *dwc = dep->dwc;
1388
1389 unsigned long flags;
1390
1391 int ret;
1392
1393 spin_lock_irqsave(&dwc->lock, flags);
1394 ret = __dwc3_gadget_ep_queue(dep, req);
1395 spin_unlock_irqrestore(&dwc->lock, flags);
1396
1397 return ret;
1398}
1399
1400static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1401 struct usb_request *request)
1402{
1403 struct dwc3_request *req = to_dwc3_request(request);
1404 struct dwc3_request *r = NULL;
1405
1406 struct dwc3_ep *dep = to_dwc3_ep(ep);
1407 struct dwc3 *dwc = dep->dwc;
1408
1409 unsigned long flags;
1410 int ret = 0;
1411
1412 trace_dwc3_ep_dequeue(req);
1413
1414 spin_lock_irqsave(&dwc->lock, flags);
1415
1416 list_for_each_entry(r, &dep->pending_list, list) {
1417 if (r == req)
1418 break;
1419 }
1420
1421 if (r != req) {
1422 list_for_each_entry(r, &dep->started_list, list) {
1423 if (r == req)
1424 break;
1425 }
1426 if (r == req) {
1427 /* wait until it is processed */
1428 dwc3_stop_active_transfer(dwc, dep->number, true);
1429
1430 /*
1431 * If request was already started, this means we had to
1432 * stop the transfer. With that we also need to ignore
1433 * all TRBs used by the request, however TRBs can only
1434 * be modified after completion of END_TRANSFER
1435 * command. So what we do here is that we wait for
1436 * END_TRANSFER completion and only after that, we jump
1437 * over TRBs by clearing HWO and incrementing dequeue
1438 * pointer.
1439 *
1440 * Note that we have 2 possible types of transfers here:
1441 *
1442 * i) Linear buffer request
1443 * ii) SG-list based request
1444 *
1445 * SG-list based requests will have r->num_pending_sgs
1446 * set to a valid number (> 0). Linear requests,
1447 * normally use a single TRB.
1448 *
1449 * For each of these two cases, if r->unaligned flag is
1450 * set, one extra TRB has been used to align transfer
1451 * size to wMaxPacketSize.
1452 *
1453 * All of these cases need to be taken into
1454 * consideration so we don't mess up our TRB ring
1455 * pointers.
1456 */
1457 wait_event_lock_irq(dep->wait_end_transfer,
1458 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1459 dwc->lock);
1460
1461 if (!r->trb)
1462 goto out0;
1463
1464 if (r->num_pending_sgs) {
1465 struct dwc3_trb *trb;
1466 int i = 0;
1467
1468 for (i = 0; i < r->num_pending_sgs; i++) {
1469 trb = r->trb + i;
1470 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1471 dwc3_ep_inc_deq(dep);
1472 }
1473
1474 if (r->unaligned || r->zero) {
1475 trb = r->trb + r->num_pending_sgs + 1;
1476 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1477 dwc3_ep_inc_deq(dep);
1478 }
1479 } else {
1480 struct dwc3_trb *trb = r->trb;
1481
1482 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1483 dwc3_ep_inc_deq(dep);
1484
1485 if (r->unaligned || r->zero) {
1486 trb = r->trb + 1;
1487 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1488 dwc3_ep_inc_deq(dep);
1489 }
1490 }
1491 goto out1;
1492 }
1493 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1494 request, ep->name);
1495 ret = -EINVAL;
1496 goto out0;
1497 }
1498
1499out1:
1500 /* giveback the request */
1501 dep->queued_requests--;
1502 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1503
1504out0:
1505 spin_unlock_irqrestore(&dwc->lock, flags);
1506
1507 return ret;
1508}
1509
1510int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1511{
1512 struct dwc3_gadget_ep_cmd_params params;
1513 struct dwc3 *dwc = dep->dwc;
1514 int ret;
1515
1516 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1517 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1518 return -EINVAL;
1519 }
1520
1521 memset(&params, 0x00, sizeof(params));
1522
1523 if (value) {
1524 struct dwc3_trb *trb;
1525
1526 unsigned transfer_in_flight;
1527 unsigned started;
1528
1529 if (dep->number > 1)
1530 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1531 else
1532 trb = &dwc->ep0_trb[dep->trb_enqueue];
1533
1534 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1535 started = !list_empty(&dep->started_list);
1536
1537 if (!protocol && ((dep->direction && transfer_in_flight) ||
1538 (!dep->direction && started))) {
1539 return -EAGAIN;
1540 }
1541
1542 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1543 &params);
1544 if (ret)
1545 dev_err(dwc->dev, "failed to set STALL on %s\n",
1546 dep->name);
1547 else
1548 dep->flags |= DWC3_EP_STALL;
1549 } else {
1550
1551 ret = dwc3_send_clear_stall_ep_cmd(dep);
1552 if (ret)
1553 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1554 dep->name);
1555 else
1556 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1557 }
1558
1559 return ret;
1560}
1561
1562static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1563{
1564 struct dwc3_ep *dep = to_dwc3_ep(ep);
1565 struct dwc3 *dwc = dep->dwc;
1566
1567 unsigned long flags;
1568
1569 int ret;
1570
1571 spin_lock_irqsave(&dwc->lock, flags);
1572 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1573 spin_unlock_irqrestore(&dwc->lock, flags);
1574
1575 return ret;
1576}
1577
1578static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1579{
1580 struct dwc3_ep *dep = to_dwc3_ep(ep);
1581 struct dwc3 *dwc = dep->dwc;
1582 unsigned long flags;
1583 int ret;
1584
1585 spin_lock_irqsave(&dwc->lock, flags);
1586 dep->flags |= DWC3_EP_WEDGE;
1587
1588 if (dep->number == 0 || dep->number == 1)
1589 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1590 else
1591 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1592 spin_unlock_irqrestore(&dwc->lock, flags);
1593
1594 return ret;
1595}
1596
1597/* -------------------------------------------------------------------------- */
1598
1599static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1600 .bLength = USB_DT_ENDPOINT_SIZE,
1601 .bDescriptorType = USB_DT_ENDPOINT,
1602 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1603};
1604
1605static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1606 .enable = dwc3_gadget_ep0_enable,
1607 .disable = dwc3_gadget_ep0_disable,
1608 .alloc_request = dwc3_gadget_ep_alloc_request,
1609 .free_request = dwc3_gadget_ep_free_request,
1610 .queue = dwc3_gadget_ep0_queue,
1611 .dequeue = dwc3_gadget_ep_dequeue,
1612 .set_halt = dwc3_gadget_ep0_set_halt,
1613 .set_wedge = dwc3_gadget_ep_set_wedge,
1614};
1615
1616static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1617 .enable = dwc3_gadget_ep_enable,
1618 .disable = dwc3_gadget_ep_disable,
1619 .alloc_request = dwc3_gadget_ep_alloc_request,
1620 .free_request = dwc3_gadget_ep_free_request,
1621 .queue = dwc3_gadget_ep_queue,
1622 .dequeue = dwc3_gadget_ep_dequeue,
1623 .set_halt = dwc3_gadget_ep_set_halt,
1624 .set_wedge = dwc3_gadget_ep_set_wedge,
1625};
1626
1627/* -------------------------------------------------------------------------- */
1628
1629static int dwc3_gadget_get_frame(struct usb_gadget *g)
1630{
1631 struct dwc3 *dwc = gadget_to_dwc(g);
1632
1633 return __dwc3_gadget_get_frame(dwc);
1634}
1635
1636static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1637{
1638 int retries;
1639
1640 int ret;
1641 u32 reg;
1642
1643 u8 link_state;
1644
1645 /*
1646 * According to the Databook Remote wakeup request should
1647 * be issued only when the device is in early suspend state.
1648 *
1649 * We can check that via USB Link State bits in DSTS register.
1650 */
1651 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1652
1653 link_state = DWC3_DSTS_USBLNKST(reg);
1654
1655 switch (link_state) {
1656 case DWC3_LINK_STATE_RESET:
1657 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1658 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1659 case DWC3_LINK_STATE_RESUME:
1660 break;
1661 default:
1662 return -EINVAL;
1663 }
1664
1665 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1666 if (ret < 0) {
1667 dev_err(dwc->dev, "failed to put link in Recovery\n");
1668 return ret;
1669 }
1670
1671 /* Recent versions do this automatically */
1672 if (dwc->revision < DWC3_REVISION_194A) {
1673 /* write zeroes to Link Change Request */
1674 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1675 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1676 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1677 }
1678
1679 /* poll until Link State changes to ON */
1680 retries = 20000;
1681
1682 while (retries--) {
1683 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1684
1685 /* in HS, means ON */
1686 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1687 break;
1688 }
1689
1690 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1691 dev_err(dwc->dev, "failed to send remote wakeup\n");
1692 return -EINVAL;
1693 }
1694
1695 return 0;
1696}
1697
1698static int dwc3_gadget_wakeup(struct usb_gadget *g)
1699{
1700 struct dwc3 *dwc = gadget_to_dwc(g);
1701 unsigned long flags;
1702 int ret;
1703
1704 spin_lock_irqsave(&dwc->lock, flags);
1705 ret = __dwc3_gadget_wakeup(dwc);
1706 spin_unlock_irqrestore(&dwc->lock, flags);
1707
1708 return ret;
1709}
1710
1711static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1712 int is_selfpowered)
1713{
1714 struct dwc3 *dwc = gadget_to_dwc(g);
1715 unsigned long flags;
1716
1717 spin_lock_irqsave(&dwc->lock, flags);
1718 g->is_selfpowered = !!is_selfpowered;
1719 spin_unlock_irqrestore(&dwc->lock, flags);
1720
1721 return 0;
1722}
1723
1724static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1725{
1726 u32 reg;
1727 u32 timeout = 500;
1728
1729 if (pm_runtime_suspended(dwc->dev))
1730 return 0;
1731
1732 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1733 if (is_on) {
1734 if (dwc->revision <= DWC3_REVISION_187A) {
1735 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1736 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1737 }
1738
1739 if (dwc->revision >= DWC3_REVISION_194A)
1740 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1741 reg |= DWC3_DCTL_RUN_STOP;
1742
1743 if (dwc->has_hibernation)
1744 reg |= DWC3_DCTL_KEEP_CONNECT;
1745
1746 dwc->pullups_connected = true;
1747 } else {
1748 reg &= ~DWC3_DCTL_RUN_STOP;
1749
1750 if (dwc->has_hibernation && !suspend)
1751 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1752
1753 dwc->pullups_connected = false;
1754 }
1755
1756 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1757
1758 do {
1759 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1760 reg &= DWC3_DSTS_DEVCTRLHLT;
1761 } while (--timeout && !(!is_on ^ !reg));
1762
1763 if (!timeout)
1764 return -ETIMEDOUT;
1765
1766 return 0;
1767}
1768
1769static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1770{
1771 struct dwc3 *dwc = gadget_to_dwc(g);
1772 unsigned long flags;
1773 int ret;
1774
1775 is_on = !!is_on;
1776
1777 /*
1778 * Per databook, when we want to stop the gadget, if a control transfer
1779 * is still in process, complete it and get the core into setup phase.
1780 */
1781 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1782 reinit_completion(&dwc->ep0_in_setup);
1783
1784 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1785 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1786 if (ret == 0) {
1787 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1788 return -ETIMEDOUT;
1789 }
1790 }
1791
1792 spin_lock_irqsave(&dwc->lock, flags);
1793 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1794 spin_unlock_irqrestore(&dwc->lock, flags);
1795
1796 return ret;
1797}
1798
1799static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1800{
1801 u32 reg;
1802
1803 /* Enable all but Start and End of Frame IRQs */
1804 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1805 DWC3_DEVTEN_EVNTOVERFLOWEN |
1806 DWC3_DEVTEN_CMDCMPLTEN |
1807 DWC3_DEVTEN_ERRTICERREN |
1808 DWC3_DEVTEN_WKUPEVTEN |
1809 DWC3_DEVTEN_CONNECTDONEEN |
1810 DWC3_DEVTEN_USBRSTEN |
1811 DWC3_DEVTEN_DISCONNEVTEN);
1812
1813 if (dwc->revision < DWC3_REVISION_250A)
1814 reg |= DWC3_DEVTEN_ULSTCNGEN;
1815
1816 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1817}
1818
1819static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1820{
1821 /* mask all interrupts */
1822 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1823}
1824
1825static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1826static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1827
1828/**
1829 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1830 * @dwc: pointer to our context structure
1831 *
1832 * The following looks like complex but it's actually very simple. In order to
1833 * calculate the number of packets we can burst at once on OUT transfers, we're
1834 * gonna use RxFIFO size.
1835 *
1836 * To calculate RxFIFO size we need two numbers:
1837 * MDWIDTH = size, in bits, of the internal memory bus
1838 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1839 *
1840 * Given these two numbers, the formula is simple:
1841 *
1842 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1843 *
1844 * 24 bytes is for 3x SETUP packets
1845 * 16 bytes is a clock domain crossing tolerance
1846 *
1847 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1848 */
1849static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1850{
1851 u32 ram2_depth;
1852 u32 mdwidth;
1853 u32 nump;
1854 u32 reg;
1855
1856 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1857 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1858
1859 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1860 nump = min_t(u32, nump, 16);
1861
1862 /* update NumP */
1863 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1864 reg &= ~DWC3_DCFG_NUMP_MASK;
1865 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1866 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1867}
1868
1869static int __dwc3_gadget_start(struct dwc3 *dwc)
1870{
1871 struct dwc3_ep *dep;
1872 int ret = 0;
1873 u32 reg;
1874
1875 /*
1876 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1877 * the core supports IMOD, disable it.
1878 */
1879 if (dwc->imod_interval) {
1880 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1881 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1882 } else if (dwc3_has_imod(dwc)) {
1883 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1884 }
1885
1886 /*
1887 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1888 * field instead of letting dwc3 itself calculate that automatically.
1889 *
1890 * This way, we maximize the chances that we'll be able to get several
1891 * bursts of data without going through any sort of endpoint throttling.
1892 */
1893 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1894 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1895 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1896
1897 dwc3_gadget_setup_nump(dwc);
1898
1899 /* Start with SuperSpeed Default */
1900 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1901
1902 dep = dwc->eps[0];
1903 ret = __dwc3_gadget_ep_enable(dep, false, false);
1904 if (ret) {
1905 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1906 goto err0;
1907 }
1908
1909 dep = dwc->eps[1];
1910 ret = __dwc3_gadget_ep_enable(dep, false, false);
1911 if (ret) {
1912 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1913 goto err1;
1914 }
1915
1916 /* begin to receive SETUP packets */
1917 dwc->ep0state = EP0_SETUP_PHASE;
1918 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1919 dwc3_ep0_out_start(dwc);
1920
1921 dwc3_gadget_enable_irq(dwc);
1922
1923 return 0;
1924
1925err1:
1926 __dwc3_gadget_ep_disable(dwc->eps[0]);
1927
1928err0:
1929 return ret;
1930}
1931
1932static int dwc3_gadget_start(struct usb_gadget *g,
1933 struct usb_gadget_driver *driver)
1934{
1935 struct dwc3 *dwc = gadget_to_dwc(g);
1936 unsigned long flags;
1937 int ret = 0;
1938 int irq;
1939
1940 irq = dwc->irq_gadget;
1941 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1942 IRQF_SHARED, "dwc3", dwc->ev_buf);
1943 if (ret) {
1944 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1945 irq, ret);
1946 goto err0;
1947 }
1948
1949 spin_lock_irqsave(&dwc->lock, flags);
1950 if (dwc->gadget_driver) {
1951 dev_err(dwc->dev, "%s is already bound to %s\n",
1952 dwc->gadget.name,
1953 dwc->gadget_driver->driver.name);
1954 ret = -EBUSY;
1955 goto err1;
1956 }
1957
1958 dwc->gadget_driver = driver;
1959
1960 if (pm_runtime_active(dwc->dev))
1961 __dwc3_gadget_start(dwc);
1962
1963 spin_unlock_irqrestore(&dwc->lock, flags);
1964
1965 return 0;
1966
1967err1:
1968 spin_unlock_irqrestore(&dwc->lock, flags);
1969 free_irq(irq, dwc);
1970
1971err0:
1972 return ret;
1973}
1974
1975static void __dwc3_gadget_stop(struct dwc3 *dwc)
1976{
1977 dwc3_gadget_disable_irq(dwc);
1978 __dwc3_gadget_ep_disable(dwc->eps[0]);
1979 __dwc3_gadget_ep_disable(dwc->eps[1]);
1980}
1981
1982static int dwc3_gadget_stop(struct usb_gadget *g)
1983{
1984 struct dwc3 *dwc = gadget_to_dwc(g);
1985 unsigned long flags;
1986 int epnum;
1987
1988 spin_lock_irqsave(&dwc->lock, flags);
1989
1990 if (pm_runtime_suspended(dwc->dev))
1991 goto out;
1992
1993 __dwc3_gadget_stop(dwc);
1994
1995 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1996 struct dwc3_ep *dep = dwc->eps[epnum];
1997
1998 if (!dep)
1999 continue;
2000
2001 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2002 continue;
2003
2004 wait_event_lock_irq(dep->wait_end_transfer,
2005 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
2006 dwc->lock);
2007 }
2008
2009out:
2010 dwc->gadget_driver = NULL;
2011 spin_unlock_irqrestore(&dwc->lock, flags);
2012
2013 free_irq(dwc->irq_gadget, dwc->ev_buf);
2014
2015 return 0;
2016}
2017
2018static void dwc3_gadget_set_speed(struct usb_gadget *g,
2019 enum usb_device_speed speed)
2020{
2021 struct dwc3 *dwc = gadget_to_dwc(g);
2022 unsigned long flags;
2023 u32 reg;
2024
2025 spin_lock_irqsave(&dwc->lock, flags);
2026 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2027 reg &= ~(DWC3_DCFG_SPEED_MASK);
2028
2029 /*
2030 * WORKAROUND: DWC3 revision < 2.20a have an issue
2031 * which would cause metastability state on Run/Stop
2032 * bit if we try to force the IP to USB2-only mode.
2033 *
2034 * Because of that, we cannot configure the IP to any
2035 * speed other than the SuperSpeed
2036 *
2037 * Refers to:
2038 *
2039 * STAR#9000525659: Clock Domain Crossing on DCTL in
2040 * USB 2.0 Mode
2041 */
2042 if (dwc->revision < DWC3_REVISION_220A &&
2043 !dwc->dis_metastability_quirk) {
2044 reg |= DWC3_DCFG_SUPERSPEED;
2045 } else {
2046 switch (speed) {
2047 case USB_SPEED_LOW:
2048 reg |= DWC3_DCFG_LOWSPEED;
2049 break;
2050 case USB_SPEED_FULL:
2051 reg |= DWC3_DCFG_FULLSPEED;
2052 break;
2053 case USB_SPEED_HIGH:
2054 reg |= DWC3_DCFG_HIGHSPEED;
2055 break;
2056 case USB_SPEED_SUPER:
2057 reg |= DWC3_DCFG_SUPERSPEED;
2058 break;
2059 case USB_SPEED_SUPER_PLUS:
2060 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2061 break;
2062 default:
2063 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2064
2065 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2066 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2067 else
2068 reg |= DWC3_DCFG_SUPERSPEED;
2069 }
2070 }
2071 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2072
2073 spin_unlock_irqrestore(&dwc->lock, flags);
2074}
2075
2076static const struct usb_gadget_ops dwc3_gadget_ops = {
2077 .get_frame = dwc3_gadget_get_frame,
2078 .wakeup = dwc3_gadget_wakeup,
2079 .set_selfpowered = dwc3_gadget_set_selfpowered,
2080 .pullup = dwc3_gadget_pullup,
2081 .udc_start = dwc3_gadget_start,
2082 .udc_stop = dwc3_gadget_stop,
2083 .udc_set_speed = dwc3_gadget_set_speed,
2084};
2085
2086/* -------------------------------------------------------------------------- */
2087
2088static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2089{
2090 struct dwc3_ep *dep;
2091 u8 epnum;
2092
2093 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2094
2095 for (epnum = 0; epnum < total; epnum++) {
2096 bool direction = epnum & 1;
2097 u8 num = epnum >> 1;
2098
2099 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2100 if (!dep)
2101 return -ENOMEM;
2102
2103 dep->dwc = dwc;
2104 dep->number = epnum;
2105 dep->direction = direction;
2106 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2107 dwc->eps[epnum] = dep;
2108
2109 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2110 direction ? "in" : "out");
2111
2112 dep->endpoint.name = dep->name;
2113
2114 if (!(dep->number > 1)) {
2115 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2116 dep->endpoint.comp_desc = NULL;
2117 }
2118
2119 spin_lock_init(&dep->lock);
2120
2121 if (num == 0) {
2122 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2123 dep->endpoint.maxburst = 1;
2124 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2125 if (!direction)
2126 dwc->gadget.ep0 = &dep->endpoint;
2127 } else if (direction) {
2128 int mdwidth;
2129 int kbytes;
2130 int size;
2131 int ret;
2132
2133 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2134 /* MDWIDTH is represented in bits, we need it in bytes */
2135 mdwidth /= 8;
2136
2137 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num));
2138 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2139
2140 /* FIFO Depth is in MDWDITH bytes. Multiply */
2141 size *= mdwidth;
2142
2143 kbytes = size / 1024;
2144 if (kbytes == 0)
2145 kbytes = 1;
2146
2147 /*
2148 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2149 * internal overhead. We don't really know how these are used,
2150 * but documentation say it exists.
2151 */
2152 size -= mdwidth * (kbytes + 1);
2153 size /= kbytes;
2154
2155 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2156
2157 dep->endpoint.max_streams = 15;
2158 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2159 list_add_tail(&dep->endpoint.ep_list,
2160 &dwc->gadget.ep_list);
2161
2162 ret = dwc3_alloc_trb_pool(dep);
2163 if (ret)
2164 return ret;
2165 } else {
2166 int ret;
2167
2168 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2169 dep->endpoint.max_streams = 15;
2170 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2171 list_add_tail(&dep->endpoint.ep_list,
2172 &dwc->gadget.ep_list);
2173
2174 ret = dwc3_alloc_trb_pool(dep);
2175 if (ret)
2176 return ret;
2177 }
2178
2179 if (num == 0) {
2180 dep->endpoint.caps.type_control = true;
2181 } else {
2182 dep->endpoint.caps.type_iso = true;
2183 dep->endpoint.caps.type_bulk = true;
2184 dep->endpoint.caps.type_int = true;
2185 }
2186
2187 dep->endpoint.caps.dir_in = direction;
2188 dep->endpoint.caps.dir_out = !direction;
2189
2190 INIT_LIST_HEAD(&dep->pending_list);
2191 INIT_LIST_HEAD(&dep->started_list);
2192 }
2193
2194 return 0;
2195}
2196
2197static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2198{
2199 struct dwc3_ep *dep;
2200 u8 epnum;
2201
2202 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2203 dep = dwc->eps[epnum];
2204 if (!dep)
2205 continue;
2206 /*
2207 * Physical endpoints 0 and 1 are special; they form the
2208 * bi-directional USB endpoint 0.
2209 *
2210 * For those two physical endpoints, we don't allocate a TRB
2211 * pool nor do we add them the endpoints list. Due to that, we
2212 * shouldn't do these two operations otherwise we would end up
2213 * with all sorts of bugs when removing dwc3.ko.
2214 */
2215 if (epnum != 0 && epnum != 1) {
2216 dwc3_free_trb_pool(dep);
2217 list_del(&dep->endpoint.ep_list);
2218 }
2219
2220 kfree(dep);
2221 }
2222}
2223
2224/* -------------------------------------------------------------------------- */
2225
2226static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2227 struct dwc3_request *req, struct dwc3_trb *trb,
2228 const struct dwc3_event_depevt *event, int status,
2229 int chain)
2230{
2231 unsigned int count;
2232 unsigned int s_pkt = 0;
2233 unsigned int trb_status;
2234
2235 dwc3_ep_inc_deq(dep);
2236
2237 if (req->trb == trb)
2238 dep->queued_requests--;
2239
2240 trace_dwc3_complete_trb(dep, trb);
2241
2242 /*
2243 * If we're in the middle of series of chained TRBs and we
2244 * receive a short transfer along the way, DWC3 will skip
2245 * through all TRBs including the last TRB in the chain (the
2246 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2247 * bit and SW has to do it manually.
2248 *
2249 * We're going to do that here to avoid problems of HW trying
2250 * to use bogus TRBs for transfers.
2251 */
2252 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2253 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2254
2255 /*
2256 * If we're dealing with unaligned size OUT transfer, we will be left
2257 * with one TRB pending in the ring. We need to manually clear HWO bit
2258 * from that TRB.
2259 */
2260 if ((req->zero || req->unaligned) && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2261 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2262 return 1;
2263 }
2264
2265 count = trb->size & DWC3_TRB_SIZE_MASK;
2266 req->remaining += count;
2267
2268 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2269 return 1;
2270
2271 if (dep->direction) {
2272 if (count) {
2273 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2274 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2275 /*
2276 * If missed isoc occurred and there is
2277 * no request queued then issue END
2278 * TRANSFER, so that core generates
2279 * next xfernotready and we will issue
2280 * a fresh START TRANSFER.
2281 * If there are still queued request
2282 * then wait, do not issue either END
2283 * or UPDATE TRANSFER, just attach next
2284 * request in pending_list during
2285 * giveback.If any future queued request
2286 * is successfully transferred then we
2287 * will issue UPDATE TRANSFER for all
2288 * request in the pending_list.
2289 */
2290 dep->flags |= DWC3_EP_MISSED_ISOC;
2291 } else {
2292 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2293 dep->name);
2294 status = -ECONNRESET;
2295 }
2296 } else {
2297 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2298 }
2299 } else {
2300 if (count && (event->status & DEPEVT_STATUS_SHORT))
2301 s_pkt = 1;
2302 }
2303
2304 if (s_pkt && !chain)
2305 return 1;
2306
2307 if ((event->status & DEPEVT_STATUS_IOC) &&
2308 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2309 return 1;
2310
2311 return 0;
2312}
2313
2314static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2315 const struct dwc3_event_depevt *event, int status)
2316{
2317 struct dwc3_request *req, *n;
2318 struct dwc3_trb *trb;
2319 bool ioc = false;
2320 int ret = 0;
2321
2322 list_for_each_entry_safe(req, n, &dep->started_list, list) {
2323 unsigned length;
2324 int chain;
2325
2326 length = req->request.length;
2327 chain = req->num_pending_sgs > 0;
2328 if (chain) {
2329 struct scatterlist *sg = req->sg;
2330 struct scatterlist *s;
2331 unsigned int pending = req->num_pending_sgs;
2332 unsigned int i;
2333
2334 for_each_sg(sg, s, pending, i) {
2335 trb = &dep->trb_pool[dep->trb_dequeue];
2336
2337 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2338 break;
2339
2340 req->sg = sg_next(s);
2341 req->num_pending_sgs--;
2342
2343 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2344 event, status, chain);
2345 if (ret)
2346 break;
2347 }
2348 } else {
2349 trb = &dep->trb_pool[dep->trb_dequeue];
2350 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2351 event, status, chain);
2352 }
2353
2354 if (req->unaligned || req->zero) {
2355 trb = &dep->trb_pool[dep->trb_dequeue];
2356 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2357 event, status, false);
2358 req->unaligned = false;
2359 req->zero = false;
2360 }
2361
2362 req->request.actual = length - req->remaining;
2363
2364 if ((req->request.actual < length) && req->num_pending_sgs)
2365 return __dwc3_gadget_kick_transfer(dep, 0);
2366
2367 dwc3_gadget_giveback(dep, req, status);
2368
2369 if (ret) {
2370 if ((event->status & DEPEVT_STATUS_IOC) &&
2371 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2372 ioc = true;
2373 break;
2374 }
2375 }
2376
2377 /*
2378 * Our endpoint might get disabled by another thread during
2379 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2380 * early on so DWC3_EP_BUSY flag gets cleared
2381 */
2382 if (!dep->endpoint.desc)
2383 return 1;
2384
2385 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2386 list_empty(&dep->started_list)) {
2387 if (list_empty(&dep->pending_list)) {
2388 /*
2389 * If there is no entry in request list then do
2390 * not issue END TRANSFER now. Just set PENDING
2391 * flag, so that END TRANSFER is issued when an
2392 * entry is added into request list.
2393 */
2394 dep->flags = DWC3_EP_PENDING_REQUEST;
2395 } else {
2396 dwc3_stop_active_transfer(dwc, dep->number, true);
2397 dep->flags = DWC3_EP_ENABLED;
2398 }
2399 return 1;
2400 }
2401
2402 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2403 return 0;
2404
2405 return 1;
2406}
2407
2408static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2409 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2410{
2411 unsigned status = 0;
2412 int clean_busy;
2413 u32 is_xfer_complete;
2414
2415 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2416
2417 if (event->status & DEPEVT_STATUS_BUSERR)
2418 status = -ECONNRESET;
2419
2420 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2421 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2422 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2423 dep->flags &= ~DWC3_EP_BUSY;
2424
2425 /*
2426 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2427 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2428 */
2429 if (dwc->revision < DWC3_REVISION_183A) {
2430 u32 reg;
2431 int i;
2432
2433 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2434 dep = dwc->eps[i];
2435
2436 if (!(dep->flags & DWC3_EP_ENABLED))
2437 continue;
2438
2439 if (!list_empty(&dep->started_list))
2440 return;
2441 }
2442
2443 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2444 reg |= dwc->u1u2;
2445 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2446
2447 dwc->u1u2 = 0;
2448 }
2449
2450 /*
2451 * Our endpoint might get disabled by another thread during
2452 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2453 * early on so DWC3_EP_BUSY flag gets cleared
2454 */
2455 if (!dep->endpoint.desc)
2456 return;
2457
2458 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2459 int ret;
2460
2461 ret = __dwc3_gadget_kick_transfer(dep, 0);
2462 if (!ret || ret == -EBUSY)
2463 return;
2464 }
2465}
2466
2467static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2468 const struct dwc3_event_depevt *event)
2469{
2470 struct dwc3_ep *dep;
2471 u8 epnum = event->endpoint_number;
2472 u8 cmd;
2473
2474 dep = dwc->eps[epnum];
2475
2476 if (!(dep->flags & DWC3_EP_ENABLED)) {
2477 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2478 return;
2479
2480 /* Handle only EPCMDCMPLT when EP disabled */
2481 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2482 return;
2483 }
2484
2485 if (epnum == 0 || epnum == 1) {
2486 dwc3_ep0_interrupt(dwc, event);
2487 return;
2488 }
2489
2490 switch (event->endpoint_event) {
2491 case DWC3_DEPEVT_XFERCOMPLETE:
2492 dep->resource_index = 0;
2493
2494 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2495 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2496 return;
2497 }
2498
2499 dwc3_endpoint_transfer_complete(dwc, dep, event);
2500 break;
2501 case DWC3_DEPEVT_XFERINPROGRESS:
2502 dwc3_endpoint_transfer_complete(dwc, dep, event);
2503 break;
2504 case DWC3_DEPEVT_XFERNOTREADY:
2505 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2506 dwc3_gadget_start_isoc(dwc, dep, event);
2507 } else {
2508 int ret;
2509
2510 ret = __dwc3_gadget_kick_transfer(dep, 0);
2511 if (!ret || ret == -EBUSY)
2512 return;
2513 }
2514
2515 break;
2516 case DWC3_DEPEVT_STREAMEVT:
2517 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2518 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2519 dep->name);
2520 return;
2521 }
2522 break;
2523 case DWC3_DEPEVT_EPCMDCMPLT:
2524 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2525
2526 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2527 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2528 wake_up(&dep->wait_end_transfer);
2529 }
2530 break;
2531 case DWC3_DEPEVT_RXTXFIFOEVT:
2532 break;
2533 }
2534}
2535
2536static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2537{
2538 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2539 spin_unlock(&dwc->lock);
2540 dwc->gadget_driver->disconnect(&dwc->gadget);
2541 spin_lock(&dwc->lock);
2542 }
2543}
2544
2545static void dwc3_suspend_gadget(struct dwc3 *dwc)
2546{
2547 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2548 spin_unlock(&dwc->lock);
2549 dwc->gadget_driver->suspend(&dwc->gadget);
2550 spin_lock(&dwc->lock);
2551 }
2552}
2553
2554static void dwc3_resume_gadget(struct dwc3 *dwc)
2555{
2556 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2557 spin_unlock(&dwc->lock);
2558 dwc->gadget_driver->resume(&dwc->gadget);
2559 spin_lock(&dwc->lock);
2560 }
2561}
2562
2563static void dwc3_reset_gadget(struct dwc3 *dwc)
2564{
2565 if (!dwc->gadget_driver)
2566 return;
2567
2568 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2569 spin_unlock(&dwc->lock);
2570 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2571 spin_lock(&dwc->lock);
2572 }
2573}
2574
2575static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2576{
2577 struct dwc3_ep *dep;
2578 struct dwc3_gadget_ep_cmd_params params;
2579 u32 cmd;
2580 int ret;
2581
2582 dep = dwc->eps[epnum];
2583
2584 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2585 !dep->resource_index)
2586 return;
2587
2588 /*
2589 * NOTICE: We are violating what the Databook says about the
2590 * EndTransfer command. Ideally we would _always_ wait for the
2591 * EndTransfer Command Completion IRQ, but that's causing too
2592 * much trouble synchronizing between us and gadget driver.
2593 *
2594 * We have discussed this with the IP Provider and it was
2595 * suggested to giveback all requests here, but give HW some
2596 * extra time to synchronize with the interconnect. We're using
2597 * an arbitrary 100us delay for that.
2598 *
2599 * Note also that a similar handling was tested by Synopsys
2600 * (thanks a lot Paul) and nothing bad has come out of it.
2601 * In short, what we're doing is:
2602 *
2603 * - Issue EndTransfer WITH CMDIOC bit set
2604 * - Wait 100us
2605 *
2606 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2607 * supports a mode to work around the above limitation. The
2608 * software can poll the CMDACT bit in the DEPCMD register
2609 * after issuing a EndTransfer command. This mode is enabled
2610 * by writing GUCTL2[14]. This polling is already done in the
2611 * dwc3_send_gadget_ep_cmd() function so if the mode is
2612 * enabled, the EndTransfer command will have completed upon
2613 * returning from this function and we don't need to delay for
2614 * 100us.
2615 *
2616 * This mode is NOT available on the DWC_usb31 IP.
2617 */
2618
2619 cmd = DWC3_DEPCMD_ENDTRANSFER;
2620 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2621 cmd |= DWC3_DEPCMD_CMDIOC;
2622 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2623 memset(&params, 0, sizeof(params));
2624 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2625 WARN_ON_ONCE(ret);
2626 dep->resource_index = 0;
2627 dep->flags &= ~DWC3_EP_BUSY;
2628
2629 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2630 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2631 udelay(100);
2632 }
2633}
2634
2635static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2636{
2637 u32 epnum;
2638
2639 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2640 struct dwc3_ep *dep;
2641 int ret;
2642
2643 dep = dwc->eps[epnum];
2644 if (!dep)
2645 continue;
2646
2647 if (!(dep->flags & DWC3_EP_STALL))
2648 continue;
2649
2650 dep->flags &= ~DWC3_EP_STALL;
2651
2652 ret = dwc3_send_clear_stall_ep_cmd(dep);
2653 WARN_ON_ONCE(ret);
2654 }
2655}
2656
2657static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2658{
2659 int reg;
2660
2661 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2662 reg &= ~DWC3_DCTL_INITU1ENA;
2663 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2664
2665 reg &= ~DWC3_DCTL_INITU2ENA;
2666 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2667
2668 dwc3_disconnect_gadget(dwc);
2669
2670 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2671 dwc->setup_packet_pending = false;
2672 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2673
2674 dwc->connected = false;
2675}
2676
2677static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2678{
2679 u32 reg;
2680
2681 dwc->connected = true;
2682
2683 /*
2684 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2685 * would cause a missing Disconnect Event if there's a
2686 * pending Setup Packet in the FIFO.
2687 *
2688 * There's no suggested workaround on the official Bug
2689 * report, which states that "unless the driver/application
2690 * is doing any special handling of a disconnect event,
2691 * there is no functional issue".
2692 *
2693 * Unfortunately, it turns out that we _do_ some special
2694 * handling of a disconnect event, namely complete all
2695 * pending transfers, notify gadget driver of the
2696 * disconnection, and so on.
2697 *
2698 * Our suggested workaround is to follow the Disconnect
2699 * Event steps here, instead, based on a setup_packet_pending
2700 * flag. Such flag gets set whenever we have a SETUP_PENDING
2701 * status for EP0 TRBs and gets cleared on XferComplete for the
2702 * same endpoint.
2703 *
2704 * Refers to:
2705 *
2706 * STAR#9000466709: RTL: Device : Disconnect event not
2707 * generated if setup packet pending in FIFO
2708 */
2709 if (dwc->revision < DWC3_REVISION_188A) {
2710 if (dwc->setup_packet_pending)
2711 dwc3_gadget_disconnect_interrupt(dwc);
2712 }
2713
2714 dwc3_reset_gadget(dwc);
2715
2716 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2717 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2718 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2719 dwc->test_mode = false;
2720 dwc3_clear_stall_all_ep(dwc);
2721
2722 /* Reset device address to zero */
2723 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2724 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2725 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2726}
2727
2728static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2729{
2730 struct dwc3_ep *dep;
2731 int ret;
2732 u32 reg;
2733 u8 speed;
2734
2735 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2736 speed = reg & DWC3_DSTS_CONNECTSPD;
2737 dwc->speed = speed;
2738
2739 /*
2740 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2741 * each time on Connect Done.
2742 *
2743 * Currently we always use the reset value. If any platform
2744 * wants to set this to a different value, we need to add a
2745 * setting and update GCTL.RAMCLKSEL here.
2746 */
2747
2748 switch (speed) {
2749 case DWC3_DSTS_SUPERSPEED_PLUS:
2750 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2751 dwc->gadget.ep0->maxpacket = 512;
2752 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2753 break;
2754 case DWC3_DSTS_SUPERSPEED:
2755 /*
2756 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2757 * would cause a missing USB3 Reset event.
2758 *
2759 * In such situations, we should force a USB3 Reset
2760 * event by calling our dwc3_gadget_reset_interrupt()
2761 * routine.
2762 *
2763 * Refers to:
2764 *
2765 * STAR#9000483510: RTL: SS : USB3 reset event may
2766 * not be generated always when the link enters poll
2767 */
2768 if (dwc->revision < DWC3_REVISION_190A)
2769 dwc3_gadget_reset_interrupt(dwc);
2770
2771 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2772 dwc->gadget.ep0->maxpacket = 512;
2773 dwc->gadget.speed = USB_SPEED_SUPER;
2774 break;
2775 case DWC3_DSTS_HIGHSPEED:
2776 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2777 dwc->gadget.ep0->maxpacket = 64;
2778 dwc->gadget.speed = USB_SPEED_HIGH;
2779 break;
2780 case DWC3_DSTS_FULLSPEED:
2781 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2782 dwc->gadget.ep0->maxpacket = 64;
2783 dwc->gadget.speed = USB_SPEED_FULL;
2784 break;
2785 case DWC3_DSTS_LOWSPEED:
2786 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2787 dwc->gadget.ep0->maxpacket = 8;
2788 dwc->gadget.speed = USB_SPEED_LOW;
2789 break;
2790 }
2791
2792 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2793
2794 /* Enable USB2 LPM Capability */
2795
2796 if ((dwc->revision > DWC3_REVISION_194A) &&
2797 (speed != DWC3_DSTS_SUPERSPEED) &&
2798 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2799 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2800 reg |= DWC3_DCFG_LPM_CAP;
2801 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2802
2803 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2804 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2805
2806 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2807
2808 /*
2809 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2810 * DCFG.LPMCap is set, core responses with an ACK and the
2811 * BESL value in the LPM token is less than or equal to LPM
2812 * NYET threshold.
2813 */
2814 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2815 && dwc->has_lpm_erratum,
2816 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2817
2818 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2819 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2820
2821 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2822 } else {
2823 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2824 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2825 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2826 }
2827
2828 dep = dwc->eps[0];
2829 ret = __dwc3_gadget_ep_enable(dep, true, false);
2830 if (ret) {
2831 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2832 return;
2833 }
2834
2835 dep = dwc->eps[1];
2836 ret = __dwc3_gadget_ep_enable(dep, true, false);
2837 if (ret) {
2838 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2839 return;
2840 }
2841
2842 /*
2843 * Configure PHY via GUSB3PIPECTLn if required.
2844 *
2845 * Update GTXFIFOSIZn
2846 *
2847 * In both cases reset values should be sufficient.
2848 */
2849}
2850
2851static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2852{
2853 /*
2854 * TODO take core out of low power mode when that's
2855 * implemented.
2856 */
2857
2858 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2859 spin_unlock(&dwc->lock);
2860 dwc->gadget_driver->resume(&dwc->gadget);
2861 spin_lock(&dwc->lock);
2862 }
2863}
2864
2865static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2866 unsigned int evtinfo)
2867{
2868 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2869 unsigned int pwropt;
2870
2871 /*
2872 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2873 * Hibernation mode enabled which would show up when device detects
2874 * host-initiated U3 exit.
2875 *
2876 * In that case, device will generate a Link State Change Interrupt
2877 * from U3 to RESUME which is only necessary if Hibernation is
2878 * configured in.
2879 *
2880 * There are no functional changes due to such spurious event and we
2881 * just need to ignore it.
2882 *
2883 * Refers to:
2884 *
2885 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2886 * operational mode
2887 */
2888 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2889 if ((dwc->revision < DWC3_REVISION_250A) &&
2890 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2891 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2892 (next == DWC3_LINK_STATE_RESUME)) {
2893 return;
2894 }
2895 }
2896
2897 /*
2898 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2899 * on the link partner, the USB session might do multiple entry/exit
2900 * of low power states before a transfer takes place.
2901 *
2902 * Due to this problem, we might experience lower throughput. The
2903 * suggested workaround is to disable DCTL[12:9] bits if we're
2904 * transitioning from U1/U2 to U0 and enable those bits again
2905 * after a transfer completes and there are no pending transfers
2906 * on any of the enabled endpoints.
2907 *
2908 * This is the first half of that workaround.
2909 *
2910 * Refers to:
2911 *
2912 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2913 * core send LGO_Ux entering U0
2914 */
2915 if (dwc->revision < DWC3_REVISION_183A) {
2916 if (next == DWC3_LINK_STATE_U0) {
2917 u32 u1u2;
2918 u32 reg;
2919
2920 switch (dwc->link_state) {
2921 case DWC3_LINK_STATE_U1:
2922 case DWC3_LINK_STATE_U2:
2923 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2924 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2925 | DWC3_DCTL_ACCEPTU2ENA
2926 | DWC3_DCTL_INITU1ENA
2927 | DWC3_DCTL_ACCEPTU1ENA);
2928
2929 if (!dwc->u1u2)
2930 dwc->u1u2 = reg & u1u2;
2931
2932 reg &= ~u1u2;
2933
2934 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2935 break;
2936 default:
2937 /* do nothing */
2938 break;
2939 }
2940 }
2941 }
2942
2943 switch (next) {
2944 case DWC3_LINK_STATE_U1:
2945 if (dwc->speed == USB_SPEED_SUPER)
2946 dwc3_suspend_gadget(dwc);
2947 break;
2948 case DWC3_LINK_STATE_U2:
2949 case DWC3_LINK_STATE_U3:
2950 dwc3_suspend_gadget(dwc);
2951 break;
2952 case DWC3_LINK_STATE_RESUME:
2953 dwc3_resume_gadget(dwc);
2954 break;
2955 default:
2956 /* do nothing */
2957 break;
2958 }
2959
2960 dwc->link_state = next;
2961}
2962
2963static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2964 unsigned int evtinfo)
2965{
2966 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2967
2968 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2969 dwc3_suspend_gadget(dwc);
2970
2971 dwc->link_state = next;
2972}
2973
2974static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2975 unsigned int evtinfo)
2976{
2977 unsigned int is_ss = evtinfo & BIT(4);
2978
2979 /*
2980 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2981 * have a known issue which can cause USB CV TD.9.23 to fail
2982 * randomly.
2983 *
2984 * Because of this issue, core could generate bogus hibernation
2985 * events which SW needs to ignore.
2986 *
2987 * Refers to:
2988 *
2989 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2990 * Device Fallback from SuperSpeed
2991 */
2992 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2993 return;
2994
2995 /* enter hibernation here */
2996}
2997
2998static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2999 const struct dwc3_event_devt *event)
3000{
3001 switch (event->type) {
3002 case DWC3_DEVICE_EVENT_DISCONNECT:
3003 dwc3_gadget_disconnect_interrupt(dwc);
3004 break;
3005 case DWC3_DEVICE_EVENT_RESET:
3006 dwc3_gadget_reset_interrupt(dwc);
3007 break;
3008 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3009 dwc3_gadget_conndone_interrupt(dwc);
3010 break;
3011 case DWC3_DEVICE_EVENT_WAKEUP:
3012 dwc3_gadget_wakeup_interrupt(dwc);
3013 break;
3014 case DWC3_DEVICE_EVENT_HIBER_REQ:
3015 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3016 "unexpected hibernation event\n"))
3017 break;
3018
3019 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3020 break;
3021 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3022 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3023 break;
3024 case DWC3_DEVICE_EVENT_EOPF:
3025 /* It changed to be suspend event for version 2.30a and above */
3026 if (dwc->revision >= DWC3_REVISION_230A) {
3027 /*
3028 * Ignore suspend event until the gadget enters into
3029 * USB_STATE_CONFIGURED state.
3030 */
3031 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3032 dwc3_gadget_suspend_interrupt(dwc,
3033 event->event_info);
3034 }
3035 break;
3036 case DWC3_DEVICE_EVENT_SOF:
3037 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3038 case DWC3_DEVICE_EVENT_CMD_CMPL:
3039 case DWC3_DEVICE_EVENT_OVERFLOW:
3040 break;
3041 default:
3042 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3043 }
3044}
3045
3046static void dwc3_process_event_entry(struct dwc3 *dwc,
3047 const union dwc3_event *event)
3048{
3049 trace_dwc3_event(event->raw, dwc);
3050
3051 if (!event->type.is_devspec)
3052 dwc3_endpoint_interrupt(dwc, &event->depevt);
3053 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3054 dwc3_gadget_interrupt(dwc, &event->devt);
3055 else
3056 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3057}
3058
3059static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3060{
3061 struct dwc3 *dwc = evt->dwc;
3062 irqreturn_t ret = IRQ_NONE;
3063 int left;
3064 u32 reg;
3065
3066 left = evt->count;
3067
3068 if (!(evt->flags & DWC3_EVENT_PENDING))
3069 return IRQ_NONE;
3070
3071 while (left > 0) {
3072 union dwc3_event event;
3073
3074 event.raw = *(u32 *) (evt->cache + evt->lpos);
3075
3076 dwc3_process_event_entry(dwc, &event);
3077
3078 /*
3079 * FIXME we wrap around correctly to the next entry as
3080 * almost all entries are 4 bytes in size. There is one
3081 * entry which has 12 bytes which is a regular entry
3082 * followed by 8 bytes data. ATM I don't know how
3083 * things are organized if we get next to the a
3084 * boundary so I worry about that once we try to handle
3085 * that.
3086 */
3087 evt->lpos = (evt->lpos + 4) % evt->length;
3088 left -= 4;
3089 }
3090
3091 evt->count = 0;
3092 evt->flags &= ~DWC3_EVENT_PENDING;
3093 ret = IRQ_HANDLED;
3094
3095 /* Unmask interrupt */
3096 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3097 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3098 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3099
3100 if (dwc->imod_interval) {
3101 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3102 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3103 }
3104
3105 return ret;
3106}
3107
3108static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3109{
3110 struct dwc3_event_buffer *evt = _evt;
3111 struct dwc3 *dwc = evt->dwc;
3112 unsigned long flags;
3113 irqreturn_t ret = IRQ_NONE;
3114
3115 spin_lock_irqsave(&dwc->lock, flags);
3116 ret = dwc3_process_event_buf(evt);
3117 spin_unlock_irqrestore(&dwc->lock, flags);
3118
3119 return ret;
3120}
3121
3122static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3123{
3124 struct dwc3 *dwc = evt->dwc;
3125 u32 amount;
3126 u32 count;
3127 u32 reg;
3128
3129 if (pm_runtime_suspended(dwc->dev)) {
3130 pm_runtime_get(dwc->dev);
3131 disable_irq_nosync(dwc->irq_gadget);
3132 dwc->pending_events = true;
3133 return IRQ_HANDLED;
3134 }
3135
3136 /*
3137 * With PCIe legacy interrupt, test shows that top-half irq handler can
3138 * be called again after HW interrupt deassertion. Check if bottom-half
3139 * irq event handler completes before caching new event to prevent
3140 * losing events.
3141 */
3142 if (evt->flags & DWC3_EVENT_PENDING)
3143 return IRQ_HANDLED;
3144
3145 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3146 count &= DWC3_GEVNTCOUNT_MASK;
3147 if (!count)
3148 return IRQ_NONE;
3149
3150 evt->count = count;
3151 evt->flags |= DWC3_EVENT_PENDING;
3152
3153 /* Mask interrupt */
3154 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3155 reg |= DWC3_GEVNTSIZ_INTMASK;
3156 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3157
3158 amount = min(count, evt->length - evt->lpos);
3159 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3160
3161 if (amount < count)
3162 memcpy(evt->cache, evt->buf, count - amount);
3163
3164 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3165
3166 return IRQ_WAKE_THREAD;
3167}
3168
3169static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3170{
3171 struct dwc3_event_buffer *evt = _evt;
3172
3173 return dwc3_check_event_buf(evt);
3174}
3175
3176static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3177{
3178 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3179 int irq;
3180
3181 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3182 if (irq > 0)
3183 goto out;
3184
3185 if (irq == -EPROBE_DEFER)
3186 goto out;
3187
3188 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3189 if (irq > 0)
3190 goto out;
3191
3192 if (irq == -EPROBE_DEFER)
3193 goto out;
3194
3195 irq = platform_get_irq(dwc3_pdev, 0);
3196 if (irq > 0)
3197 goto out;
3198
3199 if (irq != -EPROBE_DEFER)
3200 dev_err(dwc->dev, "missing peripheral IRQ\n");
3201
3202 if (!irq)
3203 irq = -EINVAL;
3204
3205out:
3206 return irq;
3207}
3208
3209/**
3210 * dwc3_gadget_init - initializes gadget related registers
3211 * @dwc: pointer to our controller context structure
3212 *
3213 * Returns 0 on success otherwise negative errno.
3214 */
3215int dwc3_gadget_init(struct dwc3 *dwc)
3216{
3217 int ret;
3218 int irq;
3219
3220 irq = dwc3_gadget_get_irq(dwc);
3221 if (irq < 0) {
3222 ret = irq;
3223 goto err0;
3224 }
3225
3226 dwc->irq_gadget = irq;
3227
3228 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3229 sizeof(*dwc->ep0_trb) * 2,
3230 &dwc->ep0_trb_addr, GFP_KERNEL);
3231 if (!dwc->ep0_trb) {
3232 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3233 ret = -ENOMEM;
3234 goto err0;
3235 }
3236
3237 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3238 if (!dwc->setup_buf) {
3239 ret = -ENOMEM;
3240 goto err1;
3241 }
3242
3243 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3244 &dwc->bounce_addr, GFP_KERNEL);
3245 if (!dwc->bounce) {
3246 ret = -ENOMEM;
3247 goto err2;
3248 }
3249
3250 init_completion(&dwc->ep0_in_setup);
3251
3252 dwc->gadget.ops = &dwc3_gadget_ops;
3253 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3254 dwc->gadget.sg_supported = true;
3255 dwc->gadget.name = "dwc3-gadget";
3256
3257 /*
3258 * FIXME We might be setting max_speed to <SUPER, however versions
3259 * <2.20a of dwc3 have an issue with metastability (documented
3260 * elsewhere in this driver) which tells us we can't set max speed to
3261 * anything lower than SUPER.
3262 *
3263 * Because gadget.max_speed is only used by composite.c and function
3264 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3265 * to happen so we avoid sending SuperSpeed Capability descriptor
3266 * together with our BOS descriptor as that could confuse host into
3267 * thinking we can handle super speed.
3268 *
3269 * Note that, in fact, we won't even support GetBOS requests when speed
3270 * is less than super speed because we don't have means, yet, to tell
3271 * composite.c that we are USB 2.0 + LPM ECN.
3272 */
3273 if (dwc->revision < DWC3_REVISION_220A &&
3274 !dwc->dis_metastability_quirk)
3275 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3276 dwc->revision);
3277
3278 dwc->gadget.max_speed = dwc->maximum_speed;
3279
3280 /*
3281 * REVISIT: Here we should clear all pending IRQs to be
3282 * sure we're starting from a well known location.
3283 */
3284
3285 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3286 if (ret)
3287 goto err3;
3288
3289 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3290 if (ret) {
3291 dev_err(dwc->dev, "failed to register udc\n");
3292 goto err4;
3293 }
3294
3295 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3296
3297 return 0;
3298
3299err4:
3300 dwc3_gadget_free_endpoints(dwc);
3301
3302err3:
3303 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3304 dwc->bounce_addr);
3305
3306err2:
3307 kfree(dwc->setup_buf);
3308
3309err1:
3310 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3311 dwc->ep0_trb, dwc->ep0_trb_addr);
3312
3313err0:
3314 return ret;
3315}
3316
3317/* -------------------------------------------------------------------------- */
3318
3319void dwc3_gadget_exit(struct dwc3 *dwc)
3320{
3321 usb_del_gadget_udc(&dwc->gadget);
3322 dwc3_gadget_free_endpoints(dwc);
3323 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3324 dwc->bounce_addr);
3325 kfree(dwc->setup_buf);
3326 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3327 dwc->ep0_trb, dwc->ep0_trb_addr);
3328}
3329
3330int dwc3_gadget_suspend(struct dwc3 *dwc)
3331{
3332 if (!dwc->gadget_driver)
3333 return 0;
3334
3335 dwc3_gadget_run_stop(dwc, false, false);
3336 dwc3_disconnect_gadget(dwc);
3337 __dwc3_gadget_stop(dwc);
3338
3339 synchronize_irq(dwc->irq_gadget);
3340
3341 return 0;
3342}
3343
3344int dwc3_gadget_resume(struct dwc3 *dwc)
3345{
3346 int ret;
3347
3348 if (!dwc->gadget_driver)
3349 return 0;
3350
3351 ret = __dwc3_gadget_start(dwc);
3352 if (ret < 0)
3353 goto err0;
3354
3355 ret = dwc3_gadget_run_stop(dwc, true, false);
3356 if (ret < 0)
3357 goto err1;
3358
3359 return 0;
3360
3361err1:
3362 __dwc3_gadget_stop(dwc);
3363
3364err0:
3365 return ret;
3366}
3367
3368void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3369{
3370 if (dwc->pending_events) {
3371 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3372 dwc->pending_events = false;
3373 enable_irq(dwc->irq_gadget);
3374 }
3375}