src/kernel/linux/v4.14/include/dt-bindings/clock/mt2731-clk.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Author: Yong Wu <yong.wu@mediatek.com>
 */

#ifndef _DT_BINDINGS_CLK_MT2731_H
#define _DT_BINDINGS_CLK_MT2731_H

/* APMIXEDSYS */

#define CLK_APMIXED_ARMPLL		0
#define CLK_APMIXED_MAINPLL		1
#define CLK_APMIXED_UNIVPLL		2
#define CLK_APMIXED_MSDCPLL		3
#define CLK_APMIXED_APLL1		4
#define CLK_APMIXED_APLL2		5
#define CLK_APMIXED_MPLL		6
#define CLK_APMIXED_ETHERPLL		7
#define CLK_APMIXED_NR_CLK		8

/* TOPCKGEN */

#define CLK_TOP_CLK26M			0
#define CLK_TOP_SYSPLL			1
#define CLK_TOP_SYSPLL_D2		2
#define CLK_TOP_SYSPLL1_D2		3
#define CLK_TOP_SYSPLL1_D4		4
#define CLK_TOP_SYSPLL1_D8		5
#define CLK_TOP_SYSPLL1_D16		6
#define CLK_TOP_SYSPLL_D3		7
#define CLK_TOP_SYSPLL2_D2		8
#define CLK_TOP_SYSPLL2_D4		9
#define CLK_TOP_SYSPLL2_D8		10
#define CLK_TOP_SYSPLL_D5		11
#define CLK_TOP_SYSPLL3_D2		12
#define CLK_TOP_SYSPLL3_D4		13
#define CLK_TOP_SYSPLL_D7		14
#define CLK_TOP_SYSPLL4_D2		15
#define CLK_TOP_SYSPLL4_D4		16
#define CLK_TOP_USB20_192M		17
#define CLK_TOP_USB20_192M_D2		18
#define CLK_TOP_USB20_192M_D4		19
#define CLK_TOP_UNIVPLL_D2		20
#define CLK_TOP_UNIVPLL1_D2		21
#define CLK_TOP_UNIVPLL1_D4		22
#define CLK_TOP_UNIVPLL1_D8		23
#define CLK_TOP_UNIVPLL_D3		24
#define CLK_TOP_UNIVPLL2_D2		25
#define CLK_TOP_UNIVPLL2_D4		26
#define CLK_TOP_UNIVPLL2_D8		27
#define CLK_TOP_UNIVPLL2_D16		28
#define CLK_TOP_UNIVPLL_D5		29
#define CLK_TOP_UNIVPLL3_D2		30
#define CLK_TOP_UNIVPLL3_D4		31
#define CLK_TOP_MSDCPLL			32
#define CLK_TOP_MSDCPLL_D2		33
#define CLK_TOP_APLL1			34
#define CLK_TOP_APLL1_D2		35
#define CLK_TOP_APLL1_D4		36
#define CLK_TOP_APLL1_D8		37
#define CLK_TOP_APLL2			38
#define CLK_TOP_APLL2_D2		39
#define CLK_TOP_APLL2_D4		40
#define CLK_TOP_APLL2_D8		41
#define CLK_TOP_ETHERPLL		42
#define CLK_TOP_ETHERPLL_D4		43
#define CLK_TOP_ETHERPLL_D10		44
#define CLK_TOP_HD_FAXI			45
#define CLK_TOP_F_FUART			46
#define CLK_TOP_SPI			47
#define CLK_TOP_MSDC50_0		48
#define CLK_TOP_MSDC30_1		49
#define CLK_TOP_AUDIO			50
#define CLK_TOP_AUD_1			51
#define CLK_TOP_AUD_ENGEN1		52
#define CLK_TOP_AUD_ENGEN2		53
#define CLK_TOP_HSM_CRYPTO		54
#define CLK_TOP_I2C			55
#define CLK_TOP_MSDC50_2_HCLK		56
#define CLK_TOP_MSDC30_2		57
#define CLK_TOP_NFI1X_BCLK		58
#define CLK_TOP_PCIE_MAC		59
#define CLK_TOP_F_FSSUSB_TOP		60
#define CLK_TOP_SPISLV			61
#define CLK_TOP_ETHER_125M		62
#define CLK_TOP_PWM			63
#define CLK_TOP_ARMPLL_DIVIDER_PLL1	64
#define CLK_TOP_ARMPLL_DIVIDER_PLL2	65
#define CLK_TOP_AXI_SEL			66
#define CLK_TOP_UART_SEL		67
#define CLK_TOP_SPI_SEL			68
#define CLK_TOP_MSDC50_0_HCLK_SEL	69
#define CLK_TOP_MSDC50_0_SEL		70
#define CLK_TOP_MSDC30_1_SEL		71
#define CLK_TOP_AUDIO_SEL		72
#define CLK_TOP_AUD_INTBUS_SEL		73
#define CLK_TOP_AUD_1_SEL		74
#define CLK_TOP_AUD_2_SEL		75
#define CLK_TOP_AUD_ENGEN1_SEL		76
#define CLK_TOP_AUD_ENGEN2_SEL		77
#define CLK_TOP_DXCC_SEL		78
#define CLK_TOP_HSM_CRYPTO_SEL		79 /* no use */
#define CLK_TOP_HSM_ARC_SEL		80 /* no use */
#define CLK_TOP_GCPU_SEL		81
#define CLK_TOP_ECC_SEL			82
#define CLK_TOP_USB_TOP_SEL		83
#define CLK_TOP_SPM_SEL			84
#define CLK_TOP_I2C_SEL			85
#define CLK_TOP_PWRAP_ULPOSC_SEL	86
#define CLK_TOP_MSDC50_2_HCLK_SEL	87
#define CLK_TOP_MSDC30_2_SEL		88
#define CLK_TOP_NFI1X_BCLK_SEL		89
#define CLK_TOP_SPINFI_BCLK_SEL		90
#define CLK_TOP_PCIE_MAC_SEL		91
#define CLK_TOP_SSUSB_TOP_SEL		92
#define CLK_TOP_SPISLV_SEL		93
#define CLK_TOP_ETHER_125M_SEL		94
#define CLK_TOP_ETHER_50M_RMII_SEL	95
#define CLK_TOP_ETHER_62P4M_SEL		96
#define CLK_TOP_PWM_SEL			97
#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN	98
#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN	99
#define CLK_TOP_I2S0_M_SEL		100
#define CLK_TOP_I2S1_M_SEL		101
#define CLK_TOP_I2S2_M_SEL		102
#define CLK_TOP_I2S3_M_SEL		103
#define CLK_TOP_I2S4_M_SEL		104
#define CLK_TOP_I2S5_M_SEL		105
#define CLK_TOP_APLL12_DIV0		106
#define CLK_TOP_APLL12_DIV1		107
#define CLK_TOP_APLL12_DIV2		108
#define CLK_TOP_APLL12_DIV3		109
#define CLK_TOP_APLL12_DIV4		110
#define CLK_TOP_APLL12_DIVB		111
#define CLK_TOP_APLL12_DIV5		112
#define CLK_TOP_NR_CLK			113

/* INFRACFG */

#define CLK_IFR_APXGPT			0
#define CLK_IFR_ICUSB			1
#define CLK_IFR_GCE			2
#define CLK_IFR_THERM			3
#define CLK_IFR_I2C_AP			4
#define CLK_IFR_I2C_CCU			5
#define CLK_IFR_I2C_SSPM		6
#define CLK_IFR_I2C_RSV			7
#define CLK_IFR_PWM_HCLK		8
#define CLK_IFR_PWM1			9
#define CLK_IFR_PWM2			10
#define CLK_IFR_PWM3			11
#define CLK_IFR_PWM4			12
#define CLK_IFR_PWM5			13
#define CLK_IFR_PWM			14
#define CLK_IFR_UART0			15
#define CLK_IFR_UART1			16
#define CLK_IFR_UART2			17
#define CLK_IFR_UART3			18
#define CLK_IFR_GCE_26M			19
#define CLK_IFR_CQ_DMA_FPC		20 /* defeature */
#define CLK_IFR_SPI0			21
#define CLK_IFR_MSDC0			22
#define CLK_IFR_MSDC1			23
#define CLK_IFR_MSDC2			24
#define CLK_IFR_TRNG			25
#define CLK_IFR_CCIF1_AP		26
#define CLK_IFR_CCIF1_MD		27
#define CLK_IFR_PCIE			28
#define CLK_IFR_NFI			29
#define CLK_IFR_AP_DMA			30
#define CLK_IFR_DEVICE_APC		31
#define CLK_IFR_CCIF_AP			32
/* #define CLK_IFR_DEBUGSYS		33 */
#define CLK_IFR_CCIF_MD			34
#define CLK_IFR_HSM			35 /* no use */
#define CLK_IFR_HSM_AO			36 /* no use */
#define CLK_IFR_ETHER			37
#define CLK_IFR_SPI_SLAVE		38
#define CLK_IFR_RG_PWM_FBCLK6		39
#define CLK_IFR_SSUSB			40
#define CLK_IFR_CLDMA_BCLK		41
#define CLK_IFR_AUDIO_26M_BCLK		42
#define CLK_IFR_SPI1			43
#define CLK_IFR_SPI2			44
#define CLK_IFR_SPI3			45 /* defeature */
#define CLK_IFR_SPI4			46 /* defeature */
#define CLK_IFR_SPI5			47 /* defeature */
#define CLK_IFR_CQ_DMA			48
#define CLK_IFR_I2C6			49 /* defeature */
#define CLK_IFR_MSDC0_SRC		50
#define CLK_IFR_MSDC1_SRC		51
#define CLK_IFR_MSDC2_SRC		52
#define CLK_IFR_MCU_PM_BCLK		53
#define CLK_IFR_CCIF2_AP		54
#define CLK_IFR_CCIF2_MD		55
#define CLK_IFR_UART4			56
#define CLK_IFR_UART5			57
#define CLK_IFR_UART6			58
#define CLK_IFR_NR_CLK			59

/* AUDIO */

#define CLK_AUDIO_AFE			0
#define CLK_AUDIO_22M			1
#define CLK_AUDIO_24M			2
#define CLK_AUDIO_APLL2_TUNER		3
#define CLK_AUDIO_APLL_TUNER		4
#define CLK_AUDIO_ADC			5
#define CLK_AUDIO_DAC			6
#define CLK_AUDIO_DAC_PREDIS		7
#define CLK_AUDIO_TML			8
#define CLK_AUDIO_NLE			9
#define CLK_AUDIO_I2S0_BCLK		10
#define CLK_AUDIO_I2S1_BCLK		11
#define CLK_AUDIO_I2S2_BCLK		12
#define CLK_AUDIO_I2S4_BCLK		13
#define CLK_AUDIO_I2S5_BCLK		14
#define CLK_AUDIO_I2S6_BCLK		15
#define CLK_AUDIO_NR_CLK		16

#endif /* _DT_BINDINGS_CLK_MT2731_H */