| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2019 MediaTek Inc. |
| 4 | */ |
| 5 | |
| 6 | #ifndef _DT_BINDINGS_MT6389_IRQ_H |
| 7 | #define _DT_BINDINGS_MT6389_IRQ_H |
| 8 | |
| 9 | #define SP_BUCK 0 |
| 10 | #define SP_LDO 1 |
| 11 | #define SP_PSC 2 |
| 12 | #define SP_SCK 3 |
| 13 | #define SP_HK 4 |
| 14 | #define SP_AUD 5 |
| 15 | #define SP_MISC 6 |
| 16 | |
| 17 | // BUCK |
| 18 | #define INT_VPROC_OC 0 |
| 19 | #define INT_VCORE_OC 1 |
| 20 | #define INT_VSRAM_OTHERS_OC 2 |
| 21 | #define INT_VMODEM_OC 3 |
| 22 | #define INT_VDRAM1_OC 4 |
| 23 | #define INT_VS1_OC 5 |
| 24 | #define INT_VS2_OC 6 |
| 25 | #define INT_VPA_OC 7 |
| 26 | // LDO |
| 27 | #define INT_VFE28_OC 16 |
| 28 | #define INT_VRF18_OC 17 |
| 29 | #define INT_VRF12_OC 18 |
| 30 | #define INT_VGP3_OC 19 |
| 31 | #define INT_VCN33_OC 20 |
| 32 | #define INT_VCN18_OC 21 |
| 33 | #define INT_VA12_OC 22 |
| 34 | #define INT_VA09_OC 23 |
| 35 | #define INT_VAUX18_OC 24 |
| 36 | #define INT_VAUD28_OC 25 |
| 37 | #define INT_VIO18_OC 26 |
| 38 | #define INT_VIO33_OC 27 |
| 39 | #define INT_VGP1_OC 28 |
| 40 | #define INT_VGP2_OC 29 |
| 41 | #define INT_VSRAM_PROC_OC 30 |
| 42 | #define INT_VDRAM2_OC 31 |
| 43 | #define INT_VMCH_OC 32 |
| 44 | #define INT_VEMC_OC 33 |
| 45 | #define INT_VSIM1_OC 34 |
| 46 | #define INT_VSIM2_OC 35 |
| 47 | #define INT_VUSB_OC 36 |
| 48 | #define INT_VXO22_OC 37 |
| 49 | #define INT_VRFCK_OC 38 |
| 50 | #define INT_VBBCK_OC 39 |
| 51 | // PSC |
| 52 | #define INT_ENB_R 48 |
| 53 | #define INT_PMIC_RESET_B_H2L 49 |
| 54 | #define INT_NI_LBAT_INT 50 |
| 55 | #define INT_CHRDET 51 |
| 56 | #define INT_CHRDET_EDGE 52 |
| 57 | // SCK |
| 58 | #define INT_RTC 64 |
| 59 | // HK |
| 60 | #define INT_THR_H 86 |
| 61 | #define INT_THR_L 87 |
| 62 | #define INT_INTER1_DET_DIV_H 96 |
| 63 | #define INT_INTER1_DET_DIV_L 97 |
| 64 | #define INT_INTER2_DET_DIV_H 98 |
| 65 | #define INT_INTER2_DET_DIV_L 99 |
| 66 | #define INT_INTER3_DET_DIV_H 100 |
| 67 | #define INT_INTER3_DET_DIV_L 101 |
| 68 | #define INT_INTER4_DET_DIV_H 102 |
| 69 | #define INT_INTER4_DET_DIV_L 103 |
| 70 | #define INT_INTER5_DET_DIV_H 104 |
| 71 | #define INT_INTER5_DET_DIV_L 105 |
| 72 | #define INT_INTER6_DET_DIV_H 106 |
| 73 | #define INT_INTER6_DET_DIV_L 107 |
| 74 | #define INT_INTER7_DET_DIV_H 108 |
| 75 | #define INT_INTER7_DET_DIV_L 109 |
| 76 | #define INT_INTER8_DET_DIV_H 110 |
| 77 | #define INT_INTER8_DET_DIV_L 111 |
| 78 | #define INT_INTER9_DET_DIV_H 112 |
| 79 | #define INT_INTER9_DET_DIV_L 113 |
| 80 | #define INT_INTER10_DET_DIV_H 114 |
| 81 | #define INT_INTER10_DET_DIV_L 115 |
| 82 | #define INT_INTER11_DET_DIV_H 116 |
| 83 | #define INT_INTER11_DET_DIV_L 117 |
| 84 | #define INT_INTER12_DET_DIV_H 118 |
| 85 | #define INT_INTER12_DET_DIV_L 119 |
| 86 | #define INT_INTER13_DET_DIV_H 120 |
| 87 | #define INT_INTER13_DET_DIV_L 121 |
| 88 | #define INT_INTER14_DET_DIV_H 122 |
| 89 | #define INT_INTER14_DET_DIV_L 123 |
| 90 | #define INT_INTER1_DET_H 124 |
| 91 | #define INT_INTER1_DET_L 125 |
| 92 | #define INT_INTER2_DET_H 128 |
| 93 | #define INT_INTER2_DET_L 129 |
| 94 | #define INT_INTER3_DET_H 130 |
| 95 | #define INT_INTER3_DET_L 131 |
| 96 | #define INT_INTER4_DET_H 132 |
| 97 | #define INT_INTER4_DET_L 133 |
| 98 | #define INT_INTER5_DET_H 134 |
| 99 | #define INT_INTER5_DET_L 135 |
| 100 | #define INT_INTER6_DET_H 136 |
| 101 | #define INT_INTER6_DET_L 137 |
| 102 | #define INT_INTER7_DET_H 138 |
| 103 | #define INT_INTER7_DET_L 139 |
| 104 | #define INT_INTER8_DET_H 140 |
| 105 | #define INT_INTER8_DET_L 141 |
| 106 | #define INT_INTER9_DET_H 142 |
| 107 | #define INT_INTER9_DET_L 143 |
| 108 | // AUDIO |
| 109 | #define INT_AUDIO 144 |
| 110 | // MISC |
| 111 | #define INT_SPI_CMD_ALERT 160 |
| 112 | |
| 113 | #endif /* _DT_BINDINGS_MT6389_IRQ_H */ |