| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* MFD cell driver data for the DS1WM driver |
| 3 | * |
| 4 | * to be defined in the MFD device that is |
| 5 | * using this driver for one of his sub devices |
| 6 | */ |
| 7 | |
| 8 | struct ds1wm_driver_data { |
| 9 | int active_high; |
| 10 | int clock_rate; |
| 11 | /* in milliseconds, the amount of time to |
| 12 | * sleep following a reset pulse. Zero |
| 13 | * should work if your bus devices recover |
| 14 | * time respects the 1-wire spec since the |
| 15 | * ds1wm implements the precise timings of |
| 16 | * a reset pulse/presence detect sequence. |
| 17 | */ |
| 18 | unsigned int reset_recover_delay; |
| 19 | |
| 20 | /* Say 1 here for big endian Hardware |
| 21 | * (only relevant with bus-shift > 0 |
| 22 | */ |
| 23 | bool is_hw_big_endian; |
| 24 | |
| 25 | /* left shift of register number to get register address offsett. |
| 26 | * Only 0,1,2 allowed for 8,16 or 32 bit bus width respectively |
| 27 | */ |
| 28 | unsigned int bus_shift; |
| 29 | }; |