| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef __ADAU1373_H__ |
| 3 | #define __ADAU1373_H__ |
| 4 | |
| 5 | enum adau1373_pll_src { |
| 6 | ADAU1373_PLL_SRC_MCLK1 = 0, |
| 7 | ADAU1373_PLL_SRC_BCLK1 = 1, |
| 8 | ADAU1373_PLL_SRC_BCLK2 = 2, |
| 9 | ADAU1373_PLL_SRC_BCLK3 = 3, |
| 10 | ADAU1373_PLL_SRC_LRCLK1 = 4, |
| 11 | ADAU1373_PLL_SRC_LRCLK2 = 5, |
| 12 | ADAU1373_PLL_SRC_LRCLK3 = 6, |
| 13 | ADAU1373_PLL_SRC_GPIO1 = 7, |
| 14 | ADAU1373_PLL_SRC_GPIO2 = 8, |
| 15 | ADAU1373_PLL_SRC_GPIO3 = 9, |
| 16 | ADAU1373_PLL_SRC_GPIO4 = 10, |
| 17 | ADAU1373_PLL_SRC_MCLK2 = 11, |
| 18 | }; |
| 19 | |
| 20 | enum adau1373_pll { |
| 21 | ADAU1373_PLL1 = 0, |
| 22 | ADAU1373_PLL2 = 1, |
| 23 | }; |
| 24 | |
| 25 | enum adau1373_clk_src { |
| 26 | ADAU1373_CLK_SRC_PLL1 = 0, |
| 27 | ADAU1373_CLK_SRC_PLL2 = 1, |
| 28 | }; |
| 29 | |
| 30 | #endif |