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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / kernel / linux / v4.14 / sound / soc / codecs / mt6358.c
blob: e6ef08e7cffea4cb5a1975a81a99b2a3e2dc40a9 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2//
3// mt6358.c -- mt6358 ALSA SoC audio codec driver
4//
5// Copyright (c) 2018 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/platform_device.h>
9#include <linux/module.h>
10#include <linux/of_device.h>
11#include <linux/delay.h>
12#include <linux/debugfs.h>
13#include <linux/kthread.h>
14#include <linux/sched.h>
15
16#include <sound/soc.h>
17#include <sound/tlv.h>
18
19#include "mt6358.h"
20
21enum {
22 AUDIO_ANALOG_VOLUME_HSOUTL,
23 AUDIO_ANALOG_VOLUME_HSOUTR,
24 AUDIO_ANALOG_VOLUME_HPOUTL,
25 AUDIO_ANALOG_VOLUME_HPOUTR,
26 AUDIO_ANALOG_VOLUME_LINEOUTL,
27 AUDIO_ANALOG_VOLUME_LINEOUTR,
28 AUDIO_ANALOG_VOLUME_MICAMP1,
29 AUDIO_ANALOG_VOLUME_MICAMP2,
30 AUDIO_ANALOG_VOLUME_TYPE_MAX
31};
32
33enum {
34 MUX_ADC_L,
35 MUX_ADC_R,
36 MUX_PGA_L,
37 MUX_PGA_R,
38 MUX_MIC_TYPE,
39 MUX_HP_L,
40 MUX_HP_R,
41 MUX_NUM,
42};
43
44enum {
45 DEVICE_HP,
46 DEVICE_LO,
47 DEVICE_RCV,
48 DEVICE_MIC1,
49 DEVICE_MIC2,
50 DEVICE_NUM
51};
52
53/* Supply widget subseq */
54enum {
55 /* common */
56 SUPPLY_SEQ_CLK_BUF,
57 SUPPLY_SEQ_AUD_GLB,
58 SUPPLY_SEQ_CLKSQ,
59 SUPPLY_SEQ_VOW_AUD_LPW,
60 SUPPLY_SEQ_AUD_VOW,
61 SUPPLY_SEQ_VOW_CLK,
62 SUPPLY_SEQ_VOW_LDO,
63 SUPPLY_SEQ_TOP_CK,
64 SUPPLY_SEQ_TOP_CK_LAST,
65 SUPPLY_SEQ_AUD_TOP,
66 SUPPLY_SEQ_AUD_TOP_LAST,
67 SUPPLY_SEQ_AFE,
68 /* capture */
69 SUPPLY_SEQ_ADC_SUPPLY,
70};
71
72enum {
73 CH_L = 0,
74 CH_R,
75 NUM_CH,
76};
77
78#define REG_STRIDE 2
79
80struct mt6358_priv {
81 struct device *dev;
82 struct regmap *regmap;
83
84 unsigned int dl_rate;
85 unsigned int ul_rate;
86
87 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
88 unsigned int mux_select[MUX_NUM];
89
90 int dev_counter[DEVICE_NUM];
91
92 int mtkaif_protocol;
93
94 struct dentry *debugfs; // TODO: remove
95 unsigned int debug_flag;
96};
97
98int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
99 int mtkaif_protocol)
100{
101 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
102
103 priv->mtkaif_protocol = mtkaif_protocol;
104 return 0;
105}
106
107static void playback_gpio_set(struct mt6358_priv *priv)
108{
109 /* set gpio mosi mode */
110 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
111 0x01f8, 0x01f8);
112 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET,
113 0xffff, 0x0249);
114 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
115 0xffff, 0x0249);
116}
117
118static void playback_gpio_reset(struct mt6358_priv *priv)
119{
120 /* set pad_aud_*_mosi to GPIO mode and dir input
121 * reason:
122 * pad_aud_dat_mosi*, because the pin is used as boot strap
123 * don't clean clk/sync, for mtkaif protocol 2
124 */
125 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
126 0x01f8, 0x01f8);
127 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
128 0x01f8, 0x0000);
129 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
130 0xf << 8, 0x0);
131}
132
133static void capture_gpio_set(struct mt6358_priv *priv)
134{
135 /* set gpio miso mode */
136 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
137 0xffff, 0xffff);
138 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET,
139 0xffff, 0x0249);
140 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
141 0xffff, 0x0249);
142}
143
144static void capture_gpio_reset(struct mt6358_priv *priv)
145{
146 /* set pad_aud_*_miso to GPIO mode and dir input
147 * reason:
148 * pad_aud_clk_miso, because when playback only the miso_clk
149 * will also have 26m, so will have power leak
150 * pad_aud_dat_miso*, because the pin is used as boot strap
151 */
152 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
153 0xffff, 0xffff);
154 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
155 0xffff, 0x0000);
156 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
157 0xf << 12, 0x0);
158}
159
160/* use only when not govern by DAPM */
161static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable)
162{
163 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14,
164 0x1 << RG_XO_AUDIO_EN_M_SFT,
165 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
166 return 0;
167}
168
169/* use only when not govern by DAPM */
170static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable)
171{
172 /* audio clk source from internal dcxo */
173 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
174 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
175 0x0);
176
177 /* Enable/disable CLKSQ 26MHz */
178 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
179 RG_CLKSQ_EN_MASK_SFT,
180 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
181 return 0;
182}
183
184/* use only when not govern by DAPM */
185static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable)
186{
187 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
188 RG_AUDGLB_PWRDN_VA28_MASK_SFT,
189 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT);
190 return 0;
191}
192
193/* use only when not govern by DAPM */
194static int mt6358_set_topck(struct mt6358_priv *priv, bool enable)
195{
196 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
197 0x0066, enable ? 0x0 : 0x66);
198 return 0;
199}
200
201static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv)
202{
203 switch (priv->mtkaif_protocol) {
204 case MT6358_MTKAIF_PROTOCOL_2_CLK_P2:
205 /* MTKAIF TX format setting */
206 regmap_update_bits(priv->regmap,
207 MT6358_AFE_ADDA_MTKAIF_CFG0,
208 0xffff, 0x0010);
209 /* enable aud_pad TX fifos */
210 regmap_update_bits(priv->regmap,
211 MT6358_AFE_AUD_PAD_TOP,
212 0xff00, 0x3800);
213 regmap_update_bits(priv->regmap,
214 MT6358_AFE_AUD_PAD_TOP,
215 0xff00, 0x3900);
216 break;
217 case MT6358_MTKAIF_PROTOCOL_2:
218 /* MTKAIF TX format setting */
219 regmap_update_bits(priv->regmap,
220 MT6358_AFE_ADDA_MTKAIF_CFG0,
221 0xffff, 0x0010);
222 /* enable aud_pad TX fifos */
223 regmap_update_bits(priv->regmap,
224 MT6358_AFE_AUD_PAD_TOP,
225 0xff00, 0x3100);
226 break;
227 case MT6358_MTKAIF_PROTOCOL_1:
228 default:
229 /* MTKAIF TX format setting */
230 regmap_update_bits(priv->regmap,
231 MT6358_AFE_ADDA_MTKAIF_CFG0,
232 0xffff, 0x0000);
233 /* enable aud_pad TX fifos */
234 regmap_update_bits(priv->regmap,
235 MT6358_AFE_AUD_PAD_TOP,
236 0xff00, 0x3100);
237 break;
238 }
239 return 0;
240}
241
242static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv)
243{
244 /* disable aud_pad TX fifos */
245 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP,
246 0xff00, 0x3000);
247 return 0;
248}
249
250int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
251{
252 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
253
254 playback_gpio_set(priv);
255 capture_gpio_set(priv);
256 mt6358_mtkaif_tx_enable(priv);
257
258 mt6358_set_dcxo(priv, true);
259 mt6358_set_aud_global_bias(priv, true);
260 mt6358_set_clksq(priv, true);
261 mt6358_set_topck(priv, true);
262
263 /* set dat_miso_loopback on */
264 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
265 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
266 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
267 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
268 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
269 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
270 return 0;
271}
272
273int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
274{
275 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
276
277 /* set dat_miso_loopback off */
278 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
279 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
280 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
281 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
282 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
283 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
284
285 mt6358_set_topck(priv, false);
286 mt6358_set_clksq(priv, false);
287 mt6358_set_aud_global_bias(priv, false);
288 mt6358_set_dcxo(priv, false);
289
290 mt6358_mtkaif_tx_disable(priv);
291 playback_gpio_reset(priv);
292 capture_gpio_reset(priv);
293 return 0;
294}
295
296int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
297 int phase_1, int phase_2)
298{
299 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
300
301 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
302 RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
303 phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
304 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
305 RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
306 phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
307 return 0;
308}
309
310/* dl pga gain */
311enum {
312 DL_GAIN_8DB = 0,
313 DL_GAIN_0DB = 8,
314 DL_GAIN_N_1DB = 9,
315 DL_GAIN_N_10DB = 18,
316 DL_GAIN_N_40DB = 0x1f,
317};
318#define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
319#define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
320#define DL_GAIN_REG_MASK 0x0f9f
321
322static void lo_store_gain(struct mt6358_priv *priv)
323{
324 unsigned int reg;
325 unsigned int gain_l, gain_r;
326
327 regmap_read(priv->regmap, MT6358_ZCD_CON1, &reg);
328 gain_l = (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
329 gain_r = (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
330
331 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = gain_l;
332 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = gain_r;
333}
334
335static void hp_store_gain(struct mt6358_priv *priv)
336{
337 unsigned int reg;
338 unsigned int gain_l, gain_r;
339
340 regmap_read(priv->regmap, MT6358_ZCD_CON2, &reg);
341 gain_l = (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
342 gain_r = (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
343
344 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = gain_l;
345 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = gain_r;
346}
347
348static void hp_zcd_disable(struct mt6358_priv *priv)
349{
350 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000);
351}
352
353static void hp_main_output_ramp(struct mt6358_priv *priv, bool up)
354{
355 int i = 0, stage = 0;
356 int target = 7;
357
358 /* Enable/Reduce HPL/R main output stage step by step */
359 for (i = 0; i <= target; i++) {
360 stage = up ? i : target - i;
361 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
362 0x7 << 8, stage << 8);
363 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
364 0x7 << 11, stage << 11);
365 usleep_range(100, 150);
366 }
367}
368
369static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up)
370{
371 int i = 0, stage = 0;
372
373 /* Reduce HP aux feedback loop gain step by step */
374 for (i = 0; i <= 0xf; i++) {
375 stage = up ? i : 0xf - i;
376 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
377 0xf << 12, stage << 12);
378 usleep_range(100, 150);
379 }
380}
381
382static void hp_pull_down(struct mt6358_priv *priv, bool enable)
383{
384 int i;
385
386 if (enable) {
387 for (i = 0x0; i <= 0x6; i++) {
388 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
389 0x7, i);
390 udelay(600);
391 }
392 } else {
393 for (i = 0x6; i >= 0x1; i--) {
394 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
395 0x7, i);
396 udelay(600);
397 }
398 }
399}
400
401static bool is_valid_hp_pga_idx(int reg_idx)
402{
403 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) ||
404 reg_idx == DL_GAIN_N_40DB;
405}
406
407static void headset_volume_ramp(struct mt6358_priv *priv,
408 int from, int to)
409{
410 int offset = 0, count = 1, reg_idx;
411
412 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to))
413 dev_info(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
414 __func__, from, to);
415
416 dev_info(priv->dev, "%s(), from %d, to %d\n",
417 __func__, from, to);
418
419 if (to > from)
420 offset = to - from;
421 else
422 offset = from - to;
423
424 while (offset > 0) {
425 if (to > from)
426 reg_idx = from + count;
427 else
428 reg_idx = from - count;
429
430 if (is_valid_hp_pga_idx(reg_idx)) {
431 regmap_update_bits(priv->regmap,
432 MT6358_ZCD_CON2,
433 DL_GAIN_REG_MASK,
434 (reg_idx << 7) | reg_idx);
435 usleep_range(200, 300);
436 }
437 offset--;
438 count++;
439 }
440}
441
442static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
443static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
444
445static const struct snd_kcontrol_new mt6358_snd_controls[] = {
446 /* dl pga gain */
447 SOC_DOUBLE_TLV("Headphone Volume",
448 MT6358_ZCD_CON2, 0, 7, 0x12, 1,
449 playback_tlv),
450 SOC_DOUBLE_TLV("Lineout Volume",
451 MT6358_ZCD_CON1, 0, 7, 0x12, 1,
452 playback_tlv),
453 SOC_SINGLE_TLV("Handset Volume",
454 MT6358_ZCD_CON3, 0, 0x12, 1,
455 playback_tlv),
456 /* ul pga gain */
457 SOC_DOUBLE_R_TLV("PGA Volume",
458 MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1,
459 8, 4, 0,
460 pga_tlv),
461};
462
463/* MUX */
464/* LOL MUX */
465static const char * const lo_in_mux_map[] = {
466 "Open", "Mute", "Playback", "Test Mode"
467};
468
469static int lo_in_mux_map_value[] = {
470 0x0, 0x1, 0x2, 0x3,
471};
472
473static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
474 MT6358_AUDDEC_ANA_CON7,
475 RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
476 RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
477 lo_in_mux_map,
478 lo_in_mux_map_value);
479
480static const struct snd_kcontrol_new lo_in_mux_control =
481 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
482
483/*HP MUX */
484enum {
485 HP_MUX_OPEN = 0,
486 HP_MUX_HPSPK,
487 HP_MUX_HP,
488 HP_MUX_TEST_MODE,
489 HP_MUX_HP_IMPEDANCE,
490 HP_MUX_MASK = 0x7,
491};
492
493static const char * const hp_in_mux_map[] = {
494 "Open",
495 "LoudSPK Playback",
496 "Audio Playback",
497 "Test Mode",
498 "HP Impedance",
499 "undefined1",
500 "undefined2",
501 "undefined3",
502};
503
504static int hp_in_mux_map_value[] = {
505 HP_MUX_OPEN,
506 HP_MUX_HPSPK,
507 HP_MUX_HP,
508 HP_MUX_TEST_MODE,
509 HP_MUX_HP_IMPEDANCE,
510 HP_MUX_OPEN,
511 HP_MUX_OPEN,
512 HP_MUX_OPEN,
513};
514
515static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
516 SND_SOC_NOPM,
517 0,
518 HP_MUX_MASK,
519 hp_in_mux_map,
520 hp_in_mux_map_value);
521
522static const struct snd_kcontrol_new hpl_in_mux_control =
523 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
524
525static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
526 SND_SOC_NOPM,
527 0,
528 HP_MUX_MASK,
529 hp_in_mux_map,
530 hp_in_mux_map_value);
531
532static const struct snd_kcontrol_new hpr_in_mux_control =
533 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
534
535/* RCV MUX */
536enum {
537 RCV_MUX_OPEN = 0,
538 RCV_MUX_MUTE,
539 RCV_MUX_VOICE_PLAYBACK,
540 RCV_MUX_TEST_MODE,
541 RCV_MUX_MASK = 0x3,
542};
543
544static const char * const rcv_in_mux_map[] = {
545 "Open", "Mute", "Voice Playback", "Test Mode"
546};
547
548static int rcv_in_mux_map_value[] = {
549 RCV_MUX_OPEN,
550 RCV_MUX_MUTE,
551 RCV_MUX_VOICE_PLAYBACK,
552 RCV_MUX_TEST_MODE,
553};
554
555static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
556 SND_SOC_NOPM,
557 0,
558 RCV_MUX_MASK,
559 rcv_in_mux_map,
560 rcv_in_mux_map_value);
561
562static const struct snd_kcontrol_new rcv_in_mux_control =
563 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
564
565/* DAC In MUX */
566static const char * const dac_in_mux_map[] = {
567 "Normal Path", "Sgen"
568};
569
570static int dac_in_mux_map_value[] = {
571 0x0, 0x1,
572};
573
574static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
575 MT6358_AFE_TOP_CON0,
576 DL_SINE_ON_SFT,
577 DL_SINE_ON_MASK,
578 dac_in_mux_map,
579 dac_in_mux_map_value);
580
581static const struct snd_kcontrol_new dac_in_mux_control =
582 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
583
584/* AIF Out MUX */
585static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
586 MT6358_AFE_TOP_CON0,
587 UL_SINE_ON_SFT,
588 UL_SINE_ON_MASK,
589 dac_in_mux_map,
590 dac_in_mux_map_value);
591
592static const struct snd_kcontrol_new aif_out_mux_control =
593 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
594
595/* Mic Type MUX */
596enum {
597 MIC_TYPE_MUX_IDLE = 0,
598 MIC_TYPE_MUX_ACC,
599 MIC_TYPE_MUX_DMIC,
600 MIC_TYPE_MUX_DCC,
601 MIC_TYPE_MUX_DCC_ECM_DIFF,
602 MIC_TYPE_MUX_DCC_ECM_SINGLE,
603 MIC_TYPE_MUX_MASK = 0x7,
604};
605
606#define IS_DCC_BASE(x) (x == MIC_TYPE_MUX_DCC || \
607 x == MIC_TYPE_MUX_DCC_ECM_DIFF || \
608 x == MIC_TYPE_MUX_DCC_ECM_SINGLE)
609
610static const char * const mic_type_mux_map[] = {
611 "Idle",
612 "ACC",
613 "DMIC",
614 "DCC",
615 "DCC_ECM_DIFF",
616 "DCC_ECM_SINGLE",
617};
618
619static int mic_type_mux_map_value[] = {
620 MIC_TYPE_MUX_IDLE,
621 MIC_TYPE_MUX_ACC,
622 MIC_TYPE_MUX_DMIC,
623 MIC_TYPE_MUX_DCC,
624 MIC_TYPE_MUX_DCC_ECM_DIFF,
625 MIC_TYPE_MUX_DCC_ECM_SINGLE,
626};
627
628static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
629 SND_SOC_NOPM,
630 0,
631 MIC_TYPE_MUX_MASK,
632 mic_type_mux_map,
633 mic_type_mux_map_value);
634
635static const struct snd_kcontrol_new mic_type_mux_control =
636 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
637
638/* ADC L MUX */
639enum {
640 ADC_MUX_IDLE = 0,
641 ADC_MUX_AIN0,
642 ADC_MUX_PREAMPLIFIER,
643 ADC_MUX_IDLE1,
644 ADC_MUX_MASK = 0x3,
645};
646
647static const char * const adc_left_mux_map[] = {
648 "Idle", "AIN0", "Left Preamplifier", "Idle_1"
649};
650
651static int adc_mux_map_value[] = {
652 ADC_MUX_IDLE,
653 ADC_MUX_AIN0,
654 ADC_MUX_PREAMPLIFIER,
655 ADC_MUX_IDLE1,
656};
657
658static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
659 SND_SOC_NOPM,
660 0,
661 ADC_MUX_MASK,
662 adc_left_mux_map,
663 adc_mux_map_value);
664
665static const struct snd_kcontrol_new adc_left_mux_control =
666 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
667
668/* ADC R MUX */
669static const char * const adc_right_mux_map[] = {
670 "Idle", "AIN0", "Right Preamplifier", "Idle_1"
671};
672
673static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
674 SND_SOC_NOPM,
675 0,
676 ADC_MUX_MASK,
677 adc_right_mux_map,
678 adc_mux_map_value);
679
680static const struct snd_kcontrol_new adc_right_mux_control =
681 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
682
683/* PGA L MUX */
684enum {
685 PGA_MUX_NONE = 0,
686 PGA_MUX_AIN0,
687 PGA_MUX_AIN1,
688 PGA_MUX_AIN2,
689 PGA_MUX_MASK = 0x3,
690};
691
692static const char * const pga_mux_map[] = {
693 "None", "AIN0", "AIN1", "AIN2"
694};
695
696static int pga_mux_map_value[] = {
697 PGA_MUX_NONE,
698 PGA_MUX_AIN0,
699 PGA_MUX_AIN1,
700 PGA_MUX_AIN2,
701};
702
703static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
704 SND_SOC_NOPM,
705 0,
706 PGA_MUX_MASK,
707 pga_mux_map,
708 pga_mux_map_value);
709
710static const struct snd_kcontrol_new pga_left_mux_control =
711 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
712
713/* PGA R MUX */
714static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
715 SND_SOC_NOPM,
716 0,
717 PGA_MUX_MASK,
718 pga_mux_map,
719 pga_mux_map_value);
720
721static const struct snd_kcontrol_new pga_right_mux_control =
722 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
723
724static int mt_clksq_event(struct snd_soc_dapm_widget *w,
725 struct snd_kcontrol *kcontrol,
726 int event)
727{
728 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
729 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
730
731 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
732
733 switch (event) {
734 case SND_SOC_DAPM_PRE_PMU:
735 /* audio clk source from internal dcxo */
736 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
737 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
738 0x0);
739 break;
740 default:
741 break;
742 }
743
744 return 0;
745}
746
747static int mt_sgen_event(struct snd_soc_dapm_widget *w,
748 struct snd_kcontrol *kcontrol,
749 int event)
750{
751 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
752 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
753
754 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
755
756 switch (event) {
757 case SND_SOC_DAPM_PRE_PMU:
758 /* sdm audio fifo clock power on */
759 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
760 /* scrambler clock on enable */
761 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
762 /* sdm power on */
763 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
764 /* sdm fifo enable */
765 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
766
767 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0,
768 0xff3f,
769 0x0000);
770 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1,
771 0xffff,
772 0x0001);
773 break;
774 case SND_SOC_DAPM_POST_PMD:
775 /* DL scrambler disabling sequence */
776 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
777 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
778 break;
779 default:
780 break;
781 }
782
783 return 0;
784}
785
786static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
787 struct snd_kcontrol *kcontrol,
788 int event)
789{
790 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
791 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
792
793 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
794 __func__, event, priv->dl_rate);
795
796 switch (event) {
797 case SND_SOC_DAPM_PRE_PMU:
798 playback_gpio_set(priv);
799
800 /* sdm audio fifo clock power on */
801 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
802 /* scrambler clock on enable */
803 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
804 /* sdm power on */
805 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
806 /* sdm fifo enable */
807 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
808 break;
809 case SND_SOC_DAPM_POST_PMD:
810 /* DL scrambler disabling sequence */
811 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
812 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
813
814 playback_gpio_reset(priv);
815 break;
816 default:
817 break;
818 }
819
820 return 0;
821}
822
823static int mtk_hp_enable(struct mt6358_priv *priv)
824{
825 /* Pull-down HPL/R to AVSS28_AUD */
826 hp_pull_down(priv, true);
827 /* release HP CMFB gate rstb */
828 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
829 0x1 << 6, 0x1 << 6);
830
831 /* Reduce ESD resistance of AU_REFN */
832 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
833
834 /* save target gain to restore after hardware open complete */
835 hp_store_gain(priv);
836 /* Set HPR/HPL gain as minimum (~ -40dB) */
837 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG);
838
839 /* Turn on DA_600K_NCP_VA18 */
840 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
841 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
842 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
843 /* Toggle RG_DIVCKS_CHG */
844 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
845 /* Set NCP soft start mode as default mode: 100us */
846 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
847 /* Enable NCP */
848 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
849 usleep_range(250, 270);
850
851 /* Enable cap-less LDOs (1.5V) */
852 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
853 0x1055, 0x1055);
854 /* Enable NV regulator (-1.2V) */
855 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
856 usleep_range(100, 120);
857
858 /* Disable AUD_ZCD */
859 hp_zcd_disable(priv);
860
861 /* Disable headphone short-circuit protection */
862 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
863
864 /* Enable IBIST */
865 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
866
867 /* Set HP DR bias current optimization, 010: 6uA */
868 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
869 /* Set HP & ZCD bias current optimization */
870 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
871 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
872 /* Set HPP/N STB enhance circuits */
873 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
874
875 /* Enable HP aux output stage */
876 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c);
877 /* Enable HP aux feedback loop */
878 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c);
879 /* Enable HP aux CMFB loop */
880 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
881 /* Enable HP driver bias circuits */
882 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
883 /* Enable HP driver core circuits */
884 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
885 /* Short HP main output to HP aux output stage */
886 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc);
887
888 /* Enable HP main CMFB loop */
889 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
890 /* Disable HP aux CMFB loop */
891 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
892
893 /* Select CMFB resistor bulk to AC mode */
894 /* Selec HS/LO cap size (6.5pF default) */
895 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
896
897 /* Enable HP main output stage */
898 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff);
899 /* Enable HPR/L main output stage step by step */
900 hp_main_output_ramp(priv, true);
901
902 /* Reduce HP aux feedback loop gain */
903 hp_aux_feedback_loop_gain_ramp(priv, true);
904 /* Disable HP aux feedback loop */
905 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
906
907 /* apply volume setting */
908 headset_volume_ramp(priv,
909 DL_GAIN_N_10DB,
910 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
911
912 /* Disable HP aux output stage */
913 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
914 /* Unshort HP main output to HP aux output stage */
915 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03);
916 usleep_range(100, 120);
917
918 /* Enable AUD_CLK */
919 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
920 /* Enable Audio DAC */
921 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff);
922 /* Enable low-noise mode of DAC */
923 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201);
924 usleep_range(100, 120);
925
926 /* Switch HPL MUX to audio DAC */
927 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff);
928 /* Switch HPR MUX to audio DAC */
929 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff);
930
931 /* Disable Pull-down HPL/R to AVSS28_AUD */
932 hp_pull_down(priv, false);
933
934 return 0;
935}
936
937static int mtk_hp_disable(struct mt6358_priv *priv)
938{
939 /* Pull-down HPL/R to AVSS28_AUD */
940 hp_pull_down(priv, true);
941
942 /* HPR/HPL mux to open */
943 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
944 0x0f00, 0x0000);
945
946 /* Disable low-noise mode of DAC */
947 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
948 0x0001, 0x0000);
949
950 /* Disable Audio DAC */
951 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
952 0x000f, 0x0000);
953
954 /* Disable AUD_CLK */
955 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
956
957 /* Short HP main output to HP aux output stage */
958 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
959 /* Enable HP aux output stage */
960 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
961
962 /* decrease HPL/R gain to normal gain step by step */
963 headset_volume_ramp(priv,
964 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
965 DL_GAIN_N_40DB);
966
967 /* Enable HP aux feedback loop */
968 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
969
970 /* Reduce HP aux feedback loop gain */
971 hp_aux_feedback_loop_gain_ramp(priv, false);
972
973 /* decrease HPR/L main output stage step by step */
974 hp_main_output_ramp(priv, false);
975
976 /* Disable HP main output stage */
977 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
978
979 /* Enable HP aux CMFB loop */
980 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
981
982 /* Disable HP main CMFB loop */
983 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
984
985 /* Unshort HP main output to HP aux output stage */
986 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
987 0x3 << 6, 0x0);
988
989 /* Disable HP driver core circuits */
990 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
991 0x3 << 4, 0x0);
992
993 /* Disable HP driver bias circuits */
994 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
995 0x3 << 6, 0x0);
996
997 /* Disable HP aux CMFB loop */
998 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
999
1000 /* Disable HP aux feedback loop */
1001 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1002 0x3 << 4, 0x0);
1003
1004 /* Disable HP aux output stage */
1005 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1006 0x3 << 2, 0x0);
1007
1008 /* Disable IBIST */
1009 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1010 0x1 << 8, 0x1 << 8);
1011
1012 /* Disable NV regulator (-1.2V) */
1013 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1014 /* Disable cap-less LDOs (1.5V) */
1015 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1016 0x1055, 0x0);
1017 /* Disable NCP */
1018 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1019 0x1, 0x1);
1020
1021 /* Increase ESD resistance of AU_REFN */
1022 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2,
1023 0x1 << 14, 0x0);
1024
1025 /* Set HP CMFB gate rstb */
1026 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1027 0x1 << 6, 0x0);
1028 /* disable Pull-down HPL/R to AVSS28_AUD */
1029 hp_pull_down(priv, false);
1030
1031 return 0;
1032}
1033
1034static int mtk_hp_spk_enable(struct mt6358_priv *priv)
1035{
1036 /* Pull-down HPL/R to AVSS28_AUD */
1037 hp_pull_down(priv, true);
1038 /* release HP CMFB gate rstb */
1039 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1040 0x1 << 6, 0x1 << 6);
1041
1042 /* Reduce ESD resistance of AU_REFN */
1043 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1044
1045 /* save target gain to restore after hardware open complete */
1046 hp_store_gain(priv);
1047 /* Set HPR/HPL gain to -10dB */
1048 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG);
1049
1050 /* Turn on DA_600K_NCP_VA18 */
1051 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1052 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1053 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1054 /* Toggle RG_DIVCKS_CHG */
1055 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1056 /* Set NCP soft start mode as default mode: 100us */
1057 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1058 /* Enable NCP */
1059 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1060 usleep_range(250, 270);
1061
1062 /* Enable cap-less LDOs (1.5V) */
1063 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1064 0x1055, 0x1055);
1065 /* Enable NV regulator (-1.2V) */
1066 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1067 usleep_range(100, 120);
1068
1069 /* Disable AUD_ZCD */
1070 hp_zcd_disable(priv);
1071
1072 /* Disable headphone short-circuit protection */
1073 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
1074
1075 /* Enable IBIST */
1076 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1077
1078 /* Set HP DR bias current optimization, 010: 6uA */
1079 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1080 /* Set HP & ZCD bias current optimization */
1081 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1082 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1083 /* Set HPP/N STB enhance circuits */
1084 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
1085
1086 /* Disable Pull-down HPL/R to AVSS28_AUD */
1087 hp_pull_down(priv, false);
1088
1089 /* Enable HP driver bias circuits */
1090 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
1091 /* Enable HP driver core circuits */
1092 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
1093 /* Enable HP main CMFB loop */
1094 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
1095
1096 /* Select CMFB resistor bulk to AC mode */
1097 /* Selec HS/LO cap size (6.5pF default) */
1098 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1099
1100 /* Enable HP main output stage */
1101 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003);
1102 /* Enable HPR/L main output stage step by step */
1103 hp_main_output_ramp(priv, true);
1104
1105 /* Set LO gain as minimum (~ -40dB) */
1106 lo_store_gain(priv);
1107 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG);
1108 /* apply volume setting */
1109 headset_volume_ramp(priv,
1110 DL_GAIN_N_10DB,
1111 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1112
1113
1114 /* Set LO STB enhance circuits */
1115 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110);
1116 /* Enable LO driver bias circuits */
1117 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112);
1118 /* Enable LO driver core circuits */
1119 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113);
1120
1121 /* Set LOL gain to normal gain step by step */
1122 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1123 RG_AUDLOLGAIN_MASK_SFT,
1124 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] <<
1125 RG_AUDLOLGAIN_SFT);
1126 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1127 RG_AUDLORGAIN_MASK_SFT,
1128 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] <<
1129 RG_AUDLORGAIN_SFT);
1130
1131 /* Enable AUD_CLK */
1132 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
1133 /* Enable Audio DAC */
1134 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9);
1135 /* Enable low-noise mode of DAC */
1136 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201);
1137 /* Switch LOL MUX to audio DAC */
1138 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b);
1139 /* Switch HPL/R MUX to Line-out */
1140 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9);
1141
1142 return 0;
1143}
1144
1145
1146static int mtk_hp_spk_disable(struct mt6358_priv *priv)
1147{
1148 /* HPR/HPL mux to open */
1149 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1150 0x0f00, 0x0000);
1151 /* LOL mux to open */
1152 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1153 0x3 << 2, 0x0000);
1154
1155 /* Disable Audio DAC */
1156 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1157 0x000f, 0x0000);
1158
1159 /* Disable AUD_CLK */
1160 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1161
1162 /* decrease HPL/R gain to normal gain step by step */
1163 headset_volume_ramp(priv,
1164 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1165 DL_GAIN_N_40DB);
1166
1167 /* decrease LOL gain to minimum gain step by step */
1168 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1169 DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG);
1170
1171 /* decrease HPR/L main output stage step by step */
1172 hp_main_output_ramp(priv, false);
1173
1174 /* Disable HP main output stage */
1175 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1176
1177 /* Short HP main output to HP aux output stage */
1178 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1179 /* Enable HP aux output stage */
1180 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1181
1182 /* Enable HP aux feedback loop */
1183 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1184
1185 /* Reduce HP aux feedback loop gain */
1186 hp_aux_feedback_loop_gain_ramp(priv, false);
1187
1188 /* Disable HP driver core circuits */
1189 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1190 0x3 << 4, 0x0);
1191 /* Disable LO driver core circuits */
1192 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1193 0x1, 0x0);
1194
1195 /* Disable HP driver bias circuits */
1196 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1197 0x3 << 6, 0x0);
1198 /* Disable LO driver bias circuits */
1199 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1200 0x1 << 1, 0x0);
1201
1202 /* Disable HP aux CMFB loop */
1203 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1204 0xff << 8, 0x0000);
1205
1206 /* Disable IBIST */
1207 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1208 0x1 << 8, 0x1 << 8);
1209 /* Disable NV regulator (-1.2V) */
1210 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1211 /* Disable cap-less LDOs (1.5V) */
1212 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0);
1213 /* Disable NCP */
1214 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1);
1215
1216 /* Set HP CMFB gate rstb */
1217 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1218 0x1 << 6, 0x0);
1219 /* disable Pull-down HPL/R to AVSS28_AUD */
1220 hp_pull_down(priv, false);
1221
1222 return 0;
1223}
1224
1225static int mt_hp_event(struct snd_soc_dapm_widget *w,
1226 struct snd_kcontrol *kcontrol,
1227 int event)
1228{
1229 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1230 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1231 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1232 int device = DEVICE_HP;
1233
1234 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1235 __func__,
1236 event,
1237 priv->dev_counter[device],
1238 mux);
1239
1240 switch (event) {
1241 case SND_SOC_DAPM_PRE_PMU:
1242 priv->dev_counter[device]++;
1243 if (priv->dev_counter[device] > 1)
1244 break; /* already enabled, do nothing */
1245 else if (priv->dev_counter[device] <= 0)
1246 dev_info(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
1247 __func__,
1248 priv->dev_counter[device]);
1249
1250 priv->mux_select[MUX_HP_L] = mux;
1251
1252 if (mux == HP_MUX_HP)
1253 mtk_hp_enable(priv);
1254 else if (mux == HP_MUX_HPSPK)
1255 mtk_hp_spk_enable(priv);
1256 break;
1257 case SND_SOC_DAPM_PRE_PMD:
1258 priv->dev_counter[device]--;
1259 if (priv->dev_counter[device] > 0) {
1260 break; /* still being used, don't close */
1261 } else if (priv->dev_counter[device] < 0) {
1262 dev_info(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
1263 __func__,
1264 priv->dev_counter[device]);
1265 priv->dev_counter[device] = 0;
1266 break;
1267 }
1268
1269 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
1270 mtk_hp_disable(priv);
1271 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
1272 mtk_hp_spk_disable(priv);
1273
1274 priv->mux_select[MUX_HP_L] = mux;
1275 break;
1276 default:
1277 break;
1278 }
1279
1280 return 0;
1281}
1282
1283static int mt_rcv_event(struct snd_soc_dapm_widget *w,
1284 struct snd_kcontrol *kcontrol,
1285 int event)
1286{
1287 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1288 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1289
1290 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1291 __func__,
1292 event,
1293 dapm_kcontrol_get_value(w->kcontrols[0]));
1294
1295 switch (event) {
1296 case SND_SOC_DAPM_PRE_PMU:
1297 /* Reduce ESD resistance of AU_REFN */
1298 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1299
1300 /* Turn on DA_600K_NCP_VA18 */
1301 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1302 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1303 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1304 /* Toggle RG_DIVCKS_CHG */
1305 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1306 /* Set NCP soft start mode as default mode: 100us */
1307 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1308 /* Enable NCP */
1309 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1310 usleep_range(250, 270);
1311
1312 /* Enable cap-less LDOs (1.5V) */
1313 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1314 0x1055, 0x1055);
1315 /* Enable NV regulator (-1.2V) */
1316 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1317 usleep_range(100, 120);
1318
1319 /* Disable AUD_ZCD */
1320 hp_zcd_disable(priv);
1321
1322 /* Disable handset short-circuit protection */
1323 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010);
1324
1325 /* Enable IBIST */
1326 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1327 /* Set HP DR bias current optimization, 010: 6uA */
1328 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1329 /* Set HP & ZCD bias current optimization */
1330 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1331 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1332 /* Set HS STB enhance circuits */
1333 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090);
1334
1335 /* Disable HP main CMFB loop */
1336 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1337 /* Select CMFB resistor bulk to AC mode */
1338 /* Selec HS/LO cap size (6.5pF default) */
1339 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1340
1341 /* Enable HS driver bias circuits */
1342 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092);
1343 /* Enable HS driver core circuits */
1344 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093);
1345
1346 /* Enable AUD_CLK */
1347 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1348 0x1, 0x1);
1349
1350 /* Enable Audio DAC */
1351 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009);
1352 /* Enable low-noise mode of DAC */
1353 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001);
1354 /* Switch HS MUX to audio DAC */
1355 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b);
1356 break;
1357 case SND_SOC_DAPM_PRE_PMD:
1358 /* HS mux to open */
1359 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1360 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
1361 RCV_MUX_OPEN);
1362
1363 /* Disable Audio DAC */
1364 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1365 0x000f, 0x0000);
1366
1367 /* Disable AUD_CLK */
1368 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1369 0x1, 0x0);
1370
1371 /* decrease HS gain to minimum gain step by step */
1372 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB);
1373
1374 /* Disable HS driver core circuits */
1375 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1376 0x1, 0x0);
1377
1378 /* Disable HS driver bias circuits */
1379 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1380 0x1 << 1, 0x0000);
1381
1382 /* Disable HP aux CMFB loop */
1383 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1384 0xff << 8, 0x0);
1385
1386 /* Enable HP main CMFB Switch */
1387 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1388 0xff << 8, 0x2 << 8);
1389
1390 /* Disable IBIST */
1391 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1392 0x1 << 8, 0x1 << 8);
1393
1394 /* Disable NV regulator (-1.2V) */
1395 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15,
1396 0x1, 0x0);
1397 /* Disable cap-less LDOs (1.5V) */
1398 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1399 0x1055, 0x0);
1400 /* Disable NCP */
1401 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1402 0x1, 0x1);
1403 break;
1404 default:
1405 break;
1406 }
1407
1408 return 0;
1409}
1410
1411static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
1412 struct snd_kcontrol *kcontrol,
1413 int event)
1414{
1415 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1416 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1417
1418 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
1419 __func__, event, priv->ul_rate);
1420
1421 switch (event) {
1422 case SND_SOC_DAPM_PRE_PMU:
1423 capture_gpio_set(priv);
1424 break;
1425 case SND_SOC_DAPM_POST_PMD:
1426 capture_gpio_reset(priv);
1427 break;
1428 default:
1429 break;
1430 }
1431
1432 return 0;
1433}
1434
1435static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
1436 struct snd_kcontrol *kcontrol,
1437 int event)
1438{
1439 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1440 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1441
1442 dev_dbg(priv->dev, "%s(), event 0x%x\n",
1443 __func__, event);
1444
1445 switch (event) {
1446 case SND_SOC_DAPM_PRE_PMU:
1447 /* Enable audio ADC CLKGEN */
1448 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1449 0x1 << 5, 0x1 << 5);
1450 /* ADC CLK from CLKGEN (13MHz) */
1451 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3,
1452 0x0000);
1453 /* Enable LCLDO_ENC 1P8V */
1454 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1455 0x2500, 0x0100);
1456 /* LCLDO_ENC remote sense */
1457 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1458 0x2500, 0x2500);
1459 break;
1460 case SND_SOC_DAPM_POST_PMD:
1461 /* LCLDO_ENC remote sense off */
1462 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1463 0x2500, 0x0100);
1464 /* disable LCLDO_ENC 1P8V */
1465 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1466 0x2500, 0x0000);
1467
1468 /* ADC CLK from CLKGEN (13MHz) */
1469 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000);
1470 /* disable audio ADC CLKGEN */
1471 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1472 0x1 << 5, 0x0 << 5);
1473 break;
1474 default:
1475 break;
1476 }
1477
1478 return 0;
1479}
1480
1481static int mt6358_amic_enable(struct mt6358_priv *priv)
1482{
1483 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1484 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1485 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1486
1487 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1488 __func__, mic_type, mux_pga_l, mux_pga_r);
1489
1490 if (IS_DCC_BASE(mic_type)) {
1491 /* DCC 50k CLK (from 26M) */
1492 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1493 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1494 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1495 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061);
1496 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100);
1497 }
1498
1499 /* mic bias 0 */
1500 if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
1501 mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
1502 switch (mic_type) {
1503 case MIC_TYPE_MUX_DCC_ECM_DIFF:
1504 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1505 0xff00, 0x7700);
1506 break;
1507 case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1508 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1509 0xff00, 0x1100);
1510 break;
1511 default:
1512 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1513 0xff00, 0x0000);
1514 break;
1515 }
1516 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1517 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1518 0xff, 0x21);
1519 }
1520
1521 /* mic bias 1 */
1522 if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
1523 /* Enable MICBIAS1, MISBIAS1 = 2P6V */
1524 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
1525 regmap_write(priv->regmap,
1526 MT6358_AUDENC_ANA_CON10, 0x0161);
1527 else
1528 regmap_write(priv->regmap,
1529 MT6358_AUDENC_ANA_CON10, 0x0061);
1530 }
1531
1532 if (IS_DCC_BASE(mic_type)) {
1533 /* Audio L/R preamplifier DCC precharge */
1534 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1535 0xf8ff, 0x0004);
1536 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1537 0xf8ff, 0x0004);
1538 } else {
1539 /* reset reg */
1540 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1541 0xf8ff, 0x0000);
1542 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1543 0xf8ff, 0x0000);
1544 }
1545
1546 if (mux_pga_l != PGA_MUX_NONE) {
1547 /* L preamplifier input sel */
1548 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1549 RG_AUDPREAMPLINPUTSEL_MASK_SFT,
1550 mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);
1551
1552 /* L preamplifier enable */
1553 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1554 RG_AUDPREAMPLON_MASK_SFT,
1555 0x1 << RG_AUDPREAMPLON_SFT);
1556
1557 if (IS_DCC_BASE(mic_type)) {
1558 /* L preamplifier DCCEN */
1559 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1560 RG_AUDPREAMPLDCCEN_MASK_SFT,
1561 0x1 << RG_AUDPREAMPLDCCEN_SFT);
1562 }
1563
1564 /* L ADC input sel : L PGA. Enable audio L ADC */
1565 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1566 RG_AUDADCLINPUTSEL_MASK_SFT,
1567 ADC_MUX_PREAMPLIFIER <<
1568 RG_AUDADCLINPUTSEL_SFT);
1569 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1570 RG_AUDADCLPWRUP_MASK_SFT,
1571 0x1 << RG_AUDADCLPWRUP_SFT);
1572 }
1573
1574 if (mux_pga_r != PGA_MUX_NONE) {
1575 /* R preamplifier input sel */
1576 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1577 RG_AUDPREAMPRINPUTSEL_MASK_SFT,
1578 mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);
1579
1580 /* R preamplifier enable */
1581 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1582 RG_AUDPREAMPRON_MASK_SFT,
1583 0x1 << RG_AUDPREAMPRON_SFT);
1584
1585 if (IS_DCC_BASE(mic_type)) {
1586 /* R preamplifier DCCEN */
1587 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1588 RG_AUDPREAMPRDCCEN_MASK_SFT,
1589 0x1 << RG_AUDPREAMPRDCCEN_SFT);
1590 }
1591
1592 /* R ADC input sel : R PGA. Enable audio R ADC */
1593 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1594 RG_AUDADCRINPUTSEL_MASK_SFT,
1595 ADC_MUX_PREAMPLIFIER <<
1596 RG_AUDADCRINPUTSEL_SFT);
1597 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1598 RG_AUDADCRPWRUP_MASK_SFT,
1599 0x1 << RG_AUDADCRPWRUP_SFT);
1600 }
1601
1602 if (IS_DCC_BASE(mic_type)) {
1603 usleep_range(100, 150);
1604 /* Audio L preamplifier DCC precharge off */
1605 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1606 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0);
1607 /* Audio R preamplifier DCC precharge off */
1608 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1609 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0);
1610
1611 /* Short body to ground in PGA */
1612 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3,
1613 0x1 << 12, 0x0);
1614 }
1615
1616 /* here to set digital part */
1617 mt6358_mtkaif_tx_enable(priv);
1618
1619 /* UL dmic setting off */
1620 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000);
1621
1622 /* UL turn on */
1623 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001);
1624
1625 return 0;
1626}
1627
1628static void mt6358_amic_disable(struct mt6358_priv *priv)
1629{
1630 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1631 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1632 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1633
1634 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1635 __func__, mic_type, mux_pga_l, mux_pga_r);
1636
1637 /* UL turn off */
1638 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1639 0x0001, 0x0000);
1640
1641 /* disable aud_pad TX fifos */
1642 mt6358_mtkaif_tx_disable(priv);
1643
1644 /* L ADC input sel : off, disable L ADC */
1645 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1646 0xf000, 0x0000);
1647 /* L preamplifier DCCEN */
1648 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1649 0x1 << 1, 0x0);
1650 /* L preamplifier input sel : off, L PGA 0 dB gain */
1651 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1652 0xfffb, 0x0000);
1653
1654 /* disable L preamplifier DCC precharge */
1655 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1656 0x1 << 2, 0x0);
1657
1658 /* R ADC input sel : off, disable R ADC */
1659 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1660 0xf000, 0x0000);
1661 /* R preamplifier DCCEN */
1662 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1663 0x1 << 1, 0x0);
1664 /* R preamplifier input sel : off, R PGA 0 dB gain */
1665 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1666 0x0ffb, 0x0000);
1667
1668 /* disable R preamplifier DCC precharge */
1669 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1670 0x1 << 2, 0x0);
1671
1672 /* mic bias */
1673 /* Disable MICBIAS0, MISBIAS0 = 1P7V */
1674 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1675
1676 /* Disable MICBIAS1 */
1677 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1678 0x0001, 0x0000);
1679
1680 if (IS_DCC_BASE(mic_type)) {
1681 /* dcclk_gen_on=1'b0 */
1682 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1683 /* dcclk_pdn=1'b1 */
1684 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1685 /* dcclk_ref_ck_sel=2'b00 */
1686 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1687 /* dcclk_div=11'b00100000011 */
1688 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1689 }
1690}
1691
1692static int mt6358_dmic_enable(struct mt6358_priv *priv)
1693{
1694 dev_info(priv->dev, "%s()\n", __func__);
1695
1696 /* mic bias */
1697 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1698 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021);
1699
1700 /* RG_BANDGAPGEN=1'b0 */
1701 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1702 0x1 << 12, 0x0);
1703
1704 /* DMIC enable */
1705 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005);
1706
1707 /* here to set digital part */
1708 mt6358_mtkaif_tx_enable(priv);
1709
1710 /* UL dmic setting */
1711 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080);
1712
1713 /* UL turn on */
1714 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003);
1715 return 0;
1716}
1717
1718static void mt6358_dmic_disable(struct mt6358_priv *priv)
1719{
1720 dev_info(priv->dev, "%s()\n", __func__);
1721
1722 /* UL turn off */
1723 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1724 0x0003, 0x0000);
1725
1726 /* disable aud_pad TX fifos */
1727 mt6358_mtkaif_tx_disable(priv);
1728
1729 /* DMIC disable */
1730 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000);
1731
1732 /* mic bias */
1733 /* MISBIAS0 = 1P7V */
1734 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001);
1735
1736 /* RG_BANDGAPGEN=1'b0 */
1737 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1738 0x1 << 12, 0x0);
1739
1740 /* MICBIA0 disable */
1741 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1742}
1743
1744static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
1745 struct snd_kcontrol *kcontrol,
1746 int event)
1747{
1748 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1749 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1750 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1751
1752 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1753 __func__, event, mux);
1754
1755 switch (event) {
1756 case SND_SOC_DAPM_WILL_PMU:
1757 priv->mux_select[MUX_MIC_TYPE] = mux;
1758 break;
1759 case SND_SOC_DAPM_PRE_PMU:
1760 switch (mux) {
1761 case MIC_TYPE_MUX_DMIC:
1762 mt6358_dmic_enable(priv);
1763 break;
1764 default:
1765 mt6358_amic_enable(priv);
1766 break;
1767 }
1768
1769 break;
1770 case SND_SOC_DAPM_POST_PMD:
1771 switch (priv->mux_select[MUX_MIC_TYPE]) {
1772 case MIC_TYPE_MUX_DMIC:
1773 mt6358_dmic_disable(priv);
1774 break;
1775 default:
1776 mt6358_amic_disable(priv);
1777 break;
1778 }
1779
1780 priv->mux_select[MUX_MIC_TYPE] = mux;
1781 break;
1782 default:
1783 break;
1784 }
1785
1786 return 0;
1787}
1788
1789static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
1790 struct snd_kcontrol *kcontrol,
1791 int event)
1792{
1793 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1794 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1795 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1796
1797 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1798 __func__, event, mux);
1799
1800 priv->mux_select[MUX_ADC_L] = mux;
1801
1802 return 0;
1803}
1804
1805static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
1806 struct snd_kcontrol *kcontrol,
1807 int event)
1808{
1809 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1810 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1811 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1812
1813 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1814 __func__, event, mux);
1815
1816 priv->mux_select[MUX_ADC_R] = mux;
1817
1818 return 0;
1819}
1820
1821static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
1822 struct snd_kcontrol *kcontrol,
1823 int event)
1824{
1825 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1826 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1827 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1828
1829 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1830 __func__, event, mux);
1831
1832 priv->mux_select[MUX_PGA_L] = mux;
1833
1834 return 0;
1835}
1836
1837static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
1838 struct snd_kcontrol *kcontrol,
1839 int event)
1840{
1841 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1842 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1843 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1844
1845 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1846 __func__, event, mux);
1847
1848 priv->mux_select[MUX_PGA_R] = mux;
1849
1850 return 0;
1851}
1852
1853static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
1854 struct snd_kcontrol *kcontrol,
1855 int event)
1856{
1857 switch (event) {
1858 case SND_SOC_DAPM_POST_PMU:
1859 usleep_range(250, 270);
1860 break;
1861 case SND_SOC_DAPM_PRE_PMD:
1862 usleep_range(250, 270);
1863 break;
1864 default:
1865 break;
1866 }
1867
1868 return 0;
1869}
1870
1871/* DAPM Widgets */
1872static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = {
1873 /* Global Supply*/
1874 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
1875 MT6358_DCXO_CW14,
1876 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
1877 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
1878 MT6358_AUDDEC_ANA_CON13,
1879 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
1880 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
1881 MT6358_AUDENC_ANA_CON6,
1882 RG_CLKSQ_EN_SFT, 0,
1883 mt_clksq_event,
1884 SND_SOC_DAPM_PRE_PMU),
1885 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
1886 MT6358_AUD_TOP_CKPDN_CON0,
1887 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
1888 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
1889 MT6358_AUD_TOP_CKPDN_CON0,
1890 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
1891 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
1892 MT6358_AUD_TOP_CKPDN_CON0,
1893 RG_AUD_CK_PDN_SFT, 1,
1894 mt_delay_250_event,
1895 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1896 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
1897 MT6358_AUD_TOP_CKPDN_CON0,
1898 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
1899
1900 /* Digital Clock */
1901 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
1902 MT6358_AUDIO_TOP_CON0,
1903 PDN_AFE_CTL_SFT, 1,
1904 mt_delay_250_event,
1905 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1906 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
1907 MT6358_AUDIO_TOP_CON0,
1908 PDN_DAC_CTL_SFT, 1, NULL, 0),
1909 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
1910 MT6358_AUDIO_TOP_CON0,
1911 PDN_ADC_CTL_SFT, 1, NULL, 0),
1912 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
1913 MT6358_AUDIO_TOP_CON0,
1914 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
1915 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
1916 MT6358_AUDIO_TOP_CON0,
1917 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
1918 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
1919 MT6358_AUDIO_TOP_CON0,
1920 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
1921 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
1922 MT6358_AUDIO_TOP_CON0,
1923 PDN_RESERVED_SFT, 1, NULL, 0),
1924
1925 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
1926 0, 0, NULL, 0),
1927
1928 /* AFE ON */
1929 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
1930 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
1931 NULL, 0),
1932
1933 /* AIF Rx*/
1934 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
1935 MT6358_AFE_DL_SRC2_CON0_L,
1936 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
1937 mt_aif_in_event,
1938 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1939
1940 /* DL Supply */
1941 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
1942 0, 0, NULL, 0),
1943
1944 /* DAC */
1945 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
1946
1947 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
1948
1949 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
1950
1951 /* LOL */
1952 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
1953
1954 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7,
1955 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
1956
1957 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7,
1958 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
1959
1960 /* Headphone */
1961 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
1962 &hpl_in_mux_control,
1963 mt_hp_event,
1964 SND_SOC_DAPM_PRE_PMU |
1965 SND_SOC_DAPM_PRE_PMD),
1966
1967 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
1968 &hpr_in_mux_control,
1969 mt_hp_event,
1970 SND_SOC_DAPM_PRE_PMU |
1971 SND_SOC_DAPM_PRE_PMD),
1972
1973 /* Receiver */
1974 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
1975 &rcv_in_mux_control,
1976 mt_rcv_event,
1977 SND_SOC_DAPM_PRE_PMU |
1978 SND_SOC_DAPM_PRE_PMD),
1979
1980 /* Outputs */
1981 SND_SOC_DAPM_OUTPUT("Receiver"),
1982 SND_SOC_DAPM_OUTPUT("Headphone L"),
1983 SND_SOC_DAPM_OUTPUT("Headphone R"),
1984 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
1985 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
1986 SND_SOC_DAPM_OUTPUT("LINEOUT L"),
1987 SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
1988
1989 /* SGEN */
1990 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0,
1991 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
1992 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0,
1993 SGEN_MUTE_SW_CTL_SFT, 1,
1994 mt_sgen_event,
1995 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1996 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L,
1997 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
1998 /* tricky, same reg/bit as "AIF_RX", reconsider */
1999
2000 SND_SOC_DAPM_INPUT("SGEN DL"),
2001
2002 /* Uplinks */
2003 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2004 SND_SOC_NOPM, 0, 0,
2005 mt_aif_out_event,
2006 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2007
2008 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
2009 SND_SOC_NOPM, 0, 0,
2010 mt_adc_supply_event,
2011 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2012
2013 /* Uplinks MUX */
2014 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2015 &aif_out_mux_control),
2016
2017 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2018 &mic_type_mux_control,
2019 mt_mic_type_event,
2020 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
2021 SND_SOC_DAPM_WILL_PMU),
2022
2023 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2024 &adc_left_mux_control,
2025 mt_adc_l_event,
2026 SND_SOC_DAPM_WILL_PMU),
2027 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2028 &adc_right_mux_control,
2029 mt_adc_r_event,
2030 SND_SOC_DAPM_WILL_PMU),
2031
2032 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2033 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2034
2035 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2036 &pga_left_mux_control,
2037 mt_pga_left_event,
2038 SND_SOC_DAPM_WILL_PMU),
2039 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2040 &pga_right_mux_control,
2041 mt_pga_right_event,
2042 SND_SOC_DAPM_WILL_PMU),
2043
2044 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2045 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2046
2047 /* UL input */
2048 SND_SOC_DAPM_INPUT("AIN0"),
2049 SND_SOC_DAPM_INPUT("AIN1"),
2050 SND_SOC_DAPM_INPUT("AIN2"),
2051};
2052
2053static const struct snd_soc_dapm_route mt6358_dapm_routes[] = {
2054 /* Capture */
2055 {"AIF1TX", NULL, "AIF Out Mux"},
2056 {"AIF1TX", NULL, "CLK_BUF"},
2057 {"AIF1TX", NULL, "AUDGLB"},
2058 {"AIF1TX", NULL, "CLKSQ Audio"},
2059
2060 {"AIF1TX", NULL, "AUD_CK"},
2061 {"AIF1TX", NULL, "AUDIF_CK"},
2062
2063 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
2064 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
2065 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
2066 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
2067 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
2068
2069 {"AIF1TX", NULL, "AFE_ON"},
2070
2071 {"AIF Out Mux", NULL, "Mic Type Mux"},
2072
2073 {"Mic Type Mux", "ACC", "ADC L"},
2074 {"Mic Type Mux", "ACC", "ADC R"},
2075 {"Mic Type Mux", "DCC", "ADC L"},
2076 {"Mic Type Mux", "DCC", "ADC R"},
2077 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
2078 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
2079 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
2080 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
2081 {"Mic Type Mux", "DMIC", "AIN0"},
2082 {"Mic Type Mux", "DMIC", "AIN2"},
2083
2084 {"ADC L", NULL, "ADC L Mux"},
2085 {"ADC L", NULL, "ADC Supply"},
2086 {"ADC R", NULL, "ADC R Mux"},
2087 {"ADC R", NULL, "ADC Supply"},
2088
2089 {"ADC L Mux", "Left Preamplifier", "PGA L"},
2090
2091 {"ADC R Mux", "Right Preamplifier", "PGA R"},
2092
2093 {"PGA L", NULL, "PGA L Mux"},
2094 {"PGA R", NULL, "PGA R Mux"},
2095
2096 {"PGA L Mux", "AIN0", "AIN0"},
2097 {"PGA L Mux", "AIN1", "AIN1"},
2098 {"PGA L Mux", "AIN2", "AIN2"},
2099
2100 {"PGA R Mux", "AIN0", "AIN0"},
2101 {"PGA R Mux", "AIN1", "AIN1"},
2102 {"PGA R Mux", "AIN2", "AIN2"},
2103
2104 /* DL Supply */
2105 {"DL Power Supply", NULL, "CLK_BUF"},
2106 {"DL Power Supply", NULL, "AUDGLB"},
2107 {"DL Power Supply", NULL, "CLKSQ Audio"},
2108
2109 {"DL Power Supply", NULL, "AUDNCP_CK"},
2110 {"DL Power Supply", NULL, "ZCD13M_CK"},
2111 {"DL Power Supply", NULL, "AUD_CK"},
2112 {"DL Power Supply", NULL, "AUDIF_CK"},
2113
2114 /* DL Digital Supply */
2115 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
2116 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
2117 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
2118
2119 {"DL Digital Clock", NULL, "AFE_ON"},
2120
2121 {"AIF_RX", NULL, "DL Digital Clock"},
2122
2123 /* DL Path */
2124 {"DAC In Mux", "Normal Path", "AIF_RX"},
2125
2126 {"DAC In Mux", "Sgen", "SGEN DL"},
2127 {"SGEN DL", NULL, "SGEN DL SRC"},
2128 {"SGEN DL", NULL, "SGEN MUTE"},
2129 {"SGEN DL", NULL, "SGEN DL Enable"},
2130 {"SGEN DL", NULL, "DL Digital Clock"},
2131 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
2132
2133 {"DACL", NULL, "DAC In Mux"},
2134 {"DACL", NULL, "DL Power Supply"},
2135
2136 {"DACR", NULL, "DAC In Mux"},
2137 {"DACR", NULL, "DL Power Supply"},
2138
2139 /* Lineout Path */
2140 {"LOL Mux", "Playback", "DACL"},
2141
2142 {"LOL Buffer", NULL, "LOL Mux"},
2143 {"LOL Buffer", NULL, "LO Stability Enh"},
2144
2145 {"LINEOUT L", NULL, "LOL Buffer"},
2146
2147 /* Headphone Path */
2148 {"HPL Mux", "Audio Playback", "DACL"},
2149 {"HPR Mux", "Audio Playback", "DACR"},
2150 {"HPL Mux", "HP Impedance", "DACL"},
2151 {"HPR Mux", "HP Impedance", "DACR"},
2152 {"HPL Mux", "LoudSPK Playback", "DACL"},
2153 {"HPR Mux", "LoudSPK Playback", "DACR"},
2154
2155 {"Headphone L", NULL, "HPL Mux"},
2156 {"Headphone R", NULL, "HPR Mux"},
2157 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
2158 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
2159 {"LINEOUT L HSSPK", NULL, "HPL Mux"},
2160
2161 /* Receiver Path */
2162 {"RCV Mux", "Voice Playback", "DACL"},
2163 {"Receiver", NULL, "RCV Mux"},
2164};
2165
2166static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream,
2167 struct snd_pcm_hw_params *params,
2168 struct snd_soc_dai *dai)
2169{
2170 struct snd_soc_component *cmpnt = dai->component;
2171 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2172 unsigned int rate = params_rate(params);
2173
2174
2175 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
2176 __func__,
2177 substream->stream,
2178 rate,
2179 substream->number);
2180
2181 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2182 priv->dl_rate = rate;
2183 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2184 priv->ul_rate = rate;
2185
2186 return 0;
2187}
2188
2189static const struct snd_soc_dai_ops mt6358_codec_dai_ops = {
2190 .hw_params = mt6358_codec_dai_hw_params,
2191};
2192
2193#define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
2194 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
2195 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
2196 SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
2197 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
2198 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
2199
2200static struct snd_soc_dai_driver mt6358_dai_driver[] = {
2201 {
2202 .name = "mt6358-snd-codec-aif1",
2203 .playback = {
2204 .stream_name = "AIF1 Playback",
2205 .channels_min = 1,
2206 .channels_max = 2,
2207 .rates = SNDRV_PCM_RATE_8000_48000 |
2208 SNDRV_PCM_RATE_96000 |
2209 SNDRV_PCM_RATE_192000,
2210 .formats = MT6358_FORMATS,
2211 },
2212 .capture = {
2213 .stream_name = "AIF1 Capture",
2214 .channels_min = 1,
2215 .channels_max = 2,
2216 .rates = SNDRV_PCM_RATE_8000 |
2217 SNDRV_PCM_RATE_16000 |
2218 SNDRV_PCM_RATE_32000 |
2219 SNDRV_PCM_RATE_48000,
2220 .formats = MT6358_FORMATS,
2221 },
2222 .ops = &mt6358_codec_dai_ops,
2223 },
2224};
2225
2226static int mt6358_codec_init_reg(struct mt6358_priv *priv)
2227{
2228 int ret = 0;
2229
2230 /* Disable HeadphoneL/HeadphoneR short circuit protection */
2231 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2232 RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT,
2233 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT);
2234 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2235 RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT,
2236 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT);
2237 /* Disable voice short circuit protection */
2238 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
2239 RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
2240 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
2241 /* disable LO buffer left short circuit protection */
2242 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
2243 RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
2244 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);
2245
2246 /* gpio miso driving set to 4mA */
2247 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888);
2248
2249 /* set gpio */
2250 playback_gpio_reset(priv);
2251 capture_gpio_reset(priv);
2252
2253 return ret;
2254}
2255
2256static int mt6358_codec_probe(struct snd_soc_codec *codec)
2257{
2258 struct snd_soc_component *cmpnt = &codec->component;
2259 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2260
2261 snd_soc_component_init_regmap(cmpnt, priv->regmap);
2262
2263 mt6358_codec_init_reg(priv);
2264 pr_info("%s()\n", __func__);
2265 return 0;
2266}
2267
2268static struct snd_soc_codec_driver mt6358_soc_codec_driver = {
2269 .probe = mt6358_codec_probe,
2270 .component_driver = {
2271 .controls = mt6358_snd_controls,
2272 .num_controls = ARRAY_SIZE(mt6358_snd_controls),
2273 .dapm_widgets = mt6358_dapm_widgets,
2274 .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets),
2275 .dapm_routes = mt6358_dapm_routes,
2276 .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes),
2277 },
2278};
2279
2280static void debug_write_reg(struct file *file, void *arg)
2281{
2282 struct mt6358_priv *priv = file->private_data;
2283 char *token1 = NULL;
2284 char *token2 = NULL;
2285 char *temp = arg;
2286 char delim[] = " ,";
2287 unsigned int reg_addr = 0;
2288 unsigned int reg_value = 0;
2289 int ret = 0;
2290
2291 token1 = strsep(&temp, delim);
2292 token2 = strsep(&temp, delim);
2293 dev_info(priv->dev, "%s(), token1 = %s, token2 = %s, temp = %s\n",
2294 __func__, token1, token2, temp);
2295
2296 if ((token1 != NULL) && (token2 != NULL)) {
2297 ret = kstrtouint(token1, 16, &reg_addr);
2298 ret = kstrtouint(token2, 16, &reg_value);
2299 dev_info(priv->dev, "%s(), reg_addr = 0x%x, reg_value = 0x%x\n",
2300 __func__,
2301 reg_addr, reg_value);
2302 regmap_write(priv->regmap, reg_addr, reg_value);
2303 regmap_read(priv->regmap, reg_addr, &reg_value);
2304 dev_info(priv->dev, "%s(), reg_addr = 0x%x, reg_value = 0x%x\n",
2305 __func__,
2306 reg_addr, reg_value);
2307 } else {
2308 dev_info(priv->dev, "token1 or token2 is NULL!\n");
2309 }
2310}
2311
2312static void debug_set_debug_flag(struct file *file, void *arg)
2313{
2314 struct mt6358_priv *priv = file->private_data;
2315 char *token1 = NULL;
2316 char *temp = arg;
2317 char delim[] = " ,";
2318 int ret = 0;
2319 unsigned int value;
2320
2321 token1 = strsep(&temp, delim);
2322 dev_info(priv->dev, "%s(), token1 = %s, temp = %s\n",
2323 __func__, token1, temp);
2324
2325 if (token1 != NULL) {
2326 ret = kstrtouint(token1, 16, &value);
2327 priv->debug_flag = value;
2328 } else {
2329 dev_info(priv->dev, "%s(), token1 is NULL!\n", __func__);
2330 }
2331}
2332
2333struct command_function {
2334 const char *cmd;
2335 void (*fn)(struct file *, void *);
2336};
2337
2338#define CMD_FN(_cmd, _fn) { \
2339 .cmd = _cmd, \
2340 .fn = _fn, \
2341}
2342
2343static const struct command_function debug_cmds[] = {
2344 CMD_FN("write_reg", debug_write_reg),
2345 CMD_FN("set_debug_flag", debug_set_debug_flag),
2346 {}
2347};
2348
2349static int mt6358_debugfs_open(struct inode *inode, struct file *file)
2350{
2351 file->private_data = inode->i_private;
2352 return 0;
2353}
2354
2355static ssize_t mt6358_debugfs_read(struct file *file, char __user *buf,
2356 size_t count, loff_t *pos)
2357{
2358 struct mt6358_priv *priv = file->private_data;
2359 const int size = 12288;
2360 char *buffer = NULL; /* for reduce kernel stack */
2361 int n = 0;
2362 unsigned int value;
2363 int ret = 0;
2364
2365 buffer = kmalloc(size, GFP_KERNEL);
2366 if (!buffer)
2367 return -ENOMEM;
2368
2369 n += scnprintf(buffer + n, size - n, "mtkaif_protocol = %d\n",
2370 priv->mtkaif_protocol);
2371
2372 n += scnprintf(buffer + n, size - n, "debug_flag = 0x%x\n",
2373 priv->debug_flag);
2374
2375 regmap_read(priv->regmap, MT6358_DRV_CON3, &value);
2376 n += scnprintf(buffer + n, size - n,
2377 "MT6358_DRV_CON3 = 0x%x\n", value);
2378 regmap_read(priv->regmap, MT6358_GPIO_DIR0, &value);
2379 n += scnprintf(buffer + n, size - n,
2380 "MT6358_GPIO_DIR0 = 0x%x\n", value);
2381 regmap_read(priv->regmap, MT6358_GPIO_MODE2, &value);
2382 n += scnprintf(buffer + n, size - n,
2383 "MT6358_GPIO_MODE2 = 0x%x\n", value);
2384 regmap_read(priv->regmap, MT6358_GPIO_MODE3, &value);
2385 n += scnprintf(buffer + n, size - n,
2386 "MT6358_GPIO_MODE3 = 0x%x\n", value);
2387 regmap_read(priv->regmap, MT6358_TOP_CKPDN_CON0, &value);
2388 n += scnprintf(buffer + n, size - n,
2389 "MT6358_TOP_CKPDN_CON0 = 0x%x\n", value);
2390 regmap_read(priv->regmap, MT6358_TOP_CKHWEN_CON0, &value);
2391 n += scnprintf(buffer + n, size - n,
2392 "MT6358_TOP_CKHWEN_CON0 = 0x%x\n", value);
2393 regmap_read(priv->regmap, MT6358_DCXO_CW13, &value);
2394 n += scnprintf(buffer + n, size - n,
2395 "MT6358_DCXO_CW13 = 0x%x\n", value);
2396 regmap_read(priv->regmap, MT6358_DCXO_CW14, &value);
2397 n += scnprintf(buffer + n, size - n,
2398 "MT6358_DCXO_CW14 = 0x%x\n", value);
2399 regmap_read(priv->regmap, MT6358_AUXADC_CON10, &value);
2400 n += scnprintf(buffer + n, size - n,
2401 "MT6358_AUXADC_CON10 = 0x%x\n", value);
2402
2403 regmap_read(priv->regmap, MT6358_AUD_TOP_ID, &value);
2404 n += scnprintf(buffer + n, size - n,
2405 "MT6358_AUD_TOP_ID = 0x%x\n", value);
2406 regmap_read(priv->regmap, MT6358_AUD_TOP_REV0, &value);
2407 n += scnprintf(buffer + n, size - n,
2408 "MT6358_AUD_TOP_REV0 = 0x%x\n", value);
2409 regmap_read(priv->regmap, MT6358_AUD_TOP_DBI, &value);
2410 n += scnprintf(buffer + n, size - n,
2411 "MT6358_AUD_TOP_DBI = 0x%x\n", value);
2412 regmap_read(priv->regmap, MT6358_AUD_TOP_DXI, &value);
2413 n += scnprintf(buffer + n, size - n,
2414 "MT6358_AUD_TOP_DXI = 0x%x\n", value);
2415 regmap_read(priv->regmap, MT6358_AUD_TOP_CKPDN_TPM0, &value);
2416 n += scnprintf(buffer + n, size - n,
2417 "MT6358_AUD_TOP_CKPDN_TPM0 = 0x%x\n", value);
2418 regmap_read(priv->regmap, MT6358_AUD_TOP_CKPDN_TPM1, &value);
2419 n += scnprintf(buffer + n, size - n,
2420 "MT6358_AUD_TOP_CKPDN_TPM1 = 0x%x\n", value);
2421 regmap_read(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, &value);
2422 n += scnprintf(buffer + n, size - n,
2423 "MT6358_AUD_TOP_CKPDN_CON0 = 0x%x\n", value);
2424 regmap_read(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0_SET, &value);
2425 n += scnprintf(buffer + n, size - n,
2426 "MT6358_AUD_TOP_CKPDN_CON0_SET = 0x%x\n", value);
2427 regmap_read(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0_CLR, &value);
2428 n += scnprintf(buffer + n, size - n,
2429 "MT6358_AUD_TOP_CKPDN_CON0_CLR = 0x%x\n", value);
2430 regmap_read(priv->regmap, MT6358_AUD_TOP_CKSEL_CON0, &value);
2431 n += scnprintf(buffer + n, size - n,
2432 "MT6358_AUD_TOP_CKSEL_CON0 = 0x%x\n", value);
2433 regmap_read(priv->regmap, MT6358_AUD_TOP_CKSEL_CON0_SET, &value);
2434 n += scnprintf(buffer + n, size - n,
2435 "MT6358_AUD_TOP_CKSEL_CON0_SET = 0x%x\n", value);
2436 regmap_read(priv->regmap, MT6358_AUD_TOP_CKSEL_CON0_CLR, &value);
2437 n += scnprintf(buffer + n, size - n,
2438 "MT6358_AUD_TOP_CKSEL_CON0_CLR = 0x%x\n", value);
2439 regmap_read(priv->regmap, MT6358_AUD_TOP_CKTST_CON0, &value);
2440 n += scnprintf(buffer + n, size - n,
2441 "MT6358_AUD_TOP_CKTST_CON0 = 0x%x\n", value);
2442 regmap_read(priv->regmap, MT6358_AUD_TOP_CLK_HWEN_CON0, &value);
2443 n += scnprintf(buffer + n, size - n,
2444 "MT6358_AUD_TOP_CLK_HWEN_CON0 = 0x%x\n", value);
2445 regmap_read(priv->regmap, MT6358_AUD_TOP_CLK_HWEN_CON0_SET, &value);
2446 n += scnprintf(buffer + n, size - n,
2447 "MT6358_AUD_TOP_CLK_HWEN_CON0_SET = 0x%x\n", value);
2448 regmap_read(priv->regmap, MT6358_AUD_TOP_CLK_HWEN_CON0_CLR, &value);
2449 n += scnprintf(buffer + n, size - n,
2450 "MT6358_AUD_TOP_CLK_HWEN_CON0_CLR = 0x%x\n", value);
2451 regmap_read(priv->regmap, MT6358_AUD_TOP_RST_CON0, &value);
2452 n += scnprintf(buffer + n, size - n,
2453 "MT6358_AUD_TOP_RST_CON0 = 0x%x\n", value);
2454 regmap_read(priv->regmap, MT6358_AUD_TOP_RST_CON0_SET, &value);
2455 n += scnprintf(buffer + n, size - n,
2456 "MT6358_AUD_TOP_RST_CON0_SET = 0x%x\n", value);
2457 regmap_read(priv->regmap, MT6358_AUD_TOP_RST_CON0_CLR, &value);
2458 n += scnprintf(buffer + n, size - n,
2459 "MT6358_AUD_TOP_RST_CON0_CLR = 0x%x\n", value);
2460 regmap_read(priv->regmap, MT6358_AUD_TOP_RST_BANK_CON0, &value);
2461 n += scnprintf(buffer + n, size - n,
2462 "MT6358_AUD_TOP_RST_BANK_CON0 = 0x%x\n", value);
2463 regmap_read(priv->regmap, MT6358_AUD_TOP_INT_CON0, &value);
2464 n += scnprintf(buffer + n, size - n,
2465 "MT6358_AUD_TOP_INT_CON0 = 0x%x\n", value);
2466 regmap_read(priv->regmap, MT6358_AUD_TOP_INT_CON0_SET, &value);
2467 n += scnprintf(buffer + n, size - n,
2468 "MT6358_AUD_TOP_INT_CON0_SET = 0x%x\n", value);
2469 regmap_read(priv->regmap, MT6358_AUD_TOP_INT_CON0_CLR, &value);
2470 n += scnprintf(buffer + n, size - n,
2471 "MT6358_AUD_TOP_INT_CON0_CLR = 0x%x\n", value);
2472 regmap_read(priv->regmap, MT6358_AUD_TOP_INT_MASK_CON0, &value);
2473 n += scnprintf(buffer + n, size - n,
2474 "MT6358_AUD_TOP_INT_MASK_CON0 = 0x%x\n", value);
2475 regmap_read(priv->regmap, MT6358_AUD_TOP_INT_MASK_CON0_SET, &value);
2476 n += scnprintf(buffer + n, size - n,
2477 "MT6358_AUD_TOP_INT_MASK_CON0_SET = 0x%x\n", value);
2478 regmap_read(priv->regmap, MT6358_AUD_TOP_INT_MASK_CON0_CLR, &value);
2479 n += scnprintf(buffer + n, size - n,
2480 "MT6358_AUD_TOP_INT_MASK_CON0_CLR = 0x%x\n", value);
2481 regmap_read(priv->regmap, MT6358_AUD_TOP_INT_STATUS0, &value);
2482 n += scnprintf(buffer + n, size - n,
2483 "MT6358_AUD_TOP_INT_STATUS0 = 0x%x\n", value);
2484 regmap_read(priv->regmap, MT6358_AUD_TOP_INT_RAW_STATUS0, &value);
2485 n += scnprintf(buffer + n, size - n,
2486 "MT6358_AUD_TOP_INT_RAW_STATUS0 = 0x%x\n", value);
2487 regmap_read(priv->regmap, MT6358_AUD_TOP_INT_MISC_CON0, &value);
2488 n += scnprintf(buffer + n, size - n,
2489 "MT6358_AUD_TOP_INT_MISC_CON0 = 0x%x\n", value);
2490 regmap_read(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, &value);
2491 n += scnprintf(buffer + n, size - n,
2492 "MT6358_AUDNCP_CLKDIV_CON0 = 0x%x\n", value);
2493 regmap_read(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, &value);
2494 n += scnprintf(buffer + n, size - n,
2495 "MT6358_AUDNCP_CLKDIV_CON1 = 0x%x\n", value);
2496 regmap_read(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, &value);
2497 n += scnprintf(buffer + n, size - n,
2498 "MT6358_AUDNCP_CLKDIV_CON2 = 0x%x\n", value);
2499 regmap_read(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, &value);
2500 n += scnprintf(buffer + n, size - n,
2501 "MT6358_AUDNCP_CLKDIV_CON3 = 0x%x\n", value);
2502 regmap_read(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, &value);
2503 n += scnprintf(buffer + n, size - n,
2504 "MT6358_AUDNCP_CLKDIV_CON4 = 0x%x\n", value);
2505 regmap_read(priv->regmap, MT6358_AUD_TOP_MON_CON0, &value);
2506 n += scnprintf(buffer + n, size - n,
2507 "MT6358_AUD_TOP_MON_CON0 = 0x%x\n", value);
2508 regmap_read(priv->regmap, MT6358_AUDIO_DIG_DSN_ID, &value);
2509 n += scnprintf(buffer + n, size - n,
2510 "MT6358_AUDIO_DIG_DSN_ID = 0x%x\n", value);
2511 regmap_read(priv->regmap, MT6358_AUDIO_DIG_DSN_REV0, &value);
2512 n += scnprintf(buffer + n, size - n,
2513 "MT6358_AUDIO_DIG_DSN_REV0 = 0x%x\n", value);
2514 regmap_read(priv->regmap, MT6358_AUDIO_DIG_DSN_DBI, &value);
2515 n += scnprintf(buffer + n, size - n,
2516 "MT6358_AUDIO_DIG_DSN_DBI = 0x%x\n", value);
2517 regmap_read(priv->regmap, MT6358_AUDIO_DIG_DSN_DXI, &value);
2518 n += scnprintf(buffer + n, size - n,
2519 "MT6358_AUDIO_DIG_DSN_DXI = 0x%x\n", value);
2520 regmap_read(priv->regmap, MT6358_AFE_UL_DL_CON0, &value);
2521 n += scnprintf(buffer + n, size - n,
2522 "MT6358_AFE_UL_DL_CON0 = 0x%x\n", value);
2523 regmap_read(priv->regmap, MT6358_AFE_DL_SRC2_CON0_L, &value);
2524 n += scnprintf(buffer + n, size - n,
2525 "MT6358_AFE_DL_SRC2_CON0_L = 0x%x\n", value);
2526 regmap_read(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, &value);
2527 n += scnprintf(buffer + n, size - n,
2528 "MT6358_AFE_UL_SRC_CON0_H = 0x%x\n", value);
2529 regmap_read(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, &value);
2530 n += scnprintf(buffer + n, size - n,
2531 "MT6358_AFE_UL_SRC_CON0_L = 0x%x\n", value);
2532 regmap_read(priv->regmap, MT6358_AFE_TOP_CON0, &value);
2533 n += scnprintf(buffer + n, size - n,
2534 "MT6358_AFE_TOP_CON0 = 0x%x\n", value);
2535 regmap_read(priv->regmap, MT6358_AUDIO_TOP_CON0, &value);
2536 n += scnprintf(buffer + n, size - n,
2537 "MT6358_AUDIO_TOP_CON0 = 0x%x\n", value);
2538 regmap_read(priv->regmap, MT6358_AFE_MON_DEBUG0, &value);
2539 n += scnprintf(buffer + n, size - n,
2540 "MT6358_AFE_MON_DEBUG0 = 0x%x\n", value);
2541 regmap_read(priv->regmap, MT6358_AFUNC_AUD_CON0, &value);
2542 n += scnprintf(buffer + n, size - n,
2543 "MT6358_AFUNC_AUD_CON0 = 0x%x\n", value);
2544 regmap_read(priv->regmap, MT6358_AFUNC_AUD_CON1, &value);
2545 n += scnprintf(buffer + n, size - n,
2546 "MT6358_AFUNC_AUD_CON1 = 0x%x\n", value);
2547 regmap_read(priv->regmap, MT6358_AFUNC_AUD_CON2, &value);
2548 n += scnprintf(buffer + n, size - n,
2549 "MT6358_AFUNC_AUD_CON2 = 0x%x\n", value);
2550 regmap_read(priv->regmap, MT6358_AFUNC_AUD_CON3, &value);
2551 n += scnprintf(buffer + n, size - n,
2552 "MT6358_AFUNC_AUD_CON3 = 0x%x\n", value);
2553 regmap_read(priv->regmap, MT6358_AFUNC_AUD_CON4, &value);
2554 n += scnprintf(buffer + n, size - n,
2555 "MT6358_AFUNC_AUD_CON4 = 0x%x\n", value);
2556 regmap_read(priv->regmap, MT6358_AFUNC_AUD_CON5, &value);
2557 n += scnprintf(buffer + n, size - n,
2558 "MT6358_AFUNC_AUD_CON5 = 0x%x\n", value);
2559 regmap_read(priv->regmap, MT6358_AFUNC_AUD_CON6, &value);
2560 n += scnprintf(buffer + n, size - n,
2561 "MT6358_AFUNC_AUD_CON6 = 0x%x\n", value);
2562 regmap_read(priv->regmap, MT6358_AFUNC_AUD_MON0, &value);
2563 n += scnprintf(buffer + n, size - n,
2564 "MT6358_AFUNC_AUD_MON0 = 0x%x\n", value);
2565 regmap_read(priv->regmap, MT6358_AUDRC_TUNE_MON0, &value);
2566 n += scnprintf(buffer + n, size - n,
2567 "MT6358_AUDRC_TUNE_MON0 = 0x%x\n", value);
2568 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_FIFO_CFG0, &value);
2569 n += scnprintf(buffer + n, size - n,
2570 "MT6358_AFE_ADDA_MTKAIF_FIFO_CFG0 = 0x%x\n", value);
2571 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_FIFO_LOG_MON1, &value);
2572 n += scnprintf(buffer + n, size - n,
2573 "MT6358_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 = 0x%x\n", value);
2574 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_MON0, &value);
2575 n += scnprintf(buffer + n, size - n,
2576 "MT6358_AFE_ADDA_MTKAIF_MON0 = 0x%x\n", value);
2577 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_MON1, &value);
2578 n += scnprintf(buffer + n, size - n,
2579 "MT6358_AFE_ADDA_MTKAIF_MON1 = 0x%x\n", value);
2580 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_MON2, &value);
2581 n += scnprintf(buffer + n, size - n,
2582 "MT6358_AFE_ADDA_MTKAIF_MON2 = 0x%x\n", value);
2583 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_MON3, &value);
2584 n += scnprintf(buffer + n, size - n,
2585 "MT6358_AFE_ADDA_MTKAIF_MON3 = 0x%x\n", value);
2586 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_CFG0, &value);
2587 n += scnprintf(buffer + n, size - n,
2588 "MT6358_AFE_ADDA_MTKAIF_CFG0 = 0x%x\n", value);
2589 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_RX_CFG0, &value);
2590 n += scnprintf(buffer + n, size - n,
2591 "MT6358_AFE_ADDA_MTKAIF_RX_CFG0 = 0x%x\n", value);
2592 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_RX_CFG1, &value);
2593 n += scnprintf(buffer + n, size - n,
2594 "MT6358_AFE_ADDA_MTKAIF_RX_CFG1 = 0x%x\n", value);
2595 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_RX_CFG2, &value);
2596 n += scnprintf(buffer + n, size - n,
2597 "MT6358_AFE_ADDA_MTKAIF_RX_CFG2 = 0x%x\n", value);
2598 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_RX_CFG3, &value);
2599 n += scnprintf(buffer + n, size - n,
2600 "MT6358_AFE_ADDA_MTKAIF_RX_CFG3 = 0x%x\n", value);
2601 regmap_read(priv->regmap, MT6358_AFE_ADDA_MTKAIF_TX_CFG1, &value);
2602 n += scnprintf(buffer + n, size - n,
2603 "MT6358_AFE_ADDA_MTKAIF_TX_CFG1 = 0x%x\n", value);
2604 regmap_read(priv->regmap, MT6358_AFE_SGEN_CFG0, &value);
2605 n += scnprintf(buffer + n, size - n,
2606 "MT6358_AFE_SGEN_CFG0 = 0x%x\n", value);
2607 regmap_read(priv->regmap, MT6358_AFE_SGEN_CFG1, &value);
2608 n += scnprintf(buffer + n, size - n,
2609 "MT6358_AFE_SGEN_CFG1 = 0x%x\n", value);
2610 regmap_read(priv->regmap, MT6358_AFE_ADC_ASYNC_FIFO_CFG, &value);
2611 n += scnprintf(buffer + n, size - n,
2612 "MT6358_AFE_ADC_ASYNC_FIFO_CFG = 0x%x\n", value);
2613 regmap_read(priv->regmap, MT6358_AFE_DCCLK_CFG0, &value);
2614 n += scnprintf(buffer + n, size - n,
2615 "MT6358_AFE_DCCLK_CFG0 = 0x%x\n", value);
2616 regmap_read(priv->regmap, MT6358_AFE_DCCLK_CFG1, &value);
2617 n += scnprintf(buffer + n, size - n,
2618 "MT6358_AFE_DCCLK_CFG1 = 0x%x\n", value);
2619 regmap_read(priv->regmap, MT6358_AUDIO_DIG_CFG, &value);
2620 n += scnprintf(buffer + n, size - n,
2621 "MT6358_AUDIO_DIG_CFG = 0x%x\n", value);
2622 regmap_read(priv->regmap, MT6358_AFE_AUD_PAD_TOP, &value);
2623 n += scnprintf(buffer + n, size - n,
2624 "MT6358_AFE_AUD_PAD_TOP = 0x%x\n", value);
2625 regmap_read(priv->regmap, MT6358_AFE_AUD_PAD_TOP_MON, &value);
2626 n += scnprintf(buffer + n, size - n,
2627 "MT6358_AFE_AUD_PAD_TOP_MON = 0x%x\n", value);
2628 regmap_read(priv->regmap, MT6358_AFE_AUD_PAD_TOP_MON1, &value);
2629 n += scnprintf(buffer + n, size - n,
2630 "MT6358_AFE_AUD_PAD_TOP_MON1 = 0x%x\n", value);
2631 regmap_read(priv->regmap, MT6358_AFE_DL_NLE_CFG, &value);
2632 n += scnprintf(buffer + n, size - n,
2633 "MT6358_AFE_DL_NLE_CFG = 0x%x\n", value);
2634 regmap_read(priv->regmap, MT6358_AFE_DL_NLE_MON, &value);
2635 n += scnprintf(buffer + n, size - n,
2636 "MT6358_AFE_DL_NLE_MON = 0x%x\n", value);
2637 regmap_read(priv->regmap, MT6358_AFE_CG_EN_MON, &value);
2638 n += scnprintf(buffer + n, size - n,
2639 "MT6358_AFE_CG_EN_MON = 0x%x\n", value);
2640 regmap_read(priv->regmap, MT6358_AUDIO_DIG_2ND_DSN_ID, &value);
2641 n += scnprintf(buffer + n, size - n,
2642 "MT6358_AUDIO_DIG_2ND_DSN_ID = 0x%x\n", value);
2643 regmap_read(priv->regmap, MT6358_AUDIO_DIG_2ND_DSN_REV0, &value);
2644 n += scnprintf(buffer + n, size - n,
2645 "MT6358_AUDIO_DIG_2ND_DSN_REV0 = 0x%x\n", value);
2646 regmap_read(priv->regmap, MT6358_AUDIO_DIG_2ND_DSN_DBI, &value);
2647 n += scnprintf(buffer + n, size - n,
2648 "MT6358_AUDIO_DIG_2ND_DSN_DBI = 0x%x\n", value);
2649 regmap_read(priv->regmap, MT6358_AUDIO_DIG_2ND_DSN_DXI, &value);
2650 n += scnprintf(buffer + n, size - n,
2651 "MT6358_AUDIO_DIG_2ND_DSN_DXI = 0x%x\n", value);
2652 regmap_read(priv->regmap, MT6358_AFE_PMIC_NEWIF_CFG3, &value);
2653 n += scnprintf(buffer + n, size - n,
2654 "MT6358_AFE_PMIC_NEWIF_CFG3 = 0x%x\n", value);
2655 regmap_read(priv->regmap, MT6358_AFE_VOW_TOP, &value);
2656 n += scnprintf(buffer + n, size - n,
2657 "MT6358_AFE_VOW_TOP = 0x%x\n", value);
2658 regmap_read(priv->regmap, MT6358_AFE_VOW_CFG0, &value);
2659 n += scnprintf(buffer + n, size - n,
2660 "MT6358_AFE_VOW_CFG0 = 0x%x\n", value);
2661 regmap_read(priv->regmap, MT6358_AFE_VOW_CFG1, &value);
2662 n += scnprintf(buffer + n, size - n,
2663 "MT6358_AFE_VOW_CFG1 = 0x%x\n", value);
2664 regmap_read(priv->regmap, MT6358_AFE_VOW_CFG2, &value);
2665 n += scnprintf(buffer + n, size - n,
2666 "MT6358_AFE_VOW_CFG2 = 0x%x\n", value);
2667 regmap_read(priv->regmap, MT6358_AFE_VOW_CFG3, &value);
2668 n += scnprintf(buffer + n, size - n,
2669 "MT6358_AFE_VOW_CFG3 = 0x%x\n", value);
2670 regmap_read(priv->regmap, MT6358_AFE_VOW_CFG4, &value);
2671 n += scnprintf(buffer + n, size - n,
2672 "MT6358_AFE_VOW_CFG4 = 0x%x\n", value);
2673 regmap_read(priv->regmap, MT6358_AFE_VOW_CFG5, &value);
2674 n += scnprintf(buffer + n, size - n,
2675 "MT6358_AFE_VOW_CFG5 = 0x%x\n", value);
2676 regmap_read(priv->regmap, MT6358_AFE_VOW_CFG6, &value);
2677 n += scnprintf(buffer + n, size - n,
2678 "MT6358_AFE_VOW_CFG6 = 0x%x\n", value);
2679 regmap_read(priv->regmap, MT6358_AFE_VOW_MON0, &value);
2680 n += scnprintf(buffer + n, size - n,
2681 "MT6358_AFE_VOW_MON0 = 0x%x\n", value);
2682 regmap_read(priv->regmap, MT6358_AFE_VOW_MON1, &value);
2683 n += scnprintf(buffer + n, size - n,
2684 "MT6358_AFE_VOW_MON1 = 0x%x\n", value);
2685 regmap_read(priv->regmap, MT6358_AFE_VOW_MON2, &value);
2686 n += scnprintf(buffer + n, size - n,
2687 "MT6358_AFE_VOW_MON2 = 0x%x\n", value);
2688 regmap_read(priv->regmap, MT6358_AFE_VOW_MON3, &value);
2689 n += scnprintf(buffer + n, size - n,
2690 "MT6358_AFE_VOW_MON3 = 0x%x\n", value);
2691 regmap_read(priv->regmap, MT6358_AFE_VOW_MON4, &value);
2692 n += scnprintf(buffer + n, size - n,
2693 "MT6358_AFE_VOW_MON4 = 0x%x\n", value);
2694 regmap_read(priv->regmap, MT6358_AFE_VOW_MON5, &value);
2695 n += scnprintf(buffer + n, size - n,
2696 "MT6358_AFE_VOW_MON5 = 0x%x\n", value);
2697 regmap_read(priv->regmap, MT6358_AFE_VOW_SN_INI_CFG, &value);
2698 n += scnprintf(buffer + n, size - n,
2699 "MT6358_AFE_VOW_SN_INI_CFG = 0x%x\n", value);
2700 regmap_read(priv->regmap, MT6358_AFE_VOW_TGEN_CFG0, &value);
2701 n += scnprintf(buffer + n, size - n,
2702 "MT6358_AFE_VOW_TGEN_CFG0 = 0x%x\n", value);
2703 regmap_read(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, &value);
2704 n += scnprintf(buffer + n, size - n,
2705 "MT6358_AFE_VOW_POSDIV_CFG0 = 0x%x\n", value);
2706 regmap_read(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, &value);
2707 n += scnprintf(buffer + n, size - n,
2708 "MT6358_AFE_VOW_HPF_CFG0 = 0x%x\n", value);
2709 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG0, &value);
2710 n += scnprintf(buffer + n, size - n,
2711 "MT6358_AFE_VOW_PERIODIC_CFG0 = 0x%x\n", value);
2712 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG1, &value);
2713 n += scnprintf(buffer + n, size - n,
2714 "MT6358_AFE_VOW_PERIODIC_CFG1 = 0x%x\n", value);
2715 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG2, &value);
2716 n += scnprintf(buffer + n, size - n,
2717 "MT6358_AFE_VOW_PERIODIC_CFG2 = 0x%x\n", value);
2718 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG3, &value);
2719 n += scnprintf(buffer + n, size - n,
2720 "MT6358_AFE_VOW_PERIODIC_CFG3 = 0x%x\n", value);
2721 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG4, &value);
2722 n += scnprintf(buffer + n, size - n,
2723 "MT6358_AFE_VOW_PERIODIC_CFG4 = 0x%x\n", value);
2724 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG5, &value);
2725 n += scnprintf(buffer + n, size - n,
2726 "MT6358_AFE_VOW_PERIODIC_CFG5 = 0x%x\n", value);
2727 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG6, &value);
2728 n += scnprintf(buffer + n, size - n,
2729 "MT6358_AFE_VOW_PERIODIC_CFG6 = 0x%x\n", value);
2730 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG7, &value);
2731 n += scnprintf(buffer + n, size - n,
2732 "MT6358_AFE_VOW_PERIODIC_CFG7 = 0x%x\n", value);
2733 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG8, &value);
2734 n += scnprintf(buffer + n, size - n,
2735 "MT6358_AFE_VOW_PERIODIC_CFG8 = 0x%x\n", value);
2736 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG9, &value);
2737 n += scnprintf(buffer + n, size - n,
2738 "MT6358_AFE_VOW_PERIODIC_CFG9 = 0x%x\n", value);
2739 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG10, &value);
2740 n += scnprintf(buffer + n, size - n,
2741 "MT6358_AFE_VOW_PERIODIC_CFG10 = 0x%x\n", value);
2742 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG11, &value);
2743 n += scnprintf(buffer + n, size - n,
2744 "MT6358_AFE_VOW_PERIODIC_CFG11 = 0x%x\n", value);
2745 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG12, &value);
2746 n += scnprintf(buffer + n, size - n,
2747 "MT6358_AFE_VOW_PERIODIC_CFG12 = 0x%x\n", value);
2748 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG13, &value);
2749 n += scnprintf(buffer + n, size - n,
2750 "MT6358_AFE_VOW_PERIODIC_CFG13 = 0x%x\n", value);
2751 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG14, &value);
2752 n += scnprintf(buffer + n, size - n,
2753 "MT6358_AFE_VOW_PERIODIC_CFG14 = 0x%x\n", value);
2754 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG15, &value);
2755 n += scnprintf(buffer + n, size - n,
2756 "MT6358_AFE_VOW_PERIODIC_CFG15 = 0x%x\n", value);
2757 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG16, &value);
2758 n += scnprintf(buffer + n, size - n,
2759 "MT6358_AFE_VOW_PERIODIC_CFG16 = 0x%x\n", value);
2760 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG17, &value);
2761 n += scnprintf(buffer + n, size - n,
2762 "MT6358_AFE_VOW_PERIODIC_CFG17 = 0x%x\n", value);
2763 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG18, &value);
2764 n += scnprintf(buffer + n, size - n,
2765 "MT6358_AFE_VOW_PERIODIC_CFG18 = 0x%x\n", value);
2766 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG19, &value);
2767 n += scnprintf(buffer + n, size - n,
2768 "MT6358_AFE_VOW_PERIODIC_CFG19 = 0x%x\n", value);
2769 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG20, &value);
2770 n += scnprintf(buffer + n, size - n,
2771 "MT6358_AFE_VOW_PERIODIC_CFG20 = 0x%x\n", value);
2772 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG21, &value);
2773 n += scnprintf(buffer + n, size - n,
2774 "MT6358_AFE_VOW_PERIODIC_CFG21 = 0x%x\n", value);
2775 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG22, &value);
2776 n += scnprintf(buffer + n, size - n,
2777 "MT6358_AFE_VOW_PERIODIC_CFG22 = 0x%x\n", value);
2778 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_CFG23, &value);
2779 n += scnprintf(buffer + n, size - n,
2780 "MT6358_AFE_VOW_PERIODIC_CFG23 = 0x%x\n", value);
2781 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_MON0, &value);
2782 n += scnprintf(buffer + n, size - n,
2783 "MT6358_AFE_VOW_PERIODIC_MON0 = 0x%x\n", value);
2784 regmap_read(priv->regmap, MT6358_AFE_VOW_PERIODIC_MON1, &value);
2785 n += scnprintf(buffer + n, size - n,
2786 "MT6358_AFE_VOW_PERIODIC_MON1 = 0x%x\n", value);
2787 regmap_read(priv->regmap, MT6358_AUDENC_DSN_ID, &value);
2788 n += scnprintf(buffer + n, size - n,
2789 "MT6358_AUDENC_DSN_ID = 0x%x\n", value);
2790 regmap_read(priv->regmap, MT6358_AUDENC_DSN_REV0, &value);
2791 n += scnprintf(buffer + n, size - n,
2792 "MT6358_AUDENC_DSN_REV0 = 0x%x\n", value);
2793 regmap_read(priv->regmap, MT6358_AUDENC_DSN_DBI, &value);
2794 n += scnprintf(buffer + n, size - n,
2795 "MT6358_AUDENC_DSN_DBI = 0x%x\n", value);
2796 regmap_read(priv->regmap, MT6358_AUDENC_DSN_FPI, &value);
2797 n += scnprintf(buffer + n, size - n,
2798 "MT6358_AUDENC_DSN_FPI = 0x%x\n", value);
2799 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, &value);
2800 n += scnprintf(buffer + n, size - n,
2801 "MT6358_AUDENC_ANA_CON0 = 0x%x\n", value);
2802 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, &value);
2803 n += scnprintf(buffer + n, size - n,
2804 "MT6358_AUDENC_ANA_CON1 = 0x%x\n", value);
2805 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON2, &value);
2806 n += scnprintf(buffer + n, size - n,
2807 "MT6358_AUDENC_ANA_CON2 = 0x%x\n", value);
2808 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON3, &value);
2809 n += scnprintf(buffer + n, size - n,
2810 "MT6358_AUDENC_ANA_CON3 = 0x%x\n", value);
2811 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON4, &value);
2812 n += scnprintf(buffer + n, size - n,
2813 "MT6358_AUDENC_ANA_CON4 = 0x%x\n", value);
2814 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON5, &value);
2815 n += scnprintf(buffer + n, size - n,
2816 "MT6358_AUDENC_ANA_CON5 = 0x%x\n", value);
2817 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON6, &value);
2818 n += scnprintf(buffer + n, size - n,
2819 "MT6358_AUDENC_ANA_CON6 = 0x%x\n", value);
2820 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON7, &value);
2821 n += scnprintf(buffer + n, size - n,
2822 "MT6358_AUDENC_ANA_CON7 = 0x%x\n", value);
2823 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON8, &value);
2824 n += scnprintf(buffer + n, size - n,
2825 "MT6358_AUDENC_ANA_CON8 = 0x%x\n", value);
2826 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON9, &value);
2827 n += scnprintf(buffer + n, size - n,
2828 "MT6358_AUDENC_ANA_CON9 = 0x%x\n", value);
2829 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON10, &value);
2830 n += scnprintf(buffer + n, size - n,
2831 "MT6358_AUDENC_ANA_CON10 = 0x%x\n", value);
2832 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON11, &value);
2833 n += scnprintf(buffer + n, size - n,
2834 "MT6358_AUDENC_ANA_CON11 = 0x%x\n", value);
2835 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON12, &value);
2836 n += scnprintf(buffer + n, size - n,
2837 "MT6358_AUDENC_ANA_CON12 = 0x%x\n", value);
2838 regmap_read(priv->regmap, MT6358_AUDDEC_DSN_ID, &value);
2839 n += scnprintf(buffer + n, size - n,
2840 "MT6358_AUDDEC_DSN_ID = 0x%x\n", value);
2841 regmap_read(priv->regmap, MT6358_AUDDEC_DSN_REV0, &value);
2842 n += scnprintf(buffer + n, size - n,
2843 "MT6358_AUDDEC_DSN_REV0 = 0x%x\n", value);
2844 regmap_read(priv->regmap, MT6358_AUDDEC_DSN_DBI, &value);
2845 n += scnprintf(buffer + n, size - n,
2846 "MT6358_AUDDEC_DSN_DBI = 0x%x\n", value);
2847 regmap_read(priv->regmap, MT6358_AUDDEC_DSN_FPI, &value);
2848 n += scnprintf(buffer + n, size - n,
2849 "MT6358_AUDDEC_DSN_FPI = 0x%x\n", value);
2850 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON0, &value);
2851 n += scnprintf(buffer + n, size - n,
2852 "MT6358_AUDDEC_ANA_CON0 = 0x%x\n", value);
2853 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON1, &value);
2854 n += scnprintf(buffer + n, size - n,
2855 "MT6358_AUDDEC_ANA_CON1 = 0x%x\n", value);
2856 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON2, &value);
2857 n += scnprintf(buffer + n, size - n,
2858 "MT6358_AUDDEC_ANA_CON2 = 0x%x\n", value);
2859 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON3, &value);
2860 n += scnprintf(buffer + n, size - n,
2861 "MT6358_AUDDEC_ANA_CON3 = 0x%x\n", value);
2862 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON4, &value);
2863 n += scnprintf(buffer + n, size - n,
2864 "MT6358_AUDDEC_ANA_CON4 = 0x%x\n", value);
2865 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON5, &value);
2866 n += scnprintf(buffer + n, size - n,
2867 "MT6358_AUDDEC_ANA_CON5 = 0x%x\n", value);
2868 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON6, &value);
2869 n += scnprintf(buffer + n, size - n,
2870 "MT6358_AUDDEC_ANA_CON6 = 0x%x\n", value);
2871 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON7, &value);
2872 n += scnprintf(buffer + n, size - n,
2873 "MT6358_AUDDEC_ANA_CON7 = 0x%x\n", value);
2874 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON8, &value);
2875 n += scnprintf(buffer + n, size - n,
2876 "MT6358_AUDDEC_ANA_CON8 = 0x%x\n", value);
2877 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON9, &value);
2878 n += scnprintf(buffer + n, size - n,
2879 "MT6358_AUDDEC_ANA_CON9 = 0x%x\n", value);
2880 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON10, &value);
2881 n += scnprintf(buffer + n, size - n,
2882 "MT6358_AUDDEC_ANA_CON10 = 0x%x\n", value);
2883 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON11, &value);
2884 n += scnprintf(buffer + n, size - n,
2885 "MT6358_AUDDEC_ANA_CON11 = 0x%x\n", value);
2886 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON12, &value);
2887 n += scnprintf(buffer + n, size - n,
2888 "MT6358_AUDDEC_ANA_CON12 = 0x%x\n", value);
2889 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON13, &value);
2890 n += scnprintf(buffer + n, size - n,
2891 "MT6358_AUDDEC_ANA_CON13 = 0x%x\n", value);
2892 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON14, &value);
2893 n += scnprintf(buffer + n, size - n,
2894 "MT6358_AUDDEC_ANA_CON14 = 0x%x\n", value);
2895 regmap_read(priv->regmap, MT6358_AUDDEC_ANA_CON15, &value);
2896 n += scnprintf(buffer + n, size - n,
2897 "MT6358_AUDDEC_ANA_CON15 = 0x%x\n", value);
2898 regmap_read(priv->regmap, MT6358_AUDDEC_ELR_NUM, &value);
2899 n += scnprintf(buffer + n, size - n,
2900 "MT6358_AUDDEC_ELR_NUM = 0x%x\n", value);
2901 regmap_read(priv->regmap, MT6358_AUDDEC_ELR_0, &value);
2902 n += scnprintf(buffer + n, size - n,
2903 "MT6358_AUDDEC_ELR_0 = 0x%x\n", value);
2904 regmap_read(priv->regmap, MT6358_AUDZCD_DSN_ID, &value);
2905 n += scnprintf(buffer + n, size - n,
2906 "MT6358_AUDZCD_DSN_ID = 0x%x\n", value);
2907 regmap_read(priv->regmap, MT6358_AUDZCD_DSN_REV0, &value);
2908 n += scnprintf(buffer + n, size - n,
2909 "MT6358_AUDZCD_DSN_REV0 = 0x%x\n", value);
2910 regmap_read(priv->regmap, MT6358_AUDZCD_DSN_DBI, &value);
2911 n += scnprintf(buffer + n, size - n,
2912 "MT6358_AUDZCD_DSN_DBI = 0x%x\n", value);
2913 regmap_read(priv->regmap, MT6358_AUDZCD_DSN_FPI, &value);
2914 n += scnprintf(buffer + n, size - n,
2915 "MT6358_AUDZCD_DSN_FPI = 0x%x\n", value);
2916 regmap_read(priv->regmap, MT6358_ZCD_CON0, &value);
2917 n += scnprintf(buffer + n, size - n,
2918 "MT6358_ZCD_CON0 = 0x%x\n", value);
2919 regmap_read(priv->regmap, MT6358_ZCD_CON1, &value);
2920 n += scnprintf(buffer + n, size - n,
2921 "MT6358_ZCD_CON1 = 0x%x\n", value);
2922 regmap_read(priv->regmap, MT6358_ZCD_CON2, &value);
2923 n += scnprintf(buffer + n, size - n,
2924 "MT6358_ZCD_CON2 = 0x%x\n", value);
2925 regmap_read(priv->regmap, MT6358_ZCD_CON3, &value);
2926 n += scnprintf(buffer + n, size - n,
2927 "MT6358_ZCD_CON3 = 0x%x\n", value);
2928 regmap_read(priv->regmap, MT6358_ZCD_CON4, &value);
2929 n += scnprintf(buffer + n, size - n,
2930 "MT6358_ZCD_CON4 = 0x%x\n", value);
2931 regmap_read(priv->regmap, MT6358_ZCD_CON5, &value);
2932 n += scnprintf(buffer + n, size - n,
2933 "MT6358_ZCD_CON5 = 0x%x\n", value);
2934
2935 ret = simple_read_from_buffer(buf, count, pos, buffer, n);
2936 kfree(buffer);
2937 return ret;
2938}
2939
2940static ssize_t mt6358_debugfs_write(struct file *f, const char __user *buf,
2941 size_t count, loff_t *offset)
2942{
2943#define MAX_DEBUG_WRITE_INPUT 256
2944 struct mt6358_priv *priv = f->private_data;
2945 char input[MAX_DEBUG_WRITE_INPUT];
2946 char *temp = input;
2947 char *command = NULL;
2948 char delim[] = " ,\n";
2949 const struct command_function *cf;
2950
2951 memset((void *)input, 0, MAX_DEBUG_WRITE_INPUT);
2952
2953 if (count > MAX_DEBUG_WRITE_INPUT)
2954 count = MAX_DEBUG_WRITE_INPUT;
2955
2956 if (copy_from_user(input, buf, count))
2957 dev_info(priv->dev, "%s(), copy_from_user fail, count = %zu\n",
2958 __func__, count);
2959
2960 command = strsep(&temp, delim);
2961
2962 for (cf = debug_cmds; cf->cmd; cf++) {
2963 if (strcmp(cf->cmd, command) == 0) {
2964 cf->fn(f, temp);
2965 break;
2966 }
2967 }
2968
2969 return count;
2970}
2971
2972// TODO: remove debug fs
2973static const struct file_operations mt6358_debugfs_ops = {
2974 .open = mt6358_debugfs_open,
2975 .write = mt6358_debugfs_write,
2976 .read = mt6358_debugfs_read,
2977};
2978
2979static int mt6358_platform_driver_probe(struct platform_device *pdev)
2980{
2981 struct mt6358_priv *priv;
2982
2983 priv = devm_kzalloc(&pdev->dev,
2984 sizeof(struct mt6358_priv),
2985 GFP_KERNEL);
2986 dev_info(priv->dev, "+%s() ,dev_name %s mt6358_priv %p\n",
2987 __func__, dev_name(&pdev->dev), priv);
2988 if (priv == NULL)
2989 return -ENOMEM;
2990
2991 dev_set_drvdata(&pdev->dev, priv);
2992
2993 priv->dev = &pdev->dev;
2994
2995 priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
2996 dev_info(priv->dev, "%s() IS_ERR %d\n", __func__, IS_ERR(priv->regmap));
2997 if (IS_ERR(priv->regmap))
2998 return PTR_ERR(priv->regmap);
2999
3000 /* create debugfs file */
3001 priv->debugfs = debugfs_create_file("mtksocanaaudio",
3002 S_IFREG | 0444, NULL,
3003 priv, &mt6358_debugfs_ops);
3004
3005 dev_info(priv->dev, "%s(), dev name %s\n",
3006 __func__, dev_name(&pdev->dev));
3007
3008 return snd_soc_register_codec(&pdev->dev,
3009 &mt6358_soc_codec_driver,
3010 mt6358_dai_driver,
3011 ARRAY_SIZE(mt6358_dai_driver));
3012}
3013
3014static int mt6358_platform_driver_remove(struct platform_device *pdev)
3015{
3016 struct mt6358_priv *priv = dev_get_drvdata(&pdev->dev);
3017
3018 dev_info(&pdev->dev, "%s()\n", __func__);
3019
3020 debugfs_remove(priv->debugfs);
3021
3022 snd_soc_unregister_codec(&pdev->dev);
3023 return 0;
3024}
3025
3026static const struct of_device_id mt6358_of_match[] = {
3027 {.compatible = "mediatek,mt6358-sound",},
3028 {}
3029};
3030MODULE_DEVICE_TABLE(of, mt6358_of_match);
3031
3032static struct platform_driver mt6358_platform_driver = {
3033 .driver = {
3034 .name = "mt6358-sound",
3035 .of_match_table = mt6358_of_match,
3036 },
3037 .probe = mt6358_platform_driver_probe,
3038 .remove = mt6358_platform_driver_remove,
3039};
3040
3041module_platform_driver(mt6358_platform_driver)
3042
3043/* Module information */
3044MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver");
3045MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
3046MODULE_LICENSE("GPL v2");