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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / kernel / linux / v4.14 / sound / soc / codecs / mt6389.c
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rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2//
3// MT6389.c -- MT6389 ALSA SoC audio codec driver
4//
5// Copyright (c) 2018 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/platform_device.h>
9#include <linux/module.h>
10#include <linux/of_device.h>
11#include <linux/delay.h>
12#include <linux/debugfs.h>
13#include <linux/kthread.h>
14#include <linux/sched.h>
15
16#include <sound/soc.h>
17#ifndef CONFIG_MTK_PMIC_WRAP /* y: use regmap, else use legacy api */
18#ifdef CONFIG_MTK_PMIC_WRAP_HAL /* y: legacy api is defined */
19#include <mach/mtk_pmic_wrap.h>
20#endif
21#endif
22#ifdef CONFIG_MTK_PMIC_WRAP
23#include <linux/soc/mediatek/pmic_wrap.h>
24#endif
25#include <sound/tlv.h>
26
27#include "mt6389.h"
28
29enum {
30 AUDIO_ANALOG_VOLUME_HSOUTL,
31 AUDIO_ANALOG_VOLUME_HSOUTR,
32 AUDIO_ANALOG_VOLUME_HPOUTL,
33 AUDIO_ANALOG_VOLUME_HPOUTR,
34 AUDIO_ANALOG_VOLUME_LINEOUTL,
35 AUDIO_ANALOG_VOLUME_LINEOUTR,
36 AUDIO_ANALOG_VOLUME_MICAMP1,
37 AUDIO_ANALOG_VOLUME_MICAMP2,
38 AUDIO_ANALOG_VOLUME_TYPE_MAX
39};
40
41enum {
42 MUX_ADC_L,
43 MUX_ADC_R,
44 MUX_PGA_L,
45 MUX_PGA_R,
46 MUX_MIC_TYPE,
47 MUX_HP_L,
48 MUX_HP_R,
49 MUX_NUM,
50};
51
52enum {
53 DEVICE_HP,
54 DEVICE_LO,
55 DEVICE_RCV,
56 DEVICE_MIC1,
57 DEVICE_MIC2,
58 DEVICE_NUM
59};
60
61/* Supply widget subseq */
62enum {
63 /* common */
64 SUPPLY_SEQ_LDO_VAUD28,
65 SUPPLY_SEQ_AUD_GLB,
66 SUPPLY_SEQ_CLK_BUF,
67 SUPPLY_SEQ_CLKSQ,
68 SUPPLY_SEQ_VOW_AUD_LPW,
69 SUPPLY_SEQ_AUD_VOW,
70 SUPPLY_SEQ_VOW_CLK,
71 SUPPLY_SEQ_VOW_LDO,
72 SUPPLY_SEQ_TOP_CK,
73 SUPPLY_SEQ_TOP_CK_LAST,
74 SUPPLY_SEQ_AUD_TOP,
75 SUPPLY_SEQ_AUD_TOP_LAST,
76 SUPPLY_SEQ_AFE,
77 /* capture */
78 SUPPLY_SEQ_ADC_SUPPLY,
79};
80
81enum {
82 CH_L = 0,
83 CH_R,
84 NUM_CH,
85};
86
87#define REG_STRIDE 2
88
89struct mt6389_priv {
90 struct device *dev;
91 struct regmap *regmap;
92
93 unsigned int dl_rate;
94 unsigned int ul_rate;
95
96 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
97 unsigned int mux_select[MUX_NUM];
98
99 int dev_counter[DEVICE_NUM];
100
101 struct mt6389_codec_ops ops;
102 int mtkaif_protocol;
103
104 struct dentry *debugfs; // TODO: remove
105 unsigned int debug_flag;
106};
107
108int mt6389_set_codec_ops(struct snd_soc_component *cmpnt,
109 struct mt6389_codec_ops *ops)
110{
111 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
112
113 priv->ops.enable_dc_compensation = ops->enable_dc_compensation;
114 priv->ops.set_lch_dc_compensation = ops->set_lch_dc_compensation;
115 priv->ops.set_rch_dc_compensation = ops->set_rch_dc_compensation;
116 priv->ops.adda_dl_gain_control = ops->adda_dl_gain_control;
117 return 0;
118}
119int mt6389_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
120 int mtkaif_protocol)
121{
122 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
123
124 priv->mtkaif_protocol = mtkaif_protocol;
125 return 0;
126}
127
128static void gpio_smt_set(struct mt6389_priv *priv)
129{
130 /* set gpio SMT mode */
131 regmap_update_bits(priv->regmap, MT6389_SMT_CON1,
132 0x3ff0, 0x3ff0);
133}
134
135static void playback_gpio_set(struct mt6389_priv *priv)
136{
137 /* set gpio mosi mode */
138 regmap_update_bits(priv->regmap, MT6389_GPIO_MODE2_CLR,
139 0x01f8, 0x01f8);
140 regmap_update_bits(priv->regmap, MT6389_GPIO_MODE2_SET,
141 0xffff, 0x0249);
142 regmap_update_bits(priv->regmap, MT6389_GPIO_MODE2,
143 0xffff, 0x0249);
144}
145
146static void playback_gpio_reset(struct mt6389_priv *priv)
147{
148 /* set pad_aud_*_mosi to GPIO mode and dir input
149 * reason:
150 * pad_aud_dat_mosi*, because the pin is used as boot strap
151 * don't clean clk/sync, for mtkaif protocol 2
152 */
153 regmap_update_bits(priv->regmap, MT6389_GPIO_MODE2_CLR,
154 0x01f8, 0x01f8);
155 regmap_update_bits(priv->regmap, MT6389_GPIO_MODE2,
156 0x01f8, 0x0000);
157 regmap_update_bits(priv->regmap, MT6389_GPIO_DIR0,
158 0xf << 8, 0x0);
159}
160
161static void capture_gpio_set(struct mt6389_priv *priv)
162{
163 /* set gpio miso mode */
164 regmap_update_bits(priv->regmap, MT6389_GPIO_MODE3_CLR,
165 0xffff, 0xffff);
166 regmap_update_bits(priv->regmap, MT6389_GPIO_MODE3_SET,
167 0xffff, 0x0249);
168 regmap_update_bits(priv->regmap, MT6389_GPIO_MODE3,
169 0xffff, 0x0249);
170}
171
172static void capture_gpio_reset(struct mt6389_priv *priv)
173{
174 /* set pad_aud_*_miso to GPIO mode and dir input
175 * reason:
176 * pad_aud_clk_miso, because when playback only the miso_clk
177 * will also have 26m, so will have power leak
178 * pad_aud_dat_miso*, because the pin is used as boot strap
179 */
180 regmap_update_bits(priv->regmap, MT6389_GPIO_MODE3_CLR,
181 0xffff, 0xffff);
182 regmap_update_bits(priv->regmap, MT6389_GPIO_MODE3,
183 0xffff, 0x0000);
184 regmap_update_bits(priv->regmap, MT6389_GPIO_DIR0,
185 0xf << 12, 0x0);
186}
187
188/* use only when not govern by DAPM */
189static int mt6389_set_dcxo(struct mt6389_priv *priv, bool enable)
190{
191 regmap_update_bits(priv->regmap, MT6389_DCXO_CW12,
192 0x1 << RG_XO_AUDIO_EN_M_SFT,
193 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
194 return 0;
195}
196
197/* use only when not govern by DAPM */
198static int mt6389_set_clksq(struct mt6389_priv *priv, bool enable)
199{
200 /* Enable/disable CLKSQ 26MHz */
201 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
202 RG_CLKSQ_IN_SEL_MASK_SFT,
203 0 << RG_CLKSQ_IN_SEL_SFT);
204 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
205 RG_CLKSQ_EN_MASK_SFT,
206 enable << RG_CLKSQ_EN_SFT);
207
208 return 0;
209}
210
211/* use only when not govern by DAPM */
212static int mt6389_set_aud_global_bias(struct mt6389_priv *priv, bool enable)
213{
214 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
215 RG_AUDGLB_PWRDN_VA28_MASK_SFT,
216 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT);
217 return 0;
218}
219
220/* use only when not govern by DAPM */
221static int mt6389_set_topck(struct mt6389_priv *priv, bool enable)
222{
223 regmap_update_bits(priv->regmap, MT6389_AUD_TOP_CKPDN_CON0,
224 0x0066, enable ? 0x0 : 0x66);
225 return 0;
226}
227
228static int mt6389_mtkaif_tx_enable(struct mt6389_priv *priv)
229{
230 switch (priv->mtkaif_protocol) {
231 case MT6389_MTKAIF_PROTOCOL_2_CLK_P2:
232 /* MTKAIF TX format setting */
233 regmap_update_bits(priv->regmap,
234 MT6389_AFE_ADDA_MTKAIF_CFG0,
235 0xffff, 0x0010);
236 /* enable aud_pad TX fifos */
237 regmap_update_bits(priv->regmap,
238 MT6389_AFE_AUD_PAD_TOP,
239 0xff00, 0x3800);
240 regmap_update_bits(priv->regmap,
241 MT6389_AFE_AUD_PAD_TOP,
242 0xff00, 0x3900);
243 break;
244 case MT6389_MTKAIF_PROTOCOL_2:
245 /* MTKAIF TX format setting */
246 regmap_update_bits(priv->regmap,
247 MT6389_AFE_ADDA_MTKAIF_CFG0,
248 0xffff, 0x0010);
249 /* enable aud_pad TX fifos */
250 regmap_update_bits(priv->regmap,
251 MT6389_AFE_AUD_PAD_TOP,
252 0xff00, 0x3100);
253 break;
254 case MT6389_MTKAIF_PROTOCOL_1:
255 default:
256 /* MTKAIF TX format setting */
257 regmap_update_bits(priv->regmap,
258 MT6389_AFE_ADDA_MTKAIF_CFG0,
259 0xff00, 0x0000);
260 /* enable aud_pad TX fifos */
261 regmap_update_bits(priv->regmap,
262 MT6389_AFE_AUD_PAD_TOP,
263 0xff00, 0x3100);
264 break;
265 }
266 return 0;
267}
268
269static int mt6389_mtkaif_tx_disable(struct mt6389_priv *priv)
270{
271 /* disable aud_pad TX fifos */
272 regmap_update_bits(priv->regmap, MT6389_AFE_AUD_PAD_TOP,
273 0xff00, 0x3000);
274 return 0;
275}
276
277int mt6389_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
278{
279 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
280
281 playback_gpio_set(priv);
282 capture_gpio_set(priv);
283 mt6389_mtkaif_tx_enable(priv);
284
285 mt6389_set_dcxo(priv, true);
286 mt6389_set_aud_global_bias(priv, true);
287 mt6389_set_clksq(priv, true);
288 mt6389_set_topck(priv, true);
289 /* no use in Mt6389 */
290 return 0;
291}
292
293int mt6389_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
294{
295 /* no use in Mt6389 */
296 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
297
298 mt6389_set_topck(priv, false);
299 mt6389_set_clksq(priv, false);
300 mt6389_set_aud_global_bias(priv, false);
301 mt6389_set_dcxo(priv, false);
302
303 mt6389_mtkaif_tx_disable(priv);
304 playback_gpio_reset(priv);
305 capture_gpio_reset(priv);
306 return 0;
307}
308
309/* dl pga gain */
310enum {
311 DL_GAIN_8DB = 0,
312 DL_GAIN_0DB = 8,
313 DL_GAIN_N_1DB = 9,
314 DL_GAIN_N_10DB = 18,
315 DL_GAIN_N_40DB = 0x1f,
316};
317#define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
318#define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
319#define DL_GAIN_REG_MASK 0x0f9f
320
321/* reg idx for -40dB*/
322#define PGA_MINUS_40_DB_REG_VAL 0x1f
323#define HP_PGA_MINUS_40_DB_REG_VAL 0x3f
324static const char *const dl_pga_gain[] = {
325 "8Db", "7Db", "6Db", "5Db", "4Db",
326 "3Db", "2Db", "1Db", "0Db", "-1Db",
327 "-2Db", "-3Db", "-4Db", "-5Db", "-6Db",
328 "-7Db", "-8Db", "-9Db", "-10Db", "-40Db"
329};
330
331static void hp_zcd_disable(struct mt6389_priv *priv)
332{
333 regmap_write(priv->regmap, MT6389_ZCD_CON0, 0x0000);
334}
335
336static int dl_pga_get(struct snd_kcontrol *kcontrol,
337 struct snd_ctl_elem_value *ucontrol)
338{
339 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
340 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
341 unsigned int id = kcontrol->id.device;
342 int array_size, reg_minus_40db;
343
344 array_size = ARRAY_SIZE(dl_pga_gain);
345 reg_minus_40db = PGA_MINUS_40_DB_REG_VAL;
346
347 ucontrol->value.integer.value[0] = priv->ana_gain[id];
348
349 if (ucontrol->value.integer.value[0] == reg_minus_40db)
350 ucontrol->value.integer.value[0] = array_size - 1;
351
352 return 0;
353}
354
355static int dl_pga_set(struct snd_kcontrol *kcontrol,
356 struct snd_ctl_elem_value *ucontrol)
357{
358 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
359 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
360 int index = ucontrol->value.integer.value[0];
361 unsigned int id = kcontrol->id.device;
362 int array_size, reg_minus_40db;
363
364 dev_info(priv->dev, "%s(), id %d, index %d\n", __func__, id, index);
365
366 array_size = ARRAY_SIZE(dl_pga_gain);
367 reg_minus_40db = PGA_MINUS_40_DB_REG_VAL;
368
369 if (index >= array_size) {
370 dev_warn(priv->dev, "return -EINVAL\n");
371 return -EINVAL;
372 }
373
374 if (index == (array_size - 1))
375 index = reg_minus_40db; /* reg idx for -40dB*/
376
377 switch (id) {
378 case AUDIO_ANALOG_VOLUME_HPOUTL:
379 regmap_update_bits(priv->regmap, MT6389_ZCD_CON2,
380 RG_AUDHPLGAIN_MASK_SFT,
381 index << RG_AUDHPLGAIN_SFT);
382 break;
383 case AUDIO_ANALOG_VOLUME_HPOUTR:
384 regmap_update_bits(priv->regmap, MT6389_ZCD_CON2,
385 RG_AUDHPRGAIN_MASK_SFT,
386 index << RG_AUDHPRGAIN_SFT);
387 break;
388 case AUDIO_ANALOG_VOLUME_HSOUTL:
389 regmap_update_bits(priv->regmap, MT6389_ZCD_CON3,
390 RG_AUDHSGAIN_MASK_SFT,
391 index << RG_AUDHSGAIN_SFT);
392 break;
393 case AUDIO_ANALOG_VOLUME_LINEOUTL:
394 regmap_update_bits(priv->regmap, MT6389_ZCD_CON1,
395 RG_AUDLOLGAIN_MASK_SFT,
396 index << RG_AUDLOLGAIN_SFT);
397 break;
398 case AUDIO_ANALOG_VOLUME_LINEOUTR:
399 regmap_update_bits(priv->regmap, MT6389_ZCD_CON1,
400 RG_AUDLORGAIN_MASK_SFT,
401 index << RG_AUDLORGAIN_SFT);
402 break;
403 default:
404 return 0;
405 }
406
407 priv->ana_gain[id] = index;
408 return 0;
409}
410
411static const struct soc_enum dl_pga_enum[] = {
412 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dl_pga_gain), dl_pga_gain),
413};
414
415#define MT_SOC_ENUM_EXT_ID(xname, xenum, xhandler_get, xhandler_put, id) \
416{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .device = id,\
417 .info = snd_soc_info_enum_double, \
418 .get = xhandler_get, .put = xhandler_put, \
419 .private_value = (unsigned long)&xenum }
420
421static const struct snd_kcontrol_new mt6389_snd_controls[] = {
422 MT_SOC_ENUM_EXT_ID("Headset_PGAL_GAIN", dl_pga_enum[0],
423 dl_pga_get, dl_pga_set,
424 AUDIO_ANALOG_VOLUME_HPOUTL),
425 MT_SOC_ENUM_EXT_ID("Headset_PGAR_GAIN", dl_pga_enum[0],
426 dl_pga_get, dl_pga_set,
427 AUDIO_ANALOG_VOLUME_HPOUTR),
428 MT_SOC_ENUM_EXT_ID("Handset_PGA_GAIN", dl_pga_enum[0],
429 dl_pga_get, dl_pga_set,
430 AUDIO_ANALOG_VOLUME_HSOUTL),
431 MT_SOC_ENUM_EXT_ID("Lineout_PGAL_GAIN", dl_pga_enum[0],
432 dl_pga_get, dl_pga_set,
433 AUDIO_ANALOG_VOLUME_LINEOUTL),
434 MT_SOC_ENUM_EXT_ID("Lineout_PGAR_GAIN", dl_pga_enum[0],
435 dl_pga_get, dl_pga_set,
436 AUDIO_ANALOG_VOLUME_LINEOUTR),
437};
438
439/* ul pga gain */
440static const char *const ul_pga_gain[] = {
441 "0Db", "6Db", "12Db", "18Db", "24Db"
442};
443
444static const struct soc_enum ul_pga_enum[] = {
445 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ul_pga_gain), ul_pga_gain),
446};
447
448static int ul_pga_get(struct snd_kcontrol *kcontrol,
449 struct snd_ctl_elem_value *ucontrol)
450{
451 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
452 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
453
454 ucontrol->value.integer.value[0] =
455 priv->ana_gain[kcontrol->id.device];
456 return 0;
457}
458
459static int ul_pga_set(struct snd_kcontrol *kcontrol,
460 struct snd_ctl_elem_value *ucontrol)
461{
462 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
463 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
464 int index = ucontrol->value.integer.value[0];
465 unsigned int id = kcontrol->id.device;
466
467 dev_info(priv->dev, "%s(), id %d, index %d\n", __func__, id, index);
468 if (index > ARRAY_SIZE(ul_pga_gain)) {
469 dev_warn(priv->dev, "return -EINVAL\n");
470 return -EINVAL;
471 }
472
473 switch (id) {
474 case AUDIO_ANALOG_VOLUME_MICAMP1:
475 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
476 RG_AUDPREAMPLGAIN_MASK_SFT,
477 index << RG_AUDPREAMPLGAIN_SFT);
478 break;
479 case AUDIO_ANALOG_VOLUME_MICAMP2:
480 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
481 RG_AUDPREAMPRGAIN_MASK_SFT,
482 index << RG_AUDPREAMPRGAIN_SFT);
483 break;
484 default:
485 return 0;
486 }
487
488 priv->ana_gain[id] = index;
489 return 0;
490}
491
492static const struct snd_kcontrol_new mt6389_snd_ul_controls[] = {
493 MT_SOC_ENUM_EXT_ID("Audio_PGA1_Setting", ul_pga_enum[0],
494 ul_pga_get, ul_pga_set,
495 AUDIO_ANALOG_VOLUME_MICAMP1),
496 MT_SOC_ENUM_EXT_ID("Audio_PGA2_Setting", ul_pga_enum[0],
497 ul_pga_get, ul_pga_set,
498 AUDIO_ANALOG_VOLUME_MICAMP2),
499};
500/* MUX */
501/* LOL MUX */
502static const char * const lo_in_mux_map[] = {
503 "Open", "Mute", "Playback", "Test Mode"
504};
505
506static int lo_in_mux_map_value[] = {
507 0x0, 0x1, 0x2, 0x3,
508};
509
510static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
511 MT6389_AUDDEC_ANA_CON5,
512 RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
513 RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
514 lo_in_mux_map,
515 lo_in_mux_map_value);
516
517static const struct snd_kcontrol_new lo_in_mux_control =
518 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
519
520/*HP MUX */
521enum {
522 HP_MUX_OPEN = 0,
523 HP_MUX_HPSPK,
524 HP_MUX_HP,
525 HP_MUX_TEST_MODE,
526 HP_MUX_HP_IMPEDANCE,
527 HP_MUX_MASK = 0x7,
528};
529
530static const char * const hp_in_mux_map[] = {
531 "Open",
532 "LoudSPK Playback",
533 "Audio Playback",
534 "Test Mode",
535 "HP Impedance",
536 "undefined1",
537 "undefined2",
538 "undefined3",
539};
540
541static int hp_in_mux_map_value[] = {
542 HP_MUX_OPEN,
543 HP_MUX_HPSPK,
544 HP_MUX_HP,
545 HP_MUX_TEST_MODE,
546 HP_MUX_HP_IMPEDANCE,
547 HP_MUX_OPEN,
548 HP_MUX_OPEN,
549 HP_MUX_OPEN,
550};
551
552static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
553 SND_SOC_NOPM,
554 0,
555 HP_MUX_MASK,
556 hp_in_mux_map,
557 hp_in_mux_map_value);
558
559static const struct snd_kcontrol_new hpl_in_mux_control =
560 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
561
562static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
563 SND_SOC_NOPM,
564 0,
565 HP_MUX_MASK,
566 hp_in_mux_map,
567 hp_in_mux_map_value);
568
569static const struct snd_kcontrol_new hpr_in_mux_control =
570 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
571
572/* RCV MUX */
573enum {
574 RCV_MUX_OPEN = 0,
575 RCV_MUX_MUTE,
576 RCV_MUX_VOICE_PLAYBACK,
577 RCV_MUX_TEST_MODE,
578 RCV_MUX_MASK = 0x3,
579};
580
581static const char * const rcv_in_mux_map[] = {
582 "Open", "Mute", "Voice Playback", "Test Mode"
583};
584
585static int rcv_in_mux_map_value[] = {
586 RCV_MUX_OPEN,
587 RCV_MUX_MUTE,
588 RCV_MUX_VOICE_PLAYBACK,
589 RCV_MUX_TEST_MODE,
590};
591
592static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
593 SND_SOC_NOPM,
594 0,
595 RCV_MUX_MASK,
596 rcv_in_mux_map,
597 rcv_in_mux_map_value);
598
599static const struct snd_kcontrol_new rcv_in_mux_control =
600 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
601
602/* Direct MUX */
603enum {
604 DIR_MUX_OPEN = 0,
605 DIR_MUX_MUTE,
606 DIR_MUX_PLAYBACK,
607 DIR_MUX_TEST_MODE,
608 DIR_MUX_MASK = 0x3,
609};
610
611static const char * const direct_in_mux_map[] = {
612 "Open", "Mute", "Playback", "Test Mode"
613};
614
615static int direct_in_mux_map_value[] = {
616 DIR_MUX_OPEN,
617 DIR_MUX_MUTE,
618 DIR_MUX_PLAYBACK,
619 DIR_MUX_TEST_MODE,
620};
621
622static SOC_VALUE_ENUM_SINGLE_DECL(direct_in_mux_map_enum,
623 SND_SOC_NOPM,
624 0,
625 DIR_MUX_MASK,
626 direct_in_mux_map,
627 direct_in_mux_map_value);
628
629static const struct snd_kcontrol_new direct_in_mux_control =
630 SOC_DAPM_ENUM("DIRECT Select", direct_in_mux_map_enum);
631
632/* Direct_lo MUX */
633enum {
634 DIR_LO_MUX_OPEN = 0,
635 DIR_LO_MUX_MUTE,
636 DIR_LO_MUX_PLAYBACK,
637 DIR_LO_MUX_TEST_MODE,
638 DIR_LO_MUX_MASK = 0x3,
639};
640
641static const char * const direct_lo_in_mux_map[] = {
642 "Open", "Mute", "Playback", "Test Mode"
643};
644
645static int direct_lo_in_mux_map_value[] = {
646 DIR_LO_MUX_OPEN,
647 DIR_LO_MUX_MUTE,
648 DIR_LO_MUX_PLAYBACK,
649 DIR_LO_MUX_TEST_MODE,
650};
651
652static SOC_VALUE_ENUM_SINGLE_DECL(direct_lo_in_mux_map_enum,
653 SND_SOC_NOPM,
654 0,
655 DIR_LO_MUX_MASK,
656 direct_lo_in_mux_map,
657 direct_lo_in_mux_map_value);
658
659static const struct snd_kcontrol_new direct_lo_in_mux_control =
660 SOC_DAPM_ENUM("DIRECT_LO Select", direct_lo_in_mux_map_enum);
661
662/* DAC In MUX */
663static const char * const dac_in_mux_map[] = {
664 "Normal Path", "Sgen"
665};
666
667static int dac_in_mux_map_value[] = {
668 0x0, 0x1,
669};
670
671static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
672 MT6389_AFE_TOP_CON0,
673 DL_SINE_ON_SFT,
674 DL_SINE_ON_MASK,
675 dac_in_mux_map,
676 dac_in_mux_map_value);
677
678static const struct snd_kcontrol_new dac_in_mux_control =
679 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
680
681/* AIF Out MUX */
682static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
683 MT6389_AFE_TOP_CON0,
684 UL_SINE_ON_SFT,
685 UL_SINE_ON_MASK,
686 dac_in_mux_map,
687 dac_in_mux_map_value);
688
689static const struct snd_kcontrol_new aif_out_mux_control =
690 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
691
692/* Mic Type MUX */
693enum {
694 MIC_TYPE_MUX_IDLE = 0,
695 MIC_TYPE_MUX_ACC,
696 MIC_TYPE_MUX_DMIC,
697 MIC_TYPE_MUX_DCC,
698 MIC_TYPE_MUX_DCC_ECM_DIFF,
699 MIC_TYPE_MUX_DCC_ECM_SINGLE,
700 MIC_TYPE_MUX_ACCDIFF,
701 MIC_TYPE_MUX_MASK = 0x7,
702};
703
704#define IS_DCC_BASE(x) (x == MIC_TYPE_MUX_DCC || \
705 x == MIC_TYPE_MUX_DCC_ECM_DIFF || \
706 x == MIC_TYPE_MUX_DCC_ECM_SINGLE)
707
708static const char * const mic_type_mux_map[] = {
709 "Idle",
710 "ACC",
711 "DMIC",
712 "DCC",
713 "DCC_ECM_DIFF",
714 "DCC_ECM_SINGLE",
715 "ACCDIFF",
716};
717
718static int mic_type_mux_map_value[] = {
719 MIC_TYPE_MUX_IDLE,
720 MIC_TYPE_MUX_ACC,
721 MIC_TYPE_MUX_DMIC,
722 MIC_TYPE_MUX_DCC,
723 MIC_TYPE_MUX_DCC_ECM_DIFF,
724 MIC_TYPE_MUX_DCC_ECM_SINGLE,
725 MIC_TYPE_MUX_ACCDIFF,
726};
727
728static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
729 SND_SOC_NOPM,
730 0,
731 MIC_TYPE_MUX_MASK,
732 mic_type_mux_map,
733 mic_type_mux_map_value);
734
735static const struct snd_kcontrol_new mic_type_mux_control =
736 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
737
738/* ADC L MUX */
739enum {
740 ADC_MUX_IDLE = 0,
741 ADC_MUX_AIN0,
742 ADC_MUX_PREAMPLIFIER,
743 ADC_MUX_IDLE1,
744 ADC_MUX_MASK = 0x3,
745};
746
747static const char * const adc_left_mux_map[] = {
748 "Idle", "AIN0", "Left Preamplifier", "Idle_1"
749};
750
751static int adc_mux_map_value[] = {
752 ADC_MUX_IDLE,
753 ADC_MUX_AIN0,
754 ADC_MUX_PREAMPLIFIER,
755 ADC_MUX_IDLE1,
756};
757
758static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
759 SND_SOC_NOPM,
760 0,
761 ADC_MUX_MASK,
762 adc_left_mux_map,
763 adc_mux_map_value);
764
765static const struct snd_kcontrol_new adc_left_mux_control =
766 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
767
768/* ADC R MUX */
769static const char * const adc_right_mux_map[] = {
770 "Idle", "AIN0", "Right Preamplifier", "Idle_1"
771};
772
773static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
774 SND_SOC_NOPM,
775 0,
776 ADC_MUX_MASK,
777 adc_right_mux_map,
778 adc_mux_map_value);
779
780static const struct snd_kcontrol_new adc_right_mux_control =
781 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
782
783/* PGA L MUX */
784enum {
785 PGA_MUX_NONE = 0,
786 PGA_MUX_AIN0,
787 PGA_MUX_AIN1,
788 PGA_MUX_AIN2,
789 PGA_MUX_MASK = 0x3,
790};
791
792static const char * const pga_mux_map[] = {
793 "None", "AIN0", "AIN1", "AIN2"
794};
795
796static int pga_mux_map_value[] = {
797 PGA_MUX_NONE,
798 PGA_MUX_AIN0,
799 PGA_MUX_AIN1,
800 PGA_MUX_AIN2,
801};
802
803static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
804 SND_SOC_NOPM,
805 0,
806 PGA_MUX_MASK,
807 pga_mux_map,
808 pga_mux_map_value);
809
810static const struct snd_kcontrol_new pga_left_mux_control =
811 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
812
813/* PGA R MUX */
814static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
815 SND_SOC_NOPM,
816 0,
817 PGA_MUX_MASK,
818 pga_mux_map,
819 pga_mux_map_value);
820
821static const struct snd_kcontrol_new pga_right_mux_control =
822 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
823
824static int mt_clksq_event(struct snd_soc_dapm_widget *w,
825 struct snd_kcontrol *kcontrol,
826 int event)
827{
828 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
829 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
830 unsigned int value;
831
832 dev_info(priv->dev, "%s(), event = 0x%x\n", __func__, event);
833
834 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
835 RG_CLKSQ_IN_SEL_MASK_SFT,
836 0 << RG_CLKSQ_IN_SEL_SFT);
837
838 switch (event) {
839 case SND_SOC_DAPM_POST_PMU:
840 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
841 RG_CLKSQ_EN_MASK_SFT,
842 1 << RG_CLKSQ_EN_SFT);
843 break;
844 case SND_SOC_DAPM_PRE_PMD:
845 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
846 RG_CLKSQ_EN_MASK_SFT,
847 0 << RG_CLKSQ_EN_SFT);
848 break;
849 default:
850 break;
851 }
852 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON5, &value);
853
854 dev_info(priv->dev, "%s(), MT6389_AUDENC_ANA_CON5 = 0x%x\n",
855 __func__, value);
856
857 return 0;
858}
859
860static int mt_sgen_event(struct snd_soc_dapm_widget *w,
861 struct snd_kcontrol *kcontrol,
862 int event)
863{
864 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
865 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
866
867 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
868
869 switch (event) {
870 case SND_SOC_DAPM_PRE_PMU:
871 /* sdm audio fifo clock power on */
872 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0006);
873 /* scrambler clock on enable */
874 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON0, 0xCBA1);
875 /* sdm power on */
876 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0003);
877 /* sdm fifo enable */
878 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x000B);
879
880 regmap_update_bits(priv->regmap, MT6389_AFE_SGEN_CFG0,
881 0xff3f,
882 0x0000);
883 regmap_update_bits(priv->regmap, MT6389_AFE_SGEN_CFG1,
884 0xffff,
885 0x0001);
886 break;
887 case SND_SOC_DAPM_POST_PMD:
888 /* DL scrambler disabling sequence */
889 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0000);
890 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON0, 0xcba0);
891 break;
892 default:
893 break;
894 }
895
896 return 0;
897}
898
899static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
900 struct snd_kcontrol *kcontrol,
901 int event)
902{
903 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
904 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
905
906 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
907 __func__, event, priv->dl_rate);
908
909 switch (event) {
910 case SND_SOC_DAPM_PRE_PMU:
911 playback_gpio_set(priv);
912 /* enable aud_pad TX fifos */
913 regmap_update_bits(priv->regmap,
914 MT6389_AFE_AUD_PAD_TOP,
915 0x00ff, 0x0031);
916 /* sdm audio fifo clock power on */
917 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0006);
918 /* scrambler clock on enable */
919 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON0, 0xCBA1);
920 /* sdm power on */
921 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0003);
922 /* sdm fifo enable */
923 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x000B);
924 break;
925 case SND_SOC_DAPM_POST_PMD:
926 /* DL scrambler disabling sequence */
927 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON2, 0x0000);
928 regmap_write(priv->regmap, MT6389_AFUNC_AUD_CON0, 0xcba0);
929 regmap_update_bits(priv->regmap,
930 MT6389_AFE_AUD_PAD_TOP,
931 0x00ff, 0x0000);
932 playback_gpio_reset(priv);
933 break;
934 default:
935 break;
936 }
937
938 return 0;
939}
940
941static int mtk_hp_enable(struct mt6389_priv *priv)
942{
943 /* mt6389 not support HP path */
944 return 0;
945}
946
947static int mtk_hp_disable(struct mt6389_priv *priv)
948{
949 /* mt6389 not support HP path */
950 return 0;
951}
952
953static int mtk_hp_spk_enable(struct mt6389_priv *priv)
954{
955 /* mt6389 not support HP path */
956 return 0;
957}
958
959
960static int mtk_hp_spk_disable(struct mt6389_priv *priv)
961{
962 /* mt6389 not support HP path */
963 return 0;
964}
965
966static int mt_hp_event(struct snd_soc_dapm_widget *w,
967 struct snd_kcontrol *kcontrol,
968 int event)
969{
970 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
971 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
972 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
973 int device = DEVICE_HP;
974
975 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
976 __func__,
977 event,
978 priv->dev_counter[device],
979 mux);
980
981 switch (event) {
982 case SND_SOC_DAPM_PRE_PMU:
983 priv->dev_counter[device]++;
984 if (priv->dev_counter[device] > 1)
985 break; /* already enabled, do nothing */
986 else if (priv->dev_counter[device] <= 0)
987 dev_info(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
988 __func__,
989 priv->dev_counter[device]);
990
991 priv->mux_select[MUX_HP_L] = mux;
992
993 if (mux == HP_MUX_HP)
994 mtk_hp_enable(priv);
995 else if (mux == HP_MUX_HPSPK)
996 mtk_hp_spk_enable(priv);
997 break;
998 case SND_SOC_DAPM_PRE_PMD:
999 priv->dev_counter[device]--;
1000 if (priv->dev_counter[device] > 0) {
1001 break; /* still being used, don't close */
1002 } else if (priv->dev_counter[device] < 0) {
1003 dev_info(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
1004 __func__,
1005 priv->dev_counter[device]);
1006 priv->dev_counter[device] = 0;
1007 break;
1008 }
1009
1010 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
1011 mtk_hp_disable(priv);
1012 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
1013 mtk_hp_spk_disable(priv);
1014
1015 priv->mux_select[MUX_HP_L] = mux;
1016 break;
1017 default:
1018 break;
1019 }
1020
1021 return 0;
1022}
1023
1024static void set_speaker_gain(struct mt6389_priv *priv, int spk_gain)
1025{
1026 dev_info(priv->dev, "%s(), spk_gain = %d\n", __func__, spk_gain);
1027 regmap_update_bits(priv->regmap, MT6389_ZCD_CON1,
1028 DL_GAIN_REG_MASK, (spk_gain << 7) | spk_gain);
1029}
1030
1031static int mt_lo_event(struct snd_soc_dapm_widget *w,
1032 struct snd_kcontrol *kcontrol,
1033 int event)
1034{
1035 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1036 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1037
1038 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1039 __func__,
1040 event,
1041 dapm_kcontrol_get_value(w->kcontrols[0]));
1042
1043 switch (event) {
1044 case SND_SOC_DAPM_PRE_PMU:
1045 /* reset LOL output */
1046 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1047 0x1 << 10, 0x1 << 10);
1048 /* reset HS output */
1049 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1050 0x1 << 10, 0x1 << 10);
1051 /* Reduce ESD resistance of AU_REFN */
1052 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON2, 0x4000);
1053 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1054 0x10, 0x10);
1055 /* Turn on DA_600K_NCP_VA18 */
1056 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, 0x0001);
1057 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1058 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON2, 0x002c);
1059 /* Toggle RG_DIVCKS_CHG */
1060 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON0, 0x0001);
1061 /* Set NCP soft start mode as default mode: 100us */
1062 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON4, 0x0002);
1063 /* Enable NCP */
1064 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3, 0x0000);
1065 usleep_range(250, 270);
1066
1067 /* Enable cap-less LDOs (1.5V) */
1068 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1069 0x1055, 0x1055);
1070 /* Enable NV regulator (-1.2V) */
1071 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON13, 0x0001);
1072 usleep_range(100, 120);
1073
1074 /* Disable AUD_ZCD */
1075 hp_zcd_disable(priv);
1076
1077 /* Disable lineout short-ckt protection */
1078 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1079 0x1 << 4, 0x1 << 4);
1080 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1081 0x1 << 4, 0x1 << 4);
1082
1083 /* Enable IBIST */
1084 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);
1085 /* Set HP DR bias current optimization, 010: 6uA */
1086 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON9, 0x4900);
1087 /* Set HP & ZCD bias current optimization */
1088 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1089 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);
1090
1091 /* Set HS STB enhance circuits */
1092 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1093 0x1 << 7, 0x1 << 7);
1094
1095 /* Set LO STB enhance circuits */
1096 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1097 0x1 << 8, 0x1 << 8);
1098
1099 /* Release HS output */
1100 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1101 0x1 << 10, 0x0 << 10);
1102 /* Release LOL output */
1103 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1104 0x1 << 10, 0x0 << 10);
1105
1106 /* Enable HS/LOL CMFB circuit */
1107 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1108 0xff00, 0xC000);
1109
1110 /* Select CMFB resistor bulk to AC mode */
1111 /* Selec HS/LO cap size (6.5pF default) */
1112 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON8, 0x0000);
1113
1114 /* Enable HS/LOL offset trim circuit */
1115 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ELR_0,
1116 0x3fc0, 0x2040);
1117
1118 /* Set OUT2 output select HS amp (100) */
1119 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1120 0x7000, 0x4000);
1121 /* Set OUT1 output select LOL amp (011) */
1122 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1123 0x0700, 0x0300);
1124
1125 /* Enable HS driver bias circuits */
1126 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1127 0x1 << 1, 0x1 << 1);
1128
1129 /* Enable HS driver core circuits */
1130 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1131 0x1, 0x1);
1132
1133 /* Enable LO driver bias circuits */
1134 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1135 0x1 << 1, 0x1 << 1);
1136 /* Enable LO driver core circuits */
1137 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1138 0x1, 0x1);
1139
1140 /* Set HS gain to normal gain step by step */
1141 regmap_update_bits(priv->regmap, MT6389_ZCD_CON3,
1142 RG_AUDHSGAIN_MASK_SFT,
1143 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] <<
1144 RG_AUDHSGAIN_SFT);
1145 /* Set LO gain to normal gain step by step */
1146 set_speaker_gain(priv,
1147 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);
1148
1149 /* Enable AUD_CLK */
1150 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
1151 0x1, 0x1);
1152
1153 /* Enable Audio DACL/R */
1154 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1155 0x000f, 0x000f);
1156 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0001);
1157 /* Switch HS MUX to audio DAC L */
1158 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1159 0x3 << 2, 0x1 << 2);
1160 /* Switch LOL MUX to audio DAC R*/
1161 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1162 0x3 << 2, 0x2 << 2);
1163
1164 break;
1165 case SND_SOC_DAPM_PRE_PMD:
1166 /* Switch HS MUX to open */
1167 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1168 0x3 << 2, 0x0 << 2);
1169
1170 /* Switch LOL MUX to open */
1171 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1172 0x3 << 2, 0x0 << 2);
1173
1174 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0000);
1175
1176 /* Disable Audio DAC */
1177 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1178 0x000f, 0x0000);
1179
1180 /* Disable AUD_CLK */
1181 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
1182 0x1, 0x0);
1183
1184 /* decrease HS gain to minimum gain step by step */
1185 regmap_write(priv->regmap, MT6389_ZCD_CON3,
1186 DL_GAIN_N_40DB_REG);
1187
1188 /* decrease LO gain to minimum gain step by step */
1189 regmap_write(priv->regmap, MT6389_ZCD_CON1,
1190 DL_GAIN_N_40DB_REG);
1191
1192 /* Disable HS driver core circuits */
1193 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1194 0x1, 0x0);
1195 /* Disable LO driver bias circuits */
1196 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1197 0x1 << 1, 0x0 << 1);
1198
1199 /* Disable HS driver bias circuits */
1200 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1201 0x1 << 1, 0x0 << 1);
1202
1203 /* Disable LO driver core circuits */
1204 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1205 0x1, 0x0);
1206 /* Disable HS STB enhance circuits */
1207 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1208 0x1 << 7, 0x0 << 7);
1209
1210 /* Disable LO STB enhance circuits */
1211 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1212 0x1 << 8, 0x0 << 8);
1213
1214 /* Disable LOL offset trim circuit */
1215 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ELR_0,
1216 0x3f80, 0x0000);
1217
1218 /* Disable LOL CMFB circuit */
1219 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1220 0xff00, 0x0000);
1221 /* reset LOL output */
1222 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1223 0x1 << 10, 0x1 << 10);
1224 /* reset HS output */
1225 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1226 0x1 << 10, 0x1 << 10);
1227
1228 /* Reset OUT1 output select none */
1229 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1230 0x0700, 0x0000);
1231 /* Reset OUT2 output select none */
1232 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1233 0x7000, 0x0000);
1234
1235 /* Disable IBIST */
1236 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON10,
1237 0x1 << 8, 0x1 << 8);
1238 /* Release ESD resistance of AU_REFN */
1239 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1240 0x10, 0x0);
1241
1242 /* Disable NV regulator (-1.2V) */
1243 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON13,
1244 0x1, 0x0);
1245 /* Disable cap-less LDOs (1.5V) */
1246 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1247 0x1055, 0x0);
1248 /* Disable NCP */
1249 regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3,
1250 0x1, 0x1);
1251 /* Turn off DA_600K_NCP_VA18 */
1252 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, 0x0);
1253 break;
1254 default:
1255 break;
1256 }
1257 return 0;
1258}
1259
1260static int mt_rcv_event(struct snd_soc_dapm_widget *w,
1261 struct snd_kcontrol *kcontrol,
1262 int event)
1263{
1264 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1265 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1266
1267 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1268 __func__,
1269 event,
1270 dapm_kcontrol_get_value(w->kcontrols[0]));
1271
1272 switch (event) {
1273 case SND_SOC_DAPM_PRE_PMU:
1274 /* Reduce ESD resistance of AU_REFN */
1275 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1276 0x10, 0x10);
1277 /* Turn on DA_600K_NCP_VA18 */
1278 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, 0x0001);
1279 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1280 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON2, 0x002c);
1281 /* Toggle RG_DIVCKS_CHG */
1282 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON0, 0x0001);
1283 /* Set NCP soft start mode as default mode: 100us */
1284 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON4, 0x0002);
1285 /* Enable NCP */
1286 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3, 0x0000);
1287 usleep_range(250, 270);
1288
1289 /* Enable cap-less LDOs (1.5V) */
1290 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1291 0x1055, 0x1055);
1292 /* Enable NV regulator (-1.2V) */
1293 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON13, 0x0001);
1294 usleep_range(100, 120);
1295
1296 /* Disable AUD_ZCD */
1297 hp_zcd_disable(priv);
1298
1299 /* Disable handset short-circuit protection */
1300 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1301 0x1 << 4, 0x1 << 4);
1302 /* Enable IBIST */
1303 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);
1304 /* Set HP DR bias current optimization, 010: 6uA */
1305 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON9, 0x4900);
1306 /* Set HP & ZCD bias current optimization */
1307 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1308 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);
1309 /* Set HS STB enhance circuits */
1310 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1311 0x1 << 7, 0x1 << 7);
1312 /* Enable HS CMFB circuit */
1313 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1314 0xff00, 0x4000);
1315
1316 /* Disable HP main CMFB loop */
1317 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0000);
1318 /* Select CMFB resistor bulk to AC mode */
1319 /* Selec HS/LO cap size (6.5pF default) */
1320 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON8, 0x0000);
1321
1322 /* Enable HS offset trim circuit */
1323 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ELR_0,
1324 0x3f80, 0x0040);
1325 /* Set OUT2 output select HS amp (100) */
1326 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1327 0x7000, 0x4000);
1328
1329 /* Enable HS driver bias circuits */
1330 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1331 0x1 << 1, 0x1 << 1);
1332
1333 /* Enable HS driver core circuits */
1334 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1335 0x1, 0x1);
1336
1337 /* Set HS gain to normal gain step by step */
1338 regmap_update_bits(priv->regmap, MT6389_ZCD_CON3,
1339 RG_AUDHSGAIN_MASK_SFT,
1340 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] <<
1341 RG_AUDHSGAIN_SFT);
1342
1343 /* Enable AUD_CLK */
1344 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
1345 0x1, 0x1);
1346 /* Enable Audio DACL */
1347 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1348 0x0009, 0x0009);
1349
1350 /* Enable low-noise mode of DAC */
1351 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0001);
1352 /* Switch HS MUX to audio DACL */
1353 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1354 0x3 << 2, 0x2 << 2);
1355
1356 break;
1357 case SND_SOC_DAPM_PRE_PMD:
1358 /* HS mux to open */
1359 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1360 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
1361 RCV_MUX_OPEN);
1362
1363 /* Disable Audio DAC */
1364 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1365 0x000f, 0x0000);
1366
1367 /* Disable AUD_CLK */
1368 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
1369 0x1, 0x0);
1370
1371 /* decrease HS gain to minimum gain step by step */
1372 regmap_write(priv->regmap, MT6389_ZCD_CON3, DL_GAIN_N_40DB);
1373
1374 /* Disable HS driver core circuits */
1375 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1376 0x1, 0x0);
1377
1378 /* Disable HS driver bias circuits */
1379 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1380 0x1 << 1, 0x0 << 1);
1381
1382
1383 /* Disable HP aux CMFB loop */
1384 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON7,
1385 0xff << 8, 0x0);
1386
1387 /* Enable HP main CMFB Switch */
1388 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON7,
1389 0xff << 8, 0x2 << 8);
1390
1391 /* Disable IBIST */
1392 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON10,
1393 0x1 << 8, 0x1 << 8);
1394
1395 /* Disable NV regulator (-1.2V) */
1396 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON13,
1397 0x1, 0x0);
1398 /* Disable cap-less LDOs (1.5V) */
1399 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1400 0x1055, 0x0);
1401 /* Disable NCP */
1402 regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3,
1403 0x1, 0x1);
1404 break;
1405 default:
1406 break;
1407 }
1408
1409 return 0;
1410}
1411
1412static int mt_direct_event(struct snd_soc_dapm_widget *w,
1413 struct snd_kcontrol *kcontrol,
1414 int event)
1415{
1416 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1417 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1418
1419 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1420 __func__,
1421 event,
1422 dapm_kcontrol_get_value(w->kcontrols[0]));
1423
1424 switch (event) {
1425 case SND_SOC_DAPM_PRE_PMU:
1426 /* Reduce ESD resistance of AU_REFN */
1427 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1428 0x10, 0x10);
1429 /* Turn on DA_600K_NCP_VA18 */
1430 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, 0x0001);
1431 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1432 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON2, 0x002c);
1433 /* Toggle RG_DIVCKS_CHG */
1434 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON0, 0x0001);
1435 /* Set NCP soft start mode as default mode: 100us */
1436 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON4, 0x0002);
1437 /* Enable NCP */
1438 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3, 0x0000);
1439 usleep_range(250, 270);
1440
1441 /* Enable cap-less LDOs (1.5V) */
1442 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1443 0x1055, 0x1055);
1444 usleep_range(100, 120);
1445
1446 /* Enable VCM buffer */
1447 /* Set VCM output level = 0.75V */
1448 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
1449 0x0071, 0x0041);
1450
1451 /* Set LO gain to normal gain step by step */
1452 set_speaker_gain(priv,
1453 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);
1454
1455 /* Set LOL input reset for ADP mode */
1456 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1457 RG_LOINPUTRESET0_VAUDP15_MASK_SFT,
1458 0x1 << RG_LOINPUTRESET0_VAUDP15_SFT);
1459 /* Disable LO STB enhance circuits for ADP mode */
1460 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1461 RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT,
1462 0x0 << RG_LOOUTPUTSTBENH_VAUDP15_SFT);
1463
1464 /* Set OUT0 output select UL VIN0 (001) */
1465 /* Set OUT1 output select UL VIN1 (010) */
1466 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1467 0x0770, 0x0210);
1468
1469 /* Pre-charge VIN0&VIN1 input cap (1uF) to VCM */
1470 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1471 0xf, 0xf);
1472 /* Pre-charge OUT0&OUT1 output cap (1uF) to VCM with 2Kohm */
1473 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
1474 0xff, 0x33);
1475 /* OUT0&OUT1 ADP SW change to source-tied */
1476 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1477 0xff00, 0x0300);
1478 /* Precharge settle time 100ms */
1479 usleep_range(100, 120);
1480
1481 /* Enable OUT0/1 to VCM path SW with 50K ohm */
1482 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
1483 0x0f00, 0x0f00);
1484 /* Disable Pre-charge VIN0&VIN1 input */
1485 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1486 0xf, 0x0);
1487 /* Disable pre-charge OUT0&OUT1 output */
1488 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
1489 0xff, 0x0);
1490 break;
1491 case SND_SOC_DAPM_PRE_PMD:
1492
1493 /* Disable ADP source-tied, disable HS&LO CMFB path */
1494 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1495 0xff00, 0x0000);
1496
1497 /* Disable OUT0/1 to VCM path SW with 50K ohm */
1498 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
1499 0x0f00, 0x0000);
1500 /* VIN0&VIN1 to VCM path SW */
1501 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1502 0xf, 0x0);
1503 /* OUT0&OUT1&VIN0&VIN1 discharge to AVSS with 2K ohm */
1504 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
1505 0xff, 0xcc);
1506 /* Disable VCM buffer */
1507 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
1508 RG_AUDVCMBUF_EN_VAUDP28_MASK_SFT,
1509 0x0 << RG_AUDVCMBUF_EN_VAUDP28_SFT);
1510 /* Discharge settle time 100ms */
1511 usleep_range(100, 120);
1512
1513 /* Disable pre-charge OUT0&OUT1 output */
1514 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
1515 0xff, 0xcc);
1516 /* Set OUT0/1/2 output select open (000) */
1517 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1518 0x7770, 0x0000);
1519
1520 /* Release LOL input reset */
1521 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1522 RG_LOINPUTRESET0_VAUDP15_MASK_SFT,
1523 0x0 << RG_LOINPUTRESET0_VAUDP15_SFT);
1524 /* Disable LO STB enhance circuits for ADP mode */
1525 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1526 RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT,
1527 0x1 << RG_LOOUTPUTSTBENH_VAUDP15_SFT);
1528
1529 /* Disable IBIST */
1530 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON10,
1531 RG_AUDIBIASPWRDN_VAUDP15_MASK_SFT,
1532 0x1 << RG_AUDIBIASPWRDN_VAUDP15_SFT);
1533
1534 /* Release ESD resistance of AU_REFN */
1535 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1536 RG_AUDREFN_DERES_EN_VAUDP28_MASK_SFT,
1537 0x0 << RG_AUDREFN_DERES_EN_VAUDP28_SFT);
1538
1539 /* Set LOL gain to mute */
1540 regmap_write(priv->regmap, MT6389_ZCD_CON1, DL_GAIN_N_40DB);
1541
1542 /* Disable cap-less LDOs (1.5V) */
1543 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1544 0x1055, 0x0);
1545 /* Disable NCP */
1546 regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3,
1547 0x1, 0x1);
1548
1549 /* Turn off DA_600K_NCP_VA18*/
1550 regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1,
1551 RG_DIVCKS_ON_MASK_SFT,
1552 0x0 << RG_DIVCKS_ON_SFT);
1553
1554 break;
1555 default:
1556 break;
1557 }
1558
1559 return 0;
1560}
1561
1562static int mt_direct_lo_event(struct snd_soc_dapm_widget *w,
1563 struct snd_kcontrol *kcontrol,
1564 int event)
1565{
1566 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1567 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1568
1569 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1570 __func__,
1571 event,
1572 dapm_kcontrol_get_value(w->kcontrols[0]));
1573
1574 switch (event) {
1575 case SND_SOC_DAPM_PRE_PMU:
1576 /* Reduce ESD resistance of AU_REFN */
1577 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1578 0x10, 0x10);
1579 /* Turn on DA_600K_NCP_VA18 */
1580 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, 0x0001);
1581 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1582 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON2, 0x002c);
1583 /* Toggle RG_DIVCKS_CHG */
1584 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON0, 0x0001);
1585 /* Set NCP soft start mode as default mode: 100us */
1586 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON4, 0x0002);
1587 /* Enable NCP */
1588 regmap_write(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3, 0x0000);
1589 usleep_range(250, 270);
1590
1591 /* Enable cap-less LDOs (1.5V) */
1592 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1593 0x1055, 0x1055);
1594 /* Enable NV regulator (-1.2V) */
1595 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON13, 0x0001);
1596 usleep_range(100, 120);
1597
1598 /* Enable VCM buffer */
1599 /* Set VCM output level = 0.75V */
1600 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
1601 0x0071, 0x0041);
1602
1603 /* Disable AUD_ZCD */
1604 hp_zcd_disable(priv);
1605
1606 /* Set LO gain to normal gain step by step */
1607 set_speaker_gain(priv,
1608 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);
1609
1610 /* Set LOL input reset for ADP mode */
1611 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1612 RG_LOINPUTRESET0_VAUDP15_MASK_SFT,
1613 0x1 << RG_LOINPUTRESET0_VAUDP15_SFT);
1614 /* Disable LO STB enhance circuits for ADP mode */
1615 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1616 RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT,
1617 0x0 << RG_LOOUTPUTSTBENH_VAUDP15_SFT);
1618
1619 /* Set OUT0 output select UL VIN0 (001) */
1620 /* Set OUT1 output select UL VIN1 (010) */
1621 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1622 0x0770, 0x0210);
1623
1624 /* Pre-charge VIN0&VIN1 input cap (1uF) to VCM */
1625 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1626 0xf, 0xf);
1627 /* Pre-charge OUT0&OUT1 output cap (1uF) to VCM with 2Kohm */
1628 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
1629 0xff, 0x33);
1630 /* OUT0&OUT1 ADP SW change to source-tied */
1631 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1632 0xff00, 0x0300);
1633 /* Precharge settle time 100ms */
1634 usleep_range(100, 120);
1635
1636 /* Enable OUT0/1 to VCM path SW with 50K ohm */
1637 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
1638 0x0f00, 0x0f00);
1639 /* Disable Pre-charge VIN0&VIN1 input */
1640 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1641 0xf, 0x0);
1642 /* Disable pre-charge OUT0&OUT1 output */
1643 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
1644 0xff, 0x0);
1645 /* Disable handset short-ckt protection. */
1646 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1647 0x10, 0x10);
1648
1649 /* Enable IBIST */
1650 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);
1651 /* Set HP DR bias current optimization, 010: 6uA */
1652 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON9, 0x4900);
1653 /* Set HP & ZCD bias current optimization */
1654 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1655 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON10, 0x0055);
1656
1657 /* Set HS STB enhance circuits */
1658 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON4, 0x0090);
1659
1660 /* Enable HS CMFB circuit for normal operation */
1661 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1662 0xff00, 0x4300);
1663
1664 /* Select CMFB resistor bulk to AC mode */
1665 /* Selec HS/LO cap size (6.5pF default) */
1666 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON8, 0x0000);
1667
1668
1669 /* Enable HS offset trim circuit */
1670 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ELR_0,
1671 0x7f, 0x40);
1672
1673 /* Set OUT2 output select HS amp (100) */
1674 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1675 0x7000, 0x4000);
1676 /* Enable HS driver bias circuits */
1677 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON4, 0x0092);
1678 /* Enable HS driver core circuits */
1679 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON4, 0x0093);
1680
1681 /* Set HS gain to normal gain step by step */
1682 regmap_write(priv->regmap, MT6389_ZCD_CON3,
1683 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);
1684
1685 /* Enable AUD_CLK */
1686 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
1687 0x1, 0x1);
1688
1689 /* Enable Audio DACL */
1690 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1691 0x9, 0x9);
1692
1693 /* Enable low-noise mode of DAC */
1694 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0001);
1695 /* Switch HS MUX to audio DAC */
1696 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON4, 0x009b);
1697
1698 break;
1699 case SND_SOC_DAPM_PRE_PMD:
1700
1701 /* decrease HS gain to minimum gain step by step */
1702 regmap_write(priv->regmap, MT6389_ZCD_CON3, DL_GAIN_N_40DB);
1703
1704 /* Disable AUD_ZCD */
1705 hp_zcd_disable(priv);
1706
1707 /* HS mux to open */
1708 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1709 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
1710 RCV_MUX_OPEN);
1711
1712 /* Enable low-noise mode of DAC */
1713 regmap_write(priv->regmap, MT6389_AUDDEC_ANA_CON7, 0x0000);
1714
1715 /* Disable Audio DAC */
1716 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1717 0x9, 0x0);
1718
1719 /* Disable AUD_CLK */
1720 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
1721 0x1, 0x0);
1722
1723 /* Disable HS driver core circuits */
1724 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1725 0x1, 0x0);
1726
1727 /* Disable HS driver bias circuits */
1728 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1729 0x2, 0x0);
1730
1731 /* Disable HS offset trim circuit */
1732 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ELR_0,
1733 0x7f, 0x0);
1734
1735 /* Disable ADP source-tied, disable HS&LO CMFB path */
1736 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1737 0xff00, 0x0000);
1738
1739 /* Disable handset short-ckt protection. */
1740 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
1741 0x400, 0x400);
1742
1743 /* Release LOL input reset */
1744 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1745 RG_LOINPUTRESET0_VAUDP15_MASK_SFT,
1746 0x0 << RG_LOINPUTRESET0_VAUDP15_SFT);
1747 /* Disable LO STB enhance circuits for ADP mode */
1748 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
1749 RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT,
1750 0x1 << RG_LOOUTPUTSTBENH_VAUDP15_SFT);
1751
1752 /* Disable IBIST */
1753 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON10,
1754 RG_AUDIBIASPWRDN_VAUDP15_MASK_SFT,
1755 0x1 << RG_AUDIBIASPWRDN_VAUDP15_SFT);
1756
1757 /* Release ESD resistance of AU_REFN */
1758 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1759 RG_AUDREFN_DERES_EN_VAUDP28_MASK_SFT,
1760 0x0 << RG_AUDREFN_DERES_EN_VAUDP28_SFT);
1761
1762 /* Disable OUT0/1 to VCM path SW with 50K ohm */
1763 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
1764 0x0f00, 0x0000);
1765 /* VIN0&VIN1 to VCM path SW */
1766 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON2,
1767 0xf, 0x0);
1768 /* OUT0&OUT1&VIN0&VIN1 discharge to AVSS with 2K ohm */
1769 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
1770 0xff, 0xcc);
1771 /* Disable VCM buffer */
1772 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON1,
1773 RG_AUDVCMBUF_EN_VAUDP28_MASK_SFT,
1774 0x0 << RG_AUDVCMBUF_EN_VAUDP28_SFT);
1775 /* Discharge settle time 100ms */
1776 usleep_range(100, 120);
1777
1778 /* Disable pre-charge OUT0&OUT1 output */
1779 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON3,
1780 0xff, 0xcc);
1781 /* Set OUT0/1/2 output select open (000) */
1782 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
1783 0x7770, 0x0000);
1784
1785 /* Disable NV regulator (-1.2V) */
1786 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON13,
1787 0x1, 0x0);
1788 /* Set LOL gain to mute */
1789 regmap_write(priv->regmap, MT6389_ZCD_CON1, DL_GAIN_N_40DB);
1790
1791 /* Disable cap-less LDOs (1.5V) */
1792 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1793 0x1055, 0x0);
1794 /* Disable NCP */
1795 regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3,
1796 0x1, 0x1);
1797
1798 /* Turn off DA_600K_NCP_VA18*/
1799 regmap_update_bits(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1,
1800 RG_DIVCKS_ON_MASK_SFT,
1801 0x0 << RG_DIVCKS_ON_SFT);
1802
1803 break;
1804 default:
1805 break;
1806 }
1807
1808 return 0;
1809}
1810
1811static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
1812 struct snd_kcontrol *kcontrol,
1813 int event)
1814{
1815 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1816 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1817
1818 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
1819 __func__, event, priv->ul_rate);
1820
1821 switch (event) {
1822 case SND_SOC_DAPM_PRE_PMU:
1823 capture_gpio_set(priv);
1824 break;
1825 case SND_SOC_DAPM_POST_PMD:
1826 capture_gpio_reset(priv);
1827 break;
1828 default:
1829 break;
1830 }
1831
1832 return 0;
1833}
1834
1835static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
1836 struct snd_kcontrol *kcontrol,
1837 int event)
1838{
1839 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1840 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1841
1842 dev_dbg(priv->dev, "%s(), event 0x%x\n",
1843 __func__, event);
1844
1845 switch (event) {
1846 case SND_SOC_DAPM_PRE_PMU:
1847 /* Enable audio ADC CLKGEN */
1848 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
1849 0x1 << 5, 0x1 << 5);
1850 /* ADC CLK from CLKGEN (13MHz) */
1851 regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON3,
1852 0x0000);
1853 /* Enable LCLDO_ENC 1P8V */
1854 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1855 0x2500, 0x0100);
1856 /* LCLDO_ENC remote sense */
1857 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1858 0x2500, 0x2500);
1859 break;
1860 case SND_SOC_DAPM_POST_PMD:
1861 /* LCLDO_ENC remote sense off */
1862 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1863 0x2500, 0x0100);
1864 /* disable LCLDO_ENC 1P8V */
1865 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON12,
1866 0x2500, 0x0000);
1867
1868 /* ADC CLK from CLKGEN (13MHz) */
1869 regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON3, 0x0000);
1870 /* disable audio ADC CLKGEN */
1871 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON11,
1872 0x1 << 5, 0x0 << 5);
1873 break;
1874 default:
1875 break;
1876 }
1877
1878 return 0;
1879}
1880
1881static int mt6389_amic_enable(struct mt6389_priv *priv)
1882{
1883 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1884 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1885 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1886 int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
1887 int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
1888
1889 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u, mic_gain l %d, r %d\n",
1890 __func__, mic_type, mux_pga_l, mux_pga_r,
1891 mic_gain_l, mic_gain_r);
1892
1893 if (IS_DCC_BASE(mic_type)) {
1894 /* DCC 50k CLK (from 26M) */
1895 regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2062);
1896 regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2062);
1897 regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2060);
1898 regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2061);
1899 regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG1, 0x0100);
1900 }
1901
1902 /* mic bias 0 */
1903 if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
1904 mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
1905 switch (mic_type) {
1906 case MIC_TYPE_MUX_DCC_ECM_DIFF:
1907 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON9,
1908 0xff00, 0x7700);
1909 break;
1910 case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1911 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON9,
1912 0xff00, 0x1100);
1913 break;
1914 default:
1915 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON9,
1916 0xff00, 0x0000);
1917 break;
1918 }
1919 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1920 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON9,
1921 0xff, 0x21);
1922 }
1923
1924 /* mic bias 1 */
1925 if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
1926 /* Enable MICBIAS1, MISBIAS1 = 2P6V */
1927 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
1928 regmap_write(priv->regmap,
1929 MT6389_AUDENC_ANA_CON10, 0x0161);
1930 else
1931 regmap_write(priv->regmap,
1932 MT6389_AUDENC_ANA_CON10, 0x0061);
1933 }
1934
1935 /* set mic pga gain */
1936 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
1937 RG_AUDPREAMPLGAIN_MASK_SFT,
1938 mic_gain_l << RG_AUDPREAMPLGAIN_SFT);
1939 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
1940 RG_AUDPREAMPRGAIN_MASK_SFT,
1941 mic_gain_r << RG_AUDPREAMPRGAIN_SFT);
1942
1943 if (IS_DCC_BASE(mic_type)) {
1944 /* Audio L/R preamplifier DCC precharge */
1945 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
1946 0xf8ff, 0x0004);
1947 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
1948 0xf8ff, 0x0004);
1949 } else {
1950 /* reset reg */
1951 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
1952 0xf8ff, 0x0000);
1953 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
1954 0xf8ff, 0x0000);
1955 }
1956
1957 if (mux_pga_l != PGA_MUX_NONE) {
1958 /* L preamplifier input sel */
1959 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
1960 RG_AUDPREAMPLINPUTSEL_MASK_SFT,
1961 mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);
1962
1963 /* L preamplifier enable */
1964 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
1965 RG_AUDPREAMPLON_MASK_SFT,
1966 0x1 << RG_AUDPREAMPLON_SFT);
1967
1968 if (IS_DCC_BASE(mic_type)) {
1969 /* L preamplifier DCCEN */
1970 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
1971 RG_AUDPREAMPLDCCEN_MASK_SFT,
1972 0x1 << RG_AUDPREAMPLDCCEN_SFT);
1973 }
1974
1975 /* L ADC input sel : L PGA. Enable audio L ADC */
1976 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
1977 RG_AUDADCLINPUTSEL_MASK_SFT,
1978 ADC_MUX_PREAMPLIFIER <<
1979 RG_AUDADCLINPUTSEL_SFT);
1980 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
1981 RG_AUDADCLPWRUP_MASK_SFT,
1982 0x1 << RG_AUDADCLPWRUP_SFT);
1983
1984 if (mic_type == MIC_TYPE_MUX_ACC) {
1985 /* ACC single mode */
1986 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
1987 RG_AUDPREAMPLSE_MASK_SFT,
1988 0x1 << RG_AUDPREAMPLSE_SFT);
1989 }
1990 }
1991
1992 if (mux_pga_r != PGA_MUX_NONE) {
1993 /* R preamplifier input sel */
1994 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
1995 RG_AUDPREAMPRINPUTSEL_MASK_SFT,
1996 mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);
1997
1998 /* R preamplifier enable */
1999 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
2000 RG_AUDPREAMPRON_MASK_SFT,
2001 0x1 << RG_AUDPREAMPRON_SFT);
2002
2003 if (IS_DCC_BASE(mic_type)) {
2004 /* R preamplifier DCCEN */
2005 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
2006 RG_AUDPREAMPRDCCEN_MASK_SFT,
2007 0x1 << RG_AUDPREAMPRDCCEN_SFT);
2008 }
2009
2010 /* R ADC input sel : R PGA. Enable audio R ADC */
2011 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
2012 RG_AUDADCRINPUTSEL_MASK_SFT,
2013 ADC_MUX_PREAMPLIFIER <<
2014 RG_AUDADCRINPUTSEL_SFT);
2015 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
2016 RG_AUDADCRPWRUP_MASK_SFT,
2017 0x1 << RG_AUDADCRPWRUP_SFT);
2018
2019 if (mic_type == MIC_TYPE_MUX_ACC) {
2020 /* ACC single mode */
2021 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
2022 RG_AUDPREAMPLSE_MASK_SFT,
2023 0x1 << RG_AUDPREAMPLSE_SFT);
2024 }
2025 }
2026
2027 if (IS_DCC_BASE(mic_type)) {
2028 usleep_range(100, 150);
2029 /* Short body to ground in PGA */
2030 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON3,
2031 0x1 << 12, 0x0);
2032 }
2033
2034 /* here to set digital part */
2035 mt6389_mtkaif_tx_enable(priv);
2036
2037 /* UL dmic setting off */
2038 regmap_write(priv->regmap, MT6389_AFE_UL_SRC_CON0_H, 0x0000);
2039
2040 /* UL turn on */
2041 regmap_write(priv->regmap, MT6389_AFE_UL_SRC_CON0_L, 0x0001);
2042
2043 return 0;
2044}
2045
2046static void mt6389_amic_disable(struct mt6389_priv *priv)
2047{
2048 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
2049 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
2050 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
2051 int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
2052 int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
2053
2054 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u, mic_gain l %d, r %d\n",
2055 __func__, mic_type, mux_pga_l, mux_pga_r,
2056 mic_gain_l, mic_gain_r);
2057
2058 /* UL turn off */
2059 regmap_update_bits(priv->regmap, MT6389_AFE_UL_SRC_CON0_L,
2060 0x0001, 0x0000);
2061
2062 /* disable aud_pad TX fifos */
2063 mt6389_mtkaif_tx_disable(priv);
2064
2065 /* L ADC input sel : off, disable L ADC */
2066 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
2067 0xf000, 0x0000);
2068 /* L preamplifier DCCEN */
2069 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
2070 0x1 << 1, 0x0);
2071 /* L preamplifier input sel : off, L PGA 0 dB gain */
2072 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
2073 0xfffb, 0x0000);
2074
2075 /* disable L preamplifier DCC precharge */
2076 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON0,
2077 0x1 << 2, 0x0);
2078
2079 /* R ADC input sel : off, disable R ADC */
2080 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
2081 0xf000, 0x0000);
2082 /* R preamplifier DCCEN */
2083 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
2084 0x1 << 1, 0x0);
2085 /* R preamplifier input sel : off, R PGA 0 dB gain */
2086 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
2087 0x0ffb, 0x0000);
2088
2089 /* disable R preamplifier DCC precharge */
2090 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON1,
2091 0x1 << 2, 0x0);
2092
2093 /* mic bias */
2094 /* Disable MICBIAS0, MISBIAS0 = 1P7V */
2095 regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON9, 0x0000);
2096
2097 /* Disable MICBIAS1 */
2098 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON10,
2099 0x0001, 0x0000);
2100
2101 if (IS_DCC_BASE(mic_type)) {
2102 /* dcclk_gen_on=1'b0 */
2103 regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2060);
2104 /* dcclk_pdn=1'b1 */
2105 regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2062);
2106 /* dcclk_ref_ck_sel=2'b00 */
2107 regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2062);
2108 /* dcclk_div=11'b00100000011 */
2109 regmap_write(priv->regmap, MT6389_AFE_DCCLK_CFG0, 0x2062);
2110 }
2111}
2112
2113static int mt6389_dmic_enable(struct mt6389_priv *priv)
2114{
2115 dev_info(priv->dev, "%s()\n", __func__);
2116
2117 /* mic bias */
2118 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
2119 regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON9, 0x0021);
2120
2121 /* RG_BANDGAPGEN=1'b0 */
2122 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON10,
2123 0x1 << 12, 0x0);
2124
2125 /* DMIC enable */
2126 regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON8, 0x0005);
2127
2128 /* here to set digital part */
2129 mt6389_mtkaif_tx_enable(priv);
2130
2131 /* UL dmic setting */
2132 regmap_write(priv->regmap, MT6389_AFE_UL_SRC_CON0_H, 0x0080);
2133
2134 /* UL turn on */
2135 regmap_write(priv->regmap, MT6389_AFE_UL_SRC_CON0_L, 0x0003);
2136 return 0;
2137}
2138
2139static void mt6389_dmic_disable(struct mt6389_priv *priv)
2140{
2141 dev_info(priv->dev, "%s()\n", __func__);
2142
2143 /* UL turn off */
2144 regmap_update_bits(priv->regmap, MT6389_AFE_UL_SRC_CON0_L,
2145 0x0003, 0x0000);
2146
2147 /* disable aud_pad TX fifos */
2148 mt6389_mtkaif_tx_disable(priv);
2149
2150 /* DMIC disable */
2151 regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON8, 0x0000);
2152
2153 /* mic bias */
2154 /* MISBIAS0 = 1P7V */
2155 regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON9, 0x0001);
2156
2157 /* RG_BANDGAPGEN=1'b0 */
2158 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON10,
2159 0x1 << 12, 0x0);
2160
2161 /* MICBIA0 disable */
2162 regmap_write(priv->regmap, MT6389_AUDENC_ANA_CON9, 0x0000);
2163}
2164
2165static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
2166 struct snd_kcontrol *kcontrol,
2167 int event)
2168{
2169 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2170 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2171 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
2172
2173 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
2174 __func__, event, mux);
2175
2176 switch (event) {
2177 case SND_SOC_DAPM_WILL_PMU:
2178 priv->mux_select[MUX_MIC_TYPE] = mux;
2179 break;
2180 case SND_SOC_DAPM_PRE_PMU:
2181 switch (mux) {
2182 case MIC_TYPE_MUX_DMIC:
2183 mt6389_dmic_enable(priv);
2184 break;
2185 default:
2186 mt6389_amic_enable(priv);
2187 break;
2188 }
2189
2190 break;
2191 case SND_SOC_DAPM_POST_PMD:
2192 switch (priv->mux_select[MUX_MIC_TYPE]) {
2193 case MIC_TYPE_MUX_DMIC:
2194 mt6389_dmic_disable(priv);
2195 break;
2196 default:
2197 mt6389_amic_disable(priv);
2198 break;
2199 }
2200
2201 priv->mux_select[MUX_MIC_TYPE] = mux;
2202 break;
2203 default:
2204 break;
2205 }
2206
2207 return 0;
2208}
2209
2210static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
2211 struct snd_kcontrol *kcontrol,
2212 int event)
2213{
2214 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2215 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2216 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
2217
2218 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
2219 __func__, event, mux);
2220
2221 priv->mux_select[MUX_ADC_L] = mux;
2222
2223 return 0;
2224}
2225
2226static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
2227 struct snd_kcontrol *kcontrol,
2228 int event)
2229{
2230 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2231 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2232 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
2233
2234 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
2235 __func__, event, mux);
2236
2237 priv->mux_select[MUX_ADC_R] = mux;
2238
2239 return 0;
2240}
2241
2242static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
2243 struct snd_kcontrol *kcontrol,
2244 int event)
2245{
2246 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2247 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2248 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
2249
2250 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
2251 __func__, event, mux);
2252
2253 priv->mux_select[MUX_PGA_L] = mux;
2254
2255 return 0;
2256}
2257
2258static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
2259 struct snd_kcontrol *kcontrol,
2260 int event)
2261{
2262 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2263 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2264 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
2265
2266 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
2267 __func__, event, mux);
2268
2269 priv->mux_select[MUX_PGA_R] = mux;
2270
2271 return 0;
2272}
2273
2274static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
2275 struct snd_kcontrol *kcontrol,
2276 int event)
2277{
2278 switch (event) {
2279 case SND_SOC_DAPM_POST_PMU:
2280 usleep_range(250, 270);
2281 break;
2282 case SND_SOC_DAPM_PRE_PMD:
2283 usleep_range(250, 270);
2284 break;
2285 default:
2286 break;
2287 }
2288
2289 return 0;
2290}
2291
2292/* DAPM Widgets */
2293static const struct snd_soc_dapm_widget mt6389_dapm_widgets[] = {
2294 /* Global Supply*/
2295 SND_SOC_DAPM_SUPPLY_S("LDO_VAUD28", SUPPLY_SEQ_LDO_VAUD28,
2296 MT6389_LDO_VAUD28_CON0,
2297 RG_LDO_VAUD28_EN_SFT, 0, NULL, 0),
2298 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
2299 MT6389_AUDDEC_ANA_CON11,
2300 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
2301 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
2302 MT6389_DCXO_CW12,
2303 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
2304 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
2305 MT6389_AUDENC_ANA_CON5,
2306 RG_CLKSQ_EN_MASK_SFT, 0,
2307 mt_clksq_event,
2308 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2309 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
2310 MT6389_AUD_TOP_CKPDN_CON0,
2311 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
2312 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
2313 MT6389_AUD_TOP_CKPDN_CON0,
2314 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
2315 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
2316 MT6389_AUD_TOP_CKPDN_CON0,
2317 RG_AUD_CK_PDN_SFT, 1,
2318 mt_delay_250_event,
2319 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2320 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
2321 MT6389_AUD_TOP_CKPDN_CON0,
2322 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
2323
2324 /* Digital Clock */
2325 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
2326 MT6389_AUDIO_TOP_CON0,
2327 PDN_AFE_CTL_SFT, 1,
2328 mt_delay_250_event,
2329 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2330 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
2331 MT6389_AUDIO_TOP_CON0,
2332 PDN_DAC_CTL_SFT, 1, NULL, 0),
2333 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
2334 MT6389_AUDIO_TOP_CON0,
2335 PDN_ADC_CTL_SFT, 1, NULL, 0),
2336 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
2337 MT6389_AUDIO_TOP_CON0,
2338 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
2339 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
2340 MT6389_AUDIO_TOP_CON0,
2341 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
2342 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
2343 MT6389_AUDIO_TOP_CON0,
2344 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
2345 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
2346 MT6389_AUDIO_TOP_CON0,
2347 PDN_AFE_DL_PREDIST_CTL_SFT, 1, NULL, 0),
2348
2349 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
2350 0, 0, NULL, 0),
2351
2352 /* AFE ON */
2353 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
2354 MT6389_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
2355 NULL, 0),
2356
2357 /* AIF Rx*/
2358 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
2359 MT6389_AFE_DL_SRC2_CON0_L,
2360 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
2361 mt_aif_in_event,
2362 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2363
2364 /* DL Supply */
2365 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
2366 0, 0, NULL, 0),
2367
2368 /* DAC */
2369 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
2370
2371 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
2372
2373 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
2374
2375 /* LOL */
2376 SND_SOC_DAPM_MUX_E("LOL Mux", SND_SOC_NOPM, 0, 0,
2377 &lo_in_mux_control,
2378 mt_lo_event,
2379 SND_SOC_DAPM_PRE_PMU |
2380 SND_SOC_DAPM_PRE_PMD),
2381
2382 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6389_AUDDEC_ANA_CON5,
2383 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
2384
2385 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6389_AUDDEC_ANA_CON5,
2386 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
2387
2388 /* Headphone */
2389 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
2390 &hpl_in_mux_control,
2391 mt_hp_event,
2392 SND_SOC_DAPM_PRE_PMU |
2393 SND_SOC_DAPM_PRE_PMD),
2394
2395 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
2396 &hpr_in_mux_control,
2397 mt_hp_event,
2398 SND_SOC_DAPM_PRE_PMU |
2399 SND_SOC_DAPM_PRE_PMD),
2400
2401 /* Receiver */
2402 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2403 &rcv_in_mux_control,
2404 mt_rcv_event,
2405 SND_SOC_DAPM_PRE_PMU |
2406 SND_SOC_DAPM_PRE_PMD),
2407
2408 /* Direct output */
2409 SND_SOC_DAPM_MUX_E("DIRECT Mux", SND_SOC_NOPM, 0, 0,
2410 &direct_in_mux_control,
2411 mt_direct_event,
2412 SND_SOC_DAPM_PRE_PMU |
2413 SND_SOC_DAPM_PRE_PMD),
2414
2415 /* Direct + LO output */
2416 SND_SOC_DAPM_MUX_E("DIRECT_LO Mux", SND_SOC_NOPM, 0, 0,
2417 &direct_lo_in_mux_control,
2418 mt_direct_lo_event,
2419 SND_SOC_DAPM_PRE_PMU |
2420 SND_SOC_DAPM_PRE_PMD),
2421
2422 /* Outputs */
2423 SND_SOC_DAPM_OUTPUT("Receiver"),
2424 SND_SOC_DAPM_OUTPUT("Headphone L"),
2425 SND_SOC_DAPM_OUTPUT("Headphone R"),
2426 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
2427 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
2428 SND_SOC_DAPM_OUTPUT("LINEOUT L"),
2429 SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
2430 SND_SOC_DAPM_OUTPUT("Direct"),
2431 SND_SOC_DAPM_OUTPUT("Direct_LO"),
2432
2433 /* SGEN */
2434 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6389_AFE_SGEN_CFG0,
2435 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2436 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6389_AFE_SGEN_CFG0,
2437 SGEN_MUTE_SW_CTL_SFT, 1,
2438 mt_sgen_event,
2439 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2440 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6389_AFE_DL_SRC2_CON0_L,
2441 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2442 /* tricky, same reg/bit as "AIF_RX", reconsider */
2443
2444 SND_SOC_DAPM_INPUT("SGEN DL"),
2445
2446 /* Uplinks */
2447 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2448 SND_SOC_NOPM, 0, 0,
2449 mt_aif_out_event,
2450 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2451
2452 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
2453 SND_SOC_NOPM, 0, 0,
2454 mt_adc_supply_event,
2455 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2456
2457 /* Uplinks MUX */
2458 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2459 &aif_out_mux_control),
2460
2461 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2462 &mic_type_mux_control,
2463 mt_mic_type_event,
2464 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
2465 SND_SOC_DAPM_WILL_PMU),
2466
2467 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2468 &adc_left_mux_control,
2469 mt_adc_l_event,
2470 SND_SOC_DAPM_WILL_PMU),
2471 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2472 &adc_right_mux_control,
2473 mt_adc_r_event,
2474 SND_SOC_DAPM_WILL_PMU),
2475
2476 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2477 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2478
2479 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2480 &pga_left_mux_control,
2481 mt_pga_left_event,
2482 SND_SOC_DAPM_WILL_PMU),
2483 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2484 &pga_right_mux_control,
2485 mt_pga_right_event,
2486 SND_SOC_DAPM_WILL_PMU),
2487
2488 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2489 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2490
2491 /* UL input */
2492 SND_SOC_DAPM_INPUT("AIN0"),
2493 SND_SOC_DAPM_INPUT("AIN1"),
2494 SND_SOC_DAPM_INPUT("AIN2"),
2495};
2496
2497static const struct snd_soc_dapm_route mt6389_dapm_routes[] = {
2498 /* Capture */
2499 {"AIF1TX", NULL, "AIF Out Mux"},
2500 {"AIF1TX", NULL, "LDO_VAUD28"},
2501 {"AIF1TX", NULL, "AUDGLB"},
2502 {"AIF1TX", NULL, "CLK_BUF"},
2503 {"AIF1TX", NULL, "CLKSQ Audio"},
2504
2505 {"AIF1TX", NULL, "AUD_CK"},
2506 {"AIF1TX", NULL, "AUDIF_CK"},
2507
2508 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
2509 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
2510 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
2511 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
2512 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
2513
2514 {"AIF1TX", NULL, "AFE_ON"},
2515
2516 {"AIF Out Mux", NULL, "Mic Type Mux"},
2517
2518 {"Mic Type Mux", "ACC", "ADC L"},
2519 {"Mic Type Mux", "ACC", "ADC R"},
2520 {"Mic Type Mux", "DCC", "ADC L"},
2521 {"Mic Type Mux", "DCC", "ADC R"},
2522 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
2523 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
2524 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
2525 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
2526 {"Mic Type Mux", "DMIC", "AIN0"},
2527 {"Mic Type Mux", "DMIC", "AIN2"},
2528
2529 {"ADC L", NULL, "ADC L Mux"},
2530 {"ADC L", NULL, "ADC Supply"},
2531 {"ADC R", NULL, "ADC R Mux"},
2532 {"ADC R", NULL, "ADC Supply"},
2533
2534 {"ADC L Mux", "Left Preamplifier", "PGA L"},
2535 {"ADC R Mux", "Right Preamplifier", "PGA R"},
2536
2537 {"PGA L", NULL, "PGA L Mux"},
2538 {"PGA R", NULL, "PGA R Mux"},
2539
2540 {"PGA L Mux", "AIN0", "AIN0"},
2541 {"PGA L Mux", "AIN1", "AIN1"},
2542 {"PGA L Mux", "AIN2", "AIN2"},
2543
2544 {"PGA R Mux", "AIN0", "AIN0"},
2545 {"PGA R Mux", "AIN1", "AIN1"},
2546 {"PGA R Mux", "AIN2", "AIN2"},
2547
2548 /* DL Supply */
2549
2550 {"DL Power Supply", NULL, "LDO_VAUD28"},
2551 {"DL Power Supply", NULL, "AUDGLB"},
2552 {"DL Power Supply", NULL, "CLK_BUF"},
2553 {"DL Power Supply", NULL, "CLKSQ Audio"},
2554
2555 {"DL Power Supply", NULL, "AUDNCP_CK"},
2556 {"DL Power Supply", NULL, "ZCD13M_CK"},
2557 {"DL Power Supply", NULL, "AUD_CK"},
2558 {"DL Power Supply", NULL, "AUDIF_CK"},
2559
2560 /* DL Digital Supply */
2561 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
2562 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
2563 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
2564
2565 {"DL Digital Clock", NULL, "AFE_ON"},
2566
2567 {"AIF_RX", NULL, "DL Digital Clock"},
2568
2569 /* DL Path */
2570 {"DAC In Mux", "Normal Path", "AIF_RX"},
2571
2572 {"DAC In Mux", "Sgen", "SGEN DL"},
2573 {"SGEN DL", NULL, "SGEN DL SRC"},
2574 {"SGEN DL", NULL, "SGEN MUTE"},
2575 {"SGEN DL", NULL, "SGEN DL Enable"},
2576 {"SGEN DL", NULL, "DL Digital Clock"},
2577 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
2578
2579 {"DACL", NULL, "DAC In Mux"},
2580 {"DACL", NULL, "DL Power Supply"},
2581
2582 {"DACR", NULL, "DAC In Mux"},
2583 {"DACR", NULL, "DL Power Supply"},
2584
2585 /* Lineout Path */
2586 {"LOL Mux", "Playback", "DACL"},
2587
2588 {"LOL Buffer", NULL, "LOL Mux"},
2589 {"LOL Buffer", NULL, "LO Stability Enh"},
2590
2591 {"LINEOUT L", NULL, "LOL Buffer"},
2592
2593 /* Headphone Path */
2594 {"HPL Mux", "Audio Playback", "DACL"},
2595 {"HPR Mux", "Audio Playback", "DACR"},
2596 {"HPL Mux", "HP Impedance", "DACL"},
2597 {"HPR Mux", "HP Impedance", "DACR"},
2598 {"HPL Mux", "LoudSPK Playback", "DACL"},
2599 {"HPR Mux", "LoudSPK Playback", "DACR"},
2600
2601 {"Headphone L", NULL, "HPL Mux"},
2602 {"Headphone R", NULL, "HPR Mux"},
2603 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
2604 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
2605 {"LINEOUT L HSSPK", NULL, "HPL Mux"},
2606
2607 /* Receiver Path */
2608 {"RCV Mux", "Voice Playback", "DACL"},
2609 {"Receiver", NULL, "RCV Mux"},
2610
2611 /* Direct Path */
2612 {"DIRECT Mux", "Playback", "DACL"},
2613 {"Direct", NULL, "DIRECT Mux"},
2614
2615 /* Direct_lo Path */
2616 {"DIRECT_LO Mux", "Playback", "DACL"},
2617 {"Direct_LO", NULL, "DIRECT_LO Mux"},
2618};
2619
2620static int mt6389_codec_dai_hw_params(struct snd_pcm_substream *substream,
2621 struct snd_pcm_hw_params *params,
2622 struct snd_soc_dai *dai)
2623{
2624 struct snd_soc_component *cmpnt = dai->component;
2625 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2626 unsigned int rate = params_rate(params);
2627
2628
2629 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
2630 __func__,
2631 substream->stream,
2632 rate,
2633 substream->number);
2634
2635 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2636 priv->dl_rate = rate;
2637 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2638 priv->ul_rate = rate;
2639
2640 return 0;
2641}
2642
2643static const struct snd_soc_dai_ops mt6389_codec_dai_ops = {
2644 .hw_params = mt6389_codec_dai_hw_params,
2645};
2646
2647#define MT6389_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
2648 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
2649 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
2650 SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
2651 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
2652 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
2653
2654static struct snd_soc_dai_driver mt6389_dai_driver[] = {
2655 {
2656 .name = "mt6389-snd-codec-aif1",
2657 .playback = {
2658 .stream_name = "AIF1 Playback",
2659 .channels_min = 1,
2660 .channels_max = 2,
2661 .rates = SNDRV_PCM_RATE_8000_48000 |
2662 SNDRV_PCM_RATE_96000 |
2663 SNDRV_PCM_RATE_192000,
2664 .formats = MT6389_FORMATS,
2665 },
2666 .capture = {
2667 .stream_name = "AIF1 Capture",
2668 .channels_min = 1,
2669 .channels_max = 2,
2670 .rates = SNDRV_PCM_RATE_8000 |
2671 SNDRV_PCM_RATE_16000 |
2672 SNDRV_PCM_RATE_32000 |
2673 SNDRV_PCM_RATE_48000,
2674 .formats = MT6389_FORMATS,
2675 },
2676 .ops = &mt6389_codec_dai_ops,
2677 },
2678};
2679
2680static int mt6389_codec_init_reg(struct mt6389_priv *priv)
2681{
2682 int ret = 0;
2683 unsigned int value;
2684
2685 /* enable LDO_VAUD28 */
2686 regmap_update_bits(priv->regmap, MT6389_LDO_VAUD28_CON0,
2687 0x1 << RG_LDO_VAUD28_EN_SFT,
2688 0x1 << RG_LDO_VAUD28_EN_SFT);
2689
2690 /* enable clk buf */
2691 regmap_update_bits(priv->regmap, MT6389_DCXO_CW12,
2692 0x1 << RG_XO_AUDIO_EN_M_SFT,
2693 0x1 << RG_XO_AUDIO_EN_M_SFT);
2694
2695 /* set those not controlled by dapm widget */
2696
2697 /* audio clk source from internal dcxo */
2698 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
2699 RG_CLKSQ_IN_SEL_MASK_SFT,
2700 0 << RG_CLKSQ_IN_SEL_SFT);
2701 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
2702 RG_CLKSQ_EN_MASK_SFT,
2703 1 << RG_CLKSQ_EN_SFT);
2704 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON5, &value);
2705
2706 /* Reset OUT1 output select none */
2707 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON0,
2708 0x0700, 0x0000);
2709 /* Disable voice short circuit protection */
2710 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON4,
2711 RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
2712 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
2713 /* disable LO buffer left short circuit protection */
2714 regmap_update_bits(priv->regmap, MT6389_AUDDEC_ANA_CON5,
2715 RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
2716 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);
2717
2718 /* gpio miso driving set to 4mA */
2719 regmap_write(priv->regmap, MT6389_DRV_CON3, 0xcccc);
2720
2721 /* set gpio smt */
2722 gpio_smt_set(priv);
2723
2724 /* set gpio */
2725 playback_gpio_reset(priv);
2726 capture_gpio_reset(priv);
2727
2728 /* disable clk buf */
2729 regmap_update_bits(priv->regmap, MT6389_AUDENC_ANA_CON5,
2730 RG_CLKSQ_EN_MASK_SFT,
2731 0 << RG_CLKSQ_EN_SFT);
2732 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON5, &value);
2733
2734 /* disable clk buf */
2735 regmap_update_bits(priv->regmap, MT6389_DCXO_CW12,
2736 0x1 << RG_XO_AUDIO_EN_M_SFT,
2737 0x0 << RG_XO_AUDIO_EN_M_SFT);
2738
2739 /* disable LDO_VAUD28 */
2740 regmap_update_bits(priv->regmap, MT6389_LDO_VAUD28_CON0,
2741 0x1 << RG_LDO_VAUD28_EN_SFT,
2742 0x0 << RG_LDO_VAUD28_EN_SFT);
2743
2744 return ret;
2745}
2746
2747static int mt6389_codec_probe(struct snd_soc_codec *codec)
2748{
2749 struct snd_soc_component *cmpnt = &codec->component;
2750 struct mt6389_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2751
2752 snd_soc_component_init_regmap(cmpnt, priv->regmap);
2753
2754 /* add codec controls */
2755 snd_soc_add_component_controls(cmpnt,
2756 mt6389_snd_controls,
2757 ARRAY_SIZE(mt6389_snd_controls));
2758 snd_soc_add_component_controls(cmpnt,
2759 mt6389_snd_ul_controls,
2760 ARRAY_SIZE(mt6389_snd_ul_controls));
2761
2762 mt6389_codec_init_reg(priv);
2763 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = 8;
2764 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = 8;
2765 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = 0;
2766 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = 0;
2767 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = 3;
2768 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = 3;
2769 return 0;
2770}
2771
2772static struct snd_soc_codec_driver mt6389_soc_codec_driver = {
2773 .probe = mt6389_codec_probe,
2774 .component_driver = {
2775 .dapm_widgets = mt6389_dapm_widgets,
2776 .num_dapm_widgets = ARRAY_SIZE(mt6389_dapm_widgets),
2777 .dapm_routes = mt6389_dapm_routes,
2778 .num_dapm_routes = ARRAY_SIZE(mt6389_dapm_routes),
2779 },
2780};
2781
2782static void debug_write_reg(struct file *file, void *arg)
2783{
2784 struct mt6389_priv *priv = file->private_data;
2785 char *token1 = NULL;
2786 char *token2 = NULL;
2787 char *temp = arg;
2788 char delim[] = " ,";
2789 unsigned int reg_addr = 0;
2790 unsigned int reg_value = 0;
2791 int ret = 0;
2792
2793 token1 = strsep(&temp, delim);
2794 token2 = strsep(&temp, delim);
2795 dev_info(priv->dev, "%s(), token1 = %s, token2 = %s, temp = %s\n",
2796 __func__, token1, token2, temp);
2797
2798 if ((token1 != NULL) && (token2 != NULL)) {
2799 ret = kstrtouint(token1, 16, &reg_addr);
2800 ret = kstrtouint(token2, 16, &reg_value);
2801 dev_info(priv->dev, "%s(), reg_addr = 0x%x, reg_value = 0x%x\n",
2802 __func__,
2803 reg_addr, reg_value);
2804 regmap_write(priv->regmap, reg_addr, reg_value);
2805 regmap_read(priv->regmap, reg_addr, &reg_value);
2806 dev_info(priv->dev, "%s(), reg_addr = 0x%x, reg_value = 0x%x\n",
2807 __func__,
2808 reg_addr, reg_value);
2809 } else {
2810 dev_info(priv->dev, "token1 or token2 is NULL!\n");
2811 }
2812}
2813
2814static void debug_set_debug_flag(struct file *file, void *arg)
2815{
2816 struct mt6389_priv *priv = file->private_data;
2817 char *token1 = NULL;
2818 char *temp = arg;
2819 char delim[] = " ,";
2820 int ret = 0;
2821 unsigned int value;
2822
2823 token1 = strsep(&temp, delim);
2824 dev_info(priv->dev, "%s(), token1 = %s, temp = %s\n",
2825 __func__, token1, temp);
2826
2827 if (token1 != NULL) {
2828 ret = kstrtouint(token1, 16, &value);
2829 priv->debug_flag = value;
2830 } else {
2831 dev_info(priv->dev, "%s(), token1 is NULL!\n", __func__);
2832 }
2833}
2834
2835struct command_function {
2836 const char *cmd;
2837 void (*fn)(struct file *, void *);
2838};
2839
2840#define CMD_FN(_cmd, _fn) { \
2841 .cmd = _cmd, \
2842 .fn = _fn, \
2843}
2844
2845static const struct command_function debug_cmds[] = {
2846 CMD_FN("write_reg", debug_write_reg),
2847 CMD_FN("set_debug_flag", debug_set_debug_flag),
2848 {}
2849};
2850
2851static int mt6389_debugfs_open(struct inode *inode, struct file *file)
2852{
2853 file->private_data = inode->i_private;
2854 return 0;
2855}
2856
2857static ssize_t mt6389_debugfs_read(struct file *file, char __user *buf,
2858 size_t count, loff_t *pos)
2859{
2860 struct mt6389_priv *priv = file->private_data;
2861 const int size = 12288;
2862 char *buffer = NULL; /* for reduce kernel stack */
2863 int n = 0;
2864 unsigned int value;
2865 int ret = 0;
2866
2867 buffer = kmalloc(size, GFP_KERNEL);
2868 if (!buffer)
2869 return -ENOMEM;
2870
2871 n += scnprintf(buffer + n, size - n, "mtkaif_protocol = %d\n",
2872 priv->mtkaif_protocol);
2873
2874 n += scnprintf(buffer + n, size - n, "debug_flag = 0x%x\n",
2875 priv->debug_flag);
2876
2877 regmap_read(priv->regmap, MT6389_DRV_CON3, &value);
2878 n += scnprintf(buffer + n, size - n,
2879 "MT6389_DRV_CON3 = 0x%x\n", value);
2880 regmap_read(priv->regmap, MT6389_GPIO_DIR0, &value);
2881 n += scnprintf(buffer + n, size - n,
2882 "MT6389_GPIO_DIR0 = 0x%x\n", value);
2883 regmap_read(priv->regmap, MT6389_GPIO_MODE2, &value);
2884 n += scnprintf(buffer + n, size - n,
2885 "MT6389_GPIO_MODE2 = 0x%x\n", value);
2886 regmap_read(priv->regmap, MT6389_GPIO_MODE3, &value);
2887 n += scnprintf(buffer + n, size - n,
2888 "MT6389_GPIO_MODE3 = 0x%x\n", value);
2889 regmap_read(priv->regmap, MT6389_DCXO_CW12, &value);
2890 n += scnprintf(buffer + n, size - n,
2891 "MT6389_DCXO_CW12 = 0x%x\n", value);
2892 regmap_read(priv->regmap, MT6389_LDO_VAUD28_CON0, &value);
2893 n += scnprintf(buffer + n, size - n,
2894 "MT6389_LDO_VAUD28_CON0 = 0x%x\n", value);
2895 regmap_read(priv->regmap, MT6389_AUXADC_CON10, &value);
2896 n += scnprintf(buffer + n, size - n,
2897 "MT6389_AUXADC_CON10 = 0x%x\n", value);
2898 regmap_read(priv->regmap, MT6389_AUD_TOP_ID, &value);
2899 n += scnprintf(buffer + n, size - n,
2900 "MT6389_AUD_TOP_ID = 0x%x\n", value);
2901 regmap_read(priv->regmap, MT6389_AUD_TOP_REV0, &value);
2902 n += scnprintf(buffer + n, size - n,
2903 "MT6389_AUD_TOP_REV0 = 0x%x\n", value);
2904 regmap_read(priv->regmap, MT6389_AUD_TOP_DBI, &value);
2905 n += scnprintf(buffer + n, size - n,
2906 "MT6389_AUD_TOP_DBI = 0x%x\n", value);
2907 regmap_read(priv->regmap, MT6389_AUD_TOP_DXI, &value);
2908 n += scnprintf(buffer + n, size - n,
2909 "MT6389_AUD_TOP_DXI = 0x%x\n", value);
2910 regmap_read(priv->regmap, MT6389_AUD_TOP_CKPDN_TPM0, &value);
2911 n += scnprintf(buffer + n, size - n,
2912 "MT6389_AUD_TOP_CKPDN_TPM0 = 0x%x\n", value);
2913 regmap_read(priv->regmap, MT6389_AUD_TOP_CKPDN_TPM1, &value);
2914 n += scnprintf(buffer + n, size - n,
2915 "MT6389_AUD_TOP_CKPDN_TPM1 = 0x%x\n", value);
2916 regmap_read(priv->regmap, MT6389_AUD_TOP_CKPDN_CON0, &value);
2917 n += scnprintf(buffer + n, size - n,
2918 "MT6389_AUD_TOP_CKPDN_CON0 = 0x%x\n", value);
2919 regmap_read(priv->regmap, MT6389_AUD_TOP_CKPDN_CON0_SET, &value);
2920 n += scnprintf(buffer + n, size - n,
2921 "MT6389_AUD_TOP_CKPDN_CON0_SET = 0x%x\n", value);
2922 regmap_read(priv->regmap, MT6389_AUD_TOP_CKPDN_CON0_CLR, &value);
2923 n += scnprintf(buffer + n, size - n,
2924 "MT6389_AUD_TOP_CKPDN_CON0_CLR = 0x%x\n", value);
2925 regmap_read(priv->regmap, MT6389_AUD_TOP_CKSEL_CON0, &value);
2926 n += scnprintf(buffer + n, size - n,
2927 "MT6389_AUD_TOP_CKSEL_CON0 = 0x%x\n", value);
2928 regmap_read(priv->regmap, MT6389_AUD_TOP_CKSEL_CON0_SET, &value);
2929 n += scnprintf(buffer + n, size - n,
2930 "MT6389_AUD_TOP_CKSEL_CON0_SET = 0x%x\n", value);
2931 regmap_read(priv->regmap, MT6389_AUD_TOP_CKSEL_CON0_CLR, &value);
2932 n += scnprintf(buffer + n, size - n,
2933 "MT6389_AUD_TOP_CKSEL_CON0_CLR = 0x%x\n", value);
2934 regmap_read(priv->regmap, MT6389_AUD_TOP_CKTST_CON0, &value);
2935 n += scnprintf(buffer + n, size - n,
2936 "MT6389_AUD_TOP_CKTST_CON0 = 0x%x\n", value);
2937 regmap_read(priv->regmap, MT6389_AUD_TOP_CLK_HWEN_CON0, &value);
2938 n += scnprintf(buffer + n, size - n,
2939 "MT6389_AUD_TOP_CLK_HWEN_CON0 = 0x%x\n", value);
2940 regmap_read(priv->regmap, MT6389_AUD_TOP_CLK_HWEN_CON0_SET, &value);
2941 n += scnprintf(buffer + n, size - n,
2942 "MT6389_AUD_TOP_CLK_HWEN_CON0_SET = 0x%x\n", value);
2943 regmap_read(priv->regmap, MT6389_AUD_TOP_CLK_HWEN_CON0_CLR, &value);
2944 n += scnprintf(buffer + n, size - n,
2945 "MT6389_AUD_TOP_CLK_HWEN_CON0_CLR = 0x%x\n", value);
2946 regmap_read(priv->regmap, MT6389_AUD_TOP_RST_CON0, &value);
2947 n += scnprintf(buffer + n, size - n,
2948 "MT6389_AUD_TOP_RST_CON0 = 0x%x\n", value);
2949 regmap_read(priv->regmap, MT6389_AUD_TOP_RST_CON0_SET, &value);
2950 n += scnprintf(buffer + n, size - n,
2951 "MT6389_AUD_TOP_RST_CON0_SET = 0x%x\n", value);
2952 regmap_read(priv->regmap, MT6389_AUD_TOP_RST_CON0_CLR, &value);
2953 n += scnprintf(buffer + n, size - n,
2954 "MT6389_AUD_TOP_RST_CON0_CLR = 0x%x\n", value);
2955 regmap_read(priv->regmap, MT6389_AUD_TOP_RST_BANK_CON0, &value);
2956 n += scnprintf(buffer + n, size - n,
2957 "MT6389_AUD_TOP_RST_BANK_CON0 = 0x%x\n", value);
2958 regmap_read(priv->regmap, MT6389_AUD_TOP_INT_CON0, &value);
2959 n += scnprintf(buffer + n, size - n,
2960 "MT6389_AUD_TOP_INT_CON0 = 0x%x\n", value);
2961 regmap_read(priv->regmap, MT6389_AUD_TOP_INT_CON0_SET, &value);
2962 n += scnprintf(buffer + n, size - n,
2963 "MT6389_AUD_TOP_INT_CON0_SET = 0x%x\n", value);
2964 regmap_read(priv->regmap, MT6389_AUD_TOP_INT_CON0_CLR, &value);
2965 n += scnprintf(buffer + n, size - n,
2966 "MT6389_AUD_TOP_INT_CON0_CLR = 0x%x\n", value);
2967 regmap_read(priv->regmap, MT6389_AUD_TOP_INT_MASK_CON0, &value);
2968 n += scnprintf(buffer + n, size - n,
2969 "MT6389_AUD_TOP_INT_MASK_CON0 = 0x%x\n", value);
2970 regmap_read(priv->regmap, MT6389_AUD_TOP_INT_MASK_CON0_SET, &value);
2971 n += scnprintf(buffer + n, size - n,
2972 "MT6389_AUD_TOP_INT_MASK_CON0_SET = 0x%x\n", value);
2973 regmap_read(priv->regmap, MT6389_AUD_TOP_INT_MASK_CON0_CLR, &value);
2974 n += scnprintf(buffer + n, size - n,
2975 "MT6389_AUD_TOP_INT_MASK_CON0_CLR = 0x%x\n", value);
2976 regmap_read(priv->regmap, MT6389_AUD_TOP_INT_STATUS0, &value);
2977 n += scnprintf(buffer + n, size - n,
2978 "MT6389_AUD_TOP_INT_STATUS0 = 0x%x\n", value);
2979 regmap_read(priv->regmap, MT6389_AUD_TOP_INT_RAW_STATUS0, &value);
2980 n += scnprintf(buffer + n, size - n,
2981 "MT6389_AUD_TOP_INT_RAW_STATUS0 = 0x%x\n", value);
2982 regmap_read(priv->regmap, MT6389_AUD_TOP_INT_MISC_CON0, &value);
2983 n += scnprintf(buffer + n, size - n,
2984 "MT6389_AUD_TOP_INT_MISC_CON0 = 0x%x\n", value);
2985 regmap_read(priv->regmap, MT6389_AUDNCP_CLKDIV_CON0, &value);
2986 n += scnprintf(buffer + n, size - n,
2987 "MT6389_AUDNCP_CLKDIV_CON0 = 0x%x\n", value);
2988 regmap_read(priv->regmap, MT6389_AUDNCP_CLKDIV_CON1, &value);
2989 n += scnprintf(buffer + n, size - n,
2990 "MT6389_AUDNCP_CLKDIV_CON1 = 0x%x\n", value);
2991 regmap_read(priv->regmap, MT6389_AUDNCP_CLKDIV_CON2, &value);
2992 n += scnprintf(buffer + n, size - n,
2993 "MT6389_AUDNCP_CLKDIV_CON2 = 0x%x\n", value);
2994 regmap_read(priv->regmap, MT6389_AUDNCP_CLKDIV_CON3, &value);
2995 n += scnprintf(buffer + n, size - n,
2996 "MT6389_AUDNCP_CLKDIV_CON3 = 0x%x\n", value);
2997 regmap_read(priv->regmap, MT6389_AUDNCP_CLKDIV_CON4, &value);
2998 n += scnprintf(buffer + n, size - n,
2999 "MT6389_AUDNCP_CLKDIV_CON4 = 0x%x\n", value);
3000 regmap_read(priv->regmap, MT6389_AUD_TOP_MON_CON0, &value);
3001 n += scnprintf(buffer + n, size - n,
3002 "MT6389_AUD_TOP_MON_CON0 = 0x%x\n", value);
3003 regmap_read(priv->regmap, MT6389_AUDIO_DIG_DSN_ID, &value);
3004 n += scnprintf(buffer + n, size - n,
3005 "MT6389_AUDIO_DIG_DSN_ID = 0x%x\n", value);
3006 regmap_read(priv->regmap, MT6389_AUDIO_DIG_DSN_REV0, &value);
3007 n += scnprintf(buffer + n, size - n,
3008 "MT6389_AUDIO_DIG_DSN_REV0 = 0x%x\n", value);
3009 regmap_read(priv->regmap, MT6389_AUDIO_DIG_DSN_DBI, &value);
3010 n += scnprintf(buffer + n, size - n,
3011 "MT6389_AUDIO_DIG_DSN_DBI = 0x%x\n", value);
3012 regmap_read(priv->regmap, MT6389_AUDIO_DIG_DSN_DXI, &value);
3013 n += scnprintf(buffer + n, size - n,
3014 "MT6389_AUDIO_DIG_DSN_DXI = 0x%x\n", value);
3015 regmap_read(priv->regmap, MT6389_AFE_UL_DL_CON0, &value);
3016 n += scnprintf(buffer + n, size - n,
3017 "MT6389_AFE_UL_DL_CON0 = 0x%x\n", value);
3018 regmap_read(priv->regmap, MT6389_AFE_DL_SRC2_CON0_L, &value);
3019 n += scnprintf(buffer + n, size - n,
3020 "MT6389_AFE_DL_SRC2_CON0_L = 0x%x\n", value);
3021 regmap_read(priv->regmap, MT6389_AFE_UL_SRC_CON0_H, &value);
3022 n += scnprintf(buffer + n, size - n,
3023 "MT6389_AFE_UL_SRC_CON0_H = 0x%x\n", value);
3024 regmap_read(priv->regmap, MT6389_AFE_UL_SRC_CON0_L, &value);
3025 n += scnprintf(buffer + n, size - n,
3026 "MT6389_AFE_UL_SRC_CON0_L = 0x%x\n", value);
3027 regmap_read(priv->regmap, MT6389_AFE_TOP_CON0, &value);
3028 n += scnprintf(buffer + n, size - n,
3029 "MT6389_AFE_TOP_CON0 = 0x%x\n", value);
3030 regmap_read(priv->regmap, MT6389_AUDIO_TOP_CON0, &value);
3031 n += scnprintf(buffer + n, size - n,
3032 "MT6389_AUDIO_TOP_CON0 = 0x%x\n", value);
3033 regmap_read(priv->regmap, MT6389_AFE_MON_DEBUG0, &value);
3034 n += scnprintf(buffer + n, size - n,
3035 "MT6389_AFE_MON_DEBUG0 = 0x%x\n", value);
3036 regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON0, &value);
3037 n += scnprintf(buffer + n, size - n,
3038 "MT6389_AFUNC_AUD_CON0 = 0x%x\n", value);
3039 regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON1, &value);
3040 n += scnprintf(buffer + n, size - n,
3041 "MT6389_AFUNC_AUD_CON1 = 0x%x\n", value);
3042 regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON2, &value);
3043 n += scnprintf(buffer + n, size - n,
3044 "MT6389_AFUNC_AUD_CON2 = 0x%x\n", value);
3045 regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON3, &value);
3046 n += scnprintf(buffer + n, size - n,
3047 "MT6389_AFUNC_AUD_CON3 = 0x%x\n", value);
3048 regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON4, &value);
3049 n += scnprintf(buffer + n, size - n,
3050 "MT6389_AFUNC_AUD_CON4 = 0x%x\n", value);
3051 regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON5, &value);
3052 n += scnprintf(buffer + n, size - n,
3053 "MT6389_AFUNC_AUD_CON5 = 0x%x\n", value);
3054 regmap_read(priv->regmap, MT6389_AFUNC_AUD_CON6, &value);
3055 n += scnprintf(buffer + n, size - n,
3056 "MT6389_AFUNC_AUD_CON6 = 0x%x\n", value);
3057 regmap_read(priv->regmap, MT6389_AFUNC_AUD_MON0, &value);
3058 n += scnprintf(buffer + n, size - n,
3059 "MT6389_AFUNC_AUD_MON0 = 0x%x\n", value);
3060 regmap_read(priv->regmap, MT6389_AUDRC_TUNE_MON0, &value);
3061 n += scnprintf(buffer + n, size - n,
3062 "MT6389_AUDRC_TUNE_MON0 = 0x%x\n", value);
3063 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_FIFO_CFG0, &value);
3064 n += scnprintf(buffer + n, size - n,
3065 "MT6389_AFE_ADDA_MTKAIF_FIFO_CFG0 = 0x%x\n", value);
3066 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_FIFO_LOG_MON1, &value);
3067 n += scnprintf(buffer + n, size - n,
3068 "MT6389_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 = 0x%x\n",
3069 value);
3070 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_MON0, &value);
3071 n += scnprintf(buffer + n, size - n,
3072 "MT6389_AFE_ADDA_MTKAIF_MON0 = 0x%x\n", value);
3073 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_MON1, &value);
3074 n += scnprintf(buffer + n, size - n,
3075 "MT6389_AFE_ADDA_MTKAIF_MON1 = 0x%x\n", value);
3076 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_MON2, &value);
3077 n += scnprintf(buffer + n, size - n,
3078 "MT6389_AFE_ADDA_MTKAIF_MON2 = 0x%x\n", value);
3079 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_MON3, &value);
3080 n += scnprintf(buffer + n, size - n,
3081 "MT6389_AFE_ADDA_MTKAIF_MON3 = 0x%x\n", value);
3082 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_CFG0, &value);
3083 n += scnprintf(buffer + n, size - n,
3084 "MT6389_AFE_ADDA_MTKAIF_CFG0 = 0x%x\n", value);
3085 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_RX_CFG0, &value);
3086 n += scnprintf(buffer + n, size - n,
3087 "MT6389_AFE_ADDA_MTKAIF_RX_CFG0 = 0x%x\n", value);
3088 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_RX_CFG1, &value);
3089 n += scnprintf(buffer + n, size - n,
3090 "MT6389_AFE_ADDA_MTKAIF_RX_CFG1 = 0x%x\n", value);
3091 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_RX_CFG2, &value);
3092 n += scnprintf(buffer + n, size - n,
3093 "MT6389_AFE_ADDA_MTKAIF_RX_CFG2 = 0x%x\n", value);
3094 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_RX_CFG3, &value);
3095 n += scnprintf(buffer + n, size - n,
3096 "MT6389_AFE_ADDA_MTKAIF_RX_CFG3 = 0x%x\n", value);
3097 regmap_read(priv->regmap, MT6389_AFE_ADDA_MTKAIF_TX_CFG1, &value);
3098 n += scnprintf(buffer + n, size - n,
3099 "MT6389_AFE_ADDA_MTKAIF_TX_CFG1 = 0x%x\n", value);
3100 regmap_read(priv->regmap, MT6389_AFE_SGEN_CFG0, &value);
3101 n += scnprintf(buffer + n, size - n,
3102 "MT6389_AFE_SGEN_CFG0 = 0x%x\n", value);
3103 regmap_read(priv->regmap, MT6389_AFE_SGEN_CFG1, &value);
3104 n += scnprintf(buffer + n, size - n,
3105 "MT6389_AFE_SGEN_CFG1 = 0x%x\n", value);
3106 regmap_read(priv->regmap, MT6389_AFE_ADC_ASYNC_FIFO_CFG, &value);
3107 n += scnprintf(buffer + n, size - n,
3108 "MT6389_AFE_ADC_ASYNC_FIFO_CFG = 0x%x\n", value);
3109 regmap_read(priv->regmap, MT6389_AFE_DCCLK_CFG0, &value);
3110 n += scnprintf(buffer + n, size - n,
3111 "MT6389_AFE_DCCLK_CFG0 = 0x%x\n", value);
3112 regmap_read(priv->regmap, MT6389_AFE_DCCLK_CFG1, &value);
3113 n += scnprintf(buffer + n, size - n,
3114 "MT6389_AFE_DCCLK_CFG1 = 0x%x\n", value);
3115 regmap_read(priv->regmap, MT6389_AUDIO_DIG_CFG, &value);
3116 n += scnprintf(buffer + n, size - n,
3117 "MT6389_AUDIO_DIG_CFG = 0x%x\n", value);
3118 regmap_read(priv->regmap, MT6389_AFE_AUD_PAD_TOP, &value);
3119 n += scnprintf(buffer + n, size - n,
3120 "MT6389_AFE_AUD_PAD_TOP = 0x%x\n", value);
3121 regmap_read(priv->regmap, MT6389_AFE_AUD_PAD_TOP_MON, &value);
3122 n += scnprintf(buffer + n, size - n,
3123 "MT6389_AFE_AUD_PAD_TOP_MON = 0x%x\n", value);
3124 regmap_read(priv->regmap, MT6389_AFE_AUD_PAD_TOP_MON1, &value);
3125 n += scnprintf(buffer + n, size - n,
3126 "MT6389_AFE_AUD_PAD_TOP_MON1 = 0x%x\n", value);
3127 regmap_read(priv->regmap, MT6389_AFE_CG_EN_MON, &value);
3128 n += scnprintf(buffer + n, size - n,
3129 "MT6389_AFE_CG_EN_MON = 0x%x\n", value);
3130 regmap_read(priv->regmap, MT6389_AUDENC_DSN_ID, &value);
3131 n += scnprintf(buffer + n, size - n,
3132 "MT6389_AUDENC_DSN_ID = 0x%x\n", value);
3133 regmap_read(priv->regmap, MT6389_AUDENC_DSN_REV0, &value);
3134 n += scnprintf(buffer + n, size - n,
3135 "MT6389_AUDENC_DSN_REV0 = 0x%x\n", value);
3136 regmap_read(priv->regmap, MT6389_AUDENC_DSN_DBI, &value);
3137 n += scnprintf(buffer + n, size - n,
3138 "MT6389_AUDENC_DSN_DBI = 0x%x\n", value);
3139 regmap_read(priv->regmap, MT6389_AUDENC_DSN_FPI, &value);
3140 n += scnprintf(buffer + n, size - n,
3141 "MT6389_AUDENC_DSN_FPI = 0x%x\n", value);
3142 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON0, &value);
3143 n += scnprintf(buffer + n, size - n,
3144 "MT6389_AUDENC_ANA_CON0 = 0x%x\n", value);
3145 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON1, &value);
3146 n += scnprintf(buffer + n, size - n,
3147 "MT6389_AUDENC_ANA_CON1 = 0x%x\n", value);
3148 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON2, &value);
3149 n += scnprintf(buffer + n, size - n,
3150 "MT6389_AUDENC_ANA_CON2 = 0x%x\n", value);
3151 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON3, &value);
3152 n += scnprintf(buffer + n, size - n,
3153 "MT6389_AUDENC_ANA_CON3 = 0x%x\n", value);
3154 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON4, &value);
3155 n += scnprintf(buffer + n, size - n,
3156 "MT6389_AUDENC_ANA_CON4 = 0x%x\n", value);
3157 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON5, &value);
3158 n += scnprintf(buffer + n, size - n,
3159 "MT6389_AUDENC_ANA_CON5 = 0x%x\n", value);
3160 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON6, &value);
3161 n += scnprintf(buffer + n, size - n,
3162 "MT6389_AUDENC_ANA_CON6 = 0x%x\n", value);
3163 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON7, &value);
3164 n += scnprintf(buffer + n, size - n,
3165 "MT6389_AUDENC_ANA_CON7 = 0x%x\n", value);
3166 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON8, &value);
3167 n += scnprintf(buffer + n, size - n,
3168 "MT6389_AUDENC_ANA_CON8 = 0x%x\n", value);
3169 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON9, &value);
3170 n += scnprintf(buffer + n, size - n,
3171 "MT6389_AUDENC_ANA_CON9 = 0x%x\n", value);
3172 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON10, &value);
3173 n += scnprintf(buffer + n, size - n,
3174 "MT6389_AUDENC_ANA_CON10 = 0x%x\n", value);
3175 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON11, &value);
3176 n += scnprintf(buffer + n, size - n,
3177 "MT6389_AUDENC_ANA_CON11 = 0x%x\n", value);
3178 regmap_read(priv->regmap, MT6389_AUDENC_ANA_CON12, &value);
3179 n += scnprintf(buffer + n, size - n,
3180 "MT6389_AUDENC_ANA_CON12 = 0x%x\n", value);
3181 regmap_read(priv->regmap, MT6389_AUDDEC_DSN_ID, &value);
3182 n += scnprintf(buffer + n, size - n,
3183 "MT6389_AUDDEC_DSN_ID = 0x%x\n", value);
3184 regmap_read(priv->regmap, MT6389_AUDDEC_DSN_REV0, &value);
3185 n += scnprintf(buffer + n, size - n,
3186 "MT6389_AUDDEC_DSN_REV0 = 0x%x\n", value);
3187 regmap_read(priv->regmap, MT6389_AUDDEC_DSN_DBI, &value);
3188 n += scnprintf(buffer + n, size - n,
3189 "MT6389_AUDDEC_DSN_DBI = 0x%x\n", value);
3190 regmap_read(priv->regmap, MT6389_AUDDEC_DSN_FPI, &value);
3191 n += scnprintf(buffer + n, size - n,
3192 "MT6389_AUDDEC_DSN_FPI = 0x%x\n", value);
3193 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON0, &value);
3194 n += scnprintf(buffer + n, size - n,
3195 "MT6389_AUDDEC_ANA_CON0 = 0x%x\n", value);
3196 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON1, &value);
3197 n += scnprintf(buffer + n, size - n,
3198 "MT6389_AUDDEC_ANA_CON1 = 0x%x\n", value);
3199 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON2, &value);
3200 n += scnprintf(buffer + n, size - n,
3201 "MT6389_AUDDEC_ANA_CON2 = 0x%x\n", value);
3202 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON3, &value);
3203 n += scnprintf(buffer + n, size - n,
3204 "MT6389_AUDDEC_ANA_CON3 = 0x%x\n", value);
3205 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON4, &value);
3206 n += scnprintf(buffer + n, size - n,
3207 "MT6389_AUDDEC_ANA_CON4 = 0x%x\n", value);
3208 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON5, &value);
3209 n += scnprintf(buffer + n, size - n,
3210 "MT6389_AUDDEC_ANA_CON5 = 0x%x\n", value);
3211 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON6, &value);
3212 n += scnprintf(buffer + n, size - n,
3213 "MT6389_AUDDEC_ANA_CON6 = 0x%x\n", value);
3214 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON7, &value);
3215 n += scnprintf(buffer + n, size - n,
3216 "MT6389_AUDDEC_ANA_CON7 = 0x%x\n", value);
3217 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON8, &value);
3218 n += scnprintf(buffer + n, size - n,
3219 "MT6389_AUDDEC_ANA_CON8 = 0x%x\n", value);
3220 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON9, &value);
3221 n += scnprintf(buffer + n, size - n,
3222 "MT6389_AUDDEC_ANA_CON9 = 0x%x\n", value);
3223 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON10, &value);
3224 n += scnprintf(buffer + n, size - n,
3225 "MT6389_AUDDEC_ANA_CON10 = 0x%x\n", value);
3226 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON11, &value);
3227 n += scnprintf(buffer + n, size - n,
3228 "MT6389_AUDDEC_ANA_CON11 = 0x%x\n", value);
3229 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON12, &value);
3230 n += scnprintf(buffer + n, size - n,
3231 "MT6389_AUDDEC_ANA_CON12 = 0x%x\n", value);
3232 regmap_read(priv->regmap, MT6389_AUDDEC_ANA_CON13, &value);
3233 n += scnprintf(buffer + n, size - n,
3234 "MT6389_AUDDEC_ANA_CON13 = 0x%x\n", value);
3235 regmap_read(priv->regmap, MT6389_AUDDEC_ELR_NUM, &value);
3236 n += scnprintf(buffer + n, size - n,
3237 "MT6389_AUDDEC_ELR_NUM = 0x%x\n", value);
3238 regmap_read(priv->regmap, MT6389_AUDDEC_ELR_0, &value);
3239 n += scnprintf(buffer + n, size - n,
3240 "MT6389_AUDDEC_ELR_0 = 0x%x\n", value);
3241 regmap_read(priv->regmap, MT6389_AUDZCD_DSN_ID, &value);
3242 n += scnprintf(buffer + n, size - n,
3243 "MT6389_AUDZCD_DSN_ID = 0x%x\n", value);
3244 regmap_read(priv->regmap, MT6389_AUDZCD_DSN_REV0, &value);
3245 n += scnprintf(buffer + n, size - n,
3246 "MT6389_AUDZCD_DSN_REV0 = 0x%x\n", value);
3247 regmap_read(priv->regmap, MT6389_AUDZCD_DSN_DBI, &value);
3248 n += scnprintf(buffer + n, size - n,
3249 "MT6389_AUDZCD_DSN_DBI = 0x%x\n", value);
3250 regmap_read(priv->regmap, MT6389_AUDZCD_DSN_FPI, &value);
3251 n += scnprintf(buffer + n, size - n,
3252 "MT6389_AUDZCD_DSN_FPI = 0x%x\n", value);
3253 regmap_read(priv->regmap, MT6389_ZCD_CON0, &value);
3254 n += scnprintf(buffer + n, size - n,
3255 "MT6389_ZCD_CON0 = 0x%x\n", value);
3256 regmap_read(priv->regmap, MT6389_ZCD_CON1, &value);
3257 n += scnprintf(buffer + n, size - n,
3258 "MT6389_ZCD_CON1 = 0x%x\n", value);
3259 regmap_read(priv->regmap, MT6389_ZCD_CON2, &value);
3260 n += scnprintf(buffer + n, size - n,
3261 "MT6389_ZCD_CON2 = 0x%x\n", value);
3262 regmap_read(priv->regmap, MT6389_ZCD_CON3, &value);
3263 n += scnprintf(buffer + n, size - n,
3264 "MT6389_ZCD_CON3 = 0x%x\n", value);
3265 regmap_read(priv->regmap, MT6389_ZCD_CON4, &value);
3266 n += scnprintf(buffer + n, size - n,
3267 "MT6389_ZCD_CON4 = 0x%x\n", value);
3268 regmap_read(priv->regmap, MT6389_ZCD_CON5, &value);
3269 n += scnprintf(buffer + n, size - n,
3270 "MT6389_ZCD_CON5 = 0x%x\n", value);
3271 regmap_read(priv->regmap, MT6389_SMT_CON1, &value);
3272 n += scnprintf(buffer + n, size - n,
3273 "MT6359_SMT_CON1 = 0x%x\n", value);
3274
3275 ret = simple_read_from_buffer(buf, count, pos, buffer, n);
3276 kfree(buffer);
3277 return ret;
3278}
3279
3280static ssize_t mt6389_debugfs_write(struct file *f, const char __user *buf,
3281 size_t count, loff_t *offset)
3282{
3283#define MAX_DEBUG_WRITE_INPUT 256
3284 struct mt6389_priv *priv = f->private_data;
3285 char input[MAX_DEBUG_WRITE_INPUT];
3286 char *temp = NULL;
3287 char *command = NULL;
3288 char *str_begin = NULL;
3289 char delim[] = " ,";
3290 const struct command_function *cf;
3291
3292 if (!count) {
3293 dev_info(priv->dev, "%s(), count is 0, return directly\n",
3294 __func__);
3295 goto exit;
3296 }
3297
3298 if (count > MAX_DEBUG_WRITE_INPUT)
3299 count = MAX_DEBUG_WRITE_INPUT;
3300
3301 memset((void *)input, 0, MAX_DEBUG_WRITE_INPUT);
3302
3303 if (copy_from_user(input, buf, count))
3304 dev_info(priv->dev, "%s(), copy_from_user fail, count = %zu\n",
3305 __func__, count);
3306
3307 str_begin = kstrndup(input, MAX_DEBUG_WRITE_INPUT - 1,
3308 GFP_KERNEL);
3309 if (!str_begin) {
3310 dev_info(priv->dev, "%s(), kstrdup fail\n", __func__);
3311 goto exit;
3312 }
3313 temp = str_begin;
3314
3315 command = strsep(&temp, delim);
3316
3317 dev_info(priv->dev, "%s(), command %s, content %s\n",
3318 __func__, command, temp);
3319
3320 for (cf = debug_cmds; cf->cmd; cf++) {
3321 if (strcmp(cf->cmd, command) == 0) {
3322 cf->fn(f, temp);
3323 break;
3324 }
3325 }
3326
3327 kfree(str_begin);
3328exit:
3329
3330 return count;
3331}
3332
3333// TODO: remove debug fs
3334static const struct file_operations mt6389_debugfs_ops = {
3335 .open = mt6389_debugfs_open,
3336 .write = mt6389_debugfs_write,
3337 .read = mt6389_debugfs_read,
3338};
3339
3340#ifndef CONFIG_MTK_PMIC_WRAP
3341#ifdef CONFIG_MTK_PMIC_WRAP_HAL
3342static DEFINE_SPINLOCK(codec_set_reg_lock);
3343#endif
3344static unsigned int codec_get_reg(unsigned int offset)
3345{
3346#ifdef CONFIG_MTK_PMIC_WRAP_HAL
3347 int ret = 0;
3348 unsigned int data = 0;
3349#ifdef DEBUG_PMIC_WRAP
3350 pr_info("%s(), call pwrap_read, offset = 0x%x\n",
3351 __func__, offset);
3352#endif
3353 ret = pwrap_read(offset, &data);
3354
3355 return data;
3356#else
3357 return 0;
3358#endif
3359}
3360
3361static void codec_set_reg(unsigned int offset,
3362 unsigned int value,
3363 unsigned int mask)
3364{
3365 int ret = 0;
3366 unsigned int reg_value;
3367 unsigned long flags = 0;
3368
3369#ifdef CONFIG_MTK_PMIC_WRAP_HAL
3370 spin_lock_irqsave(&codec_set_reg_lock, flags);
3371 reg_value = codec_get_reg(offset);
3372 reg_value &= (~mask);
3373 reg_value |= (value & mask);
3374#ifdef DEBUG_PMIC_WRAP
3375 pr_info("%s(), call pwrap_write, offset = 0x%x, value = 0x%x, mask = 0x%x\n",
3376 __func__, offset, value, mask);
3377#endif
3378 ret = pwrap_write(offset, reg_value);
3379 spin_unlock_irqrestore(&codec_set_reg_lock, flags);
3380
3381 reg_value = codec_get_reg(offset);
3382 if ((reg_value & mask) != (value & mask))
3383 pr_warn("%s(), offset = 0x%x, mask = 0x%x, ret = %d, reg_value = 0x%x\n",
3384 __func__, offset, mask, ret, reg_value);
3385#endif
3386}
3387
3388static bool is_writeable_reg(struct device *dev, unsigned int reg)
3389{
3390 return true;
3391}
3392
3393static bool is_volatile_reg(struct device *dev, unsigned int reg)
3394{
3395 return true;
3396}
3397
3398static bool is_readable_reg(struct device *dev, unsigned int reg)
3399{
3400 switch (reg) {
3401 case MT6389_DRV_CON3:
3402 case MT6389_SMT_CON1:
3403 case MT6389_GPIO_DIR0:
3404 case MT6389_GPIO_MODE2:
3405 case MT6389_GPIO_MODE3:
3406 case MT6389_DCXO_CW12:
3407 case MT6389_LDO_VAUD28_CON0:
3408 case MT6389_AUXADC_CON10:
3409 return true;
3410 default:
3411 break;
3412 };
3413
3414 if (reg >= MT6389_AUD_TOP_ID && reg <= MT6389_ZCD_CON5)
3415 return true;
3416
3417 return false;
3418}
3419
3420static int reg_read(void *context, unsigned int reg, unsigned int *val)
3421{
3422 *val = codec_get_reg(reg);
3423 return 0;
3424}
3425
3426static int reg_write(void *context, unsigned int reg, unsigned int val)
3427{
3428 codec_set_reg(reg, val, 0xffff);
3429 return 0;
3430}
3431
3432#define REG_STRIDE 2
3433static const struct regmap_config mt6389_regmap = {
3434 .reg_bits = 16,
3435 .val_bits = 16,
3436 .reg_stride = REG_STRIDE,
3437
3438 .max_register = MT6389_MAX_REGISTER,
3439 .writeable_reg = is_writeable_reg,
3440 .volatile_reg = is_volatile_reg,
3441 .readable_reg = is_readable_reg,
3442
3443 .reg_read = reg_read,
3444 .reg_write = reg_write,
3445
3446 .cache_type = REGCACHE_NONE,
3447};
3448#endif
3449
3450//tianyan@2021.10.19 modify for add audio hardware check start
3451static int mt6389_audio_hw_debugfs_open(struct inode *inode, struct file *file)
3452{
3453 file->private_data = inode->i_private;
3454 return 0;
3455}
3456
3457static ssize_t mt6389_audio_hw_debugfs_read(struct file *file, char __user *buf,
3458 size_t count, loff_t *pos)
3459{
3460 struct mt6389_priv *priv = file->private_data;
3461 const int size = 128;
3462 char *buffer = NULL; /* for reduce kernel stack */
3463 int n = 0;
3464 unsigned int value;
3465 int ret = 0;
3466
3467 buffer = kmalloc(size, GFP_KERNEL);
3468 if (!buffer || !buf)
3469 return -ENOMEM;
3470
3471 if(regmap_read(priv->regmap, MT6389_LDO_VAUD28_CON0, &value))
3472 n += scnprintf(buffer + n, size - n, "audio hw status: Not Ok!\n");
3473 else
3474 n += scnprintf(buffer + n, size - n, "audio hw status: Ok!\n");
3475
3476 if(value)
3477 n += scnprintf(buffer + n, size - n, "whether play: playing!\n");
3478 else
3479 n += scnprintf(buffer + n, size - n, "whether play: not playing!\n");
3480
3481 ret = simple_read_from_buffer(buf, count, pos, buffer, n);
3482 kfree(buffer);
3483 return ret;
3484}
3485
3486static const struct file_operations mt6389_audio_hw_debugfs_ops = {
3487 .open = mt6389_audio_hw_debugfs_open,
3488 .read = mt6389_audio_hw_debugfs_read,
3489};
3490//tianyan@2021.10.19 modify for add audio hardware check end
3491
3492static int mt6389_platform_driver_probe(struct platform_device *pdev)
3493{
3494 struct mt6389_priv *priv;
3495#ifdef CONFIG_MTK_PMIC_WRAP
3496 struct device_node *pwrap_node;
3497#endif
3498
3499 priv = devm_kzalloc(&pdev->dev,
3500 sizeof(struct mt6389_priv),
3501 GFP_KERNEL);
3502 dev_info(priv->dev, "+%s() ,dev_name %s mt6389_priv %p\n",
3503 __func__, dev_name(&pdev->dev), priv);
3504 if (priv == NULL)
3505 return -ENOMEM;
3506
3507 dev_set_drvdata(&pdev->dev, priv);
3508
3509 priv->dev = &pdev->dev;
3510
3511#ifndef CONFIG_MTK_PMIC_WRAP
3512 priv->regmap = devm_regmap_init(&pdev->dev, NULL, NULL, &mt6389_regmap);
3513#else
3514 pwrap_node = of_parse_phandle(pdev->dev.of_node,
3515 "mediatek,pwrap-regmap", 0);
3516 if (pwrap_node) {
3517 priv->regmap = pwrap_node_to_regmap(pwrap_node);
3518 if (IS_ERR(priv->regmap))
3519 return PTR_ERR(priv->regmap);
3520 } else {
3521 dev_err(&pdev->dev, "get pwrap node fail\n");
3522 return -EINVAL;
3523 }
3524#endif
3525 if (IS_ERR(priv->regmap))
3526 return PTR_ERR(priv->regmap);
3527
3528 /* create debugfs file */
3529 priv->debugfs = debugfs_create_file("mtksocanaaudio",
3530 S_IFREG | 0444, NULL,
3531 priv, &mt6389_debugfs_ops);
3532
3533//tianyan@2021.10.19 modify for add audio hardware check start
3534 (void*)debugfs_create_file("audio_hw",
3535 S_IFREG | 0444, NULL,
3536 priv, &mt6389_audio_hw_debugfs_ops);
3537//tianyan@2021.10.19 modify for add audio hardware check end
3538
3539 dev_info(priv->dev, "%s(), dev name %s\n",
3540 __func__, dev_name(&pdev->dev));
3541
3542 return snd_soc_register_codec(&pdev->dev,
3543 &mt6389_soc_codec_driver,
3544 mt6389_dai_driver,
3545 ARRAY_SIZE(mt6389_dai_driver));
3546}
3547
3548static int mt6389_platform_driver_remove(struct platform_device *pdev)
3549{
3550 struct mt6389_priv *priv = dev_get_drvdata(&pdev->dev);
3551
3552 dev_info(&pdev->dev, "%s()\n", __func__);
3553
3554 debugfs_remove(priv->debugfs);
3555
3556 snd_soc_unregister_codec(&pdev->dev);
3557 return 0;
3558}
3559
3560static const struct of_device_id mt6389_of_match[] = {
3561 {.compatible = "mediatek,mt6389-sound",},
3562 {}
3563};
3564MODULE_DEVICE_TABLE(of, mt6389_of_match);
3565
3566static struct platform_driver mt6389_platform_driver = {
3567 .driver = {
3568 .name = "mt6389-sound",
3569 .of_match_table = mt6389_of_match,
3570 },
3571 .probe = mt6389_platform_driver_probe,
3572 .remove = mt6389_platform_driver_remove,
3573};
3574
3575module_platform_driver(mt6389_platform_driver)
3576
3577/* Module information */
3578MODULE_DESCRIPTION("MT6389 ALSA SoC codec driver");
3579MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
3580MODULE_LICENSE("GPL v2");