Blame - src/kernel/linux/v4.14/sound/soc/codecs/mt6389.h - T103

rjw

1f88458

2022-01-06 17:20:42 +0800

[diff] [blame^]

1

/* SPDX-License-Identifier: GPL-2.0 */

2

/*

3

* MT6389.h -- MT6389 ALSA SoC audio codec driver

4

*

5

6

* Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>

*/

#ifndef __MT6389_H__

#define __MT6389_H__

/* Reg bit define */

/* MT6389_DCXO_CW12 */

14

#define RG_XO_AUDIO_EN_M_SFT 13

15

16

/* LDO_VAUD28_CON0 */

17

#define RG_LDO_VAUD28_EN_SFT 0

18

#define RG_LDO_VAUD28_EN_MASK 0x1

19

#define RG_LDO_VAUD28_EN_MASK_SFT (0x1 << 0)

20

#define RG_LDO_VAUD28_LP_SFT 1

21

#define RG_LDO_VAUD28_LP_MASK 0x1

22

#define RG_LDO_VAUD28_LP_MASK_SFT (0x1 << 1)

23

24

/* AUD_TOP_CKPDN_CON0 */

25

#define RG_AUDNCP_CK_PDN_SFT 6

26

#define RG_AUDNCP_CK_PDN_MASK 0x1

27

#define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)

28

#define RG_ZCD13M_CK_PDN_SFT 5

29

#define RG_ZCD13M_CK_PDN_MASK 0x1

30

#define RG_ZCD13M_CK_PDN_MASK_SFT (0x1 << 5)

31

#define RG_AUD_INTRP_CK_PDN_SFT 3

32

#define RG_AUD_INTRP_CK_PDN_MASK 0x1

33

#define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 3)

34

#define RG_AUDIF_CK_PDN_SFT 2

35

#define RG_AUDIF_CK_PDN_MASK 0x1

36

#define RG_AUDIF_CK_PDN_MASK_SFT (0x1 << 2)

37

#define RG_AUD_CK_PDN_SFT 1

38

#define RG_AUD_CK_PDN_MASK 0x1

39

#define RG_AUD_CK_PDN_MASK_SFT (0x1 << 1)

40

41

/* AUD_TOP_CKPDN_CON0_SET */

42

#define RG_AUD_TOP_CKPDN_CON0_SET_SFT 0

43

#define RG_AUD_TOP_CKPDN_CON0_SET_MASK 0x7f

44

#define RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT (0x7f << 0)

45

46

/* AUD_TOP_CKPDN_CON0_CLR */

47

#define RG_AUD_TOP_CKPDN_CON0_CLR_SFT 0

48

#define RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0x7f

49

#define RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT (0x7f << 0)

50

51

/* AUD_TOP_CKSEL_CON0 */

52

#define RG_AUDIF_CK_CKSEL_SFT 3

53

#define RG_AUDIF_CK_CKSEL_MASK 0x1

54

#define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3)

55

#define RG_AUD_CK_CKSEL_SFT 2

56

#define RG_AUD_CK_CKSEL_MASK 0x1

57

#define RG_AUD_CK_CKSEL_MASK_SFT (0x1 << 2)

58

59

/* AUD_TOP_CKSEL_CON0_SET */

60

#define RG_AUD_TOP_CKSEL_CON0_SET_SFT 0

61

#define RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xf

62

#define RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT (0xf << 0)

63

64

/* AUD_TOP_CKSEL_CON0_CLR */

65

#define RG_AUD_TOP_CKSEL_CON0_CLR_SFT 0

66

#define RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xf

67

#define RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT (0xf << 0)

68

69

/* AUD_TOP_CKTST_CON0 */

70

#define RG_AUD26M_CK_TSTSEL_SFT 4

71

#define RG_AUD26M_CK_TSTSEL_MASK 0x1

72

#define RG_AUD26M_CK_TSTSEL_MASK_SFT (0x1 << 4)

73

#define RG_AUDIF_CK_TSTSEL_SFT 3

74

#define RG_AUDIF_CK_TSTSEL_MASK 0x1

75

#define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3)

76

#define RG_AUD_CK_TSTSEL_SFT 2

77

#define RG_AUD_CK_TSTSEL_MASK 0x1

78

#define RG_AUD_CK_TSTSEL_MASK_SFT (0x1 << 2)

79

#define RG_AUD26M_CK_TST_DIS_SFT 0

80

#define RG_AUD26M_CK_TST_DIS_MASK 0x1

81

#define RG_AUD26M_CK_TST_DIS_MASK_SFT (0x1 << 0)

82

83

/* AUD_TOP_CLK_HWEN_CON0 */

84

#define RG_AUD_INTRP_CK_PDN_HWEN_SFT 0

85

#define RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1

86

#define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT (0x1 << 0)

87

88

/* AUD_TOP_CLK_HWEN_CON0_SET */

89

#define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT 0

90

#define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xffff

91

#define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT (0xffff << 0)

92

93

/* AUD_TOP_CLK_HWEN_CON0_CLR */

94

#define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT 0

95

#define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK 0xffff

96

#define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT (0xffff << 0)

97

98

/* AUD_TOP_RST_CON0 */

99

#define RG_AUDNCP_RST_SFT 3

100

#define RG_AUDNCP_RST_MASK 0x1

101

#define RG_AUDNCP_RST_MASK_SFT (0x1 << 3)

102

#define RG_ZCD_RST_SFT 2

103

#define RG_ZCD_RST_MASK 0x1

104

#define RG_ZCD_RST_MASK_SFT (0x1 << 2)

105

#define RG_AUDIO_RST_SFT 0

106

#define RG_AUDIO_RST_MASK 0x1

107

#define RG_AUDIO_RST_MASK_SFT (0x1 << 0)

108

109

/* AUD_TOP_RST_CON0_SET */

110

#define RG_AUD_TOP_RST_CON0_SET_SFT 0

111

#define RG_AUD_TOP_RST_CON0_SET_MASK 0xf

112

#define RG_AUD_TOP_RST_CON0_SET_MASK_SFT (0xf << 0)

113

114

/* AUD_TOP_RST_CON0_CLR */

115

#define RG_AUD_TOP_RST_CON0_CLR_SFT 0

116

#define RG_AUD_TOP_RST_CON0_CLR_MASK 0xf

117

#define RG_AUD_TOP_RST_CON0_CLR_MASK_SFT (0xf << 0)

118

119

/* AUD_TOP_RST_BANK_CON0 */

120

#define BANK_AUDZCD_SWRST_SFT 2

121

#define BANK_AUDZCD_SWRST_MASK 0x1

122

#define BANK_AUDZCD_SWRST_MASK_SFT (0x1 << 2)

123

#define BANK_AUDIO_SWRST_SFT 1

124

#define BANK_AUDIO_SWRST_MASK 0x1

125

#define BANK_AUDIO_SWRST_MASK_SFT (0x1 << 1)

126

127

/* AUD_TOP_INT_CON0 */

128

#define RG_INT_EN_AUDIO_SFT 0

129

#define RG_INT_EN_AUDIO_MASK 0x1

130

#define RG_INT_EN_AUDIO_MASK_SFT (0x1 << 0)

131

132

/* AUD_TOP_INT_CON0_SET */

133

#define RG_AUD_INT_CON0_SET_SFT 0

134

#define RG_AUD_INT_CON0_SET_MASK 0xffff

135

#define RG_AUD_INT_CON0_SET_MASK_SFT (0xffff << 0)

136

137

/* AUD_TOP_INT_CON0_CLR */

138

#define RG_AUD_INT_CON0_CLR_SFT 0

139

#define RG_AUD_INT_CON0_CLR_MASK 0xffff

140

#define RG_AUD_INT_CON0_CLR_MASK_SFT (0xffff << 0)

141

142

/* AUD_TOP_INT_MASK_CON0 */

143

#define RG_INT_MASK_AUDIO_SFT 0

144

#define RG_INT_MASK_AUDIO_MASK 0x1

145

#define RG_INT_MASK_AUDIO_MASK_SFT (0x1 << 0)

146

147

/* AUD_TOP_INT_MASK_CON0_SET */

148

#define RG_AUD_INT_MASK_CON0_SET_SFT 0

149

#define RG_AUD_INT_MASK_CON0_SET_MASK 0xffff

150

#define RG_AUD_INT_MASK_CON0_SET_MASK_SFT (0xffff << 0)

151

152

/* AUD_TOP_INT_MASK_CON0_CLR */

153

#define RG_AUD_INT_MASK_CON0_CLR_SFT 0

154

#define RG_AUD_INT_MASK_CON0_CLR_MASK 0xffff

155

#define RG_AUD_INT_MASK_CON0_CLR_MASK_SFT (0xffff << 0)

156

157

/* AUD_TOP_INT_STATUS0 */

158

#define RG_INT_STATUS_AUDIO_SFT 0

159

#define RG_INT_STATUS_AUDIO_MASK 0x1

160

#define RG_INT_STATUS_AUDIO_MASK_SFT (0x1 << 0)

161

162

/* AUD_TOP_INT_RAW_STATUS0 */

163

#define RG_INT_RAW_STATUS_AUDIO_SFT 0

164

#define RG_INT_RAW_STATUS_AUDIO_MASK 0x1

165

#define RG_INT_RAW_STATUS_AUDIO_MASK_SFT (0x1 << 0)

166

167

/* AUD_TOP_INT_MISC_CON0 */

168

#define RG_AUD_TOP_INT_POLARITY_SFT 0

169

#define RG_AUD_TOP_INT_POLARITY_MASK 0x1

170

#define RG_AUD_TOP_INT_POLARITY_MASK_SFT (0x1 << 0)

171

172

/* AUDNCP_CLKDIV_CON0 */

173

#define RG_DIVCKS_CHG_SFT 0

174

#define RG_DIVCKS_CHG_MASK 0x1

175

#define RG_DIVCKS_CHG_MASK_SFT (0x1 << 0)

176

177

/* AUDNCP_CLKDIV_CON1 */

178

#define RG_DIVCKS_ON_SFT 0

179

#define RG_DIVCKS_ON_MASK 0x1

180

#define RG_DIVCKS_ON_MASK_SFT (0x1 << 0)

181

182

/* AUDNCP_CLKDIV_CON2 */

183

#define RG_DIVCKS_PRG_SFT 0

184

#define RG_DIVCKS_PRG_MASK 0x1ff

185

#define RG_DIVCKS_PRG_MASK_SFT (0x1ff << 0)

186

187

/* AUDNCP_CLKDIV_CON3 */

188

#define RG_DIVCKS_PWD_NCP_SFT 0

189

#define RG_DIVCKS_PWD_NCP_MASK 0x1

190

#define RG_DIVCKS_PWD_NCP_MASK_SFT (0x1 << 0)

191

192

/* AUDNCP_CLKDIV_CON4 */

193

#define RG_DIVCKS_PWD_NCP_ST_SEL_SFT 0

194

#define RG_DIVCKS_PWD_NCP_ST_SEL_MASK 0x3

195

#define RG_DIVCKS_PWD_NCP_ST_SEL_MASK_SFT (0x3 << 0)

196

197

/* AUD_TOP_MON_CON0 */

198

#define RG_AUD_TOP_MON_SEL_SFT 0

199

#define RG_AUD_TOP_MON_SEL_MASK 0x7

200

#define RG_AUD_TOP_MON_SEL_MASK_SFT (0x7 << 0)

201

#define RG_AUD_CLK_INT_MON_FLAG_SEL_SFT 3

202

#define RG_AUD_CLK_INT_MON_FLAG_SEL_MASK 0xff

203

#define RG_AUD_CLK_INT_MON_FLAG_SEL_MASK_SFT (0xff << 3)

204

#define RG_AUD_CLK_INT_MON_FLAG_EN_SFT 11

205

#define RG_AUD_CLK_INT_MON_FLAG_EN_MASK 0x1

206

#define RG_AUD_CLK_INT_MON_FLAG_EN_MASK_SFT (0x1 << 11)

207

208

/* AUDIO_DIG_DSN_ID */

209

#define AUDIO_DIG_ANA_ID_SFT 0

210

#define AUDIO_DIG_ANA_ID_MASK 0xff

211

#define AUDIO_DIG_ANA_ID_MASK_SFT (0xff << 0)

212

#define AUDIO_DIG_DIG_ID_SFT 8

213

#define AUDIO_DIG_DIG_ID_MASK 0xff

214

#define AUDIO_DIG_DIG_ID_MASK_SFT (0xff << 8)

215

216

/* AUDIO_DIG_DSN_REV0 */

217

#define AUDIO_DIG_ANA_MINOR_REV_SFT 0

218

#define AUDIO_DIG_ANA_MINOR_REV_MASK 0xf

219

#define AUDIO_DIG_ANA_MINOR_REV_MASK_SFT (0xf << 0)

220

#define AUDIO_DIG_ANA_MAJOR_REV_SFT 4

221

#define AUDIO_DIG_ANA_MAJOR_REV_MASK 0xf

222

#define AUDIO_DIG_ANA_MAJOR_REV_MASK_SFT (0xf << 4)

223

#define AUDIO_DIG_DIG_MINOR_REV_SFT 8

224

#define AUDIO_DIG_DIG_MINOR_REV_MASK 0xf

225

#define AUDIO_DIG_DIG_MINOR_REV_MASK_SFT (0xf << 8)

226

#define AUDIO_DIG_DIG_MAJOR_REV_SFT 12

227

#define AUDIO_DIG_DIG_MAJOR_REV_MASK 0xf

228

#define AUDIO_DIG_DIG_MAJOR_REV_MASK_SFT (0xf << 12)

229

230

/* AUDIO_DIG_DSN_DBI */

231

#define AUDIO_DIG_DSN_CBS_SFT 0

232

#define AUDIO_DIG_DSN_CBS_MASK 0x3

233

#define AUDIO_DIG_DSN_CBS_MASK_SFT (0x3 << 0)

234

#define AUDIO_DIG_DSN_BIX_SFT 2

235

#define AUDIO_DIG_DSN_BIX_MASK 0x3

236

#define AUDIO_DIG_DSN_BIX_MASK_SFT (0x3 << 2)

237

#define AUDIO_DIG_ESP_SFT 8

238

#define AUDIO_DIG_ESP_MASK 0xff

239

#define AUDIO_DIG_ESP_MASK_SFT (0xff << 8)

240

241

/* AUDIO_DIG_DSN_DXI */

242

#define AUDIO_DIG_DSN_FPI_SFT 0

243

#define AUDIO_DIG_DSN_FPI_MASK 0xff

244

#define AUDIO_DIG_DSN_FPI_MASK_SFT (0xff << 0)

245

246

/* AFE_UL_DL_CON0 */

247

#define AFE_UL_LR_SWAP_SFT 15

248

#define AFE_UL_LR_SWAP_MASK 0x1

249

#define AFE_UL_LR_SWAP_MASK_SFT (0x1 << 15)

250

#define AFE_DL_LR_SWAP_SFT 14

251

#define AFE_DL_LR_SWAP_MASK 0x1

252

#define AFE_DL_LR_SWAP_MASK_SFT (0x1 << 14)

253

#define AFE_ON_SFT 0

254

#define AFE_ON_MASK 0x1

255

#define AFE_ON_MASK_SFT (0x1 << 0)

256

257

/* AFE_DL_SRC2_CON0_L */

258

#define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0

259

#define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1

260

#define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)

261

262

/* AFE_UL_SRC_CON0_H */

263

#define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 11

264

#define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7

265

#define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)

266

#define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 8

267

#define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7

268

#define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)

269

#define C_TWO_DIGITAL_MIC_CTL_SFT 7

270

#define C_TWO_DIGITAL_MIC_CTL_MASK 0x1

271

#define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)

272

273

/* AFE_UL_SRC_CON0_L */

274

#define DMIC_LOW_POWER_MODE_CTL_SFT 14

275

#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3

276

#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)

277

#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5

278

#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1

279

#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)

280

#define UL_LOOP_BACK_MODE_CTL_SFT 2

281

#define UL_LOOP_BACK_MODE_CTL_MASK 0x1

282

#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)

283

#define UL_SDM_3_LEVEL_CTL_SFT 1

284

#define UL_SDM_3_LEVEL_CTL_MASK 0x1

285

#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)

286

#define UL_SRC_ON_TMP_CTL_SFT 0

287

#define UL_SRC_ON_TMP_CTL_MASK 0x1

288

#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)

289

290

/* AFE_TOP_CON0 */

291

#define MTKAIF_SINE_ON_SFT 2

292

#define MTKAIF_SINE_ON_MASK 0x1

293

#define MTKAIF_SINE_ON_MASK_SFT (0x1 << 2)

294

#define UL_SINE_ON_SFT 1

295

#define UL_SINE_ON_MASK 0x1

296

#define UL_SINE_ON_MASK_SFT (0x1 << 1)

297

#define DL_SINE_ON_SFT 0

298

#define DL_SINE_ON_MASK 0x1

299

#define DL_SINE_ON_MASK_SFT (0x1 << 0)

300

301

/* AUDIO_TOP_CON0 */

302

#define PDN_AFE_CTL_SFT 7

303

#define PDN_AFE_CTL_MASK 0x1

304

#define PDN_AFE_CTL_MASK_SFT (0x1 << 7)

305

#define PDN_DAC_CTL_SFT 6

306

#define PDN_DAC_CTL_MASK 0x1

307

#define PDN_DAC_CTL_MASK_SFT (0x1 << 6)

308

#define PDN_ADC_CTL_SFT 5

309

#define PDN_ADC_CTL_MASK 0x1

310

#define PDN_ADC_CTL_MASK_SFT (0x1 << 5)

311

#define PDN_I2S_DL_CTL_SFT 3

312

#define PDN_I2S_DL_CTL_MASK 0x1

313

#define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3)

314

#define PWR_CLK_DIS_CTL_SFT 2

315

#define PWR_CLK_DIS_CTL_MASK 0x1

316

#define PWR_CLK_DIS_CTL_MASK_SFT (0x1 << 2)

317

#define PDN_AFE_TESTMODEL_CTL_SFT 1

318

#define PDN_AFE_TESTMODEL_CTL_MASK 0x1

319

#define PDN_AFE_TESTMODEL_CTL_MASK_SFT (0x1 << 1)

320

#define PDN_AFE_DL_PREDIST_CTL_SFT 0

321

#define PDN_AFE_DL_PREDIST_CTL_MASK 0x1

322

#define PDN_AFE_DL_PREDIST_CTL_MASK_SFT (0x1 << 0)

323

324

/* AFE_MON_DEBUG0 */

325

#define AUDIO_SYS_TOP_MON_SWAP_SFT 14

326

#define AUDIO_SYS_TOP_MON_SWAP_MASK 0x3

327

#define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 14)

328

#define AUDIO_SYS_TOP_MON_SEL_SFT 8

329

#define AUDIO_SYS_TOP_MON_SEL_MASK 0x1f

330

#define AUDIO_SYS_TOP_MON_SEL_MASK_SFT (0x1f << 8)

331

#define AFE_MON_SEL_SFT 0

332

#define AFE_MON_SEL_MASK 0xf

333

#define AFE_MON_SEL_MASK_SFT (0xf << 0)

334

335

/* AFUNC_AUD_CON0 */

336

#define CCI_AUD_ANACK_SEL_SFT 15

337

#define CCI_AUD_ANACK_SEL_MASK 0x1

338

#define CCI_AUD_ANACK_SEL_MASK_SFT (0x1 << 15)

339

#define CCI_AUDIO_FIFO_WPTR_SFT 12

340

#define CCI_AUDIO_FIFO_WPTR_MASK 0x7

341

#define CCI_AUDIO_FIFO_WPTR_MASK_SFT (0x7 << 12)

342

#define CCI_SCRAMBLER_CG_EN_SFT 11

343

#define CCI_SCRAMBLER_CG_EN_MASK 0x1

344

#define CCI_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 11)

345

#define CCI_LCH_INV_SFT 10

346

#define CCI_LCH_INV_MASK 0x1

347

#define CCI_LCH_INV_MASK_SFT (0x1 << 10)

348

#define CCI_RAND_EN_SFT 9

349

#define CCI_RAND_EN_MASK 0x1

350

#define CCI_RAND_EN_MASK_SFT (0x1 << 9)

351

#define CCI_SPLT_SCRMB_CLK_ON_SFT 8

352

#define CCI_SPLT_SCRMB_CLK_ON_MASK 0x1

353

#define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT (0x1 << 8)

354

#define CCI_SPLT_SCRMB_ON_SFT 7

355

#define CCI_SPLT_SCRMB_ON_MASK 0x1

356

#define CCI_SPLT_SCRMB_ON_MASK_SFT (0x1 << 7)

357

#define CCI_AUD_IDAC_TEST_EN_SFT 6

358

#define CCI_AUD_IDAC_TEST_EN_MASK 0x1

359

#define CCI_AUD_IDAC_TEST_EN_MASK_SFT (0x1 << 6)

360

#define CCI_ZERO_PAD_DISABLE_SFT 5

361

#define CCI_ZERO_PAD_DISABLE_MASK 0x1

362

#define CCI_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 5)

363

#define CCI_AUD_SPLIT_TEST_EN_SFT 4

364

#define CCI_AUD_SPLIT_TEST_EN_MASK 0x1

365

#define CCI_AUD_SPLIT_TEST_EN_MASK_SFT (0x1 << 4)

366

#define CCI_AUD_SDM_MUTEL_SFT 3

367

#define CCI_AUD_SDM_MUTEL_MASK 0x1

368

#define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3)

369

#define CCI_AUD_SDM_MUTER_SFT 2

370

#define CCI_AUD_SDM_MUTER_MASK 0x1

371

#define CCI_AUD_SDM_MUTER_MASK_SFT (0x1 << 2)

372

#define CCI_AUD_SDM_7BIT_SEL_SFT 1

373

#define CCI_AUD_SDM_7BIT_SEL_MASK 0x1

374

#define CCI_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 1)

375

#define CCI_SCRAMBLER_EN_SFT 0

376

#define CCI_SCRAMBLER_EN_MASK 0x1

377

#define CCI_SCRAMBLER_EN_MASK_SFT (0x1 << 0)

378

379

/* AFUNC_AUD_CON1 */

380

#define AUD_SDM_TEST_L_SFT 8

381

#define AUD_SDM_TEST_L_MASK 0xff

382

#define AUD_SDM_TEST_L_MASK_SFT (0xff << 8)

383

#define AUD_SDM_TEST_R_SFT 0

384

#define AUD_SDM_TEST_R_MASK 0xff

385

#define AUD_SDM_TEST_R_MASK_SFT (0xff << 0)

386

387

/* AFUNC_AUD_CON2 */

388

#define CCI_AUD_DAC_ANA_MUTE_SFT 7

389

#define CCI_AUD_DAC_ANA_MUTE_MASK 0x1

390

#define CCI_AUD_DAC_ANA_MUTE_MASK_SFT (0x1 << 7)

391

#define CCI_AUD_DAC_ANA_RSTB_SEL_SFT 6

392

#define CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x1

393

#define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT (0x1 << 6)

394

#define CCI_AUDIO_FIFO_CLKIN_INV_SFT 4

395

#define CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x1

396

#define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT (0x1 << 4)

397

#define CCI_AUDIO_FIFO_ENABLE_SFT 3

398

#define CCI_AUDIO_FIFO_ENABLE_MASK 0x1

399

#define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3)

400

#define CCI_ACD_MODE_SFT 2

401

#define CCI_ACD_MODE_MASK 0x1

402

#define CCI_ACD_MODE_MASK_SFT (0x1 << 2)

403

#define CCI_AFIFO_CLK_PWDB_SFT 1

404

#define CCI_AFIFO_CLK_PWDB_MASK 0x1

405

#define CCI_AFIFO_CLK_PWDB_MASK_SFT (0x1 << 1)

406

#define CCI_ACD_FUNC_RSTB_SFT 0

407

#define CCI_ACD_FUNC_RSTB_MASK 0x1

408

#define CCI_ACD_FUNC_RSTB_MASK_SFT (0x1 << 0)

409

410

/* AFUNC_AUD_CON3 */

411

#define SDM_ANA13M_TESTCK_SEL_SFT 15

412

#define SDM_ANA13M_TESTCK_SEL_MASK 0x1

413

#define SDM_ANA13M_TESTCK_SEL_MASK_SFT (0x1 << 15)

414

#define SDM_ANA13M_TESTCK_SRC_SEL_SFT 12

415

#define SDM_ANA13M_TESTCK_SRC_SEL_MASK 0x7

416

#define SDM_ANA13M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 12)

417

#define SDM_TESTCK_SRC_SEL_SFT 8

418

#define SDM_TESTCK_SRC_SEL_MASK 0x7

419

#define SDM_TESTCK_SRC_SEL_MASK_SFT (0x7 << 8)

420

#define DIGMIC_TESTCK_SRC_SEL_SFT 4

421

#define DIGMIC_TESTCK_SRC_SEL_MASK 0x7

422

#define DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4)

423

#define DIGMIC_TESTCK_SEL_SFT 0

424

#define DIGMIC_TESTCK_SEL_MASK 0x1

425

#define DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 0)

426

427

/* AFUNC_AUD_CON4 */

428

#define UL_FIFO_WCLK_INV_SFT 8

429

#define UL_FIFO_WCLK_INV_MASK 0x1

430

#define UL_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)

431

#define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT 6

432

#define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1

433

#define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)

434

#define UL_FIFO_WDATA_TESTEN_SFT 5

435

#define UL_FIFO_WDATA_TESTEN_MASK 0x1

436

#define UL_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)

437

#define UL_FIFO_WDATA_TESTSRC_SEL_SFT 4

438

#define UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1

439

#define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)

440

#define UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3

441

#define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1

442

#define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)

443

#define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0

444

#define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7

445

#define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)

446

447

/* AFUNC_AUD_CON5 */

448

#define R_AUD_DAC_POS_LARGE_MONO_SFT 8

449

#define R_AUD_DAC_POS_LARGE_MONO_MASK 0xff

450

#define R_AUD_DAC_POS_LARGE_MONO_MASK_SFT (0xff << 8)

451

#define R_AUD_DAC_NEG_LARGE_MONO_SFT 0

452

#define R_AUD_DAC_NEG_LARGE_MONO_MASK 0xff

453

#define R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT (0xff << 0)

454

455

/* AFUNC_AUD_CON6 */

456

#define R_AUD_DAC_POS_SMALL_MONO_SFT 12

457

#define R_AUD_DAC_POS_SMALL_MONO_MASK 0xf

458

#define R_AUD_DAC_POS_SMALL_MONO_MASK_SFT (0xf << 12)

459

#define R_AUD_DAC_NEG_SMALL_MONO_SFT 8

460

#define R_AUD_DAC_NEG_SMALL_MONO_MASK 0xf

461

#define R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT (0xf << 8)

462

#define R_AUD_DAC_POS_TINY_MONO_SFT 6

463

#define R_AUD_DAC_POS_TINY_MONO_MASK 0x3

464

#define R_AUD_DAC_POS_TINY_MONO_MASK_SFT (0x3 << 6)

465

#define R_AUD_DAC_NEG_TINY_MONO_SFT 4

466

#define R_AUD_DAC_NEG_TINY_MONO_MASK 0x3

467

#define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT (0x3 << 4)

468

#define R_AUD_DAC_MONO_SEL_SFT 3

469

#define R_AUD_DAC_MONO_SEL_MASK 0x1

470

#define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3)

471

#define R_AUD_DAC_SGEN_SW_RSTB_SFT 0

472

#define R_AUD_DAC_SGEN_SW_RSTB_MASK 0x1

473

#define R_AUD_DAC_SGEN_SW_RSTB_MASK_SFT (0x1 << 0)

474

475

/* AFUNC_AUD_MON0 */

476

#define AUD_SCR_OUT_L_SFT 8

477

#define AUD_SCR_OUT_L_MASK 0xff

478

#define AUD_SCR_OUT_L_MASK_SFT (0xff << 8)

479

#define AUD_SCR_OUT_R_SFT 0

480

#define AUD_SCR_OUT_R_MASK 0xff

481

#define AUD_SCR_OUT_R_MASK_SFT (0xff << 0)

482

483

/* AUDRC_TUNE_MON0 */

484

#define ASYNC_TEST_OUT_BCK_SFT 15

485

#define ASYNC_TEST_OUT_BCK_MASK 0x1

486

#define ASYNC_TEST_OUT_BCK_MASK_SFT (0x1 << 15)

487

#define RGS_AUDRCTUNE1READ_SFT 8

488

#define RGS_AUDRCTUNE1READ_MASK 0x1f

489

#define RGS_AUDRCTUNE1READ_MASK_SFT (0x1f << 8)

490

#define RGS_AUDRCTUNE0READ_SFT 0

491

#define RGS_AUDRCTUNE0READ_MASK 0x1f

492

#define RGS_AUDRCTUNE0READ_MASK_SFT (0x1f << 0)

493

494

/* AFE_ADDA_MTKAIF_FIFO_CFG0 */

495

#define AFE_RESERVED_SFT 1

496

#define AFE_RESERVED_MASK 0x7fff

497

#define AFE_RESERVED_MASK_SFT (0x7fff << 1)

498

#define RG_MTKAIF_RXIF_FIFO_INTEN_SFT 0

499

#define RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1

500

#define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT (0x1 << 0)

501

502

/* AFE_ADDA_MTKAIF_FIFO_LOG_MON1 */

503

#define MTKAIF_RXIF_WR_FULL_STATUS_SFT 1

504

#define MTKAIF_RXIF_WR_FULL_STATUS_MASK 0x1

505

#define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT (0x1 << 1)

506

#define MTKAIF_RXIF_RD_EMPTY_STATUS_SFT 0

507

#define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x1

508

#define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT (0x1 << 0)

509

510

/* AFE_ADDA_MTKAIF_MON0 */

511

#define MTKAIFTX_V3_SYNC_OUT_SFT 14

512

#define MTKAIFTX_V3_SYNC_OUT_MASK 0x1

513

#define MTKAIFTX_V3_SYNC_OUT_MASK_SFT (0x1 << 14)

514

#define MTKAIFTX_V3_SDATA_OUT2_SFT 13

515

#define MTKAIFTX_V3_SDATA_OUT2_MASK 0x1

516

#define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT (0x1 << 13)

517

#define MTKAIFTX_V3_SDATA_OUT1_SFT 12

518

#define MTKAIFTX_V3_SDATA_OUT1_MASK 0x1

519

#define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT (0x1 << 12)

520

#define MTKAIF_RXIF_FIFO_STATUS_SFT 0

521

#define MTKAIF_RXIF_FIFO_STATUS_MASK 0xfff

522

#define MTKAIF_RXIF_FIFO_STATUS_MASK_SFT (0xfff << 0)

523

524

/* AFE_ADDA_MTKAIF_MON1 */

525

#define MTKAIFRX_V3_SYNC_IN_SFT 14

526

#define MTKAIFRX_V3_SYNC_IN_MASK 0x1

527

#define MTKAIFRX_V3_SYNC_IN_MASK_SFT (0x1 << 14)

528

#define MTKAIFRX_V3_SDATA_IN2_SFT 13

529

#define MTKAIFRX_V3_SDATA_IN2_MASK 0x1

530

#define MTKAIFRX_V3_SDATA_IN2_MASK_SFT (0x1 << 13)

531

#define MTKAIFRX_V3_SDATA_IN1_SFT 12

532

#define MTKAIFRX_V3_SDATA_IN1_MASK 0x1

533

#define MTKAIFRX_V3_SDATA_IN1_MASK_SFT (0x1 << 12)

534

#define MTKAIF_RXIF_SEARCH_FAIL_FLAG_SFT 11

535

#define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK 0x1

536

#define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 11)

537

#define MTKAIF_RXIF_INVALID_FLAG_SFT 8

538

#define MTKAIF_RXIF_INVALID_FLAG_MASK 0x1

539

#define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT (0x1 << 8)

540

#define MTKAIF_RXIF_INVALID_CYCLE_SFT 0

541

#define MTKAIF_RXIF_INVALID_CYCLE_MASK 0xff

542

#define MTKAIF_RXIF_INVALID_CYCLE_MASK_SFT (0xff << 0)

543

544

/* AFE_ADDA_MTKAIF_MON2 */

545

#define MTKAIF_TXIF_IN_CH2_SFT 8

546

#define MTKAIF_TXIF_IN_CH2_MASK 0xff

547

#define MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8)

548

#define MTKAIF_TXIF_IN_CH1_SFT 0

549

#define MTKAIF_TXIF_IN_CH1_MASK 0xff

550

#define MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0)

551

552

/* AFE_ADDA_MTKAIF_MON3 */

553

#define MTKAIF_RXIF_OUT_CH2_SFT 8

554

#define MTKAIF_RXIF_OUT_CH2_MASK 0xff

555

#define MTKAIF_RXIF_OUT_CH2_MASK_SFT (0xff << 8)

556

#define MTKAIF_RXIF_OUT_CH1_SFT 0

557

#define MTKAIF_RXIF_OUT_CH1_MASK 0xff

558

#define MTKAIF_RXIF_OUT_CH1_MASK_SFT (0xff << 0)

559

560

/* AFE_ADDA_MTKAIF_CFG0 */

561

#define RG_MTKAIF_RXIF_CLKINV_SFT 15

562

#define RG_MTKAIF_RXIF_CLKINV_MASK 0x1

563

#define RG_MTKAIF_RXIF_CLKINV_MASK_SFT (0x1 << 15)

564

#define RG_MTKAIF_RXIF_PROTOCOL2_SFT 8

565

#define RG_MTKAIF_RXIF_PROTOCOL2_MASK 0x1

566

#define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 8)

567

#define RG_MTKAIF_BYPASS_SRC_MODE_SFT 6

568

#define RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x3

569

#define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT (0x3 << 6)

570

#define RG_MTKAIF_BYPASS_SRC_TEST_SFT 5

571

#define RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x1

572

#define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT (0x1 << 5)

573

#define RG_MTKAIF_TXIF_PROTOCOL2_SFT 4

574

#define RG_MTKAIF_TXIF_PROTOCOL2_MASK 0x1

575

#define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)

576

#define RG_MTKAIF_PMIC_TXIF_8TO5_SFT 2

577

#define RG_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1

578

#define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 2)

579

#define RG_MTKAIF_LOOPBACK_TEST2_SFT 1

580

#define RG_MTKAIF_LOOPBACK_TEST2_MASK 0x1

581

#define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT (0x1 << 1)

582

#define RG_MTKAIF_LOOPBACK_TEST1_SFT 0

583

#define RG_MTKAIF_LOOPBACK_TEST1_MASK 0x1

584

#define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT (0x1 << 0)

585

586

/* AFE_ADDA_MTKAIF_RX_CFG0 */

587

#define RG_MTKAIF_RXIF_VOICE_MODE_SFT 12

588

#define RG_MTKAIF_RXIF_VOICE_MODE_MASK 0xf

589

#define RG_MTKAIF_RXIF_VOICE_MODE_MASK_SFT (0xf << 12)

590

#define RG_MTKAIF_RXIF_DATA_BIT_SFT 8

591

#define RG_MTKAIF_RXIF_DATA_BIT_MASK 0x7

592

#define RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)

593

#define RG_MTKAIF_RXIF_FIFO_RSP_SFT 4

594

#define RG_MTKAIF_RXIF_FIFO_RSP_MASK 0x7

595

#define RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)

596

#define RG_MTKAIF_RXIF_DETECT_ON_SFT 3

597

#define RG_MTKAIF_RXIF_DETECT_ON_MASK 0x1

598

#define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3)

599

#define RG_MTKAIF_RXIF_DATA_MODE_SFT 0

600

#define RG_MTKAIF_RXIF_DATA_MODE_MASK 0x1

601

#define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)

602

603

/* AFE_ADDA_MTKAIF_RX_CFG1 */

604

#define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_SFT 12

605

#define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK 0xf

606

#define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12)

607

#define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 8

608

#define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf

609

#define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)

610

#define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_SFT 4

611

#define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK 0xf

612

#define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)

613

#define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SFT 0

614

#define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK 0xf

615

#define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK_SFT (0xf << 0)

616

617

/* AFE_ADDA_MTKAIF_RX_CFG2 */

618

#define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_SFT 12

619

#define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK 0x1

620

#define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 12)

621

#define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SFT 0

622

#define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK 0xfff

623

#define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 0)

624

625

/* AFE_ADDA_MTKAIF_RX_CFG3 */

626

#define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4

627

#define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7

628

#define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)

629

#define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 3

630

#define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1

631

#define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3)

632

633

/* AFE_ADDA_MTKAIF_TX_CFG1 */

634

#define RG_MTKAIF_SYNC_WORD2_SFT 4

635

#define RG_MTKAIF_SYNC_WORD2_MASK 0x7

636

#define RG_MTKAIF_SYNC_WORD2_MASK_SFT (0x7 << 4)

637

#define RG_MTKAIF_SYNC_WORD1_SFT 0

638

#define RG_MTKAIF_SYNC_WORD1_MASK 0x7

639

#define RG_MTKAIF_SYNC_WORD1_MASK_SFT (0x7 << 0)

640

641

/* AFE_SGEN_CFG0 */

642

#define SGEN_AMP_DIV_CH1_CTL_SFT 12

643

#define SGEN_AMP_DIV_CH1_CTL_MASK 0xf

644

#define SGEN_AMP_DIV_CH1_CTL_MASK_SFT (0xf << 12)

645

#define SGEN_DAC_EN_CTL_SFT 7

646

#define SGEN_DAC_EN_CTL_MASK 0x1

647

#define SGEN_DAC_EN_CTL_MASK_SFT (0x1 << 7)

648

#define SGEN_MUTE_SW_CTL_SFT 6

649

#define SGEN_MUTE_SW_CTL_MASK 0x1

650

#define SGEN_MUTE_SW_CTL_MASK_SFT (0x1 << 6)

651

#define R_AUD_SDM_MUTE_L_SFT 5

652

#define R_AUD_SDM_MUTE_L_MASK 0x1

653

#define R_AUD_SDM_MUTE_L_MASK_SFT (0x1 << 5)

654

#define R_AUD_SDM_MUTE_R_SFT 4

655

#define R_AUD_SDM_MUTE_R_MASK 0x1

656

#define R_AUD_SDM_MUTE_R_MASK_SFT (0x1 << 4)

657

658

/* AFE_SGEN_CFG1 */

659

#define C_SGEN_RCH_INV_5BIT_SFT 15

660

#define C_SGEN_RCH_INV_5BIT_MASK 0x1

661

#define C_SGEN_RCH_INV_5BIT_MASK_SFT (0x1 << 15)

662

#define C_SGEN_RCH_INV_8BIT_SFT 14

663

#define C_SGEN_RCH_INV_8BIT_MASK 0x1

664

#define C_SGEN_RCH_INV_8BIT_MASK_SFT (0x1 << 14)

665

#define SGEN_FREQ_DIV_CH1_CTL_SFT 0

666

#define SGEN_FREQ_DIV_CH1_CTL_MASK 0x1f

667

#define SGEN_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 0)

668

669

/* AFE_ADC_ASYNC_FIFO_CFG */

670

#define RG_UL_ASYNC_FIFO_SOFT_RST_EN_SFT 5

671

#define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1

672

#define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)

673

#define RG_UL_ASYNC_FIFO_SOFT_RST_SFT 4

674

#define RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1

675

#define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)

676

#define RG_AMIC_UL_ADC_CLK_SEL_SFT 1

677

#define RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1

678

#define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT (0x1 << 1)

679

680

/* AFE_DCCLK_CFG0 */

681

#define DCCLK_DIV_SFT 5

682

#define DCCLK_DIV_MASK 0x7ff

683

#define DCCLK_DIV_MASK_SFT (0x7ff << 5)

684

#define DCCLK_INV_SFT 4

685

#define DCCLK_INV_MASK 0x1

686

#define DCCLK_INV_MASK_SFT (0x1 << 4)

687

#define DCCLK_PDN_SFT 1

688

#define DCCLK_PDN_MASK 0x1

689

#define DCCLK_PDN_MASK_SFT (0x1 << 1)

690

#define DCCLK_GEN_ON_SFT 0

691

#define DCCLK_GEN_ON_MASK 0x1

692

#define DCCLK_GEN_ON_MASK_SFT (0x1 << 0)

693

694

/* AFE_DCCLK_CFG1 */

695

#define RESYNC_SRC_SEL_SFT 10

696

#define RESYNC_SRC_SEL_MASK 0x3

697

#define RESYNC_SRC_SEL_MASK_SFT (0x3 << 10)

698

#define RESYNC_SRC_CK_INV_SFT 9

699

#define RESYNC_SRC_CK_INV_MASK 0x1

700

#define RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 9)

701

#define DCCLK_RESYNC_BYPASS_SFT 8

702

#define DCCLK_RESYNC_BYPASS_MASK 0x1

703

#define DCCLK_RESYNC_BYPASS_MASK_SFT (0x1 << 8)

704

#define DCCLK_PHASE_SEL_SFT 4

705

#define DCCLK_PHASE_SEL_MASK 0xf

706

#define DCCLK_PHASE_SEL_MASK_SFT (0xf << 4)

707

708

/* AUDIO_DIG_CFG */

709

#define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT 15

710

#define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1

711

#define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT (0x1 << 15)

712

#define RG_AUD_PAD_TOP_PHASE_MODE2_SFT 8

713

#define RG_AUD_PAD_TOP_PHASE_MODE2_MASK 0x7f

714

#define RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT (0x7f << 8)

715

#define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT 7

716

#define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1

717

#define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT (0x1 << 7)

718

#define RG_AUD_PAD_TOP_PHASE_MODE_SFT 0

719

#define RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7f

720

#define RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT (0x7f << 0)

721

722

/* AFE_AUD_PAD_TOP */

723

#define RG_AUD_PAD_TOP_TX_FIFO_RSP_SFT 12

724

#define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x7

725

#define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT (0x7 << 12)

726

#define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SFT 11

727

#define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1

728

#define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT (0x1 << 11)

729

#define RG_AUD_PAD_TOP_TX_FIFO_ON_SFT 8

730

#define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1

731

#define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT (0x1 << 8)

732

733

/* AFE_AUD_PAD_TOP_MON */

734

#define ADDA_AUD_PAD_TOP_MON_SFT 0

735

#define ADDA_AUD_PAD_TOP_MON_MASK 0xffff

736

#define ADDA_AUD_PAD_TOP_MON_MASK_SFT (0xffff << 0)

737

738

/* AFE_AUD_PAD_TOP_MON1 */

739

#define ADDA_AUD_PAD_TOP_MON1_SFT 0

740

#define ADDA_AUD_PAD_TOP_MON1_MASK 0xffff

741

#define ADDA_AUD_PAD_TOP_MON1_MASK_SFT (0xffff << 0)

742

743

/* AFE_CG_EN_MON */

744

#define AFE_CG_EN_MON_SFT 0

745

#define AFE_CG_EN_MON_MASK 0x3f

746

#define AFE_CG_EN_MON_MASK_SFT (0x3f << 0)

747

748

/* AUDENC_DSN_ID */

749

#define AUDENC_ANA_ID_SFT 0

750

#define AUDENC_ANA_ID_MASK 0xff

751

#define AUDENC_ANA_ID_MASK_SFT (0xff << 0)

752

#define AUDENC_DIG_ID_SFT 8

753

#define AUDENC_DIG_ID_MASK 0xff

754

#define AUDENC_DIG_ID_MASK_SFT (0xff << 8)

755

756

/* AUDENC_DSN_REV0 */

757

#define AUDENC_ANA_MINOR_REV_SFT 0

758

#define AUDENC_ANA_MINOR_REV_MASK 0xf

759

#define AUDENC_ANA_MINOR_REV_MASK_SFT (0xf << 0)

760

#define AUDENC_ANA_MAJOR_REV_SFT 4

761

#define AUDENC_ANA_MAJOR_REV_MASK 0xf

762

#define AUDENC_ANA_MAJOR_REV_MASK_SFT (0xf << 4)

763

#define AUDENC_DIG_MINOR_REV_SFT 8

764

#define AUDENC_DIG_MINOR_REV_MASK 0xf

765

#define AUDENC_DIG_MINOR_REV_MASK_SFT (0xf << 8)

766

#define AUDENC_DIG_MAJOR_REV_SFT 12

767

#define AUDENC_DIG_MAJOR_REV_MASK 0xf

768

#define AUDENC_DIG_MAJOR_REV_MASK_SFT (0xf << 12)

769

770

/* AUDENC_DSN_DBI */

771

#define AUDENC_DSN_CBS_SFT 0

772

#define AUDENC_DSN_CBS_MASK 0x3

773

#define AUDENC_DSN_CBS_MASK_SFT (0x3 << 0)

774

#define AUDENC_DSN_BIX_SFT 2

775

#define AUDENC_DSN_BIX_MASK 0x3

776

#define AUDENC_DSN_BIX_MASK_SFT (0x3 << 2)

777

#define AUDENC_DSN_ESP_SFT 8

778

#define AUDENC_DSN_ESP_MASK 0xff

779

#define AUDENC_DSN_ESP_MASK_SFT (0xff << 8)

780

781

/* AUDENC_DSN_FPI */

782

#define AUDENC_DSN_FPI_SFT 0

783

#define AUDENC_DSN_FPI_MASK 0xff

784

#define AUDENC_DSN_FPI_MASK_SFT (0xff << 0)

785

786

/* AUDENC_ANA_CON0 */

787

#define RG_AUDPREAMPLON_SFT 0

788

#define RG_AUDPREAMPLON_MASK 0x1

789

#define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)

790

#define RG_AUDPREAMPLDCCEN_SFT 1

791

#define RG_AUDPREAMPLDCCEN_MASK 0x1

792

#define RG_AUDPREAMPLDCCEN_MASK_SFT (0x1 << 1)

793

#define RG_AUDPREAMPLDCRPECHARGE_SFT 2

794

#define RG_AUDPREAMPLDCRPECHARGE_MASK 0x1

795

#define RG_AUDPREAMPLDCRPECHARGE_MASK_SFT (0x1 << 2)

796

#define RG_AUDPREAMPLPGATEST_SFT 3

797

#define RG_AUDPREAMPLPGATEST_MASK 0x1

798

#define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3)

799

#define RG_AUDPREAMPLVSCALE_SFT 4

800

#define RG_AUDPREAMPLVSCALE_MASK 0x3

801

#define RG_AUDPREAMPLVSCALE_MASK_SFT (0x3 << 4)

802

#define RG_AUDPREAMPLINPUTSEL_SFT 6

803

#define RG_AUDPREAMPLINPUTSEL_MASK 0x3

804

#define RG_AUDPREAMPLINPUTSEL_MASK_SFT (0x3 << 6)

805

#define RG_AUDPREAMPLGAIN_SFT 8

806

#define RG_AUDPREAMPLGAIN_MASK 0x7

807

#define RG_AUDPREAMPLGAIN_MASK_SFT (0x7 << 8)

808

#define RG_AUDADCLPWRUP_SFT 12

809

#define RG_AUDADCLPWRUP_MASK 0x1

810

#define RG_AUDADCLPWRUP_MASK_SFT (0x1 << 12)

811

#define RG_AUDADCLINPUTSEL_SFT 13

812

#define RG_AUDADCLINPUTSEL_MASK 0x3

813

#define RG_AUDADCLINPUTSEL_MASK_SFT (0x3 << 13)

814

#define RG_AUDPREAMPLSE_SFT 15

815

#define RG_AUDPREAMPLSE_MASK 0x1

816

#define RG_AUDPREAMPLSE_MASK_SFT (0x1 << 15)

817

818

/* AUDENC_ANA_CON1 */

819

#define RG_AUDPREAMPRON_SFT 0

820

#define RG_AUDPREAMPRON_MASK 0x1

821

#define RG_AUDPREAMPRON_MASK_SFT (0x1 << 0)

822

#define RG_AUDPREAMPRDCCEN_SFT 1

823

#define RG_AUDPREAMPRDCCEN_MASK 0x1

824

#define RG_AUDPREAMPRDCCEN_MASK_SFT (0x1 << 1)

825

#define RG_AUDPREAMPRDCRPECHARGE_SFT 2

826

#define RG_AUDPREAMPRDCRPECHARGE_MASK 0x1

827

#define RG_AUDPREAMPRDCRPECHARGE_MASK_SFT (0x1 << 2)

828

#define RG_AUDPREAMPRPGATEST_SFT 3

829

#define RG_AUDPREAMPRPGATEST_MASK 0x1

830

#define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3)

831

#define RG_AUDPREAMPRVSCALE_SFT 4

832

#define RG_AUDPREAMPRVSCALE_MASK 0x3

833

#define RG_AUDPREAMPRVSCALE_MASK_SFT (0x3 << 4)

834

#define RG_AUDPREAMPRINPUTSEL_SFT 6

835

#define RG_AUDPREAMPRINPUTSEL_MASK 0x3

836

#define RG_AUDPREAMPRINPUTSEL_MASK_SFT (0x3 << 6)

837

#define RG_AUDPREAMPRGAIN_SFT 8

838

#define RG_AUDPREAMPRGAIN_MASK 0x7

839

#define RG_AUDPREAMPRGAIN_MASK_SFT (0x7 << 8)

840

#define RG_AUDADCRPWRUP_SFT 12

841

#define RG_AUDADCRPWRUP_MASK 0x1

842

#define RG_AUDADCRPWRUP_MASK_SFT (0x1 << 12)

843

#define RG_AUDADCRINPUTSEL_SFT 13

844

#define RG_AUDADCRINPUTSEL_MASK 0x3

845

#define RG_AUDADCRINPUTSEL_MASK_SFT (0x3 << 13)

846

#define RG_AUDPREAMPRSE_SFT 15

847

#define RG_AUDPREAMPRSE_MASK 0x1

848

#define RG_AUDPREAMPRSE_MASK_SFT (0x1 << 15)

849

850

/* AUDENC_ANA_CON2 */

851

#define RG_AUDULHALFBIAS_SFT 0

852

#define RG_AUDULHALFBIAS_MASK 0x1

853

#define RG_AUDULHALFBIAS_MASK_SFT (0x1 << 0)

854

#define RG_AUDGLBMADLPWEN_SFT 1

855

#define RG_AUDGLBMADLPWEN_MASK 0x1

856

#define RG_AUDGLBMADLPWEN_MASK_SFT (0x1 << 1)

857

#define RG_AUDPREAMPLPEN_SFT 2

858

#define RG_AUDPREAMPLPEN_MASK 0x1

859

#define RG_AUDPREAMPLPEN_MASK_SFT (0x1 << 2)

860

#define RG_AUDADC1STSTAGELPEN_SFT 3

861

#define RG_AUDADC1STSTAGELPEN_MASK 0x1

862

#define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3)

863

#define RG_AUDADC2NDSTAGELPEN_SFT 4

864

#define RG_AUDADC2NDSTAGELPEN_MASK 0x1

865

#define RG_AUDADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)

866

#define RG_AUDADCFLASHLPEN_SFT 5

867

#define RG_AUDADCFLASHLPEN_MASK 0x1

868

#define RG_AUDADCFLASHLPEN_MASK_SFT (0x1 << 5)

869

#define RG_AUDPREAMPIDDTEST_SFT 6

870

#define RG_AUDPREAMPIDDTEST_MASK 0x3

871

#define RG_AUDPREAMPIDDTEST_MASK_SFT (0x3 << 6)

872

#define RG_AUDADC1STSTAGEIDDTEST_SFT 8

873

#define RG_AUDADC1STSTAGEIDDTEST_MASK 0x3

874

#define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)

875

#define RG_AUDADC2NDSTAGEIDDTEST_SFT 10

876

#define RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3

877

#define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)

878

#define RG_AUDADCREFBUFIDDTEST_SFT 12

879

#define RG_AUDADCREFBUFIDDTEST_MASK 0x3

880

#define RG_AUDADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)

881

#define RG_AUDADCFLASHIDDTEST_SFT 14

882

#define RG_AUDADCFLASHIDDTEST_MASK 0x3

883

#define RG_AUDADCFLASHIDDTEST_MASK_SFT (0x3 << 14)

884

885

/* AUDENC_ANA_CON3 */

886

#define RG_AUDADCDAC0P25FS_SFT 0

887

#define RG_AUDADCDAC0P25FS_MASK 0x1

888

#define RG_AUDADCDAC0P25FS_MASK_SFT (0x1 << 0)

889

#define RG_AUDADCCLKSEL_SFT 1

890

#define RG_AUDADCCLKSEL_MASK 0x1

891

#define RG_AUDADCCLKSEL_MASK_SFT (0x1 << 1)

892

#define RG_AUDADCCLKSOURCE_SFT 2

893

#define RG_AUDADCCLKSOURCE_MASK 0x3

894

#define RG_AUDADCCLKSOURCE_MASK_SFT (0x3 << 2)

895

#define RG_AUDPREAMPAAFEN_SFT 8

896

#define RG_AUDPREAMPAAFEN_MASK 0x1

897

#define RG_AUDPREAMPAAFEN_MASK_SFT (0x1 << 8)

898

#define RG_DCCVCMBUFLPMODSEL_SFT 9

899

#define RG_DCCVCMBUFLPMODSEL_MASK 0x1

900

#define RG_DCCVCMBUFLPMODSEL_MASK_SFT (0x1 << 9)

901

#define RG_DCCVCMBUFLPSWEN_SFT 10

902

#define RG_DCCVCMBUFLPSWEN_MASK 0x1

903

#define RG_DCCVCMBUFLPSWEN_MASK_SFT (0x1 << 10)

904

#define RG_AUDSPAREPGA_SFT 11

905

#define RG_AUDSPAREPGA_MASK 0x1

906

#define RG_AUDSPAREPGA_MASK_SFT (0x1 << 11)

907

908

/* AUDENC_ANA_CON4 */

909

#define RG_AUDADC1STSTAGESDENB_SFT 0

910

#define RG_AUDADC1STSTAGESDENB_MASK 0x1

911

#define RG_AUDADC1STSTAGESDENB_MASK_SFT (0x1 << 0)

912

#define RG_AUDADC2NDSTAGERESET_SFT 1

913

#define RG_AUDADC2NDSTAGERESET_MASK 0x1

914

#define RG_AUDADC2NDSTAGERESET_MASK_SFT (0x1 << 1)

915

#define RG_AUDADC3RDSTAGERESET_SFT 2

916

#define RG_AUDADC3RDSTAGERESET_MASK 0x1

917

#define RG_AUDADC3RDSTAGERESET_MASK_SFT (0x1 << 2)

918

#define RG_AUDADCFSRESET_SFT 3

919

#define RG_AUDADCFSRESET_MASK 0x1

920

#define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3)

921

#define RG_AUDADCWIDECM_SFT 4

922

#define RG_AUDADCWIDECM_MASK 0x1

923

#define RG_AUDADCWIDECM_MASK_SFT (0x1 << 4)

924

#define RG_AUDADCNOPATEST_SFT 5

925

#define RG_AUDADCNOPATEST_MASK 0x1

926

#define RG_AUDADCNOPATEST_MASK_SFT (0x1 << 5)

927

#define RG_AUDADCBYPASS_SFT 6

928

#define RG_AUDADCBYPASS_MASK 0x1

929

#define RG_AUDADCBYPASS_MASK_SFT (0x1 << 6)

930

#define RG_AUDADCFFBYPASS_SFT 7

931

#define RG_AUDADCFFBYPASS_MASK 0x1

932

#define RG_AUDADCFFBYPASS_MASK_SFT (0x1 << 7)

933

#define RG_AUDADCDACFBCURRENT_SFT 8

934

#define RG_AUDADCDACFBCURRENT_MASK 0x1

935

#define RG_AUDADCDACFBCURRENT_MASK_SFT (0x1 << 8)

936

#define RG_AUDADCDACIDDTEST_SFT 9

937

#define RG_AUDADCDACIDDTEST_MASK 0x3

938

#define RG_AUDADCDACIDDTEST_MASK_SFT (0x3 << 9)

939

#define RG_AUDADCDACNRZ_SFT 11

940

#define RG_AUDADCDACNRZ_MASK 0x1

941

#define RG_AUDADCDACNRZ_MASK_SFT (0x1 << 11)

942

#define RG_AUDADCNODEM_SFT 12

943

#define RG_AUDADCNODEM_MASK 0x1

944

#define RG_AUDADCNODEM_MASK_SFT (0x1 << 12)

945

#define RG_AUDADCDACTEST_SFT 13

946

#define RG_AUDADCDACTEST_MASK 0x1

947

#define RG_AUDADCDACTEST_MASK_SFT (0x1 << 13)

948

949

/* AUDENC_ANA_CON5 */

950

#define RG_CLKSQ_EN_SFT 0

951

#define RG_CLKSQ_EN_MASK 0x1

952

#define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)

953

#define RG_CLKSQ_IN_SEL_SFT 1

954

#define RG_CLKSQ_IN_SEL_MASK 0x1

955

#define RG_CLKSQ_IN_SEL_MASK_SFT (0x1 << 1)

956

#define RG_AUDSPARE2VA28_SFT 2

957

#define RG_AUDSPARE2VA28_MASK 0x3fff

958

#define RG_AUDSPARE2VA28_MASK_SFT (0x3fff << 2)

959

960

/* AUDENC_ANA_CON6 */

961

#define RG_AUDRCTUNEL_SFT 0

962

#define RG_AUDRCTUNEL_MASK 0x1f

963

#define RG_AUDRCTUNEL_MASK_SFT (0x1f << 0)

964

#define RG_AUDRCTUNELSEL_SFT 5

965

#define RG_AUDRCTUNELSEL_MASK 0x1

966

#define RG_AUDRCTUNELSEL_MASK_SFT (0x1 << 5)

967

#define RG_AUDRCTUNER_SFT 8

968

#define RG_AUDRCTUNER_MASK 0x1f

969

#define RG_AUDRCTUNER_MASK_SFT (0x1f << 8)

970

#define RG_AUDRCTUNERSEL_SFT 13

971

#define RG_AUDRCTUNERSEL_MASK 0x1

972

#define RG_AUDRCTUNERSEL_MASK_SFT (0x1 << 13)

973

974

/* AUDENC_ANA_CON7 */

975

#define RG_AUDSPAREVA28_SFT 0

976

#define RG_AUDSPAREVA28_MASK 0xf

977

#define RG_AUDSPAREVA28_MASK_SFT (0xf << 0)

978

#define RG_AUDSPAREVA18_SFT 4

979

#define RG_AUDSPAREVA18_MASK 0xf

980

#define RG_AUDSPAREVA18_MASK_SFT (0xf << 4)

981

#define RG_AUDENCSPAREVA28_SFT 8

982

#define RG_AUDENCSPAREVA28_MASK 0xf

983

#define RG_AUDENCSPAREVA28_MASK_SFT (0xf << 8)

984

#define RG_AUDENCSPAREVA18_SFT 12

985

#define RG_AUDENCSPAREVA18_MASK 0xf

986

#define RG_AUDENCSPAREVA18_MASK_SFT (0xf << 12)

987

988

/* AUDENC_ANA_CON8 */

989

#define RG_AUDDIGMICEN_SFT 0

990

#define RG_AUDDIGMICEN_MASK 0x1

991

#define RG_AUDDIGMICEN_MASK_SFT (0x1 << 0)

992

#define RG_AUDDIGMICBIAS_SFT 1

993

#define RG_AUDDIGMICBIAS_MASK 0x3

994

#define RG_AUDDIGMICBIAS_MASK_SFT (0x3 << 1)

995

#define RG_DMICHPCLKEN_SFT 3

996

#define RG_DMICHPCLKEN_MASK 0x1

997

#define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3)

998

#define RG_AUDDIGMICPDUTY_SFT 4

999

#define RG_AUDDIGMICPDUTY_MASK 0x3

1000

#define RG_AUDDIGMICPDUTY_MASK_SFT (0x3 << 4)

1001

#define RG_AUDDIGMICNDUTY_SFT 6

1002

#define RG_AUDDIGMICNDUTY_MASK 0x3

1003

#define RG_AUDDIGMICNDUTY_MASK_SFT (0x3 << 6)

1004

#define RG_DMICMONEN_SFT 8

1005

#define RG_DMICMONEN_MASK 0x1

1006

#define RG_DMICMONEN_MASK_SFT (0x1 << 8)

1007

#define RG_DMICMONSEL_SFT 9

1008

#define RG_DMICMONSEL_MASK 0x7

1009

#define RG_DMICMONSEL_MASK_SFT (0x7 << 9)

1010

#define RG_AUDSPAREVMIC_SFT 12

1011

#define RG_AUDSPAREVMIC_MASK 0xf

1012

#define RG_AUDSPAREVMIC_MASK_SFT (0xf << 12)

1013

1014

/* AUDENC_ANA_CON9 */

1015

#define RG_AUDPWDBMICBIAS0_SFT 0

1016

#define RG_AUDPWDBMICBIAS0_MASK 0x1

1017

#define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)

1018

#define RG_AUDMICBIAS0BYPASSEN_SFT 1

1019

#define RG_AUDMICBIAS0BYPASSEN_MASK 0x1

1020

#define RG_AUDMICBIAS0BYPASSEN_MASK_SFT (0x1 << 1)

1021

#define RG_AUDMICBIAS0LOWPEN_SFT 2

1022

#define RG_AUDMICBIAS0LOWPEN_MASK 0x1

1023

#define RG_AUDMICBIAS0LOWPEN_MASK_SFT (0x1 << 2)

1024

#define RG_AUDMICBIAS0VREF_SFT 4

1025

#define RG_AUDMICBIAS0VREF_MASK 0x7

1026

#define RG_AUDMICBIAS0VREF_MASK_SFT (0x7 << 4)

1027

#define RG_AUDMICBIAS0DCSW0P1EN_SFT 8

1028

#define RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1

1029

#define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT (0x1 << 8)

1030

#define RG_AUDMICBIAS0DCSW0P2EN_SFT 9

1031

#define RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1

1032

#define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT (0x1 << 9)

1033

#define RG_AUDMICBIAS0DCSW0NEN_SFT 10

1034

#define RG_AUDMICBIAS0DCSW0NEN_MASK 0x1

1035

#define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT (0x1 << 10)

1036

#define RG_AUDMICBIAS0DCSW2P1EN_SFT 12

1037

#define RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1

1038

#define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT (0x1 << 12)

1039

#define RG_AUDMICBIAS0DCSW2P2EN_SFT 13

1040

#define RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1

1041

#define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT (0x1 << 13)

1042

#define RG_AUDMICBIAS0DCSW2NEN_SFT 14

1043

#define RG_AUDMICBIAS0DCSW2NEN_MASK 0x1

1044

#define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT (0x1 << 14)

1045

1046

/* AUDENC_ANA_CON10 */

1047

#define RG_AUDPWDBMICBIAS1_SFT 0

1048

#define RG_AUDPWDBMICBIAS1_MASK 0x1

1049

#define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)

1050

#define RG_AUDMICBIAS1BYPASSEN_SFT 1

1051

#define RG_AUDMICBIAS1BYPASSEN_MASK 0x1

1052

#define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)

1053

#define RG_AUDMICBIAS1LOWPEN_SFT 2

1054

#define RG_AUDMICBIAS1LOWPEN_MASK 0x1

1055

#define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)

1056

#define RG_AUDMICBIAS1VREF_SFT 4

1057

#define RG_AUDMICBIAS1VREF_MASK 0x7

1058

#define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)

1059

#define RG_AUDMICBIAS1DCSW1PEN_SFT 8

1060

#define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1

1061

#define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)

1062

#define RG_AUDMICBIAS1DCSW1NEN_SFT 9

1063

#define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1

1064

#define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)

1065

#define RG_BANDGAPGEN_SFT 12

1066

#define RG_BANDGAPGEN_MASK 0x1

1067

#define RG_BANDGAPGEN_MASK_SFT (0x1 << 12)

1068

1069

/* AUDENC_ANA_CON11 */

1070

#define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0

1071

#define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1

1072

#define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)

1073

#define RG_AUDACCDETMICBIAS1PULLLOW_SFT 1

1074

#define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1

1075

#define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)

1076

#define RG_AUDACCDETVIN1PULLLOW_SFT 2

1077

#define RG_AUDACCDETVIN1PULLLOW_MASK 0x1

1078

#define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 2)

1079

#define RG_AUDACCDETVTHACAL_SFT 4

1080

#define RG_AUDACCDETVTHACAL_MASK 0x1

1081

#define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)

1082

#define RG_AUDACCDETVTHBCAL_SFT 5

1083

#define RG_AUDACCDETVTHBCAL_MASK 0x1

1084

#define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)

1085

#define RG_AUDACCDETTVDET_SFT 6

1086

#define RG_AUDACCDETTVDET_MASK 0x1

1087

#define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)

1088

#define RG_ACCDETSEL_SFT 7

1089

#define RG_ACCDETSEL_MASK 0x1

1090

#define RG_ACCDETSEL_MASK_SFT (0x1 << 7)

1091

#define RG_SWBUFMODSEL_SFT 8

1092

#define RG_SWBUFMODSEL_MASK 0x1

1093

#define RG_SWBUFMODSEL_MASK_SFT (0x1 << 8)

1094

#define RG_SWBUFSWEN_SFT 9

1095

#define RG_SWBUFSWEN_MASK 0x1

1096

#define RG_SWBUFSWEN_MASK_SFT (0x1 << 9)

1097

#define RG_EINTCOMPVTH_SFT 10

1098

#define RG_EINTCOMPVTH_MASK 0x1

1099

#define RG_EINTCOMPVTH_MASK_SFT (0x1 << 10)

1100

#define RG_EINTCONFIGACCDET_SFT 11

1101

#define RG_EINTCONFIGACCDET_MASK 0x1

1102

#define RG_EINTCONFIGACCDET_MASK_SFT (0x1 << 11)

1103

#define RG_EINTHIRENB_SFT 12

1104

#define RG_EINTHIRENB_MASK 0x1

1105

#define RG_EINTHIRENB_MASK_SFT (0x1 << 12)

1106

#define RG_ACCDETSPAREVA28_SFT 13

1107

#define RG_ACCDETSPAREVA28_MASK 0x7

1108

#define RG_ACCDETSPAREVA28_MASK_SFT (0x7 << 13)

1109

1110

/* AUDENC_ANA_CON12 */

1111

#define RGS_AUDRCTUNELREAD_SFT 0

1112

#define RGS_AUDRCTUNELREAD_MASK 0x1f

1113

#define RGS_AUDRCTUNELREAD_MASK_SFT (0x1f << 0)

1114

#define RGS_AUDRCTUNERREAD_SFT 8

1115

#define RGS_AUDRCTUNERREAD_MASK 0x1f

1116

#define RGS_AUDRCTUNERREAD_MASK_SFT (0x1f << 8)

1117

1118

/* AUDDEC_DSN_ID */

1119

#define AUDDEC_ANA_ID_SFT 0

1120

#define AUDDEC_ANA_ID_MASK 0xff

1121

#define AUDDEC_ANA_ID_MASK_SFT (0xff << 0)

1122

#define AUDDEC_DIG_ID_SFT 8

1123

#define AUDDEC_DIG_ID_MASK 0xff

1124

#define AUDDEC_DIG_ID_MASK_SFT (0xff << 8)

1125

1126

/* AUDDEC_DSN_REV0 */

1127

#define AUDDEC_ANA_MINOR_REV_SFT 0

1128

#define AUDDEC_ANA_MINOR_REV_MASK 0xf

1129

#define AUDDEC_ANA_MINOR_REV_MASK_SFT (0xf << 0)

1130

#define AUDDEC_ANA_MAJOR_REV_SFT 4

1131

#define AUDDEC_ANA_MAJOR_REV_MASK 0xf

1132

#define AUDDEC_ANA_MAJOR_REV_MASK_SFT (0xf << 4)

1133

#define AUDDEC_DIG_MINOR_REV_SFT 8

1134

#define AUDDEC_DIG_MINOR_REV_MASK 0xf

1135

#define AUDDEC_DIG_MINOR_REV_MASK_SFT (0xf << 8)

1136

#define AUDDEC_DIG_MAJOR_REV_SFT 12

1137

#define AUDDEC_DIG_MAJOR_REV_MASK 0xf

1138

#define AUDDEC_DIG_MAJOR_REV_MASK_SFT (0xf << 12)

1139

1140

/* AUDDEC_DSN_DBI */

1141

#define AUDDEC_DSN_CBS_SFT 0

1142

#define AUDDEC_DSN_CBS_MASK 0x3

1143

#define AUDDEC_DSN_CBS_MASK_SFT (0x3 << 0)

1144

#define AUDDEC_DSN_BIX_SFT 2

1145

#define AUDDEC_DSN_BIX_MASK 0x3

1146

#define AUDDEC_DSN_BIX_MASK_SFT (0x3 << 2)

1147

#define AUDDEC_DSN_ESP_SFT 8

1148

#define AUDDEC_DSN_ESP_MASK 0xff

1149

#define AUDDEC_DSN_ESP_MASK_SFT (0xff << 8)

1150

1151

/* AUDDEC_DSN_FPI */

1152

#define AUDDEC_DSN_FPI_SFT 0

1153

#define AUDDEC_DSN_FPI_MASK 0xff

1154

#define AUDDEC_DSN_FPI_MASK_SFT (0xff << 0)

1155

1156

/* AUDDEC_ANA_CON0 */

1157

#define RG_AUDDACLPWRUP_VAUDP15_SFT 0

1158

#define RG_AUDDACLPWRUP_VAUDP15_MASK 0x1

1159

#define RG_AUDDACLPWRUP_VAUDP15_MASK_SFT (0x1 << 0)

1160

#define RG_AUDDACRPWRUP_VAUDP15_SFT 1

1161

#define RG_AUDDACRPWRUP_VAUDP15_MASK 0x1

1162

#define RG_AUDDACRPWRUP_VAUDP15_MASK_SFT (0x1 << 1)

1163

#define RG_AUD_DAC_PWR_UP_VA28_SFT 2

1164

#define RG_AUD_DAC_PWR_UP_VA28_MASK 0x1

1165

#define RG_AUD_DAC_PWR_UP_VA28_MASK_SFT (0x1 << 2)

1166

#define RG_AUD_DAC_PWL_UP_VA28_SFT 3

1167

#define RG_AUD_DAC_PWL_UP_VA28_MASK 0x1

1168

#define RG_AUD_DAC_PWL_UP_VA28_MASK_SFT (0x1 << 3)

1169

#define RG_AUDOUT0_MUX_VAUDP28_SFT 4

1170

#define RG_AUDOUT0_MUX_VAUDP28_MASK 0x7

1171

#define RG_AUDOUT0_MUX_VAUDP28_MASK_SFT (0x7 << 4)

1172

#define RG_AUDOUT1_MUX_VAUDP28_SFT 8

1173

#define RG_AUDOUT1_MUX_VAUDP28_MASK 0x7

1174

#define RG_AUDOUT1_MUX_VAUDP28_MASK_SFT (0x7 << 8)

1175

#define RG_AUDOUT2_MUX_VAUDP28_SFT 12

1176

#define RG_AUDOUT2_MUX_VAUDP28_MASK 0x7

1177

#define RG_AUDOUT2_MUX_VAUDP28_MASK_SFT (0x7 << 12)

1178

1179

/* AUDDEC_ANA_CON1 */

1180

#define RG_AUDVCMBUF_EN_VAUDP28_SFT 0

1181

#define RG_AUDVCMBUF_EN_VAUDP28_MASK 0x1

1182

#define RG_AUDVCMBUF_EN_VAUDP28_MASK_SFT (0x1 << 0)

1183

#define RG_AUDVCMBUF_VOSEL_VAUDP28_SFT 4

1184

#define RG_AUDVCMBUF_VOSEL_VAUDP28_MASK 0x7

1185

#define RG_AUDVCMBUF_VOSEL_VAUDP28_MASK_SFT (0x7 << 4)

1186

#define RG_AUDVCM2OUT0P_SW_EN_VAUDP28_SFT 8

1187

#define RG_AUDVCM2OUT0P_SW_EN_VAUDP28_MASK 0x1

1188

#define RG_AUDVCM2OUT0P_SW_EN_VAUDP28_MASK_SFT (0x1 << 8)

1189

#define RG_AUDVCM2OUT0N_SW_EN_VAUDP28_SFT 9

1190

#define RG_AUDVCM2OUT0N_SW_EN_VAUDP28_MASK 0x1

1191

#define RG_AUDVCM2OUT0N_SW_EN_VAUDP28_MASK_SFT (0x1 << 9)

1192

#define RG_AUDVCM2OUT1P_SW_EN_VAUDP28_SFT 10

1193

#define RG_AUDVCM2OUT1P_SW_EN_VAUDP28_MASK 0x1

1194

#define RG_AUDVCM2OUT1P_SW_EN_VAUDP28_MASK_SFT (0x1 << 10)

1195

#define RG_AUDVCM2OUT1N_SW_EN_VAUDP28_SFT 11

1196

#define RG_AUDVCM2OUT1N_SW_EN_VAUDP28_MASK 0x1

1197

#define RG_AUDVCM2OUT1N_SW_EN_VAUDP28_MASK_SFT (0x1 << 11)

1198

#define RG_AUDVCM2OUT2P_SW_EN_VAUDP28_SFT 12

1199

#define RG_AUDVCM2OUT2P_SW_EN_VAUDP28_MASK 0x1

1200

#define RG_AUDVCM2OUT2P_SW_EN_VAUDP28_MASK_SFT (0x1 << 12)

1201

#define RG_AUDVCM2OUT2N_SW_EN_VAUDP28_SFT 13

1202

#define RG_AUDVCM2OUT2N_SW_EN_VAUDP28_MASK 0x1

1203

#define RG_AUDVCM2OUT2N_SW_EN_VAUDP28_MASK_SFT (0x1 << 13)

1204

1205

/* AUDDEC_ANA_CON2 */

1206

#define RG_AUDVCM2VIN0P_SW_EN_VAUDP28_SFT 0

1207

#define RG_AUDVCM2VIN0P_SW_EN_VAUDP28_MASK 0x1

1208

#define RG_AUDVCM2VIN0P_SW_EN_VAUDP28_MASK_SFT (0x1 << 0)

1209

#define RG_AUDVCM2VIN0N_SW_EN_VAUDP28_SFT 1

1210

#define RG_AUDVCM2VIN0N_SW_EN_VAUDP28_MASK 0x1

1211

#define RG_AUDVCM2VIN0N_SW_EN_VAUDP28_MASK_SFT (0x1 << 1)

1212

#define RG_AUDVCM2VIN1P_SW_EN_VAUDP28_SFT 2

1213

#define RG_AUDVCM2VIN1P_SW_EN_VAUDP28_MASK 0x1

1214

#define RG_AUDVCM2VIN1P_SW_EN_VAUDP28_MASK_SFT (0x1 << 2)

1215

#define RG_AUDVCM2VIN1N_SW_EN_VAUDP28_SFT 3

1216

#define RG_AUDVCM2VIN1N_SW_EN_VAUDP28_MASK 0x1

1217

#define RG_AUDVCM2VIN1N_SW_EN_VAUDP28_MASK_SFT (0x1 << 3)

1218

#define RG_AUDREFN_DERES_EN_VAUDP28_SFT 4

1219

#define RG_AUDREFN_DERES_EN_VAUDP28_MASK 0x1

1220

#define RG_AUDREFN_DERES_EN_VAUDP28_MASK_SFT (0x1 << 4)

1221

#define RG_ABIDEC_RSVD0_VAUDP28_SFT 8

1222

#define RG_ABIDEC_RSVD0_VAUDP28_MASK 0xff

1223

#define RG_ABIDEC_RSVD0_VAUDP28_MASK_SFT (0xff << 8)

1224

1225

/* AUDDEC_ANA_CON3 */

1226

#define RG_ABIDEC_RSVD1_VAUDP28_SFT 0

1227

#define RG_ABIDEC_RSVD1_VAUDP28_MASK 0xff

1228

#define RG_ABIDEC_RSVD1_VAUDP28_MASK_SFT (0xff << 0)

1229

#define RG_ABIDEC_RSVD2_VAUDP28_SFT 8

1230

#define RG_ABIDEC_RSVD2_VAUDP28_MASK 0xff

1231

#define RG_ABIDEC_RSVD2_VAUDP28_MASK_SFT (0xff << 8)

1232

1233

/* AUDDEC_ANA_CON4 */

1234

#define RG_AUDHSPWRUP_VAUDP15_SFT 0

1235

#define RG_AUDHSPWRUP_VAUDP15_MASK 0x1

1236

#define RG_AUDHSPWRUP_VAUDP15_MASK_SFT (0x1 << 0)

1237

#define RG_AUDHSPWRUP_IBIAS_VAUDP15_SFT 1

1238

#define RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK 0x1

1239

#define RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 1)

1240

#define RG_AUDHSMUXINPUTSEL_VAUDP15_SFT 2

1241

#define RG_AUDHSMUXINPUTSEL_VAUDP15_MASK 0x3

1242

#define RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 2)

1243

#define RG_AUDHSSCDISABLE_VAUDP15_SFT 4

1244

#define RG_AUDHSSCDISABLE_VAUDP15_MASK 0x1

1245

#define RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT (0x1 << 4)

1246

#define RG_AUDHSBSCCURRENT_VAUDP15_SFT 5

1247

#define RG_AUDHSBSCCURRENT_VAUDP15_MASK 0x1

1248

#define RG_AUDHSBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 5)

1249

#define RG_AUDHSSTARTUP_VAUDP15_SFT 6

1250

#define RG_AUDHSSTARTUP_VAUDP15_MASK 0x1

1251

#define RG_AUDHSSTARTUP_VAUDP15_MASK_SFT (0x1 << 6)

1252

#define RG_HSOUTPUTSTBENH_VAUDP15_SFT 7

1253

#define RG_HSOUTPUTSTBENH_VAUDP15_MASK 0x1

1254

#define RG_HSOUTPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 7)

1255

#define RG_HSINPUTSTBENH_VAUDP15_SFT 8

1256

#define RG_HSINPUTSTBENH_VAUDP15_MASK 0x1

1257

#define RG_HSINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 8)

1258

#define RG_HSINPUTRESET0_VAUDP15_SFT 9

1259

#define RG_HSINPUTRESET0_VAUDP15_MASK 0x1

1260

#define RG_HSINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 9)

1261

#define RG_HSOUTPUTRESET0_VAUDP15_SFT 10

1262

#define RG_HSOUTPUTRESET0_VAUDP15_MASK 0x1

1263

#define RG_HSOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 10)

1264

#define RG_HSOUT_SHORTVCM_VAUDP15_SFT 11

1265

#define RG_HSOUT_SHORTVCM_VAUDP15_MASK 0x1

1266

#define RG_HSOUT_SHORTVCM_VAUDP15_MASK_SFT (0x1 << 11)

1267

1268

/* AUDDEC_ANA_CON5 */

1269

#define RG_AUDLOLPWRUP_VAUDP15_SFT 0

1270

#define RG_AUDLOLPWRUP_VAUDP15_MASK 0x1

1271

#define RG_AUDLOLPWRUP_VAUDP15_MASK_SFT (0x1 << 0)

1272

#define RG_AUDLOLPWRUP_IBIAS_VAUDP15_SFT 1

1273

#define RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK 0x1

1274

#define RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 1)

1275

#define RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT 2

1276

#define RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK 0x3

1277

#define RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 2)

1278

#define RG_AUDLOLSCDISABLE_VAUDP15_SFT 4

1279

#define RG_AUDLOLSCDISABLE_VAUDP15_MASK 0x1

1280

#define RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT (0x1 << 4)

1281

#define RG_AUDLOLBSCCURRENT_VAUDP15_SFT 5

1282

#define RG_AUDLOLBSCCURRENT_VAUDP15_MASK 0x1

1283

#define RG_AUDLOLBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 5)

1284

#define RG_AUDLOSTARTUP_VAUDP15_SFT 6

1285

#define RG_AUDLOSTARTUP_VAUDP15_MASK 0x1

1286

#define RG_AUDLOSTARTUP_VAUDP15_MASK_SFT (0x1 << 6)

1287

#define RG_LOINPUTSTBENH_VAUDP15_SFT 7

1288

#define RG_LOINPUTSTBENH_VAUDP15_MASK 0x1

1289

#define RG_LOINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 7)

1290

#define RG_LOOUTPUTSTBENH_VAUDP15_SFT 8

1291

#define RG_LOOUTPUTSTBENH_VAUDP15_MASK 0x1

1292

#define RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 8)

1293

#define RG_LOINPUTRESET0_VAUDP15_SFT 9

1294

#define RG_LOINPUTRESET0_VAUDP15_MASK 0x1

1295

#define RG_LOINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 9)

1296

#define RG_LOOUTPUTRESET0_VAUDP15_SFT 10

1297

#define RG_LOOUTPUTRESET0_VAUDP15_MASK 0x1

1298

#define RG_LOOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 10)

1299

#define RG_LOOUT_SHORTVCM_VAUDP15_SFT 11

1300

#define RG_LOOUT_SHORTVCM_VAUDP15_MASK 0x1

1301

#define RG_LOOUT_SHORTVCM_VAUDP15_MASK_SFT (0x1 << 11)

1302

1303

/* AUDDEC_ANA_CON6 */

1304

#define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_SFT 0

1305

#define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK 0xf

1306

#define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK_SFT (0xf << 0)

1307

#define RG_AUDTRIMBUF_GAINSEL_VAUDP15_SFT 4

1308

#define RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK 0x3

1309

#define RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK_SFT (0x3 << 4)

1310

#define RG_AUDTRIMBUF_EN_VAUDP15_SFT 6

1311

#define RG_AUDTRIMBUF_EN_VAUDP15_MASK 0x1

1312

#define RG_AUDTRIMBUF_EN_VAUDP15_MASK_SFT (0x1 << 6)

1313

#define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_SFT 8

1314

#define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK 0x3

1315

#define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK_SFT (0x3 << 8)

1316

#define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_SFT 10

1317

#define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK 0x3

1318

#define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK_SFT (0x3 << 10)

1319

#define RG_AUDHPSPKDET_EN_VAUDP15_SFT 12

1320

#define RG_AUDHPSPKDET_EN_VAUDP15_MASK 0x1

1321

#define RG_AUDHPSPKDET_EN_VAUDP15_MASK_SFT (0x1 << 12)

1322

1323

/* AUDDEC_ANA_CON7 */

1324

#define RG_ABIDEC_RSVD0_VA28_SFT 0

1325

#define RG_ABIDEC_RSVD0_VA28_MASK 0xff

1326

#define RG_ABIDEC_RSVD0_VA28_MASK_SFT (0xff << 0)

1327

#define RG_ABIDEC_RSVD0_VAUDP15_SFT 8

1328

#define RG_ABIDEC_RSVD0_VAUDP15_MASK 0xff

1329

#define RG_ABIDEC_RSVD0_VAUDP15_MASK_SFT (0xff << 8)

1330

1331

/* AUDDEC_ANA_CON8 */

1332

#define RG_ABIDEC_RSVD1_VAUDP15_SFT 0

1333

#define RG_ABIDEC_RSVD1_VAUDP15_MASK 0xff

1334

#define RG_ABIDEC_RSVD1_VAUDP15_MASK_SFT (0xff << 0)

1335

#define RG_ABIDEC_RSVD2_VAUDP15_SFT 8

1336

#define RG_ABIDEC_RSVD2_VAUDP15_MASK 0xff

1337

#define RG_ABIDEC_RSVD2_VAUDP15_MASK_SFT (0xff << 8)

1338

1339

/* AUDDEC_ANA_CON9 */

1340

#define RG_AUDZCDMUXSEL_VAUDP15_SFT 0

1341

#define RG_AUDZCDMUXSEL_VAUDP15_MASK 0x7

1342

#define RG_AUDZCDMUXSEL_VAUDP15_MASK_SFT (0x7 << 0)

1343

#define RG_AUDZCDCLKSEL_VAUDP15_SFT 3

1344

#define RG_AUDZCDCLKSEL_VAUDP15_MASK 0x1

1345

#define RG_AUDZCDCLKSEL_VAUDP15_MASK_SFT (0x1 << 3)

1346

#define RG_AUDBIASADJ_0_VAUDP15_SFT 7

1347

#define RG_AUDBIASADJ_0_VAUDP15_MASK 0x1ff

1348

#define RG_AUDBIASADJ_0_VAUDP15_MASK_SFT (0x1ff << 7)

1349

1350

/* AUDDEC_ANA_CON10 */

1351

#define RG_AUDBIASADJ_1_VAUDP15_SFT 0

1352

#define RG_AUDBIASADJ_1_VAUDP15_MASK 0xff

1353

#define RG_AUDBIASADJ_1_VAUDP15_MASK_SFT (0xff << 0)

1354

#define RG_AUDIBIASPWRDN_VAUDP15_SFT 8

1355

#define RG_AUDIBIASPWRDN_VAUDP15_MASK 0x1

1356

#define RG_AUDIBIASPWRDN_VAUDP15_MASK_SFT (0x1 << 8)

1357

1358

/* AUDDEC_ANA_CON11 */

1359

#define RG_RSTB_DECODER_VA28_SFT 0

1360

#define RG_RSTB_DECODER_VA28_MASK 0x1

1361

#define RG_RSTB_DECODER_VA28_MASK_SFT (0x1 << 0)

1362

#define RG_SEL_DECODER_96K_VA28_SFT 1

1363

#define RG_SEL_DECODER_96K_VA28_MASK 0x1

1364

#define RG_SEL_DECODER_96K_VA28_MASK_SFT (0x1 << 1)

1365

#define RG_SEL_DELAY_VCORE_SFT 2

1366

#define RG_SEL_DELAY_VCORE_MASK 0x1

1367

#define RG_SEL_DELAY_VCORE_MASK_SFT (0x1 << 2)

1368

#define RG_AUDGLB_PWRDN_VA28_SFT 4

1369

#define RG_AUDGLB_PWRDN_VA28_MASK 0x1

1370

#define RG_AUDGLB_PWRDN_VA28_MASK_SFT (0x1 << 4)

1371

#define RG_RSTB_ENCODER_VA28_SFT 5

1372

#define RG_RSTB_ENCODER_VA28_MASK 0x1

1373

#define RG_RSTB_ENCODER_VA28_MASK_SFT (0x1 << 5)

1374

#define RG_SEL_ENCODER_96K_VA28_SFT 6

1375

#define RG_SEL_ENCODER_96K_VA28_MASK 0x1

1376

#define RG_SEL_ENCODER_96K_VA28_MASK_SFT (0x1 << 6)

1377

1378

/* AUDDEC_ANA_CON12 */

1379

#define RG_HCLDO_EN_VA18_SFT 0

1380

#define RG_HCLDO_EN_VA18_MASK 0x1

1381

#define RG_HCLDO_EN_VA18_MASK_SFT (0x1 << 0)

1382

#define RG_HCLDO_PDDIS_EN_VA18_SFT 1

1383

#define RG_HCLDO_PDDIS_EN_VA18_MASK 0x1

1384

#define RG_HCLDO_PDDIS_EN_VA18_MASK_SFT (0x1 << 1)

1385

#define RG_HCLDO_REMOTE_SENSE_VA18_SFT 2

1386

#define RG_HCLDO_REMOTE_SENSE_VA18_MASK 0x1

1387

#define RG_HCLDO_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 2)

1388

#define RG_LCLDO_EN_VA18_SFT 4

1389

#define RG_LCLDO_EN_VA18_MASK 0x1

1390

#define RG_LCLDO_EN_VA18_MASK_SFT (0x1 << 4)

1391

#define RG_LCLDO_PDDIS_EN_VA18_SFT 5

1392

#define RG_LCLDO_PDDIS_EN_VA18_MASK 0x1

1393

#define RG_LCLDO_PDDIS_EN_VA18_MASK_SFT (0x1 << 5)

1394

#define RG_LCLDO_REMOTE_SENSE_VA18_SFT 6

1395

#define RG_LCLDO_REMOTE_SENSE_VA18_MASK 0x1

1396

#define RG_LCLDO_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 6)

1397

#define RG_LCLDO_ENC_EN_VA28_SFT 8

1398

#define RG_LCLDO_ENC_EN_VA28_MASK 0x1

1399

#define RG_LCLDO_ENC_EN_VA28_MASK_SFT (0x1 << 8)

1400

#define RG_LCLDO_ENC_PDDIS_EN_VA28_SFT 9

1401

#define RG_LCLDO_ENC_PDDIS_EN_VA28_MASK 0x1

1402

#define RG_LCLDO_ENC_PDDIS_EN_VA28_MASK_SFT (0x1 << 9)

1403

#define RG_LCLDO_ENC_REMOTE_SENSE_VA28_SFT 10

1404

#define RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK 0x1

1405

#define RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK_SFT (0x1 << 10)

1406

#define RG_VA33REFGEN_EN_VA18_SFT 12

1407

#define RG_VA33REFGEN_EN_VA18_MASK 0x1

1408

#define RG_VA33REFGEN_EN_VA18_MASK_SFT (0x1 << 12)

1409

#define RG_VA28REFGEN_EN_VA28_SFT 13

1410

#define RG_VA28REFGEN_EN_VA28_MASK 0x1

1411

#define RG_VA28REFGEN_EN_VA28_MASK_SFT (0x1 << 13)

1412

#define RG_HCLDO_VOSEL_VA18_SFT 14

1413

#define RG_HCLDO_VOSEL_VA18_MASK 0x1

1414

#define RG_HCLDO_VOSEL_VA18_MASK_SFT (0x1 << 14)

1415

#define RG_LCLDO_VOSEL_VA18_SFT 15

1416

#define RG_LCLDO_VOSEL_VA18_MASK 0x1

1417

#define RG_LCLDO_VOSEL_VA18_MASK_SFT (0x1 << 15)

1418

1419

/* AUDDEC_ANA_CON13 */

1420

#define RG_NVREG_EN_VAUDP15_SFT 0

1421

#define RG_NVREG_EN_VAUDP15_MASK 0x1

1422

#define RG_NVREG_EN_VAUDP15_MASK_SFT (0x1 << 0)

1423

#define RG_NVREG_PULL0V_VAUDP15_SFT 1

1424

#define RG_NVREG_PULL0V_VAUDP15_MASK 0x1

1425

#define RG_NVREG_PULL0V_VAUDP15_MASK_SFT (0x1 << 1)

1426

#define RG_AUDPMU_RSD0_VAUDP15_SFT 4

1427

#define RG_AUDPMU_RSD0_VAUDP15_MASK 0xf

1428

#define RG_AUDPMU_RSD0_VAUDP15_MASK_SFT (0xf << 4)

1429

#define RG_AUDPMU_RSD0_VA18_SFT 8

1430

#define RG_AUDPMU_RSD0_VA18_MASK 0xf

1431

#define RG_AUDPMU_RSD0_VA18_MASK_SFT (0xf << 8)

1432

#define RG_AUDPMU_RSD0_VA28_SFT 12

1433

#define RG_AUDPMU_RSD0_VA28_MASK 0xf

1434

#define RG_AUDPMU_RSD0_VA28_MASK_SFT (0xf << 12)

1435

1436

/* AUDDEC_ELR_NUM */

1437

#define AUDDEC_ELR_LEN_SFT 0

1438

#define AUDDEC_ELR_LEN_MASK 0xff

1439

#define AUDDEC_ELR_LEN_MASK_SFT (0xff << 0)

1440

1441

/* AUDDEC_ELR_0 */

1442

#define RG_AUDHSTRIM_VAUDP15_SFT 0

1443

#define RG_AUDHSTRIM_VAUDP15_MASK 0xf

1444

#define RG_AUDHSTRIM_VAUDP15_MASK_SFT (0xf << 0)

1445

#define RG_AUDHSFINETRIM_VAUDP15_SFT 4

1446

#define RG_AUDHSFINETRIM_VAUDP15_MASK 0x3

1447

#define RG_AUDHSFINETRIM_VAUDP15_MASK_SFT (0x3 << 4)

1448

#define RG_AUDHSTRIM_EN_VAUDP15_SFT 6

1449

#define RG_AUDHSTRIM_EN_VAUDP15_MASK 0x1

1450

#define RG_AUDHSTRIM_EN_VAUDP15_MASK_SFT (0x1 << 6)

1451

#define RG_AUDLOLTRIM_VAUDP15_SFT 7

1452

#define RG_AUDLOLTRIM_VAUDP15_MASK 0xf

1453

#define RG_AUDLOLTRIM_VAUDP15_MASK_SFT (0xf << 7)

1454

#define RG_AUDLOLFINETRIM_VAUDP15_SFT 11

1455

#define RG_AUDLOLFINETRIM_VAUDP15_MASK 0x3

1456

#define RG_AUDLOLFINETRIM_VAUDP15_MASK_SFT (0x3 << 11)

1457

#define RG_AUDLOLTRIM_EN_VAUDP15_SFT 13

1458

#define RG_AUDLOLTRIM_EN_VAUDP15_MASK 0x1

1459

#define RG_AUDLOLTRIM_EN_VAUDP15_MASK_SFT (0x1 << 13)

1460

1461

/* AUDZCD_DSN_ID */

1462

#define AUDZCD_ANA_ID_SFT 0

1463

#define AUDZCD_ANA_ID_MASK 0xff

1464

#define AUDZCD_ANA_ID_MASK_SFT (0xff << 0)

1465

#define AUDZCD_DIG_ID_SFT 8

1466

#define AUDZCD_DIG_ID_MASK 0xff

1467

#define AUDZCD_DIG_ID_MASK_SFT (0xff << 8)

1468

1469

/* AUDZCD_DSN_REV0 */

1470

#define AUDZCD_ANA_MINOR_REV_SFT 0

1471

#define AUDZCD_ANA_MINOR_REV_MASK 0xf

1472

#define AUDZCD_ANA_MINOR_REV_MASK_SFT (0xf << 0)

1473

#define AUDZCD_ANA_MAJOR_REV_SFT 4

1474

#define AUDZCD_ANA_MAJOR_REV_MASK 0xf

1475

#define AUDZCD_ANA_MAJOR_REV_MASK_SFT (0xf << 4)

1476

#define AUDZCD_DIG_MINOR_REV_SFT 8

1477

#define AUDZCD_DIG_MINOR_REV_MASK 0xf

1478

#define AUDZCD_DIG_MINOR_REV_MASK_SFT (0xf << 8)

1479

#define AUDZCD_DIG_MAJOR_REV_SFT 12

1480

#define AUDZCD_DIG_MAJOR_REV_MASK 0xf

1481

#define AUDZCD_DIG_MAJOR_REV_MASK_SFT (0xf << 12)

1482

1483

/* AUDZCD_DSN_DBI */

1484

#define AUDZCD_DSN_CBS_SFT 0

1485

#define AUDZCD_DSN_CBS_MASK 0x3

1486

#define AUDZCD_DSN_CBS_MASK_SFT (0x3 << 0)

1487

#define AUDZCD_DSN_BIX_SFT 2

1488

#define AUDZCD_DSN_BIX_MASK 0x3

1489

#define AUDZCD_DSN_BIX_MASK_SFT (0x3 << 2)

1490

#define AUDZCD_DSN_ESP_SFT 8

1491

#define AUDZCD_DSN_ESP_MASK 0xff

1492

#define AUDZCD_DSN_ESP_MASK_SFT (0xff << 8)

1493

1494

/* AUDZCD_DSN_FPI */

1495

#define AUDZCD_DSN_FPI_SFT 0

1496

#define AUDZCD_DSN_FPI_MASK 0xff

1497

#define AUDZCD_DSN_FPI_MASK_SFT (0xff << 0)

1498

1499

/* ZCD_CON0 */

1500

#define RG_AUDZCDENABLE_SFT 0

1501

#define RG_AUDZCDENABLE_MASK 0x1

1502

#define RG_AUDZCDENABLE_MASK_SFT (0x1 << 0)

1503

#define RG_AUDZCDGAINSTEPTIME_SFT 1

1504

#define RG_AUDZCDGAINSTEPTIME_MASK 0x7

1505

#define RG_AUDZCDGAINSTEPTIME_MASK_SFT (0x7 << 1)

1506

#define RG_AUDZCDGAINSTEPSIZE_SFT 4

1507

#define RG_AUDZCDGAINSTEPSIZE_MASK 0x3

1508

#define RG_AUDZCDGAINSTEPSIZE_MASK_SFT (0x3 << 4)

1509

#define RG_AUDZCDTIMEOUTMODESEL_SFT 6

1510

#define RG_AUDZCDTIMEOUTMODESEL_MASK 0x1

1511

#define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT (0x1 << 6)

1512

1513

/* ZCD_CON1 */

1514

#define RG_AUDLOLGAIN_SFT 0

1515

#define RG_AUDLOLGAIN_MASK 0x1f

1516

#define RG_AUDLOLGAIN_MASK_SFT (0x1f << 0)

1517

#define RG_AUDLORGAIN_SFT 7

1518

#define RG_AUDLORGAIN_MASK 0x1f

1519

#define RG_AUDLORGAIN_MASK_SFT (0x1f << 7)

1520

1521

/* ZCD_CON2 */

1522

#define RG_AUDHPLGAIN_SFT 0

1523

#define RG_AUDHPLGAIN_MASK 0x1f

1524

#define RG_AUDHPLGAIN_MASK_SFT (0x1f << 0)

1525

#define RG_AUDHPRGAIN_SFT 7

1526

#define RG_AUDHPRGAIN_MASK 0x1f

1527

#define RG_AUDHPRGAIN_MASK_SFT (0x1f << 7)

1528

1529

/* ZCD_CON3 */

1530

#define RG_AUDHSGAIN_SFT 0

1531

#define RG_AUDHSGAIN_MASK 0x1f

1532

#define RG_AUDHSGAIN_MASK_SFT (0x1f << 0)

1533

1534

/* ZCD_CON4 */

1535

#define RG_AUDIVLGAIN_SFT 0

1536

#define RG_AUDIVLGAIN_MASK 0x7

1537

#define RG_AUDIVLGAIN_MASK_SFT (0x7 << 0)

1538

#define RG_AUDIVRGAIN_SFT 8

1539

#define RG_AUDIVRGAIN_MASK 0x7

1540

#define RG_AUDIVRGAIN_MASK_SFT (0x7 << 8)

1541

1542

/* ZCD_CON5 */

1543

#define RG_AUDINTGAIN1_SFT 0

1544

#define RG_AUDINTGAIN1_MASK 0x3f

1545

#define RG_AUDINTGAIN1_MASK_SFT (0x3f << 0)

1546

#define RG_AUDINTGAIN2_SFT 8

1547

#define RG_AUDINTGAIN2_MASK 0x3f

1548

#define RG_AUDINTGAIN2_MASK_SFT (0x3f << 8)

1549

1550

/* audio register */

1551

#define MT6389_DRV_CON3 0x3c

1552

#define MT6389_GPIO_DIR0 0x88

1553

1554

#define MT6389_GPIO_MODE2 0xd8 /* mosi */

1555

#define MT6389_GPIO_MODE2_SET 0xda

1556

#define MT6389_GPIO_MODE2_CLR 0xdc

1557

1558

#define MT6389_GPIO_MODE3 0xde /* miso */

1559

#define MT6389_GPIO_MODE3_SET 0xe0

1560

#define MT6389_GPIO_MODE3_CLR 0xe2

1561

1562

#define MT6389_DCXO_CW12 0x7a8

1563

1564

#define MT6389_AUXADC_CON10 0x11a0

1565

#define MT6389_SMT_CON1 0x32

1566

#define MT6389_LDO_VAUD28_CON0 0x1dbe

1567

1568

/* audio register */

1569

#define MT6389_AUD_TOP_ID 0x2480

1570

#define MT6389_AUD_TOP_REV0 0x2482

1571

#define MT6389_AUD_TOP_DBI 0x2484

1572

#define MT6389_AUD_TOP_DXI 0x2486

1573

#define MT6389_AUD_TOP_CKPDN_TPM0 0x2488

1574

#define MT6389_AUD_TOP_CKPDN_TPM1 0x248a

1575

#define MT6389_AUD_TOP_CKPDN_CON0 0x248c

1576

#define MT6389_AUD_TOP_CKPDN_CON0_SET 0x248e

1577

#define MT6389_AUD_TOP_CKPDN_CON0_CLR 0x2490

1578

#define MT6389_AUD_TOP_CKSEL_CON0 0x2492

1579

#define MT6389_AUD_TOP_CKSEL_CON0_SET 0x2494

1580

#define MT6389_AUD_TOP_CKSEL_CON0_CLR 0x2496

1581

#define MT6389_AUD_TOP_CKTST_CON0 0x2498

1582

#define MT6389_AUD_TOP_CLK_HWEN_CON0 0x249a

1583

#define MT6389_AUD_TOP_CLK_HWEN_CON0_SET 0x249c

1584

#define MT6389_AUD_TOP_CLK_HWEN_CON0_CLR 0x249e

1585

#define MT6389_AUD_TOP_RST_CON0 0x24a0

1586

#define MT6389_AUD_TOP_RST_CON0_SET 0x24a2

1587

#define MT6389_AUD_TOP_RST_CON0_CLR 0x24a4

1588

#define MT6389_AUD_TOP_RST_BANK_CON0 0x24a6

1589

#define MT6389_AUD_TOP_INT_CON0 0x24a8

1590

#define MT6389_AUD_TOP_INT_CON0_SET 0x24aa

1591

#define MT6389_AUD_TOP_INT_CON0_CLR 0x24ac

1592

#define MT6389_AUD_TOP_INT_MASK_CON0 0x24ae

1593

#define MT6389_AUD_TOP_INT_MASK_CON0_SET 0x24b0

1594

#define MT6389_AUD_TOP_INT_MASK_CON0_CLR 0x24b2

1595

#define MT6389_AUD_TOP_INT_STATUS0 0x24b4

1596

#define MT6389_AUD_TOP_INT_RAW_STATUS0 0x24b6

1597

#define MT6389_AUD_TOP_INT_MISC_CON0 0x24b8

1598

#define MT6389_AUDNCP_CLKDIV_CON0 0x24ba

1599

#define MT6389_AUDNCP_CLKDIV_CON1 0x24bc

1600

#define MT6389_AUDNCP_CLKDIV_CON2 0x24be

1601

#define MT6389_AUDNCP_CLKDIV_CON3 0x24c0

1602

#define MT6389_AUDNCP_CLKDIV_CON4 0x24c2

1603

#define MT6389_AUD_TOP_MON_CON0 0x24c4

1604

#define MT6389_AUDIO_DIG_DSN_ID 0x2500

1605

#define MT6389_AUDIO_DIG_DSN_REV0 0x2502

1606

#define MT6389_AUDIO_DIG_DSN_DBI 0x2504

1607

#define MT6389_AUDIO_DIG_DSN_DXI 0x2506

1608

#define MT6389_AFE_UL_DL_CON0 0x2508

1609

#define MT6389_AFE_DL_SRC2_CON0_L 0x250a

1610

#define MT6389_AFE_UL_SRC_CON0_H 0x250c

1611

#define MT6389_AFE_UL_SRC_CON0_L 0x250e

1612

#define MT6389_AFE_TOP_CON0 0x2510

1613

#define MT6389_AUDIO_TOP_CON0 0x2512

1614

#define MT6389_AFE_MON_DEBUG0 0x2514

1615

#define MT6389_AFUNC_AUD_CON0 0x2516

1616

#define MT6389_AFUNC_AUD_CON1 0x2518

1617

#define MT6389_AFUNC_AUD_CON2 0x251a

1618

#define MT6389_AFUNC_AUD_CON3 0x251c

1619

#define MT6389_AFUNC_AUD_CON4 0x251e

1620

#define MT6389_AFUNC_AUD_CON5 0x2520

1621

#define MT6389_AFUNC_AUD_CON6 0x2522

1622

#define MT6389_AFUNC_AUD_MON0 0x2524

1623

#define MT6389_AUDRC_TUNE_MON0 0x2526

1624

#define MT6389_AFE_ADDA_MTKAIF_FIFO_CFG0 0x2528

1625

#define MT6389_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 0x252a

1626

#define MT6389_AFE_ADDA_MTKAIF_MON0 0x252c

1627

#define MT6389_AFE_ADDA_MTKAIF_MON1 0x252e

1628

#define MT6389_AFE_ADDA_MTKAIF_MON2 0x2530

1629

#define MT6389_AFE_ADDA_MTKAIF_MON3 0x2532

1630

#define MT6389_AFE_ADDA_MTKAIF_CFG0 0x2534

1631

#define MT6389_AFE_ADDA_MTKAIF_RX_CFG0 0x2536

1632

#define MT6389_AFE_ADDA_MTKAIF_RX_CFG1 0x2538

1633

#define MT6389_AFE_ADDA_MTKAIF_RX_CFG2 0x253a

1634

#define MT6389_AFE_ADDA_MTKAIF_RX_CFG3 0x253c

1635

#define MT6389_AFE_ADDA_MTKAIF_TX_CFG1 0x253e

1636

#define MT6389_AFE_SGEN_CFG0 0x2540

1637

#define MT6389_AFE_SGEN_CFG1 0x2542

1638

#define MT6389_AFE_ADC_ASYNC_FIFO_CFG 0x2544

1639

#define MT6389_AFE_DCCLK_CFG0 0x2546

1640

#define MT6389_AFE_DCCLK_CFG1 0x2548

1641

#define MT6389_AUDIO_DIG_CFG 0x254a

1642

#define MT6389_AFE_AUD_PAD_TOP 0x254c

1643

#define MT6389_AFE_AUD_PAD_TOP_MON 0x254e

1644

#define MT6389_AFE_AUD_PAD_TOP_MON1 0x2550

1645

#define MT6389_AFE_CG_EN_MON 0x2552

1646

#define MT6389_AUDENC_DSN_ID 0x2580

1647

#define MT6389_AUDENC_DSN_REV0 0x2582

1648

#define MT6389_AUDENC_DSN_DBI 0x2584

1649

#define MT6389_AUDENC_DSN_FPI 0x2586

1650

#define MT6389_AUDENC_ANA_CON0 0x2588

1651

#define MT6389_AUDENC_ANA_CON1 0x258a

1652

#define MT6389_AUDENC_ANA_CON2 0x258c

1653

#define MT6389_AUDENC_ANA_CON3 0x258e

1654

#define MT6389_AUDENC_ANA_CON4 0x2590

1655

#define MT6389_AUDENC_ANA_CON5 0x2592

1656

#define MT6389_AUDENC_ANA_CON6 0x2594

1657

#define MT6389_AUDENC_ANA_CON7 0x2596

1658

#define MT6389_AUDENC_ANA_CON8 0x2598

1659

#define MT6389_AUDENC_ANA_CON9 0x259a

1660

#define MT6389_AUDENC_ANA_CON10 0x259c

1661

#define MT6389_AUDENC_ANA_CON11 0x259e

1662

#define MT6389_AUDENC_ANA_CON12 0x25a0

1663

#define MT6389_AUDDEC_DSN_ID 0x2600

1664

#define MT6389_AUDDEC_DSN_REV0 0x2602

1665

#define MT6389_AUDDEC_DSN_DBI 0x2604

1666

#define MT6389_AUDDEC_DSN_FPI 0x2606

1667

#define MT6389_AUDDEC_ANA_CON0 0x2608

1668

#define MT6389_AUDDEC_ANA_CON1 0x260a

1669

#define MT6389_AUDDEC_ANA_CON2 0x260c

1670

#define MT6389_AUDDEC_ANA_CON3 0x260e

1671

#define MT6389_AUDDEC_ANA_CON4 0x2610

1672

#define MT6389_AUDDEC_ANA_CON5 0x2612

1673

#define MT6389_AUDDEC_ANA_CON6 0x2614

1674

#define MT6389_AUDDEC_ANA_CON7 0x2616

1675

#define MT6389_AUDDEC_ANA_CON8 0x2618

1676

#define MT6389_AUDDEC_ANA_CON9 0x261a

1677

#define MT6389_AUDDEC_ANA_CON10 0x261c

1678

#define MT6389_AUDDEC_ANA_CON11 0x261e

1679

#define MT6389_AUDDEC_ANA_CON12 0x2620

1680

#define MT6389_AUDDEC_ANA_CON13 0x2622

1681

#define MT6389_AUDDEC_ELR_NUM 0x2624

1682

#define MT6389_AUDDEC_ELR_0 0x2626

1683

#define MT6389_AUDZCD_DSN_ID 0x2680

1684

#define MT6389_AUDZCD_DSN_REV0 0x2682

1685

#define MT6389_AUDZCD_DSN_DBI 0x2684

1686

#define MT6389_AUDZCD_DSN_FPI 0x2686

1687

#define MT6389_ZCD_CON0 0x2688

1688

#define MT6389_ZCD_CON1 0x268a

1689

#define MT6389_ZCD_CON2 0x268c

1690

#define MT6389_ZCD_CON3 0x268e

1691

#define MT6389_ZCD_CON4 0x2690

1692

#define MT6389_ZCD_CON5 0x2692

1693

1694

#define MT6389_MAX_REGISTER MT6389_ZCD_CON5

1695

1696

enum {

1697

MT6389_MTKAIF_PROTOCOL_1 = 0,

1698

MT6389_MTKAIF_PROTOCOL_2,

1699

MT6389_MTKAIF_PROTOCOL_2_CLK_P2,

1700

};

1701

1702

/* set only during init */

1703

struct mt6389_codec_ops {

1704

int (*enable_dc_compensation)(bool enable);

1705

int (*set_lch_dc_compensation)(int value);

1706

int (*set_rch_dc_compensation)(int value);

1707

int (*adda_dl_gain_control)(bool mute);

1708

};

1709

1710

int mt6389_set_codec_ops(struct snd_soc_component *cmpnt,

1711

struct mt6389_codec_ops *ops);

1712

int mt6389_set_mtkaif_protocol(struct snd_soc_component *cmpnt,

1713

int mtkaif_protocol);

1714

int mt6389_mtkaif_calibration_enable(struct snd_soc_component *cmpnt);

1715

int mt6389_mtkaif_calibration_disable(struct snd_soc_component *cmpnt);

1716

int mt6389_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,

1717

int phase_1, int phase_2);

1718

1719

#endif /* __MT6389_H__ */

1720