| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame] | 1 | /* |
| 2 | * R-Car Gen3 Clock Pulse Generator |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Glider bvba |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ |
| 12 | #define __CLK_RENESAS_RCAR_GEN3_CPG_H__ |
| 13 | |
| 14 | enum rcar_gen3_clk_types { |
| 15 | CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, |
| 16 | CLK_TYPE_GEN3_PLL0, |
| 17 | CLK_TYPE_GEN3_PLL1, |
| 18 | CLK_TYPE_GEN3_PLL2, |
| 19 | CLK_TYPE_GEN3_PLL3, |
| 20 | CLK_TYPE_GEN3_PLL4, |
| 21 | CLK_TYPE_GEN3_SD, |
| 22 | CLK_TYPE_GEN3_R, |
| 23 | CLK_TYPE_GEN3_PE, |
| 24 | }; |
| 25 | |
| 26 | #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ |
| 27 | DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) |
| 28 | |
| 29 | #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ |
| 30 | _div_clean) \ |
| 31 | DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \ |
| 32 | (_parent_sscg) << 16 | (_parent_clean), \ |
| 33 | .div = (_div_sscg) << 16 | (_div_clean)) |
| 34 | |
| 35 | struct rcar_gen3_cpg_pll_config { |
| 36 | u8 extal_div; |
| 37 | u8 pll1_mult; |
| 38 | u8 pll1_div; |
| 39 | u8 pll3_mult; |
| 40 | u8 pll3_div; |
| 41 | }; |
| 42 | |
| 43 | #define CPG_RCKCR 0x240 |
| 44 | |
| 45 | struct clk *rcar_gen3_cpg_clk_register(struct device *dev, |
| 46 | const struct cpg_core_clk *core, const struct cpg_mssr_info *info, |
| 47 | struct clk **clks, void __iomem *base); |
| 48 | int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, |
| 49 | unsigned int clk_extalr, u32 mode); |
| 50 | |
| 51 | #endif |