| /* |
| *********************************************************** |
| */ |
| |
| #ifndef __EFUSE_H__ |
| #define __EFUSE_H__ |
| |
| |
| /* -------- efuse ¼Ä´æÆ÷-------------*/ |
| #define SYS_EFUSE_BASE 0x0121b000 |
| #define EFUSE_RAM_BASE (SYS_EFUSE_BASE+0x40) |
| |
| #define SYS_CTRL_BASE 0x00140000 |
| #define EFUSE_BYPASS (SYS_CTRL_BASE+0x140) |
| |
| |
| #define CHIP_DDR_32M 0 |
| #define CHIP_DDR_64M 1 |
| #define CHIP_DDR_128M 2 |
| #define CHIP_DDR_256M 3 |
| #define CHIP_DDR_512M 4 |
| |
| |
| #define SECURE_VERIFY_ENABLE 0 |
| #define SECURE_VERIFY_DISABLE 1 |
| |
| #define ZX297520V3_GW_NYB_1G_DDR 0xF86302 |
| #define ZX297520V3_GW_NYC_1G_DDR 0xF86303 |
| #define ZX297520V3ECO_GW_UNILC_512M_DDR 0xF86304 |
| #define ZX297520V3ECO_GW_APM_512M_DDR 0xF86305 |
| #define ZX297520V3ECO_GW_NYB_1G_DDR 0xF86306 |
| #define ZX297520V3ECO_GW_NYC_1G_DDR 0xF86307 |
| #define ZX297520V3ECO_GW_WINBD_256M_DDR 0xF86308 |
| #define ZX297520V3ECO_GW_UNILC_256M_DDR 0xF86309 |
| #define ZX297520V3ECO_GW_APM_256M_DDR 0xF8630a |
| #define ZX297520V3ECO_GW_ESMT_512M_DDR 0xF8630b |
| #define ZX297520V3SC_GW_NYC_1G_DDR 0xF8630c |
| #define ZX297520V3ECOSCC_GW_UNILC_1G_DDR 0xF8630d |
| #define ZX297520V3ECOSCC_GW_NYC_1G_DDR 0xF8630e |
| #define ZX297520V3ECOSC_GW_NYC_1G_DDR 0xF8630f |
| #define ZX297520V3ECOSC_GW_UNILC_1G_DDR 0xF86310 |
| #define ZX297520V3ECOSC_GW_NYC_2G_DDR 0xF86311 |
| #define ZX297520V3ECOSCC_GW_NYB_4G_DDR 0xF86313 |
| #define ZX297520V3ECOGG_GW_NYC_2G_DDR 0xF86314 |
| #define ZX297520V3ECOGG_GW_NYB_4G_DDR 0xF86315 |
| #define ZX297520V3ECOGG_GW_NYC_NOR_2G_DDR 0xF86316 |
| #define ZX297520V3ECOSC_GW_NYC_NOR_2G_DDR 0xF86317 |
| |
| #define ZX297520V3_ZW_NYB_1G_DDR 0x1E871E |
| #define ZX297520V3_ZW_NYC_1G_DDR 0x1E871F |
| #define ZX297520V3ECO_ZW_UNILC_512M_DDR 0x1E8720 |
| #define ZX297520V3ECO_ZW_APM_512M_DDR 0x1E8721 |
| #define ZX297520V3ECO_ZW_NYB_1G_DDR 0x1E8722 |
| #define ZX297520V3ECO_ZW_NYC_1G_DDR 0x1E8723 |
| #define ZX297520V3ECO_ZW_WINBD_256M_DDR 0x1E8724 |
| #define ZX297520V3ECO_ZW_UNILC_256M_DDR 0x1E8725 |
| #define ZX297520V3ECO_ZW_APM_256M_DDR 0x1E8726 |
| #define ZX297520V3ECO_ZW_ESMT_512M_DDR 0x1E8727 |
| |
| #define ZX297520V3ECO_AZW_UNILC_512M_DDR 0x1F9801 |
| |
| |
| /*ΪÁË¿´ÆðÀ´·½±ã, hashºÍkeyÔÚbufferµÄ´æ·Å˳ÐòΪµÍµØÖ··Å¸ßλÊý¾Ý*/ |
| // ¶¨Òå½á¹¹ |
| typedef volatile struct |
| { |
| u32 secure_flag; |
| u32 puk_hash[4]; |
| } efuse_struct; |
| |
| |
| |
| void efuse_init(void); |
| int get_ddr_flag(void); |
| int get_secure_verify_status(void); |
| |
| |
| #endif /* __EFUSE_H__ */ |