[Feature][ZXW-96]uart 1and2 supports the maximum baudrate of 4M
Only Configure:No;
Affected branch:master;
Affected module:Uart;
Is it affected on both ZXIC and MTK: only ZXIC;
Self-test: Yes;
Doc Update:No
Change-Id: I48aacbadd9f69aa0f562bee515e91e8ed0999fdb
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/arch/arm/boot/dts/zx297520v3.dtsi b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/arch/arm/boot/dts/zx297520v3.dtsi
index 3a19b4f..94587cb 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/arch/arm/boot/dts/zx297520v3.dtsi
+++ b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/arch/arm/boot/dts/zx297520v3.dtsi
@@ -351,6 +351,9 @@
<GIC_SPI UART0_RXD_INT IRQ_TYPE_EDGE_FALLING>;
clocks = <&clkc UART0_WCLK>, <&clkc UART0_PCLK>;
clock-names = "uartclk", "apb_pclk";
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start*/
+ uart-max-bus-freq = <104000000>;
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end*/
status = "disabled";
};
@@ -372,6 +375,9 @@
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "uart2_tx_rx";
pinctrl-0 = <&uart2_pins>;
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start*/
+ uart-max-bus-freq = <104000000>;
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end*/
status = "disabled";
};
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/tty/serial/zx29_uart.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/tty/serial/zx29_uart.c
index f199d9c..26f5d98 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/tty/serial/zx29_uart.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/tty/serial/zx29_uart.c
@@ -3235,7 +3235,9 @@
unsigned int offset=(unsigned int)(pdev->id);
struct device_node *np = pdev->dev.of_node;
unsigned int baud, ibrd, fbrd;
-
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start*/
+ unsigned int max_bus_clk;
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end*/
struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
//struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -3259,6 +3261,12 @@
printk("failed to get zx29_port->wclk: %d\n", ret);
return ret;
}
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start*/
+ if(0 == pdev->id || 2 == pdev->id){
+ device_property_read_u32(&pdev->dev, "uart-max-bus-freq", &max_bus_clk);
+ clk_set_rate(zx29_port->wclk, max_bus_clk);
+ }
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end*/
if(offset == 0){
clk_set_rate(zx29_port->wclk, 104 * 1000000);
}
@@ -3288,6 +3296,11 @@
//here is temple def
if(port->uartclk == 0){
printk("---zx29_init_ports, uartclk hard set to 26M\n");
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start*/
+ if(0 == pdev->id || 2 == pdev->id)
+ port->uartclk = 104000000;
+ else
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end*/
port->uartclk = 26000000;
}
printk("---zx29_init_ports, line:%d, irq:%d, membase:%08x, uartclk:%d\n", port->line, port->irq, port->membase, port->uartclk);