[Feature][ZXW-76]merged P48U04 base code
Change-Id: Ia14632a24eb4e8ddf720d8f53f2fe3a1b52a0a8e
diff --git a/allbins/zx297520v3/prj_evb/nv/Ref_nvrw_0x26C00.bin b/allbins/zx297520v3/prj_evb/nv/Ref_nvrw_0x26C00.bin
index e157198..1bd7d1f 100755
--- a/allbins/zx297520v3/prj_evb/nv/Ref_nvrw_0x26C00.bin
+++ b/allbins/zx297520v3/prj_evb/nv/Ref_nvrw_0x26C00.bin
Binary files differ
diff --git a/allbins/zx297520v3/prj_evb/nv/at_nvrw_0x00001000.bin b/allbins/zx297520v3/prj_evb/nv/at_nvrw_0x00001000.bin
index 7888edb..af80450 100755
--- a/allbins/zx297520v3/prj_evb/nv/at_nvrw_0x00001000.bin
+++ b/allbins/zx297520v3/prj_evb/nv/at_nvrw_0x00001000.bin
Binary files differ
diff --git "a/allbins/zx297520v3/prj_evb/nv/config/\345\236\213\345\217\267\346\234\272/AT\345\217\202\346\225\260\350\256\276\347\275\256.xml" "b/allbins/zx297520v3/prj_evb/nv/config/\345\236\213\345\217\267\346\234\272/AT\345\217\202\346\225\260\350\256\276\347\275\256.xml"
index 159851d..fc91aea 100755
--- "a/allbins/zx297520v3/prj_evb/nv/config/\345\236\213\345\217\267\346\234\272/AT\345\217\202\346\225\260\350\256\276\347\275\256.xml"
+++ "b/allbins/zx297520v3/prj_evb/nv/config/\345\236\213\345\217\267\346\234\272/AT\345\217\202\346\225\260\350\256\276\347\275\256.xml"
@@ -59,4 +59,12 @@
<NVPARAM name="Ñ°ºôÓÅÏÈ»¹ÊÇÁбíÓÅÏÈ" UIType="combobox" type="enum" select="PSÑ°ºôÓÅÏÈ:0;ÁбíÓÅÏÈ:1" value="" path="T_CommAtSetting.PsPageOrPlmnlistPrio" ParamDetail="" />
<NVPARAM name="¿ìËÙɨƵ¼ä¸ôʱ¼ä" UIType="text" type="number" value="0" minivalue="0" maxvalue="65535" path="T_CommAtSetting.wFastScanTime" ParamDetail="" />
<NVPARAM name="¿ìËÙɨƵ¹¦ÄÜ¿ª¹Ø" UIType="combobox" type="enum" select="¹Ø±Õ:0;´ò¿ª:1" value="" path="T_CommAtSetting.bFastScanFreqFg" ParamDetail="" />
+ <NVPARAM name="Ò»Èí¶àÓ²¹¦ÄÜ¿ª¹Ø" UIType="combobox" type="enum" select="¹Ø±Õ:0;´ò¿ª:1" value="" path="T_CommAtSetting.bMultiRfFlag" ParamDetail="" />
+ <NVPARAM name="Ò»Èí¶àÓ²¹¦ÄܵÄGPIO0" UIType="text" type="number" value="0" minivalue="0" maxvalue="255" path="T_CommAtSetting.bGpio0Val" ParamDetail="" />
+ <NVPARAM name="Ò»Èí¶àÓ²¹¦ÄܵÄGPIO1" UIType="text" type="number" value="0" minivalue="0" maxvalue="255" path="T_CommAtSetting.bGpio1Val" ParamDetail="" />
+ <NVPARAM name="Ò»Èí¶àÓ²¹¦ÄܵÄGPIO2" UIType="text" type="number" value="0" minivalue="0" maxvalue="255" path="T_CommAtSetting.bGpio2Val" ParamDetail="" />
+ <NVPARAM name="OOSÃÅÏÞÊÇ·ñÆôÓÃ" UIType="combobox" type="enum" select="¹Ø±Õ:0;´ò¿ª:1" value="" path="T_CommAtSetting.OosThreshFlg" ParamDetail="" />
+ <NVPARAM name="OOSÃÅÏÞÖµ" UIType="text" type="number" value="0" minivalue="0" maxvalue="60" path="T_CommAtSetting.OosThresh" ParamDetail="È¡Öµ·¶Î§0-60£¬ÆäÖÐ0¶ÔÓ¦-20db,1¶ÔÓ¦-19db£¬2¶ÔÓ¦-18db£¬ÒÔ´ËÀàÍÆ60¶ÔÓ¦40db" />
+ <NVPARAM name="¹ÂµºÃÅÏÞÊÇ·ñÆôÓÃ" UIType="combobox" type="enum" select="¹Ø±Õ:0;´ò¿ª:1" value="" path="T_CommAtSetting.IslandThreshFlg" ParamDetail="" />
+ <NVPARAM name="¹ÂµºÃÅÏÞÖµ" UIType="text" type="number" value="0" minivalue="0" maxvalue="60" path="T_CommAtSetting.IslandThresh" ParamDetail="È¡Öµ·¶Î§0-60£¬ÆäÖÐ0¶ÔÓ¦-20db,1¶ÔÓ¦-19db£¬2¶ÔÓ¦-18db£¬ÒÔ´ËÀàÍÆ60¶ÔÓ¦40db" />
</FUNCTION>
diff --git a/allbins/zx297520v3/prj_evb/nv/nv.xml b/allbins/zx297520v3/prj_evb/nv/nv.xml
index e47d53d..4a306ee 100755
--- a/allbins/zx297520v3/prj_evb/nv/nv.xml
+++ b/allbins/zx297520v3/prj_evb/nv/nv.xml
@@ -14146,7 +14146,7 @@
<child kind="BaseType" type="BYTE" />
</child>
</TypeDefine>
- <TypeDefine name="T_CommAtSetting" kind="struct" len="796">
+ <TypeDefine name="T_CommAtSetting" kind="struct" len="800">
<child offset="0" name="magic" kind="array" num="8">
<child kind="BaseType" type="char" />
</child>
@@ -14323,7 +14323,11 @@
<child offset="790" name="bFreqScanTmax" kind="BaseType" type="WORD" />
<child offset="792" name="wFastScanTime" kind="BaseType" type="WORD" />
<child offset="794" name="bFastScanFreqFg" kind="BaseType" type="BYTE" />
- <child offset="795" name="bSpare" kind="BaseType" type="BYTE" />
+ <child offset="795" name="bMultiRfFlag" kind="BaseType" type="BYTE" />
+ <child offset="796" name="bGpio0Val" kind="BaseType" type="BYTE" />
+ <child offset="797" name="bGpio1Val" kind="BaseType" type="BYTE" />
+ <child offset="798" name="bGpio2Val" kind="BaseType" type="BYTE" />
+ <child offset="799" name="bSpare" kind="BaseType" type="BYTE" />
</TypeDefine>
<TypeDefine name="tagMCI_ANIM_WINDOW_PARMSA" kind="struct" len="16">
<child offset="0" name="dwCallback" kind="BaseType" type="DWORD" />
diff --git a/allbins/zx297520v3/prj_evb/nv_230a/Ref_nvrw_0x26C00.bin b/allbins/zx297520v3/prj_evb/nv_230a/Ref_nvrw_0x26C00.bin
index 9844fc7..dc9d5e8 100755
--- a/allbins/zx297520v3/prj_evb/nv_230a/Ref_nvrw_0x26C00.bin
+++ b/allbins/zx297520v3/prj_evb/nv_230a/Ref_nvrw_0x26C00.bin
Binary files differ
diff --git a/allbins/zx297520v3/prj_evb/nv_230a/at_nvrw_0x00001000.bin b/allbins/zx297520v3/prj_evb/nv_230a/at_nvrw_0x00001000.bin
index 325694b..79573bd 100755
--- a/allbins/zx297520v3/prj_evb/nv_230a/at_nvrw_0x00001000.bin
+++ b/allbins/zx297520v3/prj_evb/nv_230a/at_nvrw_0x00001000.bin
Binary files differ
diff --git a/allbins/zx297520v3/prj_evb/nv_230a_dcxo/Ref_nvrw_0x26C00.bin b/allbins/zx297520v3/prj_evb/nv_230a_dcxo/Ref_nvrw_0x26C00.bin
index 9844fc7..dc9d5e8 100755
--- a/allbins/zx297520v3/prj_evb/nv_230a_dcxo/Ref_nvrw_0x26C00.bin
+++ b/allbins/zx297520v3/prj_evb/nv_230a_dcxo/Ref_nvrw_0x26C00.bin
Binary files differ
diff --git a/allbins/zx297520v3/prj_vehicle/config_dc_4Gb/partition.bin b/allbins/zx297520v3/prj_vehicle/config_dc_4Gb/partition.bin
index d0e84d3..f71683d 100755
--- a/allbins/zx297520v3/prj_vehicle/config_dc_4Gb/partition.bin
+++ b/allbins/zx297520v3/prj_vehicle/config_dc_4Gb/partition.bin
Binary files differ
diff --git a/allbins/zx297520v3/prj_vehicle/config_dc_4Gb/partition.ini b/allbins/zx297520v3/prj_vehicle/config_dc_4Gb/partition.ini
index a33c36a..6209e73 100755
--- a/allbins/zx297520v3/prj_vehicle/config_dc_4Gb/partition.ini
+++ b/allbins/zx297520v3/prj_vehicle/config_dc_4Gb/partition.ini
@@ -2,7 +2,7 @@
partition_magic=0x31594876
partition_platform=WF7520
partition_version=0x00201304
-partition_entrys=0x11
+partition_entrys=0x12
partition_crc=0x12345678
[Partition0]
@@ -63,45 +63,51 @@
partition_name=userdata
partition_type=nand
partition_addr=0x04900000
-partition_size=0x04000000
+partition_size=0x01000000
[Partition10]
partition_name=caprootfs
partition_type=nand
-partition_addr=0x08900000
+partition_addr=0x05900000
partition_size=0x02000000
[Partition11]
partition_name=caprootfs2
partition_type=nand
-partition_addr=0x0A900000
+partition_addr=0x07900000
partition_size=0x02000000
[Partition12]
partition_name=capuserdata
partition_type=nand
-partition_addr=0x0C900000
-partition_size=0x0D000000
+partition_addr=0x09900000
+partition_size=0x02800000
[Partition13]
partition_name=oem
partition_type=nand
-partition_addr=0x19900000
-partition_size=0x03200000
+partition_addr=0x0C100000
+partition_size=0x06400000
[Partition14]
partition_name=oem2
partition_type=nand
-partition_addr=0x1CB00000
-partition_size=0x03200000
+partition_addr=0x12500000
+partition_size=0x06400000
[Partition15]
+partition_name=oemdata
+partition_type=nand
+partition_addr=0x18900000
+partition_size=0x07400000
+
+[Partition16]
partition_name=ddr
partition_type=ddr
partition_addr=0x00000000
partition_size=0xFFFFFFFF
-[Partition16]
+[Partition17]
partition_name=raw
partition_type=raw
partition_addr=0x00000000
diff --git a/allbins/zx297520v3/prj_vehicle/nv/Ref_nvrw_0x26C00.bin b/allbins/zx297520v3/prj_vehicle/nv/Ref_nvrw_0x26C00.bin
index f741f2d..4dd4a04 100755
--- a/allbins/zx297520v3/prj_vehicle/nv/Ref_nvrw_0x26C00.bin
+++ b/allbins/zx297520v3/prj_vehicle/nv/Ref_nvrw_0x26C00.bin
Binary files differ
diff --git a/allbins/zx297520v3/prj_vehicle/nv/at_nvrw_0x00001000.bin b/allbins/zx297520v3/prj_vehicle/nv/at_nvrw_0x00001000.bin
index 325694b..56c0e59 100755
--- a/allbins/zx297520v3/prj_vehicle/nv/at_nvrw_0x00001000.bin
+++ b/allbins/zx297520v3/prj_vehicle/nv/at_nvrw_0x00001000.bin
Binary files differ
diff --git a/allbins/zx297520v3/prj_vehicle/nv_dc/Ref_nvrw_0x26C00.bin b/allbins/zx297520v3/prj_vehicle/nv_dc/Ref_nvrw_0x26C00.bin
index c3ad813..f65d7cf 100755
--- a/allbins/zx297520v3/prj_vehicle/nv_dc/Ref_nvrw_0x26C00.bin
+++ b/allbins/zx297520v3/prj_vehicle/nv_dc/Ref_nvrw_0x26C00.bin
Binary files differ
diff --git a/allbins/zx297520v3/prj_vehicle/nv_dc_4Gb/Ref_nvrw_0x26C00.bin b/allbins/zx297520v3/prj_vehicle/nv_dc_4Gb/Ref_nvrw_0x26C00.bin
index 87896dc..62b4bd8 100755
--- a/allbins/zx297520v3/prj_vehicle/nv_dc_4Gb/Ref_nvrw_0x26C00.bin
+++ b/allbins/zx297520v3/prj_vehicle/nv_dc_4Gb/Ref_nvrw_0x26C00.bin
Binary files differ
diff --git a/allbins/zx297520v3/prj_vehicle/scripts/AllInOneImage_dc_4Gb.ini b/allbins/zx297520v3/prj_vehicle/scripts/AllInOneImage_dc_4Gb.ini
index 1d0c5c6..6f62be8 100755
--- a/allbins/zx297520v3/prj_vehicle/scripts/AllInOneImage_dc_4Gb.ini
+++ b/allbins/zx297520v3/prj_vehicle/scripts/AllInOneImage_dc_4Gb.ini
@@ -24,6 +24,7 @@
..\allbins_dc_4Gb\ap_imagefs2.img
..\allbins_dc_4Gb\ap_userdata.img
..\allbins_dc_4Gb\ap_capuserdata.img
+..\allbins_dc_4Gb\cap_oemdata.img
..\allbins_dc_4Gb\ap_rootfs.img
..\allbins_dc_4Gb\ap_rootfs2.img
..\allbins_dc_4Gb\ap_caprootfs.img
diff --git a/allbins/zx297520v3/prj_vehicle/scripts/copy_a_to_b.bat b/allbins/zx297520v3/prj_vehicle/scripts/copy_a_to_b.bat
index 2745f80..572a566 100755
--- a/allbins/zx297520v3/prj_vehicle/scripts/copy_a_to_b.bat
+++ b/allbins/zx297520v3/prj_vehicle/scripts/copy_a_to_b.bat
@@ -8,14 +8,10 @@
set COPY_ALLBINDIR=%COPY_TOPDIR%\allbins\%COPY_CHIP_NAME%\%COPY_PRJ_NAME%\allbins
-set COPY_OTHERBINDIR=%COPY_TOPDIR%\allbins\%COPY_CHIP_NAME%\%COPY_PRJ_NAME%\elf
set COPY_ALLBINDCDIR=%COPY_TOPDIR%\allbins\%COPY_CHIP_NAME%\%COPY_PRJ_NAME%\allbins_dc
-set COPY_OTHERBINDCDIR=%COPY_TOPDIR%\allbins\%COPY_CHIP_NAME%\%COPY_PRJ_NAME%\elf_dc
set COPY_ALLBINDC4GbDIR=%COPY_TOPDIR%\allbins\%COPY_CHIP_NAME%\%COPY_PRJ_NAME%\allbins_dc_4Gb
-set COPY_OTHERBINDC4GbDIR=%COPY_TOPDIR%\allbins\%COPY_CHIP_NAME%\%COPY_PRJ_NAME%\elf_dc_4Gb
-
-
-
+set COPY_ALLBIN_DC_REF_DIR=%COPY_TOPDIR%\allbins\%COPY_CHIP_NAME%\%COPY_PRJ_NAME%\allbins_dc_ref
+set COPY_ALLBIN_DC_SYSTEMD_DIR=%COPY_TOPDIR%\allbins\%COPY_CHIP_NAME%\%COPY_PRJ_NAME%\allbins_dc_systemd
echo "Enter call copybin.bat!!!!"
@@ -36,6 +32,18 @@
call :CopyFile %COPY_ALLBINDC4GbDIR%\cap_oem.img %COPY_ALLBINDC4GbDIR%\cap_oem2.img
call :CopyFile %COPY_ALLBINDC4GbDIR%\uboot.bin %COPY_ALLBINDC4GbDIR%\uboot2.bin
+call :CopyFile %COPY_ALLBIN_DC_REF_DIR%\ap_imagefs.img %COPY_ALLBIN_DC_REF_DIR%\ap_imagefs2.img
+call :CopyFile %COPY_ALLBIN_DC_REF_DIR%\ap_rootfs.img %COPY_ALLBIN_DC_REF_DIR%\ap_rootfs2.img
+call :CopyFile %COPY_ALLBIN_DC_REF_DIR%\ap_caprootfs.img %COPY_ALLBIN_DC_REF_DIR%\ap_caprootfs2.img
+call :CopyFile %COPY_ALLBIN_DC_REF_DIR%\cap_oem.img %COPY_ALLBIN_DC_REF_DIR%\cap_oem2.img
+call :CopyFile %COPY_ALLBIN_DC_REF_DIR%\uboot.bin %COPY_ALLBIN_DC_REF_DIR%\uboot2.bin
+
+call :CopyFile %COPY_ALLBIN_DC_SYSTEMD_DIR%\ap_imagefs.img %COPY_ALLBIN_DC_SYSTEMD_DIR%\ap_imagefs2.img
+call :CopyFile %COPY_ALLBIN_DC_SYSTEMD_DIR%\ap_rootfs.img %COPY_ALLBIN_DC_SYSTEMD_DIR%\ap_rootfs2.img
+call :CopyFile %COPY_ALLBIN_DC_SYSTEMD_DIR%\ap_caprootfs.img %COPY_ALLBIN_DC_SYSTEMD_DIR%\ap_caprootfs2.img
+call :CopyFile %COPY_ALLBIN_DC_SYSTEMD_DIR%\cap_oem.img %COPY_ALLBIN_DC_SYSTEMD_DIR%\cap_oem2.img
+call :CopyFile %COPY_ALLBIN_DC_SYSTEMD_DIR%\uboot.bin %COPY_ALLBIN_DC_SYSTEMD_DIR%\uboot2.bin
+
goto :EOF
diff --git a/allbins/zx297520v3/prj_vehicle/scripts/merge.bat b/allbins/zx297520v3/prj_vehicle/scripts/merge.bat
index 403c3f8..4349a86 100755
--- a/allbins/zx297520v3/prj_vehicle/scripts/merge.bat
+++ b/allbins/zx297520v3/prj_vehicle/scripts/merge.bat
@@ -9,14 +9,22 @@
%HomeDir%\..\..\..\..\tools\Image\Image.exe -n NVRWOInOneImage_dc.ini
%HomeDir%\..\..\..\..\tools\Image\Image.exe -n NVRWInOneImage_dc_4Gb.ini
%HomeDir%\..\..\..\..\tools\Image\Image.exe -n NVRWOInOneImage_dc_4Gb.ini
+%HomeDir%\..\..\..\..\tools\Image\Image.exe -n NVRWInOneImage_dc_ref.ini
+%HomeDir%\..\..\..\..\tools\Image\Image.exe -n NVRWOInOneImage_dc_ref.ini
+%HomeDir%\..\..\..\..\tools\Image\Image.exe -n NVRWInOneImage_dc_systemd.ini
+%HomeDir%\..\..\..\..\tools\Image\Image.exe -n NVRWOInOneImage_dc_systemd.ini
%HomeDir%\..\..\..\..\tools\Image\Image.exe -f FsImage.ini
%HomeDir%\..\..\..\..\tools\Image\Image.exe -f FsImage_dc.ini
%HomeDir%\..\..\..\..\tools\Image\Image.exe -f FsImage_dc_4Gb.ini
+%HomeDir%\..\..\..\..\tools\Image\Image.exe -f FsImage_dc_ref.ini
+%HomeDir%\..\..\..\..\tools\Image\Image.exe -f FsImage_dc_systemd.ini
cd %HomeDir%
call copy_a_to_b.bat
%HomeDir%\..\..\..\..\tools\Image\Image.exe -m AllInOneImage.ini
%HomeDir%\..\..\..\..\tools\Image\Image.exe -m AllInOneImage_dc.ini
%HomeDir%\..\..\..\..\tools\Image\Image.exe -m AllInOneImage_dc_4Gb.ini
+%HomeDir%\..\..\..\..\tools\Image\Image.exe -m AllInOneImage_dc_ref.ini
+%HomeDir%\..\..\..\..\tools\Image\Image.exe -m AllInOneImage_dc_systemd.ini
diff --git a/allbins/zx297520v3/prj_vehicle/scripts_linux/AllInOneImage_dc_4Gb.ini b/allbins/zx297520v3/prj_vehicle/scripts_linux/AllInOneImage_dc_4Gb.ini
index 6645ffe..7d666b0 100755
--- a/allbins/zx297520v3/prj_vehicle/scripts_linux/AllInOneImage_dc_4Gb.ini
+++ b/allbins/zx297520v3/prj_vehicle/scripts_linux/AllInOneImage_dc_4Gb.ini
@@ -23,6 +23,7 @@
../allbins_dc_4Gb/ap_imagefs2.img
../allbins_dc_4Gb/ap_userdata.img
../allbins_dc_4Gb/ap_capuserdata.img
+../allbins_dc_4Gb/cap_oemdata.img
../allbins_dc_4Gb/ap_rootfs.img
../allbins_dc_4Gb/ap_rootfs2.img
../allbins_dc_4Gb/ap_caprootfs.img
diff --git a/allbins/zx297520v3/prj_vehicle/scripts_linux/copybin_a_to_b.sh b/allbins/zx297520v3/prj_vehicle/scripts_linux/copybin_a_to_b.sh
index 3f53b4f..697130b 100755
--- a/allbins/zx297520v3/prj_vehicle/scripts_linux/copybin_a_to_b.sh
+++ b/allbins/zx297520v3/prj_vehicle/scripts_linux/copybin_a_to_b.sh
@@ -8,21 +8,31 @@
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_imagefs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_imagefs2.img
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_imagefs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_imagefs2.img
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_imagefs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_imagefs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_imagefs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_imagefs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_imagefs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_imagefs2.img
#ap_rootfs.img
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_rootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_rootfs2.img
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_rootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_rootfs2.img
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_rootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_rootfs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_rootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_rootfs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_rootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_rootfs2.img
#ap_caprootfs
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_caprootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_caprootfs2.img
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_caprootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_caprootfs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_caprootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_caprootfs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_caprootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_caprootfs2.img
#uboot
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins/uboot.bin $TOP_DIR/zx297520v3/prj_vehicle/allbins/uboot2.bin
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/uboot.bin $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/uboot2.bin
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/uboot.bin $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/uboot2.bin
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/uboot.bin $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/uboot2.bin
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/uboot.bin $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/uboot2.bin
#oem
cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_oem.img $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_oem2.img
-cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/cap_oem.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/cap_oem2.img
\ No newline at end of file
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/cap_oem.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/cap_oem2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/cap_oem.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/cap_oem2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/cap_oem.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/cap_oem2.img
\ No newline at end of file
diff --git a/allbins/zx297520v3/prj_vehicle/scripts_linux/merge.sh b/allbins/zx297520v3/prj_vehicle/scripts_linux/merge.sh
index 1b589b4..fd50615 100755
--- a/allbins/zx297520v3/prj_vehicle/scripts_linux/merge.sh
+++ b/allbins/zx297520v3/prj_vehicle/scripts_linux/merge.sh
@@ -6,12 +6,20 @@
./Image -n NVRWOInOneImage_dc.ini
./Image -n NVRWInOneImage_dc_4Gb.ini
./Image -n NVRWOInOneImage_dc_4Gb.ini
+./Image -n NVRWInOneImage_dc_ref.ini
+./Image -n NVRWOInOneImage_dc_ref.ini
+./Image -n NVRWInOneImage_dc_systemd.ini
+./Image -n NVRWOInOneImage_dc_systemd.ini
./Image -f FsImage.ini
./Image -f FsImage_dc.ini
./Image -f FsImage_dc_4Gb.ini
+./Image -f FsImage_dc_ref.ini
+./Image -f FsImage_dc_systemd.ini
bash copybin_a_to_b.sh
./Image -m AllInOneImage.ini
./Image -m AllInOneImage_dc.ini
./Image -m AllInOneImage_dc_4Gb.ini
+./Image -m AllInOneImage_dc_ref.ini
+./Image -m AllInOneImage_dc_systemd.ini
diff --git a/ap/app/Script/scripts/internet.sh b/ap/app/Script/scripts/internet.sh
index b9ff044..95a56b4 100755
--- a/ap/app/Script/scripts/internet.sh
+++ b/ap/app/Script/scripts/internet.sh
@@ -9,6 +9,13 @@
echo "Info: internet.sh start" > $test_log
echo "Info: `date +%m-%d %H:%M:%S`" >> $test_log
+#CONFIG_BRIDGE_IGMP_SNOOPING¿ª¹Ø
+br_multi_off=`nv get br_multi_off`
+echo "Info: set br_multi_off: $br_multi_off" >> $test_log
+if [ "-$br_multi_off" == "-1" ]; then
+ echo 1 > /proc/net/br_multi_off
+fi
+
genSysFiles()
{
login=`nv get Login`
@@ -88,17 +95,17 @@
#½«¿ìËÙת·¢¼¶±ð´«¸øÄÚºË
fastnat_level=`nv get fastnat_level`
-echo "Info: set fastnat_level£º$fastnat_level" >> $test_log
+echo "Info: set fastnat_level: $fastnat_level" >> $test_log
echo $fastnat_level > /proc/net/fastnat_level
#½«²»Ö§³Ö¿ìËÙת·¢µÄÐÒé¶Ë¿ÚºÅ´«¸øÄÚºË
nofast_port=`nv get nofast_port`
-echo "Info: set nofast_port£º$nofast_port" >> $test_log
+echo "Info: set nofast_port: $nofast_port" >> $test_log
echo $nofast_port > /proc/net/nofast_port
#SKB debug¿ª¹Ø
skb_debug=`nv get skb_debug`
-echo "Info: set skb_debug£º$skb_debug" >> $test_log
+echo "Info: set skb_debug: $skb_debug" >> $test_log
if [ "-$skb_debug" != "-1" ]; then
echo 0 > /proc/net/skb_debug_off
fi
diff --git a/ap/app/Script/scripts/psext_updown.sh b/ap/app/Script/scripts/psext_updown.sh
index 890a6f1..56f4103 100755
--- a/ap/app/Script/scripts/psext_updown.sh
+++ b/ap/app/Script/scripts/psext_updown.sh
@@ -277,7 +277,7 @@
get_netmask_btrunk $pdp_ip
fi
- ifconfig $ps_if $ps_ip up 2>>$test_log
+ ifconfig $ps_if $ps_ip netmask 255.255.255.0 up 2>>$test_log
if [ $? -ne 0 ];then
echo "Error: ifconfig $ps_if $ps_ip up failed." >> $test_log
fi
diff --git a/ap/app/Script/scripts/wan_ipv4.sh b/ap/app/Script/scripts/wan_ipv4.sh
index e5f7446..e4c5a40 100755
--- a/ap/app/Script/scripts/wan_ipv4.sh
+++ b/ap/app/Script/scripts/wan_ipv4.sh
@@ -113,7 +113,7 @@
if [ $? -ne 0 ];then
echo "Error: ifconfig $wan_if down failed." >> $test_log
fi
- ifconfig $wan_if $pswan_ip up 2>>$test_log
+ ifconfig $wan_if $pswan_ip netmask 255.255.255.0 up 2>>$test_log
if [ $? -ne 0 ];then
echo "Error: ifconfig $wan_if $pswan_ip up failed." >> $test_log
fi
diff --git a/ap/lib/libatext/ext_dev_func.c b/ap/lib/libatext/ext_dev_func.c
index 24cbc83..3b442e4 100755
--- a/ap/lib/libatext/ext_dev_func.c
+++ b/ap/lib/libatext/ext_dev_func.c
@@ -329,7 +329,6 @@
int ate_req_rcv_act(char *at_paras,int at_fd,struct at_context *context)
{
int32_t setResult = 0;
- char strAtReplyCmd[AT_CMD_MAX] = {0};
if(atoi(at_paras) == 0 || atoi(at_paras) == 1)
{
@@ -347,9 +346,8 @@
setResult = vFnPortEchoType(at_fd, OPENECHO);
if(setResult != 0)
- {
- sprintf(strAtReplyCmd,"\r\nERROR: %d\r\n", setResult);
- at_write(at_fd, strAtReplyCmd, strlen(strAtReplyCmd));
+ {
+ at_write(at_fd, "\r\nERROR\r\n", strlen("\r\nERROR\r\n"));
}
else
{
diff --git a/ap/lib/libatext/ext_locknet.c b/ap/lib/libatext/ext_locknet.c
index efe68a0..d4372b8 100755
--- a/ap/lib/libatext/ext_locknet.c
+++ b/ap/lib/libatext/ext_locknet.c
@@ -3,74 +3,122 @@
int ext_LocklistAuth_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKLISTAUTH_REQ,strlen(at_paras), (unsigned char *)at_paras,0);
- return AT_CONTINUE;
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKLISTAUTH_REQ,strlen(at_paras), (unsigned char *)at_paras,0))
+ return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
int ext_LocknetList_set_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETLIST_SET_REQ,strlen(at_paras), (unsigned char *)at_paras,0);
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETLIST_SET_REQ,strlen(at_paras), (unsigned char *)at_paras,0))
return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
int ext_LocknetKey_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETKEY_REQ,strlen(at_paras), (unsigned char *)at_paras,0);
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETKEY_REQ,strlen(at_paras), (unsigned char *)at_paras,0))
return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
int ext_LocknetAmtStatus_get_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETAMTSTATUS_GET_REQ, 0, NULL,0);
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETAMTSTATUS_GET_REQ, 0, NULL,0))
return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
int ext_LocknetDigest_get_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETDIGEST_GET_REQ, 0, NULL,0);
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETDIGEST_GET_REQ, 0, NULL,0))
return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
int ext_LocknetSign_set_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETSIGN_SET_REQ,strlen(at_paras), (unsigned char *)at_paras,0);
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETSIGN_SET_REQ,strlen(at_paras), (unsigned char *)at_paras,0))
return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
int ext_LocknetLevel_get_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETLEVEL_GET_REQ, 0, NULL,0);
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETLEVEL_GET_REQ, 0, NULL,0))
return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
int ext_LocknetList_get_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETLIST_GET_REQ,strlen(at_paras), (unsigned char *)at_paras,0);
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETLIST_GET_REQ,strlen(at_paras), (unsigned char *)at_paras,0))
return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
int ext_LocknetAuth_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETAUTH_REQ, 0, NULL,0);
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETAUTH_REQ, 0, NULL,0))
return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
int ext_LocknetUnlockTimes_get_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETUNLOCKTIMES_GET_REQ, 0, NULL,0);
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETUNLOCKTIMES_GET_REQ, 0, NULL,0))
return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
int ext_LocknetStatus_get_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETSTATUS_GET_REQ, 0, NULL,0);
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETSTATUS_GET_REQ, 0, NULL,0))
return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
int ext_LocknetUnlock_func(char *at_paras, void ** res_msg)
{
- ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETUNLOCK_REQ,strlen(at_paras), (unsigned char *)at_paras,0);
+ if(0 == ipc_send_message(MODULE_ID_AT_CTL,MODULE_ID_LOCKNET,MSG_CMD_LOCKNETUNLOCK_REQ,strlen(at_paras), (unsigned char *)at_paras,0))
return AT_CONTINUE;
+ else{
+ *res_msg = at_err_build(ATERR_PROC_FAILED);
+ return AT_END;
+ }
}
//ÊÕµ½zudryÖ÷¶¯Éϱ¨ÃüÁîºó£¬Ï·¢AT+ZSCHPLMN=1ʹmodemÔÊÐíËÑÍø(¸ÃÃüÁîÊÇÔÚËøÍø¹¦ÄÜÖÐʹÓÃ)
diff --git a/ap/os/linux/linux-3.4.x/arch/arm/mach-zx297520v3/Makefile b/ap/os/linux/linux-3.4.x/arch/arm/mach-zx297520v3/Makefile
old mode 100644
new mode 100755
index e9d2669..1d079c1
--- a/ap/os/linux/linux-3.4.x/arch/arm/mach-zx297520v3/Makefile
+++ b/ap/os/linux/linux-3.4.x/arch/arm/mach-zx297520v3/Makefile
@@ -27,7 +27,7 @@
ifeq ($(USE_BTRUNK_SUPPORT),yes)
obj-y += hal_xp2xp.o
else
-ifeq ($(USE_VEHICLE_DC),yes)
+ifeq ($(USE_VEHICLE),yes)
obj-y += hal_xp2xp.o
endif
diff --git a/ap/os/linux/linux-3.4.x/drivers/mfd/zx234290-adc.c b/ap/os/linux/linux-3.4.x/drivers/mfd/zx234290-adc.c
old mode 100644
new mode 100755
index af82c3d..b15d08c
--- a/ap/os/linux/linux-3.4.x/drivers/mfd/zx234290-adc.c
+++ b/ap/os/linux/linux-3.4.x/drivers/mfd/zx234290-adc.c
@@ -354,10 +354,7 @@
int index=0;
int tmpValue=0,totalValue=0;
uint avgValue;
-#ifdef _USE_VEHICLE_DC
- printk("%s adc not support in ap\n",__func__);
- return 0;
-#endif
+
for(index = 0; index < counter; index++)
{
zx234290_adc_read(ADC_CHANNEL_VBAT_ADC, &tmpValue);
@@ -387,10 +384,7 @@
int index=0;
int tmpValue=0,totalValue=0;
uint avgValue;
-#ifdef _USE_VEHICLE_DC
- printk("%s adc not support in ap\n",__func__);
- return 0;
-#endif
+
for(index = 0; index < counter; index++)
{
zx234290_adc_read(ADC_CHANNEL_VADC1, &tmpValue);
@@ -421,10 +415,7 @@
int index=0;
int tmpValue=0,totalValue=0;
uint avgValue;
-#ifdef _USE_VEHICLE_DC
- printk("%s adc not support in ap\n",__func__);
- return 0;
-#endif
+
//wake_lock(&adc_wake_lock);
for(index = 0; index < counter; index++)
{
diff --git a/ap/os/linux/linux-3.4.x/drivers/usb/gadget/adb_server.c b/ap/os/linux/linux-3.4.x/drivers/usb/gadget/adb_server.c
old mode 100644
new mode 100755
index b2ed27e..ff872df
--- a/ap/os/linux/linux-3.4.x/drivers/usb/gadget/adb_server.c
+++ b/ap/os/linux/linux-3.4.x/drivers/usb/gadget/adb_server.c
@@ -38,9 +38,7 @@
struct adb_dev *g_adb_agent;
ssize_t adb_server_write2usb( const char *buf,size_t count);
extern void usb_rpmsg_notify_ap(usb_rpmsg_cmd *notify, int has_param);
-//xf.li@20230614 add for adb offline start
extern int usb_get_adb_agent(void);
-//xf.li@20230614 add for adb offline end
void adb_recv_from_ap(void *buf, unsigned int len)
{
@@ -184,10 +182,12 @@
if (!g_adb_agent)
return -1;
- T_ZDrvRpMsg_Msg *rpmsg = &g_adb_agent->rpmsg_tx;
-
- rpmsg->flag = 0;
- rpmsg->flag |= 1;
+ T_ZDrvRpMsg_Msg rpmsg = {0};
+
+ rpmsg.actorID = CAP_ID;
+ rpmsg.chID = ADB_RPMSG_CH;
+ rpmsg.flag = 0;
+ rpmsg.flag |= 1;
USBSTACK_DBG("adb_rpmsg_write2ap datalen:%d\n", len);
#if 0
if(len && len < 32){
@@ -201,8 +201,8 @@
}
#endif
if(len == 0){//just send notify
- rpmsg->len = len;
- ret = zDrvRpMsg_Write_Cap(&g_adb_agent->rpmsg_tx);
+ rpmsg.len = len;
+ ret = zDrvRpMsg_Write_Cap(&rpmsg);
if(ret < 0)
printk("adb_rpmsg_write2ap notify send fail, ret:%d\n", ret);
return ret;
@@ -211,11 +211,11 @@
while(total_cnt){
transfer_cnt = total_cnt > ADB_RPMSG_MAX_SIZE ? ADB_RPMSG_MAX_SIZE: total_cnt;
memcpy(g_adb_agent->rx2agt_buf, tmp, transfer_cnt);
- rpmsg->len = transfer_cnt;
- rpmsg->buf = g_adb_agent->rx2agt_buf;
+ rpmsg.len = transfer_cnt;
+ rpmsg.buf = g_adb_agent->rx2agt_buf;
atomic_set(&g_adb_agent->write_busy, 1);
- ret = zDrvRpMsg_Write_Cap(&g_adb_agent->rpmsg_tx);
- if(rpmsg->len != ret){
+ ret = zDrvRpMsg_Write_Cap(&rpmsg);
+ if(rpmsg.len != ret){
atomic_set(&g_adb_agent->write_busy, 0);
printk("[adb_rpmsg_write2ap] msg send error:(%d)", ret);
return ret;
@@ -422,7 +422,7 @@
ret = wait_event_interruptible(dev->agent_monitor_wq,
(atomic_read(&dev->agent_switch) ||kthread_should_stop()));
if (ret < 0) {
- printk("monitor_thread wait fail\n");
+ USBSTACK_DBG("monitor_thread wait fail\n");
//return ret;
continue;
}
@@ -443,11 +443,9 @@
//wakeup adb read and return
//dev->rx_done = 1;
//wake_up(&dev->read_wq);
- //xf.li@20230614 add for adb offline start
if (atomic_read(&dev->read_excl)){
adb_agent_dequeue_rx(dev);
}
- //xf.li@20230614 add for adb offline end
}else{
//dev->agent_start = 0;
//disable agent
@@ -486,19 +484,23 @@
return 0;
}
EXPORT_SYMBOL_GPL(adb_enable_rpmsg_agent);
-//xf.li@20230614 add for adb offline start
+
+
void adb_agent_switch_work(struct work_struct *work)
{
struct adb_dev *dev = container_of(work, struct adb_dev, agent_switch_work);
+
if(usb_get_adb_agent() == 1){
printk("agent_switch_work, switch to CAP\n");
adb_enable_rpmsg_agent(1);
return;
}
+
printk("agent_switch_work, switch to AP\n");
adb_enable_rpmsg_agent(0);
+
}
-//xf.li@20230614 add for adb offline end
+
void adb_rpmsg_recv_thread(void *ptr)
{
@@ -534,7 +536,7 @@
req->length = ADB_BULK_BUFFER_SIZE;
dev->rx_done = 0;
if(!dev->online){
- printk("rpmsg_recv dev is offline\n");
+ USBSTACK_DBG("rpmsg_recv dev is offline\n");
r = -EIO;
goto done;
}
@@ -568,21 +570,21 @@
dev->agt_error = 1;
r = ret;
usb_ep_dequeue(dev->ep_out, req);
- USBSTACK_DBG("rpmsg_recv stop ret: 0x%x", ret);
+ printk("rpmsg_recv stop ret: 0x%x", ret);
goto done;
}
if (!dev->agt_error) {
if(!dev->online){
- printk("rpmsg_recv dev is offline cannot requeue req\n");
+ USBSTACK_DBG("rpmsg_recv dev is offline cannot requeue req\n");
r = -EIO;
goto done;
}
/* If we got a 0-len packet, throw it back and try again. */
if (req->actual == 0){
- printk("rpmsg_recv actual is 0, requeue_req again\n");
+ USBSTACK_DBG("rpmsg_recv actual is 0, requeue_req again\n");
goto requeue_req;
}
- printk("rpmsg_recv rx %p actual:%d\n", req, req->actual);
+ //printk("rpmsg_recv rx %p actual:%d\n", req, req->actual);
xfer = req->actual;
r = adb_rpmsg_write2ap(req->buf, xfer);
@@ -593,11 +595,11 @@
goto requeue_req;
} else{
if(dev->agent_start){
- printk("rpmsg_recv fail ,len:%d, status:%d\n", req->actual, req->status);
+ USBSTACK_DBG("rpmsg_recv fail ,len:%d, status:%d\n", req->actual, req->status);
r = -EIO;
dev->rx_done = 0;
}else{
- printk("adb_rpmsg_write wake_up agt_read_wq, len:%d, status:%d\n", req->actual, req->status);
+ USBSTACK_DBG("adb_rpmsg_write wake_up agt_read_wq, len:%d, status:%d\n", req->actual, req->status);
wake_up(&dev->agt_read_wq);
}
@@ -629,9 +631,7 @@
init_waitqueue_head(&dev->agt_read_wq);
init_waitqueue_head(&dev->agt_write_wq);
INIT_WORK(&dev->agent_inform_work, adb_agent_inform_work);
-//xf.li@20230614 add for adb offline start
INIT_DELAYED_WORK(&dev->agent_switch_work, adb_agent_switch_work);
-//xf.li@20230614 add for adb offline end
atomic_set(&dev->agent_switch, 0);
atomic_set(&dev->write_busy, 0);
atomic_set(&dev->agt_read_flag, 0);
@@ -655,9 +655,6 @@
dev->agent_monitor_thread = kthread_run(adb_agent_monitor_thread, (unsigned long)dev+1, "adb_agent_monitor");
BUG_ON(IS_ERR(dev->agent_monitor_thread));
g_adb_agent = dev;
- g_adb_agent->rpmsg_tx.actorID = CAP_ID;
- g_adb_agent->rpmsg_tx.chID = ADB_RPMSG_CH;
- //g_adb_agent->rpmsg_tx.flag= 0x1;
//alloc 512
g_adb_agent->rx2agt_buf = kmalloc(ADB_BULK_BUFFER_SIZE, GFP_KERNEL);
if(!g_adb_agent->rx2agt_buf){
diff --git a/ap/os/linux/linux-3.4.x/drivers/usb/gadget/f_adb.c b/ap/os/linux/linux-3.4.x/drivers/usb/gadget/f_adb.c
old mode 100644
new mode 100755
index 75825ef..9561ca8
--- a/ap/os/linux/linux-3.4.x/drivers/usb/gadget/f_adb.c
+++ b/ap/os/linux/linux-3.4.x/drivers/usb/gadget/f_adb.c
@@ -38,9 +38,8 @@
extern int adb_rpmsg_write2ap(void *buf, unsigned int len);
extern int adb_agent_close(void);
extern void adb_server_plug_notify(e_usb_rpmsg_cmd_type plug_type);
-//xf.li@20230614 add for adb offline start
extern int usb_get_adb_agent(void);
-//xf.li@20230614 add for adb offline end
+
#endif
static const char adb_shortname[] = "android_adb";
@@ -73,7 +72,6 @@
atomic_t agt_read_flag;
atomic_t adb_read_flag;
int agt_error;
- T_ZDrvRpMsg_Msg rpmsg_tx;
char *rx2agt_buf;
struct task_struct *rpmsg_thread;
struct task_struct *agent_monitor_thread;
@@ -324,18 +322,20 @@
int ret;
USBSTACK_DBG("adb_read enter(%d)\n", count);
- if (!_adb_dev)
+ if (!_adb_dev){
+ USBSTACK_DBG("adb_read: _adb_dev is NULL\n");
return -ENODEV;
-
+ }
if (count > ADB_BULK_BUFFER_SIZE)
return -EINVAL;
- if (adb_lock(&dev->read_excl))
+ if (adb_lock(&dev->read_excl)){
+ USBSTACK_DBG("adb_read: read_excl lock fail, \n");
return -EBUSY;
-
+ }
/* we will block until we're online */
while (!(dev->online || dev->error)) {
- pr_debug("adb_read: waiting for online state\n");
+ USBSTACK_DBG("adb_read: waiting for online state\n");
ret = wait_event_interruptible(dev->read_wq,
(dev->online || dev->error));
if (ret < 0) {
@@ -554,7 +554,7 @@
printk("---adb_open, switch to cap\n");
schedule_delayed_work(&_adb_dev->agent_switch_work, 200);
}
-#endif
+#endif
USBSTACK_DBG("%s", __func__);
if (adb_lock(&_adb_dev->open_excl)){
printk("\n adb_open,open_excl:%d\n", atomic_read(&_adb_dev->open_excl));
@@ -570,16 +570,13 @@
if(atomic_read(&_adb_dev->enable_excl)){
_adb_dev->online = 1;
wake_up(&_adb_dev->read_wq);
-//xf.li@20230614 add for adb offline start
}else{
-
adb_unlock(&_adb_dev->open_excl);
return -ENODEV;
-//xf.li@20230614 add for adb offline end
}
usb_record_dbginfo(USB_DEV_OPEN, 0, 3);
- printk("\n adb_open--ok--exit\n");
+ printk("\n adb_open--ok--exit,online:%d\n", _adb_dev->online);
return 0;
}
@@ -747,6 +744,7 @@
return 0;
if(atomic_read(&dev->open_excl)==1){
+ printk("adb_function_set_alt, adb open, and set online \n");
dev->online = 1;
dev->error= 0;
/* readers may be blocked waiting for us to go online */
diff --git a/ap/os/linux/linux-3.4.x/net/bridge/br_forward.c b/ap/os/linux/linux-3.4.x/net/bridge/br_forward.c
old mode 100644
new mode 100755
index 36cde04..b3dc65f
--- a/ap/os/linux/linux-3.4.x/net/bridge/br_forward.c
+++ b/ap/os/linux/linux-3.4.x/net/bridge/br_forward.c
@@ -267,6 +267,8 @@
void br_multicast_deliver(struct net_bridge_mdb_entry *mdst,
struct sk_buff *skb)
{
+ if(br_multicast_off)
+ return;
br_multicast_flood(mdst, skb, NULL, __br_deliver);
}
@@ -274,6 +276,8 @@
void br_multicast_forward(struct net_bridge_mdb_entry *mdst,
struct sk_buff *skb, struct sk_buff *skb2)
{
+ if(br_multicast_off)
+ return;
br_multicast_flood(mdst, skb, skb2, __br_forward);
}
#endif
diff --git a/ap/os/linux/linux-3.4.x/net/bridge/br_multicast.c b/ap/os/linux/linux-3.4.x/net/bridge/br_multicast.c
old mode 100644
new mode 100755
index 87ae8c3..548920d
--- a/ap/os/linux/linux-3.4.x/net/bridge/br_multicast.c
+++ b/ap/os/linux/linux-3.4.x/net/bridge/br_multicast.c
@@ -38,7 +38,7 @@
static void br_multicast_add_router(struct net_bridge *br,
struct net_bridge_port *port);
-
+int br_multicast_off = 0;
#if IS_ENABLED(CONFIG_IPV6)
static inline int ipv6_is_transient_multicast(const struct in6_addr *addr)
{
@@ -140,6 +140,8 @@
struct net_bridge_mdb_entry *br_mdb_get(struct net_bridge *br,
struct sk_buff *skb)
{
+ if(br_multicast_off)
+ return NULL;
struct net_bridge_mdb_htable *mdb = rcu_dereference(br->mdb);
struct br_ip ip;
@@ -226,6 +228,8 @@
static void br_multicast_group_expired(unsigned long data)
{
+ if(br_multicast_off)
+ return;
struct net_bridge_mdb_entry *mp = (void *)data;
struct net_bridge *br = mp->br;
struct net_bridge_mdb_htable *mdb;
@@ -287,6 +291,8 @@
static void br_multicast_port_group_expired(unsigned long data)
{
+ if(br_multicast_off)
+ return;
struct net_bridge_port_group *pg = (void *)data;
struct net_bridge *br = pg->port->br;
@@ -725,6 +731,8 @@
static void br_multicast_router_expired(unsigned long data)
{
+ if(br_multicast_off)
+ return;
struct net_bridge_port *port = (void *)data;
struct net_bridge *br = port->br;
@@ -793,6 +801,8 @@
static void br_multicast_port_query_expired(unsigned long data)
{
+ if(br_multicast_off)
+ return;
struct net_bridge_port *port = (void *)data;
struct net_bridge *br = port->br;
@@ -814,6 +824,8 @@
void br_multicast_add_port(struct net_bridge_port *port)
{
+ if(br_multicast_off)
+ return;
port->multicast_router = 1;
setup_timer(&port->multicast_router_timer, br_multicast_router_expired,
@@ -824,6 +836,8 @@
void br_multicast_del_port(struct net_bridge_port *port)
{
+ if(br_multicast_off)
+ return;
del_timer_sync(&port->multicast_router_timer);
}
@@ -839,7 +853,8 @@
void br_multicast_enable_port(struct net_bridge_port *port)
{
struct net_bridge *br = port->br;
-
+ if(br_multicast_off)
+ return;
spin_lock(&br->multicast_lock);
if (br->multicast_disabled || !netif_running(br->dev))
goto out;
@@ -857,7 +872,8 @@
struct net_bridge *br = port->br;
struct net_bridge_port_group *pg;
struct hlist_node *p, *n;
-
+ if(br_multicast_off)
+ return;
spin_lock(&br->multicast_lock);
hlist_for_each_entry_safe(pg, p, n, &port->mglist, mglist)
br_multicast_del_pg(br, pg);
@@ -1522,6 +1538,8 @@
int br_multicast_rcv(struct net_bridge *br, struct net_bridge_port *port,
struct sk_buff *skb)
{
+ if(br_multicast_off)
+ return 0;
BR_INPUT_SKB_CB(skb)->igmp = 0;
BR_INPUT_SKB_CB(skb)->mrouters_only = 0;
@@ -1543,7 +1561,8 @@
static void br_multicast_query_expired(unsigned long data)
{
struct net_bridge *br = (void *)data;
-
+ if(br_multicast_off)
+ return;
spin_lock(&br->multicast_lock);
if (br->multicast_startup_queries_sent <
br->multicast_startup_query_count)
@@ -1556,6 +1575,8 @@
void br_multicast_init(struct net_bridge *br)
{
+ if(br_multicast_off)
+ return;
br->hash_elasticity = 4;
br->hash_max = 512;
@@ -1581,6 +1602,8 @@
void br_multicast_open(struct net_bridge *br)
{
+ if(br_multicast_off)
+ return;
br->multicast_startup_queries_sent = 0;
if (br->multicast_disabled)
@@ -1596,7 +1619,8 @@
struct hlist_node *p, *n;
u32 ver;
int i;
-
+ if(br_multicast_off)
+ return;
del_timer_sync(&br->multicast_router_timer);
del_timer_sync(&br->multicast_querier_timer);
del_timer_sync(&br->multicast_query_timer);
diff --git a/ap/os/linux/linux-3.4.x/net/bridge/br_private.h b/ap/os/linux/linux-3.4.x/net/bridge/br_private.h
old mode 100644
new mode 100755
index 6822ef1..bfb0f3d
--- a/ap/os/linux/linux-3.4.x/net/bridge/br_private.h
+++ b/ap/os/linux/linux-3.4.x/net/bridge/br_private.h
@@ -421,8 +421,11 @@
extern int br_multicast_toggle(struct net_bridge *br, unsigned long val);
extern int br_multicast_set_hash_max(struct net_bridge *br, unsigned long val);
+extern int br_multicast_off;
static inline bool br_multicast_is_router(struct net_bridge *br)
{
+ if(br_multicast_off)
+ return 0;
return br->multicast_router == 2 ||
(br->multicast_router == 1 &&
timer_pending(&br->multicast_router_timer));
diff --git a/ap/os/linux/linux-3.4.x/net/core/fastproc/fast_track.c b/ap/os/linux/linux-3.4.x/net/core/fastproc/fast_track.c
index 1ae104b..c118526 100755
--- a/ap/os/linux/linux-3.4.x/net/core/fastproc/fast_track.c
+++ b/ap/os/linux/linux-3.4.x/net/core/fastproc/fast_track.c
@@ -1112,6 +1112,7 @@
const char __user *buffer, size_t count, loff_t *pos)
{
skb_debug_off();
+ printk("skb_debug_off\n");
return count;
}
@@ -1195,6 +1196,20 @@
.write = skb_debug_off_set,
};
+extern int br_multicast_off;
+static ssize_t br_multicast_off_set(struct file *file,
+ const char __user *buffer, size_t count, loff_t *pos)
+{
+ br_multicast_off = 1;
+ printk("br_multicast_off\n");
+ return count;
+}
+
+static const struct file_operations br_multicast_off_file_ops = {
+ .owner = THIS_MODULE,
+ .write = br_multicast_off_set,
+};
+
//¿ìËÙת·¢procÎļþµÄ³õʼ»¯
int fast_conntrack_init_proc(void)
{
@@ -1227,6 +1242,10 @@
//turn off skb debug
proc_create("skb_debug_off", 0440, init_net.proc_net, &skb_debug_off_file_ops);
+
+ //turn off br multicast
+ proc_create("br_multi_off", 0440, init_net.proc_net, &br_multicast_off_file_ops);
+
return 1;
}
diff --git a/cap/zx297520v3/sources/meta-zxic/recipes-app/fota-upi-ab/fota-upi-ab.bb b/cap/zx297520v3/sources/meta-zxic/recipes-app/fota-upi-ab/fota-upi-ab.bb
index 7c0e66e..e2f1edb 100755
--- a/cap/zx297520v3/sources/meta-zxic/recipes-app/fota-upi-ab/fota-upi-ab.bb
+++ b/cap/zx297520v3/sources/meta-zxic/recipes-app/fota-upi-ab/fota-upi-ab.bb
@@ -1,6 +1,6 @@
DESCRIPTION = "fota_upi_ab"
#ota-upgrade依赖库
-DEPENDS = "libmtd libnvram libsoftap libsofttimer libatutils libupi-ab"
+DEPENDS = "libnvram libsoftap libsofttimer libatutils libupi-ab"
SECTION = "app"
LICENSE = "zte"
PV = "1.0.0"
@@ -9,7 +9,7 @@
#配置code路径信息。
FILESEXTRAPATHS_prepend :="${APP-OPEN-PATH}/platform:"
SRC_URI = " \
- ${@bb.utils.contains("MK_SDK_VERSION", "yes", "", "file://fota_upi_ab", d)} \
+ file://fota_upi_ab \
"
LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/zte;md5=c075689d1d1e06d4ab5bbe53623a6808"
@@ -23,30 +23,21 @@
#编译
do_compile() {
- if [ ${MK_SDK_VERSION} = "no" ]; then
- make -C fota_upi_ab
- fi
+ make -C fota_upi_ab
}
#库文件的安装，封库的宏MK_SDK_VERSION
-do_install () {
- if [ ${MK_SDK_VERSION} = "no" ]; then
- install -d ${RELEASE-PATH}/executable
- install -m 0755 ${S}/fota_upi_ab/fota_upi_ab_static ${RELEASE-PATH}/executable
-
- #install elfs
- install -d ${ELFS-PATH}/
- install -m 0755 ${S}/fota_upi_ab/fota_upi_ab_static ${ELFS-PATH}/
- fi
-
+do_install () {
install -d ${D}${bindir}/
- install -m 0755 ${RELEASE-PATH}/executable/fota_upi_ab_static ${D}${bindir}/
+ install -m 0755 ${S}/fota_upi_ab/fota_upi_ab_static ${D}${bindir}/
+
+ #install elfs
+ install -d ${ELFS-PATH}/
+ install -m 0755 ${S}/fota_upi_ab/fota_upi_ab_static ${ELFS-PATH}/
}
#清库
do_cleanlibs () {
- if [ ${MK_SDK_VERSION} = "no" ]; then
- rm -fr ${ELFS-PATH}/fota_upi_ab
- fi
+ rm -fr ${ELFS-PATH}/fota_upi_ab
}
addtask cleanlibs after do_clean before do_cleansstate
diff --git a/cap/zx297520v3/sources/meta-zxic/recipes-app/libupi-ab/libupi-ab.bb b/cap/zx297520v3/sources/meta-zxic/recipes-app/libupi-ab/libupi-ab.bb
index cecb662..b54d5e7 100755
--- a/cap/zx297520v3/sources/meta-zxic/recipes-app/libupi-ab/libupi-ab.bb
+++ b/cap/zx297520v3/sources/meta-zxic/recipes-app/libupi-ab/libupi-ab.bb
@@ -1,5 +1,5 @@
DESCRIPTION = "libupi_ab"
-DEPENDS = "libnvram libsoftap libsofttimer libatutils zlib openssl libmtd"
+DEPENDS = "libnvram libsoftap libsofttimer libatutils zlib openssl"
SECTION = "lib"
LICENSE = "zte"
PV = "1.0.0"
@@ -7,7 +7,7 @@
LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/zte;md5=c075689d1d1e06d4ab5bbe53623a6808"
#配置code路径信息。
-FILESEXTRAPATHS_prepend :="${APP-OPEN-PATH}/sdk:"
+FILESEXTRAPATHS_prepend :="${APP-PATH}:"
SRC_URI = " \
${@bb.utils.contains("MK_SDK_VERSION", "yes", "", "file://libupi_ab", d)} \
"
@@ -22,7 +22,7 @@
do_compile () {
if [ ${MK_SDK_VERSION} = "no" ]; then
make -C libupi_ab
- fi
+ fi
}
do_install () {
@@ -32,18 +32,19 @@
install -m 0755 ${S}/libupi_ab/libupi_ab.so ${RELEASE-PATH}/lib
install -m 0755 ${S}/libupi_ab/libupi_ab.a ${RELEASE-PATH}/lib
- install -m 0644 ${S}/libupi_ab/inc/*.h ${RELEASE-PATH}/include/upi_ab
+ install -m 0644 ${S}/libupi_ab/inc/zxic_fota_ab_upgrade.h ${RELEASE-PATH}/include/upi_ab
#install elfs
install -d ${ELFS-PATH}/
install -m 0755 ${S}/libupi_ab/libupi_ab.so ${ELFS-PATH}/
- fi
+ fi
+
install -d ${D}${libdir}/
install -d ${D}/usr/include
install -m 0755 ${RELEASE-PATH}/lib/libupi_ab.so ${D}${libdir}/
install -m 0755 ${RELEASE-PATH}/lib/libupi_ab.a ${D}${libdir}/
- install -m 0644 ${RELEASE-PATH}/include/upi_ab/*.h ${D}/usr/include/
+ install -m 0644 ${RELEASE-PATH}/include/upi_ab/*.h ${D}/usr/include/
}
#清库
@@ -63,4 +64,4 @@
FILES_SOLIBSDEV = ""
INSANE_SKIP_${PN} = "dev-so"
-RDEPENDS_${PN} = "libnvram libsoftap libsofttimer libatutils zlib libmtd"
+RDEPENDS_${PN} = "libnvram libsoftap libsofttimer libatutils zlib"
diff --git a/cap/zx297520v3/sources/poky/meta/classes/reproducible_build.bbclass b/cap/zx297520v3/sources/poky/meta/classes/reproducible_build.bbclass
old mode 100644
new mode 100755
index ec86255..2b402b9
--- a/cap/zx297520v3/sources/poky/meta/classes/reproducible_build.bbclass
+++ b/cap/zx297520v3/sources/poky/meta/classes/reproducible_build.bbclass
@@ -64,7 +64,6 @@
SSTATETASKS += "do_deploy_source_date_epoch"
do_deploy_source_date_epoch () {
-
mkdir -p ${SDE_DEPLOYDIR}
if [ -e ${SDE_FILE} ]; then
echo "Deploying SDE from ${SDE_FILE} -> ${SDE_DEPLOYDIR}."
diff --git a/cap/zx297520v3/zxic_code/zxic_binary/zxic_app_release/glibc/include/upi_ab/zxic_fota_ab_upgrade.h b/cap/zx297520v3/zxic_code/zxic_binary/zxic_app_release/glibc/include/upi_ab/zxic_fota_ab_upgrade.h
new file mode 100755
index 0000000..3757f91
--- /dev/null
+++ b/cap/zx297520v3/zxic_code/zxic_binary/zxic_app_release/glibc/include/upi_ab/zxic_fota_ab_upgrade.h
@@ -0,0 +1,384 @@
+/**
+* @file zxic_fota_ab_upgrade.h
+* @brief ABϵͳFOTAÉý¼¶¶ÔÍâ½Ó¿Ú
+*
+* Copyright (C) 2017 Sanechips Technology Co., Ltd.
+* @author
+*
+*/
+
+#ifndef ZXIC_FOTA_AB_UPGRADE_H
+#define ZXIC_FOTA_AB_UPGRADE_H
+
+/*******************************************************************************
+ * Include header files *
+ ******************************************************************************/
+
+
+
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+
+#define Z_FOTA_SUCCESS (0)
+#define Z_FOTA_FAIL (-1)
+
+/*
+ ºê¶¨Ò壺Éý¼¶×´Ì¬ºê
+ */
+#define Z_UPGRAGE_STATUS_FREE (-1)
+#define Z_UPGRADE_STATUS_VERIFING (0)
+#define Z_UPGRADE_STATUS_VERIFY_SUCCESS (1)
+#define Z_UPGRADE_STATUS_VERIFY_FAIL (2)
+#define Z_UPGRADE_STATUS_UPDATING (3)
+#define Z_UPGRADE_STATUS_UPDATE_SUCCESS (4)
+#define Z_UPGRADE_STATUS_UPDATE_FAIL (5)
+
+
+/*
+ * ºê¶¨Ò壺˫ϵͳÆô¶¯£¬ÏµÍ³×´Ì¬
+ */
+#define Z_DUALSYSTEM_STATUS_BOOTABLE (0xB0AB) /* ¿ÉÆô¶¯ */
+#define Z_DUALSYSTEM_STATUS_SUCCESSFUL (0x5CCF) /* Äܳɹ¦Æô¶¯ */
+#define Z_DUALSYSTEM_STATUS_UNBOOTABLE (0xBABE) /* ²»¿ÉÆô¶¯ */
+
+
+#define Z_DUAL_SYSTEM (0x875A)
+#define Z_DUAL_SYSTEM2 (0x986B)
+
+
+/*
+ *ºê¶¨Ò壺Éý¼¶ÀàÐÍ
+ */
+#define Z_UPGRADE_TYPE_ALL (0) /* È«°æ±¾ÀàÐÍ */
+#define Z_UPGRADE_TYPE_PLATFORM (1) /* ƽ̨ÀàÐÍ */
+#define Z_UPGRADE_TYPE_OEM (2) /* OEMÀàÐÍ */
+#define Z_UPGRADE_TYPE_INVALID (-1) /* ÎÞЧÀàÐÍ */
+
+
+/*******************************************************************************
+ * Type definitions *
+ ******************************************************************************/
+
+
+
+/*
+ * ˵Ã÷£ºÉý¼¶×´Ì¬ÐÅÏ¢½á¹¹Ìå
+ * upgrade_status:Éý¼¶×´Ì¬£¬È¡Öµ²Î¿¼¡¾Éý¼¶×´Ì¬ºê¡¿
+ * total_size:´ýдÈëÉý¼¶·ÖÇø×ܳ¤¶È
+ * upgraded_size:ÒÑÉý¼¶·ÖÇø³¤¶È
+ * ×¢Ò⣺
+ * ³¤¶ÈÐÅÏ¢½öÔÚÉý¼¶×´Ì¬ÎªUPGRADE_STATUS_UPDATINGʱÓÐЧ£¬ÆäËü״̬²ÎÊýÖµÎÞʵ¼ÊÒâÒå
+ */
+
+typedef struct
+{
+ int upgrade_status;
+ int total_size;
+ int upgraded_size;
+} z_upgrade_status_info_t;
+
+
+/*
+ * ˵Ã÷£ºµ¥ÏµÍ³×´Ì¬
+ * system:µ±Ç°ÏµÍ³ Z_DUAL_SYSTEM¡¢Z_DUAL_SYSTEM2
+ * status:ϵͳ״̬ Z_DUALSYSTEM_STATUS_BOOTABLE¡¢Z_DUALSYSTEM_STATUS_SUCCESSFUL¡¢Z_DUALSYSTEM_STATUS_UNBOOTABLE
+ * try_cnt:ÖØÆô´ÎÊý
+ * ×¢Ò⣺
+ * ³¤¶ÈÐÅÏ¢½öÔÚÉý¼¶×´Ì¬ÎªUPGRADE_STATUS_UPDATINGʱÓÐЧ£¬ÆäËü״̬²ÎÊýÖµÎÞʵ¼ÊÒâÒå
+ */
+typedef struct
+{
+ int system;
+ int status; /* bootable/successful/unbootable */
+ int try_cnt;
+} z_system_info_t;
+
+
+/*
+ * ˵Ã÷£ºÏµÍ³×´Ì¬
+ * boot_to:Ï´ÎÆô¶¯ÏµÍ³
+ * system_1:ϵͳ1״̬
+ * system_2:ϵͳ2״̬
+ * ×¢Ò⣺
+ *
+ */
+typedef struct
+{
+ int boot_to; /* µ±Ç°Æô¶¯ÏµÍ³±êÖ¾*/
+ int fota_status;
+ z_system_info_t system_1;
+ z_system_info_t system_2;
+} z_upgrade_system_info_t;
+
+
+typedef struct
+{
+ z_upgrade_status_info_t *status;
+ void(* status_cb)(z_upgrade_status_info_t *status);
+} z_upgrade_flush_status_t;
+
+
+//typedef void(* flush_upgrade_status)(z_upgrade_status_info_t *status);
+
+
+/*******************************************************************************
+ * Global variable declarations *
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Global function declarations *
+ ******************************************************************************/
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_verify
+ * ¹¦ÄÜÃèÊö:Éý¼¶°üºÏ·¨ÐÔУÑé
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£ºÎÞ
+ * Êä³ö²ÎÊý:ÎÞ
+ * ·µ»ØÖµ£º
+ * Z_FOTA_SUCCESS УÑé³É¹¦
+ * Z_FOTA_FAILУÑéʧ°Ü
+ * ×¢Òâ:
+ * ͬ²½½Ó¿Ú£¬½¨ÒéÒì²½µ÷ÓÃ
+ ********************************************************************************/
+int zxic_dual_verify();
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_upgrade
+ * ¹¦ÄÜÃèÊö:¿ªÊ¼Éý¼¶
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£º
+ * flush_upgrade_status ״̬»Øµ÷½Ó¿Ú
+ * Êä³ö²ÎÊý:ÎÞ
+ * ·µ»ØÖµ£º
+ * Z_FOTA_SUCCESS Éý¼¶³É¹¦
+ * Z_FOTA_FAILÉý¼¶Ê§°Ü
+ * ×¢Òâ:
+ * ͬ²½½Ó¿Ú£¬½¨ÒéÒì²½µ÷Ó㬱ÜÃâ×èÈû
+ * ״̬»Øµ÷½Ó¿ÚÖнûÖ¹×ö¸´ÔÓ²Ù×÷£¬½¨Òé½ö½øÐÐ״̬Êä³ö
+********************************************************************************/
+
+int zxic_dual_upgrade(z_upgrade_flush_status_t* flush_status);
+
+
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_get_upgrade_status
+ * ¹¦ÄÜÃèÊö:Éý¼¶×´Ì¬»ñÈ¡
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£ºÎÞ
+ * Êä³ö²ÎÊý:
+ * upgrade_info_t *upgrade_info Éý¼¶×´Ì¬
+ * ·µ»ØÖµ£º
+ * Z_FOTA_SUCCESS Éý¼¶³É¹¦
+ * Z_FOTA_FAILÉý¼¶Ê§°Ü
+ * ×¢Òâ:
+********************************************************************************/
+int zxic_dual_get_upgrade_status(z_upgrade_status_info_t *upgrade_info);
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_get_current_system
+ * ¹¦ÄÜÃèÊö:»ñÈ¡µ±Ç°ÔËÐÐϵͳ
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£ºÎÞ
+ * Êä³ö²ÎÊý:ÎÞ
+ * ·µ»ØÖµ£º
+ * µ±Ç°ÔËÐÐϵͳ
+ * ×¢Òâ:
+********************************************************************************/
+int zxic_dual_get_current_system();
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_get_boot_to_system
+ * ¹¦ÄÜÃèÊö:»ñÈ¡ÖØÆôºóÄ¿±êÆô¶¯ÏµÍ³
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£ºÎÞ
+ * Êä³ö²ÎÊý:ÎÞ
+ * ·µ»ØÖµ£º
+ * µ±Ç°ÔËÐÐϵͳ
+ * ×¢Òâ:
+********************************************************************************/
+int zxic_dual_get_boot_to_system();
+
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_set_boot_to_system
+ * ¹¦ÄÜÃèÊö:ÉèÖÃÄ¿±êÔËÐÐϵͳ
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£º
+ * system:Ä¿±êϵͳ
+ * reboot_flag:ÉèÖÃÍê±ÏºóÊÇ·ñÁ¢¼´ÖØÆô 0:²»ÖØÆô,1:ÖØÆô
+ * Êä³ö²ÎÊý:
+ * ϵͳ״̬ÐÅÏ¢
+ * ·µ»ØÖµ£º
+ * Z_FOTA_SUCCESS »ñÈ¡ÐÅÏ¢³É¹¦
+ * Z_FOTA_FAIL»ñÈ¡ÐÅϢʧ°Ü
+ * ×¢Òâ:
+ * ·µ»ØÖµ£ºÖ»ÔÚ²»ÐèÒªÖØÆôʱÓÐЧ
+********************************************************************************/
+int zxic_dual_set_boot_to_system(int system, int reboot_flag);
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_get_system_status
+ * ¹¦ÄÜÃèÊö:²éѯABϵͳ״̬
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£ºÎÞ
+ * Êä³ö²ÎÊý:
+ * system_info ϵͳ״̬ÐÅÏ¢
+ * ·µ»ØÖµ£º
+ * Z_FOTA_SUCCESS »ñÈ¡ÐÅÏ¢³É¹¦
+ * Z_FOTA_FAIL»ñÈ¡ÐÅϢʧ°Ü
+ * ×¢Òâ:
+********************************************************************************/
+int zxic_dual_get_system_status(z_upgrade_system_info_t *system_info);
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_set_system_status
+ * ¹¦ÄÜÃèÊö:ÉèÖÃϵͳ״̬
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£º
+ * system:´ýÉèÖÃϵͳ
+ * status:ÉèÖÃϵͳ״̬
+ * Êä³ö²ÎÊý:ÎÞ
+ * ·µ»ØÖµ£º
+ * Z_FOTA_SUCCESS »ñÈ¡ÐÅÏ¢³É¹¦
+ * Z_FOTA_FAIL»ñÈ¡ÐÅϢʧ°Ü
+ * ×¢Òâ:
+********************************************************************************/
+int zxic_dual_set_system_status(int system, int status);
+
+/*******************************************************************************
+ * Inline function implementations *
+ ******************************************************************************/
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_init_flag_partition
+ * ¹¦ÄÜÃèÊö:³õʼ»¯flag·ÖÇøÐÅÏ¢,²âÊÔ½Ó¿Ú£¬Õý³£Á÷³Ì²»¿ÉʹÓÃ
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý:ÎÞ
+ * Êä³ö²ÎÊý:ÎÞ
+ * ·µ»ØÖµ£º
+ * Z_FOTA_SUCCESS »ñÈ¡ÐÅÏ¢³É¹¦
+ * Z_FOTA_FAIL»ñÈ¡ÐÅϢʧ°Ü
+ * ×¢Òâ:
+********************************************************************************/
+
+int zxic_init_flag_partition();
+
+
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_get_fota_status_for_nv
+ * ¹¦ÄÜÃèÊö:»ñȡϵͳNVÊÇ·ñͬ²½±êÖ¾
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£ºÎÞ
+ * Êä³ö²ÎÊý:ÎÞ
+ * ·µ»ØÖµ£º
+ * ״̬±êÖ¾ 0£º²»ÐèҪͬ²½£¬1£ºÐèҪͬ²½
+ * ×¢Òâ:
+********************************************************************************/
+int zxic_dual_get_fota_status_for_nv();
+int dual_AB_get_fota_status_for_nv();
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_set_fota_status_for_nv
+ * ¹¦ÄÜÃèÊö:ÉèÖÃϵͳNVÊÇ·ñͬ²½±êÖ¾
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£º
+ * status:״̬±êÖ¾£¬0£º²»ÐèҪͬ²½£¬1£ºÐèҪͬ²½
+ * Êä³ö²ÎÊý:ÎÞ
+ * ·µ»ØÖµ£º
+ * Z_FOTA_SUCCESS ÉèÖóɹ¦
+ * Z_FOTA_FAIL ÉèÖÃʧ°Ü
+ * ×¢Òâ:
+********************************************************************************/
+int zxic_dual_set_fota_status_for_nv(int status);
+int dual_AB_set_fota_status_for_nv(int status);
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_sync_system
+ * ¹¦ÄÜÃèÊö: AB-AAϵͳͬ²½
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£ºÎÞ
+ * Êä³ö²ÎÊý: ÎÞ
+ * ·µ»ØÖµ£º
+ * Z_FOTA_SUCCESS ͬ²½³É¹¦
+ * Z_FOTA_FAIL ͬ²½Ê§°Ü
+ * ×¢Òâ:
+ ********************************************************************************/
+int zxic_dual_sync_system(void);
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_get_upgrade_type
+ * ¹¦ÄÜÃèÊö: »ñÈ¡Éý¼¶ÀàÐÍ
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£ºÎÞ
+ * Êä³ö²ÎÊý: ÎÞ
+ * ·µ»ØÖµ£º
+ * Z_UPGRADE_TYPE_ALL È«°æ±¾ÀàÐÍ
+ * Z_UPGRADE_TYPE_PLATFORM ƽ̨ÀàÐÍ
+ * Z_UPGRADE_TYPE_OEM OEMÀàÐÍ
+ * Z_UPGRADE_TYPE_INVALID ÎÞЧÀàÐÍ
+ * ×¢Òâ:
+ ********************************************************************************/
+int zxic_dual_get_upgrade_type(void);
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_get_sync_status
+ * ¹¦ÄÜÃèÊö: »ñȡͬ²½×´Ì¬
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£ºÎÞ
+ * Êä³ö²ÎÊý:
+ * sync_status ͬ²½×´Ì¬
+ * ·µ»ØÖµ£ºÎÞ
+ * ×¢Òâ:
+ ********************************************************************************/
+void zxic_dual_get_sync_status(int *sync_status);
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_set_sync_status
+ * ¹¦ÄÜÃèÊö: ÉèÖÃͬ²½×´Ì¬
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£º
+ * sync_status ͬ²½×´Ì¬
+ * Êä³ö²ÎÊý: ÎÞ
+ * ·µ»ØÖµ£º
+ * Z_FOTA_SUCCESS ÉèÖóɹ¦
+ * Z_FOTA_FAIL ÉèÖÃʧ°Ü
+ * ×¢Òâ:
+ ********************************************************************************/
+int zxic_dual_set_sync_status(int sync_status);
+
+
+/********************************************************************************
+ * º¯ÊýÃû: zxic_dual_config_package_path
+ * ¹¦ÄÜÃèÊö: ÉèÖÃÉý¼¶°ü·¾¶
+ * ²ÎÊý˵Ã÷£º
+ * ÊäÈë²ÎÊý£º
+ * upgrade_package_path Éý¼¶°ü·¾¶
+ * length Éý¼¶°ü·¾¶³¤¶È
+ * Êä³ö²ÎÊý: ÎÞ
+ * ·µ»ØÖµ£º
+ * Z_FOTA_SUCCESS ÉèÖóɹ¦
+ * Z_FOTA_FAIL ÉèÖÃʧ°Ü
+ * ×¢Òâ:
+ ********************************************************************************/
+int zxic_dual_config_package_path(char *upgrade_package_path, int length);
+
+
+#endif // ZXIC_FOTA_AB_UPGRADE_H
+
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/dma/zte/Makefile b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/dma/zte/Makefile
deleted file mode 100644
index 55a9fca..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/dma/zte/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-$(CONFIG_ARCH_ZX297520V3) += zx297520v3_dma.o
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/dma/zte/zx297520v3_dma.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/dma/zte/zx297520v3_dma.c
deleted file mode 100644
index 1753798..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/dma/zte/zx297520v3_dma.c
+++ /dev/null
@@ -1,1454 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2013, ZTE Corporation.
- *
- * File Name:dma.c
- * File Mark:
- * Description:
- * Others:
- * Version: 0.1
- * Author: limeifeng
- * Date:
- * modify
-
-
- ********************************************************************************/
-
-/****************************************************************************
-* Include files
-****************************************************************************/
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/dma-mapping.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <linux/ioport.h>
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/delay.h>
-#include <linux/kthread.h>
-
-#include <asm/cacheflush.h>
-#include <asm/io.h>
-#include "../dmaengine.h"
-#include <linux/soc/zte/common.h>
-#include <linux/soc/zte/spinlock.h>
-
-#include "zx297520v3_dma.h"
-
-//#pragma GCC optimize("O0")
-#define DMA_SUCCESS DMA_COMPLETE
-
-#define DMA_CHANNEL_CONFIG(peripheral_id, is_used , enable_mem2mem) {peripheral_id, is_used, enable_mem2mem}
-
-/*dma channel config define*/
-typedef struct
-{
- dma_peripheral_id peripheral_id; /* hw channel id */
- unsigned int is_used;
- unsigned int enable_mem2mem;
-#if 0
- void * data;
- dma_callback_func channel_callback;
-#endif
-}dma_channel_config;
-
-static dma_channel_config dma_chan_config[] =
-{
- DMA_CHANNEL_CONFIG(DMA_CH_UART0_TX, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_UART0_RX, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_UART1_TX, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_UART1_RX, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_SSP0_TX, false, false),
-
- DMA_CHANNEL_CONFIG(DMA_CH_SSP0_RX, false, true),
-#if 1 /* only ps core used */
- DMA_CHANNEL_CONFIG(DMA_CH_GPRS0, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_GPRS1, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_USIM, false, false),
-#endif
- DMA_CHANNEL_CONFIG(DMA_CH_I2S0_TX, false, false),
-
- DMA_CHANNEL_CONFIG(DMA_CH_I2S0_RX0, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_I2S1_TX, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_I2S1_RX0, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_SPIFC_TX, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_SPIFC_RX, false, false),
-
- DMA_CHANNEL_CONFIG(DMA_CH_SSP1_TX, false, true),
- DMA_CHANNEL_CONFIG(DMA_CH_SSP1_RX, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_UART2_TX, false, true),
- DMA_CHANNEL_CONFIG(DMA_CH_UART2_RX, false, true),
-
- DMA_CHANNEL_CONFIG(DMA_CH_EMBMS, false, false),
- #if 1 /* only ps core used */
- DMA_CHANNEL_CONFIG(DMA_CH_USIM1, false, false),
- #endif
- DMA_CHANNEL_CONFIG(DMA_CH_M2M_TX, false, true),
- DMA_CHANNEL_CONFIG(DMA_CH_M2M_RX, false, true),
-};
-
-/****************************************************************************
-* Local Macros
-****************************************************************************/
-#define BIT_SHIFT_L(value,BIT_NO) ((unsigned int)(value << (BIT_NO)))
-#define GET_HIGH_16BIT(val) (unsigned int)(val >> (16))
-#define GET_LOW_16BIT(val) (unsigned int)(val & (0xffff))
-#define DMA_CHANNEL(dmac,channel) (unsigned int)(dmac << (16)|(channel) )
-
-/*dma control reg bit */
-#define DMA_CTRL_ENABLE(value) BIT_SHIFT_L(value,0)
-#define DMA_CTRL_SOFT_B_REQ(value) BIT_SHIFT_L(value,1)
-#define DMA_CTRL_SRC_FIFO_MOD(value) BIT_SHIFT_L(value,2)
-#define DMA_CTRL_DEST_FIFO_MOD(value) BIT_SHIFT_L(value,3)
-#define DMA_CTRL_IRQ_MOD(value) BIT_SHIFT_L(value,4)
-#define DMA_CTRL_SRC_BURST_SIZE(value) BIT_SHIFT_L(value,6)
-#define DMA_CTRL_SRC_BURST_LENGTH(value) BIT_SHIFT_L(value,9)
-#define DMA_CTRL_DEST_BURST_SIZE(value) BIT_SHIFT_L(value,13)
-#define DMA_CTRL_DEST_BURST_LENGTH(value) BIT_SHIFT_L(value,16)
-#define DMA_CTRL_INTERRUPT_SEL(value) BIT_SHIFT_L(value,20)
-#define DMA_CTRL_FORCE_CLOSE(value) BIT_SHIFT_L(value,31)
-
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-
-/* Ò»¸öÁ´±íÖÐ×î´óµÄÁ´±íÏî¸öÊý */
-#define MAX_LLI_PARA_CNT (32)
-
-
-/* config dma reused */
-#define DMA_SEL_CFG_REG (get_socsys_base() + 0x120)
-
-#if defined(CONFIG_ARCH_ZX297520V2)
-#define DMA_SEL_UART2_I2S (1U << 0)
-#define DMA_SEL_UART1_HASH (1U << 1)
-#define DMA_SEL_I2S0_TDM (1U << 2)
-#define DMA_SEL_I2S1_TDM (1U << 3)
-#elif defined(CONFIG_ARCH_ZX297520V3)
-#define DMA_SEL_UART2TX_I2S0RX1 (1U << 0)
-#define DMA_SEL_UART2RX_I2S1RX1 (1U << 1)
-#define DMA_SEL_UART1RX_HASH (1U << 2)
-#define DMA_SEL_I2S0TX_TDMTX0 (1U << 3)
-#define DMA_SEL_I2S0RX0_TDMRX0 (1U << 4)
-#define DMA_SEL_I2S1TX_TDMTX1 (1U << 5)
-#define DMA_SEL_I2S1RX0_TDMRX1 (1U << 6)
-#endif
-
-typedef struct
-{
- volatile unsigned int src_addr;
- volatile unsigned int dest_addr;
- volatile unsigned int xpara;
- volatile unsigned int yzpara;
- volatile unsigned int src_yzstep;
- volatile unsigned int dest_yzstep;
- volatile unsigned int reserved0;
- volatile unsigned int link_addr;
- volatile unsigned int control;
-}dma_lli_param;
-
-#define MAX_LLI_PARAMS_CNT (sizeof(dma_lli_param)*MAX_LLI_PARA_CNT)
-static dma_lli_param *dma_lli_params[DMA_CH_NUM];
-static dma_addr_t dma_lli_phy_addr[DMA_CH_NUM];
-
-#define ZX29_DMA_TEST 0
-
-typedef struct
-{
- volatile unsigned short core_id; /* zte_coreid -- for debug */
- volatile unsigned short is_used;
-}dma_pub_config;
-
-static dma_pub_config *dma_pub_configs;
-
-#define ZX29_DMA_INT_SEL DMA_INT_TO_A9
-
-/****************************************************************************
-* Local Types
-****************************************************************************/
-static DEFINE_MUTEX(dma_mutex);
-
-struct zx29_dma_channel
-{
- dma_peripheral_id peripheral_id;
- struct zx29_dma * dma_device;
- struct dma_chan chan;
- struct dma_async_tx_descriptor desc;
- struct tasklet_struct tasklet;
- enum dma_status status;
- unsigned int cyclic;
- dma_peripheral_id req_peripheral_id;
-// dma_channel_def dma_chan_par;
- dma_cookie_t zx29_dma_cookie;
-};
-
-struct zx29_dma
-{
- struct dma_device dma;
- dma_regs __iomem * reg;
- dma_channel_config * chan_config;
- unsigned int channel_count;
- struct zx29_dma_channel dma_chan[DMA_CH_NUM];
-};
-/****************************************************************************
-* DMA trace
-****************************************************************************/
-/* #define ZX_TRACE_DMA */
-
-#ifdef ZX_TRACE_DMA
-/*#pragma GCC optimize("O0")*/
-
-extern unsigned int test_timer_read( void );
-
-#define TRACE_DMA_COUNT 1000
-
-typedef enum
-{
- DMA_DO_SUBMIT = 0,
- DMA_DO_START = 1,
- DMA_DO_ERR = 2,
- DMA_DO_SUCCESS = 3,
-}dma_behavior_t;
-
-typedef struct
-{
- dma_peripheral_id peripheral_id;
- dma_behavior_t behavior;
-}dma_trace_t;
-
-volatile dma_trace_t dma_trace_view[TRACE_DMA_COUNT+10];
-volatile unsigned int dma_trace_index = 0;
-
-#define dma_trace_index_inc() \
-do{ \
- dma_trace_index++;\
- if(dma_trace_index>=TRACE_DMA_COUNT)\
- dma_trace_index=0;\
-}while(0)
-
-static struct zx29_dma_channel *to_zx29_dma_chan(struct dma_chan *chan);
-static void dma_trace_submit(struct dma_async_tx_descriptor *tx)
-{
- struct zx29_dma_channel *dma_channel = to_zx29_dma_chan(tx->chan);
-
- dma_trace_view[dma_trace_index].peripheral_id = dma_channel->peripheral_id;
- dma_trace_view[dma_trace_index].behavior = DMA_DO_SUBMIT;
- dma_trace_index_inc();
-}
-
-static void dma_trace_pending(dma_peripheral_id peripheral_id)
-{
- dma_trace_view[dma_trace_index].peripheral_id = peripheral_id;
- dma_trace_view[dma_trace_index].behavior = DMA_DO_START;
- dma_trace_index_inc();
-}
-
-static void dma_trace_err(dma_peripheral_id peripheral_id)
-{
- dma_trace_view[dma_trace_index].peripheral_id = peripheral_id;
- dma_trace_view[dma_trace_index].behavior = DMA_DO_ERR;
- dma_trace_index_inc();
-}
-
-static void dma_trace_success(dma_peripheral_id peripheral_id)
-{
- dma_trace_view[dma_trace_index].peripheral_id = peripheral_id;
- dma_trace_view[dma_trace_index].behavior = DMA_DO_SUCCESS;
- dma_trace_index_inc();
-}
-#else
-static void dma_trace_submit(struct dma_async_tx_descriptor *tx){}
-static void dma_trace_pending(dma_peripheral_id peripheral_id){}
-static void dma_trace_err(dma_peripheral_id peripheral_id){}
-static void dma_trace_success(dma_peripheral_id peripheral_id){}
-#endif
-
-static struct zx29_dma dma_dev;
-
-unsigned int dma_err_num = 0;
-
-#if 0
-#define DMA_CHANNEL_CONFIG(peripheral_id, is_used , enable_mem2mem) {peripheral_id, is_used, enable_mem2mem}
-static dma_channel_config dma_chan_config[] =
-{
- DMA_CHANNEL_CONFIG(DMA_CH_UART0_TX, false, true),
- DMA_CHANNEL_CONFIG(DMA_CH_UART0_RX, false, true),
- DMA_CHANNEL_CONFIG(DMA_CH_UART1_TX, false, true),
- DMA_CHANNEL_CONFIG(DMA_CH_UART1_RX, false, true),
- DMA_CHANNEL_CONFIG(DMA_CH_SSP0_TX, false, true),
-
- DMA_CHANNEL_CONFIG(DMA_CH_SSP0_RX, false, true),
-#if 0 /* only ps core used */
- DMA_CHANNEL_CONFIG(DMA_CH_GPRS0, true, true),
- DMA_CHANNEL_CONFIG(DMA_CH_GPRS1, true, true),
- DMA_CHANNEL_CONFIG(DMA_CH_USIM, true, true),
-#endif
- DMA_CHANNEL_CONFIG(DMA_CH_I2S0_TX, false, false),
-
- DMA_CHANNEL_CONFIG(DMA_CH_I2S0_RX0, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_I2S1_TX, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_I2S1_RX0, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_SPIFC_TX, false, false),
- DMA_CHANNEL_CONFIG(DMA_CH_SPIFC_RX, false, false),
-
- DMA_CHANNEL_CONFIG(DMA_CH_SSP1_TX, false, true),
- DMA_CHANNEL_CONFIG(DMA_CH_SSP1_RX, false, true),
- DMA_CHANNEL_CONFIG(DMA_CH_UART2_TX, false, true),
- DMA_CHANNEL_CONFIG(DMA_CH_UART2_RX, false, true),
-
-#ifdef CONFIG_ARCH_ZX297520V2
-#else
- DMA_CHANNEL_CONFIG(DMA_CH_EMBMS, false, true),
- #if 0 /* only ps core used */
- DMA_CHANNEL_CONFIG(DMA_CH_USIM1, false, true),
- #endif
- DMA_CHANNEL_CONFIG(DMA_CH_M2M_TX, false, true),
- DMA_CHANNEL_CONFIG(DMA_CH_M2M_RX, false, true),
-#endif
-};
-
-#endif
-static unsigned short dma_chan_check_lock(dma_peripheral_id peripheral_id)
-{
- if((peripheral_id == DMA_CH_SPIFC_TX) || (peripheral_id == DMA_CH_SPIFC_RX))
- return false;
-
- return dma_pub_configs[peripheral_id].is_used;
-}
-
-static void dma_chan_lock(dma_peripheral_id peripheral_id)
-{
- if((peripheral_id == DMA_CH_SPIFC_TX) || (peripheral_id == DMA_CH_SPIFC_RX))
- return;
- dma_pub_configs[peripheral_id].core_id = 208 /*for cap CORE_ID_AP*/;
- dma_pub_configs[peripheral_id].is_used = true;
-}
-
-static void dma_chan_unlock(dma_peripheral_id peripheral_id)
-{
- if((peripheral_id == DMA_CH_SPIFC_TX) || (peripheral_id == DMA_CH_SPIFC_RX))
- return;
- dma_pub_configs[peripheral_id].core_id = CORE_ID_NUM;
- dma_pub_configs[peripheral_id].is_used = false;
-}
-
-/* some channel need config reuse register */
-static void dma_reuse_config(dma_peripheral_id peripheral_id)
-{
- switch(peripheral_id)
- {
-#if defined(CONFIG_ARCH_ZX297520V2)
- case DMA_CH_UART2_TX:
- case DMA_CH_UART2_RX:
- zx_clr_reg(DMA_SEL_CFG_REG, DMA_SEL_UART2_I2S);
- break;
-
- case DMA_CH_I2S0_RX1:
- case DMA_CH_I2S1_RX1:
- zx_set_reg(DMA_SEL_CFG_REG, DMA_SEL_UART2_I2S);
- break;
-
- case DMA_CH_UART1_RX:
- zx_clr_reg(DMA_SEL_CFG_REG, DMA_SEL_UART1_HASH);
- break;
-
- case DMA_CH_HASH_RX:
- zx_set_reg(DMA_SEL_CFG_REG, DMA_SEL_UART1_HASH);
- break;
-
- case DMA_CH_I2S0_TX:
- case DMA_CH_I2S0_RX0:
- zx_clr_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S0_TDM);
- break;
-
- case DMA_CH_TDM_TX0:
- case DMA_CH_TDM_RX0:
- zx_set_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S0_TDM);
- break;
-
- case DMA_CH_I2S1_TX:
- case DMA_CH_I2S1_RX0:
- zx_clr_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S1_TDM);
- break;
-
- case DMA_CH_TDM_TX1:
- case DMA_CH_TDM_RX1:
- zx_set_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S1_TDM);
- break;
-
-#elif defined(CONFIG_ARCH_ZX297520V3)
- case DMA_CH_UART1_RX:
- zx_clr_reg(DMA_SEL_CFG_REG, DMA_SEL_UART1RX_HASH);
- break;
- case DMA_CH_I2S0_TX:
- zx_clr_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S0TX_TDMTX0);
- break;
- case DMA_CH_I2S0_RX0:
- zx_clr_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S0RX0_TDMRX0);
- break;
- case DMA_CH_I2S1_TX:
- zx_clr_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S1TX_TDMTX1);
- break;
- case DMA_CH_I2S1_RX0:
- zx_clr_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S1RX0_TDMRX1);
- break;
- case DMA_CH_UART2_TX:
- zx_clr_reg(DMA_SEL_CFG_REG, DMA_SEL_UART2TX_I2S0RX1);
- break;
- case DMA_CH_UART2_RX:
- zx_clr_reg(DMA_SEL_CFG_REG, DMA_SEL_UART2RX_I2S1RX1);
- break;
- case DMA_CH_HASH_RX:
- zx_set_reg(DMA_SEL_CFG_REG, DMA_SEL_UART1RX_HASH);
- break;
- case DMA_CH_TDM_TX0:
- zx_set_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S0TX_TDMTX0);
- break;
- case DMA_CH_TDM_RX0:
- zx_set_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S0RX0_TDMRX0);
- break;
- case DMA_CH_TDM_TX1:
- zx_set_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S1TX_TDMTX1);
- break;
- case DMA_CH_TDM_RX1:
- zx_set_reg(DMA_SEL_CFG_REG, DMA_SEL_I2S1RX0_TDMRX1);
- break;
- case DMA_CH_I2S0_RX1:
- zx_set_reg(DMA_SEL_CFG_REG, DMA_SEL_UART2TX_I2S0RX1);
- break;
- case DMA_CH_I2S1_RX1:
- zx_set_reg(DMA_SEL_CFG_REG, DMA_SEL_UART2RX_I2S1RX1);
- break;
-#endif
-
- default:
- break;
- }
-}
-
-static dma_peripheral_id get_real_peri_id(dma_peripheral_id peripheral_id)
-{
- if(peripheral_id < DMA_CH_NUM)
- return peripheral_id;
-
- switch(peripheral_id)
- {
- case DMA_CH_HASH_RX:
- return DMA_CH_UART1_RX;
- case DMA_CH_TDM_TX0:
- return DMA_CH_I2S0_TX;
- case DMA_CH_TDM_RX0:
- return DMA_CH_I2S0_RX0;
- case DMA_CH_TDM_TX1:
- return DMA_CH_I2S1_TX;
- case DMA_CH_TDM_RX1:
- return DMA_CH_I2S1_RX0;
- case DMA_CH_I2S0_RX1:
- return DMA_CH_UART2_TX;
- case DMA_CH_I2S1_RX1:
- return DMA_CH_UART2_RX;
- default:
- return 0xff;
- }
-}
-
-static unsigned int get_channel_id(dma_peripheral_id peripheral_id)
-{
- int i;
- dma_channel_config *chan_config = dma_dev.chan_config;
- dma_peripheral_id real_peripheral_id = 0xff;
-
- real_peripheral_id = get_real_peri_id(peripheral_id);
-
- for(i=0; i<dma_dev.channel_count; i++)
- {
- if ( (chan_config[i].peripheral_id==real_peripheral_id))
- return i;
- }
-
- return 0xff;
-}
-
-static void dma_sync_lli_for_cpu(unsigned int channel_id)
-{
- dma_sync_single_for_cpu(dma_dev.dma.dev, dma_lli_phy_addr[channel_id], MAX_LLI_PARAMS_CNT, DMA_BIDIRECTIONAL);
-}
-
-static void dma_sync_lli_for_device(unsigned int channel_id)
-{
- dma_sync_single_for_device(dma_dev.dma.dev, dma_lli_phy_addr[channel_id], MAX_LLI_PARAMS_CNT, DMA_BIDIRECTIONAL);
-}
-
-static signed int dma_find_chan(dma_peripheral_id channel_id);
-static signed int dma_reset_chan(struct zx29_dma_channel *channel);
-
-static void dma_tasklet(unsigned long data)
-{
- struct zx29_dma_channel *chan = (struct zx29_dma_channel *)data;
-
- if (chan->desc.callback)
- chan->desc.callback(chan->desc.callback_param);
-}
-
-static struct zx29_dma_channel *to_zx29_dma_chan(struct dma_chan *chan)
-{
- return container_of(chan, struct zx29_dma_channel, chan);
-}
-
-static signed int dma_disable_chan(struct zx29_dma_channel *chan)
-{
- dma_chan_reg __iomem* chan_reg_ptr=NULL;
-
- if (chan->peripheral_id >= DMA_CH_NUM)
- {
- return -EINVAL;
- }
-
- chan_reg_ptr= &(dma_dev.reg->channel[chan->peripheral_id]);
- chan_reg_ptr->control |= DMA_CTRL_FORCE_CLOSE(1);
-
- return 0;
-}
-
-/*reset channel para*/
-static signed int dma_reset_chan(struct zx29_dma_channel *chan)
-{
- unsigned int peripheral_id;
- unsigned int channel_id;
- dma_regs __iomem* pReg;
- dma_chan_reg __iomem* chan_reg_ptr;
-
- if (!chan) {
- return -EINVAL;
- }
-
- peripheral_id = (unsigned int)chan->peripheral_id;
- if (peripheral_id >= DMA_CH_NUM) {
- return -EINVAL;
- }
-
- channel_id = get_channel_id(chan->peripheral_id);
- if(channel_id == 0xff)
- return -EINVAL;
-
- pReg= dma_dev.reg;
- chan_reg_ptr= &(pReg->channel[peripheral_id]);
-
- /*force close current channel*/
- chan_reg_ptr->control |= DMA_CTRL_FORCE_CLOSE(1);
-
- //memset((void*) chan_reg_ptr,0,sizeof(dma_chan_reg));
- pReg->raw_int_tc_status |= BIT_SHIFT_L(0x1,peripheral_id);
- pReg->raw_int_src_err_status |= BIT_SHIFT_L(0x1,peripheral_id);
- pReg->raw_int_dest_err_status |= BIT_SHIFT_L(0x1,peripheral_id);
- pReg->raw_int_cfg_err_status |= BIT_SHIFT_L(0x1,peripheral_id);
- memset((void*) chan_reg_ptr,0,sizeof(dma_chan_reg));
- //dma_dev[dmac_id].chan_config[channel_id].channelCbk = NULL;
- //dma_dev[dmac_id].chan_config[channel_id].data = NULL;
- chan->status = DMA_SUCCESS;
- chan->cyclic = 0;
- dma_dev.chan_config[channel_id].is_used = false;
- dma_chan_unlock(dma_dev.chan_config[channel_id].peripheral_id);
-
- return 0;
-}
-
-/*find the fixed free channel for peripheralID*/
-static signed int dma_find_chan(dma_peripheral_id peripheral_id)
-{
- unsigned int channel_id = 0xff;
- dma_channel_config *chan_config = dma_dev.chan_config;
-
-#if 0/*move to zx29_dma_filter_fn*/
- /*in case there is free channel,allocate it to M2M*/
- if (DMA_CH_MEMORY==peripheral_id)
- {
- for(i=0; i<dma_dev.channel_count; i++)
- {
- if((chan_config[i].is_used==false) && \
- (dma_chan_check_lock(chan_config[i].peripheral_id)==false) && \
- (chan_config[i].enable_mem2mem==true))
- {
- chan_config[i].is_used = true;
- dma_chan_lock(chan_config[i].peripheral_id);
- return i;
- }
- }
- return -EAGAIN;
- }
-#endif
-
- channel_id = get_channel_id(peripheral_id);
- if(channel_id==0xff)
- return -EAGAIN;
-
- reg_spin_lock();
- /*if channle has been used,return error*/
- if((chan_config[channel_id].is_used==true) || \
- (dma_chan_check_lock(chan_config[channel_id].peripheral_id)==true))
- {
- reg_spin_unlock();
- return -EAGAIN;
- }
-
- /*get the channel number*/
- chan_config[channel_id].is_used =true;
- dma_chan_lock(chan_config[channel_id].peripheral_id);
- reg_spin_unlock();
-
- /* channel reuse*/
- dma_reuse_config(peripheral_id);
-
- return channel_id;
-}
-
-static u32 dma_get_residue(struct zx29_dma_channel *chan)
-{
- dma_regs __iomem* pReg = NULL;
- dma_chan_reg __iomem* chan_reg_ptr = NULL;
-
- pReg= dma_dev.reg;
- chan_reg_ptr= &(pReg->channel[chan->peripheral_id]);
-
- return chan_reg_ptr->xpara;
-}
-
-static enum dma_status zx29_dma_tx_status(struct dma_chan *chan,
- dma_cookie_t cookie, struct dma_tx_state *txstate)
-{
- struct zx29_dma_channel *zx29_chan = to_zx29_dma_chan(chan);
- dma_cookie_t last_used;
- u32 bytes;
-
- bytes = dma_get_residue(zx29_chan);
- last_used = chan->cookie;
- dma_set_tx_state(txstate, chan->completed_cookie, last_used, bytes);
-
- return zx29_chan->status;
-}
-
-static unsigned int parse_dma_req(dma_transfer_mode trans_mode)
-{
- unsigned int control = 0;
-
- switch(trans_mode)
- {
- case TRAN_PERI_TO_PERI:
- control = DMA_CTRL_SOFT_B_REQ(DMA_PERIPHERAL_REQ)\
- | DMA_CTRL_SRC_FIFO_MOD(DMA_ADDRMOD_FIFO) \
- | DMA_CTRL_DEST_FIFO_MOD(DMA_ADDRMOD_FIFO);
- break;
-
- case TRAN_PERI_TO_MEM:
- control = DMA_CTRL_SOFT_B_REQ(DMA_PERIPHERAL_REQ)\
- | DMA_CTRL_SRC_FIFO_MOD(DMA_ADDRMOD_FIFO) \
- | DMA_CTRL_DEST_FIFO_MOD(DMA_ADDRMOD_RAM);
- break;
-
- case TRAN_MEM_TO_PERI:
- control = DMA_CTRL_SOFT_B_REQ(DMA_PERIPHERAL_REQ)\
- | DMA_CTRL_SRC_FIFO_MOD(DMA_ADDRMOD_RAM) \
- | DMA_CTRL_DEST_FIFO_MOD(DMA_ADDRMOD_FIFO);
- break;
-
- case TRAN_MEM_TO_MEM:
- default:
- control = DMA_CTRL_SOFT_B_REQ(DMA_SOFT_REQ)\
- | DMA_CTRL_SRC_FIFO_MOD(DMA_ADDRMOD_RAM) \
- | DMA_CTRL_DEST_FIFO_MOD(DMA_ADDRMOD_RAM);
- break;
- }
-
- return control;
-}
-
-static signed int dma_set_chan_para(unsigned int channel)//,dma_channel_def * chan_para)
-{
- volatile dma_chan_reg __iomem* chan_reg = &(dma_dev.reg->channel[channel]);
- unsigned int channel_id = get_channel_id(channel);
- dma_lli_param *temp_dma_lli_params = NULL;
-
- if(channel_id>= DMA_CH_NUM)
- return -EAGAIN;
-
- temp_dma_lli_params = dma_lli_params[channel_id];
-
-/* chan_reg->src_addr = chan_para->src_addr;
- chan_reg->dest_addr = chan_para->dest_addr;
- chan_reg->xpara = chan_para->count;
- chan_reg->link_addr = chan_para->link_addr;
-
- if(chan_para->link_addr)
- chan_reg->link_addr = dma_lli_phy_addr[get_channel_id(channel)];
-
- chan_reg->control = parse_dma_req(chan_para->dma_control.tran_mode)\
- | DMA_CTRL_SRC_BURST_SIZE(chan_para->dma_control.src_burst_size) \
- | DMA_CTRL_SRC_BURST_LENGTH((chan_para->dma_control.src_burst_len )) \
- | DMA_CTRL_DEST_BURST_SIZE(chan_para->dma_control.dest_burst_size) \
- | DMA_CTRL_DEST_BURST_LENGTH((chan_para->dma_control.dest_burst_len ))\
- | DMA_CTRL_INTERRUPT_SEL(DMA_INT_TO_PS) ;
-
- if(chan_para->dma_control.irq_mode)
- {
- if(chan_para->link_addr)
- chan_reg->control |= DMA_CTRL_IRQ_MOD(DMA_ERR_IRQ_ENABLE);
- else
- chan_reg->control |= DMA_CTRL_IRQ_MOD(DMA_ALL_IRQ_ENABLE);
- }*/
-
- chan_reg->src_addr = temp_dma_lli_params[0].src_addr;
- chan_reg->dest_addr = temp_dma_lli_params[0].dest_addr;
- chan_reg->xpara = temp_dma_lli_params[0].xpara;
- chan_reg->link_addr = temp_dma_lli_params[0].link_addr;
- chan_reg->control = temp_dma_lli_params[0].control &
- (~(DMA_CTRL_ENABLE(DMA_ENABLE)));
-
- return 0;
-}
-
-/*allocate a channel for peripheralID,
-and return the channel number.if failed return -EAGAIN
-*/
-signed int zx29_dma_request(dma_peripheral_id peripheral_id)
-{
- signed int errCode = -EAGAIN;
-
- mutex_lock(&dma_mutex);
- errCode=dma_find_chan(peripheral_id);
- mutex_unlock(&dma_mutex);
-
- return errCode;
-}
-
-static void dma_config_lli(unsigned int channel_id, dma_channel_def *chan_para)
-{
- int i = 0;
- dma_lli_param *temp_dma_lli_params = dma_lli_params[channel_id];
-
- dma_sync_lli_for_cpu(channel_id);
- do{
- temp_dma_lli_params[i].src_addr = chan_para[i].src_addr;
- temp_dma_lli_params[i].dest_addr = chan_para[i].dest_addr;
- temp_dma_lli_params[i].xpara = chan_para[i].count;
- temp_dma_lli_params[i].yzpara = chan_para[i].ycount | (chan_para[i].zcount << 16);
- temp_dma_lli_params[i].src_yzstep = chan_para[i].src_ystep | (chan_para[i].src_zstep << 16);
- temp_dma_lli_params[i].dest_yzstep = chan_para[i].dest_ystep | (chan_para[i].dest_zstep << 16);
- temp_dma_lli_params[i].control = parse_dma_req(chan_para[i].dma_control.tran_mode)\
- | DMA_CTRL_SRC_BURST_SIZE(chan_para[i].dma_control.src_burst_size) \
- | DMA_CTRL_SRC_BURST_LENGTH((chan_para[i].dma_control.src_burst_len )) \
- | DMA_CTRL_DEST_BURST_SIZE(chan_para[i].dma_control.dest_burst_size) \
- | DMA_CTRL_DEST_BURST_LENGTH((chan_para[i].dma_control.dest_burst_len ))\
- | DMA_CTRL_INTERRUPT_SEL(ZX29_DMA_INT_SEL)\
- | DMA_CTRL_ENABLE(DMA_ENABLE);
-
- if(chan_para[i].dma_control.irq_mode > DMA_ALL_IRQ_DISABLE)
- temp_dma_lli_params[i].control |= DMA_CTRL_IRQ_MOD(DMA_ERR_IRQ_ENABLE);
-
- if(chan_para[i].link_addr > 0)
- temp_dma_lli_params[i].link_addr = dma_lli_phy_addr[channel_id] + sizeof(dma_lli_param)*(i+1);
- else
- {
- if(chan_para[i].dma_control.irq_mode > DMA_ALL_IRQ_DISABLE)
- temp_dma_lli_params[i].control |= DMA_CTRL_IRQ_MOD(DMA_ALL_IRQ_ENABLE);
-
- temp_dma_lli_params[i].link_addr = 0;
- }
-
-// i++;
- }while(chan_para[i++].link_addr);
-
- dma_sync_lli_for_device(channel_id);
-}
-
-signed int zx29_dma_config(struct dma_chan *chan,
- struct dma_slave_config *cfg)
-{
- struct zx29_dma_channel *dma_channel;
- dma_peripheral_id peripheral_id;
- unsigned int channel_id;
- dma_channel_def *chan_para;
-
- if (!cfg || !chan)
- return -EINVAL;
-
- dma_channel = to_zx29_dma_chan(chan);
- peripheral_id = dma_channel->peripheral_id;
-
- channel_id = get_channel_id(peripheral_id);
-
- if(dma_dev.chan_config[channel_id].is_used == false)
- return -EINVAL;
-
- chan_para = (dma_channel_def *)cfg;
- if (chan_para->dma_control.tran_mode>=DMA_TRAN_MOD_ALL\
- ||chan_para->dma_control.irq_mode>=DMA_IRQMOD_ALL\
- ||chan_para->dma_control.src_burst_size>=DMA_BURST_SIZE_ALL\
- ||chan_para->dma_control.src_burst_len>=DMA_BURST_LEN_ALL\
- ||chan_para->dma_control.dest_burst_size>=DMA_BURST_SIZE_ALL\
- ||chan_para->dma_control.dest_burst_len>=DMA_BURST_LEN_ALL)
- {
- return -EINVAL;
- }
-
- /* config lli */
- dma_config_lli(channel_id, chan_para);
-
- /* config regs */
-#if 0
- dma_dev.chan_config[channel_id].channel_callback = chan_para->callback;
- dma_dev.chan_config[channel_id].data = chan_para->data;
-#endif
-
- return 0;//dma_set_chan_para((unsigned int)peripheral_id, chan_para);
-}
-
-signed int zx29_dma_start(unsigned int channel_id)
-{
- volatile dma_regs __iomem * pReg = dma_dev.reg;
-
- if(channel_id >= DMA_CH_NUM)
- {
- BUG();
- return -EINVAL;
- }
-
- dsb();
-
- pReg->channel[channel_id].control |= DMA_CTRL_ENABLE(DMA_ENABLE);
-
- return 0;
-}
-
-signed int zx29_dma_stop(unsigned int channel_id)
-{
- volatile dma_regs __iomem * pReg = dma_dev.reg;
-
- if(channel_id >= DMA_CH_NUM)
- return -EINVAL;
-
- //pReg->channel[channel_id].control &= ~(DMA_CTRL_ENABLE(DMA_ENABLE));
- pReg->channel[channel_id].control |= DMA_CTRL_FORCE_CLOSE(1);//change by gsn for linuxDMA
- return 0;
-}
-signed int zx29_dma_get_transfer_num(unsigned int channel_id)
-{
- volatile dma_regs __iomem * pReg = dma_dev.reg;
- if(channel_id >= DMA_CH_NUM)
- return -EINVAL;
- return (pReg->channel[channel_id].xpara);
-}
-
-signed int zx29_dma_set_priority(dma_group_order groupOrder, dma_group_mode groupMode)
-{
- if(groupOrder >= DMA_GROUP_ALL ||groupMode >= DMA_MODE_ALL)
- return -EINVAL;
-
- dma_dev.reg->group_order = groupOrder;
- dma_dev.reg->arbit_mode = groupMode;
-
- return 0;
-}
-
-static dma_cookie_t zx29_dma_tx_submit(struct dma_async_tx_descriptor *tx)
-{
- dma_trace_submit(tx);
-
- return dma_cookie_assign(tx);
-}
-
-static int zx29_dma_alloc_chan_resources(struct dma_chan *chan)
-{
- int ret = 0;
- struct zx29_dma_channel *dma_channel = to_zx29_dma_chan(chan);
-
- ret = zx29_dma_request(dma_channel->req_peripheral_id);
- if(ret < 0)
- return ret;
-
- dma_async_tx_descriptor_init(&dma_channel->desc, chan);
- dma_channel->desc.tx_submit = zx29_dma_tx_submit;
-
- /* the descriptor is ready */
- async_tx_ack(&dma_channel->desc);
-
- return ret;
-}
-
-void zx29_dma_free_chan_resource(struct dma_chan *chan)
-{
- struct zx29_dma_channel *dma_channel = to_zx29_dma_chan(chan);
- dma_reset_chan(dma_channel);
-}
-
-static struct dma_async_tx_descriptor *zx29_prep_dma_cyclic(
- struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
- size_t period_len, enum dma_transfer_direction direction,
- unsigned long context)
-{
- struct zx29_dma_channel *dma_channel = to_zx29_dma_chan(chan);
- struct dma_async_tx_descriptor *desc = &dma_channel->desc;
- unsigned int channel_id = get_channel_id(dma_channel->peripheral_id);
- int num_periods = buf_len / period_len;
- int i = 0;
- dma_lli_param *temp_dma_lli_params;
-
- if (channel_id >= DMA_CH_NUM)
- return NULL;
-// change by gsn for linuxDMA
- //if(dma_channel->status == DMA_IN_PROGRESS)
- //return NULL;
- dma_channel->status = DMA_IN_PROGRESS;
-
- temp_dma_lli_params = dma_lli_params[channel_id];
-
- dma_sync_lli_for_cpu(channel_id);
- for (i = 0; i < num_periods; i++)
- {
- temp_dma_lli_params[i].control |= DMA_CTRL_IRQ_MOD(DMA_ALL_IRQ_ENABLE);
- }
- temp_dma_lli_params[num_periods - 1].link_addr = dma_lli_phy_addr[channel_id];
- dma_sync_lli_for_device(channel_id);
-
- dma_channel->cyclic = 1;
-
- desc->callback = NULL;
- desc->callback_param = NULL;
-
- dma_set_chan_para(dma_channel->peripheral_id);
-
- return desc;
-}
-
-static struct dma_async_tx_descriptor *zx29_prep_dma_interleaved(
- struct dma_chan *chan,
- struct dma_interleaved_template *xt,
- unsigned long flags)
-{
- struct zx29_dma_channel *dma_channel = to_zx29_dma_chan(chan);
- struct dma_async_tx_descriptor *desc = &dma_channel->desc;
-
-// change by gsn for linuxDMA
- //if(dma_channel->status == DMA_IN_PROGRESS)
- //return NULL;
- dma_channel->status = DMA_IN_PROGRESS;
-
- desc->callback = NULL;
- desc->callback_param = NULL;
-
- dma_set_chan_para(dma_channel->peripheral_id);
-
- return desc;
-}
-
-static int zx29_dma_terminate_all(struct dma_chan *chan)
-{
- struct zx29_dma_channel *dma_channel = to_zx29_dma_chan(chan);
-
- return dma_disable_chan(dma_channel);
-}
-
-static void zx29_dma_issue_pending(struct dma_chan *chan)
-{
- struct zx29_dma_channel *dma_channel = to_zx29_dma_chan(chan);
-
- dma_trace_pending(dma_channel->peripheral_id);
-
- zx29_dma_start(dma_channel->peripheral_id);
-}
-
-unsigned int zx29_dma_get_status(void)
-{
- volatile dma_regs __iomem * pReg = dma_dev.reg;
-
- return pReg->working_status;
-}
-
-bool zx29_dma_filter_fn(struct dma_chan *chan, void *param)
-{
- struct zx29_dma_channel * channel = to_zx29_dma_chan(chan);
- unsigned int channel_id = 0;
- dma_peripheral_id peri_id = 0;
-
- peri_id = get_real_peri_id((dma_peripheral_id)param);
- if(peri_id >= DMA_CH_NUM)
- return false;
-
- channel_id = get_channel_id(channel->peripheral_id);
- if(channel_id == 0xff)
- return false;
-
- if(peri_id == DMA_CH_MEMORY)
- {
-
- if ((dma_dev.chan_config[channel_id].is_used == false)&& \
- (dma_chan_check_lock(dma_dev.chan_config[channel_id].peripheral_id)==false)&& \
- (dma_dev.chan_config[channel_id].enable_mem2mem==true))
- {
- channel->req_peripheral_id = channel->peripheral_id;
- return true;
- }
- else
- return false;
- }
-
- if (channel->peripheral_id != peri_id)
- return false;
-
- if ((dma_dev.chan_config[channel_id].is_used == false)&& \
- (dma_chan_check_lock(dma_dev.chan_config[channel_id].peripheral_id)==false))
- {
- channel->req_peripheral_id = (dma_peripheral_id)param;
- return true;
- }
- else
- return false;
-}
-EXPORT_SYMBOL(zx29_dma_filter_fn);
-
-irqreturn_t dma_Isr(int irq, void *dev)
-{
- unsigned int need_continue = 0;
- unsigned int i;
- struct zx29_dma *dmac_ptr = dev;
- dma_regs __iomem * dma_reg=dmac_ptr->reg;
- volatile unsigned int control;
- volatile unsigned int raw_tc_int = dma_reg->raw_int_tc_status;
- volatile unsigned int raw_src_err_int = dma_reg->raw_int_src_err_status;
- volatile unsigned int raw_dest_err_int = dma_reg->raw_int_dest_err_status;
- volatile unsigned int raw_cfg_err_int = dma_reg->raw_int_cfg_err_status;
- volatile unsigned int tc_int = dma_reg->int_tc_status;
-
- unsigned int channel_id;
-
- /* error */
- if (raw_src_err_int!=0 || raw_dest_err_int!=0 || raw_cfg_err_int!=0)
- {
- for (i=0; i<DMA_CH_NUM; i++)
- {
- if ((raw_src_err_int|raw_dest_err_int|raw_cfg_err_int)&(0x01<<i))
- {
- channel_id = get_channel_id(i);
- if(channel_id >= DMA_CH_NUM)
- continue;
-
- dmac_ptr->dma_chan[channel_id].status = DMA_ERROR;
- dma_trace_err(i);
- }
- }
-
- BUG();
-
-/* dma_reg->raw_int_src_err_status |= raw_src_err_int ;
- dma_reg->raw_int_dest_err_status |= raw_dest_err_int ;
- dma_reg->raw_int_cfg_err_status |= raw_cfg_err_int ;
-
- return IRQ_HANDLED;*/
- }
-
-
- do
- {
- need_continue = 0;
-
- tc_int = dma_reg->int_tc_status;
- raw_tc_int = dma_reg->raw_int_tc_status;
-
- for (i = 0;(i< DMA_CH_NUM)&&(raw_tc_int!=0); i++)
- {
- if (raw_tc_int&(0x01<<i))
- {
- control = dma_reg->channel[i].control;
- channel_id = get_channel_id(i);
- /*dma_reg->raw_int_tc_status = (0x1<<i);*//*clear here may create error clear*/
-
- if(channel_id >= DMA_CH_NUM)
- continue;
-
- if(((control&DMA_CTRL_INTERRUPT_SEL(0xf))==DMA_CTRL_INTERRUPT_SEL(ZX29_DMA_INT_SEL))&&\
- (control&DMA_CTRL_IRQ_MOD(1))&&\
- ( ((control&DMA_CTRL_ENABLE(1)) == 0) || ((dmac_ptr->dma_chan[channel_id].cyclic)&&(tc_int&(0x1<<i))) ) )
- {
- dma_reg->raw_int_tc_status = (0x1<<i);
- need_continue = 1;
- dma_trace_success(i);
-
- //channel_id = get_channel_id(i);
- dmac_ptr->dma_chan[channel_id].status = DMA_SUCCESS;
- if(dmac_ptr->dma_chan[channel_id].cyclic == 0)
- {
- dma_cookie_complete(&dmac_ptr->dma_chan[channel_id].desc);
- }
-#ifdef CONFIG_PREEMPT_RT_FULL
- if (dmac_ptr->dma_chan[channel_id].desc.callback)
- dmac_ptr->dma_chan[channel_id].desc.callback(dmac_ptr->dma_chan[channel_id].desc.callback_param);
-#else
- /* schedule tasklet on this channel */
- tasklet_schedule(&dmac_ptr->dma_chan[channel_id].tasklet);
-#endif
- }
- }
- }
- }while(need_continue);
-
- return IRQ_HANDLED;
-}
-
-#if ZX29_DMA_TEST
-
-#define DMA_LLI_TEST 0
-
-#if DMA_LLI_TEST
-#define MEM_CPY_CNT (3)
-#else
-#define MEM_CPY_CNT (1)
-#endif
-
-#define MEM_TEST_COUNT (0x200)
-
-static unsigned int dma_int_count = 0;
-static unsigned char * test_buffer = NULL;
-static dma_addr_t test_phy_addr;
-static struct dma_chan * test_chan = NULL;
-
-void dma_cb(struct zx29_dma_channel * chan)
-{
- int i;
-
-// dma_sync_single_for_cpu(dma_dev.dma.dev, test_phy_addr, MEM_TEST_COUNT*2, DMA_BIDIRECTIONAL);
- dma_unmap_single(dma_dev.dma.dev, test_phy_addr, MEM_TEST_COUNT*2*MEM_CPY_CNT, DMA_BIDIRECTIONAL);
-
- for(i=0; i<MEM_CPY_CNT; i++)
- {
- if(memcmp(test_buffer+MEM_TEST_COUNT*2*i,
- test_buffer+MEM_TEST_COUNT+MEM_TEST_COUNT*2*i,
- MEM_TEST_COUNT))
- {
- pr_info("[DMA] m2m test copy failed(%d). \n", i+1);
- }
- }
-
- kfree(test_buffer);
- if (test_chan)
- dma_release_channel(test_chan);
-
- pr_info("[DMA] m2m test copy succeeded (%d). \n", ++dma_int_count);
-
-}
-
-static void *test_prepare_buff(size_t size)
-{
- int i;
-
- /* alloc buffer */
- test_buffer = kzalloc(size, GFP_KERNEL);
- if (!test_buffer) {
- dev_err(dma_dev.dma.dev, "%s: could not alloc DMA memory\n",
- __func__);
- BUG();
- }
- pr_info("[DMA] m2m test alloc buffer (%x). \n", (unsigned int)test_buffer);
-
- /* prepare data */
- for(i=0; i<MEM_CPY_CNT; i++)
- memset(test_buffer+MEM_TEST_COUNT*2*i, 0x11+0x11*i, MEM_TEST_COUNT);
-
- return test_buffer;
-}
-
-static struct dma_chan *test_alloc_channel(void)
-{
- dma_cap_mask_t mask;
-
- dma_cap_zero(mask);
- dma_cap_set(DMA_SLAVE, mask);
-
- return dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_MEMORY);
-}
-
-static signed int test_dma_config(struct dma_chan *chan, dma_addr_t phy_addr)
-{
- dma_channel_def temp[MEM_CPY_CNT];
- int i;
-
- memset(temp, 0, sizeof(temp));
- for(i=0; i<MEM_CPY_CNT; i++)
- {
- temp[i].src_addr = phy_addr + MEM_TEST_COUNT*2*i;
- temp[i].dest_addr = temp[i].src_addr + MEM_TEST_COUNT;
- temp[i].count = MEM_TEST_COUNT;
-// temp[i].callback = (dma_callback_func)dma_cb;
-
- temp[i].dma_control.tran_mode = TRAN_MEM_TO_MEM;
- temp[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
- temp[i].dma_control.src_burst_len = DMA_BURST_LEN_16;
- temp[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
- temp[i].dma_control.dest_burst_len = DMA_BURST_LEN_16;
- temp[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
-
- temp[i].link_addr = 1;
- }
- temp[MEM_CPY_CNT-1].link_addr = 0;
-
- return dmaengine_slave_config(chan,(struct dma_slave_config*)&temp);
-}
-
-
-//static
-void dma_m2m_test(struct device *dev)
-{
- struct dma_async_tx_descriptor *desc =NULL;
- struct zx29_dma_channel * zx29_chan = NULL;
- unsigned char *p = NULL;
- int ret = 0;
-
- p = test_prepare_buff(MEM_TEST_COUNT*2*MEM_CPY_CNT);
-
- /* alloc dma channel */
- test_chan = test_alloc_channel();
- if (!test_chan)
- {
- pr_info("[DMA]test request channel failed \n");
- return;
- }
-
- /* map dma address */
- test_phy_addr = dma_map_single(dma_dev.dma.dev, (void *)p, MEM_TEST_COUNT*2*MEM_CPY_CNT, DMA_BIDIRECTIONAL);
- if (dma_mapping_error(dma_dev.dma.dev, test_phy_addr)) {
- dev_err(dma_dev.dma.dev, "Failed to dma_map_single\n");
- BUG();
- }
-
- /* config dma */
- ret = test_dma_config(test_chan, test_phy_addr);
- if(ret < 0)
- printk("dmaengine_slave_config failed(%d)~~~~~~", ret);
-
- /* start transfer */
- zx29_chan = to_zx29_dma_chan(test_chan);
-#if 0
- desc = zx29_chan->dma_device->dma.device_prep_interleaved_dma(test_chan,NULL,0);
- desc->callback = (dma_async_tx_callback)dma_cb;
- desc->callback_param = (void *) zx29_chan;
-#else
- desc = test_chan->device->device_prep_interleaved_dma(test_chan,NULL,0);
- desc->callback = (dma_async_tx_callback)dma_cb;
- desc->callback_param = (void *) zx29_chan;
-#endif
- zx29_chan->zx29_dma_cookie = dmaengine_submit(desc);
- dma_async_issue_pending(test_chan);
-
- return ;
-}
-
-
-static ssize_t dma_m2m_show(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- return sprintf(buf, "dma_int_count:%d\n", dma_int_count);
-}
-
-static ssize_t dma_m2m_store(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t count)
-{
- dma_m2m_test(dev);
-
- return (count);
-}
-
-static DEVICE_ATTR(dma,0600,dma_m2m_show,dma_m2m_store);
-static struct attribute *zx29_dma_attributes[] = {
- &dev_attr_dma.attr,
- NULL,
-};
-
-static const struct attribute_group zx29_dma_attribute_group = {
- .attrs = (struct attribute **) zx29_dma_attributes,
-};
-#endif
-
-static void dma_init_channels(void)
-{
- int i = 0;
- struct zx29_dma_channel * dma_chan_ptr = NULL;
-
- dma_dev.chan_config = dma_chan_config;
- dma_dev.channel_count = ARRAY_SIZE(dma_chan_config);
-
- INIT_LIST_HEAD(&dma_dev.dma.channels);
-
- for(i=0;i<dma_dev.channel_count;i++)
- {
- dma_chan_ptr = &dma_dev.dma_chan[i];
- dma_chan_ptr->peripheral_id = dma_dev.chan_config[i].peripheral_id;
- dma_chan_ptr->dma_device = &(dma_dev);
- dma_chan_ptr->chan.device = &(dma_dev.dma);
- dma_cookie_init(&dma_chan_ptr->chan);
-
- tasklet_init(&dma_chan_ptr->tasklet, dma_tasklet, (unsigned long)(dma_chan_ptr));
-
- list_add_tail(&dma_chan_ptr->chan.device_node, &dma_dev.dma.channels);
- }
-}
-
-static u64 general_dma_mask = DMA_BIT_MASK(32);
-
-static int dma_init_resource(struct platform_device* pdev)
-{
- int ret = 0;
- int irq;
- int i;
- struct device_node *np = pdev->dev.of_node;
-
- /* registers */
- dma_dev.reg = (dma_regs *)of_iomap(np, 0);
- if ( !dma_dev.reg ) {
- dev_err(&pdev->dev, "[DMA]Cannot get IORESOURCE_MEM\n");
- return -ENOENT;
- }
-
- dma_pub_configs = (dma_pub_config *)(dma_regs *)of_iomap(np, 1);
- if ( !dma_pub_configs ) {
- dev_err(&pdev->dev, "[DMA]Cannot get IORESOURCE_MEM 1\n");
- return -ENOENT;
- }
- // only for test
-// memset((u8 *)dma_pub_configs, 0, 0x80);
-
- /* irq */
- irq = irq_of_parse_and_map(np, 0);
- if( !irq ) {
- dev_err(&pdev->dev, "[DMA]Cannot get IORESOURCE_IRQ\n");
- return -ENOENT;
- }
- dma_dev.reg->irq_type = 0xF; /* high level for all cores */
- ret = request_irq(irq, dma_Isr, IRQF_NO_THREAD, "zx29dma", &dma_dev);
- if(ret)
- return ret;
-
- /* memory for lli */
- for(i=0; i<ARRAY_SIZE(dma_chan_config); i++)
- {
- dma_lli_params[i] = kzalloc(MAX_LLI_PARAMS_CNT, GFP_KERNEL);
- if (!dma_lli_params[i]) {
- int j;
- dev_err(&pdev->dev, "[DMA]%s: could not alloc memory for lli[%d].\n",
- __func__, i);
- for(j=0; j<i; j++)
- {
- dma_unmap_single(&pdev->dev, dma_lli_phy_addr[j], MAX_LLI_PARAMS_CNT, DMA_BIDIRECTIONAL);
- kfree(dma_lli_params[j]);
- dma_lli_phy_addr[j]=0;
- dma_lli_params[j]=NULL;
- }
- return -ENOENT;
- }
-
- dma_lli_phy_addr[i] = dma_map_single(&pdev->dev, dma_lli_params[i], MAX_LLI_PARAMS_CNT, DMA_BIDIRECTIONAL);
- }
-
- return 0;
-}
-
-static int dma_register_device(struct platform_device* pdev)
-{
- dma_cap_zero(dma_dev.dma.cap_mask);
- dma_cap_set(DMA_SLAVE, dma_dev.dma.cap_mask);
- dma_cap_set(DMA_CYCLIC, dma_dev.dma.cap_mask);
- dma_cap_set(DMA_INTERLEAVE, dma_dev.dma.cap_mask);
-
- dma_dev.dma.device_alloc_chan_resources = zx29_dma_alloc_chan_resources;
- dma_dev.dma.device_free_chan_resources = zx29_dma_free_chan_resource;
- dma_dev.dma.device_tx_status = zx29_dma_tx_status;
- dma_dev.dma.device_config = zx29_dma_config;
- dma_dev.dma.device_terminate_all = zx29_dma_terminate_all;
- dma_dev.dma.device_prep_dma_cyclic = zx29_prep_dma_cyclic;
- dma_dev.dma.device_prep_interleaved_dma = zx29_prep_dma_interleaved;
- dma_dev.dma.device_issue_pending = zx29_dma_issue_pending;
-
- dma_dev.dma.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
- BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
- BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
- BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
- dma_dev.dma.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
- BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
- BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
- BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
- dma_dev.dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | BIT(DMA_MEM_TO_MEM);
-
- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
- pdev->dev.dma_mask = &general_dma_mask;
-
- dma_dev.dma.dev = &pdev->dev;
- return dma_async_device_register(&dma_dev.dma);
-}
-
-static int zx29_dma_probe(struct platform_device* pdev)
-{
- int ret = 0;
-
- /* resource */
- ret = dma_init_resource(pdev);
- if(ret)
- {
- pr_info("[DMA]get resource failed!\n");
- return ret;
- }
-
- /* channel info */
- dma_init_channels();
-
- /* register device */
- ret = dma_register_device(pdev);
- if (ret)
- {
- dev_info(dma_dev.dma.dev, "[DMA]unable to register\n");
- return -EINVAL;
- }
-
- pr_info("[DMA]zx297520v DMA initialized\n");
-
- return 0;
-}
-
-static const struct of_device_id zx29_dma_dt_ids[] = {
- { .compatible = "arm,zx297520v3-dma" },
- {}
-};
-MODULE_DEVICE_TABLE(of, zx29_dma_dt_ids);
-
-struct platform_driver zx29_dma_driver = {
- .driver = {
- .name = "zx29_dma",
- .of_match_table = of_match_ptr(zx29_dma_dt_ids),
- },
- .probe = zx29_dma_probe,
-};
-static int __init zx29_dma_driver_init(void)
-{
- return platform_driver_register(&zx29_dma_driver);
-}
-subsys_initcall(zx29_dma_driver_init);
-
-
-/**
- * "/sys/zte/test/dma_test"
- */
-extern struct kobject *zx_test_kobj;
-int __init zx_dma_test_init(void)
-{
-#if ZX29_DMA_TEST
- int ret;
-
- ret = sysfs_create_group(zx_test_kobj, &zx29_dma_attribute_group);
- if (!ret)
- pr_debug("[DEBUG] create test dma sysfs interface OK.\n");
-#endif
-
- return 0;
-}
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/dma/zte/zx297520v3_dma.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/dma/zte/zx297520v3_dma.h
deleted file mode 100644
index 816fb08..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/dma/zte/zx297520v3_dma.h
+++ /dev/null
@@ -1,132 +0,0 @@
-#ifndef _MACH_ZX297520V3_DMA_H
-#define _MACH_ZX297520V3_DMA_H
-
-#include <linux/dma/zx-dma.h>
-
-typedef enum
-{
- DMA_INT_ERR, //transmission error
- DMA_INT_END, //transmission done
-
- MAX_DMA_INT
-}dma_int_status;
-
-//typedef void (*dma_callback_func)(unsigned int channel, dma_int_status status,void *data);
-
-
-/*----DMA Transfer Control Set------*/
-typedef enum
-{
- DMA_DISABLE = 0, //disable DMA transmission
- DMA_ENABLE = 1, //enable DMA transmission
- DMA_ENABLE_ALL
-}dma_control_enable;
-
-/*----DMA Request mode set------*/
-typedef enum
-{
- DMA_PERIPHERAL_REQ = 0, //peripheral request
- DMA_SOFT_REQ = 1, //soft request for single transfer
-
- DMA_REQ_MOD_ALL
-}dma_req_mode;
-
-/*----DMA SingleRequest mode set------*/
-typedef enum
-{
- DMA_SOFT_SINGLE_REQ_DISABLE = 0, //soft request for single transfer
- DMA_SOFT_SINGLE_REQ_ENABLE = 1, //soft request for burst transfer
-
- DMA_SINGLE_REQ_MOD_ALL
-}dma_single_req_mod;
-
-
-/*----DMA Source or Dest address mode------*/
-typedef enum
-{
- DMA_ADDRMOD_RAM = 0, //RAM mode, address will increase during transmission
- DMA_ADDRMOD_FIFO = 1, //FIFO mode, address will not change during transmission
-
- DMA_ADDRMOD_ALL
-}dma_addr_mode;
-
-
-typedef enum
-{
- DMA_INT_TO_PHY=0,
- DMA_INT_TO_PS,
- DMA_INT_TO_M0,
- DMA_INT_TO_A9,
-
-
- DMA_INT_SEL_ALL
-}dma_int_sel;
-
-typedef enum
-{
- CHANNEL_DISABLE,
- CHANNEL_ENABLE,
-
- MAX_CHANNEL_STATUS
-}dma_channel_satus;
-
-typedef enum
-{
- SYS_RST_ACTIVE=0,
- SYS_RST_RELEASE=1
-}sys_reset_state;
-
-/*----DMA priorty------*/
-typedef enum
-{
- DMA_PRIORTY_LEVEL0 = 0,
- DMA_PRIORTY_LEVEL1, /* ÿ¸öͨµÀ4×éÓÅÏȼ¶£¬00 ×î¸ß */
- DMA_PRIORTY_LEVEL2, /* ÓÅÏȼ¶ÏàͬµÄͨµÀÂÖѯ */
- DMA_PRIORTY_LEVEL3,
- DMA_PRIORTY_ALL
-} dma_priorty;
-
-/*dma channel reg define*/
-typedef struct
-{
- volatile unsigned int src_addr; /**< offset:0x0, R/W */
- volatile unsigned int dest_addr; /**< offset:0x4, R/W */
- volatile unsigned int xpara; /**< offset:0x8, R/W */
- volatile unsigned int yzpara; /**< offset:0xc, R/W */
- volatile unsigned int src_yzstep; /**< offset:0x10, R/W */
- volatile unsigned int dest_yzstep; /**< offset:0x14, R/W */
- volatile unsigned int reserved0; /**< offset:0x18, R/W */
- volatile unsigned int link_addr; /**< offset:0x1c, R/W */
- volatile unsigned int control; /**< offset:0x20, R/W */
- volatile unsigned int reserved1[7];
-}dma_chan_reg;
-
-/*dma device reg module define*/
-typedef struct
-{
- dma_chan_reg channel[32];
- volatile unsigned int int_tc_status; /**< offset:0x800, R */
- volatile unsigned int int_src_err_status; /**< offset:0x804, R */
- volatile unsigned int int_dest_err_status; /**< offset:0x808, R */
- volatile unsigned int int_cfg_err_status; /**< offset:0x80c, R */
- volatile unsigned int raw_int_tc_status; /**< offset:0x810, R/C */
- volatile unsigned int raw_int_src_err_status; /**< offset:0x814, R/C */
- volatile unsigned int raw_int_dest_err_status; /**< offset:0x818, R/C */
- volatile unsigned int raw_int_cfg_err_status; /**< offset:0x81c, R/C */
- volatile unsigned int working_status; /**< offset:0x820, R */
- volatile unsigned int group_order; /**< offset:0x824, R/W */
- volatile unsigned int arbit_mode; /**< offset:0x828, R/W */
- volatile unsigned int irq_type; /**< offset:0x82c, R/W */
-}dma_regs;
-
-signed int zx298501_dma_request(dma_peripheral_id peripheralID);
-//signed int zx298501_dma_config(unsigned int channel,dma_channel_def *tChanPar);
-signed int zx298501_dma_start(unsigned int channel);
-signed int zx298501_dma_stop(unsigned int channel);
-
-unsigned int zx298501_dma_get_status(void);
-
-extern void dma_m2m_test(struct device *dev);
-
-#endif
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/pinctrl/zte/pinctrl-zx297520v3.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/pinctrl/zte/pinctrl-zx297520v3.c
deleted file mode 100644
index 9a8fc10..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/pinctrl/zte/pinctrl-zx297520v3.c
+++ /dev/null
@@ -1,1617 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * Copyright 2017 Linaro Ltd.
- */
-
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-#include "../core.h"
-#include "../pinctrl-utils.h"
-#include "../pinmux.h"
-
-#include <dt-bindings/pinctrl/zx297520v3-pinctrl.h>
-#include "pinctrl-zx297520v3.h"
-#include <linux/soc/zte/spinlock.h>
-
-#define pin_log pr_debug
-
-/* 2bit */
-#define ZX_PE BIT(0) /* pull enable */
-#define ZX_PS BIT(1) /* 1-PU 0-PD */
-
-/* 8bit */
-#define ZX_PULL_UP BIT(5)
-#define ZX_PULL_DOWN BIT(6)
-#define ZX_ST BIT(4) /* schmitt trigger */
-#define ZX_DS_SHIFT 0
-#define ZX_DS_MASK (0x7 << ZX_DS_SHIFT)
-#define ZX_DS_VALUE(x) (((x) << ZX_DS_SHIFT) & ZX_DS_MASK)
-#define ZX_INPUT_ENABLE BIT(3)
-#define ZX_SLEW BIT(7)
-
-#define ZX_PINMUX_LOCK reg_spin_lock();
-#define ZX_PINMUX_UNLOCK reg_spin_unlock();
-
-struct zx_pinctrl {
- struct pinctrl_dev *pctldev;
- struct device *dev;
- void __iomem *base;
- void __iomem *pd_base;
- spinlock_t lock;
- struct zx_pinctrl_soc_info *info;
-};
-
-static const struct pinctrl_ops zx_pinctrl_ops = {
- .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
- .dt_free_map = pinctrl_utils_free_map,
- .get_groups_count = pinctrl_generic_get_group_count,
- .get_group_name = pinctrl_generic_get_group_name,
- .get_group_pins = pinctrl_generic_get_group_pins,
-};
-
-static void zx_write_mux(struct zx_pinctrl *zpctl, struct zx_pin_data *data, struct zx_mux_desc *mux)
-{
- u32 toffset, tbitpos;
- u32 mask, bitpos, width;
- void __iomem *reg;
- unsigned long flags;
- u32 val;
-
- if (data->top) {
- toffset = data->toffset;
- tbitpos = data->tbitpos;
- }
-
- if (mux->mux_val & PD_MUX_FLAG) {
- width = data->pwidth;
- mask = (1 << data->pwidth) - 1;
- bitpos = data->pbitpos;
- reg = zpctl->pd_base + data->poffset;
- } else {
- width = data->awidth;
- mask = (1 << data->awidth) - 1;
- bitpos = data->abitpos;
- reg = zpctl->base + data->aoffset;
- }
-
- spin_lock_irqsave(&zpctl->lock, flags);
-
- ZX_PINMUX_LOCK
-
- if (data->top) {
- val = readl(zpctl->base + toffset);
- pin_log("%s: top off(0x%x) bit(%d) cur_val(0x%x)\n", __func__, toffset, tbitpos, val);
- if (mux->mux_val & PD_MUX_FLAG)
- val |= (1 << tbitpos);
- else
- val &= ~(1 << tbitpos);
- writel(val, zpctl->base + toffset);
- pin_log("%s: top off(0x%x) bit(%d) rb_val(0x%x)\n", __func__, toffset, tbitpos, readl(zpctl->base + toffset));
- }
-
- if (width != 0) {
- val = readl(reg);
- pin_log("%s: pin reg(0x%x) bit(%d) mux_val(%d) cur_val(0x%x)\n", __func__, (u32)reg, bitpos, mux->mux_val, val);
- val &= ~(mask << bitpos);
- val |= (mux->mux_val & mask) << bitpos;
- writel(val, reg);
- pin_log("%s: pin off(0x%x) bit(%d) mux_val(%d) val(0x%x)\n", __func__, (u32)reg, bitpos, mux->mux_val, readl(reg));
- }
-
- ZX_PINMUX_UNLOCK
-
- spin_unlock_irqrestore(&zpctl->lock, flags);
-}
-
-static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
- unsigned int group_selector)
-{
- struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
- struct zx_pinctrl_soc_info *info = zpctl->info;
- const struct pinctrl_pin_desc *pindesc = info->pins + group_selector;
- struct zx_pin_data *data = pindesc->drv_data;
- struct zx_mux_desc *mux;
- struct function_desc *func;
-
- /* Skip reserved pin */
- if (!data)
- return -EINVAL;
-
- mux = data->muxes;
-
- func = pinmux_generic_get_function(pctldev, func_selector);
- if (!func)
- return -EINVAL;
-
- if (strcmp(func->name, FUNC_NOMUX) == 0)
- return 0;
-
- while (mux->name) {
- if (strcmp(mux->name, func->name) == 0)
- break;
- mux++;
- }
-
- pin_log("%s:pin(%s) func(%s)\n", __func__, pindesc->name, mux->name);
- zx_write_mux(zpctl, data, mux);
-
- return 0;
-}
-
-static int zx_gpio_request_enable(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned pin_num)
-{
- struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
- struct zx_pinctrl_soc_info *info = zpctl->info;
- const struct pinctrl_pin_desc *pindesc = info->pins + pin_num;
- struct zx_pin_data *data = pindesc->drv_data;
- struct zx_mux_desc *mux;
-
- /* Skip reserved pin */
- if (!data)
- return -EINVAL;
-
- mux = data->muxes;
-
- while (mux->name) {
- if (strcmp(mux->name, FUNC_GPIO) == 0)
- break;
- mux++;
- }
-
- pin_log("%s:pin(%s) func(%s)\n", __func__, pindesc->name, mux->name);
- zx_write_mux(zpctl, data, mux);
-
- /* pinconf also ... */
-/* return zx_write_config(zpctl, data, configs, num_configs); */
-
- return 0;
-
-}
-
-static const struct pinmux_ops zx_pinmux_ops = {
- .get_functions_count = pinmux_generic_get_function_count,
- .get_function_name = pinmux_generic_get_function_name,
- .get_function_groups = pinmux_generic_get_function_groups,
- .set_mux = zx_set_mux,
- .gpio_request_enable = zx_gpio_request_enable,
-};
-
-static int zx_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *config)
-{
- struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
- struct zx_pinctrl_soc_info *info = zpctl->info;
- const struct pinctrl_pin_desc *pindesc = info->pins + pin;
- struct zx_pin_data *data = pindesc->drv_data;
- enum pin_config_param param = pinconf_to_config_param(*config);
- u32 val;
-
- /* Skip reserved pin */
- if (!data)
- return -EINVAL;
-
- val = readl(zpctl->base + data->coffset);
- val = val >> data->cbitpos;
-
- switch (param) {
- case PIN_CONFIG_BIAS_PULL_DOWN:
- if (data->cwidth == 2) {
- if (val & ZX_PE) {
- val &= ZX_PS;
- val = !!val;
- if (val==0) {
- val = 1;
- break;
- }
- }
- return -EINVAL;
- } else {
- val &= ZX_PULL_DOWN;
- val = !!val;
- if (val == 0)
- return -EINVAL;
- }
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- if (data->cwidth == 2) {
- if (val & ZX_PE) {
- val &= ZX_PS;
- val = !!val;
- if (val==1) {
- break;
- }
- }
- return -EINVAL;
- } else {
- val &= ZX_PULL_UP;
- val = !!val;
- if (val == 0)
- return -EINVAL;
- }
- break;
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- if (data->cwidth == 2)
- return -ENOTSUPP;
-
- val &= ZX_ST;
- val = !!val;
- if (val == 0)
- return -EINVAL;
- break;
- case PIN_CONFIG_DRIVE_STRENGTH:
- if (data->cwidth == 2)
- return -ENOTSUPP;
-
- val &= ZX_DS_MASK;
- val = val >> ZX_DS_SHIFT;
- break;
-
- case PIN_CONFIG_INPUT_ENABLE:
- if (data->cwidth == 2)
- return -ENOTSUPP;
-
- val &= ZX_INPUT_ENABLE;
- val = !!val;
- if (val == 0)
- return -EINVAL;
- break;
- default:
- return -ENOTSUPP;
- }
-
- *config = pinconf_to_config_packed(param, val);
-
- return 0;
-}
-
-static int zx_write_config(struct zx_pinctrl *zpctl, struct zx_pin_data *data,
- unsigned long *configs, unsigned int num_configs)
-{
- enum pin_config_param param;
- u32 val, arg;
- unsigned long flags;
- int i;
-
- spin_lock_irqsave(&zpctl->lock, flags);
- ZX_PINMUX_LOCK
-
- val = readl(zpctl->base + data->coffset);
- pin_log("%s: coffset(0x%x) bp(%d) wid(%d) cur value (0x%x)\n", __func__, data->coffset,
- data->cbitpos, data->cwidth, val);
-
- for (i = 0; i < num_configs; i++) {
- param = pinconf_to_config_param(configs[i]);
- arg = pinconf_to_config_argument(configs[i]);
-
- switch (param) {
- case PIN_CONFIG_BIAS_PULL_DOWN:
- if (data->cwidth == 2) {
- val |= ZX_PE << data->cbitpos;
- val &= ~(ZX_PS << data->cbitpos);
- } else {
- val |= ZX_PULL_DOWN << data->cbitpos;
- }
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- if (data->cwidth == 2) {
- val |= ZX_PE << data->cbitpos;
- val |= ZX_PS << data->cbitpos;
- } else {
- val |= ZX_PULL_UP << data->cbitpos;
- }
- break;
- case PIN_CONFIG_BIAS_DISABLE:
- if (data->cwidth == 2) {
- val &= ~(ZX_PE << data->cbitpos);
- } else {
- val &= ~(ZX_PULL_DOWN << data->cbitpos);
- val &= ~(ZX_PULL_UP << data->cbitpos);
- }
- break;
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- if (data->cwidth == 2)
- break;
-
- if (arg)
- val |= ZX_ST << data->cbitpos;
- else
- val &= ~(ZX_ST << data->cbitpos);
- break;
- case PIN_CONFIG_SLEW_RATE:
- if (data->cwidth == 2)
- break;
-
- if (arg)
- val |= ZX_SLEW << data->cbitpos;
- else
- val &= ~(ZX_SLEW << data->cbitpos);
- break;
- case PIN_CONFIG_INPUT_ENABLE:
- val |= ZX_INPUT_ENABLE << data->cbitpos;
- break;
- case PIN_CONFIG_DRIVE_STRENGTH:
- if (data->cwidth == 2)
- break;
-
- val &= ~(ZX_DS_MASK << data->cbitpos);
- val |= ZX_DS_VALUE(arg) << data->cbitpos;
- break;
- default:
- ZX_PINMUX_UNLOCK
- spin_unlock_irqrestore(&zpctl->lock, flags);
- return -EINVAL;
- break;
- }
- }
-
- writel(val, zpctl->base + data->coffset);
- pin_log("%s:off(0x%x) pos(%d) wr_val(0x%x) rd_val(0x%x)\n", __func__, data->coffset, data->cbitpos, val, readl(zpctl->base + data->coffset));
-
- ZX_PINMUX_UNLOCK
- spin_unlock_irqrestore(&zpctl->lock, flags);
-
- return 0;
-
-}
-
-static int zx_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *configs, unsigned int num_configs)
-{
- struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
- struct zx_pinctrl_soc_info *info = zpctl->info;
- const struct pinctrl_pin_desc *pindesc = info->pins + pin;
- struct zx_pin_data *data = pindesc->drv_data;
-
- /* Skip reserved pin */
- if (!data)
- return -EINVAL;
-
- return zx_write_config(zpctl, data, configs, num_configs);
-}
-
-static const struct pinconf_ops zx_pinconf_ops = {
- .pin_config_set = zx_pin_config_set,
- .pin_config_get = zx_pin_config_get,
- .is_generic = true,
-};
-
-static int zx_pinctrl_build_state(struct platform_device *pdev)
-{
- struct zx_pinctrl *zpctl = platform_get_drvdata(pdev);
- struct zx_pinctrl_soc_info *info = zpctl->info;
- struct pinctrl_dev *pctldev = zpctl->pctldev;
- struct function_desc *functions;
- int nfunctions;
- struct group_desc *groups;
- int ngroups;
- int i;
-
- /* Every single pin composes a group */
- ngroups = info->npins;
- groups = devm_kcalloc(&pdev->dev, ngroups, sizeof(*groups),
- GFP_KERNEL);
- if (!groups)
- return -ENOMEM;
-
- for (i = 0; i < ngroups; i++) {
- const struct pinctrl_pin_desc *pindesc = info->pins + i;
- struct group_desc *group = groups + i;
-
- group->name = pindesc->name;
- group->pins = (int *) &pindesc->number;
- group->num_pins = 1;
- radix_tree_insert(&pctldev->pin_group_tree, i, group);
- }
-
- pctldev->num_groups = ngroups;
-
- /* Build function list from pin mux functions */
- functions = kcalloc(info->npins*6, sizeof(*functions), GFP_KERNEL);
- if (!functions)
- return -ENOMEM;
-
- nfunctions = 0;
- for (i = 0; i < info->npins; i++) {
- const struct pinctrl_pin_desc *pindesc = info->pins + i;
- struct zx_pin_data *data = pindesc->drv_data;
- struct zx_mux_desc *mux;
-
- /* Reserved pins do not have a drv_data at all */
- if (!data)
- continue;
-
- /* Loop over all muxes for the pin */
- mux = data->muxes;
- while (mux->name) {
- struct function_desc *func = functions;
-
- /* Search function list for given mux */
- while (func->name) {
- if (strcmp(mux->name, func->name) == 0) {
- /* Function exists */
- func->num_group_names++;
- break;
- }
- func++;
- }
-
- if (!func->name) {
- /* New function */
- func->name = mux->name;
- func->num_group_names = 1;
- radix_tree_insert(&pctldev->pin_function_tree,
- nfunctions++, func);
- }
-
- mux++;
- }
- }
-
- pctldev->num_functions = nfunctions;
- functions = krealloc(functions, nfunctions * sizeof(*functions),
- GFP_KERNEL);
- if (!functions)
- return -ENOMEM;
-
- /* Find pin groups for every single function */
- for (i = 0; i < info->npins; i++) {
- const struct pinctrl_pin_desc *pindesc = info->pins + i;
- struct zx_pin_data *data = pindesc->drv_data;
- struct zx_mux_desc *mux;
-
- if (!data)
- continue;
-
- mux = data->muxes;
- while (mux->name) {
- struct function_desc *func;
- const char **group;
- int j;
-
- /* Find function for given mux */
- for (j = 0; j < nfunctions; j++)
- if (strcmp(functions[j].name, mux->name) == 0)
- break;
-
- func = functions + j;
- if (!func->group_names) {
- func->group_names = devm_kcalloc(&pdev->dev,
- func->num_group_names,
- sizeof(*func->group_names),
- GFP_KERNEL);
- if (!func->group_names) {
- kfree(functions);
- return -ENOMEM;
- }
- }
-
- group = func->group_names;
- while (*group)
- group++;
- *group = pindesc->name;
-
- mux++;
- }
- }
-
- return 0;
-}
-
-int zx_pinctrl_init(struct platform_device *pdev,
- struct zx_pinctrl_soc_info *info)
-{
- struct pinctrl_desc *pctldesc;
- struct zx_pinctrl *zpctl;
- struct resource *res;
- int ret;
-
- zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), GFP_KERNEL);
- if (!zpctl)
- return -ENOMEM;
-
- spin_lock_init(&zpctl->lock);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- zpctl->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(zpctl->base))
- return PTR_ERR(zpctl->base);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- zpctl->pd_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(zpctl->pd_base))
- return PTR_ERR(zpctl->pd_base);
-
- zpctl->dev = &pdev->dev;
- zpctl->info = info;
-
- pctldesc = devm_kzalloc(&pdev->dev, sizeof(*pctldesc), GFP_KERNEL);
- if (!pctldesc)
- return -ENOMEM;
-
- pctldesc->name = dev_name(&pdev->dev);
- pctldesc->owner = THIS_MODULE;
- pctldesc->pins = info->pins;
- pctldesc->npins = info->npins;
- pctldesc->pctlops = &zx_pinctrl_ops;
- pctldesc->pmxops = &zx_pinmux_ops;
- pctldesc->confops = &zx_pinconf_ops;
-
- zpctl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, zpctl);
- if (IS_ERR(zpctl->pctldev)) {
- ret = PTR_ERR(zpctl->pctldev);
- dev_err(&pdev->dev, "failed to register pinctrl: %d\n", ret);
- return ret;
- }
-
- platform_set_drvdata(pdev, zpctl);
-
- ret = zx_pinctrl_build_state(pdev);
- if (ret) {
- dev_err(&pdev->dev, "failed to build state: %d\n", ret);
- return ret;
- }
-
- dev_info(&pdev->dev, "initialized pinctrl driver\n");
- return 0;
-}
-
-/*------------------------------------------------------------------------------------*/
-#define PMM_REG0 0x00
-#define PMM_REG1 0x04
-#define PMM_REG2 0x08
-#define PMM_REG3 0x0C
-#define PMM_REG4 0x10
-#define PMM_REG5 0x14
-#define PMM_REG6 0x18
-#define PMM_REG7 0x1C
-#define PMM_REG8 0x20
-#define PMM_REG9 0x24
-#define PMM_REG10 0x28
-#define PMM_REG11 0x2C
-#define PMM_REG12 0x30
-#define PMM_REG13 0x34
-#define PMM_REG14 0x38
-#define PMM_REG15 0x3C
-#define PMM_REG16 0x40
-#define PMM_REG17 0x44
-#define PMM_REG18 0x48
-#define PMM_REG19 0x4C
-#define PMM_REG20 0x50
-
-#define PMM_REG_INV 0xFF
-
-static const struct pinctrl_pin_desc zx297520v3_pins[] = {
-
- ZX_PIN(NAND_WE, true, PMM_REG7, 0,
- 0, 0, 0,
- PMM_REG0, 0, 1,
- PMM_REG0, 0, 2,
- PD_MUX(0x0, "NAND"), /* nand_we */
- PD_MUX(0x1, "LCD"), /* lcd_oe_n */
- AON_MUX(0x0, "BGPIO")), /* gpio0 */
-
- ZX_PIN(NAND_CSN, true, PMM_REG7, 1,
- 0, 0, 0,
- PMM_REG0, 1, 1,
- PMM_REG0, 2, 2,
- PD_MUX(0x0, "NAND"), /* nand_csn */
- PD_MUX(0x1, "LCD"), /* lcd_cs_n */
- AON_MUX(0x0, "BGPIO")), /* gpio1 */
-
- ZX_PIN(NAND_READY, true, PMM_REG7, 2,
- 0, 0, 0,
- PMM_REG0, 2, 1,
- PMM_REG0, 4, 2,
- PD_MUX(0x0, "NAND"), /* nand_ready */
- PD_MUX(0x1, "LCD"), /* lcd_rs */
- AON_MUX(0x0, "BGPIO")), /* gpio2 */
-
- ZX_PIN(NAND_CLE, true, PMM_REG7, 3,
- 0, 0, 0,
- PMM_REG0, 3, 1,
- PMM_REG0, 6, 2,
- PD_MUX(0x0, "NAND"), /* nand_ready */
- PD_MUX(0x1, "LCD"), /* lcd_rst_n */
- AON_MUX(0x0, "BGPIO")), /* gpio3 */
-
- ZX_PIN(NAND_ALE, true, PMM_REG7, 4,
- 0, 0, 0,
- PMM_REG0, 4, 1,
- PMM_REG0, 8, 2,
- PD_MUX(0x0, "NAND"), /* nand_ale */
- PD_MUX(0x1, "LCD"), /* lcd_we_n */
- AON_MUX(0x0, "BGPIO")), /* gpio4 */
-
- ZX_PIN(NAND_RE, true, PMM_REG7, 5,
- 0, 0, 0,
- PMM_REG0, 5, 1,
- PMM_REG0, 10, 2,
- PD_MUX(0x0, "NAND"), /* nand_re */
- PD_MUX(0x1, "LCD"), /* lcd_te */
- AON_MUX(0x0, "BGPIO")), /* gpio5 */
-
- ZX_PIN(NAND_WP, true, PMM_REG7, 6,
- 0, 0, 0,
- PMM_REG0, 6, 1,
- PMM_REG0, 12, 2,
- PD_MUX(0x0, "NAND"), /* nand_wp */
- PD_MUX(0x1, "LCD"), /* lcd_d0 */
- AON_MUX(0x0, "BGPIO")), /* gpio6 */
-
- ZX_PIN(NAND_D0, true, PMM_REG7, 7,
- 0, 0, 0,
- PMM_REG0, 7, 1,
- PMM_REG0, 14, 2,
- PD_MUX(0x0, "NAND"), /* nand_d0 */
- PD_MUX(0x1, "LCD"), /* lcd_d1 */
- AON_MUX(0x0, "BGPIO")), /* gpio7 */
-
- ZX_PIN(NAND_D1, true, PMM_REG7, 8,
- 0, 0, 0,
- PMM_REG0, 8, 1,
- PMM_REG0, 16, 2,
- PD_MUX(0x0, "NAND"), /* nand_d1 */
- PD_MUX(0x1, "LCD"), /* lcd_d2 */
- AON_MUX(0x0, "BGPIO")), /* gpio8 */
-
- ZX_PIN(NAND_D2, true, PMM_REG7, 9,
- 0, 0, 0,
- PMM_REG0, 9, 1,
- PMM_REG0, 18, 2,
- PD_MUX(0x0, "NAND"), /* nand_d2 */
- PD_MUX(0x1, "LCD"), /* lcd_d3 */
- AON_MUX(0x0, "BGPIO")), /* gpio9 */
-
- ZX_PIN(NAND_D3, true, PMM_REG7, 10,
- 0, 0, 0,
- PMM_REG0, 10, 1,
- PMM_REG0, 20, 2,
- PD_MUX(0x0, "NAND"), /* nand_d3 */
- PD_MUX(0x1, "LCD"), /* lcd_d4 */
- AON_MUX(0x0, "BGPIO")), /* gpio10 */
-
- ZX_PIN(NAND_D4, true, PMM_REG7, 11,
- 0, 0, 0,
- PMM_REG0, 11, 1,
- PMM_REG0, 22, 2,
- PD_MUX(0x0, "NAND"), /* nand_d4 */
- PD_MUX(0x1, "LCD"), /* lcd_d5 */
- AON_MUX(0x0, "BGPIO")), /* gpio11 */
-
- ZX_PIN(NAND_D5, true, PMM_REG7, 12,
- 0, 0, 0,
- PMM_REG0, 12, 1,
- PMM_REG0, 24, 2,
- PD_MUX(0x0, "NAND"), /* nand_d5 */
- PD_MUX(0x1, "LCD"), /* lcd_d6 */
- AON_MUX(0x0, "BGPIO")), /* gpio12 */
-
- ZX_PIN(NAND_D6, true, PMM_REG7, 13,
- 0, 0, 0,
- PMM_REG0, 13, 1,
- PMM_REG0, 26, 2,
- PD_MUX(0x0, "NAND"), /* nand_d6 */
- PD_MUX(0x1, "LCD"), /* lcd_d7 */
- AON_MUX(0x0, "BGPIO")), /* gpio13 */
-
- ZX_PIN(NAND_D7, true, PMM_REG7, 14,
- 0, 0, 0,
- PMM_REG0, 14, 1,
- PMM_REG0, 28, 2,
- PD_MUX(0x0, "NAND"), /* nand_d7 */
- PD_MUX(0x1, "LCD"), /* lcd_d8 */
- AON_MUX(0x0, "BGPIO")), /* gpio14 */
-
- ZX_PIN(CLK_OUT0, false, 0, 0,
- PMM_REG0, 0, 2,
- 0, 0, 0,
- PMM_REG1, 10, 2,
- AON_MUX(0x0, "CLK_OUT0"), /* clk_out0 */
- AON_MUX(0x1, "BGPIO")), /* gpio15 */
-
- ZX_PIN(CLK_OUT1, false, 0, 0,
- PMM_REG0, 2, 2,
- 0, 0, 0,
- PMM_REG1, 12, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio16 */
- AON_MUX(0x1, "CLK_OUT1")), /* clk_out1 */
-
- ZX_PIN(CLK_OUT2, true, PMM_REG12, 0,
- PMM_REG0, 4, 2,
- PMM_REG0, 15, 2,
- PMM_REG1, 14, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio17 */
- AON_MUX(0x1, "CLK_OUT2"), /* clk_out2 */
- AON_MUX(0x2, "TEST_CLK_OUT"), /* test_clk_out */
- PD_MUX(0x0, "TDM"), /* tdm_mclk_out */
- PD_MUX(0x1, "I2S0"), /* i2s0_mclk_out */
- PD_MUX(0x2, "I2S1")), /* i2s1_mclk_out */
-
- ZX_PIN(CLK_32K_OUT, false, 0, 0,
- PMM_REG0, 6, 2,
- 0, 0, 0,
- PMM_REG1, 16, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio18 */
- AON_MUX(0x1, "CLK_32K_OUT")), /* clk_32k_out */
-
- ZX_PIN(RMII_CLKI, true, PMM_REG7, 15,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio19 */
- PD_MUX(0x0, "RMII")), /* rmii_clk_i */
-
- ZX_PIN(RMII_CLKO, true, PMM_REG7, 16,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio20 */
- PD_MUX(0x0, "RMII")), /* rmii_clk_o */
-
- ZX_PIN(CLK_REQ0, false, 0, 0,
- PMM_REG0, 8, 2,
- 0, 0, 0,
- PMM_REG1, 18, 2,
- AON_MUX(0x0, "CLK_REQ0"), /* clk_req0 */
- AON_MUX(0x1, "BGPIO")), /* gpio21 */
-
- ZX_PIN(CLK_REQ1, false, 0, 0,
- PMM_REG0, 10, 2,
- 0, 0, 0,
- PMM_REG1, 20, 2,
- AON_MUX(0x0, "CLK_REQ1"), /* clk_req1 */
- AON_MUX(0x1, "BGPIO")), /* gpio22 */
-
- ZX_PIN(PWRCTRL, false, 0, 0,
- PMM_REG0, 12, 2,
- 0, 0, 0,
- PMM_REG1, 22, 2,
- AON_MUX(0x0, "PWRCTRL"), /* pwrctrl0 */
- AON_MUX(0x1, "BGPIO")), /* gpio23 */
-
- ZX_PIN_NOMUX(PSHOLD, PMM_REG1, 28, 2,
- AON_MUX(0, FUNC_NOMUX)),
-
- ZX_PIN(SSP0_CS, true, PMM_REG7, 17,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG2, 0, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio25 */
- PD_MUX(0x0, "SSP0")), /* ssp0_cs */
-
- ZX_PIN(SSP0_CLK, true, PMM_REG7, 18,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG2, 2, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio26 */
- PD_MUX(0x0, "SSP0")), /* ssp0_clk */
-
- ZX_PIN(SSP0_RXD, true, PMM_REG7, 19,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG2, 4, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio27 */
- PD_MUX(0x0, "SSP0")), /* ssp0_rxd */
-
- ZX_PIN(SSP0_TXD, true, PMM_REG7, 20,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG2, 6, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio28 */
- PD_MUX(0x0, "SSP0")), /* ssp0_txd */
-
- ZX_PIN(UART0_RXD, true, PMM_REG8, 0,
- PMM_REG0, 14, 2,
- PMM_REG1, 0, 1,
- PMM_REG2, 10, 2,
- AON_MUX(0x0, "UART0"), /* uart0_rxd */
- AON_MUX(0x1, "BGPIO"), /* gpio29 */
- AON_MUX(0x2, "UART00"), /* uart00_txd */
- PD_MUX(0x1, "TEST")), /* test_10 */
-
- ZX_PIN(UART0_TXD, true, PMM_REG8, 1,
- PMM_REG0, 16, 2,
- PMM_REG1, 1, 1,
- PMM_REG2, 12, 2,
- AON_MUX(0x0, "UART0"), /* uart0_txd */
- AON_MUX(0x1, "BGPIO"), /* gpio30 */
- AON_MUX(0x2, "UART00"), /* uart00_rxd */
- PD_MUX(0x1, "TEST")), /* test_11 */
-
- ZX_PIN(UART0_CTS, true, PMM_REG8, 2,
- PMM_REG0, 18, 2,
- PMM_REG1, 2, 2,
- PMM_REG2, 14, 2,
- AON_MUX(0x0, "UART0"), /* uart0_cts */
- AON_MUX(0x1, "BGPIO"), /* gpio31 */
- PD_MUX(0x1, "UART1"), /* uart1_txd */
- PD_MUX(0x2, "TEST")), /* test_12 */
-
- ZX_PIN(UART0_RTS, true, PMM_REG8, 3,
- PMM_REG0, 20, 2,
- PMM_REG1, 4, 2,
- PMM_REG2, 16, 2,
- AON_MUX(0x0, "UART0"), /* uart0_rts */
- AON_MUX(0x1, "BGPIO"), /* gpio32 */
- PD_MUX(0x1, "UART1")), /* uart1_rxd */
-
- ZX_PIN(UART1_RXD, true, PMM_REG8, 4,
- 0, 0, 0,
- PMM_REG1, 6, 2,
- PMM_REG2, 18, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio33 */
- PD_MUX(0x0, "UART1"), /* uart1_rxd */
- PD_MUX(0x1, "UART2"), /* uart2_txd */
- PD_MUX(0x2, "UART22")), /* uart22_rxd */
-
- ZX_PIN(UART1_TXD, true, PMM_REG8, 5,
- 0, 0, 0,
- PMM_REG1, 8, 2,
- PMM_REG2, 20, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio34 */
- PD_MUX(0x0, "UART1"), /* uart1_rxd */
- PD_MUX(0x1, "UART2"), /* uart2_xxd */
- PD_MUX(0x2, "UART22")), /* uart22_txd */
-
- ZX_PIN(I2S0_WS, true, PMM_REG8, 6,
- 0, 0, 0,
- PMM_REG1, 10, 2,
- PMM_REG2, 22, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio35 */
- PD_MUX(0x0, "I2S0"), /* i2s0_ws */
- PD_MUX(0x1, "TEST")), /* test_0 */
-
- ZX_PIN(I2S0_CLK, true, PMM_REG8, 7,
- 0, 0, 0,
- PMM_REG1, 12, 2,
- PMM_REG2, 24, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio36 */
- PD_MUX(0x0, "I2S0"), /* i2s0_clk */
- PD_MUX(0x1, "TEST"), /* test_1 */
- PD_MUX(0x2, "TDM")), /* tdm_clk */
-
- ZX_PIN(I2S0_DIN, true, PMM_REG8, 8,
- 0, 0, 0,
- PMM_REG1, 14, 2,
- PMM_REG2, 26, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio37 */
- PD_MUX(0x0, "I2S0"), /* i2s0_din */
- PD_MUX(0x1, "TEST"), /* test_2 */
- PD_MUX(0x2, "TDM")), /* tdm_din */
-
- ZX_PIN(I2S0_DOUT, true, PMM_REG8, 9,
- 0, 0, 0,
- PMM_REG1, 16, 2,
- PMM_REG2, 28, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio38 */
- PD_MUX(0x0, "I2S0"), /* i2s0_dout */
- PD_MUX(0x1, "TEST"), /* test_3 */
- PD_MUX(0x2, "TDM")), /* tdm_dout */
-
- ZX_PIN(I2S1_WS, true, PMM_REG8, 10,
- 0, 0, 0,
- PMM_REG1, 18, 2,
- PMM_REG2, 30, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio39 */
- PD_MUX(0x0, "I2S1"), /* i2s0_ws */
- PD_MUX(0x1, "TEST"), /* test_4 */
- PD_MUX(0x2, "TDM"), /* tdm_fs */
- PD_MUX(0x3, "PWM0")), /* pwm0 */
-
- ZX_PIN(I2S1_CLK, true, PMM_REG8, 11,
- 0, 0, 0,
- PMM_REG1, 20, 2,
- PMM_REG3, 0, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio40 */
- PD_MUX(0x0, "I2S1"), /* i2s0_clk */
- PD_MUX(0x1, "TEST"), /* test_5 */
- PD_MUX(0x2, "TDM"), /* tdm_clk */
- PD_MUX(0x3, "PWM1")), /* pwm1 */
-
- ZX_PIN(I2S1_DIN, true, PMM_REG8, 12,
- 0, 0, 0,
- PMM_REG1, 22, 2,
- PMM_REG3, 2, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio41 */
- PD_MUX(0x0, "I2S1"), /* i2s0_din */
- PD_MUX(0x1, "TEST"), /* test_6 */
- PD_MUX(0x2, "TDM")), /* tdm_din */
-
- ZX_PIN(I2S1_DOUT, true, PMM_REG8, 13,
- 0, 0, 0,
- PMM_REG1, 24, 2,
- PMM_REG3, 4, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio42 */
- PD_MUX(0x0, "I2S1"), /* i2s0_dout */
- PD_MUX(0x1, "TEST"), /* test_7 */
- PD_MUX(0x2, "TDM")), /* tdm_dout */
-
- ZX_PIN(I2C0_SCL, false, 0, 0,
- PMM_REG1, 0, 2,
- 0, 0, 0,
- PMM_REG3, 6, 2,
- AON_MUX(0x0, "I2C0"), /* i2c0_scl */
- AON_MUX(0x1, "BGPIO")), /* gpio43 */
-
- ZX_PIN(I2C0_SDA, false, 0, 0,
- PMM_REG1, 2, 2,
- 0, 0, 0,
- PMM_REG3, 8, 2,
- AON_MUX(0x0, "I2C0"), /* i2c0_sda */
- AON_MUX(0x1, "BGPIO")), /* gpio44 */
-
- ZX_PIN(I2C1_SCL, true, PMM_REG8, 14,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG3, 10, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio45 */
- PD_MUX(0x0, "I2C1")), /* i2c1_scl */
-
- ZX_PIN(I2C1_SDA, true, PMM_REG8, 15,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG3, 12, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio46 */
- PD_MUX(0x0, "I2C1")), /* i2c1_sda */
-
- ZX_PIN(EXT_INT0, false, 0, 0,
- PMM_REG1, 4, 2,
- 0, 0, 0,
- PMM_REG3, 14, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio47 */
- AON_MUX(0x1, "EXT_INT0")), /* ext_int0 */
-
- ZX_PIN(EXT_INT1, false, 0, 0,
- PMM_REG1, 6, 2,
- 0, 0, 0,
- PMM_REG3, 16, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio48 */
- AON_MUX(0x1, "EXT_INT1")), /* ext_int1 */
-
- ZX_PIN(EXT_INT2, false, 0, 0,
- PMM_REG1, 8, 2,
- 0, 0, 0,
- PMM_REG3, 18, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio49 */
- AON_MUX(0x1, "EXT_INT2")), /* ext_int2 */
-
- ZX_PIN(EXT_INT3, true, PMM_REG8, 16,
- PMM_REG1, 10, 2,
- 0, 0, 0,
- PMM_REG3, 20, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio50 */
- AON_MUX(0x1, "EXT_INT3"), /* ext_int3 */
- PD_MUX(0x0, "TEST")), /* test_8 */
-
- ZX_PIN(EXT_INT4, true, PMM_REG8, 17,
- PMM_REG1, 12, 2,
- 0, 0, 0,
- PMM_REG3, 22, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio51 */
- AON_MUX(0x1, "EXT_INT4"), /* ext_int4 */
- PD_MUX(0x0, "TEST")), /* test_9 */
-
- ZX_PIN(EXT_INT5, true, PMM_REG8, 18,
- PMM_REG1, 14, 2,
- 0, 0, 0,
- PMM_REG3, 24, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio52 */
- AON_MUX(0x1, "EXT_INT5"), /* ext_int5 */
- PD_MUX(0x0, "TEST")), /* test_13 */
-
- ZX_PIN(EXT_INT6, true, PMM_REG8, 19,
- PMM_REG1, 16, 2,
- 0, 0, 0,
- PMM_REG3, 26, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio53 */
- AON_MUX(0x1, "EXT_INT6"), /* ext_int6 */
- PD_MUX(0x0, "TEST")), /* test_14 */
-
- ZX_PIN(EXT_INT7, true, PMM_REG8, 20,
- PMM_REG1, 18, 2,
- 0, 0, 0,
- PMM_REG3, 28, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio54 */
- AON_MUX(0x1, "EXT_INT7"), /* ext_int7 */
- PD_MUX(0x0, "TEST")), /* test_15 */
-
- ZX_PIN(RMII_TXEN, true, PMM_REG9, 0,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio55 */
- PD_MUX(0x0, "RMII")), /* rmii_txen */
-
- ZX_PIN(RMII_RXEN, true, PMM_REG9, 1,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio56 */
- PD_MUX(0x0, "RMII")), /* rmii_rxen */
-
- ZX_PIN(RMII_RXD0, true, PMM_REG9, 2,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio57 */
- PD_MUX(0x0, "RMII")), /* rmii_rxd0 */
-
- ZX_PIN(RMII_RXD1, true, PMM_REG9, 3,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio58 */
- PD_MUX(0x0, "RMII")), /* rmii_rxd1 */
-
- ZX_PIN(RMII_TXD0, true, PMM_REG9, 4,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio59 */
- PD_MUX(0x0, "RMII")), /* rmii_txd0 */
-
- ZX_PIN(RMII_TXD1, true, PMM_REG9, 5,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio60 */
- PD_MUX(0x0, "RMII")), /* rmii_txd1 */
-
- ZX_PIN(MDC_SCLK, true, PMM_REG9, 6,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio61 */
- PD_MUX(0x0, "MDC")), /* mdc_sclk */
-
- ZX_PIN(MDC_SDIO, true, PMM_REG9, 7,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio62 */
- PD_MUX(0x0, "MDC")), /* mdc_sdio */
-
- ZX_PIN(PHY_RST, true, PMM_REG9, 8,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio63 */
- PD_MUX(0x0, "PHY")), /* phy_rst */
-
- ZX_PIN(PHY_INT, true, PMM_REG9, 9,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG15, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio64 */
- PD_MUX(0x0, "PHY")), /* phy_int */
-
- ZX_PIN_NOMUX(PHY_WAKE, PMM_REG15, 0, 8,
- AON_MUX(0, FUNC_NOMUX)),
-
- ZX_PIN(SD0_CLK, true, PMM_REG9, 10,
- PMM_REG2, 0, 2,
- 0, 0, 0,
- PMM_REG4, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio66 */
- AON_MUX(0x1, "KEY"), /* key_col2 */
- PD_MUX(0x0, "SD0")), /* sd0_clk */
-
- ZX_PIN(SD0_CMD, true, PMM_REG9, 11,
- PMM_REG2, 2, 2,
- 0, 0, 0,
- PMM_REG4, 8, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio67 */
- AON_MUX(0x1, "KEY"), /* key_col3 */
- PD_MUX(0x0, "SD0")), /* sd0_cmd */
-
- ZX_PIN(SD0_D0, true, PMM_REG9, 12,
- PMM_REG2, 4, 2,
- 0, 0, 0,
- PMM_REG4, 16, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio68 */
- AON_MUX(0x1, "KEY"), /* key_col4 */
- PD_MUX(0x0, "SD0")), /* sd0_d0 */
-
- ZX_PIN(SD0_D1, true, PMM_REG9, 13,
- PMM_REG2, 6, 2,
- 0, 0, 0,
- PMM_REG4, 24, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio69 */
- AON_MUX(0x1, "KEY"), /* key_row2 */
- PD_MUX(0x0, "SD0")), /* sd0_d1 */
-
- ZX_PIN(SD0_D2, true, PMM_REG9, 14,
- PMM_REG2, 8, 2,
- 0, 0, 0,
- PMM_REG5, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio70 */
- AON_MUX(0x1, "KEY"), /* key_row3 */
- PD_MUX(0x0, "SD0")), /* sd0_d2 */
-
- ZX_PIN(SD0_D3, true, PMM_REG9, 15,
- PMM_REG2, 10, 2,
- 0, 0, 0,
- PMM_REG5, 8, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio71 */
- AON_MUX(0x1, "KEY"), /* key_row4 */
- PD_MUX(0x0, "SD0")), /* sd0_d3 */
-
- ZX_PIN(SD1_CLK, true, PMM_REG9, 16,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG5, 16, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio72 */
- PD_MUX(0x0, "SD1")), /* sd1_clk */
-
- ZX_PIN(SD1_CMD, true, PMM_REG9, 17,
- PMM_REG2, 12, 2,
- PMM_REG2, 0, 2,
- PMM_REG5, 24, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio73 */
- PD_MUX(0x0, "SD1")), /* sd1_cmd */
-
- ZX_PIN(SD1_D0, true, PMM_REG9, 18,
- PMM_REG2, 14, 2,
- PMM_REG2, 2, 2,
- PMM_REG6, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio74 */
- PD_MUX(0x0, "SD1")), /* sd1_d0 */
-
- ZX_PIN(SD1_D1, true, PMM_REG9, 19,
- PMM_REG2, 16, 2,
- PMM_REG2, 4, 2,
- PMM_REG6, 8, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio75 */
- PD_MUX(0x0, "SD1")), /* sd1_d1 */
-
- ZX_PIN(SD1_D2, true, PMM_REG9, 20,
- PMM_REG2, 18, 2,
- PMM_REG2, 6, 2,
- PMM_REG6, 16, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio76 */
- PD_MUX(0x0, "SD1")), /* sd1_d2 */
-
- ZX_PIN(SD1_D3, true, PMM_REG9, 21,
- PMM_REG2, 20, 2,
- PMM_REG2, 8, 2,
- PMM_REG6, 24, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio77 */
- PD_MUX(0x0, "SD1")), /* sd1_d3 */
-
- ZX_PIN(GPIO78, true, PMM_REG9, 22,
- PMM_REG3, 0, 2,
- PMM_REG3, 0, 2,
- PMM_REG7, 0, 2,
- AON_MUX(0x1, "BGPIO")), /* gpio78 */
-
- ZX_PIN(GPIO79, true, PMM_REG9, 23,
- PMM_REG3, 2, 2,
- PMM_REG3, 2, 2,
- PMM_REG7, 2, 2,
- AON_MUX(0x1, "BGPIO")), /* gpio79 */
-
- ZX_PIN(GPIO80, true, PMM_REG9, 24,
- PMM_REG3, 4, 2,
- PMM_REG3, 4, 2,
- PMM_REG7, 4, 2,
- AON_MUX(0x1, "BGPIO")), /* gpio80 */
-
- ZX_PIN(GPIO81, true, PMM_REG9, 25,
- PMM_REG3, 6, 2,
- PMM_REG3, 6, 2,
- PMM_REG7, 6, 2,
- AON_MUX(0x1, "BGPIO")), /* gpio81 */
-
- ZX_PIN(GPIO82, true, PMM_REG9, 26,
- PMM_REG3, 8, 2,
- PMM_REG3, 8, 2,
- PMM_REG7, 8, 2,
- AON_MUX(0x1, "BGPIO")), /* gpio82 */
-
- ZX_PIN(KEY_COL0, false, 0, 0,
- PMM_REG3, 10, 2,
- 0, 0, 0,
- PMM_REG7, 10, 2,
- AON_MUX(0x0, "KEY"), /* key_col0 */
- AON_MUX(0x1, "BGPIO")), /* gpio83 */
-
- ZX_PIN(KEY_COL1, false, 0, 0,
- PMM_REG3, 12, 2,
- 0, 0, 0,
- PMM_REG7, 12, 2,
- AON_MUX(0x0, "KEY"), /* key_col1 */
- AON_MUX(0x1, "BGPIO")), /* gpio84 */
-
- ZX_PIN(KEY_ROW0, false, 0, 0,
- PMM_REG3, 14, 2,
- 0, 0, 0,
- PMM_REG7, 14, 2,
- AON_MUX(0x0, "KEY"), /* key_row0 */
- AON_MUX(0x1, "BGPIO")), /* gpio85 */
-
- ZX_PIN(KEY_ROW1, false, 0, 0,
- PMM_REG3, 16, 2,
- 0, 0, 0,
- PMM_REG7, 16, 2,
- AON_MUX(0x0, "KEY"), /* key_row1 */
- AON_MUX(0x1, "BGPIO")), /* gpio86 */
-
- ZX_PIN(CAM_SPI_CS, true, PMM_REG10, 0,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG7, 18, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio87 */
- PD_MUX(0x0, "CAM_SPI")), /* cam_spi_cs */
-
- ZX_PIN(CAM_SPI_CLK, true, PMM_REG10, 1,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG7, 20, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio88 */
- PD_MUX(0x0, "CAM_SPI")), /* cam_spi_clk */
-
- ZX_PIN(CAM_SPI_D0, true, PMM_REG10, 2,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG7, 22, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio89 */
- PD_MUX(0x0, "CAM_SPI")), /* cam_spi_d0 */
-
- ZX_PIN(CAM_SPI_D1, true, PMM_REG10, 3,
- 0, 0, 0,
- PMM_REG3, 10, 1,
- PMM_REG7, 24, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio90 */
- PD_MUX(0x0, "CAM_SPI"), /* cam_spi_d1 */
- PD_MUX(0x1, "CAM_SPI0")), /* cam_spi_txd ??? */
-
- ZX_PIN(CAM_SPI_D2, true, PMM_REG10, 4,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG7, 26, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio91 */
- PD_MUX(0x0, "CAM_SPI")), /* cam_spi_d2 */
-
- ZX_PIN(CAM_SPI_D3, true, PMM_REG10, 5,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG7, 28, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio92 */
- PD_MUX(0x0, "CAM_SPI")), /* cam_spi_d3 */
-
- ZX_PIN(SPIFC_CS, true, PMM_REG10, 6,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG8, 0, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio93 */
- PD_MUX(0x0, "SPIFC")), /* spifc_cs */
-
- ZX_PIN(SPIFC_CLK, true, PMM_REG10, 7,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG8, 2, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio94 */
- PD_MUX(0x0, "SPIFC")), /* spifc_clk */
-
- ZX_PIN(SPIFC_D0, true, PMM_REG10, 8,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG8, 4, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio95 */
- PD_MUX(0x0, "SPIFC")), /* spifc_d0 */
-
- ZX_PIN(SPIFC_D1, true, PMM_REG10, 9,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG8, 6, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio96 */
- PD_MUX(0x0, "SPIFC")), /* spifc_d1 */
-
- ZX_PIN(SPIFC_D2, true, PMM_REG10, 10,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG8, 8, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio97 */
- PD_MUX(0x0, "SPIFC")), /* spifc_d2 */
-
- ZX_PIN(SPIFC_D3, true, PMM_REG10, 11,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG8, 10, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio98 */
- PD_MUX(0x0, "SPIFC")), /* spifc_d3 */
-
- ZX_PIN(GPIO100, true, PMM_REG10, 12,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG8, 14, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio100 */
-
- ZX_PIN(GPIO101, true, PMM_REG10, 13,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG8, 16, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio101 */
-
- ZX_PIN(GPIO102, true, PMM_REG10, 14,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG8, 18, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio102 */
-
- ZX_PIN(GPIO104, true, PMM_REG10, 15,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG9, 0, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio104 */
-
- ZX_PIN(GPIO105, true, PMM_REG10, 16,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG9, 2, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio105 */
-
- ZX_PIN(GPIO106, true, PMM_REG10, 17,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG9, 4, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio106 */
-
- ZX_PIN(GPIO107, true, PMM_REG10, 18,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG9, 6, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio107 */
-
- ZX_PIN(GPIO108, true, PMM_REG10, 19,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG9, 8, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio108 */
-
- ZX_PIN(GPIO109, true, PMM_REG10, 20,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG9, 10, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio109 */
-
- ZX_PIN(GPIO110, true, PMM_REG10, 21,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG9, 12, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio110 */
-
- ZX_PIN(GPIO111, true, PMM_REG10, 22,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG9, 14, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio111 */
-
- ZX_PIN(GPIO112, true, PMM_REG10, 23,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG9, 16, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio112 */
-
- ZX_PIN(GPIO113, true, PMM_REG10, 24,
- 0, 0, 0,
- 0, 0, 0,
- PMM_REG9, 18, 2,
- AON_MUX(0x0, "BGPIO")), /* gpio113 */
-
- ZX_PIN(GPIO114, true, PMM_REG10, 25,
- PMM_REG3, 18, 2,
- 0, 0, 0,
- PMM_REG9, 20, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio114 */
- AON_MUX(0x1, "ABB_I2C")), /* abb_i2c_scl */
-
- ZX_PIN(GPIO115, true, PMM_REG10, 26,
- PMM_REG3, 20, 2,
- 0, 0, 0,
- PMM_REG9, 22, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio115 */
- AON_MUX(0x1, "ABB_I2C")), /* abb_i2c_sda */
-
- ZX_PIN(SIM_RST, false, 0, 0,
- PMM_REG3, 22, 2,
- 0, 0, 0,
- PMM_REG10, 0, 8,
- AON_MUX(0x0, "SIM"), /* sim_rst */
- AON_MUX(0x1, "BGPIO")), /* gpio116 */
-
- ZX_PIN(SIM_CLK, false, 0, 0,
- PMM_REG3, 24, 2,
- 0, 0, 0,
- PMM_REG10, 0, 8,
- AON_MUX(0x0, "SIM"), /* sim_clk */
- AON_MUX(0x1, "BGPIO")), /* gpio117 */
-
- ZX_PIN(SIM_DATA, false, 0, 0,
- PMM_REG3, 26, 2,
- 0, 0, 0,
- PMM_REG10, 0, 8,
- AON_MUX(0x0, "SIM"), /* sim_data */
- AON_MUX(0x1, "BGPIO")), /* gpio118 */
-
- ZX_PIN(EXT_INT8, true, PMM_REG11, 0,
- PMM_REG4, 0, 2,
- PMM_REG10, 0, 2,
- PMM_REG11, 0, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio119 */
- AON_MUX(0x1, "EXT_INT8"), /* ext_int8 */
- AON_MUX(0x2, "UART0"), /* uart0_rts */
- PD_MUX(0x3, "PWM0")), /* pwm0 */
-
- ZX_PIN(EXT_INT9, true, PMM_REG11, 1,
- PMM_REG4, 2, 2,
- PMM_REG10, 2, 2,
- PMM_REG11, 2, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio120 */
- AON_MUX(0x1, "EXT_INT9"), /* ext_int9 */
- AON_MUX(0x2, "UART0"), /* uart0_cts */
- PD_MUX(0x3, "PWM1")), /* pwm1 */
-
- ZX_PIN(EXT_INT10, true, PMM_REG11, 2,
- PMM_REG4, 4, 2,
- PMM_REG10, 4, 2,
- PMM_REG11, 4, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio121 */
- AON_MUX(0x1, "EXT_INT10"), /* ext_int10 */
- PD_MUX(0x3, "UART2")), /* uart2_rxd */
-
- ZX_PIN(EXT_INT11, true, PMM_REG11, 3,
- PMM_REG4, 6, 2,
- PMM_REG10, 6, 2,
- PMM_REG11, 6, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio122 */
- AON_MUX(0x1, "EXT_INT11"), /* ext_int11 */
- PD_MUX(0x3, "UART2")), /* uart2_txd */
-
- ZX_PIN(EXT_INT12, true, PMM_REG11, 4,
- PMM_REG4, 8, 2,
- PMM_REG10, 8, 2,
- PMM_REG11, 8, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio123 */
- AON_MUX(0x1, "EXT_INT12"), /* ext_int12 */
- PD_MUX(0x3, "UART2")), /* uart2_rts */
-
- ZX_PIN(EXT_INT13, true, PMM_REG11, 5,
- PMM_REG4, 10, 2,
- PMM_REG10, 10, 2,
- PMM_REG11, 10, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio124 */
- AON_MUX(0x1, "EXT_INT13"), /* ext_int13 */
- PD_MUX(0x3, "UART2")), /* uart2_cts */
-
- ZX_PIN(EXT_INT14, true, PMM_REG11, 6,
- PMM_REG4, 12, 2,
- 0, 0, 0,
- PMM_REG11, 12, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio125 */
- AON_MUX(0x1, "EXT_INT14"), /* ext_int14 */
- PD_MUX(0x0, "UART1")), /* uart1_rts */
-
- ZX_PIN(EXT_INT15, true, PMM_REG11, 7,
- PMM_REG4, 14, 2,
- 0, 0, 0,
- PMM_REG11, 14, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio126 */
- AON_MUX(0x1, "EXT_INT15"), /* ext_int15 */
- PD_MUX(0x0, "UART1")), /* uart1_cts */
-
- ZX_PIN(GPIO127, false, 0, 0,
- PMM_REG4, 16, 2,
- 0, 0, 0,
- PMM_REG11, 16, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio127 */
- AON_MUX(0x1, "EXT_INT8"), /* ext_int8 */
- AON_MUX(0x2, "KEY")), /* key_col3 */
-
- ZX_PIN(GPIO128, false, 0, 0,
- PMM_REG4, 18, 2,
- 0, 0, 0,
- PMM_REG11, 18, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio128 */
- AON_MUX(0x1, "EXT_INT9"), /* ext_int9 */
- AON_MUX(0x2, "KEY")), /* key_col4 */
-
- ZX_PIN(GPIO129, false, 0, 0,
- PMM_REG4, 20, 2,
- 0, 0, 0,
- PMM_REG11, 20, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio129 */
- AON_MUX(0x1, "EXT_INT10"), /* ext_int10 */
- AON_MUX(0x2, "KEY")), /* key_col5 */
-
- ZX_PIN(GPIO130, false, 0, 0,
- PMM_REG4, 22, 2,
- 0, 0, 0,
- PMM_REG11, 22, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio130 */
- AON_MUX(0x1, "EXT_INT11"), /* ext_int11 */
- AON_MUX(0x2, "KEY")), /* key_row2 */
-
- ZX_PIN(GPIO131, false, 0, 0,
- PMM_REG4, 24, 2,
- 0, 0, 0,
- PMM_REG11, 24, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio131 */
- AON_MUX(0x1, "EXT_INT12"), /* ext_int12 */
- AON_MUX(0x2, "KEY")), /* key_row3 */
-
- ZX_PIN(GPIO132, false, 0, 0,
- PMM_REG4, 26, 2,
- 0, 0, 0,
- PMM_REG11, 26, 2,
- AON_MUX(0x0, "BGPIO"), /* gpio132 */
- AON_MUX(0x1, "EXT_INT13"), /* ext_int13 */
- AON_MUX(0x2, "KEY")), /* key_row4 */
-
- ZX_PIN(SIM1_RST, true, PMM_REG10, 27,
- PMM_REG2, 22, 2,
- 0, 0, 0,
- PMM_REG16, 0, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio133 */
- AON_MUX(0x1, "SIM1")), /* sim1_rst */
-
- ZX_PIN(SIM1_CLK, true, PMM_REG10, 28,
- PMM_REG2, 24, 2,
- 0, 0, 0,
- PMM_REG16, 8, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio134 */
- AON_MUX(0x1, "SIM1")), /* sim1_clk */
-
- ZX_PIN(SIM1_DATA, true, PMM_REG10, 29,
- PMM_REG2, 26, 2,
- 0, 0, 0,
- PMM_REG16, 16, 8,
- AON_MUX(0x0, "BGPIO"), /* gpio135 */
- AON_MUX(0x1, "SIM1")), /* sim1_data */
-
-
- /* nomux pins */
-// ZX_PIN_NOMUX(SYS_CLK_IN, PMM_REG1, 0, ZX_MUX(0, FUNC_NOMUX)),
-// ZX_PIN_NOMUX(DIG_32K_IN, PMM_REG1, 7, ZX_MUX(0, FUNC_NOMUX)),
-};
-
-static struct zx_pinctrl_soc_info zx297520v3_pinctrl_info = {
- .pins = zx297520v3_pins,
- .npins = ARRAY_SIZE(zx297520v3_pins),
-};
-
-static int zx297520v3_pinctrl_probe(struct platform_device *pdev)
-{
- return zx_pinctrl_init(pdev, &zx297520v3_pinctrl_info);
-}
-
-static const struct of_device_id zx297520v3_pinctrl_match[] = {
- { .compatible = "zte,zx297520v3-pmm" },
- {},
-};
-
-static struct platform_driver zx297520v3_pinctrl_driver = {
- .probe = zx297520v3_pinctrl_probe,
- .driver = {
- .name = "zx297520v3-pinctrl",
- .of_match_table = zx297520v3_pinctrl_match,
- },
-};
-
-static int __init zx297520v3_pinctrl_init(void)
-{
- return platform_driver_register(&zx297520v3_pinctrl_driver);
-}
-arch_initcall(zx297520v3_pinctrl_init);
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/pinctrl/zte/pinctrl-zx297520v3.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/pinctrl/zte/pinctrl-zx297520v3.h
deleted file mode 100644
index 23a729a..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/pinctrl/zte/pinctrl-zx297520v3.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2021 ZTE Technology Co., Ltd.
- */
-
-#ifndef __PINCTRL_ZX297520V3_H
-#define __PINCTRL_ZX297520V3_H
-
-#define NAND_WE 0
-#define NAND_CSN 1
-#define NAND_READY 2
-#define NAND_CLE 3
-#define NAND_ALE 4
-#define NAND_RE 5
-#define NAND_WP 6
-#define NAND_D0 7
-#define NAND_D1 8
-#define NAND_D2 9
-#define NAND_D3 10
-#define NAND_D4 11
-#define NAND_D5 12
-#define NAND_D6 13
-#define NAND_D7 14
-#define CLK_OUT0 15
-#define CLK_OUT1 16
-#define CLK_OUT2 17
-#define CLK_32K_OUT 18
-#define RMII_CLKI 19
-#define RMII_CLKO 20
-#define CLK_REQ0 21
-#define CLK_REQ1 22
-#define PWRCTRL 23
-#define PSHOLD 24 /* gpio65 */
-#define SSP0_CS 25
-#define SSP0_CLK 26
-#define SSP0_RXD 27
-#define SSP0_TXD 28
-#define UART0_RXD 29
-#define UART0_TXD 30
-#define UART0_CTS 31
-#define UART0_RTS 32
-#define UART1_RXD 33
-#define UART1_TXD 34
-#define I2S0_WS 35
-#define I2S0_CLK 36
-#define I2S0_DIN 37
-#define I2S0_DOUT 38
-#define I2S1_WS 39
-#define I2S1_CLK 40
-#define I2S1_DIN 41
-#define I2S1_DOUT 42
-#define I2C0_SCL 43
-#define I2C0_SDA 44
-#define I2C1_SCL 45
-#define I2C1_SDA 46
-#define EXT_INT0 47
-#define EXT_INT1 48
-#define EXT_INT2 49
-#define EXT_INT3 50
-#define EXT_INT4 51
-#define EXT_INT5 52
-#define EXT_INT6 53
-#define EXT_INT7 54
-#define RMII_TXEN 55
-#define RMII_RXEN 56
-#define RMII_RXD0 57
-#define RMII_RXD1 58
-#define RMII_TXD0 59
-#define RMII_TXD1 60
-#define MDC_SCLK 61
-#define MDC_SDIO 62
-#define PHY_RST 63
-#define PHY_INT 64
-#define PHY_WAKE 65 /* gpio65 */
-#define SD0_CLK 66
-#define SD0_CMD 67
-#define SD0_D0 68
-#define SD0_D1 69
-#define SD0_D2 70
-#define SD0_D3 71
-#define SD1_CLK 72
-#define SD1_CMD 73
-#define SD1_D0 74
-#define SD1_D1 75
-#define SD1_D2 76
-#define SD1_D3 77
-#define GPIO78 78
-#define GPIO79 79
-#define GPIO80 80
-#define GPIO81 81
-#define GPIO82 82
-#define KEY_COL0 83
-#define KEY_COL1 84
-#define KEY_ROW0 85
-#define KEY_ROW1 86
-#define CAM_SPI_CS 87
-#define CAM_SPI_CLK 88
-#define CAM_SPI_D0 89
-#define CAM_SPI_D1 90
-#define CAM_SPI_D2 91
-#define CAM_SPI_D3 92
-#define SPIFC_CS 93
-#define SPIFC_CLK 94
-#define SPIFC_D0 95
-#define SPIFC_D1 96
-#define SPIFC_D2 97
-#define SPIFC_D3 98
-#define GPIO99 99
-#define GPIO100 100
-#define GPIO101 101
-#define GPIO102 102
-#define GPIO103 103
-#define GPIO104 104
-#define GPIO105 105
-#define GPIO106 106
-#define GPIO107 107
-#define GPIO108 108
-#define GPIO109 109
-#define GPIO110 110
-#define GPIO111 111
-#define GPIO112 112
-#define GPIO113 113
-#define GPIO114 114
-#define GPIO115 115
-#define SIM_RST 116
-#define SIM_CLK 117
-#define SIM_DATA 118
-#define EXT_INT8 119
-#define EXT_INT9 120
-#define EXT_INT10 121
-#define EXT_INT11 122
-#define EXT_INT12 123
-#define EXT_INT13 124
-#define EXT_INT14 125
-#define EXT_INT15 126
-#define GPIO127 127
-#define GPIO128 128
-#define GPIO129 129
-#define GPIO130 130
-#define GPIO131 131
-#define GPIO132 132
-#define SIM1_RST 133
-#define SIM1_CLK 134
-#define SIM1_DATA 135
-
-
-#define FUNC_GPIO "BGPIO"
-#define FUNC_NOMUX "NOMUX"
-
-struct zx_pinctrl_soc_info {
- const struct pinctrl_pin_desc *pins;
- unsigned int npins;
-};
-
-struct zx_mux_desc {
- const char *name;
- unsigned char mux_val;
-};
-
-struct zx_pin_data {
- /* top: when true, bit set -- pd bit clr -- aon */
- bool top;
- unsigned short toffset;
- unsigned short tbitpos;
-
- unsigned short aoffset;
- unsigned short abitpos;
- unsigned short awidth;
-
- unsigned short poffset;
- unsigned short pbitpos;
- unsigned short pwidth;
-
- unsigned short coffset;
- unsigned short cbitpos;
- unsigned short cwidth;
-
- struct zx_mux_desc *muxes;
-};
-
-#define ZX_PIN(pin, ten, toff, tbp, \
- aoff, abp, awid, \
- poff, pbp, pwid, \
- coff, cbp, cwid, ...) { \
- .number = pin, \
- .name = #pin, \
- .drv_data = &(struct zx_pin_data) { \
- .top = ten, \
- .toffset = toff, \
- .tbitpos = tbp, \
- .aoffset = aoff, \
- .abitpos = abp, \
- .awidth = awid, \
- .poffset = poff, \
- .pbitpos = pbp, \
- .pwidth = pwid, \
- .coffset = coff+0x800, \
- .cbitpos = cbp, \
- .cwidth = cwid, \
- .muxes = (struct zx_mux_desc[]) { \
- __VA_ARGS__, { } }, \
- }, \
-}
-
-#define ZX_PIN_NOMUX(pin, coff, cbp, cwid, ...) { \
- .number = pin, \
- .name = #pin, \
- .drv_data = &(struct zx_pin_data) { \
- .top = false, \
- .toffset = 0, \
- .tbitpos = 0, \
- .aoffset = 0, \
- .abitpos = 0, \
- .awidth = 0, \
- .poffset = 0, \
- .pbitpos = 0, \
- .pwidth = 0, \
- .coffset = coff+0x800, \
- .cbitpos = cbp, \
- .cwidth = cwid, \
- .muxes = (struct zx_mux_desc[]) { \
- __VA_ARGS__, { } }, \
- }, \
-}
-
-
-#define ZX_RESERVED(pin) PINCTRL_PIN(pin, #pin)
-
-#define PD_MUX_FLAG BIT(7)
-#define PD_MUX(_val, _name) { \
- .name = _name, \
- .mux_val = _val | PD_MUX_FLAG, \
-}
-
-#define AON_MUX(_val, _name) { \
- .name = _name, \
- .mux_val = _val, \
-}
-
-int zx_pinctrl_init(struct platform_device *pdev,
- struct zx_pinctrl_soc_info *info);
-
-#endif /* __PINCTRL_ZX297520V3_H */
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/sc/pcu/pcu-zx297520v3.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/sc/pcu/pcu-zx297520v3.c
old mode 100644
new mode 100755
index 9481361..cac6ac9
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/sc/pcu/pcu-zx297520v3.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/sc/pcu/pcu-zx297520v3.c
@@ -344,9 +344,9 @@
.pcu_index = PCU_UART0_RXD_INT,
.gic_index = UART0_RXD_INT,
.status_index = 59,
- .wake_index = 0xff,
+ .wake_index = 42,
.int_name = "uart0_rxd",
- .irq_type = IRQ_TYPE_LEVEL_LOW,
+ .irq_type = IRQ_TYPE_EDGE_FALLING,
.wl_type = 0xff,
},
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/Kconfig b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/Kconfig
deleted file mode 100644
index 971b841..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/Kconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# pcu options
-#
-config ZTE_PCU
- bool "zte pcu support"
- depends on ARCH_ZX298501 || ARCH_ZX297520V3
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/Makefile b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/Makefile
deleted file mode 100644
index 7c6dc44..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Makefile for the soc plat drivers
-#
-
-obj-y += pcu-common.o
-obj-$(CONFIG_ARCH_ZX298501) += pcu-zx298501.o
-obj-$(CONFIG_ARCH_ZX297520V3) += pcu-zx297520v3.o
-
-#
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-common.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-common.c
deleted file mode 100644
index faa4942..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-common.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- *
- * Copyright (C) 2015-2021 ZTE-TSP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/irq.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of_device.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-
-#include <linux/soc/zte/spinlock.h>
-#include <linux/soc/zte/common.h>
-#include <linux/soc/zte/pcu.h>
-
-#include "pcu-common.h"
-
-struct zx_pcu_dev pcu_dev = {0};
-
-#define PCU_INT_CNT (pcu_dev.int_count)
-#define PCU_INT_INFO (pcu_dev.int_info)
-#define PCU_TOP (pcu_dev.top_reg_base)
-
-#define PCU_INT_CLR_BASE (PCU_TOP + INT_CLEAR1_REG)
-#define PCU_INT_POL_BASE (PCU_TOP + INT_POL1_REG)
-#define PCU_INT_TYPE_BASE (PCU_TOP + INT_TYPE1_REG)
-#define PCU_INT_WAKE_BASE (PCU_TOP + AP_INT_WAKE_DIS1_REG)
-
-#define pcu_int_reg_off(index) (index_to_reg32_off(index))
-#define pcu_int_bit_off(index) (index_to_reg32_bit_off(index))
-
-#define PCU_LOCK reg_spin_lock();
-#define PCU_UNLOCK reg_spin_unlock();
-
-#if 0
-#define pm_ram_log printk
-#else
-#define pm_ram_log(fmt, args...) \
-{ \
- zx_ramlog_printk("[PM] " fmt, ##args); \
-}
-#endif
-/**
- * helper function
- *
- */
-static unsigned int pcu_get_index_by_gic(unsigned int gic_index)
-{
- unsigned int i;
- struct zx_pcu_int_info *int_info = PCU_INT_INFO;
-
- for(i=0; i<PCU_INT_CNT; i++)
- {
- if(gic_index == int_info[i].gic_index)
- return int_info[i].pcu_index;
- }
-
- return 0xff;
-}
-
-static unsigned int pcu_get_index_by_wake(unsigned int wake_index)
-{
- unsigned int i;
- struct zx_pcu_int_info *int_info = PCU_INT_INFO;
-
- for(i=0; i<PCU_INT_CNT; i++)
- {
- if(wake_index == int_info[i].wake_index)
- return i;
- }
-
- return 0xff;
-}
-
-
-static unsigned int pcu_get_wake_index_by_gic(unsigned int gic_index)
-{
- unsigned int i;
- struct zx_pcu_int_info *int_info = PCU_INT_INFO;
-
- for(i=0; i<PCU_INT_CNT; i++)
- {
- if(gic_index == int_info[i].gic_index)
- return int_info[i].wake_index;
- }
-
- return 0xff;
-}
-
-bool irq_type_valid(unsigned int int_type)
-{
- return ((int_type==IRQ_TYPE_LEVEL_HIGH) || (int_type==IRQ_TYPE_LEVEL_LOW) || \
- (int_type==IRQ_TYPE_EDGE_RISING) || (int_type==IRQ_TYPE_EDGE_FALLING));
-}
-
-/*only pulse int need be clear*/
-void pcu_int_clear(unsigned int pcu_index)
-{
- void __iomem *reg;
- unsigned int val;
-
- reg = PCU_INT_CLR_BASE + pcu_int_reg_off(pcu_index);
- val = 1 << pcu_int_bit_off(pcu_index);
-
- PCU_LOCK
- zx_set_reg(reg, val);
- PCU_UNLOCK
-}
-EXPORT_SYMBOL(pcu_int_clear);
-
-/**
- * helper function
- *
- * get pcu level/pol configuration.
- */
-static void pcu_split_int_type(unsigned int type, unsigned int *level, unsigned int *pol)
-{
- switch (type) {
- case IRQ_TYPE_LEVEL_HIGH:
- *level = 1;
- *pol = 1;
- break;
- case IRQ_TYPE_EDGE_RISING:
- *level = 0;
- *pol = 1;
- break;
- case IRQ_TYPE_LEVEL_LOW:
- *level = 1;
- *pol= 0;
- break;
- case IRQ_TYPE_EDGE_FALLING:
- *level = 0;
- *pol = 0;
- break;
- default:
- BUG();
- }
-}
-
-/*
- * set pcu int type,
- *
- */
-void pcu_int_set_type(unsigned int pcu_index, unsigned int type)
-{
- void __iomem *type_reg;
- void __iomem *pol_reg;
- unsigned int bit_off;
- unsigned int level;
- unsigned int pol;
-
- type_reg = PCU_INT_TYPE_BASE + pcu_int_reg_off(pcu_index);
- pol_reg = PCU_INT_POL_BASE + pcu_int_reg_off(pcu_index);
- bit_off = pcu_int_bit_off(pcu_index);
-
- pcu_split_int_type(type, &level, &pol);
-
- PCU_LOCK
- zx_wrie_bit(type_reg, bit_off, level);
- zx_wrie_bit(pol_reg, bit_off, pol);
- PCU_UNLOCK
-
- pcu_int_clear(pcu_index);
-}
-EXPORT_SYMBOL(pcu_int_set_type);
-
-/**
- * set wakeup enable.
- *
- *
- */
-static void pcu_int_wakeup(unsigned int wake_index, bool enable)
-{
- void __iomem *reg;
- unsigned int off;
- unsigned int val;
-
- reg = PCU_INT_WAKE_BASE + pcu_int_reg_off(wake_index);
- off = pcu_int_bit_off(wake_index);
- val = enable ? 0 : 1;
-
- PCU_LOCK
- zx_wrie_bit(reg, off, val);
- PCU_UNLOCK
-}
-
-/**
- * get wakeup enable status.
- *
- * return: 1 - int wakeup enabled
- */
-static bool pcu_get_int_wakeup(unsigned int wake_index)
-{
- void __iomem *reg;
- unsigned int off;
- unsigned int val;
-
- reg = PCU_INT_WAKE_BASE + pcu_int_reg_off(wake_index);
- off = pcu_int_bit_off(wake_index);
-
- PCU_LOCK
- val = zx_read_reg(reg);
- PCU_UNLOCK
-
- if (BIT(off) & val)
- return false;
-
- return true;
-}
-
-/**
- * init pcu before open irq when system start.
- *
- */
-void __init pcu_init(void)
-{
- int i;
- struct zx_pcu_int_info *int_info = PCU_INT_INFO;
-
- pr_info("[PCU] PCU_INIT begin.\n");
-
- /*set default int type/pol, and clear fake int*/
-#if 0
- for(i=0; i<PCU_INT_CNT; i++)
- {
- if(!irq_type_valid(int_info[i].irq_type))
- continue;
-
- pcu_int_set_type(int_info[i].pcu_index, int_info[i].irq_type);
- }
-#endif
-
- /* all wake src disabled */
- for(i=0; i<AP_INT_WAKE_CNT; i++)
- pcu_int_wakeup(i, false);
-
- pr_info("[PCU] PCU_INIT end.\n");
-}
-
-#ifdef CONFIG_ARCH_ZX297520V3
-extern unsigned int gic_wake_enable[3];
-#endif
-
-/**
- * set wakeup enable by gic.
- *
- *
- */
-int pcu_set_irq_wake(unsigned int gic_index, bool enable)
-{
- unsigned int wake_index;
-
- wake_index = pcu_get_wake_index_by_gic(gic_index);
- if(wake_index == 0xff)
- return -EINVAL;
-
-#ifdef CONFIG_ARCH_ZX297520V3
- if(gic_index<32)
- ;
- else if(gic_index < (32 + 32))
- gic_wake_enable[0] |=1<<(gic_index -32);
- else if(gic_index < (32 + 64))
- gic_wake_enable[1] |=1<<(gic_index -64);
- else if (gic_index < 77)
- gic_wake_enable[2] |=1<<(gic_index -96);
-#endif
-
- pcu_int_wakeup(wake_index, enable);
-
- return 0;
-}
-
-/**
- * set pcu type by gic.
- *
- *
- */
-int pcu_set_irq_type(unsigned int gic_index, unsigned int type)
-{
- unsigned int pcu_index;
-
- pcu_index = pcu_get_index_by_gic(gic_index);
- if(pcu_index == 0xff)
- return -EINVAL;
-
- pcu_int_set_type(pcu_index, type);
-
- return 0;
-}
-EXPORT_SYMBOL(pcu_set_irq_type);
-
-/**
- * clr pcu int by gic.
- *
- *
- */
-int pcu_clr_irq_pending(unsigned int gic_index)
-{
- unsigned int pcu_index;
-
- pcu_index = pcu_get_index_by_gic(gic_index);
- if(pcu_index == 0xff)
- return -EINVAL;
-
- pcu_int_clear(pcu_index);
-
- return 0;
-}
-EXPORT_SYMBOL(pcu_clr_irq_pending);
-
-#if 0
-void pcu_get_wake_cause(void)
-{
- unsigned int int_status[2];
- u64 int_status_64;
- int i;
- int index_found = 0xff;
- int info_index;
- struct zx_pcu_int_info *int_info = PCU_INT_INFO;
-
- /* when wake up, the level is high&the value is 0*/
- PCU_LOCK
- int_status[0] = zx_read_reg(PCU_TOP + INT_READOUT1_REG);
- int_status[1] = zx_read_reg(PCU_TOP + INT_READOUT2_REG);
- PCU_UNLOCK
- int_status_64 = (u64)int_status[0] | ((u64)int_status[1] << 32);
-
- pm_ram_log(" int_status_64: 0x%llx \n", int_status_64);
-
- for(i=0; i<AP_INT_WAKE_CNT; i++) {
- if (!pcu_get_int_wakeup(i))
- continue;
-
- info_index = pcu_get_index_by_wake(i);
- pm_ram_log(" wake src: %d [%s]\n", i, int_info[info_index].int_name);
-
- if (BIT_ULL(i) & int_status_64)
- continue;
-
- index_found = info_index;
- break;
- }
-
- if(index_found != 0xff)
- {
- pm_ram_log(" wake: %d [%s]\n", int_info[index_found].gic_index, int_info[index_found].int_name);
- pm_ram_log(" pcu int status:%x %x\n", int_status[0], int_status[1]);
- }
- else
- {
- pm_ram_log(" wake abnormal\n");
- pm_ram_log(" pcu int status:%x %x\n", int_status[0], int_status[1]);
- }
-}
-#endif
-/*
-int __weak zx_pcu_init(void)
-{
- return -ESRCH;
-}
-*/
-#if 0
-int __weak zx_pcu_init(struct device *dev)
-{
- return -ESRCH;
-}
-
-static int zx_pcu_probe(struct platform_device* pdev)
-{
- int (*init_fn)(struct device *dev);
-
- pr_info("[PCU] zx_pcu probe enter... \n");
-
- init_fn = of_device_get_match_data(&pdev->dev);
- if (!init_fn) {
- dev_err(&pdev->dev, "Error: No device match found\n");
- return -ENODEV;
- }
-
- return init_fn(&pdev->dev);
-}
-
-static const struct of_device_id zx_pcu_dt_ids[] = {
- {.compatible = "zte,zx298501-pcu", .data = &zx_pcu_init },
- {}
-};
-MODULE_DEVICE_TABLE(of, zx_pcu_dt_ids);
-
-struct platform_driver zx_pcu_driver = {
- .driver = {
- .name = "zx_pcu",
- .of_match_table = of_match_ptr(zx_pcu_dt_ids),
- },
- .probe = zx_pcu_probe,
-};
-
-static int zx_pcu_driver_init(void)
-{
- pr_info("[PCU] zx_pcu_driver_init enter... \n");
- return platform_driver_register(&zx_pcu_driver);
-}
-postcore_initcall(zx_pcu_driver_init);
-#endif
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-common.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-common.h
deleted file mode 100644
index 9a677ef..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-common.h
+++ /dev/null
@@ -1,67 +0,0 @@
-
-#ifndef _PCU_COMMON_H
-#define _PCU_COMMON_H
-
-struct zx_pcu_int_info
-{
- unsigned int pcu_index; /* 2 -- reg0 bit2
- 72 -- reg2 bit6 */
- unsigned int gic_index;
- unsigned status_index; /* index to PCU_INT_READOUT_REG */
- unsigned int wake_index; /* index to AP INT WAKE DIS1 REG */
- char *int_name;
- unsigned int irq_type; /*irq type enter to pcu*/
-};
-
-struct zx_pcu_dev
-{
- struct device_node *np;
- void __iomem *top_reg_base;
- void __iomem *ap_reg_base;
- u32 *wake_src;
- u32 int_count;
- struct zx_pcu_int_info *int_info;
-};
-
-#ifdef CONFIG_ARCH_ZX298501
-#include "pcu-zx298501.h"
-#endif
-
-#ifdef CONFIG_ARCH_ZX297520V3
-#include "pcu-zx297520v3.h"
-#endif
-
-
-extern struct zx_pcu_dev pcu_dev;
-
-#ifdef CONFIG_ZTE_PCU
-
-void __init pcu_init(void);
-int pcu_set_irq_type(unsigned int gic_index, unsigned int type);
-int pcu_clr_irq_pending(unsigned int gic_index);
-int pcu_set_irq_wake(unsigned int gic_index, bool enable);
-
-#else
-static inline int pcu_set_irq_type(unsigned int gic_index, unsigned int type)
-{
- return -ENODEV;
-}
-
-static inline int pcu_clr_irq_pending(unsigned int gic_index)
-{
- return 0;
-}
-
-static inline int pcu_set_irq_wake(unsigned int gic_index, bool enable)
-{
- return 0;
-}
-
-static inline int zx_pcu_init(void)
-{
- return 0;
-}
-
-#endif
-
-#endif /* _PCU_COMMON_H */
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-zx297520v3.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-zx297520v3.c
deleted file mode 100644
index e1ae364..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-zx297520v3.c
+++ /dev/null
@@ -1,879 +0,0 @@
-/*
- *
- * Copyright (C) 2015-2022 ZTE-TSP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/irq.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of_device.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/interrupt.h>
-#include <linux/irqdomain.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/percpu.h>
-#include <linux/refcount.h>
-#include <linux/slab.h>
-#include <linux/irqchip.h>
-#include <linux/suspend.h>
-#include <linux/syscore_ops.h>
-#include <linux/mfd/syscon.h>
-#include <linux/regmap.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-#include <linux/soc/zte/common.h>
-#include <linux/soc/zte/spinlock.h>
-#include <linux/soc/zte/pcu.h>
-#include <dt-bindings/soc/zx297520v3-irq.h>
-
-#include "pcu-common.h"
-
-#if 0
-
-#define pm_ram_log(fmt, args...) \
-{ \
- pm_printk("[SLP] " fmt, ##args); \
-}
-#else
-#define pm_ram_log(fmt, args...) \
-{ \
- printk(KERN_INFO "[SLP] " fmt, ##args); \
-}
-
-#endif
-
-#define ZX_IRQ_NUM (IRQ_ZX297520V3_SPI_NUM + 32)
-
-#define PCU_LOCK reg_spin_lock();
-#define PCU_UNLOCK reg_spin_unlock();
-
-static struct zx_pcu_int_info zx297520v3_pcu_int_info[] =
-{
- {
- .pcu_index = PCU_AP_TIMER1_INT,
- .gic_index = AP_TIMER1_INT,
- .status_index = 51,
- .wake_index = 0,
- .int_name = "ap_timer1",
- .irq_type = IRQ_TYPE_EDGE_RISING,
- },
- {
- .pcu_index = PCU_AP_TIMER2_INT,
- .gic_index = AP_TIMER2_INT,
- .status_index = 52,
- .wake_index = 1,
- .int_name = "ap_timer2",
- .irq_type = IRQ_TYPE_EDGE_RISING,
- },
- {
- .pcu_index = PCU_ICP_PS2AP_INT,
- .gic_index = ICP_PS2AP_INT,
- .status_index = 53,
- .wake_index = 2,
- .int_name = "icp_ps_ap",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_USB_POWERDWN_UP_INT,
- .gic_index = USB_POWERDWN_UP_INT,
- .status_index = 6,
- .wake_index = 3,
- .int_name = "usb_up",
- .irq_type = IRQ_TYPE_EDGE_RISING,
- },
- {
- .pcu_index = PCU_USB_POWERDWN_DOWN_INT,
- .gic_index = USB_POWERDWN_DOWN_INT,
- .status_index = 7,
- .wake_index = 4,
- .int_name = "usb_down",
- .irq_type = IRQ_TYPE_EDGE_FALLING,
- },
- {
- .pcu_index = PCU_HSIC_POWERDWN_UP_INT,
- .gic_index = HSIC_POWERDWN_UP_INT,
- .status_index = 8,
- .wake_index = 5,
- .int_name = "hsic_up",
- .irq_type = IRQ_TYPE_EDGE_RISING,
- },
- {
- .pcu_index = PCU_HSIC_POWERDWN_DOWN_INT,
- .gic_index = HSIC_POWERDWN_DOWN_INT,
- .status_index = 9,
- .wake_index = 6,
- .int_name = "hsic_down",
- .irq_type = IRQ_TYPE_EDGE_FALLING,
- },
- {
- .pcu_index = PCU_ICP_M02AP_INT,
- .gic_index = ICP_M02AP_INT,
- .status_index = 54,
- .wake_index = 7,
- .int_name = "icp_m0_ap",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_RTC_ALARM_INT,
- .gic_index = RTC_ALARM_INT,
- .status_index = 12,
- .wake_index = 8,
- .int_name = "rtc_alarm",
- .irq_type = IRQ_TYPE_LEVEL_LOW,
- },
- {
- .pcu_index = PCU_RTC_TIMER_INT,
- .gic_index = RTC_TIMER_INT,
- .status_index = 13,
- .wake_index = 9,
- .int_name = "rtc_timer",
- .irq_type = IRQ_TYPE_LEVEL_LOW,
- },
- {
- .pcu_index = PCU_KEYPAD_INT,
- .gic_index = KEYPAD_INT,
- .status_index = 14,
- .wake_index = 10,
- .int_name = "kpd",
- .irq_type = IRQ_TYPE_EDGE_RISING,
- },
- {
- .pcu_index = PCU_SD1_DATA1_INT,
- .gic_index = SD1_DATA1_INT,
- .status_index = 15,
- .wake_index = 11,
- .int_name = "sd1_d1",
- .irq_type = IRQ_TYPE_LEVEL_LOW,
- },
- {
- .pcu_index = PCU_EX0_INT,
- .gic_index = EX0_INT,
- .status_index = 30,
- .wake_index = 14,
- .int_name = "ext0",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX1_INT,
- .gic_index = EX1_INT,
- .status_index = 31,
- .wake_index = 15,
- .int_name = "ext1",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX2_INT,
- .gic_index = EX2_INT,
- .status_index = 32,
- .wake_index = 16,
- .int_name = "ext2",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX3_INT,
- .gic_index = EX3_INT,
- .status_index = 33,
- .wake_index = 17,
- .int_name = "ext3",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX4_INT,
- .gic_index = EX4_INT,
- .status_index = 34,
- .wake_index = 18,
- .int_name = "ext4",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX5_INT,
- .gic_index = EX5_INT,
- .status_index = 35,
- .wake_index = 19,
- .int_name = "ext5",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX6_INT,
- .gic_index = EX6_INT,
- .status_index = 36,
- .wake_index = 20,
- .int_name = "ext6",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX7_INT,
- .gic_index = EX7_INT,
- .status_index = 37,
- .wake_index = 21,
- .int_name = "ext7",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX8_INT,
- .gic_index = EX8IN1_INT,
- .status_index = 38,
- .wake_index = 22,
- .int_name = "ext8",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX9_INT,
- .gic_index = EX8IN1_INT,
- .status_index = 39,
- .wake_index = 23,
- .int_name = "ext9",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX10_INT,
- .gic_index = EX8IN1_INT,
- .status_index = 40,
- .wake_index = 24,
- .int_name = "ext10",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX11_INT,
- .gic_index = EX8IN1_INT,
- .status_index = 41,
- .wake_index = 25,
- .int_name = "ext11",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX12_INT,
- .gic_index = EX8IN1_INT,
- .status_index = 42,
- .wake_index = 26,
- .int_name = "ext12",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX13_INT,
- .gic_index = EX8IN1_INT,
- .status_index = 43,
- .wake_index = 27,
- .int_name = "ext13",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX14_INT,
- .gic_index = EX8IN1_INT,
- .status_index = 44,
- .wake_index = 28,
- .int_name = "ext14",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_EX15_INT,
- .gic_index = EX8IN1_INT,
- .status_index = 45,
- .wake_index = 29,
- .int_name = "ext15",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_SD0_DATA1_INT,
- .gic_index = SD0_DATA1_INT,
- .status_index = 2,
- .wake_index = 30,
- .int_name = "sd0_d1",
- .irq_type = IRQ_TYPE_LEVEL_LOW,
- },
- {
- .pcu_index = PCU_ICP_PHY2AP_INT,
- .gic_index = ICP_PHY2AP_INT,
- .status_index = 55,
- .wake_index = 31,
- .int_name = "icp_phy_ap",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_GMACPHY_WAKE_INT,
- .gic_index = GMACPHY_WAKE_INT,
- .status_index = 60,
- .wake_index = 0xff,
- .int_name = "gmacphy_wake",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_UART0_RXD_INT,
- .gic_index = UART0_RXD_INT,
- .status_index = 59,
- .wake_index = 0xff,
- .int_name = "uart0_rxd",
- .irq_type = IRQ_TYPE_LEVEL_LOW,
- },
- {
- .pcu_index = PCU_GMAC_INT,
- .gic_index = GMAC_INT,
- .status_index = 16,
- .wake_index = 0xff,
- .int_name = "gmac",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
- {
- .pcu_index = PCU_GMACPHY_INT,
- .gic_index = GMACPHY_INT,
- .status_index = 61,
- .wake_index = 0xff,
- .int_name = "gmacphy",
- .irq_type = IRQ_TYPE_LEVEL_HIGH,
- },
-};
-
-static int zx_pcu_get_irqchip_state(struct irq_data *data,
- enum irqchip_irq_state which, bool *val)
-{
- data = data->parent_data;
-
- if (data->chip->irq_get_irqchip_state)
- return data->chip->irq_get_irqchip_state(data, which, val);
-
- return -ENOSYS;
-}
-
-static int zx_pcu_set_irqchip_state(struct irq_data *data,
- enum irqchip_irq_state which, bool val)
-{
- data = data->parent_data;
-
- if (data->chip->irq_set_irqchip_state)
- return data->chip->irq_set_irqchip_state(data, which, val);
-
- return -ENOSYS;
-}
-
-static int zx_pcu_nmi_setup(struct irq_data *data)
-{
- data = data->parent_data;
-
- if (data->chip->irq_nmi_setup)
- return data->chip->irq_nmi_setup(data);
-
- return -ENOSYS;
-}
-
-static void zx_pcu_nmi_teardown(struct irq_data *data)
-{
- data = data->parent_data;
-
- if (data->chip->irq_nmi_teardown)
- data->chip->irq_nmi_teardown(data);
-}
-
-static int zx_pcu_set_wake(struct irq_data *data, unsigned int on)
-{
- pcu_set_irq_wake(data->hwirq, on);
-
-/* pr_info("irq:%d, onoff:%d", data->hwirq, on);*/
-
- return 0;
-}
-
-static void zx_pcu_eoi_irq(struct irq_data *data)
-{
- pcu_clr_irq_pending(data->hwirq);
-
- irq_chip_eoi_parent(data);
-}
-
-static int zx_pcu_set_type(struct irq_data *data, unsigned int type)
-{
- unsigned int new_type = type;
-
- if(!pcu_set_irq_type(data->hwirq, type))
- new_type = IRQ_TYPE_LEVEL_HIGH;
-
- return irq_chip_set_type_parent(data, new_type);
-}
-
-static int zx_pcu_set_affinity(struct irq_data *data,
- const struct cpumask *dest, bool force)
-{
-/*
- if (data->hwirq == IRQ_ZX298501_AP_TIMER1)
- return irq_chip_set_affinity_parent(data, cpumask_of(0), force); // ???
- else
-*/ return irq_chip_set_affinity_parent(data, dest, force);
-}
-
-static struct irq_chip zx_pcu_chip = {
- .name = "PCU",
- .irq_eoi = zx_pcu_eoi_irq,
- .irq_mask = irq_chip_mask_parent,
- .irq_unmask = irq_chip_unmask_parent,
- .irq_set_wake = zx_pcu_set_wake,
- .irq_set_type = zx_pcu_set_type,
-
- .irq_set_affinity = zx_pcu_set_affinity,
- .irq_get_irqchip_state = zx_pcu_get_irqchip_state,
- .irq_set_irqchip_state = zx_pcu_set_irqchip_state,
- .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
- .irq_nmi_setup = zx_pcu_nmi_setup,
- .irq_nmi_teardown = zx_pcu_nmi_teardown,
- .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED,
-};
-
-static int zx_pcu_domain_translate(struct irq_domain *d,
- struct irq_fwspec *fwspec,
- unsigned long *hwirq,
- unsigned int *type)
-{
- if (is_of_node(fwspec->fwnode)) {
- if (fwspec->param_count != 3)
- return -EINVAL;
-
- /* No PPI should point to this domain */
- if (fwspec->param[0] != 0)
- return -EINVAL;
-
- *hwirq = fwspec->param[1];
- *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
- return 0;
- }
-
- return -EINVAL;
-}
-
-static int zx_pcu_domain_alloc(struct irq_domain *domain,
- unsigned int virq,
- unsigned int nr_irqs, void *data)
-{
- struct irq_fwspec *fwspec = data;
- struct irq_fwspec parent_fwspec;
- struct zx_pcu_dev *pcu = domain->host_data;
- irq_hw_number_t hwirq;
- unsigned int i;
-
- if (fwspec->param_count != 3)
- return -EINVAL; /* Not GIC compliant */
- if (fwspec->param[0] != GIC_SPI)
- return -EINVAL; /* No PPI should point to this domain */
-
- hwirq = fwspec->param[1];
- if (hwirq >= ZX_IRQ_NUM)
- return -EINVAL;
-
- for (i = 0; i < nr_irqs; i++) {
- irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
- &zx_pcu_chip,
- (void __force *)pcu->top_reg_base);
- }
-
- parent_fwspec = *fwspec;
- parent_fwspec.fwnode = domain->parent->fwnode;
- return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
- &parent_fwspec);
-}
-
-static const struct irq_domain_ops zx_pcu_domain_ops = {
- .translate = zx_pcu_domain_translate,
- .alloc = zx_pcu_domain_alloc,
- .free = irq_domain_free_irqs_common,
-};
-
-static int __init zx_pcu_init(struct device_node *node,
- struct device_node *parent)
-{
- struct irq_domain *parent_domain, *domain;
- struct zx_pcu_dev *pcu;
-
- if (!parent) {
- pr_err("%pOF: no parent found\n", node);
- return -ENODEV;
- }
-
- parent_domain = irq_find_host(parent);
- if (!parent_domain) {
- pr_err("%pOF: unable to obtain parent domain\n", node);
- return -ENXIO;
- }
-
- pcu = &pcu_dev;
- pcu->np = node;
- pcu->top_reg_base = of_iomap(node, 0);
- WARN(!pcu->top_reg_base, "unable to map top pcu registers\n");
-
- pcu->int_info = zx297520v3_pcu_int_info;
- pcu->int_count = ARRAY_SIZE(zx297520v3_pcu_int_info);
-
- pcu_init();
-
- domain = irq_domain_add_hierarchy(parent_domain, 0, ZX_IRQ_NUM,
- node, &zx_pcu_domain_ops,
- pcu);
- if (!domain) {
- pr_err("%pOF: failed to allocated domain\n", node);
- return -ENOMEM;
- }
-
-// set_smp_cross_call();
- pm_pcu_init();
-
- return 0;
-}
-
-IRQCHIP_DECLARE(zx297520v3_pcu, "zte,zx297520v3-pcu", zx_pcu_init);
-
-/* pcu debug */
-#ifdef CONFIG_PM
-#define PCU_TOP (pcu_dev.top_reg_base)
-
-#define ARM_AP_CONFIG_REG (PCU_TOP + 0x0)
-#define ARM_AP_SLEEP_TIME_REG (PCU_TOP + 4*0x3C)
-#define AP_INT_WAKE_DIS_REG (PCU_TOP + 4*0xD)
-#define CORE_SWITCH_CONFIG_REG (PCU_TOP + 4*0x2b)
-
-#define M0_INT_WAKE_DIS_REG (PCU_TOP + 4*0xE)
-#define PCU_INT_READOUT_REG1 (PCU_TOP + 4*0x1EB)
-#define PCU_INT_READOUT_REG2 (PCU_TOP + 4*0x1EC)
-#define PCU_INT_READOUT_REG3 (PCU_TOP + 4*0x1ED)
-
-
-/*ARM_AP_CONFIG_REG*/
-#define PCU_SLEEP_MODE (1U << 0)
-#define PCU_POWEROFF_MODE (1U << 1)
-#define PCU_L2_CLK_GATE (1U << 2) /*1-can turn off*/
-#define PCU_SLEEP_2M0 (1U << 3)
-#define PCU_SLEEP_DONE_BYPASS (1U << 4)
-#define PCU_SW_CONFIG_MASK (1U << 5) /* ????? */
-
-#define PCU_MODE_MASK (0x3U << 0)
-
-/*ARM_AP_SLEEP_TIME_REG*/
-#define PCU_AP_SLEEP_TIME_DIS (1U << 31)
-
-
-
-/* low power function */
-extern unsigned int pm_get_wakesource(void);
-
-/**
- * clear pcu sleep mode.
- *
- */
-void pm_clear_pcu(void)
-{
- zx_clr_reg(ARM_AP_CONFIG_REG, PCU_MODE_MASK);
-}
-
-void pm_pcu_init(void)
-{
- zx_clr_reg(ARM_AP_CONFIG_REG, PCU_MODE_MASK);
- zx_set_reg(ARM_AP_CONFIG_REG, PCU_L2_CLK_GATE);
- zx_write_reg(AP_INT_WAKE_DIS_REG, ~(pm_get_wakesource()));
-}
-
-void zx_apmgclken_set(unsigned en)
-{
- unsigned tmp;
- if(en){
- //set ps_clk_switch=1
- tmp = zx_read_reg(CORE_SWITCH_CONFIG_REG);
- tmp |= (0x1<<2);
- zx_write_reg(CORE_SWITCH_CONFIG_REG, tmp);
- } else{
- //set ps_clk_switch=0
- tmp = zx_read_reg(CORE_SWITCH_CONFIG_REG);
- tmp &= ~(0x1<<2);
- zx_write_reg(CORE_SWITCH_CONFIG_REG, tmp);
- }
-}
-
-
-/**
- * config pcu before poweroff
- *
- */
-void pm_set_pcu_poweroff(u32 sleep_time)
-{
- zx_set_reg(ARM_AP_CONFIG_REG, PCU_POWEROFF_MODE);
- zx_write_reg(ARM_AP_SLEEP_TIME_REG, sleep_time);
-}
-EXPORT_SYMBOL(pm_set_pcu_poweroff);
-
-
-/**
- * config pcu before sleep
- *
- */
-void pm_set_pcu_sleep(u32 sleep_time)
-{
- zx_set_reg(ARM_AP_CONFIG_REG, PCU_SLEEP_MODE);
- zx_write_reg(ARM_AP_SLEEP_TIME_REG, sleep_time);
-}
-
-/**
- * get wakeup setting.
- *
- */
-unsigned int pcu_get_wakeup_setting(void)
-{
- return zx_read_reg(AP_INT_WAKE_DIS_REG);
-}
-/**
- * set wakeup enable by gic.
- *
- *
- */
-unsigned int gic_wake_enable[3]=
-{
- (1<<ICP_PS2AP_INT) |(1<<ICP_M02AP_INT) | (1<<AP_TIMER1_INT) ,
- 0,
- 0
-};
-
-void pm_get_wake_cause(void)
-{
- unsigned int int_status[2];
- int i = 0;
- int index_found = 0xff;
- unsigned int pcu_wake_setting[2];
-
- /* when wake up, the level is high&the value is 0*/
- int_status[0] = zx_read_reg(PCU_INT_READOUT_REG1);
- int_status[1] = zx_read_reg(PCU_INT_READOUT_REG2);
-
- pcu_wake_setting[0] = zx_read_reg(AP_INT_WAKE_DIS_REG);
- pcu_wake_setting[1] = zx_read_reg(M0_INT_WAKE_DIS_REG);
-
- for(i=0; i<ARRAY_SIZE(zx297520v3_pcu_int_info); i++)
- {
- if (zx297520v3_pcu_int_info[i].wake_index == 0xff)
- continue;
-
- if(pcu_wake_setting[0]&BIT(zx297520v3_pcu_int_info[i].wake_index))
- continue;
-
- if(int_status[zx297520v3_pcu_int_info[i].status_index/32]&(1<<(zx297520v3_pcu_int_info[i].status_index%32)))
- continue;
-
- index_found = i;
- break;
- }
-
- if(index_found != 0xff)
- {
- pm_ram_log(" wake: %d [%s]\n", zx297520v3_pcu_int_info[index_found].gic_index, zx297520v3_pcu_int_info[index_found].int_name);
- pm_ram_log(" pcu int status:%x %x\n",int_status[0], int_status[1]);
- }
- else
- {
- pm_ram_log(" wake abnormal\n");
- pm_ram_log(" pcu int status:%x %x\n",int_status[0], int_status[1]);
- }
-}
-
-
-static struct wakeup_source *zx_main_ws;
-static int zx_pcu_pm_callback(struct notifier_block *nb,
- unsigned long action, void *ptr)
-{
- switch (action) {
-
- case PM_POST_SUSPEND:
- __pm_wakeup_event(zx_main_ws, 1000);
- break;
-
- default:
- return NOTIFY_DONE;
- }
-
- return NOTIFY_OK;
-}
-
-static int pcu_pm_suspend(void)
-{
- int ret = 0;
-
- return ret;
-}
-
-static void pcu_pm_resume(void)
-{
-// pcu_get_wake_cause();
-}
-
-static struct syscore_ops pcu_pm_syscore_ops = {
- .suspend = pcu_pm_suspend,
- .resume = pcu_pm_resume,
-};
-
-static int pcu_pm_init(void)
-{
- zx_main_ws = wakeup_source_register(NULL, "zx_main");
- if (!zx_main_ws)
- return -ENOMEM;
-
- pm_notifier(zx_pcu_pm_callback, 0);
-
- register_syscore_ops(&pcu_pm_syscore_ops);
- return 0;
-}
-core_initcall(pcu_pm_init);
-#endif
-
-/* --------------------------------------------------------------------
- * extint_8in1
- * -------------------------------------------------------------------- */
-
-struct ext8in1_info {
- struct irq_domain *domain;
- struct regmap *regmap;
- int parent_irq;
-
-};
-
-struct ext8in1_info ext8in1_dev = {0};
-
-/*
- * return external interrupt number from ex8-ex15,
- * return value is 0-7
- */
-static unsigned int pcu_get_8in1_int_source(void)
-{
- unsigned int vector_8in1 = 0;
-
- vector_8in1 = zx_read_reg(pcu_dev.top_reg_base+0x12C);
-
- return (vector_8in1&0x7);
-}
-
-
-/*external int 8-15 need extra clear*/
-static void pcu_int_clear_8in1(unsigned int pcu_index)
-{
- unsigned int vector=0;
-
- if ( (pcu_index >= PCU_EX8_INT)&&(pcu_index <= PCU_EX15_INT) )
- {
- /*
- *in 7510 platform, 8in1 interrupt would be used by different cores.
- *when any core installs a new 8in1 interrupt, another core may be
- * responding another 8in1 interrupt, so 8in1 interrupt shouldn't be
- *cleared. in this case, nothing to be done. but a new problem comes,
- * the core install new 8in1 interrupt will receive a fake interrupt.
- */
- vector = pcu_get_8in1_int_source();
- if (pcu_index != (vector + PCU_EX8_INT) )
- return;
-
- PCU_LOCK
- zx_write_reg(pcu_dev.top_reg_base+0x128, 0x1);
- PCU_UNLOCK
- }
-}
-
-static void ext8in1_irq_lock(struct irq_data *data){}
-static void ext8in1_irq_sync_unlock(struct irq_data *data){}
-static void ext8in1_irq_mask(struct irq_data *data){}
-static void ext8in1_irq_unmask(struct irq_data *data){}
-static void ext8in1_irq_eoi(struct irq_data *data)
-{
- pcu_int_clear_8in1(data->hwirq + PCU_EX8_INT);
-}
-
-static struct irq_chip ext8in1_irq_chip =
-{
- .name = "ext8in1",
- .irq_mask = ext8in1_irq_mask,
- .irq_unmask = ext8in1_irq_unmask,
- .irq_bus_lock = ext8in1_irq_lock,
- .irq_bus_sync_unlock = ext8in1_irq_sync_unlock,
- .irq_eoi = ext8in1_irq_eoi,
-};
-
-static void ext8in1_handle_irq(struct irq_desc *desc)
-{
- struct ext8in1_info *data = irq_desc_get_handler_data(desc);
- struct irq_chip *chip = irq_desc_get_chip(desc);
- int virq;
- int hwirq;
-
- chained_irq_enter(chip, desc);
-
- hwirq = pcu_get_8in1_int_source();
-
- virq = irq_find_mapping(data->domain, hwirq);
- if (virq > 0)
- generic_handle_irq(virq);
-
- chained_irq_exit(chip, desc);
-}
-
-static int zx_ext8in1_probe(struct platform_device *pdev)
-{
- struct device_node *np = pdev->dev.of_node;
- struct device_node *parent_np;
- struct regmap *regmap;
- struct ext8in1_info *data = &ext8in1_dev;
- int i;
-
- parent_np = of_parse_phandle(pdev->dev.of_node, "parent-syscon", 0);
- if (!parent_np) {
- dev_err(&pdev->dev, "Can't get parent-syscon\n");
- return -EINVAL;
- }
-
- regmap = syscon_node_to_regmap(parent_np);
- if (IS_ERR(regmap)) {
- of_node_put(parent_np);
- return PTR_ERR(regmap);
- }
- data->regmap = regmap;
-
- data->parent_irq = platform_get_irq(pdev, 0);
- if (data->parent_irq <= 0)
- return -EPROBE_DEFER;
-
- data->domain = irq_domain_add_linear(np, 8, &irq_domain_simple_ops, NULL);
- if (!data->domain)
- return -ENODEV;
-
- for (i = EX8_INT; i <= EX15_INT; i++) {
- int virq = irq_create_mapping(data->domain, i);
-
- irq_set_chip_and_handler(virq, &ext8in1_irq_chip,
- handle_simple_irq);
- irq_set_chip_data(virq, data);
- }
-
- irq_set_chained_handler_and_data(data->parent_irq,
- ext8in1_handle_irq, data);
-
- pr_info("zx_ext8in1 init OK. \n");
-
- return 0;
-}
-
-static const struct of_device_id zx_ext8in1_match[] = {
- { .compatible = "zte,zx297520v3-ext8in1" },
- { }
-};
-
-static struct platform_driver zx_ext8in1_driver = {
- .probe = zx_ext8in1_probe,
- .driver = {
- .name = "zx_ext8in1_drv",
- .of_match_table = zx_ext8in1_match,
- },
-};
-
-static int __init zx_ext8in1_driver_init(void)
-{
- return platform_driver_register(&zx_ext8in1_driver);
-}
-core_initcall(zx_ext8in1_driver_init);
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-zx297520v3.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-zx297520v3.h
deleted file mode 100644
index 89f1aae..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/pcu/pcu-zx297520v3.h
+++ /dev/null
@@ -1,73 +0,0 @@
-
-#ifndef _PCU_ZX297520V3_H
-#define _PCU_ZX297520V3_H
-
-#ifdef _PCU_ZX297520V3_H
-/* ap related registers */
-#define AP_INT_WAKE_DIS1_REG (0x34)
-#define INT_TYPE1_REG (0x3C) /* 1-level 0-pulse */
-#define INT_POL1_REG (0x4C) /* 1-HL or Pos 0-LL or Neg */
-#define INT_CLEAR1_REG (0x5C) /* write 1 */
-
-#define INT_READOUT1_REG (0x7AC)
-//#define INT_READOUT2_REG (0x19C)
-
-#define AP_INT_WAKE_CNT (32)
-#define PCU_UNKNOWN_INT 0xff,
-
-
-/* reg1 */
-#define PCU_INT_REG1_OFF (0)
-#define PCU_GMAC_INT (PCU_INT_REG1_OFF + 0)
-#define PCU_UART0_RXD_INT (PCU_INT_REG1_OFF + 1)
-#define PCU_ICP_PHY2AP_INT (PCU_INT_REG1_OFF + 2)
-#define PCU_SD0_DATA1_INT (PCU_INT_REG1_OFF + 3)
-#define PCU_USB_POWERDWN_UP_INT (PCU_INT_REG1_OFF + 7)
-#define PCU_USB_POWERDWN_DOWN_INT (PCU_INT_REG1_OFF + 8)
-#define PCU_HSIC_POWERDWN_UP_INT (PCU_INT_REG1_OFF + 9)
-#define PCU_HSIC_POWERDWN_DOWN_INT (PCU_INT_REG1_OFF + 10)
-#define PCU_RTC_ALARM_INT (PCU_INT_REG1_OFF + 13)
-#define PCU_RTC_TIMER_INT (PCU_INT_REG1_OFF + 14)
-#define PCU_KEYPAD_INT (PCU_INT_REG1_OFF + 15)
-#define PCU_SD1_DATA1_INT (PCU_INT_REG1_OFF + 16)
-#define PCU_GMACPHY_WAKE_INT (PCU_INT_REG1_OFF + 17)
-#define PCU_SPCU_PW_INT (PCU_INT_REG1_OFF + 18)
-#define PCU_ICP_PS2AP_INT (PCU_INT_REG1_OFF + 20)
-#define PCU_ICP_M02AP_INT (PCU_INT_REG1_OFF + 21)
-#define PCU_AP_TIMER1_INT (PCU_INT_REG1_OFF + 22)
-#define PCU_AP_TIMER2_INT (PCU_INT_REG1_OFF + 23)
-#define PCU_FRM_ARM_32K_INT (PCU_INT_REG1_OFF + 31)
-
-
-
-/* reg2 */
-#define PCU_INT_REG2_OFF (32)
-#define PCU_GMACPHY_INT (PCU_INT_REG2_OFF + 0)
-
-
-
-/* reg3 */
-#define PCU_INT_REG3_OFF (64)
-#define PCU_EX0_INT (PCU_INT_REG3_OFF + 0)
-#define PCU_EX1_INT (PCU_INT_REG3_OFF + 1)
-#define PCU_EX2_INT (PCU_INT_REG3_OFF + 2)
-#define PCU_EX3_INT (PCU_INT_REG3_OFF + 3)
-#define PCU_EX4_INT (PCU_INT_REG3_OFF + 4)
-#define PCU_EX5_INT (PCU_INT_REG3_OFF + 5)
-#define PCU_EX6_INT (PCU_INT_REG3_OFF + 6)
-#define PCU_EX7_INT (PCU_INT_REG3_OFF + 7)
-#define PCU_EX8_INT (PCU_INT_REG3_OFF + 8)
-#define PCU_EX9_INT (PCU_INT_REG3_OFF + 9)
-#define PCU_EX10_INT (PCU_INT_REG3_OFF + 10)
-#define PCU_EX11_INT (PCU_INT_REG3_OFF + 11)
-#define PCU_EX12_INT (PCU_INT_REG3_OFF + 12)
-#define PCU_EX13_INT (PCU_INT_REG3_OFF + 13)
-#define PCU_EX14_INT (PCU_INT_REG3_OFF + 14)
-#define PCU_EX15_INT (PCU_INT_REG3_OFF + 15)
-
-
-
-#endif
-
-
-#endif /* _PCU_ZX297520V3_H */
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/plat/Kconfig b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/plat/Kconfig
deleted file mode 100644
index c6480f3..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/plat/Kconfig
+++ /dev/null
@@ -1,106 +0,0 @@
-#
-#
-#
-menuconfig ARCH_ZX297520V3
- bool "ZTE-TSP ZX297520V3"
- depends on ARCH_MULTI_V7
- select SOC_ZTE
- select ARM_AMBA
- select HAVE_ARM_ARCH_TIMER
- select RESET_CONTROLLER
- select RESET_SIMPLE
- select RESET_ZX29
- select MFD_SYSCON
- select PINCTRL_ZX297520V3
- select GPIO_ZX29
- select GPIOLIB_IRQCHIP
- select ZTE_PCU
- select DMADEVICES
- select ZTE_DMA
- select ZTE_RPMSG
- select ZX29_ICP
- select DECOMPRESS_RELADDR_BOOT
- help
- ZTE-TSP ZX297520V3 based systems
-
-config DTB_ADDR
- hex "DTB Physical address of main memory" if MMU
- default 0x22100000 if ARCH_ZX297520V3
-
-if ARCH_ZX297520V3
-
-comment "ZX297520V3 Board Type"
-
-config ARCH_ZX297520V3_EVB
- bool "ZTE-TSP ZX297520V3_EVB board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 EVB board.
-
-config ARCH_ZX297520V3_MDL
- bool "ZTE-TSP ZX297520V3 MDL board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 MDL board.
-
-config ARCH_ZX297520V3_MIFI
- bool "ZTE-TSP ZX297520V3 MIFI board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 MIFI board.
-
-config ARCH_ZX297520V3_UFI
- bool "ZTE-TSP ZX297520V3 UFI board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 UFI board.
-
-config ARCH_ZX297520V3_PHONE
- bool "ZTE-TSP ZX297520V3 PHONE board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 PHONE board.
-
-config ARCH_ZX297520V3_FWP
- bool "ZTE-TSP ZX297520V3 FWP board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 FWP board.
-
-config ARCH_ZX297520V3_WATCH
- bool "ZTE-TSP ZX297520V3 WATCH board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 WATCH board.
-
-config ARCH_ZX297520V3_CPE
- bool "ZTE-TSP ZX297520V3 CPE board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 CPE board.
-
-config ARCH_ZX297520V3_CPE_SWITCH
- bool "ZTE-TSP ZX297520V3 CPE SWITCH board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 CPE SWITCH board.
-config ARCH_ZX297520V3_POC
- bool "ZTE-TSP ZX297520V3 POC board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 POC board.
-
-config ARCH_ZX297520V3_FPGA
- bool "ZTE-TSP ZX297520V3 FPGA board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 FPGA board.
-
-config ARCH_ZX297520V3_CAP
- bool "ZTE-TSP ZX297520V3 CAP board"
- help
- Select this if you are using ZTE-TSP ZX297520V3 CAP board.
-
-config MIN_VERSION
- bool "min version used for 16M nor-flash"
- help
- Select this if you are using 16M nor-flash board.
-
-config MIN_8M_VERSION
- bool "min version used for 8M nor-flash"
- help
- Select this if you are using 8M nor-flash board.
-endif
-
-config DECOMPRESS_RELADDR_BOOT
- bool "get reladdr from boot when decompressed"
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/plat/Makefile b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/plat/Makefile
deleted file mode 100644
index 2b8dded..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/plat/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the soc plat drivers
-#
-
-obj-$(CONFIG_ARCH_ZX279132S) += plat-zx279132s.o
-obj-$(CONFIG_ARCH_ZX298501) += plat-zx298501.o
-obj-$(CONFIG_ARCH_ZX297520V3) += plat-zx297520v3.o
-#
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/plat/plat-zx297520v3.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/plat/plat-zx297520v3.c
deleted file mode 100644
index c6f9f47..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/plat/plat-zx297520v3.c
+++ /dev/null
@@ -1,1111 +0,0 @@
-/*
- * drivers/soc/zte/plat/plat-zx298501.c
- *
- * Copyright (C) 2021 ZTE-TSP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/syscore_ops.h>
-#include <linux/gpio.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/io.h>
-#include <linux/of_gpio.h>
-#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_runtime.h>
-#include <linux/delay.h>
-#include <linux/reset.h>
-#include <linux/io.h>
-#include <linux/amba/serial.h>
-#include <linux/serial_reg.h>
-#include <linux/of_device.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/sched/clock.h>
-#include <linux/suspend.h>
-#include <linux/mfd/syscon.h>
-#include <linux/regmap.h>
-#include <linux/reboot.h>
-#include <linux/soc/zte/common.h>
-#include <linux/soc/zte/pcu.h>
-#include <linux/soc/zte/spinlock.h>
-#include <dt-bindings/soc/zx297520v3-irq.h>
-
-/*
- * we use sysfs to test&debug some system funcs
- *
- */
-struct kobject *zx_root_kobj;
-struct kobject *zx_test_kobj;
-
-extern int __init zx_clk_test_init(void);
-extern int __init zx_dma_test_init(void);
-extern int __init zx_icp_test_init(void);
-extern int __init zx_timer_test_init(void);
-
-#define CONFIG_USE_DEBUG_LED 1
-#define ZX_RESET_TEST 1
-#define ZX_CLK_TEST 1
-#define ZX_PINCTRL_TEST 1
-#define ZX_GPIO_TEST 1
-#define ZX_EINT_TEST 1
-#define ZX_PM_TEST 1
-#if ZX_PM_TEST
-#define PM_RUNTIME_AUTO_TEST 1
-#endif
-#define ZX_SPINLOCK_TEST 0
-
-
-/*
- *
- * some test need device probe
- */
-struct zx_drv_test
-{
- struct device *dev;
-#if ZX_RESET_TEST
- struct reset_control *rst;
-#endif
-
-#if ZX_PINCTRL_TEST
- struct pinctrl *pctrl;
- struct pinctrl_state *state0;
- struct pinctrl_state *state1;
- struct pinctrl_state *state2;
-#endif
-
-#if ZX_GPIO_TEST
- int gpio;
- struct gpio_desc *gd;
-
-#endif
-
-#if ZX_EINT_TEST
- int eint_irq;
-#endif
-
-#if ZX_CLK_TEST
- struct clk *clk;
-#endif
-};
-
-struct zx_drv_test drv_test = {0};
-
-#if 0//ZX_RESET_TEST
-static void drv_reset_test(struct reset_control *rstc)
-{
- reset_control_assert(rstc);
- udelay(10);
- reset_control_deassert(rstc);
-}
-#endif
-
-#if ZX_EINT_TEST
-static irqreturn_t test_eint_isr(int irq, void *p)
-{
- static int eint_cnt = 0;
-
- pr_info("eint get = %d\n", ++eint_cnt);
-
- return IRQ_HANDLED;
-}
-#endif
-
-#if ZX_GPIO_TEST
-static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
-{
- static int irq_cnt = 0;
-
- irq_cnt ++;
- pr_info("gpio irq_cnt = %d\n", irq_cnt);
-
- return IRQ_HANDLED;
-}
-#endif
-
-/*
- * test led helper interface
- *
- */
-#if CONFIG_USE_DEBUG_LED
-static void test_led_init(void)
-{
- int ret;
-
- if (!drv_test.dev)
- return;
-
- ret = gpio_request(drv_test.gpio, "led_test");
- if (ret)
- {
- pr_info("led_test gpio request error.\n");
- return ;
- }
-
- gpio_direction_output(drv_test.gpio, 0);
-}
-static void test_led_on(void)
-{
- if (!drv_test.dev)
- return;
-
- gpio_direction_output(drv_test.gpio, 1);
-}
-static void test_led_off(void)
-{
- if (!drv_test.dev)
- return;
-
- gpio_direction_output(drv_test.gpio, 0);
-}
-#else
-static void test_led_init(void){}
-static void test_led_on(void){}
-static void test_led_off(void){}
-#endif
-
-#if ZX_PM_TEST
-
-static int zx_drv_test_pm_resume(struct device *dev)
-{
- pm_stay_awake(dev);
-
- pr_info("zx_drv_test_pm_resume\n");
- return 0;
-}
-
-static int zx_drv_test_pm_suspend(struct device *dev)
-{
- pr_info("zx_drv_test_pm_suspend\n");
- return 0;
-}
-
-static int zx_drv_test_pm_runtime_resume(struct device *dev)
-{
- /* enable clk and restore regs */
- pr_info("zx_drv_test_pm_runtime_resume\n");
- return 0;
-}
-
-static int zx_drv_test_pm_runtime_suspend(struct device *dev)
-{
- /* backup regs and disable clk */
- pr_info("zx_drv_test_pm_runtime_suspend\n");
- return 0;
-}
-
-static int zx_drv_test_pm_runtime_idle(struct device *dev)
-{
- pr_info("zx_drv_test_pm_runtime_idle\n");
- return 0;
-}
-
-static const struct dev_pm_ops zx_drv_test_pm = {
- .resume = zx_drv_test_pm_resume,
- .suspend = zx_drv_test_pm_suspend,
- .runtime_resume = zx_drv_test_pm_runtime_resume,
- .runtime_suspend = zx_drv_test_pm_runtime_suspend,
- .runtime_idle = zx_drv_test_pm_runtime_idle
-};
-#endif
-
-
-static int zx_drv_test_probe(struct platform_device *pdev)
-{
- int gpio;
- int irq;
- enum of_gpio_flags flags;
- int ret;
-
- drv_test.dev = &pdev->dev;
-
- /* reset */
-#if ZX_RESET_TEST
- drv_test.rst = devm_reset_control_get(&pdev->dev, "test_rst");
-#endif
-
- /* clk */
-#if ZX_CLK_TEST
- drv_test.clk = devm_clk_get(&pdev->dev, "test");
- if (IS_ERR(drv_test.clk)) {
- ret = PTR_ERR(drv_test.clk);
- dev_err(&pdev->dev, "failed to get test_clk: %d\n", ret);
- return ret;
- }
- clk_prepare_enable(drv_test.clk);
-#endif
-
- /* pinctrl */
-#if ZX_PINCTRL_TEST
-/*
- drv_test.pctrl = devm_pinctrl_get_select_default(&pdev->dev);
-*/
- drv_test.pctrl = devm_pinctrl_get(&pdev->dev);
- if (IS_ERR(drv_test.pctrl)) {
- dev_warn(&pdev->dev, "Failed to get test pins");
- drv_test.pctrl = NULL;
- goto pinctrl_init_end;
- }
- drv_test.state0 = pinctrl_lookup_state(drv_test.pctrl, "state0");
- if (IS_ERR(drv_test.state0)) {
- dev_err(&pdev->dev, "TEST: missing state0\n");
- }
- drv_test.state1 = pinctrl_lookup_state(drv_test.pctrl, "state1");
- if (IS_ERR(drv_test.state1)) {
- dev_err(&pdev->dev, "TEST: missing state1\n");
- }
- drv_test.state2 = pinctrl_lookup_state(drv_test.pctrl, "ext_int5");
- if (IS_ERR(drv_test.state2)) {
- dev_err(&pdev->dev, "TEST: missing state2\n");
- }
- if ( pinctrl_select_state(drv_test.pctrl, drv_test.state0) < 0) {
- dev_err(&pdev->dev, "setting state0 failed\n");
- }
-
- /* eint5 */
- if ( pinctrl_select_state(drv_test.pctrl, drv_test.state2) < 0) {
- dev_err(&pdev->dev, "setting eint5 failed\n");
- }
-
-pinctrl_init_end:
-#endif
-
-
-#if ZX_PM_TEST
- /* just show how a device use wake source */
- device_init_wakeup(&pdev->dev, true);
- pm_stay_awake(&pdev->dev);
-#endif
-
- /* eint5 irq */
-#if ZX_EINT_TEST
- drv_test.eint_irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
- ret = request_irq(drv_test.eint_irq,
- test_eint_isr,
- 0,
- "test_eint",
- &drv_test);
- if(ret<0)
- BUG();
- enable_irq_wake(drv_test.eint_irq);
-#endif
-
-#if ZX_GPIO_TEST
- drv_test.gd = gpiod_get_index(drv_test.dev, "testtt", 0, GPIOD_OUT_HIGH);
-
- /* gpio test */
- gpio = of_get_gpio_flags(pdev->dev.of_node, 0, &flags);
- if (!gpio_is_valid(gpio)) {
- pr_info("test gpio no found\n");
- goto gpio_init_end;
- }
- /* pr_info("test gpio :%d flag=0x%x\n", gpio, flags); */
-
- drv_test.gpio = gpio;
- test_led_init();
-
- irq = gpio_to_irq(gpio);
- if (irq > 0) {
- if (0 != request_irq(irq, gpio_irq_handler, IRQF_TRIGGER_RISING, "gpio_irq_test", NULL)) {
- pr_info("request gpio irq failed\n");
- goto gpio_init_end;
- }
- }
-
-gpio_init_end:
-#endif
-
-#if ZX_PM_TEST
-#if PM_RUNTIME_AUTO_TEST
- pm_runtime_set_autosuspend_delay(&pdev->dev, 3000 /*ms*/);
- pm_runtime_use_autosuspend(&pdev->dev);
- pm_runtime_enable(&pdev->dev);
- pm_runtime_get_sync(&pdev->dev);
- if (!pm_runtime_enabled(&pdev->dev)) {
- zx_drv_test_pm_runtime_resume(&pdev->dev);
- }
-
- /* put to suspend 3s later */
- pm_runtime_mark_last_busy(&pdev->dev);
- pm_runtime_put_sync_autosuspend(&pdev->dev);
-#else
- if (pdev->dev.pm_domain) {
- pm_runtime_set_active(&pdev->dev);
- pm_runtime_enable(&pdev->dev);
- }
-
- if (pm_runtime_enabled(&pdev->dev))
- pm_runtime_get_sync(&pdev->dev);
-#endif
-#endif
-
- return 0;
-}
-
-static const struct of_device_id zx297520v3_drv_test_match[] = {
- { .compatible = "zte,drv-test", },
- { }
-};
-
-static struct platform_driver zx_test_driver = {
- .probe = zx_drv_test_probe,
- .driver = {
- .name = "zx297520v3_drv_test",
-#if ZX_PM_TEST
- .pm = &zx_drv_test_pm,
-#endif
- .of_match_table = zx297520v3_drv_test_match,
- },
-};
-
-/*sys fs*/
-#define zte_attr(_name) \
-static struct kobj_attribute _name##_attr = \
-{ \
- .attr = \
- { \
- .name = __stringify(_name), \
- .mode = 0644, \
- }, \
- .show = _name##_show, \
- .store = _name##_store, \
-}
-
-/*=============================================================================
- *======== /sys/zte/test/os_timer ==============================================
- *=============================================================================
- */
-static ssize_t os_timer_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- s += sprintf(s, "%s\n", "[TEST]Test will light on/off led every 5s~");
-
- return (s - buf);
-}
-
-/*echo 1 > /sys/zte/test/os_timer*/
-static struct timer_list test_timer;
-static unsigned long test_timer_count = 0;
-static void test_timer_expired(struct timer_list *unused)
-{
- mod_timer(&test_timer, jiffies + msecs_to_jiffies(5*1000));
-
- pr_info("[TEST]Test timer arrived:%lu \n",
- ++test_timer_count);
-
-/*
- if(test_timer_count&1)
- test_led_on();
- else
- test_led_off();
-*/
-}
-
-static ssize_t os_timer_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- unsigned int temp;
-
-// if(strict_strtol(buf, 0, &temp))
- if(sscanf(buf, "%u", &temp) != 1)
- error = -EINVAL;
-
- pr_info("temp=%d", temp);
-
- if(temp == 1)
- {
- mod_timer(&test_timer, jiffies + msecs_to_jiffies(5*1000));
- }
- else
- {
- del_timer(&test_timer);
- test_timer_count = 0;
- }
-
- return error ? error : n;
-}
-
-zte_attr(os_timer);
-
-/*=============================================================================
- *======== /sys/zte/test/timer ==============================================
- *=============================================================================
- */
-/*echo 0xXXXXXXXX > /sys/zte/test/reg_read*/
-#if ZX_PM_TEST
-static ssize_t wake_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- s += sprintf(s, "%s\n", "[TEST]Read register[0xXXXXXXXX] value~");
-
- return (s - buf);
-}
-
-static ssize_t wake_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- unsigned int temp;
-
- if(sscanf(buf, "%u", &temp) != 1)
- error = -EINVAL;
-
- pr_info("temp=%d", temp);
-
- if(temp == 1)
- {
- pm_stay_awake(drv_test.dev);
- }
- else if(temp == 2)
- {
- pm_relax(drv_test.dev);
- }
-
-#if 0
- if(sscanf(buf, "%08x", &addr) != 1)
- error = -EINVAL;
-
- reg_vir_addr = ioremap(addr, 0x1000);
- pr_info("reg[%08x]=%08x\n", addr, ioread32((void __iomem *)reg_vir_addr));
-
- iounmap(reg_vir_addr);
-#endif
- return error ? error : n;
-}
-
-zte_attr(wake);
-#endif
-/*=============================================================================
- *======== /sys/zte/test/spinlock ==============================================
- *=============================================================================
- */
-/*echo 0xXXXXXXXX > /sys/zte/test/spinlock*/
-#if ZX_SPINLOCK_TEST
-void hw_spin_lock(u32 hwid);
-void hw_spin_unlock(u32 hwid);
-static ssize_t spinlock_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
-// s += sprintf(s, "%s\n", "[TEST]Read register[0xXXXXXXXX] value~");
-
- return (s - buf);
-}
-
-static ssize_t spinlock_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- u32 temp;
-
- {
-#if 0
- int irq_base ;
-
- pr_info("current irq=%d\n", irq);
- irq_base = irq_alloc_descs(-1, 0, 11, 0);
- pr_info("next irq=%d\n", irq_base);
-#endif
- struct of_phandle_args out_irq;
- int rc;
-
- rc = of_irq_parse_one(drv_test.dev->of_node, 0, &out_irq);
- pr_info("pcie irq=%d\n", rc);
-
- }
-
- sscanf(buf, "%u", &temp);
- pr_info("spinlock store:%d\n", temp);
-#if 0
- /* 1--lock 2--unlock */
- if(temp == 1)
- {
- hw_spin_lock(7);
- pr_info("spinlock lock ok!\n");
- }
- else if(temp == 2)
- {
- hw_spin_unlock(7);
- pr_info("spinlock unlock ok!\n");
- }
-#endif
- return error ? error : n;
-}
-
-zte_attr(spinlock);
-#endif
-
-/*=============================================================================
- *======== /sys/zte/test/reset ==============================================
- *=============================================================================
- */
-/* echo 1/0 > /sys/zte/test/reset */
-#if ZX_RESET_TEST
-static ssize_t reset_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- s += sprintf(s, "%s %d\n", "reset signal status:", reset_control_status(drv_test.rst));
-
- return (s - buf);
-}
-
-static ssize_t reset_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- u32 temp;
-
- sscanf(buf, "%u", &temp);
-
- /* 1--assert 0--deassert */
- if(temp == 1)
- {
- reset_control_deassert(drv_test.rst);
-
- pr_info("reset signal assert!\n");
- }
- else if(temp == 0)
- {
- reset_control_deassert(drv_test.rst);
-
- pr_info("reset signal release!\n");
- }
-
- return error ? error : n;
-}
-
-zte_attr(reset);
-#endif
-/*=============================================================================
- *======== /sys/zte/test/gpio ============================================
- *=============================================================================
- */
-/* echo 1/0 > /sys/zte/test/gpio */
-#if ZX_PINCTRL_TEST
-static ssize_t gpio_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- return (s - buf);
-}
-
-static ssize_t gpio_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- u32 temp;
-
- sscanf(buf, "%u", &temp);
-
- if (!drv_test.dev)
- return error;
-
- /* 0-out_l 1-out_h 2-in and get */
- if(temp == 0) {
- gpio_direction_output(drv_test.gpio, 0);
- pr_info("gpio out low");
- }
- else if(temp == 1) {
- gpio_direction_output(drv_test.gpio, 1);
- pr_info("gpio out high");
- }
- else if(temp == 2) {
- gpio_direction_input(drv_test.gpio);
- pr_info("gpio get value(%d) !\n",__gpio_get_value(drv_test.gpio));
- }
-
- return error ? error : n;
-}
-
-zte_attr(gpio);
-#endif
-
-/*=============================================================================
- *======== /sys/zte/test/pinctrl ============================================
- *=============================================================================
- */
-/* echo 1/0 > /sys/zte/test/pinctrl */
-#if ZX_PINCTRL_TEST
-static ssize_t pinctrl_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
- int i;
-
- for (i=0; i<16; i++)
- printk("gpio_%d mapped irq to %d \n", i, gpio_to_irq(i));
-
- return (s - buf);
-}
-
-static ssize_t pinctrl_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- u32 temp;
-
- sscanf(buf, "%u", &temp);
-
- /* temp --> pin state */
- if(temp == 1)
- {
- if ( pinctrl_select_state(drv_test.pctrl, drv_test.state1) < 0) {
- dev_err(drv_test.dev, "setting state1 failed\n");
- }
-
- pr_info("setting state1 !\n");
- }
- else if(temp == 0)
- {
- if ( pinctrl_select_state(drv_test.pctrl, drv_test.state0) < 0) {
- dev_err(drv_test.dev, "setting state0 failed\n");
- }
-
- pr_info("setting state0 !\n");
- }
- else if(temp == 2)
- {
- if ( pinctrl_select_state(drv_test.pctrl, drv_test.state2) < 0) {
- dev_err(drv_test.dev, "setting state2 failed\n");
- }
-
- pr_info("setting state2 !\n");
- }
-
- return error ? error : n;
-}
-
-zte_attr(pinctrl);
-#endif
-
-/*=============================================================================
- *======== /sys/zte/test/pd ==============================================
- *=============================================================================
- */
-/* echo 1/0 > /sys/zte/test/pd */
-#if ZX_PM_TEST
-static ssize_t pd_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- return (s - buf);
-}
-
-static ssize_t pd_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
-
-#ifdef CONFIG_PM
- u32 temp;
-
- sscanf(buf, "%u", &temp);
-
- /* 1--on 0--off */
- if(temp == 1)
- {
- pm_runtime_get_sync(drv_test.dev);
-
- pr_info("power on!\n");
- }
- else if(temp == 0)
- {
-#if PM_RUNTIME_AUTO_TEST
- pm_runtime_mark_last_busy(drv_test.dev);
- pm_runtime_put_sync_autosuspend(drv_test.dev);
-#else
- pm_runtime_put_sync(drv_test.dev);
-#endif
- pr_info("power off!\n");
- }
-#else
- error = -ENXIO;
-#endif
- return error ? error : n;
-}
-
-zte_attr(pd);
-#endif
-
-
-/*=============================================================================
- *======== /sys/zte/test/clk ==============================================
- *=============================================================================
- */
-/* echo 1/0 > /sys/zte/test/clk */
-#if ZX_CLK_TEST
-static ssize_t clk_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- s += sprintf(s, "%s %d\n", "clk enable status:", __clk_is_enabled(drv_test.clk));
- s += sprintf(s, "%s %d\n", "clk rate:", clk_get_rate(drv_test.clk));
-
- return (s - buf);
-}
-
-static ssize_t clk_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- u32 temp;
-
- sscanf(buf, "%u", &temp);
-
- /* 1--on 0--off */
- if(temp == 1) {
- clk_enable(drv_test.clk);
- }
- else if(temp == 0) {
- clk_disable(drv_test.clk);
- } else {
- clk_set_rate(drv_test.clk, temp);
- }
-
- return error ? error : n;
-}
-
-zte_attr(clk);
-#endif
-
-/*test group*/
-static struct attribute * g[] =
-{
- &os_timer_attr.attr,
-#if ZX_PM_TEST
- &wake_attr.attr,
-#endif
-#if ZX_SPINLOCK_TEST
- &spinlock_attr.attr,
-#endif
-#if ZX_RESET_TEST
- &reset_attr.attr,
-#endif
-#if ZX_GPIO_TEST
- &gpio_attr.attr,
-#endif
-#if ZX_PINCTRL_TEST
- &pinctrl_attr.attr,
-#endif
-#if ZX_PM_TEST
- &pd_attr.attr,
-#endif
-#if ZX_CLK_TEST
- &clk_attr.attr,
-#endif
- NULL,
-};
-
-static struct attribute_group zte_test_attr_group =
-{
- .attrs = g,
-};
-
-/**
- * 1¡¢create sysfs "/sys/zte/test"
- * 2¡¢call other debug modules
- */
-static int __init zx_test_init(void)
-{
- int ret;
-
- zx_test_kobj = kobject_create_and_add("test", zx_root_kobj);
- if (!zx_test_kobj)
- return -ENOMEM;
-
- ret = sysfs_create_group(zx_test_kobj, &zte_test_attr_group);
- if (ret)
- {
- pr_info("[DEBUG] sysfs_create_group ret %d\n", ret);
- return ret;
- }
-
- timer_setup(&test_timer, test_timer_expired, 0);
-
- pr_info("[DEBUG] create test sysfs interface OK.\n");
-
- return platform_driver_register(&zx_test_driver);
-}
-
-/**
- * 1¡¢create sysfs "/sys/zte"
- * 2¡¢call other debug modules
- */
-int __init zx_dma_test_init(void);
-static int __init zx_debug_init(void)
-{
- pr_info("[DEBUG] create zte sysfs interface OK.\n");
- zx_root_kobj = kobject_create_and_add("zte", NULL);
- if (!zx_root_kobj)
- return -ENOMEM;
-
-
- zx_test_init();
-
- zx_dma_test_init();
-
-/* zx_clk_test_init(); */
-
- zx_icp_test_init();
-
- zx_timer_test_init();
-
- return 0;
-}
-
-late_initcall(zx_debug_init);
-
-void __init zx29_clock_init(void);
-
-struct zx297520v3_chip_info {
- void __iomem *stdcrm_base;
- void __iomem *socsys_base;
- void __iomem *sflock_base;
- void __iomem *apcrm_base;
-};
-
-static struct zx297520v3_chip_info zx_chip_info;
-
-void __iomem *get_stdcrm_base(void)
-{
- return zx_chip_info.stdcrm_base;
-}
-
-void __iomem *get_socsys_base(void)
-{
- return zx_chip_info.socsys_base;
-}
-
-static int spinlock_init(void)
-{
- struct device_node *np;
- void __iomem *param[2];
-
- np = of_find_compatible_node(NULL, NULL, "zte,zx297520v3-standby");
- if (!np)
- {
- BUG();
- return -ENODEV;
- }
-
- zx_chip_info.stdcrm_base = of_iomap(np, 0);
- WARN(!zx_chip_info.stdcrm_base, "unable to map stdcrm_base registers\n");
-
-
- np = of_find_compatible_node(NULL, NULL, "zte,zx29_spinlock");
- if (!np)
- {
- BUG();
- return -ENODEV;
- }
-
- zx_chip_info.sflock_base = of_iomap(np, 0);
- WARN(!zx_chip_info.sflock_base, "unable to map sflock_base registers\n");
-
-
- param[0] = zx_chip_info.stdcrm_base;
- param[1] = zx_chip_info.sflock_base;
- zx_spinlock_init(param);
-
- return 0;
-}
-
-static void socsys_init(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "zte,zx297520v3-socsys");
- if (!np)
- {
- BUG();
- }
-
- zx_chip_info.socsys_base = of_iomap(np, 0);
- WARN(!zx_chip_info.socsys_base, "unable to map socsys_base registers\n");
-}
-
-/*---------------------------------------------------------*/
-#define AP_INT_MODE_BASE (zx_chip_info.apcrm_base + 0x70)
-#define AP_PPI_MODE_REG (zx_chip_info.apcrm_base + 0xA0)
-
-#define INT_HIGHLEVEL (0x0) /* 00: high level */
-#define INT_LOWLEVEL (0x1) /* 01: low level */
-#define INT_POSEDGE (0x2) /* 10: raise edge */
-#define INT_NEGEDGE (0x3) /* 11: fall edge */
-
-static int zx29_int_set_type(unsigned int hwirq, unsigned int type)
-{
- unsigned int data_tmp=0;
- unsigned int srctype=0;
- unsigned int reg_index=0,pos_index=0;
-
- switch (type) {
- case IRQ_TYPE_LEVEL_HIGH:
- srctype = INT_HIGHLEVEL;
- break;
- case IRQ_TYPE_EDGE_RISING:
- srctype = INT_POSEDGE;
- break;
- case IRQ_TYPE_LEVEL_LOW:
- srctype = INT_LOWLEVEL;
- break;
- case IRQ_TYPE_EDGE_FALLING:
- srctype = INT_NEGEDGE;
- break;
- default:
- return -EINVAL;
- }
- reg_index=(hwirq)/16;
- pos_index=((hwirq)%16)*2;
-
- data_tmp=zx_read_reg(AP_INT_MODE_BASE+reg_index*4);
- data_tmp &= ~(3<<pos_index);
- data_tmp |= srctype<<pos_index;
- zx_write_reg(AP_INT_MODE_BASE+reg_index*4, data_tmp);
-
- return 0;
-}
-
-static void int_set_type_default(unsigned int line)
-{
- unsigned int int_type=0;
-
- switch ( line )
- {
- case WDT_INT:
- case AP_TIMER0_INT:
- case GSM_RFSSCR_INT:
- case GSM_RFSSCT_INT:
- case AP_TIMER3_INT:
- case AP_TIMER4_INT:
- case SYS_COUNTER_INT:
- {
- int_type = IRQ_TYPE_EDGE_RISING;
- break;
- }
- case MCU_LCD_INT:
- {
- int_type = IRQ_TYPE_LEVEL_LOW;
- break;
- }
-
- default:
- {
- int_type = IRQ_TYPE_LEVEL_HIGH;
- break;
- }
- }
-
- zx29_int_set_type(line, int_type);
-}
-
-static void apcrm_init(void)
-{
- int i;
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "zte,zx297520v3-apcrm");
- if (!np)
- {
- BUG();
- }
-
- zx_chip_info.apcrm_base = of_iomap(np, 0);
- WARN(!zx_chip_info.apcrm_base, "unable to map apcrm_base registers\n");
-
- zx_write_reg(AP_PPI_MODE_REG, 0x55545555);
-
- for (i=0; i<IRQ_ZX297520V3_SPI_NUM; i++)
- int_set_type_default(i);
-
-}
-
-void early_drv_init(void)
-{
- spinlock_init();
-
- socsys_init();
-
- apcrm_init();
-}
-
-//early_initcall(early_drv_init);
-
-
-/*---------------------------------------------------------------*/
-static struct reset_control *reboot_rst;
-static int zx_restart(struct notifier_block *this,
- unsigned long mode, void *cmd)
-{
- if (reboot_rst) {
- reset_control_assert(reboot_rst);
- }
-
- return NOTIFY_DONE;
-}
-
-static struct notifier_block zx_restart_handler = {
- .notifier_call = zx_restart,
- .priority = 129,
-};
-
-static int zx_reboot_probe(struct platform_device *pdev)
-{
- int ret;
- struct device_node *np = pdev->dev.of_node;
-
- reboot_rst = of_reset_control_get_by_index(np, 0);
- if (!reboot_rst) {
- dev_err(&pdev->dev, "No reset handler found!");
- return -EINVAL;
- }
-
- ret = register_restart_handler(&zx_restart_handler);
- if (ret)
- pr_warn("cannot register restart handler, %d\n", ret);
-
- return 0;
-}
-
-static const struct of_device_id zx_reboot_match[] = {
- { .compatible = "zte,reboot", },
- { }
-};
-
-static struct platform_driver zx_reboot_driver = {
- .probe = zx_reboot_probe,
- .driver = {
- .name = "zx_reboot",
- .of_match_table = zx_reboot_match,
- },
-};
-builtin_platform_driver(zx_reboot_driver)
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/Kconfig b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/Kconfig
deleted file mode 100644
index 053873b..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# ZTE SoC power drivers
-#
-config ZX_RAM_CONSOLE
- bool "Write log to ram when suspend"
- depends on SUSPEND
- default y
- help
- Write log to ram when system in suspend or sleep state that
- uart may not print log normally!
-
-config ZX_PM_DEBUG
- bool "PM debug"
- depends on SUSPEND
- default y
- help
- Debug interface for power management!
-
-config ZX_PM_DEBUG_TIME
- bool "debug sleep time"
- depends on SUSPEND
- default n
- help
- Use to debug sleep time!
-
-config AXI_FREQ
- bool "change axi clock"
- depends on CPU_FREQ
- default y
- help
- Use to change axi clock!
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/Makefile b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/Makefile
deleted file mode 100644
index de2f17a..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/Makefile
+++ /dev/null
@@ -1,23 +0,0 @@
-# When adding new entries keep the list in alphabetical order
-
-ifeq ($(CONFIG_PM),y)
-obj-y += zx-pm.o zx-pm-suspend.o zx-sleep.o zx-pm-context.o \
- zx-cpu-sleep.o zx-pm-helpers.o zx-pm-custom.o
-obj-$(CONFIG_ARCH_ZX297520V3) += zx-pm-a53.o
-obj-$(CONFIG_ARCH_ZX297520V3) += zx-pm-v8.o
-obj-y += zx29-pm.o
-
-else
-obj-y += zx-pm-null.o
-endif
-
-ifeq ($(CONFIG_CPU_IDLE),y)
-obj-y += zx29-cpuidle.o
-obj-y += zx-cpuidle.o
-endif
-
-ifeq ($(CONFIG_CPU_FREQ),y)
-obj-y += zx29-cpufreq.o
-#obj-y += zx-cpufreq.o
-endif
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpu-sleep.S b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpu-sleep.S
deleted file mode 100644
index ee52f37..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpu-sleep.S
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * ZTE CPU low power powerdown and powerup code.
- *
- * Copyright (C) 2013 ZTE, Inc.
- * Written by ZXP
- *
- */
-#include <linux/linkage.h>
-#include <linux/threads.h>
-#include <asm/asm-offsets.h>
-#include <asm/assembler.h>
-#include <asm/glue-cache.h>
-#include <asm/glue-proc.h>
-
-#include <asm/memory.h>
-
-.arm
-/* =======================================================================
- * The wakeup code will jump to this code in ddr-mem.
- * This code will build C environment for resume code.
- *
- * =======================================================================*/
-ENTRY(cpu_reset_handler)
- blx reset_init
- blx invalidate_icache_v7 /* Clear I cache */
-
- blx enable_icache_v7
- blx invalidate_dcache_v7_all /* Clear all data cache levels visible to CPU */
-
- blx cpu_resume
-ENDPROC(cpu_reset_handler)
-
-
-/* =======================================================================
- * Because IRAM may power down, M0 will copy this code to IRAM(address 0)
- * after CPU_AP is waked up.
- *
- * So this code will run in IRAM.
- * =======================================================================*/
-ENTRY(cpu_wake_up)
- nop /* add 16 nops */
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- mov r2, #0x3e8 /*ldr r2, =1000 cpu_reset_handler */
-
-
- ldr r5, [r2]
- bx r5 /* call cpu_reset_handler */
-ENDPROC(cpu_wake_up)
-
-/* =======================================================================
- * When ddr dfs, A9 must run in iram and waiting till this process finished.
- *
- * r0 -- address for dfs finish flag
- * =======================================================================*/
-#define DDR_DFS_FINISH 0x2
-
-ENTRY(waiting_ddr_dfs)
-waiting_ddr_dfs:
- stmfd sp!, {r2, lr}
-
-acquire_again:
- ldr r2, [r0]
- cmp r2, #DDR_DFS_FINISH
- bne acquire_again
-
- ldmfd sp!, {r2, pc}
-ENDPROC(waiting_ddr_dfs)
-
-/* =======================================================================
- *
- * disable ddr port3.
- * addr assigned 0x200
- * =======================================================================*/
-ENTRY(do_sleep_cpu)
-
- isb
- dsb
- wfi
-
- bx lr
-ENDPROC(do_sleep_cpu)
-
-ENTRY(zx_jump_addr)
- //mov pc, r0
- B do_sleep_cpu
-ENDPROC(zx_jump_addr)
-
-wake_up_buf: .space 1024
-
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpufreq.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpufreq.h
deleted file mode 100644
index 7e4068b..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpufreq.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * arch/arm/mach-zx297510/zx-cpufreq.h
- *
- * Copyright (c) 2013, ZTE Corporation.
- * write by zxp
- *
- */
-
-#ifndef __MACH_ZX_CPU_FREQ_H
-#define __MACH_ZX_CPU_FREQ_H
-#ifdef CONFIG_ARCH_ZX297520V2
-#else
-#define SET_AXI_BY_HW
-//#define CONFIG_DDR_FREQ
-//#define SET_DDR_BY_HW
-#endif
-enum cpufreq_level_index {
- L0, L1, L2, L3, L4,
- L5, L6, L7, L8, L9,
- L10, L11, L12, L13, L14,
- L15, L16, L17, L18, L19,
- L20,
-};
-
-struct zx_dvfs_info {
- unsigned int freq_cur_idx;
- unsigned int pll_safe_idx;
- unsigned int max_support_idx;
- unsigned int min_support_idx;
- struct clk *cpu_clk;
- unsigned int *volt_table;
- struct cpufreq_frequency_table *freq_table;
- int (*set_freq)(unsigned int, unsigned int);
-};
-
-#ifdef CONFIG_AXI_FREQ
-#ifdef CONFIG_ARCH_ZX297520V2
-typedef enum
-{
- AXI_FREQ_26M = 0,
- AXI_FREQ_39M = 1,
- AXI_FREQ_52M = 2,
- AXI_FREQ_78M = 3,
- AXI_FREQ_104M = 4,
- AXI_FREQ_122_88M = 5,
- AXI_FREQ_156M = 6,
- AXI_FREQ_NULL,
- MAX_AXI_FREQ
-}zx29_axi_freq;
-
-#else
-typedef enum
-{
- AXI_FREQ_26M = 0,
- AXI_FREQ_156M = 1,
- AXI_FREQ_124_8M = 2,
- AXI_FREQ_104M = 3,
- AXI_FREQ_78M = 4,
- AXI_FREQ_52M = 5,
- AXI_FREQ_39M = 6,
- AXI_FREQ_NULL,
- MAX_AXI_FREQ
-}zx29_axi_freq;
-#endif
-typedef enum
-{
- VOL_VO_800 = 0,
- VOL_VO_825 = 1,
- VOL_VO_850 = 2,
- VOL_VO_875 = 3,
- VOL_VO_900 = 4,
- MAX_VOL
-}zx29_vol;
-
-#endif
-
-#ifdef CONFIG_DDR_FREQ
-#ifdef CONFIG_ARCH_ZX297520V2
-typedef enum
-{
- DDR_FREQ_156M = 0,
- DDR_FREQ_312M = 1,
- MAX_DDR_FREQ
-}zx29_ddr_freq;
-
-#else
-typedef enum
-{
- DDR_FREQ_312M = 0,
- DDR_FREQ_400M = 1,
- DDR_FREQ_208M = 2,
- DDR_FREQ_156M = 3,
- MAX_DDR_FREQ
-}zx29_ddr_freq;
-#endif
-#endif
-
-typedef int (*zx29xx_cpufreq_init_cb)(struct zx_dvfs_info *info);
-extern zx29xx_cpufreq_init_cb zx29xx_cpufreq_init;
-
-extern unsigned int zx_getspeed(unsigned int cpu);
-extern int zx_update_cpu_speed(unsigned long rate);
-extern int zx_cpu_set_speed_cap(unsigned int *speed_cap);
-extern unsigned int zx_count_slow_cpus(unsigned long speed_limit);
-extern unsigned int zx_get_slowest_cpu_n(void);
-extern unsigned long zx_cpu_lowest_speed(void);
-extern unsigned long zx_cpu_highest_speed(void);
-
-#ifdef CONFIG_ZX_PM_DEBUG
-extern void cpufreq_test(unsigned int old_index, unsigned int new_index);
-#endif
-
-#ifdef CONFIG_AXI_FREQ
-extern int request_axi_freq(zx29_axi_freq axi_freq);
-#endif
-
-#endif /* __MACH_ZX_CPU_FREQ_H */
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpuidle.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpuidle.c
deleted file mode 100644
index 0af9f8b..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpuidle.c
+++ /dev/null
@@ -1,918 +0,0 @@
-/*
- * zx297510 CPU idle Routines
- *
- * Copyright (C) 2013 ZTE, Ltd.
- * Shine Yu <yu.xiang5@zte.com.cn>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/sched.h>
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/cpu.h>
-#include <linux/tick.h>
-#include <linux/suspend.h>
-#include <linux/interrupt.h>
-#include <linux/soc/zte/drv_idle.h>
-#include <linux/module.h>
-#include "zx-pm.h"
-
-#ifdef CONFIG_ZX_PM_DEBUG
-//struct zx_idle_stats idle_stats;
-#endif
-#if 0
-struct cpuidle_driver zx_idle_driver = {
- .name = "zx_idle",
- .owner = THIS_MODULE,
- .en_core_tk_irqen = 0, /* no use cpuidle time keeping */
-};
-#endif
-
-static unsigned int deep_idle_disabled_by_startup = 0;
-static unsigned int deep_idle_disabled_by_suspend = 0;
-static unsigned int deep_idle_disabled_by_debug = 0;
-static unsigned int print_enabled_by_debug = 0;
-DEFINE_PER_CPU(struct cpuidle_device, zx_idle_dev);
-
-static struct delayed_work pm_idle_work;
-#define PM_IDLE_DELAY msecs_to_jiffies(30000)
-
-static unsigned int sleep_mode_flag = 0;
-static unsigned int drv_cpuidle_flag = 0;
-static DEFINE_SPINLOCK(zx_idle_lock);
-
-void zx_cpuidle_set_busy(drv_idle_flag devId)
-{
- unsigned long flags;
-
- if( devId >= IDLE_FLAG_MAX)
- {
- printk("[zx_cpuidle_set_busy] devId err, devId = %d\n",devId);
- }
- else
- {
- raw_spin_lock_irqsave(&zx_idle_lock, flags);
- drv_cpuidle_flag |= (1<<devId);
- raw_spin_unlock_irqrestore(&zx_idle_lock, flags);
- }
-
-}
-EXPORT_SYMBOL(zx_cpuidle_set_busy);
-
-void zx_cpuidle_set_free(drv_idle_flag devId)
-{
- unsigned long flags;
-
- if( devId >= IDLE_FLAG_MAX)
- {
- printk("[zx_cpuidle_set_free] devId err, devId = %d\n",devId);
- }
- else
- {
- raw_spin_lock_irqsave(&zx_idle_lock, flags);
- drv_cpuidle_flag &= ~(1<<devId);
- raw_spin_unlock_irqrestore(&zx_idle_lock, flags);
- }
-}
-EXPORT_SYMBOL(zx_cpuidle_set_free);
-
-static void pm_idle_func(struct work_struct *work)
-{
- deep_idle_disabled_by_startup = 1;
-}
-
-/**
- * idle_can_enter_deep_sleep - check can enter deep sleep state?
- *
- *
- */
-static int idle_can_enter_deep_sleep(void)
-{
- /* can not enter deep sleep now */
- if (deep_idle_disabled_by_suspend)
- return false;
-
- /* This mode only can be entered when other core's are offline */
- if(deep_idle_disabled_by_debug || num_online_cpus() > 1)
- return false;
-
- /* can not enter deep sleep when kernel startup, we delay 30s now! */
- if(!deep_idle_disabled_by_startup)
- return false;
-
- if(pm_dma_used())
- return false;
-
- if(pm_get_mask_info()&PM_IDLE_WFI)
- return false;
-
- if(drv_cpuidle_flag != 0)
- return false;
-
-
- return true;
-}
-
-
-static int zx_pm_idle_prepare(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
-{
- int new_index = index;
-
- if(new_index == drv->safe_state_index)
- return new_index;
-
- if(!idle_can_enter_deep_sleep())
- {
- new_index = drv->safe_state_index;
- return new_index;
- }
-
- return new_index;
-}
-/****************************************************/
-#define MAX_TIME_PER_CYCLE div64_u64(div64_u64((u64)0x7fffffff*USEC_PER_SEC, (u64)PERSISTENT_TIMER_CLOCK_RATE),(u64)1000)
-
-#define SAVE_RESTORE_TIME (9) //ms
-#define SHUTDOWN_SLEEP_TIME (2) //ms
-#define MAX_PM_CB_CNT (20)
-
-enum {
- DEBUG_IDLE_MSG = 1U << 0,
- DEBUG_WAKE_LOCK = 1U << 1,
-};
-
-typedef int (*pm_callback_fn)(void);
-typedef struct
-{
- pm_callback_fn cb;
- unsigned int is_sucess;
-}pm_cb_t;
-
-static int idle_debug_mask = 0; //DEBUG_IDLE_MSG;
-
-/* /sys/module/zx297520_cpuidle/parameters/debug_mask */
-module_param(idle_debug_mask, int, 0644);
-
-static u32 sleep_count = 0;
-static pm_cb_t pm_enter_cb[MAX_PM_CB_CNT];
-static pm_cb_t pm_exit_cb[MAX_PM_CB_CNT];
-static unsigned int pm_cb_cnt = 0;
-
-extern void pm_idle_sram_start(void);
-extern void pm_idle_sram_end(void);
-extern void (*arm_pm_idle)(void);
-extern void idle_set_sleeptime(s64 sleep_time);
-extern void pm_debug_wakelocks(void);
-extern void zDrvInt_MaskIrq( u32 uiLine );
-extern void zDrvInt_UnmaskIrq( u32 uiLine );
-
-extern bool zPs_IsTdMasterMode(void);
-extern bool zPs_IsLteMasterMode(void);
-extern bool zPs_IsFddMasterMode(void);
-
-int zx_idle_get_debug_flag(void)
-{
- return idle_debug_mask;
-}
-
-int zx_idle_get_idle_flag(void)
-{
- return drv_cpuidle_flag;
-}
-/**
- * zx_pm_register_callback
- *
- * register callback for sleep enter and exit,
- * enter_cb: callback for sleep enter, callback for sleep exit
- *
- *
- */
-int zx_pm_register_callback(pm_callback_fn enter_cb, pm_callback_fn exit_cb)
-{
- int i = 0;
- if(pm_cb_cnt >= MAX_PM_CB_CNT)
- return -ENOMEM;
-
- if(!enter_cb)
- return -EINVAL;
-
- if(!exit_cb)
- return -EINVAL;
-
- for(i = 0; i < pm_cb_cnt; i++){
- if(pm_enter_cb[i].cb == enter_cb ||
- pm_exit_cb[i].cb == exit_cb)
- return EINVAL;
- }
- pm_enter_cb[pm_cb_cnt].cb = enter_cb;
- pm_enter_cb[pm_cb_cnt].is_sucess=0;
- pm_exit_cb[pm_cb_cnt].cb = exit_cb;
- pm_exit_cb[pm_cb_cnt].is_sucess=0;
-
- pm_cb_cnt ++;
-
- return 0;
-}
-EXPORT_SYMBOL(zx_pm_register_callback);
-
-/**
- * zx_cpu_dev_idle_enter
- *
- *
- *
- *
- *
- */
-int zx_cpu_dev_idle_enter(void)
-{
- int i;
- int ret=0;
-
- for(i=0;i<pm_cb_cnt; i++){
- pm_enter_cb[i].is_sucess = 0;
- }
-
- for(i=0;i<pm_cb_cnt; i++){
-
- if(pm_enter_cb[i].cb)
- ret = pm_enter_cb[i].cb();
-
- if(ret)
- return ret;
-
- pm_enter_cb[i].is_sucess = 1;
-
- }
-
- return ret;
-}
-
-/**
- * zx_cpu_dev_idle_exit
- *
- * only when dev is is_sucess when enter sleep,the exit callback is visited
- *
- *
- *
- */
-int zx_cpu_dev_idle_exit(void)
-{
- int i;
- int ret=0;
-
- for(i=0;i<pm_cb_cnt; i++){
- if(pm_exit_cb[i].cb && pm_enter_cb[i].is_sucess )
- ret = pm_exit_cb[i].cb();
-
- if(ret)
- return ret;
- }
-
- return ret;
-}
-/**
- * zx_debug_check
- *
- * check whether debug allowed sleep.
- *
- * when pm_get_mask_info()&PM_IDLE_WFI is 1, return "false",
- * else return "ture"
- */
-static bool zx_debug_check(void)
-{
- if(pm_get_mask_info()&PM_IDLE_WFI)
- return false;
- else
- return true;
-}
-/**
- * zx_sleep_wakelock_check
- *
- * check whether linux allowed sleep.
- *
- * when active wakelock count is 0, return "true",
- * else return "false"
- */
-static bool zx_sleep_wakelock_check(void)
-{
- unsigned int temp_count;
-
-/*
- if (idle_debug_mask & DEBUG_WAKE_LOCK)
- pm_debug_wakelocks();
-*/
- if(pm_get_wakeup_count(&temp_count, false))
- {
- if (pm_save_wakeup_count(temp_count))
- {
- return true;
- }
- else
- {
- pr_info("[SLP]: error save wakeup_count: %d ", temp_count);
- }
- }
-
- return false;
-}
-
-/**
- * zx_sleep_idle_check
- *
- * check whether linux allowed idlesleep.
- *
- * when idle flag is 0, return "true",
- * else return "false"
- */
-static bool zx_sleep_idle_check(void)
-{
- if(pm_dma_used())
- return false;
-
- if(drv_cpuidle_flag != 0)
- return false;
-
- return true;
-
-}
-
-/**
- * zx_cpu_kernel_sleep
- *
- *
- *
- */
-void zx_cpu_kernel_sleep(void)
-{
- cpu_do_idle();
-}
-
-/**
- * zx_sleep_set_timer
- *
- * input: expect_time_ms ---the expect_time can sleep, unit:ms
- *
- * return: elapsed time when enter idle
- */
-volatile u32 tick_cur_cnt =0;
-
-u64 zx_sleep_set_timer(u32 expect_time_ms)
-{
- u64 tmptime = 0;
-
- idle_set_sleeptime((s64)expect_time_ms*(s64)1000);
- pm_stop_tick();
- tick_cur_cnt=pm_read_tick();
- tmptime =div64_u64(read_persistent_us(),(u64)1000);// read_persistent_us()/1000; //ms
- return tmptime;
-}
-
-/**
- * zx_sleep_read_timer
- *
- * return: elapsed time when exit idle
- *
- *
- */
-u64 zx_sleep_read_timer(void)
-{
- u64 tmptime = 0;
- zx29_stop_wake_timer();
-
- tmptime =div64_u64(read_persistent_us(),(u64)1000);// read_persistent_us()/1000; //ms
- pm_restart_tick(tick_cur_cnt);
-
- return tmptime;
-}
-
-/**
- * zx_sleep_mask_int
- *
- * mask int needed
- *
- *
- */
-void zx_sleep_mask_int(void)
-{
- /*********************************************************/
- // zDrvInt_MaskIrq(TD_FRM_INT);
- // zDrvInt_MaskIrq(LTE_LPM5_INT);
- // zDrvInt_MaskIrq(WD_FRM_INT);
- // CPPS_FUNC(cpps_callbacks, zDrvInt_MaskIrq)(PS_TIMER0_INT);
- pm_save_gic_wake_enable();
-}
-
-/**
- * zx_sleep_unmaskInt
- *
- * unmask int needed
- *
- *
- */
-static void zx_sleep_unmaskInt(void)
-{
-
- // zDrvInt_UnmaskIrq(TD_FRM_INT);
-// zDrvInt_UnmaskIrq(LTE_LPM5_INT);
-// zDrvInt_UnmaskIrq(WD_FRM_INT);
- //CPPS_FUNC(cpps_callbacks, zDrvInt_UnmaskIrq)(PS_TIMER0_INT);
- pm_restore_gic_wake_enable();
-}
-
-
-/**
- * zx_cpu_idle
- * the deep sleep function, enter and exit WFI, dormant or shutdown sleep
- *
- *
- *
- */
-extern unsigned int zx_getspeed(unsigned int cpu);
-extern void clock_event_handler(void);
-extern void pm_uart_mod_timer(void);
-extern void pm_uart_del_timer(void);
-
-
-#define CAPCORE_SLEEP_TIME (18*60*60*1000) //ms
-
-void zx_cpu_idle(void)
-{
- u32 expect_time = 0;
- u64 elapsed_time_enter = 0;
- u64 elapsed_time_exit = 0;
- u64 idle_time = 0;
-
- #ifdef CONFIG_ZX_PM_DEBUG
- pm_write_reg(AP_IDLE_SLEEP_STATUS_FLAG,0xff01);
- #endif
-
- if(!zx_sleep_wakelock_check())
- goto IRQ_LOCK_EXIT;
-
- if(!zx_debug_check())
- goto IRQ_LOCK_EXIT;
-
- expect_time =CAPCORE_SLEEP_TIME;
-
- elapsed_time_enter=zx_sleep_set_timer(expect_time );
-
- if(expect_time <= SHUTDOWN_SLEEP_TIME)
- goto IRQ_LOCK_EXIT;
-
- sleep_count++;
-
- zx_sleep_mask_int();
-
- #ifdef CONFIG_ZX_PM_DEBUG
- pm_write_reg(AP_IDLE_SLEEP_STATUS_FLAG,0xff03);
- #endif
-
- if(expect_time >= SAVE_RESTORE_TIME)
- zx_enter_sleep(CPU_SLEEP_TYPE_LP1);
- else
- zx_enter_sleep(CPU_SLEEP_TYPE_LP3);
-
- #ifdef CONFIG_ZX_PM_DEBUG
- pm_write_reg(AP_IDLE_SLEEP_STATUS_FLAG,0xfffe);
- #endif
-
- zx_sleep_unmaskInt();
-
- elapsed_time_exit = zx_sleep_read_timer();
- if(elapsed_time_exit>=elapsed_time_enter)
- idle_time=elapsed_time_exit - elapsed_time_enter;
- else
- idle_time=(elapsed_time_exit - elapsed_time_enter)+MAX_TIME_PER_CYCLE;
-
- clock_event_handler();
-
- pm_ram_log(" @@sleep exit:sleep_count=%d,real_idle_time=%lld,jiffies:%u\n",sleep_count, idle_time, jiffies);
-
-IRQ_LOCK_EXIT:
- #ifdef CONFIG_ZX_PM_DEBUG
- pm_write_reg(AP_IDLE_SLEEP_STATUS_FLAG,0xffff);
- #endif
- zx_cpu_kernel_sleep();
-
-}
-
-/****************************************************/
-
-/**
- * zx_enter_idle
- * @dev: cpuidle device
- * @state: The target state to be programmed
- *
- * Idle function for C1 state, WFI on a single CPU.
- * Called with irqs off, returns with irqs on.
- * Returns the amount of time spent in the low power state.
- */
-int zx_enter_idle(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- ktime_t entry_time, exit_time;
- s64 idle_time;
- int new_index = index;
-
- local_irq_disable();
-
-#ifdef CONFIG_ARCH_ZX297520V2
-#else
- local_fiq_disable();
-#endif
- entry_time = ktime_get();
-
-/*=================================================================
- *=======begin enter idle sleep====================================
- *=================================================================
- */
- new_index = zx_pm_idle_prepare(dev, drv, index);
-
- index = zx_pm_idle_enter(new_index);
-
-/*=================================================================
- *=======end enter idle sleep======================================
- *=================================================================
- */
- exit_time = ktime_get();
-#ifdef CONFIG_ARCH_ZX297520V2
-#else
- local_fiq_enable();
-#endif
- local_irq_enable();
-
- idle_time = ktime_to_ns(ktime_sub(exit_time, entry_time));
-
- dev->last_residency_ns = (int)idle_time;
-
- if(print_enabled_by_debug != 0)
- {
- printk(KERN_INFO "[CPUIDLE] exit idle: idle time= %d , enter level= %d !\n", (u32)idle_time, index);
- }
-
- return index;
-}
-
-
-
-static int idle_pm_notify(struct notifier_block *nb,
- unsigned long event, void *dummy)
-{
-#ifdef CONFIG_PM_SLEEP
- if (event == PM_SUSPEND_PREPARE)
- deep_idle_disabled_by_suspend = true;
- else if (event == PM_POST_SUSPEND)
- deep_idle_disabled_by_suspend = false;
-#endif
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block idle_pm_notifier =
-{
- .notifier_call = idle_pm_notify,
-};
-
-/**
- * zx_cpuidle_init - Init routine for zx29xx idle
- *
- * Registers the cpuidle driver with the cpuidle
- * framework with the valid set of states.
- */
-int zx_cpuidle_init(void)
-{
-
-#if 1
- arm_pm_idle = zx_cpu_idle;
- zx_apmgclken_set(0);
- printk(KERN_INFO "[CPUIDLE] zx_cpu_idle init OK\n,");
-#else
- int cpu_id;
- struct cpuidle_device *device;
- struct cpuidle_driver *drv = &zx_idle_driver;
-
- /* Setup cpuidle driver */
- drv->state_count = zx_fill_cpuidle_data(drv);
- cpuidle_register_driver(drv);
-
- /* Setup cpuidle device for each cpu */
- for_each_cpu(cpu_id, cpu_online_mask)
- {
- device = &per_cpu(zx_idle_dev, cpu_id);
- device->cpu = cpu_id;
-
- if (cpu_id == 0)
- device->state_count = drv->state_count;
- else
- device->state_count = 1; /* None boot cpu Support IDLE only now ! */
-
- if (cpuidle_register_device(device))
- {
- printk(KERN_ERR "[CPUIDLE] register device failed\n,");
- return -EIO;
- }
- }
-
- register_pm_notifier(&idle_pm_notifier);
-
- INIT_DELAYED_WORK_DEFERRABLE(&pm_idle_work, pm_idle_func);
- schedule_delayed_work(&pm_idle_work, PM_IDLE_DELAY);
-
- printk(KERN_INFO "[CPUIDLE] register device OK\n,");
-#endif
-
- return 0;
-}
-
-#if 0
-static void __exit zx_cpuidle_exit(void)
-{
- unregister_pm_notifier(&idle_pm_notifier);
- cpuidle_unregister_driver(&zx_idle_driver);
-}
-
-late_initcall(zx_cpuidle_init);
-module_exit(zx_cpuidle_exit);
-#endif
-
-#ifdef CONFIG_ZX_PM_DEBUG
-static char* lp2_debug_show(char *s)
-{
- #if 0
- int i;
-
- s += sprintf(s, "%-30s%8s %8s %8s %8s\n", " ", "cpu0","cpu1","cpu2","cpu3");
- s += sprintf(s, "%s\n", "---------------------------------------------------------------");
- s += sprintf(s, "%-30s%8u %8u %8u %8u\n", "lp3 in count:",
- idle_stats.lp3_count[0],
- idle_stats.lp3_count[1],
- idle_stats.lp3_count[2],
- idle_stats.lp3_count[3]);
-
- s += sprintf(s, "%-30s%8u %8u %8u %8u\n", "lp2 in count:",
- idle_stats.lp2_count[0],
- idle_stats.lp2_count[1],
- idle_stats.lp2_count[2],
- idle_stats.lp2_count[3]);
-
- s += sprintf(s, "%-30s%8u %8u %8u %8u\n", "lp2 completed:",
- idle_stats.lp2_completed_count[0],
- idle_stats.lp2_completed_count[1],
- idle_stats.lp2_completed_count[2],
- idle_stats.lp2_completed_count[3]);
-
- s += sprintf(s, "%-30s%7u%% %7u%% %7u%% %7u%%\n", "lp2 completed%:",
- idle_stats.lp2_completed_count [0]* 100 / (idle_stats.lp2_count[0] ?: 1),
- idle_stats.lp2_completed_count [1]* 100 / (idle_stats.lp2_count[1] ?: 1),
- idle_stats.lp2_completed_count [2]* 100 / (idle_stats.lp2_count[2] ?: 1),
- idle_stats.lp2_completed_count [3]* 100 / (idle_stats.lp2_count[3] ?: 1));
- s += sprintf(s, "%-30s%8u\n", "all idle count:", idle_stats.idle_count);
-
- s += sprintf(s, "\n%-30s%8llu %8llu %8llu %8llu ms\n", "cpu ready time:",
- div64_u64(idle_stats.cpu_wants_lp2_time[0], 1000),
- div64_u64(idle_stats.cpu_wants_lp2_time[1], 1000),
- div64_u64(idle_stats.cpu_wants_lp2_time[2], 1000),
- div64_u64(idle_stats.cpu_wants_lp2_time[3], 1000));
-
- s += sprintf(s, "%-30s%8llu %8llu %8llu %8llu ms\n", "lp2 in time:",
- div64_u64(idle_stats.in_lp2_time[0], 1000),
- div64_u64(idle_stats.in_lp2_time[1], 1000),
- div64_u64(idle_stats.in_lp2_time[2], 1000),
- div64_u64(idle_stats.in_lp2_time[3], 1000));
-
- s += sprintf(s, "%-30s%7d%% %7d%% %7d%% %7d%%\n", "lp2 in time%:",
- (int)(idle_stats.cpu_wants_lp2_time[0] ?
- div64_u64(idle_stats.in_lp2_time[0] * 100,
- idle_stats.cpu_wants_lp2_time[0]) : 0),
- (int)(idle_stats.cpu_wants_lp2_time[1] ?
- div64_u64(idle_stats.in_lp2_time[1] * 100,
- idle_stats.cpu_wants_lp2_time[1]) : 0),
- (int)(idle_stats.cpu_wants_lp2_time[2] ?
- div64_u64(idle_stats.in_lp2_time[2] * 100,
- idle_stats.cpu_wants_lp2_time[2]) : 0),
- (int)(idle_stats.cpu_wants_lp2_time[3] ?
- div64_u64(idle_stats.in_lp2_time[3] * 100,
- idle_stats.cpu_wants_lp2_time[3]) : 0));
-
- s += sprintf(s, "\n\n%3s %20s %6s %10s\n",
- "int", "name", "count", "last count");
- s += sprintf(s, "%s", "--------------------------------------------\n");
- for (i = 0; i < NR_IRQS; i++) {
- if (idle_stats.lp2_int_count[i] == 0)
- continue;
- s += sprintf(s, "%3d %20s %6d %10d\n",
- i - GIC_SPI_START,
- irq_to_desc(i)->action ? irq_to_desc(i)->action->name ?: "???" : "???",
- idle_stats.lp2_int_count[i],
- idle_stats.lp2_int_count[i] - idle_stats.last_lp2_int_count[i]);
-
- idle_stats.last_lp2_int_count[i] = idle_stats.lp2_int_count[i];
- };
- #endif
-
- return s;
-}
-
-/******************************************************
- *** 1 -- lp2 ******************************
- ******************************************************
- */
-static ssize_t lp2_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- s = lp2_debug_show(s);
-
-
- return (s - buf);
-}
-
-static ssize_t lp2_store(struct kobject *kobj, struct kobj_attribute *attr,
-
- const char *buf, size_t n)
-{
-
- int error = 0;
-
-
- return error ;
-}
-
-zte_pm_attr(lp2);
-
-
-/*=============================================================================
- *======== /sys/zte_pm/cpuidle/disable_lp2 ==================================
- *=============================================================================
- */
-static ssize_t disable_lp2_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- s += sprintf(s, "%s %d\n", "[CPUIDLE] deep_idle_disabled_by_debug:", deep_idle_disabled_by_debug);
-
- return (s - buf);
-}
-
-/* usage: "echo 1 > disable_lp2" */
-static ssize_t disable_lp2_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- unsigned int temp;
-
- if(sscanf(buf, "%u", &temp) != 1)
- error = -EINVAL;
-
- deep_idle_disabled_by_debug = temp;
-
- return error ? error : n;
-}
-zte_pm_attr(disable_lp2);
-
-
-/*=============================================================================
- *======== /sys/zte_pm/cpuidle/enable_print ==================================
- *=============================================================================
- */
-static ssize_t enable_print_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- s += sprintf(s, "%s %d\n", "[CPUIDLE] print_enabled_by_debug:", print_enabled_by_debug);
-
- return (s - buf);
-}
-
-/* usage: "echo 1 > enable_print" */
-static ssize_t enable_print_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- unsigned int temp;
-
- if(sscanf(buf, "%u", &temp) != 1)
- error = -EINVAL;
-
- print_enabled_by_debug = temp;
-
- return error ? error : n;
-}
-
-zte_pm_attr(enable_print);
-
-
-/*=============================================================================
- *======== /sys/zte_pm/cpuidle/drv_cpuidle_flag ==================================
- *=============================================================================
- */
-static ssize_t drv_cpuidle_flag_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- s += sprintf(s, "%s %x %x\n", "[CPUIDLE] drv_cpuidle_flag, pm_dma_used(): ", drv_cpuidle_flag, pm_dma_used());
-
- return (s - buf);
-}
-
-/* usage: "echo * > drv_cpuidle_flag" */
-static ssize_t drv_cpuidle_flag_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- unsigned int temp;
-
- if(sscanf(buf, "%u", &temp) != 1)
- error = -EINVAL;
-
- drv_cpuidle_flag = temp;
-
- return error ? error : n;
-}
-
-zte_pm_attr(drv_cpuidle_flag);
-
-
-/*=============================================================================
- *======== /sys/zte_pm/cpuidle/idle_debug_mask ==================================
- *=============================================================================
- */
-static ssize_t enable_idle_debug_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- s += sprintf(s, "%s %d\n", "[CPUIDLE] idle_print_enabled_by_debug:", idle_debug_mask);
-
- return (s - buf);
-}
-
-/* usage: "echo 1 > idle_debug_mask" */
-static ssize_t enable_idle_debug_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- unsigned int temp;
-
- if(sscanf(buf, "%u", &temp) != 1)
- error = -EINVAL;
-
- idle_debug_mask = temp;
-
- return error ? error : n;
-}
-zte_pm_attr(enable_idle_debug);
-
-
-static struct attribute * g[] =
-{
- &lp2_attr.attr,
- &disable_lp2_attr.attr,
- &enable_print_attr.attr,
- &drv_cpuidle_flag_attr.attr,
- &enable_idle_debug_attr.attr,
- NULL,
-};
-
-
-static struct attribute_group idle_attr_group =
-{
- .attrs = g,
-};
-/**
- * idle_debug_init
- * create cpuidle sysfs, we can use cat /sys/zte_pm/cpuidle/lp2 command view debug info
- *
- */
-static struct kobject *idle_kobj;
-
-int __init idle_debug_init(void)
-{
- int ret;
-
- idle_kobj = kobject_create_and_add("cpuidle", pm_debug_kobj);
- if (!idle_kobj)
- return -ENOMEM;
-
- ret = sysfs_create_group(idle_kobj, &idle_attr_group);
- if (ret)
- {
- pr_info("[CPUIDLE] sysfs_create_group ret %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-#endif
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpuidle.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpuidle.h
deleted file mode 100644
index 10abd7d..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-cpuidle.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * arch/arm/mach-zx297510/zx-cpuidle.h
- *
- * Copyright (c) 2013, ZTE Corporation.
- * write by zxp
- *
- */
-
-#ifndef __MACH_ZX_CPU_IDLE_H
-#define __MACH_ZX_CPU_IDLE_H
-
-#ifdef CONFIG_ZX_PM_DEBUG
-#define DEBUG_CPU_NUM 4
-/*record idle states info*/
-struct zx_idle_stats
-{
- unsigned int cpu_ready_count[DEBUG_CPU_NUM];
- unsigned int tear_down_count[DEBUG_CPU_NUM];
- unsigned long long cpu_wants_lp2_time[DEBUG_CPU_NUM];
- unsigned long long in_lp2_time[DEBUG_CPU_NUM];
- unsigned int lp2_count[DEBUG_CPU_NUM];
- unsigned int lp2_completed_count[DEBUG_CPU_NUM];
- unsigned int lp3_count[DEBUG_CPU_NUM];
- //unsigned int lp2_count_bin[32];
- //unsigned int lp2_completed_count_bin[32];
- unsigned int lp2_int_count[NR_IRQS];
- unsigned int last_lp2_int_count[NR_IRQS];
- unsigned int idle_count;
-};
-#endif
-
-#define ZX_IDLE_CSTATE_LP3 0
-#define ZX_IDLE_CSTATE_LP2 1
-#define ZX_IDLE_MAX_CSTATE 2
-
-/*
- *cpuidle functions
- */
-extern int __init zx_cpuidle_init(void);
-extern s64 idle_get_sleeptime(void);
-#ifdef CONFIG_ZX_PM_DEBUG
-extern int __init idle_debug_init(void);
-#endif
-extern int __init zx_fill_cpuidle_data(struct cpuidle_driver *drv);
-extern int zx_enter_idle(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index);
-extern int zx_pm_idle_enter(int index);
-
-#if defined CONFIG_SYSTEM_RECOVERY || defined _USE_TestHarness
-static int zx_idle_get_debug_flag(void){return 0;}
-static int zx_idle_get_idle_flag(void){return 0;}
-#endif
-
-#endif /* __MACH_ZX_CPU_IDLE_H */
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-a53.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-a53.c
deleted file mode 100644
index 5ebaf74..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-a53.c
+++ /dev/null
@@ -1,1348 +0,0 @@
-/*
- * ZTE cpu context save&restore driver
- *
- * Copyright (C) 2013 ZTE Ltd.
- * by zxp
- *
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/suspend.h>
-
-#include "zx-pm.h"
-
-/*=======================================================================
- *=======================================================================
- *======= [ZX-PM] timer interface for power management ===========================
- *=======================================================================
- *=======================================================================*/
-
-typedef struct
-{
- /* 0x00 */ volatile unsigned timer_load;
- /* 0x04 */ volatile unsigned timer_counter;
- /* 0x08 */ volatile unsigned timer_control;
- /* 0x0c */ volatile unsigned timer_interrupt_status;
- char padding1[0x10];
- /* 0x20 */ volatile unsigned watchdog_load;
- /* 0x24 */ volatile unsigned watchdog_counter;
- /* 0x28 */ volatile unsigned watchdog_control;
- /* 0x2c */ volatile unsigned watchdog_interrupt_status;
- /* 0x30 */ volatile unsigned watchdog_reset_status;
- /* 0x34 */ volatile unsigned watchdog_disable;
-} a9_timer_registers;
-
-typedef struct
-{
- unsigned timer_load;
- unsigned timer_counter;
- unsigned timer_control;
- unsigned timer_interrupt_status;
- unsigned watchdog_load;
- unsigned watchdog_counter;
- unsigned watchdog_control;
- unsigned watchdog_interrupt_status;
-} a9_timer_context;
-
-
-void save_a9_timers(u32 *pointer, unsigned twd_address)
-{
- a9_timer_context *context = (a9_timer_context *)pointer;
- a9_timer_registers *timers = (a9_timer_registers *)twd_address;
-
- /*
- * First, stop the timers
- */
- context->timer_control = timers->timer_control;
- timers->timer_control = 0;
- context->watchdog_control = timers->watchdog_control;
- timers->watchdog_control = 0;
-
- context->timer_load = timers->timer_load;
- context->timer_counter = timers->timer_counter;
- context->timer_interrupt_status = timers->timer_interrupt_status;
- context->watchdog_load = timers->watchdog_load;
- context->watchdog_counter = timers->watchdog_counter;
- context->watchdog_interrupt_status = timers->watchdog_interrupt_status;
- /*
- * We ignore watchdog_reset_status, since it can only clear the status bit.
- * If the watchdog has reset the system, the OS will want to know about it.
- * Similarly, we have no use for watchdog_disable - this is only used for
- * returning to timer mode, which is the default mode after reset.
- */
-}
-
-void restore_a9_timers(u32 *pointer, unsigned twd_address)
-{
- a9_timer_context *context = (a9_timer_context *)pointer;
- a9_timer_registers *timers = (a9_timer_registers *)twd_address;
-
- timers->timer_control = 0;
- timers->watchdog_control = 0;
-
- /*
- * We restore the load register first, because it also sets the counter register.
- */
- timers->timer_load = context->timer_load;
- timers->watchdog_load = context->watchdog_load;
-
- /*
- * If a timer has reached zero (presumably during the context save) and triggered
- * an interrupt, then we set it to the shortest possible expiry time, to make it
- * trigger again real soon.
- * We could fake this up properly, but we would have to wait around until the timer
- * ticked, which could be some time if PERIPHCLK is slow. This approach should be
- * good enough in most cases.
- */
- if (context->timer_interrupt_status)
- {
- timers->timer_counter = 1;
- }
- else
- {
- timers->timer_counter = context->timer_counter;
- }
-
- if (context->watchdog_interrupt_status)
- {
- timers->watchdog_counter = 1;
- }
- else
- {
- timers->watchdog_counter = context->watchdog_counter;
- }
-
- timers->timer_control = context->timer_control;
- timers->watchdog_control = context->watchdog_control;
-}
-
-
-typedef struct
-{
- /* 0x00 */ volatile unsigned timer_version;
- /* 0x04 */ volatile unsigned timer_config;
- /* 0x08 */ volatile unsigned timer_load;
- /* 0x0c */ volatile unsigned timer_start;
- /* 0x10 */ volatile unsigned timer_set_en;
- /* 0x14 */ volatile unsigned timer_ack;
- /* 0x18 */ volatile unsigned timer_count;
-} a53_global_timer_registers;
-
-typedef struct
-{
- unsigned timer_version;
- unsigned timer_config;
- unsigned timer_load;
- unsigned timer_start;
- unsigned timer_set_en;
- unsigned timer_ack;
- unsigned timer_count;
-
-} a53_global_timer_context;
-
-#define A53_GT_TIMER_ENABLE (1<<0)
-#define A53_GT_COMPARE_ENABLE (1<<1)
-#define A53_GT_AUTO_INCREMENT_ENABLE (1<<3)
-#define A53_GT_EVENT_FLAG (1<<0)
-
-void save_a53_sys_timer(u32 *pointer, unsigned timer_address)
-{
- a53_global_timer_registers *timer = (void*)timer_address;
- a53_global_timer_context *context = (void*)pointer;
-
- context->timer_config = timer->timer_config;
-
- context->timer_load = timer->timer_load;
- context->timer_start = timer->timer_start;
- timer->timer_start = 0;
- context->timer_set_en = timer->timer_set_en;
- context->timer_ack = timer->timer_ack; /* Ö»¶Á£¬²»Óûָ´*/
- context->timer_count = timer->timer_count;
-
-}
-
-void restore_a53_sys_timer(u32 *pointer, unsigned timer_address)
-{
- a53_global_timer_registers *timer = (void*)timer_address;
- a53_global_timer_context *context = (void*)pointer;
-
- timer->timer_config =context->timer_config;
- timer->timer_load = context->timer_load;/*ÕâÀïÓ¦¸ÃÊǸ³³õÖµ*/
- timer->timer_set_en =context->timer_set_en;
- timer->timer_start = context->timer_start;
-}
-
-
-/*=======================================================================
- *=======================================================================
- *======= [ZX-PM] SCU interface for power management ============================
- *=======================================================================
- *=======================================================================*/
-typedef struct
-{
- /* 0x00 */ volatile unsigned int control;
- /* 0x04 */ const unsigned int configuration;
- /* 0x08 */ union
- {
- volatile unsigned int w;
- volatile unsigned char b[4];
- } power_status;
- /* 0x0c */ volatile unsigned int invalidate_all;
- char padding1[48];
- /* 0x40 */ volatile unsigned int filtering_start;
- /* 0x44 */ volatile unsigned int filtering_end;
- char padding2[8];
- /* 0x50 */ volatile unsigned int access_control;
- /* 0x54 */ volatile unsigned int ns_access_control;
-} a53_scu_registers;
-
-/*
- * TODO: we need to use the power status register, not save it!
- */
-
-void save_a53_scu(u32 *pointer, unsigned scu_address)
-{
- a53_scu_registers *scu = (a53_scu_registers *)scu_address;
-
- pointer[0] = scu->control;
- pointer[1] = scu->power_status.w;
- pointer[2] = scu->filtering_start;
- pointer[3] = scu->filtering_end;
- pointer[4] = scu->access_control;
- pointer[5] = scu->ns_access_control;
-}
-
-void restore_a53_scu(u32 *pointer, unsigned scu_address)
-{
- a53_scu_registers *scu = (a53_scu_registers *)scu_address;
-
- scu->invalidate_all = 0xffff;
- scu->filtering_start = pointer[2];
- scu->filtering_end = pointer[3];
-//zxp scu->access_control = pointer[4];
- scu->ns_access_control = pointer[5];
- scu->power_status.w = pointer[1];
- scu->control = pointer[0];
-}
-
-void set_status_a53_scu(unsigned cpu_index, unsigned status, unsigned scu_address)
-{
- a53_scu_registers *scu = (a53_scu_registers *)scu_address;
- unsigned power_status;
-
- switch(status)
- {
- case CPU_POWER_MODE_STANDBY:
- case CPU_POWER_MODE_DORMANT:
- power_status = 2;
- break;
- case CPU_POWER_MODE_SHUTDOWN:
- power_status = 3;
- break;
- default:
- power_status = 0;
- }
-
- scu->power_status.b[cpu_index] = power_status;
- dsb();
-}
-
-void init_lp_of_scu(unsigned scu_address)
-{
- a53_scu_registers *scu = (a53_scu_registers *)scu_address;
-
- scu->control |= 0x61;
-}
-
-
-int num_cpus_from_a53_scu(unsigned scu_address)
-{
- a53_scu_registers *scu = (a53_scu_registers *)scu_address;
-
- return ((scu->configuration) & 0x3) + 1;
-}
-
-
-/*=======================================================================
- *=======================================================================
- *======= [ZX-PM] PL310 interface for power management ==========================
- *=======================================================================
- *=======================================================================*/
-
-
-#define C_BIT 0x01
-
-struct lockdown_regs
-{
- unsigned int d, i;
-};
-
-typedef struct
-{
- /* 0x000 */ const unsigned cache_id;
- /* 0x004 */ const unsigned cache_type;
- char padding1[0x0F8];
- /* 0x100 */ volatile unsigned control;
- /* 0x104 */ volatile unsigned aux_control;
- /* 0x108 */ volatile unsigned tag_ram_control;
- /* 0x10C */ volatile unsigned data_ram_control;
- char padding2[0x0F0];
- /* 0x200 */ volatile unsigned ev_counter_ctrl;
- /* 0x204 */ volatile unsigned ev_counter1_cfg;
- /* 0x208 */ volatile unsigned ev_counter0_cfg;
- /* 0x20C */ volatile unsigned ev_counter1;
- /* 0x210 */ volatile unsigned ev_counter0;
- /* 0x214 */ volatile unsigned int_mask;
- /* 0x218 */ const volatile unsigned int_mask_status;
- /* 0x21C */ const volatile unsigned int_raw_status;
- /* 0x220 */ volatile unsigned int_clear;
- char padding3[0x50C];
- /* 0x730 */ volatile unsigned cache_sync;
- char padding4[0x03C];
- /* 0x770 */ volatile unsigned inv_pa;
- char padding5[0x008];
- /* 0x77C */ volatile unsigned inv_way;
- char padding6[0x030];
- /* 0x7B0 */ volatile unsigned clean_pa;
- char padding7[0x004];
- /* 0x7B8 */ volatile unsigned clean_index;
- /* 0x7BC */ volatile unsigned clean_way;
- char padding8[0x030];
- /* 0x7F0 */ volatile unsigned clean_inv_pa;
- char padding9[0x004];
- /* 0x7F8 */ volatile unsigned clean_inv_index;
- /* 0x7FC */ volatile unsigned clean_inv_way;
- char paddinga[0x100];
- /* 0x900 */ volatile struct lockdown_regs lockdown[8];
- char paddingb[0x010];
- /* 0x950 */ volatile unsigned lock_line_en;
- /* 0x954 */ volatile unsigned unlock_way;
- char paddingc[0x2A8];
- /* 0xC00 */ volatile unsigned addr_filtering_start;
- /* 0xC04 */ volatile unsigned addr_filtering_end;
- char paddingd[0x338];
- /* 0xF40 */ volatile unsigned debug_ctrl;
- char paddinge[0x01C];
- /* 0xF60 */ volatile unsigned prefetch_ctrl;
- char paddingf[0x01C];
- /* 0xF80 */ volatile unsigned power_ctrl;
-} pl310_registers;
-
-
-typedef struct
-{
- unsigned int aux_control;
- unsigned int tag_ram_control;
- unsigned int data_ram_control;
- unsigned int ev_counter_ctrl;
- unsigned int ev_counter1_cfg;
- unsigned int ev_counter0_cfg;
- unsigned int ev_counter1;
- unsigned int ev_counter0;
- unsigned int int_mask;
- unsigned int lock_line_en;
- struct lockdown_regs lockdown[8];
- unsigned int unlock_way;
- unsigned int addr_filtering_start;
- unsigned int addr_filtering_end;
- unsigned int debug_ctrl;
- unsigned int prefetch_ctrl;
- unsigned int power_ctrl;
-} pl310_context;
-
-/* TODO: should be determined from cache? */
-static unsigned const cache_line_size = 32;
-
-void clean_inv_range_pl310(void *start, unsigned size, unsigned pl310_address)
-{
- unsigned addr;
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
-
- /* Align the start address to the start of a cache line */
- addr = (unsigned)start & ~(cache_line_size - 1);
-
- /* Wait for any background operations to finish */
- while(pl310->clean_inv_pa & C_BIT);
-
- while(addr <= size + (unsigned)start)
- {
- pl310->clean_inv_pa = addr;
- addr += cache_line_size;
- /* For this to work on L220 we would have to poll the C bit now */
- }
- dmb();
-}
-
-void clean_range_pl310(void *start, unsigned size, unsigned pl310_address)
-{
- unsigned addr;
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
-
- /* Align the start address to the start of a cache line */
- addr = (unsigned)start & ~(cache_line_size - 1);
-
- /* Wait for any background operations to finish */
- while(pl310->clean_pa & C_BIT);
-
- while(addr <= size + (unsigned)start)
- {
- pl310->clean_pa = addr;
- addr += cache_line_size;
- /* For this to work on L220 we would have to poll the C bit now */
- }
- dmb();
-}
-
-void inv_range_pl310(void *start, unsigned size, unsigned pl310_address)
-{
- unsigned addr;
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
-
- /* Align the start address to the start of a cache line */
- addr = (unsigned)start & ~(cache_line_size - 1);
-
- /* Wait for any background operations to finish */
- while(pl310->inv_pa & C_BIT);
-
- while(addr <= size + (unsigned)start)
- {
- pl310->inv_pa = addr;
- addr += cache_line_size;
- /* For this to work on L220 we would have to poll the C bit now */
- }
-}
-
-void clean_inv_pl310(unsigned pl310_address)
-{
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
- int i;
-
- pl310->clean_inv_way = 0xffff;
- while (pl310->clean_inv_way)
- {
- /* Spin */
- for (i=10; i>0; --i)
- {
- __nop();
- }
- }
-}
-
-void clean_pl310(unsigned pl310_address)
-{
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
- int i;
-
- pl310->clean_way = 0xffff;
- while (pl310->clean_way)
- {
- /* Spin */
- for (i=10; i>0; --i)
- {
- __nop();
- }
- }
-}
-
-static void inv_pl310(unsigned pl310_address)
-{
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
- int i;
-
- pl310->inv_way = 0xffff;
- while (pl310->inv_way)
- {
- /* Spin */
- for (i=10; i>0; --i)
- {
- __nop();
- }
- }
-}
-
-void clean_disable_pl310(unsigned pl310_address)
-{
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
- int i;
-
- pl310->clean_way = 0xffff;
- while (pl310->clean_way)
- {
- /* Spin */
- for (i=10; i>0; --i)
- {
- __nop();
- }
- }
-
- pl310->cache_sync = 0;
- dsb();
- pl310->control = 0;
-}
-
-
-int is_enabled_pl310(unsigned pl310_address)
-{
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
-
- return (pl310->control & 1);
-}
-
-void save_pl310(u32 *pointer, unsigned pl310_address)
-{
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
- pl310_context *context = (pl310_context *)pointer;
- int i;
-
- /* TODO: are all these registers are present in earlier PL310 versions? */
- context->aux_control = pl310->aux_control;
- context->tag_ram_control = pl310->tag_ram_control;
- context->data_ram_control = pl310->data_ram_control;
- context->ev_counter_ctrl = pl310->ev_counter_ctrl;
- context->ev_counter1_cfg = pl310->ev_counter1_cfg;
- context->ev_counter0_cfg = pl310->ev_counter0_cfg;
- context->ev_counter1 = pl310->ev_counter1;
- context->ev_counter0 = pl310->ev_counter0;
- context->int_mask = pl310->int_mask;
- context->lock_line_en = pl310->lock_line_en;
-
- /*
- * The lockdown registers repeat 8 times for L310, the L210 has only one
- * D and one I lockdown register at 0x0900 and 0x0904.
- */
- for (i=0; i<8; ++i)
- {
- context->lockdown[i].d = pl310->lockdown[i].d;
- context->lockdown[i].i = pl310->lockdown[i].i;
- }
-
- context->addr_filtering_start = pl310->addr_filtering_start;
- context->addr_filtering_end = pl310->addr_filtering_end;
- context->debug_ctrl = pl310->debug_ctrl;
- context->prefetch_ctrl = pl310->prefetch_ctrl;
- context->power_ctrl = pl310->power_ctrl;
-}
-
-void restore_pl310(u32 *pointer, unsigned pl310_address, int dormant)
-{
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
- pl310_context *context = (pl310_context *)pointer;
- int i;
-
- /* We may need to disable the PL310 if the boot code has turned it on */
- if (pl310->control)
- {
- /* Wait for the cache to be idle, then disable */
- pl310->cache_sync = 0;
- dsb();
- pl310->control = 0;
- }
-
- /* TODO: are all these registers present in earlier PL310 versions? */
- pl310->aux_control = context->aux_control;
- pl310->tag_ram_control = context->tag_ram_control;
- pl310->data_ram_control = context->data_ram_control;
- pl310->ev_counter_ctrl = context->ev_counter_ctrl;
- pl310->ev_counter1_cfg = context->ev_counter1_cfg;
- pl310->ev_counter0_cfg = context->ev_counter0_cfg;
- pl310->ev_counter1 = context->ev_counter1;
- pl310->ev_counter0 = context->ev_counter0;
- pl310->int_mask = context->int_mask;
- pl310->lock_line_en = context->lock_line_en;
-
- for (i=0; i<8; ++i)
- {
- pl310->lockdown[i].d = context->lockdown[i].d;
- pl310->lockdown[i].i = context->lockdown[i].i;
- }
-
- pl310->addr_filtering_start = context->addr_filtering_start;
- pl310->addr_filtering_end = context->addr_filtering_end;
- pl310->debug_ctrl = context->debug_ctrl;
- pl310->prefetch_ctrl = context->prefetch_ctrl;
- pl310->power_ctrl = context->power_ctrl;
- dsb();
-
- /*
- * If the RAMs were powered off, we need to invalidate the cache
- */
- if (!dormant)
- {
- inv_pl310(pl310_address);
- }
-
- pl310->control = 1;
- dsb();
-}
-
-void set_enabled_pl310(unsigned enabled, unsigned pl310_address)
-{
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
-
- if (enabled)
- {
- inv_pl310(pl310_address);
-
- pl310->control |= 1;
- pl310->cache_sync = 0;
- dsb();
- }
- else
- {
- /* Wait for the cache to be idle */
- pl310->cache_sync = 0;
- dsb();
- pl310->control &= ~1;
- }
-}
-
-void set_status_pl310(unsigned status, unsigned pl310_address)
-{
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
-
- if (status == CPU_POWER_MODE_STANDBY)
- {
- /* Wait for the cache to be idle */
- pl310->cache_sync = 0;
- dsb();
- pl310->power_ctrl |= 1;
- }
- else
- {
- pl310->power_ctrl &= ~1;
- }
-}
-
-void init_lp_of_l2(unsigned pl310_address)
-{
- pl310_registers *pl310 = (pl310_registers *)pl310_address;
-
- pl310->power_ctrl |= 3;
-}
-
-/*=======================================================================
- *=======================================================================
- *======= [ZX-PM] GIC interface for power management ============================
- *=======================================================================
- *=======================================================================*/
-
-
-/* This macro sets either the NS or S enable bit in the GIC distributor control register */
-#define GIC_DIST_ENABLE 0x00000001
-
-struct set_and_clear_regs
-{
- volatile unsigned int set[32], clear[32];
-};
-
-
-typedef struct
-{
- volatile uint32_t GICD_CTLR; // +0x0000 - RW - Distributor Control Register
- const volatile uint32_t GICD_TYPRE; // +0x0004 - RO - Interrupt Controller Type Register
- const volatile uint32_t GICD_IIDR; // +0x0008 - RO - Distributor Implementer Identification Register
-
- const volatile uint32_t padding0; // +0x000C - RESERVED
-
- volatile uint32_t GICD_STATUSR; // +0x0010 - RW - ????
-
- const volatile uint32_t padding1[3]; // +0x0014 - RESERVED
-
- volatile uint32_t IMP_DEF[8]; // +0x0020 - RW - Implementation defined registers
-
- volatile uint32_t GICD_SETSPI_NSR; // +0x0040 - WO - Non-Secure Set SPI Pending (Used when SPI is signalled using MSI)
- const volatile uint32_t padding2; // +0x0044 - RESERVED
- volatile uint32_t GICD_CLRSPI_NSR; // +0x0048 - WO - Non-Secure Clear SPI Pending (Used when SPI is signalled using MSI)
- const volatile uint32_t padding3; // +0x004C - RESERVED
- volatile uint32_t GICD_SETSPI_SR; // +0x0050 - WO - Secure Set SPI Pending (Used when SPI is signalled using MSI)
- const volatile uint32_t padding4; // +0x0054 - RESERVED
- volatile uint32_t GICD_CLRSPI_SR; // +0x0058 - WO - Secure Clear SPI Pending (Used when SPI is signalled using MSI)
-
- const volatile uint32_t padding5[3]; // +0x005C - RESERVED
-
- volatile uint32_t GICD_SEIR; // +0x0068 - WO - System Error Interrupt Register (Note: This was recently removed from the spec)
-
- const volatile uint32_t padding6[5]; // +0x006C - RESERVED
-
- volatile uint32_t GICD_IGROUPR[32]; // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1)
-
- volatile uint32_t GICD_ISENABLER[32]; // +0x0100 - RW - Interrupt Set-Enable Registers
- volatile uint32_t GICD_ICENABLER[32]; // +0x0180 - RW - Interrupt Clear-Enable Registers
- volatile uint32_t GICD_ISPENDR[32]; // +0x0200 - RW - Interrupt Set-Pending Registers
- volatile uint32_t GICD_ICPENDR[32]; // +0x0280 - RW - Interrupt Clear-Pending Registers
- volatile uint32_t GICD_ISACTIVER[32]; // +0x0300 - RW - Interrupt Set-Active Register
- volatile uint32_t GICD_ICACTIVER[32]; // +0x0380 - RW - Interrupt Clear-Active Register
-
- volatile uint8_t GICD_IPRIORITYR[1024]; // +0x0400 - RW - Interrupt Priority Registers
- volatile uint32_t GICD_ITARGETSR[256]; // +0x0800 - RW - Interrupt Processor Targets Registers
- volatile uint32_t GICD_ICFGR[64]; // +0x0C00 - RW - Interrupt Configuration Registers
- volatile uint32_t GICD_GRPMODR[32]; // +0x0D00 - RW - ????
- const volatile uint32_t padding7[32]; // +0x0D80 - RESERVED
- volatile uint32_t GICD_NSACR[64]; // +0x0E00 - RW - Non-Secure Access Control Register
-
- volatile uint32_t GICD_SGIR; // +0x0F00 - WO - Software Generated Interrupt Register
-
- const volatile uint32_t padding8[3]; // +0x0F04 - RESERVED
-
- volatile uint32_t GICD_CPENDSGIR[4]; // +0x0F10 - RW - ???
- volatile uint32_t GICD_SPENDSGIR[4]; // +0x0F20 - RW - ???
-
- const volatile uint32_t padding9[52]; // +0x0F30 - RESERVED
- const volatile uint32_t padding10[5120]; // +0x1000 - RESERVED
-
- volatile uint64_t GICD_ROUTER[1024]; // +0x6000 - RW - Controls SPI routing when ARE=1
-}interrupt_distributor;
-
-typedef struct
-{
- const volatile uint32_t padding1[32]; // +0x0000 - RESERVED
- volatile uint32_t GICR_IGROUPR; // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1)
- const volatile uint32_t padding2[31]; // +0x0084 - RESERVED
- volatile uint32_t GICR_ISENABLER; // +0x0100 - RW - Interrupt Set-Enable Registers
- const volatile uint32_t padding3[31]; // +0x0104 - RESERVED
- volatile uint32_t GICR_ICENABLER; // +0x0180 - RW - Interrupt Clear-Enable Registers
- const volatile uint32_t padding4[31]; // +0x0184 - RESERVED
- volatile uint32_t GICR_ISPENDR; // +0x0200 - RW - Interrupt Set-Pending Registers
- const volatile uint32_t padding5[31]; // +0x0204 - RESERVED
- volatile uint32_t GICR_ICPENDR; // +0x0280 - RW - Interrupt Clear-Pending Registers
- const volatile uint32_t padding6[31]; // +0x0284 - RESERVED
- volatile uint32_t GICR_ISACTIVER; // +0x0300 - RW - Interrupt Set-Active Register
- const volatile uint32_t padding7[31]; // +0x0304 - RESERVED
- volatile uint32_t GICR_ICACTIVER; // +0x0380 - RW - Interrupt Clear-Active Register
- const volatile uint32_t padding8[31]; // +0x0184 - RESERVED
- volatile uint8_t GICR_IPRIORITYR[32]; // +0x0400 - RW - Interrupt Priority Registers
- const volatile uint32_t padding9[504]; // +0x0420 - RESERVED
- volatile uint32_t GICR_ICFGR[2]; // +0x0C00 - RW - Interrupt Configuration Registers
- const volatile uint32_t padding10[62]; // +0x0C08 - RESERVED
- volatile uint32_t GICR_GRPMODR; // +0x0D00 - RW - ????
- const volatile uint32_t padding11[63]; // +0x0D04 - RESERVED
- volatile uint32_t GICR_NSACR; // +0x0E00 - RW - Non-Secure Access Control Register
-
-}interrupt_redistributor;
-
-
-typedef struct
-{
- /* 0x00 */ volatile unsigned int GICC_CTLR; /*control*/
- /* 0x04 */ volatile unsigned int GICC_PMR; /*priority mask register*/
- /* 0x08 */ volatile unsigned int GICC_BPR; /* binary Point register*/
- /* 0x0c */ volatile unsigned const int GICC_IAR;
- /* 0x10 */ volatile unsigned int GICC_EOIR;
- /* 0x14 */ volatile unsigned const int GICC_RPR;
- /* 0x18 */ volatile unsigned const int GICC_HPPIR;
- /* 0x1c */ volatile unsigned int GICC_ABPR;
- /* 0x1c */ volatile unsigned int GICC_AIAR;
- /* 0x1c */ volatile unsigned int GICC_AEOIR;
- /* 0x1c */ volatile unsigned int GICC_AHPPIR;
- /* 0x1c */ volatile unsigned int GICC_APR0;
- /* 0x1c */ volatile unsigned int GICC_NSAPR0;
- /* 0x1c */ volatile unsigned int GICC_IIDR;
-
-} cpu_interface;
-
-
-/*
- * Saves the GIC CPU interface context
- * Requires 3 or 4 words of memory
- */
-void save_gic_interface(u32 *pointer, unsigned gic_interface_address, int is_secure)
-{
-#if 1
- cpu_interface *ci = (cpu_interface *)gic_interface_address;
-
- pointer[0] = ci->GICC_CTLR;
- pointer[1] = ci->GICC_PMR;
- pointer[2] = ci->GICC_BPR;
-
- //ci->GICC_PMR = 0;
- // ci->GICC_BPR = 0;
- //ci->GICC_CTLR = 0;
- if (is_secure)
- {
- pointer[3] = ci->GICC_ABPR;
- // ci->GICC_ABPR = 0;// Çå0
- }
-#else
-{
- save_cpu_if(pointer);
-}
-
-#endif
-}
-
-/*
- * Enables or disables the GIC distributor (for the current security state)
- * Parameter 'enabled' is boolean.
- * Return value is boolean, and reports whether GIC was previously enabled.
- */
-int gic_distributor_set_enabled(int enabled, unsigned gic_distributor_address)
-{
- unsigned tmp;
- interrupt_distributor *id = (interrupt_distributor *)gic_distributor_address;
-
- tmp = id->GICD_CTLR;
- if (enabled)
- {
- id->GICD_CTLR = tmp | GIC_DIST_ENABLE;
- }
- else
- {
- id->GICD_CTLR = tmp & ~GIC_DIST_ENABLE;
- }
- return (tmp & GIC_DIST_ENABLE) != 0;
-}
-
-/*
- * Saves this CPU's banked parts of the distributor
- * Returns non-zero if an SGI/PPI interrupt is pending (after saving all required context)
- * Requires 19 words of memory
- */
-int save_gic_distributor_private(u32 *pointer, unsigned gic_distributor_address, int is_secure)
-{
-#if 0 //zhangpei
- interrupt_distributor *id = (interrupt_distributor *)gic_distributor_address;
-
- *pointer = id->enable.set[0];
- ++pointer;
- pointer = copy_words(pointer, id->priority, 8);
- pointer = copy_words(pointer, id->target, 8);
- if (is_secure)
- {
- *pointer = id->security[0];
- ++pointer;
- }
- /* Save just the PPI configurations (SGIs are not configurable) */
- *pointer = id->configuration[1];
- ++pointer;
- *pointer = id->pending.set[0];
- if (*pointer)
- {
- return -1;
- }
- else
- {
- return 0;
- }
-#endif
-
-return 0;
-
-}
-
-/*
- * Saves the shared parts of the distributor.
- * Requires 1 word of memory, plus 20 words for each block of 32 SPIs (max 641 words)
- * Returns non-zero if an SPI interrupt is pending (after saving all required context)
- */
-int save_gic_distributor_shared(u32 *pointer, unsigned int gic_distributor_address, int is_secure)
-{
-
- interrupt_distributor *id = (interrupt_distributor *)gic_distributor_address;
- // interrupt_redistributor *ird =(interrupt_redistributor *)(gic_distributor_address+0x40000)
- int retval = 0;
- #if 0
- unsigned num_spis, *saved_pending;
-
-
-
- /* Calculate how many SPIs the GIC supports */
- num_spis = 32 * (id->GICD_TYPRE & 0x1f);
-
- /* TODO: add nonsecure stuff */
-
- /* Save rest of GIC configuration */
- if (num_spis)
- {
- pointer = copy_words(pointer, id->enable.set + 1, num_spis / 32);
- pointer = copy_words(pointer, id->priority + 8, num_spis / 4);
- pointer = copy_words(pointer, id->target + 8, num_spis / 4);
- pointer = copy_words(pointer, id->configuration + 2, num_spis / 16);
- if (is_secure)
- {
- pointer = copy_words(pointer, id->security + 1, num_spis / 32);
- }
- saved_pending = pointer;
- pointer = copy_words(pointer, id->pending.set + 1, num_spis / 32);
-
- /* Check interrupt pending bits */
- /* zxp-- later we will check only useful int line */
- for (i=0; i<num_spis/32; ++i)
- {
- if (saved_pending[i])
- {
- retval = -1;
- break;
- }
- }
- }
- /* Save control register */
- *pointer = id->control;
-#else
-#if 1/*GICV3*//*±£´æ²»Çå0*/
-pointer = copy_words(pointer, id->GICD_ISENABLER,32); /*0x100~0x17C interrupt set-enable reg*/
-pointer = copy_words(pointer, id->GICD_ICFGR,64); /*0xc00~0xcfc interrupt config reg*/
-pointer = copy_words(pointer, id->GICD_GRPMODR,32); /*0xd00~d7c interrupt group modifer gre */
-pointer = copy_words(pointer, id->GICD_IGROUPR,32); /*0x80~0xfc interrupt group reg*/
-pointer = copy_words(pointer, id->GICD_ISPENDR,32); /*0x200~0x27c interrupt set-pending reg*/
-pointer = copy_words(pointer, (volatile unsigned int *)id->GICD_IPRIORITYR,32); /*0x400~0x7f8 Interrupt Priority Reg reg*/
-pointer = copy_words(pointer, (volatile unsigned int *)id->GICD_ROUTER,32); /*0x6100~0x7ef8 Interrupt Priority Reg reg 1024 64bit*/
-pointer = copy_words(pointer, &(id->GICD_CTLR),1); /*0x0~0x3, ditribrutor control reg*/
-// - zxp pointer = copy_words(pointer, (volatile unsigned int *)(gic_distributor_address+0x40000+0x14),1); /* GICR_WAKER*/
-#else/*GICV3*//*±£´æ²¢Çå0*/
-pointer = copy_wordsandclear(pointer, id->GICD_ISENABLER,32); /*0x100~0x17C interrupt set-enable reg*/
-pointer = copy_wordsandclear(pointer, id->GICD_ICFGR,64); /*0xc00~0xcfc interrupt config reg*/
-pointer = copy_wordsandclear(pointer, id->GICD_GRPMODR,32); /*0xd00~d7c interrupt group modifer gre */
-pointer = copy_wordsandclear(pointer, id->GICD_IGROUPR,32); /*0x80~0xfc interrupt group reg*/
-pointer = copy_wordsandclear(pointer, id->GICD_ISPENDR,32); /*0x200~0x27c interrupt set-pending reg*/
-pointer = copy_wordsandclear(pointer, id->GICD_IPRIORITYR,32); /*0x400~0x7f8 Interrupt Priority Reg reg*/
-pointer = copy_wordsandclear(pointer, (volatile unsigned int *)id->GICD_ROUTER,32); /*0x6100~0x7ef8 Interrupt Priority Reg reg 1024 64bit*/
-pointer = copy_wordsandclear(pointer, &(id->GICD_CTLR),1); /*0x0~0x3, ditribrutor control reg*/
-pointer = copy_wordsandclear(pointer, (gic_distributor_address+0x40000+0x14),1); /* GICR_WAKER*/
-#endif
-
-#endif
-
- return retval;
-}
-
-void restore_gic_interface(u32 *pointer, unsigned gic_interface_address, int is_secure)
-{
-#if 1
- cpu_interface *ci = (cpu_interface *)gic_interface_address;
-
- ci->GICC_PMR = pointer[1];
- ci->GICC_BPR = pointer[2];
-
- if (is_secure)
- {
- ci->GICC_ABPR = pointer[3];
- }
-
- /* Restore control register last */
- ci->GICC_CTLR = pointer[0];
-#else
- restore_cpu_if(pointer);
-#endif
-
-}
-
-void restore_gic_distributor_private(u32 *pointer, unsigned gic_distributor_address, int is_secure)
-{
-#if 0 //zhangpei
- interrupt_distributor *id = (interrupt_distributor *)gic_distributor_address;
-
- /* We assume the distributor is disabled so we can write to its config registers */
-
- id->enable.set[0] = *pointer;
- ++pointer;
- copy_words(id->priority, pointer, 8);
- pointer += 8;
- copy_words(id->target, pointer, 8);
- pointer += 8;
- if (is_secure)
- {
- id->security[0] = *pointer;
- ++pointer;
- }
- /* Restore just the PPI configurations (SGIs are not configurable) */
- id->configuration[1] = *pointer;
- ++pointer;
- id->pending.set[0] = *pointer;
-#endif
-}
-
-void restore_gic_distributor_shared(u32 *pointer, unsigned gic_distributor_address, int is_secure)
-{
- interrupt_distributor *id = (interrupt_distributor *)gic_distributor_address;
-
- /* Make sure the distributor is disabled */
- // gic_distributor_set_enabled(false, gic_distributor_address);
-
-#if 0
- /* Calculate how many SPIs the GIC supports */
- num_spis = 32 * ((id->controller_type) & 0x1f);
-
- /* TODO: add nonsecure stuff */
-
- /* Restore rest of GIC configuration */
- if (num_spis)
- {
- copy_words(id->enable.set + 1, pointer, num_spis / 32);
- pointer += num_spis / 32;
- copy_words(id->priority + 8, pointer, num_spis / 4);
- pointer += num_spis / 4;
- copy_words(id->target + 8, pointer, num_spis / 4);
- pointer += num_spis / 4;
- copy_words(id->configuration + 2, pointer, num_spis / 16);
- pointer += num_spis / 16;
- if (is_secure)
- {
- copy_words(id->security + 1, pointer, num_spis / 32);
- pointer += num_spis / 32;
- }
- copy_words(id->pending.set + 1, pointer, num_spis / 32);
- pointer += num_spis / 32;
- }
-
- /* Restore control register - if the GIC was disabled during save, it will be restored as disabled. */
- id->control = *pointer;
-#else
-/*GICV3*/
- copy_words( id->GICD_ISENABLER ,pointer , 32); /*0x100~0x17C interrupt set-enable reg*/
- pointer+=32;
- copy_words(id->GICD_ICFGR , pointer , 64); /*0xc00~0xcfc interrupt config reg*/
- pointer+=64;
- copy_words(id->GICD_GRPMODR, pointer , 32); /*0xd00~d7c interrupt group modifer gre */
- pointer+=32;
- copy_words(id->GICD_IGROUPR, pointer , 32); /*0x80~0xfc interrupt group reg*/
- pointer+=32;
- copy_words(id->GICD_ISPENDR, pointer , 32); /*0x200~0x27c interrupt set-pending reg*/
- pointer+=32;
- copy_words((volatile unsigned int *)id->GICD_IPRIORITYR,pointer , 32); /*0x400~0x7f8 Interrupt Priority Reg reg*/
- pointer+=32;
- copy_words((volatile unsigned int *)id->GICD_ROUTER, pointer, 32); /*0x6100~0x7ef8 Interrupt Priority Reg reg 1024 64bit*/
- pointer+=32;
- copy_words(&id->GICD_CTLR, pointer , 1); /*0x0~0x3, ditribrutor control reg*/
- pointer+=1;
-// - zxp copy_words((volatile unsigned int *)(gic_distributor_address+0x40000+0x14),pointer,1); /* GICR_WAKER*/
-
-#endif
-return;
-}
-/* ÐÂÔö*/
-unsigned int gic_set_processorsleep(bool issleep)
-{
- if(issleep)
- {
- *(volatile unsigned int *)(GIC_REDIST_BASE+0x14) = 0x2;/**/
- while((*(volatile unsigned int *) (GIC_REDIST_BASE+0x14) &0x4) == 0); /*µÈ´ýGICÖжϴ¦ÀíÍê³É*/
- }
- else
- {
- *(volatile unsigned int *) (GIC_REDIST_BASE+0x14) = 0x0;/**/
- }
-
-
- return 0;
-}
-
-unsigned int gic_get_cur_pending(unsigned gic_interface_address)
-{
-
-#if 1
- cpu_interface *ci = (cpu_interface *)gic_interface_address;;
-
- return ci->GICC_HPPIR&0x3ff;
-#else
- unsigned int value = 0;
- // unsigned int value_addr = &value;
- // asm volatile(
- // "ldr r1,=value_addr\n\t"
- // "mrc p15, 0, r1, c12, c8, 2\n\t" /* ICC_HPPIR0 */
-
- // );
- return value;
-#endif
-}
-
-extern unsigned int gic_wake_enable[3];
-static u32 pm_gic_enable[3] =
-{
- 0xFFFFFFFF, 0xFFFFFFFF, 0x0FFFFFF,
-};
-void pm_save_gic_wake_enable(void)
-{
- interrupt_distributor *id = (interrupt_distributor *)GIC_DIST_BASE;
- pm_gic_enable[0]=id->GICD_ISENABLER[1];
- pm_gic_enable[1]=id->GICD_ISENABLER[2];
- pm_gic_enable[2]=id->GICD_ISENABLER[3];
-
- id->GICD_ICENABLER[1] = ~gic_wake_enable[0];
- id->GICD_ICENABLER[2] = ~gic_wake_enable[1];
- id->GICD_ICENABLER[3] = ~gic_wake_enable[2];
-}
-
-void pm_restore_gic_wake_enable(void)
-{
- interrupt_distributor *id = (interrupt_distributor *)GIC_DIST_BASE;
- id->GICD_ISENABLER[1] = pm_gic_enable[0];
- id->GICD_ISENABLER[2] = pm_gic_enable[1];
- id->GICD_ISENABLER[3]= pm_gic_enable[2];
-
-}
-
-void pm_mask_tick(void)
-{
-// ÐÞ¸Ä
-#if 1
- interrupt_distributor *id = (interrupt_distributor *)(GIC_DIST_BASE);
-
- //id->enable.clear[1] = 0x8000;
- id->GICD_ICENABLER[1] = 0x8000;
-#endif
-}
-
-void pm_unmask_tick(void)
-{
-// ÐÞ¸Ä
-#if 1
- interrupt_distributor *id = (interrupt_distributor *)(GIC_DIST_BASE);
-
- id->GICD_ISENABLER[1] |= 0x8000;
-#endif
-}
-
-
-/*=======================================================================
- *=======================================================================
- *======= [ZX-PM] V7 debug interface for power management ============================
- *=======================================================================
- *=======================================================================*/
-
-
-#define DIDR_VERSION_SHIFT 16
-#define DIDR_VERSION_MASK 0xF
-#define DIDR_VERSION_7_1 5
-#define DIDR_BP_SHIFT 24
-#define DIDR_BP_MASK 0xF
-#define DIDR_WP_SHIFT 28
-#define DIDR_WP_MASK 0xF
-#define CLAIMCLR_CLEAR_ALL 0xff
-
-#define DRAR_VALID_MASK 0x00000003
-#define DSAR_VALID_MASK 0x00000003
-#define DRAR_ADDRESS_MASK 0xFFFFF000
-#define DSAR_ADDRESS_MASK 0xFFFFF000
-#define OSLSR_OSLM_MASK 0x00000009
-#define OSLAR_UNLOCKED 0x00000000
-#define OSLAR_LOCKED 0xC5ACCE55
-#define LAR_UNLOCKED 0xC5ACCE55
-#define LAR_LOCKED 0x00000000
-#define OSDLR_UNLOCKED 0x00000000
-#define OSDLR_LOCKED 0x00000001
-
-typedef volatile struct
-{ /* Registers Save? */
- u32 const didr; /* 0 Read only */
- u32 dscr_i; /* 1 ignore - use dscr_e instead */
- u32 const dummy1[3]; /* 2-4 ignore */
- u32 dtrrx_dtrtx_i; /* 5 ignore */
- u32 wfar; /* 6 ignore - transient information */
- u32 vcr; /* 7 Save */
- u32 const dummy2; /* 8 ignore */
- u32 ecr; /* 9 ignore */
- u32 dsccr; /* 10 ignore */
- u32 dsmcr; /* 11 ignore */
- u32 const dummy3[20]; /* 12-31 ignore */
- u32 dtrrx_e; /* 32 ignore */
- u32 itr_pcsr; /* 33 ignore */
- u32 dscr_e; /* 34 Save */
- u32 dtrtx_e; /* 35 ignore */
- u32 drcr; /* 36 ignore */
- u32 eacr; /* 37 Save - V7.1 only */
- u32 const dummy4[2]; /* 38-39 ignore */
- u32 pcsr; /* 40 ignore */
- u32 cidsr; /* 41 ignore */
- u32 vidsr; /* 42 ignore */
- u32 const dummy5[21]; /* 43-63 ignore */
- u32 bvr[16]; /* 64-79 Save */
- u32 bcr[16]; /* 80-95 Save */
- u32 wvr[16]; /* 96-111 Save */
- u32 wcr[16]; /* 112-127 Save */
- u32 const dummy6[16]; /* 128-143 ignore */
- u32 bxvr[16]; /* 144-159 Save if have Virtualization extensions */
- u32 const dummy7[32]; /* 160-191 ignore */
- u32 oslar; /* 192 If oslsr[0] is 1, unlock before save/restore */
- u32 const oslsr; /* 193 ignore */
- u32 ossrr; /* 194 ignore */
- u32 const dummy8; /* 195 ignore */
- u32 prcr; /* 196 ignore */
- u32 prsr; /* 197 clear SPD on restore */
- u32 const dummy9[762]; /* 198-959 ignore */
- u32 itctrl; /* 960 ignore */
- u32 const dummy10[39]; /* 961-999 ignore */
- u32 claimset; /* 1000 Restore claim bits to here */
- u32 claimclr; /* 1001 Save claim bits from here */
- u32 const dummy11[2]; /* 1002-1003 ignore */
- u32 lar; /* 1004 Unlock before restore */
- u32 const lsr; /* 1005 ignore */
- u32 const authstatus; /* 1006 Read only */
- u32 const dummy12; /* 1007 ignore */
- u32 const devid2; /* 1008 Read only */
- u32 const devid1; /* 1009 Read only */
- u32 const devid; /* 1010 Read only */
- u32 const devtype; /* 1011 Read only */
- u32 const pid[8]; /* 1012-1019 Read only */
- u32 const cid[4]; /* 1020-1023 Read only */
-} debug_registers_t;
-
-typedef struct
-{
- u32 vcr;
- u32 dscr_e;
- u32 eacr;
- u32 bvr[16];
- u32 bcr[16];
- u32 wvr[16];
- u32 wcr[16];
- u32 bxvr[16];
- u32 claim;
-} debug_context_t; /* total size 86 * 4 = 344 bytes */
-
-debug_registers_t *read_debug_address(void)
-{
- unsigned drar, dsar;
-
- drar = read_drar();
- dsar = read_dsar();
-
- if (!(drar & DRAR_VALID_MASK)
- || !(dsar & DSAR_VALID_MASK))
- {
- return 0; /* No memory-mapped debug on this processor */
- }
-
- return (debug_registers_t *)((drar & DRAR_ADDRESS_MASK)
- + (dsar & DSAR_ADDRESS_MASK));
-}
-
-/*
- * We assume that before save (and after restore):
- * - OSLAR is NOT locked, or the debugger would not work properly
- * - LAR is locked, because the ARM ARM says it must be
- * - OSDLR is NOT locked, or the debugger would not work properly
- */
-
-void save_v7_debug(u32 *context)
-{
- debug_registers_t *dbg = (void*)read_debug_address();
- debug_context_t *ctx = (void*)context;
- unsigned v71, num_bps, num_wps, i;
- u32 didr;
-
- if (!dbg)
- {
- return;
- }
-
- didr = dbg->didr;
- /*
- * Work out what version of debug we have
- */
- v71 = (((didr >> DIDR_VERSION_SHIFT) & DIDR_VERSION_MASK) == DIDR_VERSION_7_1);
-
- /*
- * Save all context to memory
- */
- ctx->vcr = dbg->vcr;
- ctx->dscr_e = dbg->dscr_e;
- ctx->claim = dbg->claimclr;
-
- if (v71)
- {
- ctx->eacr = dbg->eacr;
- }
-
- num_bps = 1 + ((didr >> DIDR_BP_SHIFT) & DIDR_BP_MASK);
- for (i=0; i<num_bps; ++i)
- {
- ctx->bvr[i] = dbg->bvr[i];
- ctx->bcr[i] = dbg->bcr[i];
-#ifdef VIRTUALIZATION
- ctx->bxvr[i] = dbg->bxvr[i]; /* TODO: don't save the ones that don't exist */
-#endif
- }
-
- num_wps = 1 + ((didr >> DIDR_WP_SHIFT) & DIDR_WP_MASK);
- for (i=0; i<num_wps; ++i)
- {
- ctx->wvr[i] = dbg->wvr[i];
- ctx->wcr[i] = dbg->wcr[i];
- }
-
- /*
- * If Debug V7.1, we must set osdlr (by cp14 interface) before power down.
- * Once we have done this, debug becomes inaccessible.
- */
- if (v71)
- {
- write_osdlr(OSDLR_LOCKED);
- }
-}
-
-void restore_v7_debug(u32 *context)
-{
- debug_registers_t *dbg = (void*)read_debug_address();
- debug_context_t *ctx = (void*)context;
- unsigned v71, num_bps, num_wps, i;
- u32 didr;
-
- if (!dbg)
- {
- return;
- }
-
- didr = dbg->didr;
- /*
- * Work out what version of debug we have
- */
- v71 = (((didr >> DIDR_VERSION_SHIFT) & DIDR_VERSION_MASK) == DIDR_VERSION_7_1);
-
- /* Enable write access to registers */
- dbg->lar = LAR_UNLOCKED;
- /*
- * If Debug V7.1, we must unset osdlr (by cp14 interface) before restoring.
- * (If the CPU has not actually power-cycled, osdlr may not be reset).
- */
- if (v71)
- {
- write_osdlr(OSDLR_UNLOCKED);
- }
-
- /*
- * Restore all context from memory
- */
- dbg->vcr = ctx->vcr;
- dbg->claimclr = CLAIMCLR_CLEAR_ALL;
- dbg->claimset = ctx->claim;
-
- if (v71)
- {
- dbg->eacr = ctx->eacr;
- }
-
- num_bps = 1 + ((didr >> DIDR_BP_SHIFT) & DIDR_BP_MASK);
- for (i=0; i<num_bps; ++i)
- {
- dbg->bvr[i] = ctx->bvr[i];
- dbg->bcr[i] = ctx->bcr[i];
-#ifdef VIRTUALIZATION
- dbg->bxvr[i] = ctx->bxvr[i]; /* TODO: don't restore the ones that don't exist */
-#endif
- }
-
- num_wps = 1 + ((didr >> DIDR_WP_SHIFT) & DIDR_WP_MASK);
- for (i=0; i<num_wps; ++i)
- {
- dbg->wvr[i] = ctx->wvr[i];
- dbg->wcr[i] = ctx->wcr[i];
- }
-
- /* Clear PRSR.SPD by reading PRSR */
- if (!v71)
- {
- (dbg->prsr);
- }
-
- /* Re-enable debug */
- dbg->dscr_e = ctx->dscr_e;
-
- /* Disable write access to registers */
- dbg->lar = LAR_LOCKED;
-}
-
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-context.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-context.c
deleted file mode 100644
index 9ad479f..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-context.c
+++ /dev/null
@@ -1,622 +0,0 @@
-/*
- * ZTE cpu context save&restore driver
- *
- * Copyright (C) 2013 ZTE Ltd.
- * by zxp
- *
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/suspend.h>
-
-#include <asm/memory.h>
-
-#include "zx-pm.h"
-
-
-struct zx_pm_main_table zx_pm_main_table;
-unsigned pm_device_memory [PM_MEMORY_SIZE/4];
-
-extern volatile int sleep_ret_flag[];
-
-/**
- * This is where the reset vector jumps to.
- *
- */
-static unsigned get_device_memory(unsigned size);
-/*********************************************************************
- * FUNCTION DEFINATIONS
- ********************************************************************/
-/**
- * zx_pm_context_init - initial context for cpu suspend and resume.
- *
- * initial the struct variable for context.
- */
-int zx_pm_context_init(void)
-{
- int i;
- struct zx_cluster_context* temp_cluster_context;
- struct zx_cpu_context* temp_cpu_context;
-
- pr_info("[SLP] Power/PM_CONTEXT_INIT \n");
-
- zx_set_wakeup_address(SYSTEM_WAKEUP_ADDR);
-
- zx_pm_main_table.num_cpus = MAX_CPU_NUM;
-
-#ifdef CONFIG_ARCH_ZX297520V2
- zx_pm_main_table.scu_address = (u32)SCU_ADDRESS;
- zx_pm_main_table.ic_dist_address = (u32)SCU_ADDRESS + IC_DISTRIBUTOR_OFFSET;
- zx_pm_main_table.ic_interface_address = (u32)SCU_ADDRESS + IC_INTERFACE_OFFSET;
- zx_pm_main_table.l2_address = (u32)L2_CONTROLLER_ADDRESS;
- zx_pm_main_table.crm_address = (u32)A9_CRM_ADDRESS;
-
- zx_pm_main_table.scu_address_p = (u32)SCU_ADDRESS_P;
- zx_pm_main_table.l2_address_p = (u32)L2_CONTROLLER_ADDRESS_P;
- zx_pm_main_table.crm_address_p = (u32)A9_CRM_ADDRESS_P;
-#else
- zx_pm_main_table.scu_address = (u32)0;
- zx_pm_main_table.ic_dist_address = (u32)(GIC_DIST_BASE);
- zx_pm_main_table.ic_interface_address = (u32)(ZX_GICC_BASE);
- zx_pm_main_table.l2_address = (u32)0;
- zx_pm_main_table.crm_address = (u32)AP_CRM_BASE;
-
- zx_pm_main_table.scu_address_p = (u32)0;
- zx_pm_main_table.l2_address_p = (u32)0;
- zx_pm_main_table.crm_address_p = (u32)(ZX29_AP_PERIPHERAL_PHYS+0x20000);
-#endif
- /*cluster info*/
- temp_cluster_context = (void *)get_device_memory(sizeof(struct zx_cluster_context));
- temp_cluster_context->flags = 0;
- temp_cluster_context->saved_items = 0;
- temp_cluster_context->gic_dist_shared_data = (void *)get_device_memory(GIC_DIST_SHARED_DATA_SIZE);
- temp_cluster_context->l2_data = (void *)get_device_memory(L2_DATA_SIZE);
- temp_cluster_context->scu_data = (void *)get_device_memory(SCU_DATA_SIZE);
- temp_cluster_context->global_timer_data = (void *)get_device_memory(GLOBAL_TIMER_DATA_SIZE);
- temp_cluster_context->crm_data = (void *)get_device_memory(CRM_DATA_SIZE);
- temp_cluster_context->power_state = CPU_POWER_MODE_RUN;
-
- zx_pm_main_table.cluster_context = temp_cluster_context;
-
- /*cpu info*/
- for(i=0;i<zx_pm_main_table.num_cpus;i++)
- {
- temp_cpu_context = (void *)get_device_memory(sizeof(struct zx_cpu_context));
- temp_cpu_context->flags = 0;
- temp_cpu_context->saved_items = 0;
- temp_cpu_context->control_data = (void *)get_device_memory(CONTROL_DATA_SIZE);
- temp_cpu_context->pmu_data = (void *)get_device_memory(PMU_DATA_SIZE);
- temp_cpu_context->timer_data = (void *)get_device_memory(TIMER_DATA_SIZE);
- temp_cpu_context->vfp_data = (void *)get_device_memory(VFP_DATA_SIZE);
- temp_cpu_context->gic_interface_data = (void *)get_device_memory(GIC_INTERFACE_DATA_SIZE);
- temp_cpu_context->gic_dist_private_data = (void *)get_device_memory(GIC_DIST_PRIVATE_DATA_SIZE);
- temp_cpu_context->banked_registers = (void *)get_device_memory(BANKED_REGISTERS_SIZE);
- temp_cpu_context->cp15_data = (void *)get_device_memory(CP15_DATA_SIZE);
- temp_cpu_context->debug_data = (void *)get_device_memory(DEBUG_DATA_SIZE);
- temp_cpu_context->mmu_data = (void *)get_device_memory(MMU_DATA_SIZE);
- temp_cpu_context->other_data = (void *)get_device_memory(OTHER_DATA_SIZE);
- temp_cpu_context->power_state = CPU_POWER_MODE_RUN;
- temp_cpu_context->sleep_type = CPU_SLEEP_TYPE_NULL;
-
- zx_pm_main_table.cpu_context[i] = temp_cpu_context;
- }
-
- pr_info("[SLP] Power/PM_CONTEXT_INIT END\n");
-
- return 0;
-}
-
-/**
- * sleep_type - idle/suspend.
- *
- * set the context flag will be saved according to sleep type.
- *
- */
-int zx_set_context_level (cpu_sleep_type_t sleep_type)
-{
- unsigned cpu_id;
-
- cpu_id = read_cpuid();
- zx_pm_main_table.cur_cpu = cpu_id;
-
- if(CPU_SLEEP_TYPE_LP1 == sleep_type) //suspend
- {
- zx_pm_main_table.cluster_context->flags = LP1_MG_SAVE_FLAG;
- zx_pm_main_table.cpu_context[cpu_id]->flags = LP1_CPU_SAVE_FLAG;
-
- zx_pm_main_table.cpu_context[cpu_id]->power_state = CPU_POWER_MODE_SHUTDOWN;
- zx_pm_main_table.cluster_context->power_state = CPU_POWER_MODE_SHUTDOWN;
- }
- else if(CPU_SLEEP_TYPE_IDLE_LP2 == sleep_type)//deep idle
- {
- /*if(0 == cpu_id)*/
- {
- zx_pm_main_table.cluster_context->flags = LP2_MG_SAVE_FLAG;
- zx_pm_main_table.cpu_context[cpu_id]->flags = LP2_CPU0_SAVE_FLAG;
-
- zx_pm_main_table.cpu_context[cpu_id]->power_state = CPU_POWER_MODE_DORMANT;
- zx_pm_main_table.cluster_context->power_state = CPU_POWER_MODE_DORMANT;
- }
- /*else
- {
- zx_pm_main_table.cluster_context->flags = MG_SAVE_FLAG_NULL;
- zx_pm_main_table.cpu_context[cpu_id]->flags = LP2_CPUX_SAVE_FLAG;
-
- zx_pm_main_table.cpu_context[cpu_id]->power_state = CPU_POWER_MODE_DORMANT;
- }*/
- }
- else if(CPU_SLEEP_TYPE_LP3 == sleep_type)//wfi only
- {
- zx_pm_main_table.cluster_context->flags = MG_SAVE_FLAG_NULL;
- zx_pm_main_table.cpu_context[cpu_id]->flags = MG_SAVE_FLAG_NULL;
-
- zx_pm_main_table.cpu_context[cpu_id]->power_state = CPU_POWER_MODE_STANDBY;
- zx_pm_main_table.cluster_context->power_state = CPU_POWER_MODE_STANDBY;
- }
-
- zx_pm_main_table.cpu_context[cpu_id]->sleep_type = sleep_type;
-
- return 0;
-}
-
-/**
- * This function saves all the context that will be lost
- * when a CPU and cluster enter a low power state.
- *
- */
-void zx_pm_save_context(void)
-{
- struct zx_cpu_context *context;
- struct zx_cluster_context *cluster_context;
- int is_secure = true;
- int ret=0;
-
- context = zx_pm_main_table.cpu_context[zx_pm_main_table.cur_cpu];
- cluster_context = zx_pm_main_table.cluster_context;
-#ifdef CONFIG_ARCH_ZX297520V2 /* v3 ÎÞ ÄÚ²¿timer*/
- if(context->flags&CPU_SAVE_TIMERS)
- {
- save_a9_timers(context->timer_data,
- zx_pm_main_table.scu_address+PRIVATE_TWD_OFFSET);
- context->saved_items |= CPU_SAVE_TIMERS;
- }
-#endif
- if(context->flags&CPU_SAVE_PMU)
- {
- save_performance_monitors(context->pmu_data);
- context->saved_items |= CPU_SAVE_PMU;
- }
-
- if(context->flags&CPU_SAVE_VFP)
- {
- save_vfp(context->vfp_data);
- context->saved_items |= CPU_SAVE_VFP;
- }
-
- /*only for smp */
- if(zx_pm_main_table.ic_interface_address)
- {
-#ifdef CONFIG_ARCH_ZX297520V2
-#else
- gic_set_processorsleep(1);
-#endif
- save_gic_interface(context->gic_interface_data,
- zx_pm_main_table.ic_interface_address,
- is_secure);
-#ifdef CONFIG_ARCH_ZX297520V2
- ret = save_gic_distributor_private(context->gic_dist_private_data,
- zx_pm_main_table.ic_dist_address,
- is_secure);
-#endif
- }
-
- //if(ret == -1)
- //{
- // BUG();
- //while(1);
- //}
-
- if(context->flags&CPU_SAVE_DEBUG)
- {
- save_v7_debug(context->debug_data);
- context->saved_items |= CPU_SAVE_DEBUG;
- }
-
-
- save_banked_registers(context->banked_registers);
- save_cp15(context->cp15_data);
-
- if (context->flags&CPU_SAVE_OTHER)
- {
-#ifdef CONFIG_ARCH_ZX297520V2
- save_a9_other(context->other_data, is_secure);
-#else
- #if 0
- save_a53_other(context->other_data, is_secure);
- #endif
-#endif
- context->saved_items |= CPU_SAVE_OTHER;
- }
-
- if (cluster_context->flags&CPU_SAVE_GLOBAL_TIMER)
- {
-
-
-#ifdef CONFIG_ARCH_ZX297520V2
- save_a9_global_timer(cluster_context->global_timer_data,
- zx_pm_main_table.scu_address+GLOBAL_TIMER_OFFSET);
-#else
- #if 0
- save_a53_sys_timer(cluster_context->global_timer_data,
- (0x01401000)); /*AP Timer0*/
- #endif
-#endif
- cluster_context->saved_items |= CPU_SAVE_GLOBAL_TIMER;
- }
-
- if(cluster_context->flags&CPU_SAVE_GIC)
- {
- ret = save_gic_distributor_shared(cluster_context->gic_dist_shared_data,
- zx_pm_main_table.ic_dist_address,
- is_secure);
- cluster_context->saved_items |= CPU_SAVE_GIC;
- }
-/*
- if(ret == -1)
- {
- while(1);
- }
-*/
-
- save_control_registers(context->control_data, is_secure);
- save_mmu(context->mmu_data);
-
- if (cluster_context->flags&CPU_SAVE_SCU)
- {
-#ifdef CONFIG_ARCH_ZX297520V2
- save_a9_scu(cluster_context->scu_data, zx_pm_main_table.scu_address);
-#endif
- cluster_context->saved_items |= CPU_SAVE_SCU;
- }
-
- if (cluster_context->flags&CPU_SAVE_L2)
- {
-#ifdef CONFIG_ARCH_ZX297520V2
- save_pl310(cluster_context->l2_data, zx_pm_main_table.l2_address);
-#endif
- cluster_context->saved_items |= CPU_SAVE_L2;
- }
-
- if (cluster_context->flags&CPU_SAVE_CRM)
- {
- cluster_context->saved_items |= CPU_SAVE_CRM;
- save_crm(cluster_context->crm_data, zx_pm_main_table.crm_address);
- }
-
- /*saved completely*/
- sleep_ret_flag[zx_pm_main_table.cur_cpu] = 0;
-}
-
-/**
- * This function restores all the context that was lost
- * when a CPU and cluster entered a low power state. It is called shortly after
- * reset, with the MMU and data cache off.
- *
- * note:before MMU is enable, all address should convert to PA
- */
-void zx_pm_restore_context(void)
-{
- unsigned cpu_id;
- struct zx_cpu_context *context;
- struct zx_cluster_context *cluster_context;
- int is_secure = true;
-
- cpu_id = read_cpuid();
-
- context = zx_pm_main_table.cpu_context[cpu_id];
- cluster_context = zx_pm_main_table.cluster_context;
-
- if (cluster_context->saved_items & CPU_SAVE_CRM)
- {
- restore_crm(cluster_context->crm_data, zx_pm_main_table.crm_address);
- cluster_context->saved_items &= ~CPU_SAVE_CRM;
- }
-
- if (cluster_context->saved_items & CPU_SAVE_SCU)
- {
- #ifdef CONFIG_ARCH_ZX297520V2
- restore_a9_scu(cluster_context->scu_data, zx_pm_main_table.scu_address);
- #endif
- cluster_context->saved_items &= ~CPU_SAVE_SCU;
- }
-
- if (cluster_context->saved_items & CPU_SAVE_L2)
- {
- #ifdef CONFIG_ARCH_ZX297520V2
- restore_pl310(cluster_context->l2_data,
- zx_pm_main_table.l2_address,
- cluster_context->power_state == CPU_POWER_MODE_DORMANT);
- #endif
- cluster_context->saved_items &= ~CPU_SAVE_L2;
- }
-
- /* Next get the MMU back on */
- restore_mmu(context->mmu_data);
- restore_control_registers(context->control_data, is_secure);
- /*
- * MMU and L1 and L2 caches are on, we may now read/write any data.
- * Now we need to restore the rest of this CPU's context
- */
-
- /* Restore shared items if necessary */
- if (cluster_context->saved_items & CPU_SAVE_GIC)
- {
- gic_distributor_set_enabled(false, zx_pm_main_table.ic_dist_address);
- restore_gic_distributor_shared(cluster_context->gic_dist_shared_data, zx_pm_main_table.ic_dist_address, is_secure);
- gic_distributor_set_enabled(true, zx_pm_main_table.ic_dist_address);
-#ifdef CONFIG_ARCH_ZX297520V2
-
- restore_gic_distributor_private(context->gic_dist_private_data, zx_pm_main_table.ic_dist_address, is_secure);
-#endif
- restore_gic_interface(context->gic_interface_data, zx_pm_main_table.ic_interface_address, is_secure);
- cluster_context->saved_items &= ~CPU_SAVE_GIC;
- }
- if (cluster_context->saved_items & CPU_SAVE_GLOBAL_TIMER)
- {
-#ifdef CONFIG_ARCH_ZX297520V2
- restore_a9_global_timer(cluster_context->global_timer_data,
- zx_pm_main_table.scu_address+GLOBAL_TIMER_OFFSET);
-#else
- #if 0
- restore_a53_sys_timer(cluster_context->global_timer_data,
- (0x01401000)); /*AP timer 0*/
- #endif
-#endif
- cluster_context->saved_items &= ~CPU_SAVE_GLOBAL_TIMER;
- }
-
-
- /* Get the debug registers restored, so we can debug most of the APPF code sensibly! */
- if (context->saved_items&CPU_SAVE_DEBUG)
- {
- restore_v7_debug(context->debug_data);
- context->saved_items &= ~CPU_SAVE_DEBUG;
- }
-
- if (context->saved_items&CPU_SAVE_OTHER)
- {
-#ifdef CONFIG_ARCH_ZX297520V2
- restore_a9_other(context->other_data, is_secure);
-#else
- #if 0
- restore_a53_other(context->other_data, is_secure);
- #endif
-#endif
- context->saved_items &= ~CPU_SAVE_OTHER;
- }
-
- restore_cp15(context->cp15_data);
- restore_banked_registers(context->banked_registers);
-
- if (context->saved_items&CPU_SAVE_VFP)
- {
- restore_vfp(context->vfp_data);
- context->saved_items &= ~CPU_SAVE_VFP;
- }
-
- if (context->saved_items&CPU_SAVE_TIMERS)
- {
-#ifdef CONFIG_ARCH_ZX297520V2
- restore_a9_timers(context->timer_data,
- zx_pm_main_table.scu_address+PRIVATE_TWD_OFFSET);
-#endif
- context->saved_items &= ~CPU_SAVE_TIMERS;
- }
-
- if (context->saved_items&CPU_SAVE_PMU)
- {
- restore_performance_monitors(context->pmu_data);
- context->saved_items &= ~CPU_SAVE_PMU;
- }
-
- cluster_context->power_state = CPU_POWER_MODE_RUN;
- context->power_state = CPU_POWER_MODE_RUN;
-#ifdef CONFIG_ARCH_ZX297520V2
-#else
- gic_set_processorsleep(0);
-#endif
- /*restore completely*/
- sleep_ret_flag[cpu_id] = 1;
-}
-/**
- * This function restores the context that lost when cpu not power down correctly.
- *
- */
-void zx_pm_restore_abort_context(void)
-{
- unsigned cpu_id;
- struct zx_cpu_context *context;
- struct zx_cluster_context *cluster_context;
-
- cpu_id = read_cpuid();
- context = zx_pm_main_table.cpu_context[cpu_id];
- cluster_context = zx_pm_main_table.cluster_context;
-
- if (cluster_context->saved_items & CPU_SAVE_CRM)
- {
- restore_crm(cluster_context->crm_data, zx_pm_main_table.crm_address);
- cluster_context->saved_items &= ~CPU_SAVE_CRM;
- }
-
- if (cluster_context->saved_items & CPU_SAVE_SCU)
- {
- cluster_context->saved_items &= ~CPU_SAVE_SCU;
- }
-
- if (cluster_context->saved_items & CPU_SAVE_L2)
- {
- cluster_context->saved_items &= ~CPU_SAVE_L2;
- }
-
- /*
- * MMU and L1 and L2 caches are on, we may now read/write any data.
- * Now we need to restore the rest of this CPU's context
- */
-
- /* Restore shared items if necessary */
- if (cluster_context->saved_items & CPU_SAVE_GIC)
- {
- cluster_context->saved_items &= ~CPU_SAVE_GIC;
- }
-
- if (cluster_context->saved_items & CPU_SAVE_GLOBAL_TIMER)
- {
-#ifdef CONFIG_ARCH_ZX297520V2
- restore_a9_global_timer(cluster_context->global_timer_data,
- zx_pm_main_table.scu_address+GLOBAL_TIMER_OFFSET);
-#else
- #if 0
- restore_a53_sys_timer(cluster_context->global_timer_data,
- (0x01401000));
- #endif
-#endif
- cluster_context->saved_items &= ~CPU_SAVE_GLOBAL_TIMER;
- }
-
-
- /* Get the debug registers restored, so we can debug most of the APPF code sensibly! */
- if (context->saved_items&CPU_SAVE_DEBUG)
- {
- context->saved_items &= ~CPU_SAVE_DEBUG;
- }
-
- if (context->saved_items&CPU_SAVE_OTHER)
- {
- context->saved_items &= ~CPU_SAVE_OTHER;
- }
-
- if (context->saved_items&CPU_SAVE_VFP)
- {
- restore_vfp(context->vfp_data);
- context->saved_items &= ~CPU_SAVE_VFP;
- }
-
- if (context->saved_items&CPU_SAVE_TIMERS)
- {
-#ifdef CONFIG_ARCH_ZX297520V2
- restore_a9_timers(context->timer_data,
- zx_pm_main_table.scu_address+PRIVATE_TWD_OFFSET);
-#endif
- context->saved_items &= ~CPU_SAVE_TIMERS;
- }
-
- if (context->saved_items&CPU_SAVE_PMU)
- {
- restore_performance_monitors(context->pmu_data);
- context->saved_items &= ~CPU_SAVE_PMU;
- }
-
- cluster_context->power_state = CPU_POWER_MODE_RUN;
- context->power_state = CPU_POWER_MODE_RUN;
-#ifdef CONFIG_ARCH_ZX297520V2
-#else
- gic_set_processorsleep(0);
-#endif
- /*restore completely*/
- sleep_ret_flag[cpu_id] = 1;
-}
-
-
-/**
- * Simple Device memory allocator function.
- * Returns start address of allocated region
- * Allocates region of size bytes, size will be rounded up to multiple of sizeof(long long)
- * Memory is zero-initialized.
- *
- * This function is from ARM.
- */
-static long long *device_memory = (void *)pm_device_memory;
-static unsigned get_device_memory(unsigned size)
-{
- static unsigned watermark = 0;
- static unsigned total_size = 0;
- unsigned ret, chunks_required;
-
- ret = watermark;
- chunks_required = (size + sizeof(long long) - 1) / sizeof(long long);
- watermark += chunks_required;
-
- if (watermark >= PM_MEMORY_SIZE / sizeof(long long))
- {
- pr_info("[SLP] error alloc size: %d Bytes \n", size);
- BUG();
- // while(1);
- return 0; /* No output possible, so loop */
- }
-
- total_size += size;
- pr_info("[SLP] alloc size: %d Bytes , total size %d Bytes\n", size, total_size);
-
-
- return (unsigned) &device_memory[ret];
-}
-
-/**
- * This function tell the wakeup code address to CPU_M0 for cpu waked up from deep sleep(shutdown or dormant),
- * the wakeup code will exist in iram (address 0), but iram will power down when AP sub-system or
- * whole chip power down, so A9 tell CPU_M0 the address, before A9 reset, CPU_M0 will copy the code
- * from this address to the iram.
- *
- * This code should call after zx_pm_context_init.
- */
-void zx_set_wakeup_address(u32 wakeup_addr)
-{
- wakeup_ram_area *wakeup_ram;
-
- pr_info("[SLP] Power/WAKEUP_ADDRESS \n");
-
-#ifdef CONFIG_ARCH_ZX297520V2
- zx_pm_main_table.wakeup_vaddr = (u32)ioremap_mem(wakeup_addr, WAKEUP_RAM_SIZE);
-#else
- zx_pm_main_table.wakeup_vaddr = (u32)__arm_ioremap_exec(wakeup_addr, WAKEUP_RAM_SIZE,0);
-#endif
- BUG_ON((void *)zx_pm_main_table.wakeup_vaddr == NULL);
- zx_pm_main_table.wakeup_ram_size = WAKEUP_RAM_SIZE;
- memset((void *)zx_pm_main_table.wakeup_vaddr, 0, zx_pm_main_table.wakeup_ram_size);
-
- wakeup_ram = (wakeup_ram_area *)zx_pm_main_table.wakeup_vaddr;
-
- /*copy the ddr reset code to iram*/
- memcpy(wakeup_ram->wakeup_code, (void *)cpu_wake_up, WAKEUP_CODE_LENGTH);
- memcpy(wakeup_ram->sleep_code, (void *)do_sleep_cpu, SLEEP_CODE_LENGTH);
- memcpy(wakeup_ram->ddr_dfs_code, (void *)waiting_ddr_dfs, DDR_DFS_CODE_LENGTH);
-
- wakeup_ram->reset_handler_vaddr = __pa((u32)((void *)cpu_reset_handler));
-}
-
-/**
- * get current sleep_type helper function.
- *
- * This code only used pm internel.
- */
-cpu_sleep_type_t pm_get_sleep_type(void)
-{
- return zx_pm_main_table.cpu_context[zx_pm_main_table.cur_cpu]->sleep_type;
-}
-
-/**
- * init lp for scu/l2.
- *
- * This code only used pm internel.
- */
-void pm_init_l2_and_scu(void)
-{
-#ifdef CONFIG_ARCH_ZX297520V2
- init_lp_of_scu(zx_pm_main_table.scu_address);
- init_lp_of_l2(zx_pm_main_table.l2_address);
-#endif
-}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-context.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-context.h
deleted file mode 100644
index 8df5056..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-context.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * zx-pm-context.h - cpu sleep context save&restore interface for power management.
- *
- * Written by zxp.
- *
- */
-
-#ifndef _ZX_PM_CONTEXT_H
-#define _ZX_PM_CONTEXT_H
-
-#define CPU_SAVE_PMU (1U << 0)
-#define CPU_SAVE_TIMERS (1U << 1)
-#define CPU_SAVE_VFP (1U << 2)
-#define CPU_SAVE_DEBUG (1U << 3)
-#define CPU_SAVE_GIC (1U << 4)
-#define CPU_SAVE_OTHER (1U << 5)
-
-#define CPU_SAVE_GLOBAL_TIMER (1U << 16)
-#define CPU_SAVE_L2 (1U << 17)
-#define CPU_SAVE_L2_RAM (1U << 18)
-#define CPU_SAVE_SCU (1U << 19)
-#define CPU_SAVE_CRM (1U << 20)
-
-#define SCU_ADDRESS (ZX_A9_PERIPHERAL_BASE)
-#define SCU_ADDRESS_P (ZX_A9_PERIPHERAL_PHYS)
-#define IC_INTERFACE_OFFSET (0x100)
-#define GLOBAL_TIMER_OFFSET (0x200)
-#define PRIVATE_TWD_OFFSET (0x600)
-#define IC_DISTRIBUTOR_OFFSET (0x1000)
-#define L2_CONTROLLER_ADDRESS (ZX_L2CACHE_CONFIG_BASE)
-#define L2_CONTROLLER_ADDRESS_P (ZX_L2CACHE_CONFIG_PHYS)
-#define A9_CRM_ADDRESS (A9_CRM_BASE)
-#define A9_CRM_ADDRESS_P (A9_CRM_PHYS)
-
-#define GIC_DIST_SET_PENDING (SCU_ADDRESS+IC_DISTRIBUTOR_OFFSET+0x200)
-#define GIC_CPU_HIGHPRI_PENDING (SCU_ADDRESS+IC_INTERFACE_OFFSET+0x18)
-#ifdef CONFIG_ARCH_ZX297520V2
-#define LP1_MG_SAVE_FLAG (CPU_SAVE_GIC|/*CPU_SAVE_GLOBAL_TIMER|*/CPU_SAVE_L2|CPU_SAVE_L2_RAM|CPU_SAVE_SCU|CPU_SAVE_CRM)
-#define LP1_CPU_SAVE_FLAG (CPU_SAVE_PMU|CPU_SAVE_TIMERS|/*CPU_SAVE_VFP|*//*CPU_SAVE_DEBUG|*/CPU_SAVE_GIC|CPU_SAVE_OTHER)
-#else
-#define LP1_MG_SAVE_FLAG (CPU_SAVE_GIC|/*CPU_SAVE_GLOBAL_TIMER|*//*CPU_SAVE_L2|CPU_SAVE_L2_RAM|CPU_SAVE_SCU|*/CPU_SAVE_CRM)
-#define LP1_CPU_SAVE_FLAG (CPU_SAVE_PMU|/*CPU_SAVE_TIMERS|*//*CPU_SAVE_VFP|*//*CPU_SAVE_DEBUG|*/CPU_SAVE_GIC|CPU_SAVE_OTHER)
-#endif
-
-#define LP2_MG_SAVE_FLAG (CPU_SAVE_GIC|/*CPU_SAVE_GLOBAL_TIMER|*/CPU_SAVE_L2|CPU_SAVE_L2_RAM|CPU_SAVE_SCU|CPU_SAVE_CRM)
-#define LP2_CPU0_SAVE_FLAG (CPU_SAVE_PMU|/*CPU_SAVE_TIMERS|CPU_SAVE_VFP|*//*CPU_SAVE_DEBUG|*/CPU_SAVE_GIC|CPU_SAVE_OTHER)
-#define LP2_CPUX_SAVE_FLAG (CPU_SAVE_PMU|/*CPU_SAVE_TIMERS|CPU_SAVE_VFP|*//*CPU_SAVE_DEBUG|*/CPU_SAVE_GIC|CPU_SAVE_OTHER)
-#define MG_SAVE_FLAG_NULL (0)
-
-/* Maximum size of each item of context, in bytes */
-#define PMU_DATA_SIZE (128)
-#define TIMER_DATA_SIZE (128)
-#define VFP_DATA_SIZE (288)
-#define GIC_INTERFACE_DATA_SIZE (64)
-#define GIC_DIST_PRIVATE_DATA_SIZE (96)
-#define BANKED_REGISTERS_SIZE (128)
-#define CP15_DATA_SIZE (64)
-#define DEBUG_DATA_SIZE (352)
-#define MMU_DATA_SIZE (64)
-#define OTHER_DATA_SIZE (32)
-#define CONTROL_DATA_SIZE (64)
-
-#define GIC_DIST_SHARED_DATA_SIZE (2592)
-#define SCU_DATA_SIZE (32)
-#define L2_DATA_SIZE (96)
-#define GLOBAL_TIMER_DATA_SIZE (128)
-#ifdef CONFIG_ARCH_ZX297520V2
-#define CRM_DATA_SIZE (136)
-#else
-#define CRM_DATA_SIZE (64)//(136)
-#endif
-#define PM_MEMORY_SIZE (5120)
-#define MAX_CPU_NUM (1)
-#define WAKEUP_RAM_SIZE (SZ_1K)
-
-struct zx_cluster_context
-{
- u32 flags; /*before save context, set this flag*/
- u32 saved_items; /*after save a context, set a flag for restore*/
- u32 *gic_dist_shared_data;
- u32 *l2_data;
- u32 *scu_data;
- u32 *global_timer_data;
- u32 *crm_data;
- cpu_power_mode_t power_state; /*dormant or shutdown*/
-};
-
-struct zx_cpu_context
-{
- u32 flags; /*before save context, set this flag*/
- u32 saved_items; /*after save a context, set a flag for restore*/
- u32 *control_data;
- u32 *pmu_data;
- u32 *timer_data;
- u32 *vfp_data;
- u32 *gic_interface_data;
- u32 *gic_dist_private_data;
- u32 *banked_registers;
- u32 *cp15_data;
- u32 *debug_data;
- u32 *mmu_data;
- u32 *other_data;
- cpu_power_mode_t power_state; /*dormant or shutdown*/
- cpu_sleep_type_t sleep_type; /*hotplug or idle or suspend*/
-};
-
-
-struct zx_pm_main_table
-{
- u32 wakeup_vaddr; /*the iram:0 shadow ram*/
- u32 wakeup_ram_size;
- u32 num_cpus;
- u32 cur_cpu;
- u32 scu_address; /* 0 => no SCU */
- u32 scu_address_p;
- u32 ic_dist_address; /* 0 => no Interrupt Controller */
- u32 ic_interface_address;
- u32 l2_address; /* 0 => no L2CC */
- u32 l2_address_p;
- u32 crm_address;
- u32 crm_address_p;
- struct zx_cluster_context* cluster_context;
- struct zx_cpu_context* cpu_context[MAX_CPU_NUM];
-};
-
-
-
-extern int zx_pm_context_init(void);
-extern int zx_set_context_level (cpu_sleep_type_t sleep_type);
-extern void zx_pm_save_context(void);
-extern void zx_pm_restore_context(void);
-extern void zx_pm_restore_abort_context(void);
-extern void pm_init_l2_and_scu(void);
-
-#endif /*_ZX_PM_CONTEXT_H*/
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-custom.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-custom.c
deleted file mode 100644
index 55af7d4..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-custom.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * zx-pm-custom.c - power management custom interface.
- *
- * Written by zxp.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/suspend.h>
-#include <linux/tick.h>
-
-#include "zx-pm.h"
-
-/*===================================================================
- *== 7520v2 ap interrupt arrangement ===============================
- *===================================================================
- *=================================== evb dc mifi =======
- *== timer1 -- wake y y y
- *== m02ap_icp y y y
- *== ps2ap_icp y y y
- *== ext0 -- pmu y n y
- *== ext1 -- pg(charger) y n y
- *== ext2 -- wps_key n n y
- *== ext3 -- rst_key y n y
- *== ext4 -- pwr_key y n n
- *== ext7 -- wps_key y n n
- *== ext6 -- wifi_wake y n y
- *== alarm y n n
- *== rtc y n n
- *===================================================================
- */
-/* evb */
-#if defined(CONFIG_ARCH_ZX297520V3_MIFI) || defined(CONFIG_ARCH_ZX297520V3_EVB) || defined(CONFIG_ARCH_ZX297520V3_MDL) ||\
- defined(CONFIG_ARCH_ZX297520V3_PHONE) || defined(CONFIG_ARCH_ZX297520V3_WATCH) || defined(CONFIG_ARCH_ZX297520V3_CPE) ||\
- defined(CONFIG_ARCH_ZX297520V3_POC)|| defined(CONFIG_ARCH_ZX297520V3_FWP)|| defined(CONFIG_ARCH_ZX297520V3_CAP) ||\
- defined(CONFIG_ARCH_ZX297520V3_UFI)|| defined(CONFIG_ARCH_ZX297520V3_CPE_SWITCH)
-
-/*AP_INT_*/
-#define WAKE_SRC_AP_TIMER1 (1U << 0)
-#define WAKE_SRC_AP_TIMER2 (1U << 1)
-#define WAKE_SRC_ICP_PS2AP (1U << 2)
-#define WAKE_SRC_USB_POWERDWN_UP (1U << 3)
-#define WAKE_SRC_USB_POWERDWN_DOWN (1U << 4)
-#define WAKE_SRC_HSIC_POWERDWN_UP (1U << 5)
-#define WAKE_SRC_HSIC_POWERDWN_DOWN (1U << 6)
-#define WAKE_SRC_ICP_M02AP (1U << 7)
-#define WAKE_SRC_RTC_ALARM (1U << 8)
-#define WAKE_SRC_RTC_TIMER (1U << 9)
-#define WAKE_SRC_KEYPAD (1U << 10)
-#define WAKE_SRC_SD1_DATA1 (1U << 11)
-#define WAKE_SRC_RESERVED (1U << 12)
-#define WAKE_SRC_SPCU_PW (1U << 13)
-#define WAKE_SRC_EXTERNAL0 (1U << 14)
-#define WAKE_SRC_EXTERNAL1 (1U << 15)
-#define WAKE_SRC_EXTERNAL2 (1U << 16)
-#define WAKE_SRC_EXTERNAL3 (1U << 17)
-#define WAKE_SRC_EXTERNAL4 (1U << 18)
-#define WAKE_SRC_EXTERNAL5 (1U << 19)
-#define WAKE_SRC_EXTERNAL6 (1U << 20)
-#define WAKE_SRC_EXTERNAL7 (1U << 21)
-#define WAKE_SRC_EXTERNAL8 (1U << 22)
-#define WAKE_SRC_EXTERNAL9 (1U << 23)
-#define WAKE_SRC_EXTERNAL10 (1U << 24)
-#define WAKE_SRC_EXTERNAL11 (1U << 25)
-#define WAKE_SRC_EXTERNAL12 (1U << 26)
-#define WAKE_SRC_EXTERNAL13 (1U << 27)
-#define WAKE_SRC_EXTERNAL14 (1U << 28)
-#define WAKE_SRC_EXTERNAL15 (1U << 29)
-#define WAKE_SRC_SD0_DATA1 (1U << 30)
-#define WAKE_SRC_ICP_PHY2AP (1U << 31)
-
-
-static unsigned int wake_source_for_sleep[] =
-{
- WAKE_SRC_ICP_M02AP | WAKE_SRC_ICP_PS2AP | WAKE_SRC_AP_TIMER1 | \
- WAKE_SRC_ICP_PHY2AP ,
- /*WAKE_SRC_RTC_ALARM | WAKE_SRC_RTC_TIMER | \
- WAKE_SRC_EXTERNAL0 | WAKE_SRC_EXTERNAL1 | WAKE_SRC_EXTERNAL2 | \
- WAKE_SRC_EXTERNAL3 | WAKE_SRC_EXTERNAL4 | WAKE_SRC_EXTERNAL5 | \
- WAKE_SRC_EXTERNAL6 | WAKE_SRC_EXTERNAL13 | WAKE_SRC_EXTERNAL14 |\
- WAKE_SRC_EXTERNAL7 ,*/
- /*|\
- WAKE_SRC_USB_POWERDWN_UP | WAKE_SRC_USB_POWERDWN_DOWN,*/
-};
-
-#else
-
-/* dc */
-static unsigned int wake_source_for_sleep[] =
-{
- WAKE_SRC_ICP_M02AP | WAKE_SRC_ICP_PS2AP | WAKE_SRC_AP_TIMER1 | \
- WAKE_SRC_EXTERNAL0,
-};
-
-#endif
-
-unsigned int pm_get_wakesource(void)
-{
- return wake_source_for_sleep[0];
-}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-helpers.S b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-helpers.S
deleted file mode 100644
index 8b09038..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-helpers.S
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * ZTE CPU low power powerdown and powerup helper code.
- *
- * Copyright (C) 2013 ZTE, Inc.
- * Written by ZXP
- *
- * This program is free software,you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/threads.h>
-#include <asm/asm-offsets.h>
-#include <asm/assembler.h>
-#include <asm/glue-cache.h>
-#include <asm/glue-proc.h>
-
-
-#define MIDR_CPU_MASK 0xff00fff0
-#define MMU_DISABLE_MASK 0x10001807 /* clear TRE, I Z C M */
-
-
-#define SCTLR_I (1<<12)
-#define SCTLR_Z (1<<11)
-#define SCTLR_C (1<<2)
-
-/**
- * This function takes three arguments
- * r0: Destination start address (must be word aligned)
- * r1: Source start address (must be word aligned)
- * r2: Number of words to copy
- * Return value is updated destination pointer (first unwritten word)
- */
-ENTRY(copy_words)
- cmp r2, #0
- beq copy_end
-loop_copy:
- ldr r3, [r1], #4
- str r3, [r0], #4
- subs r2, r2, #1
- bne loop_copy
-copy_end:
- bx lr
-ENDPROC(copy_words)
-
-ENTRY(copy_wordsandclear)
- cmp r2, #0
- beq copyclear_end
-loop_copyclear:
- ldr r3, [r1]
- str r3, [r0], #4
- str r2,[r1]/*Ö»Êǽ«Ô¼Ä´æÆ÷ÖµÐ޸ģ¬ÓÃÓÚÁÙʱÑéÖ¤£¬ÕýÈ·×÷·¨ÊÇÇå0*/
- add r1,r1,#4
- subs r2, r2, #1
- bne loop_copyclear
-copyclear_end:
- bx lr
-ENDPROC(copy_wordsandclear)
-/* ; Note: assumes conversion will be successful! */
-ENTRY(va_to_pa)
- mov r1, r0
- mcr p15, 0, r0, c7, c8, 1 /* Priv Write Current World VA-PA */
- mrc p15, 0, r0, c7, c4, 0 /* Get PA */
- bfc r0, #0, #12 /* We want top bits of translated addr */
- bfc r1, #12, #20 /* plus bottom bits of input addr */
- orr r0, r0, r1
- bx lr
-ENDPROC(va_to_pa)
-
-
-ENTRY(read_sctlr)
- mrc p15, 0, r0, c1, c0, 0
- bx lr
-ENDPROC(read_sctlr)
-
-
-ENTRY(write_sctlr)
- mcr p15, 0, r0, c1, c0, 0
- isb
- bx lr
-ENDPROC(write_sctlr)
-
-ENTRY(read_drar)
- mrc p14, 0, r0, c1, c0, 0 /* Read Debug ROM Address Register */
- bx lr
-ENDPROC(read_drar)
-
-
-ENTRY(read_dsar)
- mrc p14, 0, r0, c2, c0, 0 /* Read Debug Self Address Offset Register */
- bx lr
-ENDPROC(read_dsar)
-
-
-
-ENTRY(write_osdlr)
- mcr p14, 0, r0, c1, c3, 4 /* Write OS Double Lock Register */
- bx lr
-ENDPROC(write_osdlr)
-
-
-
-ENTRY(disable_mmu)
- mrc p15, 0, r3, c1, c0, 0
- ldr r2, =MMU_DISABLE_MASK
- bic r3, r3, r2
- dsb
- mcr p15, 0, r3, c1, c0, 0
- isb
- bx lr
-ENDPROC(disable_mmu)
-
-ENTRY(read_cpuid)
- mrc p15, 0, r0, c0, c0, 5 /* Read MPIDR */
- and r0, r0, #0xff /* extract CPU number */
- bx lr
-ENDPROC(read_cpuid)
-
-
-ENTRY(enable_cache)
- mrc p15, 0, r0, c1, c0, 0
- movw r1, #SCTLR_I | SCTLR_Z | SCTLR_C
- orr r0, r0, r1
- mcr p15, 0, r0, c1, c0, 0
- bx lr
-ENDPROC(enable_cache)
-
-
-ENTRY(exit_coherency)
- isb
- dsb
- mrc p15,0,r0,c1,c0,1
- bic r0,r0,#0x00000040
- mcr p15,0,r0,c1,c0,1
- isb
- dsb
- bx lr
-ENDPROC(exit_coherency)
-
-
-ENTRY(join_coherency)
- isb
- dsb
- mrc p15,0,r0,c1,c0,1
- orr r0,r0,#0x00000040
- mcr p15,0,r0,c1,c0,1
- isb
- dsb
- bx lr
-ENDPROC(join_coherency)
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-helpers.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-helpers.h
deleted file mode 100644
index 27e1512..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-helpers.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * zx-pm.h - power management helpers interface.
- *
- * Written by zxp.
- *
- */
-
-#ifndef _ZX_PM_HELPERS_H
-#define _ZX_PM_HELPERS_H
-
-/*
- * common helper functions
- */
-
-extern unsigned va_to_pa(unsigned virtual_address);
-extern unsigned read_drar(void);
-extern unsigned read_dsar(void);
-extern void write_osdlr(unsigned value);
-extern unsigned read_sctlr(void);
-extern void write_sctlr(unsigned value);
-extern void disable_mmu(void);
-extern unsigned read_cpuid(void);
-extern void enable_cache(void);
-extern void exit_coherency(void);
-extern void join_coherency(void);
-
-extern unsigned * copy_words(volatile unsigned *destination, volatile unsigned *source, unsigned num_words);
-extern unsigned * copy_wordsandclear(volatile unsigned *destination, volatile unsigned *source, unsigned num_words);
-
-/*
- * V7 functions
- */
-extern void save_control_registers(u32 *pointer, int is_secure);
-extern void save_mmu(u32 *pointer);
-extern void save_cpu_if(u32 *pointer);
-extern void gic_mask(void);
-extern void save_performance_monitors(u32 *pointer);
-extern void save_banked_registers(u32 *pointer);
-extern void save_cp15(u32 *pointer);
-extern void save_vfp(u32 *pointer);
-extern void save_generic_timer(u32 *pointer);
-extern void save_v7_debug(u32 *pointer);
-
-extern void restore_control_registers(u32 *pointer, int is_secure);
-extern void zx_restore_control_registers(u32 *pointer, int is_secure);
-extern void restore_mmu(u32 *pointer);
-extern void restore_cpu_if(u32 *pointer);
-extern void gic_unmask(void);
-extern void restore_performance_monitors(u32 *pointer);
-extern void restore_banked_registers(u32 *pointer);
-extern void restore_cp15(u32 *pointer);
-extern void restore_vfp(u32 *pointer);
-extern void restore_generic_timer(u32 *pointer);
-extern void restore_v7_debug(u32 *pointer);
-
-extern void disable_clean_inv_dcache_v7_l1(void);
-extern void disable_clean_inv_cache_pl310(unsigned pl310_address, unsigned stack_start, unsigned stack_size, int disable);
-extern void disable_clean_inv_dcache_v7_all(void);
-extern void clean_dcache_v7_l1(void);
-extern void clean_mva_dcache_v7_l1(void *mva);
-extern void invalidate_icache_v7_pou(void);
-extern void invalidate_icache_v7(void);
-extern void invalidate_dcache_v7_all(void);
-extern void enable_icache_v7(void);
-extern void appf_smc_handler(void);
-extern void enter_secure_monitor_mode(void);
-extern void enter_nonsecure_svc_mode(void);
-extern void set_security_state(int ns);
-extern void reset_init(void);
-
-/*
- * PL310 functions
- */
-extern void clean_inv_range_pl310(void *start, unsigned size, unsigned pl310_address); /* addresses are inclusive */
-extern void clean_range_pl310(void *start, unsigned size, unsigned pl310_address); /* addresses are inclusive */
-extern void inv_range_pl310(void *start, unsigned size, unsigned pl310_address);
-extern void clean_inv_pl310(unsigned pl310_address);
-extern void clean_pl310(unsigned pl310_address);
-extern void save_pl310(u32 *pointer, unsigned pl310_address);
-extern void restore_pl310(u32 *pointer, unsigned pl310_address, int dormant);
-extern void set_enabled_pl310(unsigned enabled, unsigned pl310_address);
-extern void set_status_pl310(unsigned status, unsigned pl310_address);
-extern int is_enabled_pl310(unsigned pl310_address);
-extern void init_lp_of_l2(unsigned pl310_address);
-extern void clean_disable_pl310(unsigned pl310_address);
-
-/*
- * GIC functions
- */
-extern int gic_distributor_set_enabled(int enabled, unsigned gic_distributor_address);
-extern void save_gic_interface(u32 *pointer, unsigned gic_interface_address, int is_secure);
-extern int save_gic_distributor_private(u32 *pointer, unsigned gic_distributor_address, int is_secure);
-extern int save_gic_distributor_shared(u32 *pointer, unsigned gic_distributor_address, int is_secure);
-extern void restore_gic_interface(u32 *pointer, unsigned gic_interface_address, int is_secure);
-extern void restore_gic_distributor_private(u32 *pointer, unsigned gic_distributor_address, int is_secure);
-extern void restore_gic_distributor_shared(u32 *pointer, unsigned gic_distributor_address, int is_secure);
-extern unsigned int gic_get_cur_pending(unsigned gic_interface_address);
-
-extern unsigned int gic_set_processorsleep(bool issleep);
-extern void pm_save_gic_wake_enable(void);
-extern void pm_restore_gic_wake_enable(void);
-/*
- * A9 functions
- */
-extern void save_a9_timers(u32 *pointer, unsigned twd_address);
-extern void save_a9_global_timer(u32 *pointer, unsigned timer_address);
-extern void save_a9_other(u32 *pointer, int is_secure);
-
-extern void restore_a9_timers(u32 *pointer, unsigned twd_address);
-extern void restore_a9_global_timer(u32 *pointer, unsigned timer_address);
-extern void restore_a9_other(u32 *pointer, int is_secure);
-
-
-/*
- * A9 SCU functions
- */
-extern void save_a9_scu(u32 *pointer, unsigned scu_address);
-extern void restore_a9_scu(u32 *pointer, unsigned scu_address);
-extern void set_status_a9_scu(unsigned cpu_index, unsigned status, unsigned scu_address);
-extern int num_cpus_from_a9_scu(unsigned scu_address);
-extern void init_lp_of_scu(unsigned scu_address);
-
-/*
- * pm common functions
- */
-extern void zx_set_wakeup_address(u32 wakeup_addr);
-extern void pm_printk(const char *fmt, ...);
-extern cpu_sleep_type_t pm_get_sleep_type(void);
-extern int zx_get_pll_used(void);
-extern int pm_get_pll_used(void);
-extern u32 pm_get_sleep_time(void);
-extern void pm_init_crm_temp(void);
-extern u64 read_persistent_us(void);
-
-extern void save_a53_sys_timer(u32 *pointer, unsigned timer_address);
-extern void restore_a53_sys_timer(u32 *pointer, unsigned timer_address);
-extern void disable_flush_dcache_L1_flush_cache_L2(void);
-
-/*
- *pm watchdog functions
- */
-#ifdef CONFIG_ZX29_WATCHDOG
-extern void zx_wdt_handle_before_psm(void);
-extern void zx_wdt_handle_after_psm(void);
-#else
-static void zx_wdt_handle_before_psm(void){}
-static void zx_wdt_handle_after_psm(void){}
-#endif
-
-/*
- *pm suspend functions
- */
-extern void zx_suspend_init(void);
-
-/*
- *cpu sleep functions
- */
-extern void cpu_reset_handler(void);
-extern void cpu_wake_up(void);
-extern void do_sleep_cpu(void);
-extern void zx_jump_addr(unsigned long addr);
-extern void waiting_ddr_dfs(unsigned long flag_addr);
-
-/*
- * GCC Compatibility
- */
-#ifndef __ARMCC_VERSION
-#define __nop() __asm__ __volatile__( "nop\n" )
-#endif
-
-#endif /*_ZX_PM_HELPERS_H*/
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-null.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-null.c
deleted file mode 100644
index 969dddd..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-null.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * ZTE power management main driver
- *
- * Copyright (C) 2013 ZTE Ltd.
- * by zxp
- *
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-#include <linux/suspend.h>
-#include <linux/time.h>
-#include <linux/timer.h>
-#include <linux/delay.h>
-
-unsigned int pm_get_wakesource(void)
-{
- return 0;
-}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-suspend.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-suspend.c
deleted file mode 100644
index 4440927..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-suspend.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * ZTE suspend power management driver
- *
- * Copyright (C) 2013 ZTE Ltd.
- * by zxp
- *
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/suspend.h>
-#include <linux/math64.h>
-
-#include <asm/system_misc.h>
-
-#include "zx-pm.h"
-
-/**************************************
- * SW code for suspend
- **************************************/
-
-/*********************************************************************
- * FUNCTION DEFINATIONS
- ********************************************************************/
-static int zx_suspend_ops_valid(suspend_state_t state)
-{
- return state == PM_SUSPEND_MEM;
-}
-
-static int zx_suspend_ops_begin(suspend_state_t state)
-{
- pm_ram_log("@@@@@@@@@@ Chip_pm_begin @@@@@@@@@@\n");
-
-
- pm_set_wakeup_reason(WR_NONE);
-
- return 0;
-}
-
-static int zx_suspend_ops_prepare(void)
-{
- pm_ram_log("@@@@@@@@@@ Chip_pm_prepare @@@@@@@@@@\n");
-
- return 0;
-}
-
-#define AP_SLEEP_IN_TIMERS IRAM_ADDR_FOR_WAKE_CNT
-#define AP_SLEEP_OUT_TIMERS IRAM_ADDR_FOR_SLEEP_CNT
-
-static int zx_suspend_ops_enter(suspend_state_t state)
-{
- /* legacy log */
- pm_ram_log("@@@@@@@@@@ Chip_pm_enter @@@@@@@@@@\n");
-
- pm_write_reg(AP_SLEEP_IN_TIMERS, (unsigned int)read_persistent_us());
-
-#ifdef CONFIG_ZX_PM_DEBUG
- pm_write_reg(AP_SUSPEND_STATUS_FLAG,0x1);
-#endif
- /* deal soc/clk/powerdomain/pll out of A9 module
- *¢ssuspend debug uart¡¢GPIO and other device out of A9 */
- zx_board_suspend();
- /*¢close clock&powerdomains that PCU does not controls */
- zx_dpm_suspend();
-
- /*¢mask all and backup, then unmask wakeup interrupts */
- zx_unmask_wakeup_interrupt();
-
- zx_pm_pre_suspend();
-// setup_timer_wakeup(__SLEEP_TIME_1s__*20); //20s
-// setup_timer_wakeup(60); //61us each is 30.5us used ot test abnormal exit from sleep
-
-/*
- if(pm_get_mask_info()&PM_SUSPEND_WFI)
- do_wfi();
- else
-*/
- {
- /*¢cpu enter lowpower mode */
-#ifdef CONFIG_ZX_PM_DEBUG
- // zx_enter_sleep(CPU_SLEEP_TYPE_IDLE_LP2);
- pm_write_reg(AP_SUSPEND_STATUS_FLAG,0x2);
-#endif
- zx_enter_sleep(CPU_SLEEP_TYPE_LP1);
- }
-
- /* get wakeup reason */
- //pm_wake_reason = pm_get_wakeup_reason();
- zx_pm_post_suspend();
-
-#ifdef CONFIG_ZX_PM_DEBUG
- pm_write_reg(AP_SUSPEND_STATUS_FLAG,0x8);
-#endif
- /* restore interrupt that masked */
- zx_interrupt_mask_restore();
-
- /*¢resume clock&powerdomains */
- zx_dpm_resume();
- /* resume debug uart¡¢GPIO and other device out of A9 */
- zx_board_resume();
-
- pm_write_reg(AP_SLEEP_OUT_TIMERS, (unsigned int)read_persistent_us());
- pm_write_reg(AP_SLEEP_TIME_ADDR,(pm_read_reg(AP_SLEEP_OUT_TIMERS) - pm_read_reg(AP_SLEEP_IN_TIMERS)));
-
- return 0;
-}
-
-static void zx_suspend_ops_finish(void)
-{
- pm_ram_log("@@@@@@@@@@ Chip_pm_finish @@@@@@@@@@\n");
-}
-
-static void zx_suspend_ops_end(void)
-{
- pm_ram_log("@@@@@@@@@@ Chip_pm_end @@@@@@@@@@\n");
-}
-
-static struct platform_suspend_ops zx_suspend_ops = {
- .valid = zx_suspend_ops_valid,
- .begin = zx_suspend_ops_begin,
- .prepare = zx_suspend_ops_prepare,
- .enter = zx_suspend_ops_enter,
- .finish = zx_suspend_ops_finish,
- .end = zx_suspend_ops_end,
-};
-
-void zx_suspend_init(void)
-{
- pr_info("[SLP] Power/SPM_INIT \n");
-
- suspend_set_ops(&zx_suspend_ops);
-
- pm_write_reg(AP_SLEEP_IN_TIMERS, 0);
- pm_write_reg(AP_SLEEP_OUT_TIMERS, 0);
-}
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-v8.S b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-v8.S
deleted file mode 100644
index e51b690..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm-v8.S
+++ /dev/null
@@ -1,1187 +0,0 @@
-/*
- * ZTE CPU low power powerdown and powerup helper code.
- *
- * Copyright (C) 2013 ZTE, Inc.
- * Written by ZXP
- *
- * This program is free software,you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/threads.h>
-#include <asm/asm-offsets.h>
-#include <asm/assembler.h>
-#include <asm/glue-cache.h>
-#include <asm/glue-proc.h>
-#include <asm/vfp.h>
-
-
-/* Aliases for mode encodings - do not change */
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_ABT 0x17
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-#define MODE_MON 0x16 /* A-profile (Security Extensions) only */
-#define SCR_NS 0x01 /* A-profile (Security Extensions) only */
-
-#define TTBCR_EAE (1<<31) /* Are we using LPAE? */
-
-#define CACHE_LINE_SIZE 32 /* TODO: remove this */
-#define SCTLR_I (1<<12)
-
-.arm
-
-/*cpu interface */
-ENTRY(save_cpu_if)
- /* mrc p15, 0, r3, c4, c6, 0 ICC PMR ÓÅÏȼ¶ÆÁ±Î¼Ä´æÆ÷*/
- str r3,[r0], #4
- /* mrc p15, 0, r3, c12, c12, 3 BPR1*/
- str r3,[r0], #4
- /* mrc p15, 6, r3, c12, c12, 7 ICC MGRPEN1 */
- str r3,[r0], #4
- /* mrc p15, 0, r3, c12, c12, 7 int group enable reg 1 */
- str r3,[r0], #4
- /* mrc p15, 0, r3, c12, c12, 6 int group enable reg 0 */
- str r3,[r0], #4
- mrc p15, 0, r3, c12, c12, 5 /*ICC_SRE system reg enable */
- str r3,[r0], #4
- mrc p15, 6, r3, c12, c12, 5 /*ICC_MSRE system reg for EL3 */
- str r3,[r0], #4
- mrc p15, 0, r3, c12, c12, 4 /*CTRL*/
- str r3,[r0], #4
- bx lr
-ENDPROC(save_cpu_if)
-
-ENTRY(restore_cpu_if)
- ldr r3,[r0], #4
- mcr p15, 0, r3, c4, c6, 0 /*ICC PMR ÓÅÏȼ¶ÆÁ±Î¼Ä´æÆ÷*/
- ldr r3,[r0], #4
- mcr p15, 0, r3, c12, c12, 3 /*BPR1*/
- ldr r3,[r0], #4
- mcr p15, 6, r0, c12, c12, 7 /* ICC MGRPEN1 */
- ldr r3,[r0], #4
- mcr p15, 0, r0, c12, c12, 7 /* int group enable reg 1 */
- ldr r3,[r0], #4
- mcr p15, 0, r0, c12, c12, 6 /* int group enable reg 0 */
- ldr r3,[r0], #4
- mcr p15, 0, r0, c12, c12, 5 /*ICC_SRE system reg enable */
- ldr r3,[r0], #4
- mcr p15, 6, r0, c12, c12, 5 /*ICC_MSRE system reg for EL3 */
- ldr r3,[r0], #4
- mcr p15, 0, r3, c12, c12, 4 /*CTRL*/
- bx lr
-ENDPROC(restore_cpu_if)
-
-ENTRY(gic_mask) /*cpu int disable*/
- mov r0,#0
- mcr p15, 0, r0, c12, c12, 6 /* ICC_IGRPEN0*/
- mrc p15, 0, r0, c12, c12, 7 /* ICC_IGRPEN1*/
- bic r0, r0, #1
- mcr p15, 0, r0, c12, c12, 7 /* ICC_IGRPEN1*/
- mrc p15, 6, r0, c12, c12, 7 /* ICC MGRPEN1 */
- bic r0, r0, #1
- mcr p15, 6, r0, c12, c12, 7 /* ICC MGRPEN1 */
- bx lr
-ENDPROC(gic_mask)
-
-ENTRY(gic_unmask)
-
-ENDPROC(gic_unmask)
-
-ENTRY(save_performance_monitors)
-
- stmfd sp!, {r4, r8, r9, r10}
-
- /* Ignore:
- * Count Enable Clear Register
- * Software Increment Register
- * Interrupt Enable Clear Register
- */
-
- mrc p15,0,r8,c9,c12,0 /* PMon: Control Register */
- bic r1,r8,#1
- mcr p15,0,r1,c9,c12,0 /* disable counter updates from here */
- isb /* 0b0 => PMCR<0> */
- mrc p15,0,r9,c9,c12,3 /* PMon: Overflow Flag Status Reg */
- mrc p15,0,r10,c9,c12,5 /* PMon: Event Counter Selection Reg */
- stm r0!, {r8-r10}
- ubfx r9,r8,#11,#5 /* extract # of event counters, N */
- tst r9, r9
- beq next_backup
-
-loop_backup:
- subs r9,r9,#1 /* decrement N */
- mcr p15,0,r9,c9,c12,5 /* PMon: select CounterN */
- isb
- mrc p15,0,r3,c9,c13,1 /* PMon: save Event Type register */
- mrc p15,0,r4,c9,c13,2 /* PMon: save Event Counter register */
- stm r0!, {r3,r4}
- bne loop_backup
-
-next_backup:
- mrc p15,0,r1,c9,c13,0 /* PMon: Cycle Count Register */
- mrc p15,0,r2,c9,c14,0 /* PMon: User Enable Register */
- mrc p15,0,r3,c9,c14,1 /* PMon: Interrupt Enable Set Reg */
- mrc p15,0,r4,c9,c12,1 /* PMon: Count Enable Set Register */
- stm r0!, {r1-r4}
-
- ldmfd sp!, {r4, r8, r9, r10}
- bx lr
-ENDPROC(save_performance_monitors)
-
-ENTRY(restore_performance_monitors)
-
- stmfd sp!, {r4-r5, r8-r10, lr}
- /* NOTE: all counters disabled by PMCR<0> == 0 on reset */
-
- /* Restore performance counters */
- ldm r0!,{r8-r10} /* recover first block of PMon context */
- /* (PMCR, PMOVSR, PMSELR) */
- mov r1, #0 /* generate register of all 0's */
- mvn r2, #0 /* generate register of all 1's */
- mcr p15,0,r2,c9,c14,2 /* disable all counter related interrupts */
- mcr p15,0,r2,c9,c12,3 /* clear all overflow flags */
- isb
-
- ubfx r12,r8,#11,#5 /* extract # of event counters, N (0-31) */
- tst r12, r12
- beq 20f
- mov r3, r12 /* for N >0, generate a 2nd copy of N */
- mov r4, #1
- lsl r4, r4, r3
- sub r4, r4, #1 /* set bits<N-1:0> to all 1's */
-
-0:
- subs r3,r3,#1 /* decrement N */
- mcr p15,0,r3,c9,c12,5 /* select Event CounterN */
- isb
- mrc p15,0,r5,c9,c13,1 /* read Event Type register */
- bfc r5,#0,#8
- mcr p15,0,r5,c9,c13,1 /* set Event Type to 0x0 */
- mcr p15,0,r2,c9,c13,2 /* set Event Counter to all 1's */
- isb
- bne 0b
-
- mov r3, #1
- bic r5, r9, #1<<31
- mcr p15,0,r5,c9,c12,1 /* enable Event Counters */
- /* (PMOVSR bits set) */
- mcr p15,0,r3,c9,c12,0 /* set the PMCR global enable bit */
- isb
- mcr p15,0,r9,c9,c12,4 /* set event count overflow bits */
- isb
- mcr p15,0,r4,c9,c12,2 /* disable Event Counters */
-
- /* restore the event counters */
-10:
- subs r12,r12,#1 /* decrement N */
- mcr p15,0,r12,c9,c12,5 /* select Event CounterN */
- isb
- ldm r0!,{r3-r4}
- mcr p15,0,r3,c9,c13,1 /* restore Event Type */
- mcr p15,0,r4,c9,c13,2 /* restore Event Counter */
- isb
- bne 10b
-
-20:
- tst r9, #0x80000000 /* check for cycle count overflow flag */
- beq 40f
- mcr p15,0,r2,c9,c13,0 /* set Cycle Counter to all 1's */
- isb
- mov r3, #0x80000000
- mcr p15,0,r3,c9,c12,1 /* enable the Cycle Counter */
- isb
-
-30:
- mrc p15,0,r4,c9,c12,3 /* check cycle count overflow now set */
- movs r4,r4 /* test bit<31> */
- bpl 30b
- mcr p15,0,r3,c9,c12,2 /* disable the Cycle Counter */
-
-40:
- mcr p15,0,r1,c9,c12,0 /* clear the PMCR global enable bit */
- isb
-
- /* restore the remaining PMon registers */
- ldm r0!,{r1-r4}
- mcr p15,0,r1,c9,c13,0 /* restore Cycle Count Register */
- mcr p15,0,r2,c9,c14,0 /* restore User Enable Register */
- mcr p15,0,r3,c9,c14,1 /* restore Interrupt Enable Set Reg */
- mcr p15,0,r4,c9,c12,1 /* restore Count Enable Set Register */
- mcr p15,0,r10,c9,c12,5 /* restore Event Counter Selection */
- isb
- mcr p15,0,r8,c9,c12,0 /* restore the PM Control Register */
- isb
-
- ldmfd sp!, {r4-r5, r8-r10, pc}
-ENDPROC(restore_performance_monitors)
-
-
-
-ENTRY(save_banked_registers)
- mrs r2, CPSR /* save current mode */
- cps #MODE_SYS /* switch to System mode */
- str sp,[r0], #4 /* save the User SP */
- str lr,[r0], #4 /* save the User LR */
- cps #MODE_ABT /* switch to Abort mode */
- str sp,[r0], #4 /* save the current SP */
- mrs r3,SPSR
- stm r0!,{r3,lr} /* save the current SPSR, LR */
- cps #MODE_UND /* switch to Undefined mode */
- str sp,[r0], #4 /* save the current SP */
- mrs r3,SPSR
- stm r0!,{r3,lr} /* save the current SPSR, LR */
- cps #MODE_IRQ /* switch to IRQ mode */
- str sp,[r0], #4 /* save the current SP */
- mrs r3,SPSR
- stm r0!,{r3,lr} /* save the current SPSR, LR */
- cps #MODE_FIQ /* switch to FIQ mode */
- str SP,[r0], #4 /* save the current SP */
- mrs r3,SPSR
- stm r0!,{r3,r8-r12,lr} /* save the current SPSR,r8-r12,LR */
- msr CPSR_cxsf, r2 /* switch back to original mode */
-
- bx lr
-ENDPROC(save_banked_registers)
-
-ENTRY(restore_banked_registers)
- mrs r2, CPSR /* save current mode */
- cps #MODE_SYS /* switch to System mode */
- ldr sp,[r0],#4 /* restore the User SP */
- ldr lr,[r0],#4 /* restore the User LR */
- cps #MODE_ABT /* switch to Abort mode */
- ldr sp,[r0],#4 /* restore the current SP */
- ldm r0!,{r3,lr} /* restore the current LR */
- msr SPSR_fsxc,r3 /* restore the current SPSR */
- cps #MODE_UND /* switch to Undefined mode */
- ldr sp,[r0],#4 /* restore the current SP */
- ldm r0!,{r3,lr} /* restore the current LR */
- msr SPSR_fsxc,r3 /* restore the current SPSR */
- cps #MODE_IRQ /* switch to IRQ mode */
- ldr sp,[r0],#4 /* restore the current SP */
- ldm r0!,{r3,lr} /* restore the current LR */
- msr SPSR_fsxc,r3 /* restore the current SPSR */
- cps #MODE_FIQ /* switch to FIQ mode */
- ldr sp,[r0],#4 /* restore the current SP */
- ldm r0!,{r3,r8-r12,lr} /* restore the current r8-r12,LR */
- msr SPSR_fsxc,r3 /* restore the current SPSR */
- msr CPSR_cxsf, r2 /* switch back to original mode */
-
-//0
- bx lr
-ENDPROC(restore_banked_registers)
-
-
-
-ENTRY(save_cp15)
- /* CSSELR Cache Size Selection Register */
- mrc p15,2,r3,c0,c0,0
- str r3,[r0], #4
-
- /* IMPLEMENTATION DEFINED - proprietary features:
- * (CP15 register 15, TCM support, lockdown support, etc.)
- */
-
- /* NOTE: IMP DEF registers might have save and restore order that relate
- * to other CP15 registers or logical grouping requirements and can
- * therefore occur at any point in this sequence.
- */
- bx lr
-ENDPROC(save_cp15)
-
-ENTRY(restore_cp15)
- /* CSSELR ?Cache Size Selection Register */
- ldr r3,[r0], #4
- mcr p15,2,r3,c0,c0,0
- bx lr
-ENDPROC(restore_cp15)
-
-
- /* Function called with two arguments:
- * r0 contains address to store control registers
- * r1 is non-zero if we are Secure
- */
-ENTRY(save_control_registers)
- cmp r1, #0 /* Are we Secure? */
- mrc p15,0,r2,c1,c0,1 /* ACTLR - Auxiliary Control Register */
- mrc p15,0,r3,c1,c0,0 /* SCTLR - System Control Register */
- mrc p15,0,r12,c1,c0,2 /* CPACR - Coprocessor Access Control Register */
- stm r0!, {r2-r3, r12}
-#if 0
- mrcne p15,0,r1,c12,c0,1 /* MVBAR - Monitor Vector Base Address Register */
- mrcne p15,0,r2,c1,c1,0 /* Secure Configuration Register */
- mrcne p15,0,r3,c1,c1,1 /* Secure Debug Enable Register */
- mrcne p15,0,r12,c1,c1,2 /* Non-Secure Access Control Register */
- stmne r0!, {r1-r3,r12}
-
- mrc p14,6,r1,c0,c0,0 /* TEECR */
- mrc p14,6,r2,c1,c0,0 /* TEEHBR */
- mrc p14,7,r3,c1,c0,0 /* JOSCR */
- mrc p14,7,r12,c2,c0,0 /* JMCR */
- stm r0!, {r1-r3,r12}
-#else
- mrc p15,0,r1,c5,c0,0 /* ifsr */
- mrc p15,0,r2,c6,c0,0 /* dfar */
- mrc p15,0,r3,c6,c0,2 /* ifar */
- mrc p15,0,r12,c5,c1,0 /* adfsr */
- stm r0!, {r1-r3, r12}
-
- mrc p15,0,r1,c5,c1,1 /* aifsr */
- mrc p15,1,r12,c15,c0,0 /* l2actrl */
- stm r0!, {r1,r12}
-#endif
-
- bx lr
-ENDPROC(save_control_registers)
-
-
- /* Function called with two arguments:
- * r0 contains address to read control registers
- * r1 is non-zero if we are Secure
- */
-ENTRY(restore_control_registers)
- cmp r1, #0 /* Are we Secure? */
- ldm r0!, {r2-r3, r12}
- mcr p15,0,r2,c1,c0,1 /* ACTLR - Auxiliary Control Register */
- mcr p15,0,r3,c1,c0,0 /* SCTLR - System Control Register */
- mcr p15,0,r12,c1,c0,2 /* CPACR - Coprocessor Access Control Register */
-
- #if 0
- ldmne r0!, {r1-r3,r12}
- mcrne p15,0,r1,c12,c0,1 /* MVBAR - Monitor Vector Base Address Register */
- mcrne p15,0,r2,c1,c1,0 /* Secure Configuration Register */
- mcrne p15,0,r3,c1,c1,1 /* Secure Debug Enable Register */
- mcrne p15,0,r12,c1,c1,2 /* Non-Secure Access Control Register */
-
- ldm r0!, {r1-r3,r12}
- mcr p14,6,r1,c0,c0,0 /* TEECR */
- mcr p14,6,r2,c1,c0,0 /* TEEHBR */
- mcr p14,7,r3,c1,c0,0 /* JOSCR */
- mcr p14,7,r12,c2,c0,0 /* JMCR */
- #else
- ldm r0!, {r1-r3, r12}
- mcr p15,0,r1,c5,c0,0 /* ifsr */
- mcr p15,0,r2,c6,c0,0 /* dfar */
- mcr p15,0,r3,c6,c0,2 /* ifar */
- mcr p15,0,r12,c5,c1,0 /* adfsr */
-
- ldm r0!, {r1, r12}
- mcr p15,0,r1,c5,c1,1 /* aifsr */
-// mcr p15,1,r12,c15,c0,0 /* l2actrl */
- #endif
- isb
- bx lr
-ENDPROC(restore_control_registers)
-
-ENTRY(save_mmu)
- stmfd sp!, {r4, r5, r6, r7}
- /* ASSUMPTION: no useful fault address / fault status information*/
-
- mrc p15,0,r4,c12,c0,0 /* VBAR */
- mrc p15,0,r5,c2,c0,2 /* TTBCR */
-
- tst r5, #TTBCR_EAE /* Are we using LPAE? */
-
- /* save 32 or 64 bit TTBRs */
- mrceq p15,0,r6,c2,c0,0 /* 32 bit TTBR0 */
- mrceq p15,0,r7,c2,c0,1 /* 32 bit TTBR1 */
- #if 0
- mrrcne p15,0,r6,r7,c2 /* 64 bit TTBR0 */
- #endif
- stm r0!, {r4-r7}
- #if 0
- mrrcne p15,1,r6,r7,c2 /* 64 bit TTBR1 */
- stmne r0!, {r6-r7}
- #endif
- mrc p15,0,r4,c3,c0,0 /* DACR */
- mrc p15,0,r5,c7,c4,0 /* PAR */
- mrc p15,0,r6,c10,c2,0 /* PRRR/mair0*/
- mrc p15,0,r7,c10,c2,1 /* NMRR/mair1 */
- stm r0!, {r4-r7}
-
- /* TODO: IMPLEMENTATION DEFINED - TCM, lockdown and performance monitor support
- * CP15 registers 9 and 11
- */
-
- mrc p15,0,r4,c13,c0,1 /* CONTEXTIDR */
- mrc p15,0,r5,c13,c0,2 /* TPIDRURW */
- mrc p15,0,r6,c13,c0,3 /* TPIDRURO */
- mrc p15,0,r7,c13,c0,4 /* TPIDRPRW */
- stm r0!, {r4-r7}
-
- mrc p15,0,r4,c10,c3,0 /* amair */
- mrc p15,0,r5,c10,c3,1 /* amair */
- mrc p15,0,r6,c2,c0,2 /* ttbcr */
- stm r0!, {r4-r6}
-
- ldmfd sp!, {r4, r5, r6, r7}
- bx lr
-ENDPROC(save_mmu)
-
-ENTRY(restore_mmu)
-
- stmfd sp!, {r4, r5, r6, r7}
- ldm r0!, {r4-r7}
- mcr p15,0,r4,c12,c0,0 /* VBAR */
- mcr p15,0,r5,c2,c0,2 /* TTBCR */
-
- tst r5, #TTBCR_EAE /* Are we using LPAE? */
-
- /* restore 32 or 64 bit TTBRs */
- mcreq p15,0,r6,c2,c0,0 /* 32 bit TTBR0 */
- mcreq p15,0,r7,c2,c0,1 /* 32 bit TTBR1 */
- #if 0
- mcrrne p15,0,r6,r7,c2 /* 64-bit TTBR0 */
- ldmne r0!, {r6-r7}
- mcrrne p15,1,r6,r7,c2 /* 64-bit TTBR1 */
- #endif
- ldm r0!, {r4-r7}
- mcr p15,0,r4,c3,c0,0 /* DACR */
- mcr p15,0,r5,c7,c4,0 /* PAR */
- mcr p15,0,r6,c10,c2,0 /* PRRR */
- mcr p15,0,r7,c10,c2,1 /* NMRR */
-
- /* TODO: IMPLEMENTATION DEFINED - TCM, lockdown and performance monitor support
- * CP15 registers 9 and 11
- */
-
- ldm r0!, {r4-r7}
- mcr p15,0,r4,c13,c0,1 /* CONTEXTIDR */
- mcr p15,0,r5,c13,c0,2 /* TPIDRURW */
- mcr p15,0,r6,c13,c0,3 /* TPIDRURO */
- mcr p15,0,r7,c13,c0,4 /* TPIDRPRW */
-
- ldm r0!, {r4-r6}
- mcr p15,0,r4,c10,c3,0 /* amair */
- mcr p15,0,r5,c10,c3,1 /* amair */
- mcr p15,0,r6,c2,c0,2 /* ttbcr */
-
- ldmfd sp!, {r4, r5, r6, r7}
-
- bx lr
-ENDPROC(restore_mmu)
-
-#if 0
-ENTRY(save_vfp)
- /* FPU state save/restore.
- * FPSID,MVFR0 and MVFR1 don't get serialized/saved (Read Only).
- */
- mrc p15,0,r3,c1,c0,2 /* CPACR allows CP10 and CP11 access */
- ORR r2,r3,#0xF00000
- mcr p15,0,r2,c1,c0,2
- isb
- mrc p15,0,r2,c1,c0,2
- and r2,r2,#0xF00000
- cmp r2,#0xF00000
- beq f0
- movs r2, #0
- b f2
-
-0:
- /* Save configuration registers and enable. */
- vmrs r12,FPEXC
- str r12,[r0],#4 /* Save the FPEXC */
- /* Enable FPU access to save/restore the other registers. */
- ldr r2,=0x40000000
- vmsr FPEXC,r2
- vmrs r2,FPSCR
- str r2,[r0],#4 /* Save the FPSCR */
- /* Store the VFP-D16 registers. */
- vstm r0!, {D0-D15}
- /* Check for Advanced SIMD/VFP-D32 support */
- vmrs r2,MVFR0
- and r2,r2,#0xF /* extract the A_SIMD bitfield */
- cmp r2, #0x2
- blt f1
- /* Store the Advanced SIMD/VFP-D32 additional registers. */
- vstm r0!, {D16-D31}
-
- /* IMPLEMENTATION DEFINED: save any subarchitecture defined state
- * NOTE: Don't change the order of the FPEXC and CPACR restores
- */
-1:
- vmsr FPEXC,r12 /* Restore the original En bit of FPU. */
-2:
- mcr p15,0,r3,c1,c0,2 /* Restore the original CPACR value. */
- bx lr
-ENDPROC(save_vfp)
-
-
-restore_vfp FUNCTION
- /* FPU state save/restore. Obviously FPSID,MVFR0 and MVFR1 don't get
- * serialized (RO).
- * Modify CPACR to allow CP10 and CP11 access
- */
- mrc p15,0,r1,c1,c0,2
- ORR r2,r1,#0x00F00000
- mcr p15,0,r2,c1,c0,2
- /* Enable FPU access to save/restore the rest of registers. */
- ldr r2,=0x40000000
- vmsr FPEXC, r2
- /* Recover FPEXC and FPSCR. These will be restored later. */
- ldm r0!,{r3,r12}
- /* Restore the VFP-D16 registers. */
- vldm r0!, {D0-D15}
- /* Check for Advanced SIMD/VFP-D32 support */
- vmrs r2, MVFR0
- and r2,r2,#0xF /* extract the A_SIMD bitfield */
- cmp r2, #0x2
- blt f0
-
- /* Store the Advanced SIMD/VFP-D32 additional registers. */
- vldm r0!, {D16-D31}
-
- /* IMPLEMENTATION DEFINED: restore any subarchitecture defined state */
-
-0 /* Restore configuration registers and enable.
- * Restore FPSCR _before_ FPEXC since FPEXC could disable FPU
- * and make setting FPSCR unpredictable.
- */
- vmsr FPSCR,r12
- vmsr FPEXC,r3 /* Restore FPEXC after FPSCR */
- /* Restore CPACR */
- mcr p15,0,r1,c1,c0,2
- bx lr
- ENDFUNC
-#endif
-
-ENTRY(save_vfp)
-#if 0 //zxp
-
- /* FPU state save/restore. */
- /* FPSID,MVFR0 and MVFR1 don't get serialized/saved (Read Only). */
- mrc p15,0,r3,c1,c0,2 /* CPACR allows CP10 and CP11 access */
- ORR r2,r3,#0xF00000
- mcr p15,0,r2,c1,c0,2
- isb
- mrc p15,0,r2,c1,c0,2
- and r2,r2,#0xF00000
- cmp r2,#0xF00000
- beq 0f
- movs r2, #0
- b 2f
-
- /* Save configuration registers and enable. */
-0:
- FMRX r12,FPEXC /* vmrs r12,FPEXC */
- str r12,[r0],#4 /* Save the FPEXC */
- /* Enable FPU access to save/restore the other registers. */
- ldr r2,=0x40000000
- FMXR FPEXC,r2 /* vmsr FPEXC,r2 */
- FMRX r2,FPSCR /* vmrs r2,FPSCR */
- str r2,[r0],#4 /* Save the FPSCR */
- /* Store the VFP-D16 registers. */
- vstm r0!, {D0-D15}
- /* Check for Advanced SIMD/VFP-D32 support */
- FMRX r2,MVFR0 /* vmrs r2,MVFR0 */
- and r2,r2,#0xF /* extract the A_SIMD bitfield */
- cmp r2, #0x2
- blt 1f
- /* Store the Advanced SIMD/VFP-D32 additional registers. */
- vstm r0!, {D16-D31}
-
- /* IMPLEMENTATION DEFINED: save any subarchitecture defined state */
- /* NOTE: Don't change the order of the FPEXC and CPACR restores */
-
- /* Restore the original En bit of FPU. */
-1:
- FMXR FPEXC,r12 /* vmsr FPEXC,r12 */
-
- /* Restore the original CPACR value. */
-2:
- mcr p15,0,r3,c1,c0,2
-#endif
- bx lr
-ENDPROC(save_vfp)
-
-
-ENTRY(restore_vfp)
- /* FPU state save/restore. Obviously FPSID,MVFR0 and MVFR1 don't get
- * serialized (RO).
- * Modify CPACR to allow CP10 and CP11 access
- */
-#if 0 //zxp
- mrc p15,0,r1,c1,c0,2
- ORR r2,r1,#0x00F00000
- mcr p15,0,r2,c1,c0,2
- /* Enable FPU access to save/restore the rest of registers. */
- ldr r2,=0x40000000
- FMXR FPEXC, r2 /* vmsr FPEXC, r2 */
- /* Recover FPEXC and FPSCR. These will be restored later. */
- ldm r0!,{r3,r12}
- /* Restore the VFP-D16 registers. */
- vldm r0!, {D0-D15}
- /* Check for Advanced SIMD/VFP-D32 support */
- FMRX r2, MVFR0 /* vmrs r2, MVFR0 */
- and r2,r2,#0xF /* extract the A_SIMD bitfield */
- cmp r2, #0x2
- blt 0f
-
- /* Store the Advanced SIMD/VFP-D32 additional registers. */
- vldm r0!, {D16-D31}
-
- /* IMPLEMENTATION DEFINED: restore any subarchitecture defined state */
-0:
- /* Restore configuration registers and enable.
- * Restore FPSCR _before_ FPEXC since FPEXC could disable FPU
- * and make setting FPSCR unpredictable.
- */
- FMXR FPSCR,r12 /* vmsr FPSCR,r12 */
- /* Restore FPEXC after FPSCR */
- FMXR FPEXC,r3 /* vmsr FPEXC,r3 */
- /* Restore CPACR */
- /* will restore in mt_restore_control_registers */
- /* mcr p15,0,r1,c1,c0,2 */
-#endif
- bx lr
-ENDPROC(restore_vfp)
-
-
- /* We assume that the OS is not using the Virtualization extensions,
- * and that the warm boot code will set up CNTHCTL correctly.
- * CNTP_CVAL will be preserved as it is in the always-on domain.
- */
-#if 0
-ENTRY(save_generic_timer)
- mrc p15,0,r2,c14,c2,1 /* read CNTP_CTL */
- mrc p15,0,r3,c14,c2,0 /* read CNTP_TVAL */
- mrc p15,0,r12,c14,c1,0 /* read CNTKCTL */
- stm r0!, {r2, r3, r12}
- bx lr
-ENDPROC(save_generic_timer)
-
-
-ENTRY(restore_generic_timer)
- ldm r0!, {r2, r3, r12}
- mcr p15,0,r3,c14,c2,0 /* write CNTP_TVAL */
- mcr p15,0,r12,c14,c1,0 /* write CNTKCTL */
- mcr p15,0,r2,c14,c2,1 /* write CNTP_CTL */
- bx lr
-ENDPROC(restore_generic_timer)
-#endif
-
-
- /* This function disables L1 data caching, then cleans and invalidates
- the whole L1 data cache.
- */
-
-ENTRY(disable_clean_inv_dcache_v7_l1)
- stmfd sp!, {r4, lr}
-
- /* Disable L1 cache */
- dsb
- mrc p15,0,r3,c1,c0,0
- bic r3, #4 /* Clear C bit */
- mcr p15,0,r3,c1,c0,0
- dsb
-
- /* No more Data cache allocations can happen at L1.
- Until we finish cleaning the Inner cache, any accesses to dirty data
- (e.g. by translation table walks) may get the wrong (Outer) data, so
- we have to be sure everything that might be accessed is clean.
- We already know that the translation tables are clean (see late_init).
- */
-
- mov r0, #0 /* Select L1 Data/Unified cache */
- mcr p15,2,r0,c0,c0,0
- mrc p15,1,r0,c0,c0,0 /* Read size */
- ubfx r3, r0, #13, #15 /* sets - 1 */
- add r3, r3, #1 /* sets */
- ubfx r4, r0, #0, #3 /* log2(words per line) - 2 */
- add r4, r4, #4 /* set shift = log2(bytes per line) */
- ubfx r2, r0, #3, #10 /* ways - 1 */
- clz r12, r2 /* way shift */
- add r2, r2, #1 /* ways */
-
- /* r2,r3 inner, outer loop targets, r1 inner loop counter, r0 zero */
-5:
- cmp r3, #0
- beq 20f
- sub r3, r3, #1
- mov r1, r2
-
-10:
- cmp r1, #0
- beq 5b
- sub r1, r1, #1
- mov r0, r1, lsl r12 /* Fill in Way field */
- orr r0, r0, r3, lsl r4 /* Fill in Set field */
- mcr p15,0,r0,c7,c14,2 /* DCCISW */
- b 10b
-
-20:
- dsb
- ldmfd sp!, {r4, lr}
- bx lr
-ENDPROC(disable_clean_inv_dcache_v7_l1)
-
-
-ENTRY(invalidate_icache_v7_pou)
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
- bx lr
-ENDPROC(invalidate_icache_v7_pou)
-
-
-ENTRY(invalidate_icache_v7)
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
- bx lr
-ENDPROC(invalidate_icache_v7)
-
-
-ENTRY(enable_icache_v7)
- mrc p15, 0, r0, c1, c0, 0 //enable Icache
- movw r1, #SCTLR_I
- orr r0, r0, r1
- mcr p15, 0, r0, c1, c0, 0
-ENDPROC(enable_icache_v7)
-
-
-ENTRY(invalidate_dcache_v7_all)
- /* Must iterate over the caches in order to synthesise a complete invalidation
- of data/unified cache
- */
-//zxp stmfd sp!, {r4-r11} /* zxp delete for no sp to use */
- mrc p15, 1, r0, c0, c0, 1 /* read clidr */
- ands r3, r0, #0x7000000 /* extract loc from clidr */
- mov r3, r3, lsr #23 /* left align loc bit field */
- beq finished /* if loc is 0, then no need to clean */
- mov r10, #0 /* start clean at cache level 0 (in r10) */
-loop1:
- add r2, r10, r10, lsr #1 /* work out 3x current cache level */
- mov r12, r0, lsr r2 /* extract cache type bits from clidr */
- and r12, r12, #7 /* mask of bits for current cache only */
- cmp r12, #2 /* see what cache we have at this level */
- blt skip /* skip if no cache, or just i-cache */
- mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
- mov r12, #0
- mcr p15, 0, r12, c7, c5, 4 /* prefetchflush to sync new cssr&csidr */
- mrc p15, 1, r12, c0, c0, 0 /* read the new csidr */
- and r2, r12, #7 /* extract the length of the cache lines */
- add r2, r2, #4 /* add 4 (line length offset) */
- ldr r6, =0x3ff
- ands r6, r6, r12, lsr #3 /* find maximum number on the way size */
- clz r5, r6 /* find bit pos of way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r12, lsr #13 /* extract max number of the index size */
-loop2:
- mov r8, r6 /* create working copy of max way size */
-loop3:
- orr r11, r10, r8, lsl r5 /* factor way and cache number into r11 */
- orr r11, r11, r7, lsl r2 /* factor index number into r11 */
- mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
- subs r8, r8, #1 /* decrement the way */
- bge loop3
- subs r7, r7, #1 /* decrement the index */
- bge loop2
-skip:
- add r10, r10, #2 /* increment cache number */
- cmp r3, r10
- bgt loop1
-finished:
- mov r10, #0
-
- mcr p15, 0, r10, c7, c10, 4 /* drain write buffer */
- mcr p15, 0, r10, c8, c7, 0 /* invalidate I + D TLBs */
- mcr p15, 0, r10, c2, c0, 2 /* TTB control register */
-//zxp ldmfd sp!, {r4-r11}
- bx lr
-ENDPROC(invalidate_dcache_v7_all)
-
-
-ENTRY(disable_clean_inv_dcache_v7_all)
- /* Must iterate over the caches in order to synthesise a complete clean
- of data/unified cache */
- stmfd sp!, {r4-r11}
-
- /* Disable integrated data/unified cache */
- dsb
- mrc p15, 0, r3, c1, c0, 0
- bic r3, #4 /* Clear C bit */
- mcr p15, 0, r3, c1, c0, 0
- isb
-
- /* No more Data cache allocations can happen.
- Until we finish cleaning the cache, any accesses to dirty data
- (e.g. by translation table walks) may get the wrong (Outer) data, so
- we have to be sure everything that might be accessed is clean.
- We already know that the translation tables are clean (see late_init).
- */
-
-
- mrc p15, 1, r0, c0, c0, 1 /* read clidr */
- ands r3, r0, #0x7000000 /* extract loc from clidr */
- mov r3, r3, lsr #23 /* left align loc bit field */
- beq 50f /* if loc is 0, then no need to clean */
- mov r10, #0 /* start clean at cache level 0 (in r10) */
-10:
- add r2, r10, r10, lsr #1 /* work out 3x current cache level */
- mov r12, r0, lsr r2 /* extract cache type bits from clidr */
- and r12, r12, #7 /* mask of bits for current cache only */
- cmp r12, #2 /* see what cache we have at this level */
- blt 40f /* skip if no cache, or just i-cache */
- mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
- mov r12, #0
- mcr p15, 0, r12, c7, c5, 4 /* prefetchflush to sync new cssr&csidr */
- mrc p15, 1, r12, c0, c0, 0 /* read the new csidr */
- and r2, r12, #7 /* extract the length of the cache lines */
- add r2, r2, #4 /* add 4 (line length offset) */
- ldr r6, =0x3ff
- ands r6, r6, r12, lsr #3 /* find maximum number on the way size */
- clz r5, r6 /* find bit pos of way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r12, lsr #13 /* extract max number of the index size */
-20:
- mov r8, r6 /* create working copy of max way size */
-30:
- orr r11, r10, r8, lsl r5 /* factor way and cache number into r11 */
- orr r11, r11, r7, lsl r2 /* factor index number into r11 */
- mcr p15, 0, r11, c7, c14, 2 /* clean & invalidate by set/way */
- subs r8, r8, #1 /* decrement the way */
- bge 30b
- subs r7, r7, #1 /* decrement the index */
- bge 20b
-40:
- add r10, r10, #2 /* increment cache number */
- cmp r3, r10
- bgt 10b
-50:
- mov r10, #0
- mcr p15, 0, r10, c7, c10, 4 /* drain write buffer */
- ldmfd sp!, {r4-r11}
- bx lr
-ENDPROC(disable_clean_inv_dcache_v7_all)
-
-
- /* This function cleans the whole L1 data cache */
-ENTRY(clean_dcache_v7_l1)
- stmfd sp!, {r4, lr}
-
- mov r0, #0 /* Select L1 Data/Unified cache */
- mcr p15,2,r0,c0,c0,0
- mrc p15,1,r0,c0,c0,0 /* Read size (CCSIDR) */
- ubfx r3, r0, #13, #15 /* sets - 1 */
- add r3, r3, #1 /* sets */
- ubfx r4, r0, #0, #3 /* log2(words per line) - 2 */
- add r4, r4, #4 /* set shift = log2(bytes per line) */
- ubfx r2, r0, #3, #10 /* ways - 1 */
- clz r12, r2 /* way shift */
- add r2, r2, #1 /* ways */
-
- /* r2,r3 inner, outer loop targets, r1 inner loop counter, r0 zero */
-0:
- cmp r3, #0
- beq 20f
- sub r3, r3, #1
- mov r1, r2
-
-10:
- cmp r1, #0
- beq 0b
- sub r1, r1, #1
- mov r0, r1, lsl r12 /* Fill in Way field */
- orr r0, r0, r3, lsl r4 /* Fill in Set field */
- mcr p15,0,r0,c7,c10,2 /* DCCSW */
- b 10b
-
-20:
- dsb
- pop {r4, lr}
- bx lr
-ENDPROC(clean_dcache_v7_l1)
-
-#if 0 //zxp
- /* This function cleans a single line from the L1 dcache */
-clean_mva_dcache_v7_l1
- mcr p15,0,r0,c7,c10,1 /* DCCMVAC */
- bx lr
-
-enter_secure_monitor_mode FUNCTION
- mov r0, lr
- mov r1, sp
- smc #0
-appf_smc_handler
- /* We are now in Monitor mode, make sure we're Secure */
- mrc p15, 0, r12, c1, c1, 0
- bic r12, #SCR_NS
- mcr p15, 0, r12, c1, c1, 0
- /* Restore sp and return - stack must be uncached or in NS memory! */
- mov sp, r1
- bx r0
- ENDFUNC
-
-enter_nonsecure_svc_mode FUNCTION
- /* Copy the Monitor mode sp and lr values */
- mov r2, lr
- mov r3, sp
- mrc p15, 0, r1, c1, c1, 0
- orr r1, #SCR_NS
- mcr p15, 0, r1, c1, c1, 0
- adr lr, non_secure
- movs pc, lr
-non_secure
- /* We are now in non-secure state */
- /* Restore sp and return */
- mov sp, r3
- bx r2
- ENDFUNC
-#endif
-
-ENTRY(save_a53_other)
-#if 0//A53ûÓÐ
- mrc p15,0,r12,c15,c0,0 /* Read Power Control Register */
- str r12, [r0], #4
- mrc p15, 4, r12, c15, c0, 0 /* Read Configuration Base Address Register */
- str r12, [r0], #4
-
- mrc p15,0,r3,c0,c0,0 /* Read Main ID Register */
- ubfx r3, r3, #20, #4 /* Extract major version number */
- cmp r3, #2
- blt 1f /* PLE only possible in r2p0 onwards */
- mrc p15,0,r3,c11,c0,0 /* Read PLE IDR */
- cmp r3, #0
- beq 1f /* No PLE present */
-
- mrc p15,0,r3,c11,c1,0 /* Read PLE UAR */
- mrc p15,0,r12,c11,c1,1 /* Read PLE PCR */
- stm r0!, {r3, r12}
-
-1:
- bx lr
-#else
-
-#endif
-ENDPROC(save_a53_other)
-
-
-ENTRY(restore_a53_other)
-#if 0
- cmp r1, #0 /* Check we are secure */
- ldr r12, [r0], #4
- andne r12, r12, #0x01 /* We only restore the Dynamic Clock gating bit */
- mcrne p15,0,r12,c15,c0,0 /* Write Power Control Register (if secure) */
- ldr r12, [r0], #4
- mcrne p15, 4, r12, c15, c0, 0 /* Write Configuration Base Address Register (if Secure) */
-
- mrc p15,0,r3,c0,c0,0 /* Read Main ID Register */
- ubfx r3, r3, #20, #4 /* Extract major version number */
- cmp r3, #2
- blt 1f /* PLE only possible in r2p0 onwards */
- mrc p15,0,r3,c11,c0,0 /* Read PLE IDR */
- cmp r3, #0
- beq 1f /* No PLE present */
-
- ldm r0!, {r3, r12}
- mcr p15,0,r3,c11,c1,0 /* Write PLE UAR */
- mcr p15,0,r12,c11,c1,1 /* Write PLE PCR */
-
-1:
- bx lr
-#else
-#endif
-ENDPROC(restore_a53_other)
-
-
-.equ C1_IBIT , 0x00001000
-.equ C1_CBIT , 0x00000004
-ENTRY(disable_flush_dcache_L1_flush_cache_L2)
-/******************************************************************************* *
-push stack push {r0,r1,r2,r3,r4,r5,r7,r9,r10,r11,r14}
-* ******************************************************************************/
-
- stmfd sp!, {r4,r5,r6,r7,r8, r9, r10,r11,lr}
-/*******************************************************************************
-*__disable_dcache
-* ******************************************************************************/
- MRC p15,0,r0,c1,c0,0
- BIC r0,r0,#C1_CBIT
- dsb
- MCR p15,0,r0,c1,c0,0
- dsb
- isb
-/*Erratum:794322,An instruction fetch can be allocated into the L2 cache after the cache is disabled Status
-This erratum can be avoided by inserting both of the following after the SCTLR.C bit is cleared to 0, and before the caches are cleaned or invalidated:
-1) A TLBIMVA operation to any address.
-2) A DSB instruction.*/
- MCR p15,0,r0,c8,c7,1
- dsb
- isb
-/*******************************************************************************
-* __inner_flush_dcache_L1
-* ******************************************************************************/
- dmb /*@ ensure ordering with previous memory accesses */
- mrc p15, 1, r0, c0, c0, 1 /* @ read clidr */
- ands r3, r0, #0x7000000 /* @ extract loc from clidr */
- mov r3, r3, lsr #23 /* @ left align loc bit field */
- beq DF1F2_L1_finished /* @ if loc is 0, then no need to clean */
- mov r10, #0 /* @ start clean at cache level 1 */
-DF1F2_L1_loop1:
- add r2, r10, r10, lsr #1 /* @ work out 3x current cache level */
- mov r1, r0, lsr r2 /* @ extract cache type bits from clidr */
- and r1, r1, #7 /* @ mask of the bits for current cache only */
- cmp r1, #2 /* @ see what cache we have at this level */
- blt DF1F2_L1_skip /* @ skip if no cache, or just i-cache */
- mcr p15, 2, r10, c0, c0, 0 /* @ select current cache level in cssr */
- isb /* @ isb to sych the new cssr&csidr */
- mrc p15, 1, r1, c0, c0, 0 /* @ read the new csidr */
- and r2, r1, #7 /* @ extract the length of the cache lines */
- add r2, r2, #4 /* @ add 4 (line length offset) */
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 /* @ find maximum number on the way size */
- clz r5, r4 /* @ find bit position of way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 /* @ extract max number of the index size */
-DF1F2_L1_loop2:
- mov r9, r4 /* @ create working copy of max way size */
-DF1F2_L1_loop3:
- orr r11, r10, r9, lsl r5 /* @ factor way and cache number into r11 */
- orr r11, r11, r7, lsl r2 /* @ factor index number into r11*/
-#if 1
- mcr p15, 0, r11, c7, c10, 2 /* @ clean by set/way */
- mcr p15, 0, r11, c7, c6, 2 /* @ invalidate by set/way*/
-#endif
-#if 0
- mcr p15, 0, r11, c7, c14, 2 /* @ clean & invalidate by set/way*/
-#endif
- subs r9, r9, #1 /* @ decrement the way */
- bge DF1F2_L1_loop3
- subs r7, r7, #1 /* @ decrement the index */
- bge DF1F2_L1_loop2
-DF1F2_L1_skip:
- /* @add r10, r10, #2 */ /* @ increment cache number */
- /*@cmp r3, r10
- @bgt DF1F2_L1_loop1*/
-DF1F2_L1_finished:
- mov r10, #0 /* @ swith back to cache level 0 */
- mcr p15, 2, r10, c0, c0, 0 /* @ select current cache level in cssr */
- dsb
- isb
-/******************************************************************************* *
-clrex
-* ******************************************************************************/
- clrex
-/*******************************************************************************
-* __inner_flush_dcache_L2
-* ******************************************************************************/
- dmb /* @ ensure ordering with previous memory accesses */
- mrc p15, 1, r0, c0, c0, 1 /* @ read clidr */
- ands r3, r0, #0x7000000 /* @ extract loc from clidr */
- mov r3, r3, lsr #23 /* @ left align loc bit field */
- beq DF1F2_L2_finished /* @ if loc is 0, then no need to clean */
- mov r10, #2 /* @ start clean at cache level 2*/
-DF1F2_L2_loop1:
- add r2, r10, r10, lsr #1 /* @ work out 3x current cache level */
- mov r1, r0, lsr r2 /* @ extract cache type bits from clidr */
- and r1, r1, #7 /* @ mask of the bits for current cache only */
- cmp r1, #2 /* @ see what cache we have at this level */
- blt DF1F2_L2_skip /* @ skip if no cache, or just i-cache */
- mcr p15, 2, r10, c0, c0, 0 /* @ select current cache level in cssr */
- isb /* @ isb to sych the new cssr&csidr */
- mrc p15, 1, r1, c0, c0, 0 /* @ read the new csidr */
- and r2, r1, #7 /* @ extract the length of the cache lines */
- add r2, r2, #4 /* @ add 4 (line length offset) */
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 /* @ find maximum number on the way size */
- clz r5, r4 /* @ find bit position of way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 /* @ extract max number of the index size*/
-DF1F2_L2_loop2:
- mov r9, r4 /* @ create working copy of max way size*/
-DF1F2_L2_loop3:
- orr r11, r10, r9, lsl r5 /* @ factor way and cache number into r11 */
- orr r11, r11, r7, lsl r2 /* @ factor index number into r11 */
- mcr p15, 0, r11, c7, c14, 2 /* @ clean & invalidate by set/way */
- subs r9, r9, #1 /* @ decrement the way */
- bge DF1F2_L2_loop3
- subs r7, r7, #1 /* @ decrement the index */
- bge DF1F2_L2_loop2
-DF1F2_L2_skip:
- /*@add r10, r10, #2 @ increment cache number */
- /*@cmp r3, r10 */
- /*@bgt DF1F2_L2_loop1 */
-DF1F2_L2_finished:
- mov r10, #0 /* @ swith back to cache level 0 */
- mcr p15, 2, r10, c0, c0, 0 /* @ select current cache level in cssr */
- dsb
- isb
-/*******************************************************************************
-* pop stack pop {r0,r1,r2,r3,r4,r5,r7,r9,r10,r11,r14}
-* ******************************************************************************/
- ldmfd sp!, {r4, r5,r6,r7,r8, r9, r10,r11,lr}
- bx lr
-ENDPROC(disable_flush_dcache_L1_flush_cache_L2)
-
-#if 0
-.equ HAL_CPSR_SVC_MODE, 0x13
-.equ HAL_CPSR_MON_MODE, 0x16
-ENTRY(tse_monitor_init)
-ldr r0, =monitor_exception_vectors // Get address of Monitor's vector table
- mcr p15, 0, r0, c12, c0, 1 // Write Monitor Vector Base Address Register
-
- cps #HAL_CPSR_MON_MODE // disabled irq and fiq when enter monitor mode
- ldr sp, =mon_stack // init sp for monitor mode
- cps #HAL_CPSR_SVC_MODE
-
- bx lr
-ENDPROC(tse_monitor_init)
-#endif
-
-#define GIC_DIST_BASE (0xF2000000)
-#define GIC_RDIST_BASE (0xF2040000)
-
-ENTRY(reset_init)
- ldr r3, =GIC_DIST_BASE
- ldr r0, =0x50
- str r0, [r3]
-
- ldr r3, =GIC_RDIST_BASE
- add r1, r3, #0x14
-
- LDR R0, [R1]
- LDR R2, =0xfffffffd
- AND R0, R0, R2
- STR R0, [R1]
-
- LDR R2, = 0xFFFFFFFB
-wait:
- LDR R0, [R1]
- AND R0, R0, R2
- CMP R0, #0
- BNE wait
-
- SUB R1, R1, #0x14
- LDR R2, =0x10080
- ADD R1, R1, R2
- LDR R2, =0xFFFFFFFF
- STR R2, [R1]
-
- MRS R0, CPSR
- BIC R0, #0x1F
- ORR R0, #0xD6
- MSR CPSR_c, R0
-
- MOV r3, #0xD
- MCR p15,#0x6,r3,c12,c12,#5
- MCR p15,0,r3,c12,c12,#5
-
- MRC p15,0,r1,c1,c1,0
- MOV r2, r1
- ORR r2, #0x1
- MCR p15,0,r2,c1,c1,0
-
- MCR p15,#0x4,r3,c12,c9,#5
-
- MRS R0, CPSR
- BIC R0, #0x1F
- ORR R0, #0xD3
- MSR CPSR_c, R0
-
- ret lr
-ENDPROC(reset_init)
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm.c
deleted file mode 100644
index d46668f..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm.c
+++ /dev/null
@@ -1,561 +0,0 @@
-/*
- * ZTE power management main driver
- *
- * Copyright (C) 2013 ZTE Ltd.
- * by zxp
- *
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-#include <linux/suspend.h>
-#include <linux/time.h>
-#include <linux/timer.h>
-#include <linux/delay.h>
-#include <linux/cpu.h>
-#include "zx-pm.h"
-#include <linux/timer.h>
-#include <linux/kthread.h> /*For kthread_run()*/
-
-#ifdef CONFIG_ZX_PM_DEBUG
-
-static struct delayed_work pm_debug_work;
-struct kobject *pm_debug_kobj;
-static struct timer_list pm_debug_timer;
-
-#define PM_DEBUG_DELAY msecs_to_jiffies(10000) //10s
-
-#endif
-
-/*********************************************************************
- * some common pm functions
- ********************************************************************/
-#ifdef CONFIG_ZX_RAM_CONSOLE
-#define PM_LOG_SRAM_SIZE (4*1024)
-static char pm_sram_printk_buf[PM_LOG_SRAM_SIZE]; // loop buffer
-static u32 pm_sram_point = 0;
-static u32 pm_sram_inited = 0;
-//static char pm_sram_temp_buf[512] = {0};
-
-static void pm_sram_cpy(char *s, unsigned len)
-{
- if(pm_sram_point + len >= PM_LOG_SRAM_SIZE)
- pm_sram_point = 0;
-
- memcpy(pm_sram_printk_buf+pm_sram_point, s, len);
- pm_sram_point += len;
-}
-
-/* ------------------for idle print msg-------------------------*/
-
-#define PM_IDLE_SRAM_ITEM_SIZE (200)
-#define PM_IDLE_SRAM_ITEM_CNT (8)
-#define PM_IDLE_TOTAL_SRAM_SIZE (PM_IDLE_SRAM_ITEM_SIZE*PM_IDLE_SRAM_ITEM_CNT)
-
-typedef struct
-{
- char buf[PM_IDLE_SRAM_ITEM_SIZE];
-}pm_idle_sram;
-
-static pm_idle_sram pm_idle_sram_buf[PM_IDLE_SRAM_ITEM_CNT];
-static unsigned int pm_idle_sram_state = 0;
-static unsigned int pm_idle_sram_cur_item = 0;
-
-static u32 last_uart_jiffies =0;
-struct timer_list timer_uart_print;
-
-
-#ifdef CONFIG_CPU_IDLE
-extern int zx_idle_get_debug_flag(void);
-extern int zx_idle_get_idle_flag(void); //ap idle flag
-#endif
-
-#ifndef CONFIG_CPU_IDLE
-typedef int (*pm_callback_fn)(void);
-int zx_pm_register_callback(pm_callback_fn enter_cb, pm_callback_fn exit_cb)
-{
- return 0;
-}
-EXPORT_SYMBOL(zx_pm_register_callback);
-#endif
-
-/* for idle print msg */
-
-void pm_idle_sram_start(void)
-{
- pm_idle_sram_cur_item = 0;
- pm_idle_sram_state = 1;
-}
-
-void pm_idle_sram_end(void)
-{
- pm_idle_sram_state = 0;
-}
-
-
-bool pm_idle_sram_is_permit(void)
-{
-#ifdef CONFIG_CPU_IDLE
- if(pm_idle_sram_state && (pm_get_mask_info()&PM_SLEEP_FLAG_PRINT))//if(pm_idle_sram_state && (zx_idle_get_debug_flag()&1))
- return true;
- else
- return false;
-#endif
-}
-
-static void pm_idle_sram_cpy(char *s, unsigned len)
-{
- if(!pm_idle_sram_is_permit())
- return;
-
- if((pm_idle_sram_cur_item >= PM_IDLE_SRAM_ITEM_CNT) || (len >= PM_IDLE_SRAM_ITEM_SIZE))
- {
- BUG();
- //return ;
- }
-
- memcpy(pm_idle_sram_buf[pm_idle_sram_cur_item].buf, s, len);
- pm_idle_sram_buf[pm_idle_sram_cur_item].buf[len] = 0;
- pm_idle_sram_cur_item ++;
-}
-
- /**
- * pm_uart_print
- *
- */
-
- static void pm_update_uart_jiffies(void)
- {
- last_uart_jiffies=jiffies;
- }
-
-static void pm_sleep_flag_print(void)
-{
- u32 cur_jiffies = jiffies;
- u32 work_jiffies = cur_jiffies - last_uart_jiffies;
-
- if( (work_jiffies > 200) ) {
-
- last_uart_jiffies = cur_jiffies;
- printk(" jiffies:%u; ", cur_jiffies);
- }
-}
-
-static void pm_sleepflag_print_func(struct timer_list *unused)
-{
-
- if(pm_get_mask_info()&PM_SLEEP_FLAG_PRINT) {
-
- soft_spin_lock_psm(UART_SFLOCK);
-
- pm_sleep_flag_print();
- mod_timer(&timer_uart_print ,jiffies + msecs_to_jiffies(1 * 1000));
- soft_spin_unlock_psm(UART_SFLOCK);
- }
-
-}
-
-static void pm_uart_createtimer(void)
-{
- timer_setup(&timer_uart_print, pm_sleepflag_print_func, 0);
-/*
- init_timer(&timer_uart_print);
- timer_uart_print.function = pm_sleepflag_print_func;
-*/ timer_uart_print.expires = jiffies + msecs_to_jiffies(59 * 1000);
- add_timer(&timer_uart_print);
-
-}
-
- void pm_uart_mod_timer(void)
- {
- if(pm_get_mask_info()&PM_SLEEP_FLAG_PRINT) {
- pm_update_uart_jiffies();
- mod_timer(&timer_uart_print ,jiffies + msecs_to_jiffies(1 * 1000));
- }
- }
-
- void pm_uart_del_timer(void)
- {
- if(pm_get_mask_info()&PM_SLEEP_FLAG_PRINT) {
- del_timer(&timer_uart_print);
- }
- }
-/* ------------------for idle print msg-------------------------*/
-
-#endif
-
-void pm_psm_flag_print(u32 *sleepflag)
-{
- #ifdef CONFIG_CPU_IDLE
- #endif
-}
-EXPORT_SYMBOL(pm_psm_flag_print);
-
-u32 print_cnt=0;
-
-void pm_idle_sram_print(void)
-{
-#ifdef CONFIG_ZX_RAM_CONSOLE
- int i;
-
- if((print_cnt++) % 100 == 0) {
- for(i=0; i<pm_idle_sram_cur_item; i++)
- {
- printk("%s", pm_idle_sram_buf[i].buf);
- }
-
- pm_idle_sram_cur_item = 0;
- }
-#endif
-}
-
-/**
- * usage: like printk(...)
- */
-void pm_printk(const char *fmt, ...)
-{
-#ifdef CONFIG_ZX_RAM_CONSOLE
- va_list args;
- unsigned long long t;
- unsigned long nanosec_rem;
- int tlen, len;
- char pm_sram_temp_buf[512] = {0};
-
- if(!pm_sram_inited)
- return;
-
- va_start(args, fmt);
- preempt_disable();
-
- /* add time stamp */
- t = cpu_clock(read_cpuid());
- nanosec_rem = do_div(t, 1000000000);
- tlen = sprintf(pm_sram_temp_buf, ">%5lu.%06lu< ",
- (unsigned long) t, nanosec_rem / 1000);
-
- len = vsprintf(pm_sram_temp_buf+tlen, fmt, args);
- len += tlen;
-
- pm_sram_cpy(pm_sram_temp_buf, len);
- pm_idle_sram_cpy(pm_sram_temp_buf, len);
-
- preempt_enable();
- va_end(args);
-#endif
-}
-
-void pm_sram_init(void)
-{
-#ifdef CONFIG_ZX_RAM_CONSOLE
- pr_info("[SLP] Power/SRAM_INIT \n");
-
- pm_sram_printk_buf[0] = 0;
- pm_sram_point = 0;
-
- pm_sram_inited = 1;
-#endif
-}
-
-/*********************************************************************
- * some pm debug functions
- *
- * we use sysfs interface
- ********************************************************************/
-#ifdef CONFIG_ZX_PM_DEBUG
-
-static void pm_debug_timer_expired(struct timer_list *unused)
-{
- mod_timer(&pm_debug_timer, jiffies + msecs_to_jiffies(6*1000));
-
- pr_info("[SLP] pm timer !!!");
-}
-
-
-/*=============================================================================
- *======== /sys/zte_pm/state =================================================
- *=============================================================================
- */
-
-/**
- * put the string to the buf, and return the string length
- */
-static ssize_t state_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- s += sprintf(s, "%s\n", "[SLP] no debug info now!");
-
- return (s - buf);
-}
-
-/**
- * the buf store the input string , n is the string length
- * return the status
- */
-static ssize_t state_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
-
-// zDrvRpMsg_CreateChannel(M0_ID, channel_1, 0x20);
-
- return error;
-}
-
-zte_pm_attr(state);
-
-
-/*=============================================================================
- *======== /sys/zte_pm/debug_work ===========================================
- *=============================================================================
- */
-#if 0
-static unsigned test_item = 0;
-static void pm_test_switch_clock(void)
-{
- printk("[SLP] pm_test_switch_clock: %d \n\r", test_item);
-
- switch(test_item)
- {
- case 0: /* ufi 400M */
- cpufreq_test(1, 0);
-
- break;
- case 1: /* ufi 800M */
- cpufreq_test(0, 1);
- break;
- case 2: /* 624 624M */
- cpufreq_test(1, 2);
- break;
- case 3: /* 624 156M */
- cpufreq_test(2, 3);
- break;
- case 4: /* main 26M */
- cpufreq_test(3, 4);
- test_item = 0;
- return;
- break;
- }
-
- test_item ++;
-}
-#endif
-
-static void pm_debug_func(struct work_struct *work)
-{
- printk("[SLP] runs in %s. \n\r", __func__);
-
- pm_suspend(PM_SUSPEND_MEM);
-// pm_test_switch_clock();
-
- schedule_delayed_work(&pm_debug_work, PM_DEBUG_DELAY);
-}
-
-static ssize_t pm_debug_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- s += sprintf(s, "%s\n", "[SLP] pm debug !");
-
- return (s - buf);
-}
-
-/* usage: "echo 1 > pm_debug" */
-static ssize_t pm_debug_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
- unsigned int temp;
-
- if(sscanf(buf, "%u", &temp) != 1)
- error = -EINVAL;
-
- if(temp == 1)
- schedule_delayed_work(&pm_debug_work, PM_DEBUG_DELAY);
- else
- cancel_delayed_work(&pm_debug_work);
-
- return error ? error : n;
-}
-
-zte_pm_attr(pm_debug);
-
-/*=============================================================================
- *======== /sys/zte_pm/wakelock =============================================
- *=============================================================================
- */
-extern void test_wakelock(void);
-extern void pm_debug_wakelocks(void);
-static ssize_t wakelock_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
-// pm_debug_wakelocks();
-
- return (s - buf);
-}
-
-static ssize_t wakelock_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
-
-#ifdef CONFIG_ZX_PM_SUSPEND
- test_wakelock();
-#endif
-
- return error ;
-}
-
-zte_pm_attr(wakelock);
-
-#ifdef CONFIG_ZX_AUTOSLEEP
-/*=============================================================================
- *======== /sys/zte_pm/app_done =============================================
- *=============================================================================
- */
-extern void app_start_done(void);
-static ssize_t app_done_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *s = buf;
-
- return (s - buf);
-}
-
-static ssize_t app_done_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int error = 0;
-
- app_start_done();
-
- return error;
-}
-
-zte_pm_attr(app_done);
-#endif
-
-static struct attribute * g[] =
-{
- &state_attr.attr,
- &pm_debug_attr.attr,
- &wakelock_attr.attr,
-#ifdef CONFIG_ZX_AUTOSLEEP
- &app_done_attr.attr,
-#endif
- NULL,
-};
-
-
-static struct attribute_group zte_pm_attr_group =
-{
- .attrs = g,
-};
-
-
-/**
- * 1¡¢create sysfs "/sys/zte_pm"
- * 2¡¢add attr
- */
-static int __init pm_debug_init(void)
-{
- int ret;
-
- printk(KERN_INFO "[SLP] create sysfs interface\n");
- pm_debug_kobj = kobject_create_and_add("zte_pm", NULL);
- if (!pm_debug_kobj)
- return -ENOMEM;
- ret = sysfs_create_group(pm_debug_kobj, &zte_pm_attr_group);
- if (ret)
- {
- printk(KERN_WARNING "[SLP] sysfs_create_group ret %d\n", ret);
- return ret;
- }
-
- /* init delayed work */
- INIT_DEFERRABLE_WORK(&pm_debug_work, pm_debug_func);
- /* we will start this in sysfs */
-// schedule_delayed_work(&pm_debug_work, PM_DEBUG_DELAY);
-
- timer_setup(&pm_debug_timer, pm_debug_timer_expired, 0);
-// mod_timer(&pm_debug_timer, jiffies + msecs_to_jiffies(6*1000));
-
-#ifdef CONFIG_CPU_IDLE
- /* cpuidle debug init */
- idle_debug_init();
-#endif
-
- pm_debug_mask_info_init();
-
- return 0;
-}
-
-#endif
-
-
-
-/*********************************************************************
- * FUNCTION DEFINATIONS
- ********************************************************************/
-#if 0//defined(CONFIG_ARCH_ZX297520V2EVB)
-static int __init zx_pm_init(void)
-{
- return 0;
-}
-#else
-
-static int __init zx_pm_init(void)
-{
- pr_info("[SLP] Power/PM_INIT \n");
-
- pm_init_resource();
-
-#ifdef CONFIG_PM_SLEEP
- /* 1¡¢Suspend driver */
- zx_suspend_init();
-#endif
-
-#if 0 //added when debug
- /* 2¡¢power domain initial */
- zx_pwr_init();
-#endif
-
- /* 3¡¢context memory initial */
- zx_pm_context_init();
-
- /* 4¡¢SCU/l2 lowerpower setting */
- pm_init_l2_and_scu(); /*20V5 A53 dont't need set l2,becasue l2 is ARM internal */
-
-
- /* 5¡¢acs */
- //pm_init_acs();
-
- /* 6¡¢init the ram log for pm */
- pm_sram_init();
-
-#ifdef CONFIG_ZX_PM_DEBUG
- pm_debug_init();
-#endif
-
-#ifdef CONFIG_CPU_IDLE
- /* 7¡¢idle driver initial */
-// zx_cpuidle_init();
-#endif
-
- zx29_cpufreq_init();
-
- return 0;
-}
-#endif
-
-late_initcall(zx_pm_init);
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm.h
deleted file mode 100644
index 302155d..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-pm.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * zx-pm.h - power management interface.
- *
- * Written by zxp.
- *
- */
-
-#ifndef _ZX_PM_H
-#define _ZX_PM_H
-
-#include <asm/io.h>
-#include <asm/mach/map.h>
-
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/cpuidle.h>
-
-
-#include "zx29-pm.h"
-
-#include "zx-sleep.h"
-#include "zx-pm-context.h"
-#include "zx-pm-helpers.h"
-#include "zx-cpuidle.h"
-#include "zx-cpufreq.h"
-//extern int request_ddr_freq(zx29_ddr_freq ddr_freq);
-#include <linux/soc/zte/pcu.h>
-#include <linux/soc/zte/common.h>
-#include <linux/soc/zte/spinlock.h>
-
-#ifdef CONFIG_ZX_PM_DEBUG
-
-#define zte_pm_attr(_name) \
-static struct kobj_attribute _name##_attr = \
-{ \
- .attr = \
- { \
- .name = __stringify(_name), \
- .mode = 0644, \
- }, \
- .show = _name##_show, \
- .store = _name##_store, \
-}
-
-/* /sys/zte_pm */
-extern struct kobject *pm_debug_kobj;
-#endif
-#if 0
-
-#define pm_ram_log(fmt, args...) \
-{ \
- pm_printk("[SLP] " fmt, ##args); \
-}
-#else
-#define pm_ram_log(fmt, args...) \
-{ \
- printk(KERN_INFO "[SLP] " fmt, ##args); \
- pm_printk("[SLP] " fmt, ##args); \
-}
-
-#endif
-
-/* Weak implementations for optional arch specific functions */
-#ifdef CONFIG_SYSTEM_RECOVERY
-#ifndef USE_CPPS_KO
-void __weak psm_ModemDevSleep(void)
-{
-}
-bool __weak psm_ModemSleepCheck(void)
-{
- return 0;
-}
-
-u32 __weak psm_ModemSleepTimeGet(void)
-{
- return 0;
-}
-
-void __weak psm_TimeCompensate(u32 sleepTime)
-{
-}
-void __weak psm_GetModemSleepFlagStatus(void)
-{
-}
-#endif
-#else
-extern void psm_ModemDevSleep(void);
-extern void psm_GetModemSleepFlagStatus(void);
-extern bool psm_ModemSleepCheck(void);
-extern unsigned int psm_ModemSleepTimeGet(void);
-extern void psm_TimeCompensate(unsigned int);
-#endif
-
-
-#endif /*_ZX_PM_H*/
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-sleep.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-sleep.c
deleted file mode 100644
index 8f38160..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-sleep.c
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * ZTE cpu sleep driver
- *
- * Copyright (C) 2013 ZTE Ltd.
- * by zxp
- *
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/suspend.h>
-#include <linux/cpufreq.h>
-
-#include <asm/suspend.h>
-
-#include "zx-pm.h"
-
-#ifdef CONFIG_HW_BREAKPOINT_MANAGE
-#include <linux/hw_breakpoint_manage.h>
-#endif
-/* used to return the value, if 0 represent sleeping process ok,
- * if 1 represent reset and restore back.
- */
-volatile int sleep_ret_flag[MAX_CPU_NUM] = {0};
-
-static pm_wake_reason_t pm_wake_reason;
-
-extern struct zx_pm_main_table zx_pm_main_table;
-
-//extern int request_ddr_freq(zx29_ddr_freq ddr_freq);
-
-/**
- * suspend platform device, for example: gpio, uart and so on.
- *
- */
-int zx_board_suspend(void)
-{
- //gpio
-
-// debug_uart_suspend();
-
-
- return 0;
-}
-
-/**
- * resume debug uart¡¢GPIO and other device out of A9.
- *
- */
-int zx_board_resume(void)
-{
- //gpio
-// debug_uart_resume();
-
- //uart
-
- return 0;
-}
-
-/**
- * close clocks and power domains that PCU does not controls.
- *
- */
-int zx_dpm_suspend(void)
-{
-
- return 0;
-}
-
-/**
- * resume debug uart¡¢GPIO and other device out of A9.
- *
- */
-int zx_dpm_resume(void)
-{
-
- return 0;
-}
-
-/**
- * set cpu power state before do wfi.
- *
- * cpu_context.power_state should filled in before call this function.
- */
-static void set_power_state(void)
-{
-#ifdef CONFIG_ARCH_ZX297520V2
- set_status_a9_scu(zx_pm_main_table.cur_cpu,
- zx_pm_main_table.cpu_context[zx_pm_main_table.cur_cpu]->power_state,
- zx_pm_main_table.scu_address);
-#else
-#if 0
- set_status_a53_scu(zx_pm_main_table.cur_cpu,
- zx_pm_main_table.cpu_context[zx_pm_main_table.cur_cpu]->power_state,
- zx_pm_main_table.scu_address);
-#endif
-#endif
-}
-
-#ifdef CONFIG_ZX_PM_DEBUG_TIME
-unsigned int suspend_start_time;
-unsigned int suspend_enter_time;
-unsigned int suspend_exit_time;
-unsigned int suspend_finish_time;
-unsigned int suspend_cur_time;
-unsigned int suspend_save_start_time = 0;
-unsigned int suspend_save_end_time = 0;
-unsigned int suspend_restore_start_time = 0;
-unsigned int suspend_restore_end_time = 0;
-unsigned int suspendabort_restore_start_time = 0;
-unsigned int suspendabort_restore_end_time = 0;
-unsigned int suspendabort_cnt = 0;
-unsigned int suspendsuscess_cnt = 0;
-unsigned int zx_get_cur_time(void)
-{
- return (unsigned int)read_persistent_us();
-}
-#endif
-static void zx_sleep_before_wfi(void)
-{
-// pm_switch_clk_to_26m();
-}
-
-static void zx_sleep_after_wfi(void)
-{
-// pm_switch_clk_from_26m();
-}
-
-
-/**
- * when return pointor is stored,
- * cpu will poweroff now.
- */
-static int zx_finish_suspend(unsigned long param)
-{
- /*disable&clean&inv interface*/
- disable_flush_dcache_L1_flush_cache_L2();
-
-#ifdef CONFIG_ZX_PM_DEBUG_TIME
- pm_write_reg(SLEEP_TIME_ADDR, zx_get_cur_time());
-#endif
-
- exit_coherency();
-
- set_power_state();
-
- zx_sleep_before_wfi();
-
-
-#ifdef CONFIG_ZX_PM_DEBUG
- /**/
- pm_write_reg(AP_SUSPEND_STATUS_FLAG,0x5);
-#endif
-
- zx_jump_addr(zx_pm_main_table.wakeup_vaddr+WAKEUP_CODE_LENGTH);
-
- zx_sleep_after_wfi();
-
- /* when the sleep is abnormal exit, can run here */
- return 1;
-}
-
-/**
- * when cpu sleep procedure is abort,
- * then return true.
- */
-static inline bool is_cpu_sleep_abort(void)
-{
- unsigned int cpu_id;
- struct zx_cpu_context *context;
-
- cpu_id = read_cpuid();
- context = zx_pm_main_table.cpu_context[cpu_id];
-
- if (context->power_state != CPU_POWER_MODE_RUN)
- return true;
-
- return false;
-}
-
-/**
- * cpu sleep stage may be abort for some interrupt or event pending.
- * This function is used to deal this situation.
- *
- * if state is CPU_POWER_MODE_RUN, indicated not back from restore,
- * so sleep stage is abort.
- */
-static void cpu_check_sleep_abort(void)
-{
- if (is_cpu_sleep_abort())
- {
- /*enable l1-cache, l2,
- then code can run well */
-#ifdef CONFIG_ARCH_ZX297520V2 /* 2975V2 A9*/
- set_enabled_pl310(true, zx_pm_main_table.l2_address);
-#endif
- enable_cache();
-#ifdef CONFIG_ZX_PM_DEBUG_TIME
- suspendabort_cnt++;
- suspendabort_restore_start_time = zx_get_cur_time();
-#endif
- zx_pm_restore_abort_context();
-
-#ifdef CONFIG_ZX_PM_DEBUG_TIME
- suspendabort_restore_end_time = zx_get_cur_time();
-#endif
- set_power_state();
- pm_set_wakeup_reason(WR_WAKE_SRC_ABNORMAL);
- }
- else
- {
- }
-}
-
-
-/**
- * cpu enter&resume interface code.
- *
- * sleep_type -- CPU_SLEEP_TYPE_LP1/CPU_SLEEP_TYPE_IDLE_LP2
- */
-u32 ap_susnpend_for_sleep_cnt =0;
-u32 ap_suspeend_for_poweroff_cnt =0;
-#ifdef CONFIG_PM_SLEEP
-void zx_enter_sleep(cpu_sleep_type_t sleep_type)
-{
-#ifdef CONFIG_ZX_PM_DEBUG_TIME
- pm_write_reg(SUSPEND_START_TIME_ADDR, zx_get_cur_time());
-#endif
-
- zx_set_context_level(sleep_type);
-
- /* set&enable PCU for interrupt/clock/powerdomain/pll/iram */
- zx_set_pcu();
-
-#ifdef CONFIG_ZX_PM_DEBUG
- pm_write_reg(AP_IDLE_SLEEP_STATUS_FLAG,0xff04);
-#endif
- if(CPU_SLEEP_TYPE_LP3 == sleep_type)
- {
-#ifdef CONFIG_ZX_PM_DEBUG
- ap_susnpend_for_sleep_cnt++;
-#endif
- zx_wdt_handle_before_psm();
- do_wfi();
-
- zx_wdt_handle_after_psm();
-
-#ifdef CONFIG_ZX_PM_DEBUG
- pm_write_reg(AP_IDLE_SLEEP_STATUS_FLAG,0xff05);
-#endif
-
- pm_get_wake_cause();
-
-#ifdef CONFIG_ZX_PM_DEBUG
- pm_write_reg(AP_SUSPEND_FOR_SLEEP_CNT,ap_susnpend_for_sleep_cnt);
-#endif
- }
- else
- {
-/*=================================================================
- *=== the following code is for dormant or shutdown
- *=================================================================
- */
- zx_wdt_handle_before_psm();
-#ifdef CONFIG_HAVE_HW_BREAKPOINT
- hw_breakpoint_context_save();
-#endif
- zx_pm_save_context();
-
-#ifdef CONFIG_ZX_PM_DEBUG
- pm_write_reg(AP_IDLE_SLEEP_STATUS_FLAG,0xff05);
-#endif
- if(!cpu_suspend(0, zx_finish_suspend))
- {
- zx_sleep_after_wfi();
- zx_pm_restore_context();
-#ifdef CONFIG_ZX_PM_DEBUG
- ap_suspeend_for_poweroff_cnt++;
- pm_write_reg(AP_SUSPEND_FOR_POWEROFF_CNT,ap_suspeend_for_poweroff_cnt);
- pm_write_reg(AP_IDLE_SLEEP_STATUS_FLAG,0xff06);
-#endif
- }
-
- zx_wdt_handle_after_psm();
-
- /*exit from sleep*/
- join_coherency();
-
- cpu_check_sleep_abort();
-/*=================================================================
- *=== ending with dormant or shutdown
- *=================================================================
- */
-
- /* get cause of exiting sleep */
- pm_get_wake_cause();
-#ifdef CONFIG_HAVE_HW_BREAKPOINT
- hw_breakpoint_restore_context();
-#endif //CONFIG_HAVE_HW_BREAKPOINT
- }
-#ifdef CONFIG_ZX_PM_DEBUG
- pm_write_reg(AP_IDLE_SLEEP_STATUS_FLAG,0xff07);
-#endif
-
- zx_clear_pcu();
-
-#ifdef CONFIG_ZX_PM_DEBUG_TIME
- suspend_finish_time = zx_get_cur_time();
- suspend_start_time =pm_read_reg(SUSPEND_START_TIME_ADDR);
-// pr_info("[SLP] suspend time: start:%d enter:%d total:%d\n",suspend_start_time, suspend_enter_time, suspend_start_time-suspend_enter_time);
-// pr_info("[SLP] suspend time: exit:%d finish:%d total:%d \n",suspend_exit_time, suspend_finish_time, suspend_exit_time-suspend_finish_time);
- pm_ram_log("####suspend start = [%u],end = [%u],time=[%u]\n",suspend_start_time,suspend_finish_time,(suspend_finish_time-suspend_start_time));
- pm_ram_log("####sleep time = [%u],sucess_cn=[%u],sucess_abort=[%u]\n",(suspend_exit_time-suspend_enter_time),suspendsuscess_cnt,suspendabort_cnt);
- pm_ram_log("####save time = [%u],restore time = [%u]\n",(pm_read_reg(SUSPEND_SAVE_TIME_ADDR)),(pm_read_reg(SUSPEND_RESTORE_TIME_ADDR)));
-#endif
-
-
-}
-#else
-void zx_enter_sleep(cpu_sleep_type_t sleep_type){}
-#endif
-
-/**
- * get wakeup reason .
- *
- *
- */
-pm_wake_reason_t pm_get_wakeup_reason(void)
-{
- return pm_wake_reason;
-}
-
-/**
- * set wakeup reason .
- *
- *
- */
-void pm_set_wakeup_reason(pm_wake_reason_t reason)
-{
- pm_wake_reason = reason;
-}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-sleep.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-sleep.h
deleted file mode 100644
index 4a1b76f..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx-sleep.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * zx-sleep.h - cpu sleep and wakeup interface.
- *
- * Written by zxp.
- *
- */
-
-#ifndef _ZX_SLEEP_H
-#define _ZX_SLEEP_H
-
-typedef enum
-{
- CPU_SLEEP_TYPE_NULL = 0,
- CPU_SLEEP_TYPE_LP1,
- CPU_SLEEP_TYPE_IDLE_LP2,
- CPU_SLEEP_TYPE_HOTPLUG_LP2,
- CPU_SLEEP_TYPE_LP3, /* maybe only for debug */
-} cpu_sleep_type_t;
-
-typedef enum
-{
- CPU_POWER_MODE_RUN = 0,
- CPU_POWER_MODE_STANDBY = 1,
- CPU_POWER_MODE_DORMANT = 2,
- CPU_POWER_MODE_SHUTDOWN = 3,
-} cpu_power_mode_t;
-
-typedef enum {
- WR_NONE = 0,
- WR_WAKE_SRC_NORMAL,
- WR_WAKE_SRC_UNKNOWN,
- WR_WAKE_SRC_ABNORMAL,
- WR_SW_ABORT,
-} pm_wake_reason_t;
-
-
-#define do_wfi() \
-do { \
- __asm__ __volatile__("isb" : : : "memory"); \
- __asm__ __volatile__("dsb" : : : "memory"); \
- __asm__ __volatile__("wfi" : : : "memory"); \
-} while (0)
-
-extern int zx_board_suspend(void);
-extern int zx_board_resume(void);
-extern int zx_dpm_suspend(void);
-extern int zx_dpm_resume(void);
-extern void zx_enter_sleep(cpu_sleep_type_t sleep_type);
-extern void cpu_start_restore(void);
-extern pm_wake_reason_t pm_get_wakeup_reason(void);
-extern void pm_set_wakeup_reason(pm_wake_reason_t reason);
-
-#endif /*_ZX_SLEEP_H*/
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-cpufreq.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-cpufreq.c
deleted file mode 100644
index 7eacfd7..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-cpufreq.c
+++ /dev/null
@@ -1,528 +0,0 @@
-/*
- * ZTE zx297510 dvfs driver
- *
- * Copyright (C) 2013 ZTE Ltd.
- * by zxp
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/cpufreq.h>
-#include <linux/suspend.h>
-
-#include <linux/soc/zte/rpmsg.h>
-//#include "mach/clock.h"
-#include <linux/miscdevice.h>
-#include <linux/uaccess.h>
-#include <linux/fs.h>
-#include "zx-pm.h"
-#define ZX_CPUFREQ_IOC_MAGIC 'W'
-
-/*ioctl cmd usd by device*/
-#define ZX_CPUFREQ_SET_FREQ _IOW(ZX_CPUFREQ_IOC_MAGIC, 1, char *)
-#define ZX_CPUFREQ_GET_FREQ _IOW(ZX_CPUFREQ_IOC_MAGIC, 2, char *)
-
-#define ZX_CPUFREQ_DEV "/dev/zx_cpufreq"
-
-#define PM_FREQ_TRACE 1
-#if PM_FREQ_TRACE
-
-#define FREQ_CHANGE_COUNT 20
-
-typedef struct
-{
- volatile unsigned int old_index;
- volatile unsigned int new_idex;
- volatile unsigned int time;
-}freq_change_view_trace_t;
-
-static freq_change_view_trace_t freq_change_view[FREQ_CHANGE_COUNT] ;
-static unsigned int freq_change_index = 0;
-static int cpufreq_driver_inited = 0;
-
-void trace_freq_change(unsigned int old_index,unsigned int new_index)
-{
- freq_change_view[freq_change_index].old_index = old_index;
- freq_change_view[freq_change_index].new_idex = new_index;
- freq_change_view[freq_change_index].time = ktime_to_us(ktime_get());
- freq_change_index++;
- if(freq_change_index == FREQ_CHANGE_COUNT)
- {
- freq_change_index = 0;
- }
-}
-#else
-void trace_freq_change(unsigned int old_index,unsigned int new_index){}
-#endif
-
-unsigned int freq_change_enabled_by_startup = 0;
-static struct delayed_work pm_freq_work;
-#define PM_FREQ_DELAY msecs_to_jiffies(25000)
-
-/* for count change time by M0 */
-#define DEBUG_CPUFREQ_TIME 1
-
-#ifdef CONFIG_DDR_FREQ
-#ifdef CONFIG_ARCH_ZX297520V2
-#define get_cur_ddr() pm_read_reg_16(AXI_CURRENT_FREQ)
-#define set_target_ddr(f) pm_write_reg_16(AXI_AP2M0_TARGET, f)
-#define set_ddr_req() pm_write_reg_16(AXI_AP2M0_FLAG, 1)
-#define clr_ddr_ack() pm_write_reg_16(AXI_M02AP_ACK, 0)
-
-#define wait_ddr_ack() while(!pm_read_reg_16(AXI_M02AP_ACK))
-#else
-static ddr_freq_regs *ddr_regs = (ddr_freq_regs *)IRAM_CHANGE_DDR_BASE;
-#define get_cur_ddr() (ddr_regs->cur_freq)
-#define set_target_ddr(f) (ddr_regs->ap_exp_freq = f)
-#define set_ddr_req() (ddr_regs->ap_req_flag = 1)
-
-#endif
-#endif
-
-//#undef CONFIG_AXI_FREQ
-#ifdef CONFIG_AXI_FREQ
-static DEFINE_MUTEX(axifreq_lock);
-
-static axi_freq_regs *axi_regs; // = (axi_freq_regs *)IRAM_CHANGE_AXI_BASE;
-static vol_dvs_regs *vol_regs; // = (vol_dvs_regs *)IRAM_CHANGE_DVS_BASE;
-
-#define get_cur_axi() (axi_regs->cur_freq)
-#define set_target_axi_sw(f) (axi_regs->ap_exp_freq = f)
-#define set_axi_req() (axi_regs->ap_req_flag = 1)
-
-#define get_target_axi_hw(addr) (pm_read_reg(addr)&(0x7))
-
-#if 1
-#define DDR_FREQ_156M_HW (0x4e)
-#define DDR_FREQ_208M_HW (0x68)
-#define DDR_FREQ_312M_HW (0x9c)
-#define DDR_FREQ_400M_HW (0xc8)
-
-#define set_ddr_freq_hw(addr,f) (pm_read_reg(addr)&(~0xff)|f)
-#define set_ddr_freq_sync(addr,f) (pm_read_reg(addr)&(~0x1)|f)
-#endif
-
-#define get_cur_vol() (vol_regs->cur_vol)
-#define set_target_vol(f) (vol_regs->ap_exp_vol = f)
-#define set_vol_req() (vol_regs->ap_req_flag = 1)
-
-#if 0
-#define WAIT_AXI_ACK_TIMEOUT (jiffies + msecs_to_jiffies(2)) /* wait 2 ms, we count max 200us also */
-#define wait_axi_ack(timeout) while(!pm_read_reg_16(AXI_M02AP_ACK) && time_before(jiffies, timeout))
-#else
-#define WAIT_AXI_ACK_TIMEOUT (200) /* wait 120us, we count max 200us also */
-static void wait_axi_ack(unsigned timeout)
-{
- ktime_t begin_time = ktime_get();
-
- while(((vol_regs->ap_req_flag) ||(axi_regs->ap_req_flag) )&& (unsigned)ktime_to_us(ktime_sub(ktime_get(), begin_time))<timeout);
-}
-#endif
-
-static int send_msg_to_m0(void)
-{
- unsigned int ap_m0_buf = AXI_VOL_CHANGE_ICP_BUF; /* the icp interface need a buffer */
- T_RpMsg_Msg Icp_Msg;
- int ret;
-
- Icp_Msg.coreID = CORE_M0;
- Icp_Msg.chID = 1;
- Icp_Msg.flag = RPMSG_WRITE_INT; /* 1- means send an icp interrupt> */
- Icp_Msg.buf = &ap_m0_buf;
- Icp_Msg.len = 0x4;
-
- ret = rpmsgWrite(&Icp_Msg);
- if(Icp_Msg.len == ret)
- return 0;
- else
- return ret;
-}
-
-static int axi_freq_change_allowed(void)
-{
- if(pm_get_mask_info()&PM_NO_AXI_FREQ)
- return false;
-
- return true;
-}
-
-/**
- * request to change vol.
- *
- * vol_dvs: input vol enum
- */
-int request_vol(zx29_vol vol_dvs)
-{
- unsigned int current_vol = get_cur_vol();
-
- set_target_vol(vol_dvs);
-#if DEBUG_CPUFREQ_TIME
- pm_printk("[CPUFREQ] current_vol(%d) request_vol(%d) \n",(u32)current_vol,(u32)vol_dvs);
-#endif
-
- if(vol_dvs != current_vol)
- {
- /* request freq */
- set_vol_req();
- }
-
- return 0;
-}
-
-/**
- * input axi freq.
- */
-static zx29_vol request_vol_by_axi(zx29_axi_freq axi_freq)
-{
- if(axi_freq == AXI_FREQ_156M)
- return VOL_VO_900;
- else
- return VOL_VO_850;
-}
-
-/**
- * set vol .
- *
- * we will do this by M0.
- */
-static int set_vol_by_axi(zx29_axi_freq axi_freq)
-{
- zx29_vol vol_dvs= request_vol_by_axi(axi_freq);
-
- /* set new vol*/
- return request_vol(vol_dvs);
-}
-
-
-/**
- * request to change axi freq.
- *
- * axi_freq: input freq enum
- */
-int request_axi_freq(zx29_axi_freq axi_freq)
-{
- unsigned int current_axi_freq = get_cur_axi();
- unsigned int tmp;
- int ret = 0;
-
-#if DEBUG_CPUFREQ_TIME
- ktime_t begin_time, end_time;
- s64 total_time;
-#endif
-
- if(!axi_freq_change_allowed())
- return 0;
-
-#ifdef SET_AXI_BY_HW
- tmp = (pm_read_reg(PS_MATRIX_AXI_SEL)&(~0x7))|axi_freq;
- pm_write_reg(PS_MATRIX_AXI_SEL,tmp);
- pm_printk("[CPUFREQ] current_axi_freq(%d) request_axi_freq(%d) after_request_axi_freq(%d) after_request_vol(%d)\n",(u32)current_axi_freq,(u32)axi_freq,get_cur_axi(),get_cur_vol());
-#else
- set_target_axi_sw(axi_freq);
-
- if(axi_freq != current_axi_freq)
- {
- /* request freq */
- set_axi_req();
-
-// set_vol_by_axi(axi_freq);//set vol
-
- ret = send_msg_to_m0();
-#if DEBUG_CPUFREQ_TIME
- begin_time = ktime_get();
-#endif
- if(!ret)
- {
- /* wait axi freq changed ok! we will set a timeout for safety~ */
- wait_axi_ack(WAIT_AXI_ACK_TIMEOUT);
- }
- else
- {
- pm_printk("[CPUFREQ] request_axi_freq(%d) failed: (%d) \n",(u32)axi_freq, ret);
- }
-
-#if DEBUG_CPUFREQ_TIME
- end_time = ktime_get();
- total_time = ktime_to_us(ktime_sub(end_time, begin_time));
- pm_printk("[CPUFREQ] total axi time: %d us current_axi_freq(%d) request_axi_freq(%d) after_request_axi_freq(%d) after_request_vol(%d)\n",(u32)total_time,(u32)current_axi_freq,(u32)axi_freq,get_cur_axi(),get_cur_vol());
- }
- else
- {
- pm_printk("[CPUFREQ] current_axi_freq(%d) request_axi_freq(%d) \n",(u32)current_axi_freq,(u32)axi_freq);
-#endif
- }
-#endif
-
- return 0;
-}
-
-
-/**
- * input cpu freq [KHz].
- */
-static zx29_axi_freq request_axi_freq_by_cpu(unsigned int freq)
-{
- if(freq >= 600*1000)
- return AXI_FREQ_156M;
- else
- return AXI_FREQ_78M;
-}
-
-/**
- * set axi freq .
- *
- * we will do this by M0.
- */
-static int set_axi_frequency_by_cpu(unsigned int freq)
-{
- zx29_axi_freq axi_freq = request_axi_freq_by_cpu(freq);
-
- /* set new freq */
- return request_axi_freq(axi_freq);
-}
-
-int zx_request_axi_freq(unsigned int axifreq)
-{
- zx29_axi_freq axi_freq;
-
- if (axifreq == 0xff)
- return -EINVAL;
-
- if(cpufreq_driver_inited==0)
- return -EPERM;
-
- if(axifreq >= 600*1000*1000)
- return AXI_FREQ_156M;
- else
- return AXI_FREQ_78M;
-
- return request_axi_freq(axi_freq);
-}
-
-#endif
-
-
-#ifdef CONFIG_AXI_FREQ
-/**
- * zx_axifreq_pm_notifier - acquire axifreq in suspend-resume context
- *
- * @notifier
- * @pm_event
- * @v
- *
- */
-
-static int zx_axifreq_pm_notifier(struct notifier_block *notifier,
- unsigned long pm_event, void *v)
-{
- mutex_lock(&axifreq_lock);
-
- switch (pm_event)
- {
- case PM_SUSPEND_PREPARE:
- request_axi_freq(AXI_FREQ_78M);
- break;
-
- case PM_POST_SUSPEND:
- request_axi_freq(AXI_FREQ_156M);
- break;
- }
-
- mutex_unlock(&axifreq_lock);
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block zx_axifreq_nb =
-{
- .notifier_call = zx_axifreq_pm_notifier,
-};
-
-static int __init zx29_axifreq_init(void)
-{
-
- /* pm notify */
- register_pm_notifier(&zx_axifreq_nb);
-// request_vol(VOL_VO_900);
- request_axi_freq(AXI_FREQ_156M);
-
- return 0;
-}
-
-//late_initcall(zx29_axifreq_init);
-#endif
-
-/*=============================================================================
- *======== zx29 DDR freq ===============================================
- *** ap/phy request --> m0 notify --> jump to iram --> wait completely --> ***
- *** -->jump to ddr ***====
- *=============================================================================
- */
-#ifdef CONFIG_DDR_FREQ
-static DEFINE_MUTEX(ddrfreq_lock);
-static int ddr_freq_change_allowed(void)
-{
- if(pm_get_mask_info()&PM_NO_DDR_FREQ)
- return false;
-
- return true;
-}
-
-static int send_msg_to_ps(void)
-{
- unsigned int ap_m0_buf = AXI_VOL_CHANGE_ICP_BUF; /* the icp interface need a buffer */
- T_ZDrvRpMsg_Msg Icp_Msg;
- int ret;
- Icp_Msg.actorID = PS_ID;
- Icp_Msg.chID = ICP_CHANNEL_PSM;
- Icp_Msg.flag = RPMSG_WRITE_INT; /* 1- means send an icp interrupt> */
- Icp_Msg.buf = &ap_m0_buf;
- Icp_Msg.len = 0x4;
- ret = zDrvRpMsg_Write(&Icp_Msg);
- if(Icp_Msg.len == ret)
- return 0;
- else
- return ret;
-}
-
-int request_ddr_freq_hw(unsigned int ddr_freq)
-{
- if(!ddr_freq_change_allowed())
- return 0;
- pm_write_reg(AP_DDR_FFC_SEL_SYNC,0x0);
- pm_write_reg(AP_DDR_FFC_SEL,ddr_freq);
- pm_write_reg(AP_DDR_FFC_SEL_SYNC,0x1);
- return 0;
-}
-
-int request_ddr_freq(zx29_ddr_freq ddr_freq)
-{
- int ret = 0;
- unsigned current_ddr_freq = get_cur_ddr();
- if(!ddr_freq_change_allowed())
- return 0;
-
- if(ddr_freq == current_ddr_freq)
- return 0;
-
-#ifdef SET_DDR_BY_HW
- //set_ddr_freq_hw(AP_DDR_FFC_SEL, ddr_exp_freq);
- set_ddr_freq_sync(AP_DDR_FFC_SEL_SYNC,0x1);
-#else
- set_target_ddr(ddr_freq);
- ret = send_msg_to_ps();
- if(!ret)
- {
- printk("[DDRFREQ] ddr_freq [%d]\n",get_cur_ddr());
- }
- else
- {
- printk("[DDRFREQ] request_ddr_freq failed\n");
- }
-#endif
-#if 0
- unsigned current_ddr_freq = get_cur_ddr();
- int ret = 0;
-
-#if DEBUG_CPUFREQ_TIME
- ktime_t begin_time, end_time;
- s64 total_time;
-#endif
-
- if(!ddr_freq_change_allowed())
- return 0;
-
- set_target_ddr(ddr_freq);
-
- if(ddr_freq != current_ddr_freq)
- {
- /* request freq */
- clr_ddr_ack();
- set_ddr_req();
-
-#if DEBUG_CPUFREQ_TIME
- begin_time = ktime_get();
-#endif
-
- ret = send_msg_to_m0();
- if(!ret)
- /* wait axi freq changed ok! we will set a timeout for safety~ */
- wait_ddr_ack();
- else
- pr_info("[CPUFREQ] request_ddr_freq(%d) failed: (%d) \n",(u32)ddr_freq, ret);
-
-#if DEBUG_CPUFREQ_TIME
- end_time = ktime_get();
- total_time = ktime_to_us(ktime_sub(end_time, begin_time));
- pr_info("[CPUFREQ] total ddr time: %d us\n",(u32)total_time);
-#endif
- }
-#endif
- return 0;
-}
-
-#ifdef CONFIG_ARCH_ZX297520V2
-static void ddr_freq_handler(void)
-{
- local_irq_disable();
- waiting_ddr_dfs((unsigned long)DDR_DFS_CODE_ADDR);
- local_irq_enable();
-}
-#else
-static int zx_ddrfreq_pm_notifier(struct notifier_block *notifier,
- unsigned long pm_event, void *v)
-{
- mutex_lock(&ddrfreq_lock);
- switch (pm_event)
- {
- case PM_SUSPEND_PREPARE:
- request_ddr_freq_hw(0);
- break;
- case PM_POST_SUSPEND:
- request_ddr_freq_hw(0x9c);
- break;
- }
- mutex_unlock(&ddrfreq_lock);
- return NOTIFY_OK;
-}
-static struct notifier_block zx_ddrfreq_nb =
-{
- .notifier_call = zx_ddrfreq_pm_notifier,
-};
-#endif
-
-static int __init zx29_ddrfreq_init(void)
-{
-#ifdef CONFIG_ARCH_ZX297520V2
-#else
- register_pm_notifier(&zx_ddrfreq_nb);
-#endif
- return 0;
-}
-
-#endif
-
-static void pm_m0_handler(void *buf, unsigned int len)
-{
- /* deal msg from m0 */
-}
-
-int zx29_cpufreq_init(void)
-{
- if(cpufreq_driver_inited)
- return 0;
-
- axi_regs = (axi_freq_regs *)IRAM_CHANGE_AXI_BASE;
- vol_regs = (vol_dvs_regs *)IRAM_CHANGE_DVS_BASE;
-
- cpufreq_driver_inited = 1;
-
- pr_info("[CPUFREQ] zx29_cpufreq_init ok \n");
- return 0;
-}
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-cpuidle.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-cpuidle.c
deleted file mode 100644
index cd1a1fa..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-cpuidle.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * zx297520v2 CPU idle Routines
- *
- * Copyright (C) 2013 ZTE, Ltd.
- * Shine Yu <yu.xiang5@zte.com.cn>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/sched.h>
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/cpu.h>
-#include <linux/tick.h>
-#include <linux/suspend.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-
-
-#include "zx-pm.h"
-
-#define WHOLE_CHIP_EXIT_LATENCY (4000) /* us */
-
-#define LP2_DEFAULT_EXIT_LATENCY (500 + WHOLE_CHIP_EXIT_LATENCY) /* us */
-#define LP2_MIN_POWER_OFF_TIME (500) /* us */
-
-#define LP2_DELTA_EXIT_LATENCY (100) /* us -- for timer setting refresh time, should > 2us.
- Donnot modify this. */
-
-static s64 zx_idle_sleeptime = 0xffffffff;
-static struct cpuidle_driver *cur_idle_drv;
-
-#ifdef CONFIG_ZX_PM_DEBUG
-//extern struct zx_idle_stats idle_stats;
-#endif
-
-/*===================================================================
- *========= idle states description ==============================
- *===================================================================
- *========= LP3 -- wfi(target_residency = 5) =============
- *========= LP1 -- pwroff(target_residency = 5000) =============
- *===================================================================
- */
-static struct cpuidle_state zx29_cpuidle_set[] __initdata =
-{
- /* LP3 -- wfi */
- [ZX_IDLE_CSTATE_LP3] =
- {
- .enter = zx_enter_idle,
- .exit_latency = 2,
- .target_residency = 5,
- .flags = 0,
- .name = "LP3",
- .desc = "clock gating(WFI)",
- },
- /* LP2 -- POWEROFF */
- [ZX_IDLE_CSTATE_LP2] =
- {
- .enter = zx_enter_idle,
- .exit_latency = LP2_DEFAULT_EXIT_LATENCY,
- .target_residency = LP2_DEFAULT_EXIT_LATENCY+LP2_MIN_POWER_OFF_TIME,
- .flags = 0,
- .name = "LP2",
- .desc = "POWEROFF",
- },
-};
-
-int __init zx_fill_cpuidle_data(struct cpuidle_driver *drv)
-{
- int i, max_cpuidle_state;
-
- max_cpuidle_state = sizeof(zx29_cpuidle_set) / sizeof(struct cpuidle_state);
-
- for (i = 0; i < max_cpuidle_state; i++)
- memcpy(&drv->states[i], &zx29_cpuidle_set[i], sizeof(struct cpuidle_state));
-
- drv->safe_state_index = ZX_IDLE_CSTATE_LP3;
-
- cur_idle_drv = drv;
-
- return max_cpuidle_state;
-}
-
-
-/**
- * idle_update_sleep_param
- *
- * when exit from one lp2 level sleep, update the exit_latency/target_residency.
- */
-/* our idle exit lattency may */
-#if 0
-static unsigned int lp2_exit_latencies[MAX_CPU_NUM];
-static void idle_update_sleep_param(void)
-{
-
-}
-#endif
-/**
- * idle_set_sleeptime
- *
- * set the wakeup timer
- *
- * sleep_time (us)
- */
-extern void setup_timer_wakeup(s64 us);
-void idle_set_sleeptime(s64 sleep_time)
-{
- /* set timer */
- setup_timer_wakeup(sleep_time);
-
- zx_idle_sleeptime = sleep_time;
-}
-
-/**
- * idle_get_sleeptime
- *
- * for PCU sleeptime
- */
-s64 idle_get_sleeptime(void)
-{
- return zx_idle_sleeptime;
-}
-
-/**
- * idle_unmask_interrupt
- *
- *
- */
-static void idle_unmask_interrupt(void)
-{
-}
-
-static void idle_unmask_interrupt_restore(void)
-{
-}
-
-static unsigned int idle_get_exit_latency(int index)
-{
- struct cpuidle_state* state = &(cur_idle_drv->states[index]);
-
- return state->exit_latency;
-}
-
-/**
- * When enter deep sleep the tick timer maybe stopped for
- * 26M osc will be closed. So we stop tick before entering
- * deep sleep and get sleeping time, then we restart the
- * tick(minus the sleeping time).
- */
-static u64 idle_enter_time = 0;
-static void idle_pre_enter(void)
-{
- pm_stop_tick();
-
- idle_enter_time = read_persistent_us();
-}
-
-static void idle_post_enter(s64 rem_us)
-{
- u64 cur_time = read_persistent_us();
- s64 delta;
- u64 max_persist_us;
-
- if(cur_time >= idle_enter_time)
- delta = cur_time - idle_enter_time;
- else
- {
- max_persist_us = div64_u64((u64)(0x7fffffff)*USEC_PER_SEC, (u64)PERSISTENT_TIMER_CLOCK_RATE);
- delta = max_persist_us - idle_enter_time + cur_time;
- }
-
- if(delta > rem_us + LP2_DELTA_EXIT_LATENCY)
- delta -= rem_us;
- else
- delta = LP2_DELTA_EXIT_LATENCY;
-
- pm_start_tick(delta);
-}
-
-#define PM_IDLE_TRACE 0
-#if PM_IDLE_TRACE
-
-#define TRACE_IDLE_COUNT 1000
-
-typedef struct
-{
- s64 request;
- s64 enter_remainder;
- s64 exit_remainder;
-}pm_idle_trace_t;
-
-volatile pm_idle_trace_t pm_idle_view[TRACE_IDLE_COUNT];
-volatile unsigned int pm_idle_index = 0;
-
-void trace_pm_idle_enter(s64 req_t, s64 remainder_t)
-{
- pm_idle_view[pm_idle_index].request = req_t;
- pm_idle_view[pm_idle_index].enter_remainder = remainder_t;
-}
-
-void trace_pm_idle_exit(s64 remainder_t)
-{
- pm_idle_view[pm_idle_index].exit_remainder = remainder_t;
-
- pm_idle_index++;
- if(pm_idle_index==TRACE_IDLE_COUNT)
- pm_idle_index=0;
-}
-#else
-void trace_pm_idle_enter(s64 req_t, s64 remainder_t){}
-void trace_pm_idle_exit(s64 remainder_t){}
-#endif
-
-/**
- * zx_enter_deep_idle
- *
- * enter lp2 mode
- */
- s64 sleep_time = 0;
- s64 request = 0;
- s64 remainder_timer = 0;
- s64 enter_deep_idle_enter_cnt =0;
- s64 enter_deep_idle_exit_cnt =0;
-static int zx_enter_deep_idle(int index)
-{
- bool sleep_completed = false;
- pm_wake_reason_t wake_reason;
- ktime_t delta_next;
-
-
-#ifdef CONFIG_ZX_PM_DEBUG
- ktime_t entry_time, exit_time;
- s64 idle_time;
- unsigned int cpu = read_cpuid();
-
- //idle_stats.cpu_ready_count[cpu]++;
- // idle_stats.tear_down_count[cpu]++;
-
- entry_time = ktime_get();
-#endif
- enter_deep_idle_enter_cnt++;
-
- //s64 sleep_time;
- /*s64 */request = ktime_to_us(tick_nohz_get_sleep_length(&delta_next));
- //s64 remainder_timer;
-
- /* */
- idle_unmask_interrupt();
-
- /* set wakeup timer */
- remainder_timer = pm_get_remainder_time();
- sleep_time = request - idle_get_exit_latency(index);
- if ((sleep_time > LP2_DELTA_EXIT_LATENCY) && (sleep_time < remainder_timer))
- idle_set_sleeptime(sleep_time);
- else
- return zx_pm_idle_enter(ZX_IDLE_CSTATE_LP3);
-
- trace_pm_idle_enter(request, remainder_timer);
-
- idle_pre_enter();
-
-#ifdef CONFIG_ZX_PM_DEBUG
- //idle_stats.lp2_count[cpu]++;
-#endif
-
- /* sleep */
- zx_enter_sleep(CPU_SLEEP_TYPE_LP3); /*ÐÞ¸ÄΪOFF/sleepģʽ*/
-
- enter_deep_idle_exit_cnt++;// tmp
- idle_post_enter(remainder_timer);
-
- remainder_timer = pm_get_remainder_time();
- trace_pm_idle_exit(remainder_timer);
-
- /* get wakeup cause */
- wake_reason = pm_get_wakeup_reason();
- if (wake_reason != WR_WAKE_SRC_ABNORMAL)
- {
- sleep_completed = true;
- }
- else
- {
-#ifdef CONFIG_ZX_PM_DEBUG
- int irq = 0;
- irq = zx29_gic_pending_interrupt();
- //idle_stats.lp2_int_count[irq]++;
-#endif
- }
-
- /* */
- idle_unmask_interrupt_restore();
-/*=================================================================
- *=======end enter deep sleep======================================
- *=================================================================
- */
-#ifdef CONFIG_ZX_PM_DEBUG
- exit_time = ktime_get();
- idle_time = ktime_to_us(ktime_sub(exit_time, entry_time));
-
- //idle_stats.cpu_wants_lp2_time[cpu] += idle_time;
- //idle_stats.in_lp2_time[cpu] += idle_time;
-
- //if (sleep_completed)
- //idle_stats.lp2_completed_count[cpu]++;
-#endif
-
- return index;
-}
-
-/**
- * zx_enter_lowpower - Programs cpu to enter the specified state
- * @dev: cpuidle device
- * @state: The target state to be programmed
- *
- * Called from the CPUidle framework to program the device to the
- * specified low power state selected by the governor.
- * Called with irqs off, returns with irqs on.
- * Returns the amount of time spent in the low power state.
- */
-int zx_pm_idle_enter(int index)
-{
-#ifdef CONFIG_ZX_PM_DEBUG
- //idle_stats.idle_count++;
-#endif
- if(ZX_IDLE_CSTATE_LP2 == index)
- {
- return zx_enter_deep_idle(index);
- }
- else
- {
-#ifdef CONFIG_ZX_PM_DEBUG
- unsigned cpu = read_cpuid();
- // idle_stats.lp3_count[cpu]++;
-#endif
- //gpio_direction_output(ZX29_GPIO_35, GPIO_HIGH);
- cpu_do_idle();
- //gpio_direction_output(ZX29_GPIO_35, GPIO_LOW);
- return ZX_IDLE_CSTATE_LP3;
- }
-}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-pm.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-pm.c
deleted file mode 100644
index 109c0ff..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-pm.c
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- * ZTE power management common driver
- *
- * Copyright (C) 2015 ZTE Ltd.
- * by zxp
- *
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/suspend.h>
-#include <linux/tick.h>
-
-#include "zx-pm.h"
-
-
-
-
-static unsigned int pm_enter_flag = false;
-
-unsigned int pm_get_sleep_flag(void)
-{
- return pm_enter_flag;
-}
-
-/**
- * config pcu before enter lp mode.
- *
- */
-void pm_set_pcu(void)
-{
- cpu_sleep_type_t sleep_type;
- u32 sleep_time;
-
- sleep_type = pm_get_sleep_type();
- sleep_time = pm_get_sleep_time();
-
- if(CPU_SLEEP_TYPE_LP1 == sleep_type)
- {
- pm_set_pcu_poweroff(sleep_time);
- }
- else if(CPU_SLEEP_TYPE_LP3 == sleep_type)
- {
- pm_set_pcu_sleep(sleep_time);
- }
- else
- WARN_ON(1);
-}
-
-/**
- * get sleep_time helper function.
- * used for idle sleep type.
- *
- * This code only used pm internel.
- *
- * return : unit is 26M cycle(38.4ns)
- * note: the max value is 0x7FFFFFFF (about 82.5s)
- */
-u32 pm_get_sleep_time(void)
-{
-#ifdef CONFIG_CPU_IDLE
- if(pm_enter_flag == false) {
- if(idle_get_sleeptime() >=(82500000) )
- return 0xffffffff;
- else
- return (u32)(idle_get_sleeptime()*26);
- }
- else
- return 0xffffffff;
-#else
- return 0xffffffff;
-#endif
-}
-
-/*=============================================================================
- *======== zx297520v2 CRM driver ===============================================
- *=============================================================================
- */
-typedef struct
-{
- /* 0x00 */ const volatile unsigned version;
- /* 0x04 */ volatile unsigned clkdiv;
- /* 0x08 */ volatile unsigned clken;
- char padding1[0x4];
- /* 0x10 */ volatile unsigned rsten;
- char padding2[0xC];
- /* 0x20 */ volatile unsigned gate_clk;
- char padding3[0x2C];
- /* 0x50 */ volatile unsigned int_mode[14];
-} crm_registers;
-
-typedef struct
-{
- unsigned int clkdiv;
- unsigned int clken;
- unsigned int rsten;
- unsigned int gate_clk;
- unsigned int int_mode[14];
-} crm_context;
-
-/**
- * save & restore CRM register interface for zx297520v2.
- *
- */
-void zx29_save_crm(u32 *pointer, u32 crm_base)
-{
-#ifdef CONFIG_ARCH_ZX297520V2 // 7520V2
- crm_registers *crm = (crm_registers *)crm_base;
- crm_context *context = (crm_context *)pointer;
-
- context->clkdiv = crm->clkdiv;
- context->clken = crm->clken;
- context->rsten = crm->rsten;
- context->gate_clk = crm->gate_clk;
- copy_words(context->int_mode, crm->int_mode, 14);
-#else
- pointer =copy_words(pointer,(volatile unsigned int*)(crm_base+0x78), 10); // 0x78-0xa0;
- pointer =copy_words(pointer,(volatile unsigned int*)(crm_base+0xB0), 1); // probe
-
-#endif
-}
-
-void zx29_restore_crm(u32 *pointer, u32 crm_base)
-{
-#ifdef CONFIG_ARCH_ZX297520V2 //7520V2
- crm_registers *crm = (crm_registers *)crm_base;
- crm_context *context = (crm_context *)pointer;
-
- crm->clkdiv = context->clkdiv;
- crm->clken = context->clken;
- crm->rsten = context->rsten;
- crm->gate_clk = context->gate_clk;
-
- copy_words(crm->int_mode, context->int_mode, 14);
-#else
- copy_words((volatile unsigned int*)(crm_base+0x78), (pointer), 10); // 0x78-0xa0;
- pointer += 10;
- copy_words((volatile unsigned int*)(crm_base+0xB0), (pointer), 1); // probe
- pointer += 1;
-#endif
-}
-
-/*=============================================================================
- *======== zx297520v2 PM&IDLE ==================================================
- *=============================================================================
- */
-static inline int pm_start_wake_timer(s64 us)
-{
- /* 1 cycle == 1/32768(s)*/
- /* max setting value = 0xffffffff/32768 = 131072s = 36h */
- unsigned long cycles = div64_long(us*32768, 1000000);
-
- zx29_set_wake_timer(cycles);
-
- return 0;
-}
-
-void setup_timer_wakeup(s64 us)
-{
- pm_start_wake_timer(us);
-}
-
-unsigned int zx29_gic_pending_interrupt(void)
-{
-#ifdef CONFIG_ARCH_ZX297520V2
- return gic_get_cur_pending((unsigned int)GIC_CPU_BASE);
-#else
- return gic_get_cur_pending((unsigned int)ZX_GICC_BASE);//fiy
-#endif
-}
-
-s64 pm_get_remainder_time(void)
-{
-#if 0 // zxp
- return div64_long(((s64)read_timer_clk(CLOCKEVENT_BASE))*1000000, EVENT_CLOCK_RATE);
-#else
- return 0;
-#endif
-}
-
-void pm_stop_tick(void)
-{
-#if 0 // zxp
- timer_stop(CLOCKEVENT_BASE);
-#endif
-}
-u32 pm_read_tick(void)
-{
-#if 0 // zxp
- return read_timer_clk(CLOCKEVENT_BASE);
-#else
- return 0;
-#endif
-}
-void pm_restart_tick(u32 cycles)
-{
-#if 0 // zxp
- timer_set_load(CLOCKEVENT_BASE,cycles);
- timer_start(CLOCKEVENT_BASE);
-#endif
-
-}
-
-void pm_start_tick(u64 us)
-{
-#if 0 // zxp
- unsigned long cycles = div64_long(us*EVENT_CLOCK_RATE, 1000000);
- struct clock_event_device *dev = __this_cpu_read(tick_cpu_device.evtdev);
- ktime_t expires;
-
-#if 0
- dev->set_next_event(cycles, dev);
-#else
- expires = ktime_add_ns(ktime_get(), us*1000);
- clockevents_program_event(dev, expires, 1);
-#endif
- timer_start(CLOCKEVENT_BASE);
-#endif
-}
-
-unsigned int pm_dma_used(void)
-{
-#ifdef CONFIG_ZX29_DMA
- return zx29_dma_get_status();
-#else
- return 0;
-#endif
-}
-
-/*=============================================================================
- *======== zx297520v2 DEBUG UART ===============================================
- *====== note: uart is in wakeup powerdomain =================================
- *=============================================================================
- */
-
-static struct zx_suspend_context suspend_context;
-
-
-void pm_mask_tick(void);
-void pm_unmask_tick(void);
-/* we use ap_timer1 as idle wakeup source when poweroff */
-void zx_pm_pre_suspend(void)
-{
-// setup_timer_wakeup(__SLEEP_TIME_1h__*18);//
- pm_mask_tick();
-
- pm_enter_flag = true;
-}
-
-void zx_pm_post_suspend(void)
-{
-// zx29_stop_wake_timer();
-
- pm_unmask_tick();
-
- pm_enter_flag = false;
-}
-
-static unsigned int at_command_read_flag = 0;
-static unsigned int pm_mask_info = 0;
-void pm_debug_mask_info_init(void)
-{
-// pm_mask_info = 0; /* should get value from iram */
- pm_get_mask_info();
- pm_ram_log("pm_mask_info=(%8lu)\n", pm_mask_info);
-}
-
-unsigned int pm_get_mask_info(void)
-{
- if(at_command_read_flag != AT_COMMAND_READ_FLAG)
- {
- at_command_read_flag = zx_read_reg(IRAM_AT_COMMAND_ADDR + 0x10);
- if(at_command_read_flag == AT_COMMAND_READ_FLAG)
- {
- pm_mask_info = zx_read_reg(IRAM_AT_COMMAND_ADDR + 0x4);
- if((zx_read_reg(IRAM_AT_COMMAND_ADDR)&PM_ALL_NO_SLEEP)||(pm_mask_info&PM_NO_SLEEP))//AP²»½ø˯ÃßÁ÷³Ì
- {
- pm_mask_info |= PM_IDLE_WFI;
- }
- }
- }
-
- return pm_mask_info;
-}
-
-bool pm_disable_suspend(void)
-{
- return (pm_get_mask_info()&PM_NO_SUSPEND);
-}
-
-void pm_init_acs(void)
-{
-#ifdef CONFIG_ARCH_ZX297520V2
- zx_set_reg(AP_CORE_SEL_ADDR, L2_STOPPED_SEL_EN|CORE_ACS_CLK_SEL_EN);
-#else
- //zx_clr_reg(AP_CORE_CLK_GATE_ADDR, AP_PROBE_GATE_EN|AP_PMC_GTAE_EN|AP_PROBE_BYPASS_EN);
- // zx_set_reg(AP_CORE_SEL_ADDR, CORE_ACS_CLK_SEL_EN);
-
- /*Ö§³ÖACS clk sel default 26M*/
- //zx_set_reg(AP_CORE_SEL_ADDR, /*L2_STOPPED_SEL_EN|*/CORE_ACS_CLK_SEL_EN);
- /* clk×Ô¶¯ÃÅ¿Ø*/
- //zx_set_reg(AP_AXI_CLKEN_ADDR, AP_TODDR_CLKEN_AUTO|AP_TOMATRIX_CLKEN_AUTO);
-#endif
-}
-
-u64 read_persistent_us(void)
-{
- struct timespec64 ts;
- u64 temp;
-
- read_persistent_clock64(&ts);
- temp = timespec64_to_ns(&ts);
- do_div(temp, 100);
-
- return temp;
-}
-
-struct zx_pm_ctx pm_ctx = {0};
-void pm_init_resource(void)
-{
- pm_ctx.gic_dist_base = ioremap(0xF2000000 ,0x40000);
- pm_ctx.gic_redist_base = ioremap(0xF2040000 ,0x40000);
- pm_ctx.gicc_base = ioremap(0x02900000 ,0x100000);
- pm_ctx.iram1_base = ioremap(0x100000 ,64*1024);
- pm_ctx.ap_peri_base = ioremap(0xF2200000 ,64*0x100000);
- pm_ctx.ap_crm_base = pm_ctx.ap_peri_base + 0x2000;
- pm_ctx.matrix_crm_base = get_stdcrm_base();
-}
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-pm.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-pm.h
deleted file mode 100644
index 02a1bb7..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/power/zx29-pm.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * zx297520v2-pm.h - zx297520v2 power management interface.
- *
- * Written by zxp.
- *
- */
-
-#ifndef _ZX29_PM_H
-#define _ZX29_PM_H
-
-#define GIC_DIST_BASE (pm_ctx.gic_dist_base)
-#define GIC_REDIST_BASE (pm_ctx.gic_redist_base)
-#define ZX_GICC_BASE (pm_ctx.gicc_base)
-#define ZX_IRAM1_BASE (pm_ctx.iram1_base)
-#define ZX29_IRAM1_PHYS (0x100000)
-#define AP_CRM_BASE (pm_ctx.ap_crm_base)
-#define AP_PERI_BASE (pm_ctx.ap_peri_base)
-#define ZX29_AP_PERIPHERAL_PHYS (0xF2200000)
-#define ZX_MATRIX_CRM_BASE (pm_ctx.matrix_crm_base)
-
-
-#define PERSISTENT_TIMER_CLOCK_RATE (32768)
-
-
-#define pm_reg_sync_write zx_reg_sync_write
-#define pm_read_reg zx_read_reg
-#define pm_write_reg zx_write_reg
-#define pm_set_reg zx_set_reg
-#define pm_clr_reg zx_clr_reg
-#define pm_reg_sync_write_16 zx_reg_sync_write_16
-#define pm_read_reg_16 zx_read_reg_16
-#define pm_write_reg_16 zx_write_reg_16
-
-#define ZX_A9_PERIPHERAL_PHYS (ZX29_A9_PERIPHERAL_PHYS)
-#define A9_CRM_PHYS (ZX_A9_PERIPHERAL_PHYS + 0x3000)
-#define ZX_L2CACHE_CONFIG_PHYS (ZX29_L2CACHE_CONFIG_PHYS)
-
-#define INVALID_INT_NUM (0xFFFF)
-
-#define __SLEEP_TIME_1s__ ((s64)(1000000))
-#define __SLEEP_TIME_1m__ (__SLEEP_TIME_1s__*60)
-#define __SLEEP_TIME_1h__ (__SLEEP_TIME_1m__*60)
-#define __MAX_SLEEP_TIME__ (__SLEEP_TIME_1h__*18)
-
-/* iram1 is for axi_freq and debug, data will not lost when system died */
-/*===================================================================
- *== iram1 address allocation =====================================
- *===================================================================
- *========= 0x2000 ~~ 0x2FFF : AP debug ram ===================
- *========= 0x3000 ~~ 0x37FF : common use ===================
- *========= 0x30A0 ~~ 0x30AF : at command ===================
- *========= 0x3140 ~~ 0x316F : ddr freq area ===================
- *========= 0x3170 ~~ 0x318F : axi freq area ===================
- *========= 0x3190 ~~ 0x31bF : dvs area ===================
- *===================================================================
- */
-
-#define IRAM_PM_BASE (ZX_IRAM1_BASE + 0x2000) /*0x00102000*/
-
-#define IRAM_AP_DEBUG_ADDR (IRAM_PM_BASE + 0x400) /*0x00102400/0x00100400*/
-
-#define IRAM_AP_DEBUG_LEN (0x1000)/*4K*/
-
-
-#define IRAM_COMMON_USE_ADDR (ZX_IRAM1_BASE + 0x1000)/*0x00101000 for psm flag*/
-
-//#define IRAM_COMMON_USE_LEN (0x800)
-
-#define IRAM_PS_SLEEP_FLAG_ADDR (IRAM_COMMON_USE_ADDR + 0x30)
-#define IRAM_AT_COMMAND_ADDR (IRAM_COMMON_USE_ADDR + 0xA0)
-#define IRAM_AP_DRV_FLAG_BASE (IRAM_COMMON_USE_ADDR + 0x58) /* USB FLAG TO PROXY */
-
-#define IRAM_CHANGE_DDR_BASE (IRAM_COMMON_USE_ADDR + 0x140)
-#define IRAM_CHANGE_AXI_BASE (IRAM_COMMON_USE_ADDR + 0x180)
-#define IRAM_CHANGE_DVS_BASE (IRAM_COMMON_USE_ADDR + 0x1a0) /* TBD */
-
-#define AP_SUSPEND_FOR_POWEROFF_CNT (IRAM_COMMON_USE_ADDR + 0x114)
-#define AP_SLEEP_TIME_ADDR (IRAM_COMMON_USE_ADDR + 0x134)
-
-/*test flag*/
-#define IRAM_ADDR_FOR_SLEEP_CNT (IRAM_AP_DEBUG_ADDR + 0x0)
-#define IRAM_ADDR_FOR_WAKE_CNT (IRAM_AP_DEBUG_ADDR + 0x4)
-#define SLEEP_TIME_ADDR (IRAM_AP_DEBUG_ADDR + 0x8)//(SYSTEM_WAKEUP_ADDR + 0x8)
-#define AP_SUSPEND_STATUS_FLAG (IRAM_AP_DEBUG_ADDR + 0xC)
-#define AP_SUSPEND_FOR_SLEEP_CNT (IRAM_AP_DEBUG_ADDR + 0x10)
-#define AP_IDLE_SLEEP_STATUS_FLAG (IRAM_AP_DEBUG_ADDR + 0x14)
-
-
-
-//#define SUSPEND_START_TIME_ADDR (IRAM_AP_DEBUG_ADDR + 0x10)
-//#define SUSPEND_SAVE_TIME_ADDR (IRAM_AP_DEBUG_ADDR + 0x14)
-//#define SUSPEND_RESTORE_TIME_ADDR (IRAM_AP_DEBUG_ADDR + 0x18)
-
-/*
- * flag : m0 set 0 when get request, ap set 1 to request m0
- * target : ap axi target, defined by zx297510_axi_freq
- * cur : current axi freq, defined by zx297510_axi_freq
- * ack : m0 set 1 when done request, ap set 0 before new request
-**/
-typedef struct
-{
- /* 0x00 */ volatile unsigned int ps_req_flag;
- /* 0x04 */ volatile unsigned int ps_exp_freq;
-
- /* 0x08 */ volatile unsigned int phy_req_flag;
- /* 0x0C */ volatile unsigned int phy_exp_freq;
-
- /* 0x10 */ volatile unsigned int ap_req_flag;
- /* 0x14 */ volatile unsigned int ap_exp_freq;
-
- /* 0x18 */ volatile unsigned int cur_freq;
-
-}axi_freq_regs;
-
-typedef struct
-{
- /* 0x00 */ volatile unsigned int ps_req_flag;
- /* 0x04 */ volatile unsigned int ps_exp_vol;
-
- /* 0x08 */ volatile unsigned int phy_req_flag;
- /* 0x0C */ volatile unsigned int phy_exp_vol;
-
- /* 0x10 */ volatile unsigned int ap_req_flag;
- /* 0x14 */ volatile unsigned int ap_exp_vol;
-
- /* 0x18 */ volatile unsigned int cur_vol;
-
-}vol_dvs_regs;
-
-typedef struct
-{
- /* 0x00 */ volatile unsigned int ps_req_flag;
- /* 0x04 */ volatile unsigned int ps_ack_flag;
- /* 0x08 */ volatile unsigned int ps_exp_freq;
-
- /* 0x0C */ volatile unsigned int phy_req_flag;
- /* 0x10 */ volatile unsigned int phy_ack_flag;
- /* 0x14 */ volatile unsigned int phy_exp_freq;
-
- /* 0x18 */ volatile unsigned int ap_req_flag;
- /* 0x1C */ volatile unsigned int ap_ack_flag;
- /* 0x20 */ volatile unsigned int ap_exp_freq;
-
- /* 0x24 */ volatile unsigned int cur_freq;
- /* 0x28 */ volatile unsigned int status;
-}ddr_freq_regs;
-
-/* pm mask flag for test */
-#define AT_COMMAND_READ_FLAG (0x49435001)
-#define AXI_VOL_CHANGE_ICP_BUF (0x49435002)
-
-#define PM_ALL_NO_SLEEP (0x1)
-#define PM_NO_SLEEP (0x1)
-#define PM_IDLE_WFI (0x1)
-#define PM_SLEEP_FLAG_PRINT (0x200)
-#define PM_NO_SUSPEND (0x40000)
-#define PM_SUSPEND_WFI (0x80000)
-#define PM_NO_AXI_FREQ (0x100000)
-
-/*===================================================================
- *== iram address allocation ======================================
- *===================================================================
- *========= 0 ~~ 0x1FF : wakeup code area ===================
- *========= 0x200 ~~ 0x27F : code area_1 ===================
- *========= 0x280 ~~ 0x2ff : code area_2 ===================
- *========= 0x300 ~~ 0x33f : debug area ===================
- *========= 0x340 ~~ 999 : reserved[0] ===================
- *========= 1000 ~~ 1003 : code addr[0] ===================
- *========= 1004 ~~ 1023 : reserved[1] ===================
- *===================================================================
- */
-#define ioremap_mem(cookie,size) __arm_ioremap((cookie), (size), MT_MEMORY)
-
-#define SYSTEM_WAKEUP_ADDR (ZX29_IRAM1_PHYS + 0x2000)//cap
-
-#define WAKEUP_CODE_LENGTH (0x200)
-#define SLEEP_CODE_LENGTH (0x80)
-#define DDR_DFS_CODE_LENGTH (0x80)
-
-typedef struct
-{
- /* 0x000 */ unsigned char wakeup_code[WAKEUP_CODE_LENGTH];
- /* 0x200 */ unsigned char sleep_code[SLEEP_CODE_LENGTH];
- /* 0x280 */ unsigned char ddr_dfs_code[DDR_DFS_CODE_LENGTH];
- /* 0x300 */ char padding1[1000-0x300];
- /* 1000 */ unsigned int reset_handler_vaddr;
- /* 1004 */ char padding2[20];
-} wakeup_ram_area;
-
-#define AP_CORE_SEL_ADDR (ZX_MATRIX_CRM_BASE + 0x40)
-
-#define CORE_ACS_CLK_SEL_EN (1<<8)
-#ifdef CONFIG_ARCH_ZX297520V2
-#define L2_STOPPED_SEL_EN (1<<9) /*a53 not has*/
-#else
-#define AP_AXI_CLKEN_ADDR (ZX_MATRIX_CRM_BASE + 0x44)
-#define AP_TODDR_CLKEN_AUTO (1<<5)
-#define AP_TOMATRIX_CLKEN_AUTO (1<<4)
-
-#define PS_MATRIX_AXI_SEL (ZX_MATRIX_CRM_BASE + 0x120)
-#define AP_MATRIX_AXI_SEL (ZX_MATRIX_CRM_BASE + 0x124)
-#define AP_DDR_FFC_SEL (ZX_DDR_FFC_BASE + 0x220)
-#define AP_DDR_FFC_SEL_SYNC (ZX_DDR_FFC_BASE + 0x210)
-
-
-
-
-#define AP_CORE_CLK_GATE_ADDR (AP_CRM_BASE+0xB0)
-#define AP_PROBE_GATE_EN (1<<8)
-#define AP_PMC_GTAE_EN (1<<3)
-#define AP_PROBE_BYPASS_EN (1<<15)
-#endif
-
-/* copied from zx29_uart.h */
-#define ZX29_UART0_VA (ZX_UART0_BASE)
-#define ZX29_UART1_VA (ZX_UART1_BASE)
-
-#define ZX29_UART_IBRD 0x24 /* Integer baud rate divisor register. */
-#define ZX29_UART_FBRD 0x28 /* Fractional baud rate divisor register. */
-#define ZX29_UART_LCRH 0x30 /* Line control register. */
-#define ZX29_UART_CR 0x34 /* Control register. */
-#define ZX29_UART_IFLS 0x38 /* Interrupt fifo level select. */
-#define ZX29_UART_IMSC 0x40 /* Interrupt mask. */
-#define ZX29_UART_ICR 0x4c /* Interrupt clear register. */
-#define ZX29_UART_DMACR 0x50 /* DMA control register. */
-
-/*------ uart control reg -----*/
-#define UART_CR_CTSEN (1<<15) /* CTS hardware flow control */
-#define UART_CR_RTSEN (1<<14) /* RTS hardware flow control */
-#define UART_CR_OUT2 (1<<13) /* OUT2 */
-#define UART_CR_OUT1 (1<<12) /* OUT1 */
-#define UART_CR_RTS (1<<11) /* RTS */
-#define UART_CR_DTR (1<<10) /* DTR */
-#define UART_CR_RXE (1<<9) /* receive enable */
-#define UART_CR_TXE (1<<8) /* transmit enable */
-#define UART_CR_LBE (1<<7) /* loopback enable */
-#define UART_CR_SIRLP (1<<2) /* SIR low power mode */
-#define UART_CR_SIREN (1<<1) /* SIR enable */
-#define UART_CR_UARTEN (1<<0) /* UART enable */
-
-struct zx_uart_context
-{
- unsigned int ibrd; /*0x24 Integer baud rate divisor register. */
- unsigned int fbrd; /*0x28 Fractional baud rate divisor register. */
- unsigned int lcrh; /*0x30 Line control register. */
- unsigned int cr; /*0x34 Control register. */
- unsigned int ifls; /*0x38 Interrupt fifo level select. */
- unsigned int imsc; /*0x40 Interrupt mask. */
- unsigned int dmacr; /*0x50 DMA control register. */
-};
-
-struct zx_timer_context
-{
- unsigned int cfg; /*0x04 config register. */
- unsigned int load; /*0x08 load register. */
- unsigned int start; /*0x0C timer start register. */
- unsigned int count; /*0x18 current counter register. */
-};
-
-/* for device or sw to restore */
-struct zx_suspend_context
-{
- struct zx_uart_context uart;
- struct zx_timer_context timer;
-};
-
-struct zx_pm_ctx {
- void __iomem *gic_dist_base;
- void __iomem *gic_redist_base;
- void __iomem *gicc_base;
- void __iomem *iram1_base;
- void __iomem *ap_peri_base;
- void __iomem *ap_crm_base;
- void __iomem *matrix_crm_base;
-};
-
-extern struct zx_pm_ctx pm_ctx;
-
-/*used as pm common interface*/
-void pm_set_pcu(void);
-
-extern void zx29_save_crm(u32 *pointer, u32 crm_base);
-extern void zx29_restore_crm(u32 *pointer, u32 crm_base);
-
-extern void pm_stop_tick(void);
-extern u32 pm_read_tick(void);
-extern void pm_restart_tick(u32 cycles);
-extern void pm_start_tick(u64 us);
-extern s64 pm_get_remainder_time(void);
-extern void setup_timer_wakeup(s64 us);
-extern void zx29_set_wake_timer(unsigned long cycles);
-extern void zx29_stop_wake_timer(void);
-extern u64 read_persistent_us(void);
-extern unsigned int pm_dma_used(void);
-
-extern unsigned pm_get_wakeup_int_no(void);
-extern char * pm_get_wakeup_int_name(void);
-extern void pm_get_wake_cause(void);
-extern unsigned int pm_get_wakesource(void);
-
-extern void __iomem *debug_uart_base(void);
-extern void debug_uart_suspend(void);
-extern void debug_uart_resume(void);
-
-extern void pm_timer_suspend(void);
-extern void pm_timer_resume(void);
-
-extern void zx_pm_pre_suspend(void);
-extern void zx_pm_post_suspend(void);
-
-#define zx_set_pcu pm_set_pcu
-#define zx_clear_pcu pm_clear_pcu
-
-#define save_crm zx29_save_crm
-#define restore_crm zx29_restore_crm
-
-#define zx_unmask_wakeup_interrupt()
-#define zx_interrupt_mask_restore()
-
-extern void pm_debug_mask_info_init(void);
-extern unsigned int pm_get_mask_info(void);
-
-void pm_init_acs(void);
-void pm_init_resource(void);
-unsigned int zx29_gic_pending_interrupt(void);
-void zx_apmgclken_set(unsigned en);
-int zx29_cpufreq_init(void);
-
-#endif /*_ZX297520V2_PM_H*/
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/Kconfig b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/Kconfig
deleted file mode 100644
index 69f818a..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# rpmsg options
-#
-config ZTE_RPMSG
- bool "zte remote processor message support(rpmsg)"
- depends on ARCH_ZX298501 || ARCH_ZX2AA800 || ARCH_ZX297520V3
-
-config ZX29_ICP
- bool "zx29 icp support"
- depends on ZTE_RPMSG
- depends on ARCH_ZX298501 || ARCH_ZX297520V3
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/Makefile b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/Makefile
deleted file mode 100644
index 9490f7b..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the rpmsg drivers
-#
-
-obj-$(CONFIG_ZTE_RPMSG) += icp_rpmsg.o icp_rpmsg_linux.o icp_test.o icp_dev.o rpmsg.o
-obj-$(CONFIG_ZX29_ICP) += zx29_icp.o
-
-#
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/hal_icp_i.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/hal_icp_i.h
deleted file mode 100644
index bc57a8b..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/hal_icp_i.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*---------------------------------------------------------------------------------------------------------------------
- * °æȨËùÓÐ(C)2000-2010, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾
- *
- * ÎÄ ¼þ Ãû: hal_icp_i.h
- *
- * ×÷ Õß: 00081983
- *
- * ½Ó¿ÚÃèÊö:
- * ICPÄ£¿éDRV²ãµÄÄÚ²¿Í·Îļþ
- *
- * °æ ±¾: v0.0
- *
- * ------------------------------------------------------------------------------------------------------------------
- *
- * ÐÞ¸ÄÈÕÆÚ ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
- * @li 20110518 00081983 ´´½¨
- *
- *-------------------------------------------------------------------------------------------------------------------*/
-
-/**
- * @addtogroup HAL_ICP_I
- * @{
- */
-
-#ifndef _HAL_ICP_I_H
-#define _HAL_ICP_I_H
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-
-/** ICPÄ£¿éDRV²ãµ÷ÊÔ¿ª¹Øºê */
-#define HAL_ICP_DEBUG
-
-
-
-#if 1 /* ´óС¶Ë˳Ðòת»» */
-#define HAL_ICP_ENDIAN_SWAP(x) (UINT32)( (((x) >> 24) & 0xFF) \
- | ((((x) >> 16) & 0xFF) << 8) \
- | ((((x) >> 8) & 0xFF) << 16) \
- | (((x) & 0xFF) << 24) \
- )
-#else
-#define HAL_ICP_ENDIAN_SWAP(x) (x)
-#endif
-
-
-
-/* ¼Ä´æÆ÷λÓò²Ù×÷ */
-
-/* Ϊij¸ö×Ö¶ÎÉèÖÃij¸öÖµ£¬ÆäËû×Ö¶ÎΪ0 (the Field MaKe macro) */
-#define HAL_FMK(PER_REG_FIELD, val) \
- (((val) << PER_REG_FIELD##_POS) & PER_REG_FIELD##_MASK)
-
-/* ÌáÈ¡¼Ä´æÆ÷ij¸ö×ֶεÄÖµ(the Field EXTract macro) */
-#define HAL_FEXT(reg, PER_REG_FIELD) \
- (((reg) & PER_REG_FIELD##_MASK) >> PER_REG_FIELD##_POS)
-
-/* ÔڼĴæÆ÷ij¸ö×ֶβåÈëij¸öÖµ£¬ÆäËû×ֶεÄÖµ±£³Ö²»±ä(the Field INSert macro) */
-#define HAL_FINS(reg, PER_REG_FIELD, val) \
- ((reg) = ((reg) & ~PER_REG_FIELD##_MASK) \
- | HAL_FMK(PER_REG_FIELD, val))
-
-
-/* ¼Ä´æÆ÷µ¥bitλ²Ù×÷ */
-
-/* ijbitÖÃ룬ÆäËübit²»±ä */
-#define HAL_BIT_SET(reg, bit) ((reg) = ((reg) | (1u << (bit))))
-
-/* ijbitÇåÁ㣬ÆäËübit²»±ä */
-#define HAL_BIT_CLEAR(reg, bit) ((reg) = ((reg) & (~(1u << (bit)))))
-
-/* »ñȡijbitµÄÖµ (0/1) */
-#define HAL_GET_BIT_VAL(reg, bit) (((reg)>> (bit)) & 1u)
-
-/* ÅжÏijbitµÄÖµÊÇ·ñΪ1 */
-#define HAL_IS_BIT_SET(reg, pos) (((reg) & (1u << (pos))) != 0x0u)
-
-/* ÅжÏijbitµÄÖµÊÇ·ñΪ0 */
-#define HAL_IS_BIT_CLEAR(reg, pos) (((reg) & (1u << (pos))) == 0x0u)
-
-/* ijbitλÌîдֵval,ÆäËûbit²»±ä */
-#define HAL_BIT_INSR(reg, bit, val) \
- ((reg) = (((reg) & (~(1u << (bit)))) | (((val) & 1u) << (bit))))
-
-
-
-
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-
-#endif /* _HAL_ICP_I_H */
-
-/** @} */
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp.h
deleted file mode 100644
index 0a813a7..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*---------------------------------------------------------------------------------------------------------------------
- * °æȨËùÓÐ(C)2000-2017, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾
- *
- * ÎÄ ¼þ Ãû: icp.h
- *
- *
- * ½Ó¿ÚÃèÊö:
- * ICPÄ£¿éµÄ¼Ä´æÆ÷Í·Îļþ
- *
- * °æ ±¾: v0.0
- *
- *
- *-------------------------------------------------------------------------------------------------------------------*/
-
-
-#ifndef _ICP_H
-#define _ICP_H
-
-#ifdef CONFIG_ZX298501_ICP
-#include "zx298501_icp.h"
-#endif
-
-#endif /* _ICP_H */
-
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_dev.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_dev.c
deleted file mode 100644
index 5157ad5..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_dev.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/**
- * @file icp_dev.c
- * @sub-layer between rpmsg and icp driver
- *
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * @author Qing Wang
- * @ingroup
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- */
-
-/*******************************************************************************
- * Include header files *
-
- ******************************************************************************/
-#include "icp_rpmsg.h"
-#include "icp_dev.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-static t_icpdev_ops *icpdev_ops;
-
-/**-------------------------------------------------------------------------------------------------------------------@n
- * @brief Ô´ºËÏòÄ¿±êºË·¢ËÍÏûÏ¢¡£
- *
- *
- *--------------------------------------------------------------------------------------------------------------------*/
-int icpdev_send_message(u32 actor_id, icp_msg *icp_msg)
-{
- int ret = -ENODEV;
-
- if (icpdev_ops)
- ret = icpdev_ops->send_message(actor_id, icp_msg);
-
- return ret;
-}
-
-int icpdev_mask_int(T_RpMsg_CoreID actor_id, T_RpMsg_ChID ch_id)
-{
- int ret = -ENODEV;
-
- if (icpdev_ops)
- ret = icpdev_ops->mask_int(actor_id, ch_id);
-
- return ret;
-}
-
-int icpdev_set_int(T_RpMsg_CoreID actor_id, T_RpMsg_ChID ch_id)
-{
- int ret = -ENODEV;
-
- if (icpdev_ops)
- ret = icpdev_ops->set_int(actor_id, ch_id);
-
- return ret;
-}
-
-int icpdev_unmask_int(T_RpMsg_CoreID actor_id, T_RpMsg_ChID ch_id)
-{
- int ret = -ENODEV;
-
- if (icpdev_ops)
- ret = icpdev_ops->unmask_int(actor_id, ch_id);
-
- return ret;
-}
-
-void icpdev_register_callback(icp_callback_fn cb)
-{
- if (icpdev_ops)
- icpdev_ops->register_callback(cb);
-}
-
-void icpdev_register_ops(t_icpdev_ops *ops)
-{
- icpdev_ops = ops;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_dev.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_dev.h
deleted file mode 100644
index 162e8e2..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_dev.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*---------------------------------------------------------------------------------------------------------------------
- * °æȨËùÓÐ(C)2000-2017, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾
- *
- * ÎÄ ¼þ Ãû: icp_dev.h
- *
- *
- * ½Ó¿ÚÃèÊö:
- * ICP device interface
- *
- * °æ ±¾: v0.0
- *
- *
- *-------------------------------------------------------------------------------------------------------------------*/
-
-
-#ifndef _ICP_DEV_H
-#define _ICP_DEV_H
-
-#include "icp_rpmsg_osa.h"
-#include <linux/soc/zte/rpmsg.h>
-
-typedef void (*icp_callback_fn)(void *data);
-
-typedef struct
-{
- u32 src_id;
- u32 event_id;
- u32 dest_core;
-} icp_msg;
-
-/*
-* this struct presents the operation method
-* and state of interrupt controller chip
-*/
-typedef struct _t_icpdev_ops
-{
- void (*register_callback)(icp_callback_fn cb);
- int (*set_int)(T_RpMsg_CoreID actor_id, T_RpMsg_ChID ch_id);
- int (*mask_int)(T_RpMsg_CoreID actor_id, T_RpMsg_ChID ch_id);
- int (*unmask_int)(T_RpMsg_CoreID actor_id, T_RpMsg_ChID ch_id);
- int (*send_message)(unsigned int actor_id, icp_msg *icp_msg);
-} t_icpdev_ops;
-
-void icpdev_register_callback(icp_callback_fn cb);
-int icpdev_send_message(unsigned int actor_id, icp_msg *icp_msg);
-void icpdev_register_ops(t_icpdev_ops *ops);
-int icpdev_set_int(T_RpMsg_CoreID actor_id, T_RpMsg_ChID ch_id);
-int icpdev_unmask_int(T_RpMsg_CoreID actor_id, T_RpMsg_ChID ch_id);
-
-#endif /* _ICP_DEV_H */
-
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg.c
deleted file mode 100644
index 2e010b9..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg.c
+++ /dev/null
@@ -1,857 +0,0 @@
-/**
- * @file icp_rpmsg.c
- * @brief
- *
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * @author Qing Wang
- * @ingroup
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- */
-
-/*******************************************************************************
- * Include header files *
-
- ******************************************************************************/
-#include "icp_rpmsg.h"
-#include "icp_dev.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define RPMSG_ALIGN 0x4
-#define ALIGN_RPMSG(size,align) (((unsigned int)size + align - 1)&(~(align - 1)))
-#define RPMSG_MSGHEAD_FLAG 0x5453
-#define RPMSG_BUFFER_LEN 512
-
-#define CUR_SEND_POS(coreID, chanID) rpmsgConfig[coreID].send_pos[chanID]
-
-const int Icp_rpmsg_actor = CORE_AP;
-rpmsg_sema rpmsgProcSem;
-T_RpMsg_CoreConfig rpmsgConfig[CORE_MAXID] = {0};
-static bool rpmsg_proc_inited = false;
-T_RpMsg_EvList evtList;
-
-static inline void icp_rpmsg_read(T_RpMsg_ChInfo *channelInfo, void *base, void *dest, size_t n, unsigned int offset)
-{
- unsigned int freeCnt = channelInfo->size - channelInfo->recvPos;
-
- if (n == 0)
- return;
-
- if(freeCnt >= n)
- {
- memcpy(dest, (void *)(base + offset + channelInfo->recvPos), n);
- channelInfo->recvPos += (n+n%2);
-
- if(channelInfo->recvPos == channelInfo->size)
- channelInfo->recvPos = 0;
- }
- else
- {
- memcpy(dest, (void *)(base + offset + channelInfo->recvPos), freeCnt);
- memcpy(dest + freeCnt, (void *)(base + offset), n - freeCnt);
-
- channelInfo->recvPos = n - freeCnt + n%2;
- }
-}
-
-static void icp_rpmsg_move_recv_pos(T_RpMsg_ChInfo *channelInfo, size_t n)
-{
- unsigned int freeCnt = channelInfo->size - channelInfo->recvPos;
-
- if(freeCnt >= n)
- {
- channelInfo->recvPos += (n+n%2);
-
- if(channelInfo->recvPos == channelInfo->size)
- channelInfo->recvPos = 0;
- }
- else
- channelInfo->recvPos = n-freeCnt+n%2;
-}
-
-/* static void icp_rpmsg_write(T_RpMsg_ChInfo *channelInfo, void *base, __const void *src, size_t n) */
-static void icp_rpmsg_write(T_RpMsg_ChInfo *channelInfo,
- void *base,
- __const void *src,
- size_t n,
- T_RpMsg_CoreID actor_id,
- T_RpMsg_ChID ch_id)
-{
- unsigned int freeCnt = channelInfo->size - CUR_SEND_POS(actor_id, ch_id);
-
- if (n == 0)
- return;
-
- if(freeCnt >= n)
- {
- memcpy((void *)(base + channelInfo->send_offset + CUR_SEND_POS(actor_id, ch_id)), src, n);
- CUR_SEND_POS(actor_id, ch_id) += (n+n%2);
-
- if(CUR_SEND_POS(actor_id, ch_id) == channelInfo->size)
- CUR_SEND_POS(actor_id, ch_id) = 0;
- }
- else
- {
- memcpy((void *)(base + channelInfo->send_offset + CUR_SEND_POS(actor_id, ch_id)), src, freeCnt);
- memcpy((void *)(base + channelInfo->send_offset), src + freeCnt, n - freeCnt);
- CUR_SEND_POS(actor_id, ch_id) = n-freeCnt+n%2;
- }
-}
-
-static inline bool rpmsg_IsRecvChEmpty(T_RpMsg_ChInfo *channelRecv)
-{
- if (channelRecv->sendPos == channelRecv->recvPos)
- return 1;
- else
- return 0;
-}
-
-static inline bool rpmsg_IsChFreeSpace(T_RpMsg_ChInfo *channelSend, int size)
-{
- if (channelSend->sendPos < channelSend->recvPos){
- if ((channelSend->recvPos - channelSend->sendPos) > size)
- return 1;
- else
- return 0;
- }
- else{
- if ((channelSend->size - channelSend->sendPos + channelSend->recvPos ) > size)
- return 1;
- else
- return 0;
- }
-}
-
-static inline u32 rpmsg_ChUsedSpace(T_RpMsg_ChInfo *channelInfo)
-{
- unsigned int sendPos = channelInfo->sendPos;
-
- if (sendPos >= channelInfo->recvPos)
- return (sendPos - channelInfo->recvPos);
- else
- return (channelInfo->size - channelInfo->recvPos + sendPos);
-}
-
-
-static int rpmsg_EvlistInsert(T_RpMsg_CoreID coreID, T_RpMsg_ChID chID)
-{
- unsigned next = 0;
-
- if (coreID >= CORE_MAXID || chID >= CHANNEL_MAXID(coreID))
- return RPMSG_ERROR;
-
- next = (evtList.startEvIndex+1)%RPMSG_EVENT_LIST_MAX_NUM;
- if (next == evtList.endEvIndex)
- return RPMSG_ERROR;
- else
- {
- evtList.evList[evtList.startEvIndex].coreID = coreID;
- evtList.evList[evtList.startEvIndex].chID= chID;
- evtList.startEvIndex = next;
- return RPMSG_SUCCESS;
- }
-}
-
-static int rpmsg_EvlistRemove(T_RpMsg_Event *event)
-{
- if (evtList.endEvIndex == evtList.startEvIndex)
- return RPMSG_ERROR;
-
- *event = evtList.evList[evtList.endEvIndex];
- evtList.endEvIndex = (evtList.endEvIndex+1)%RPMSG_EVENT_LIST_MAX_NUM;
-
- return RPMSG_SUCCESS;
-}
-
-static int rpmsgDispatch(T_RpMsg_CoreID coreID, T_RpMsg_ChID chID)
-{
- T_RpMsg_Callback callback;
- T_RpMsg_MsgHeader msgHeader;
- unsigned char rpmsg_buffer[RPMSG_BUFFER_LEN];
- T_RpMsg_ChInfo *channelRecv = rpmsgConfig[coreID].recvBase + chID;
- unsigned int offset;
-
- if (unlikely(!channelRecv->offset))
- return RPMSG_CHANNEL_INEXISTANCE;
-
- callback = rpmsgConfig[coreID].chConfig[chID].fn;
- if (unlikely(callback == NULL))
- return RPMSG_ERROR;
-
- offset = channelRecv->offset - rpmsgConfig[coreID].cur_rcv_addr;
-
- while(rpmsg_IsRecvChEmpty(channelRecv) != 1)
- {
- icp_rpmsg_read(channelRecv, rpmsgConfig[coreID].recvBase, &msgHeader, sizeof(T_RpMsg_MsgHeader), offset);
- if (unlikely(msgHeader.flag != RPMSG_MSGHEAD_FLAG))
- return RPMSG_CHANNEL_MSG_ERR;
-
- if (unlikely(RPMSG_BUFFER_LEN < msgHeader.len))
- rpmsg_panic();
-
- icp_rpmsg_read(channelRecv, rpmsgConfig[coreID].recvBase, rpmsg_buffer, msgHeader.len, offset);
- (*callback)(rpmsg_buffer, msgHeader.len);
- }
-
- return RPMSG_SUCCESS;
-}
-
-static int rpmsgProc(void *arg)
-{
- T_RpMsg_Event event;
- int ret = RPMSG_ERROR;
- printk("rpmsg rpmsgProc\n");
- while (1)
- {
- rpmsgGetSem(&rpmsgProcSem);
- ret = rpmsg_EvlistRemove(&event);
- if (ret == RPMSG_SUCCESS)
- {
- //printk("rpmsgProc:src = %d, chID = %d\n",event.coreID, event.chID);
- rpmsgDispatch(event.coreID, event.chID);
- }
- }
-
- return 0;
-}
-
-static void rpmsgIsr(void *data)
-{
- icp_msg *pRpMsg = data;
- T_RpMsg_ChInfo *channelRecv = rpmsgConfig[pRpMsg->src_id].recvBase + pRpMsg->event_id;
-
- if(likely(channelRecv->offset))
- {
- if(unlikely(rpmsgConfig[pRpMsg->src_id].chConfig[pRpMsg->event_id].fn != NULL))
- {
- rpmsg_EvlistInsert(pRpMsg->src_id, pRpMsg->event_id);
- rpmsgPutSem(&rpmsgProcSem);
- }
- else
- {
- rpmsgPutSem(&(rpmsgConfig[pRpMsg->src_id].chConfig[pRpMsg->event_id].recvSem));
- }
- wake_up(&(rpmsgConfig[pRpMsg->src_id].chConfig[pRpMsg->event_id].waitq));
- }
-}
-
-int rpmsgTrigger(T_RpMsg_CoreID coreID, T_RpMsg_ChID chID)
-{
- icp_msg icp_msg;
-
- icp_msg.src_id = Icp_rpmsg_actor;
- icp_msg.dest_core = coreID;
- icp_msg.event_id = chID;
-
- return icpdev_send_message(icp_msg.src_id, &icp_msg);
-}
-
-/*******************************************************************************
- * Global function implementations *
- ******************************************************************************/
-int rpmsgRead_nohead(const T_RpMsg_Msg *pMsg)
-{
- unsigned long flags;
- unsigned int result_len = 0;
- unsigned int offset;
- T_RpMsg_ChInfo *channelRecv = rpmsgConfig[pMsg->coreID].recvBase + pMsg->chID;
-
-// printk("rpmsg_Read:actorID = %d, chID = %d\n",pMsg->coreID, pMsg->chID);
-
- if (unlikely(pMsg == NULL || pMsg->coreID >= CORE_MAXID || pMsg->chID >= CHANNEL_MAXID(pMsg->coreID)))
- return RPMSG_INVALID_PARAMETER;
-
- if (unlikely(!channelRecv->offset))
- return RPMSG_CHANNEL_INEXISTANCE;
-
- while (rpmsg_IsRecvChEmpty(channelRecv) == 1)/*È·±£Ã»ÓÐÐźÅÁ¿¶Ñ»ý*/
- {
- if(pMsg->flag & RPMSG_READ_ONCE || pMsg->flag & RPMSG_READ_IRQLOCK)
- return RPMSG_NO_MSG;
-
- if(rpmsgGetSem(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].recvSem)))
- return RPMSG_ERROR;
-
- if(unlikely(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readExit == 1))
- {
- rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readExit = 0;
- return RPMSG_SUCCESS;
- }
- }
-
- if(pMsg->flag & RPMSG_READ_IRQLOCK)
- rpmsg_irq_lock(flags);
- else
- rpmsgGetMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readMutex));
-
- result_len = pMsg->len;
-
- offset = channelRecv->offset - rpmsgConfig[pMsg->coreID].cur_rcv_addr;
- icp_rpmsg_read(channelRecv, rpmsgConfig[pMsg->coreID].recvBase, pMsg->buf, result_len, offset);
-
-exit:
- if(pMsg->flag & RPMSG_READ_IRQLOCK)
- rpmsg_irq_unlock(flags);
- else
- rpmsgPutMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readMutex));
-
- return result_len;
-}
-
-int rpmsgWrite_nohead(const T_RpMsg_Msg *pMsg)
-{
- int ret;
- unsigned int size = 0;
- unsigned int flags;
- T_RpMsg_ChInfo *channelSend = rpmsgConfig[pMsg->coreID].sendBase + pMsg->chID;
-
- if (unlikely(pMsg == NULL || pMsg->coreID >= CORE_MAXID || pMsg->chID >= CHANNEL_MAXID(pMsg->coreID)))
- return RPMSG_INVALID_PARAMETER;
-
- if (unlikely(!channelSend->offset))
- return RPMSG_CHANNEL_INEXISTANCE;
-
- size = pMsg->len+ sizeof(T_RpMsg_MsgHeader);
- size = ALIGN_RPMSG(size,RPMSG_ALIGN);
-
- if(pMsg->flag & RPMSG_WRITE_IRQLOCK)
- rpmsg_irq_lock(flags);//spin_lock_irq
- else
- rpmsgGetMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].writeMutex));
-
- if (likely(rpmsg_IsChFreeSpace(channelSend, size) == 1)){
- CUR_SEND_POS(pMsg->coreID, pMsg->chID) = channelSend->sendPos;
- icp_rpmsg_write(channelSend,
- rpmsgConfig[pMsg->coreID].sendBase,
- pMsg->buf,
- pMsg->len,
- pMsg->coreID,
- pMsg->chID);
- ret = pMsg->len;
- channelSend->sendPos = CUR_SEND_POS(pMsg->coreID, pMsg->chID);
-
- asm volatile("dmb sy\n");
- }
- else
- {
- ret = RPMSG_SPACE_NOT_ENOUGH;
- goto exit;
- }
- if(pMsg->flag & RPMSG_WRITE_INT)
- ret = rpmsgTrigger(pMsg->coreID, pMsg->chID);
-
-exit:
- if(pMsg->flag & RPMSG_WRITE_IRQLOCK)
- rpmsg_irq_unlock(flags);
- else
- rpmsgPutMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].writeMutex));
-
- return ret;
-}
-
-int rpmsgRead(const T_RpMsg_Msg *pMsg)
-{
- unsigned long flags;
- unsigned int offset;
- unsigned int result_len = 0;
- T_RpMsg_MsgHeader tmpMsgHeader;
- T_RpMsg_ChInfo *channelRecv = rpmsgConfig[pMsg->coreID].recvBase + pMsg->chID;
-
-// printk("rpmsg_Read:actorID = %d, chID = %d\n",pMsg->coreID, pMsg->chID);
-
- if (unlikely(pMsg == NULL || pMsg->coreID >= CORE_MAXID || pMsg->chID >= CHANNEL_MAXID(pMsg->coreID)))
- return RPMSG_INVALID_PARAMETER;
-
- if (unlikely(!channelRecv->offset))
- return RPMSG_CHANNEL_INEXISTANCE;
-
- if ((pMsg->flag & RPMSG_READ_POLL) && (rpmsg_IsRecvChEmpty(channelRecv) == 1))
- return RPMSG_NO_MSG;
-
- while (rpmsg_IsRecvChEmpty(channelRecv) == 1)/*È·±£Ã»ÓÐÐźÅÁ¿¶Ñ»ý*/
- {
- if(pMsg->flag & RPMSG_READ_ONCE || pMsg->flag & RPMSG_READ_IRQLOCK)
- return RPMSG_NO_MSG;
-
- if(rpmsgGetSem(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].recvSem)))
- return RPMSG_ERROR;
-
- if(unlikely(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readExit == 1))
- {
- rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readExit = 0;
- return RPMSG_SUCCESS;
- }
- }
-
- if(pMsg->flag & RPMSG_READ_IRQLOCK)
- rpmsg_irq_lock(flags);
- else
- rpmsgGetMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readMutex));
-
- offset = channelRecv->offset - rpmsgConfig[pMsg->coreID].cur_rcv_addr;
-
- icp_rpmsg_read(channelRecv, rpmsgConfig[pMsg->coreID].recvBase, &tmpMsgHeader, sizeof(T_RpMsg_MsgHeader), offset);
- if (unlikely(tmpMsgHeader.flag != RPMSG_MSGHEAD_FLAG))
- {
- result_len = RPMSG_CHANNEL_MSG_ERR;
- goto exit;
- }
-
- result_len = min(pMsg->len, (unsigned int)(tmpMsgHeader.len));
-
- icp_rpmsg_read(channelRecv, rpmsgConfig[pMsg->coreID].recvBase, pMsg->buf, result_len, offset);
- if (unlikely((unsigned int)(tmpMsgHeader.len) > result_len))
- icp_rpmsg_move_recv_pos(channelRecv, (unsigned int)(tmpMsgHeader.len) - result_len - result_len%2);
-
-exit:
- if(pMsg->flag & RPMSG_READ_IRQLOCK)
- rpmsg_irq_unlock(flags);
- else
- rpmsgPutMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readMutex));
-
- return result_len;
-}
-
-int rpmsgWrite(const T_RpMsg_Msg *pMsg)
-{
- int ret;
- unsigned int size = 0;
- T_RpMsg_MsgHeader tmpMsgHeader;
- unsigned int flags;
- T_RpMsg_ChInfo *channelSend = rpmsgConfig[pMsg->coreID].sendBase + pMsg->chID;
-
- if (unlikely(pMsg == NULL || pMsg->coreID >= CORE_MAXID || pMsg->chID >= CHANNEL_MAXID(pMsg->coreID)))
- return RPMSG_INVALID_PARAMETER;
-
- if (unlikely(!channelSend->offset))
- return RPMSG_CHANNEL_INEXISTANCE;
-
- size = pMsg->len+ sizeof(T_RpMsg_MsgHeader);
- size = ALIGN_RPMSG(size,RPMSG_ALIGN);
-
- if(pMsg->flag & RPMSG_WRITE_IRQLOCK)
- rpmsg_irq_lock(flags);//spin_lock_irq
- else
- rpmsgGetMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].writeMutex));
-
- if (likely(rpmsg_IsChFreeSpace(channelSend, size) == 1)){
-#if RPMSG_LARGE_MSG_HEADER
- tmpMsgHeader.flag = RPMSG_MSGHEAD_FLAG;
- tmpMsgHeader.len = pMsg->len;
-#else
- tmpMsgHeader.flag = (unsigned short)RPMSG_MSGHEAD_FLAG;
- tmpMsgHeader.len = (unsigned short)(pMsg->len);
-#endif
- CUR_SEND_POS(pMsg->coreID, pMsg->chID) = channelSend->sendPos;
- icp_rpmsg_write(channelSend,
- rpmsgConfig[pMsg->coreID].sendBase,
- &tmpMsgHeader,
- sizeof(T_RpMsg_MsgHeader),
- pMsg->coreID,
- pMsg->chID);
- icp_rpmsg_write(channelSend,
- rpmsgConfig[pMsg->coreID].sendBase,
- pMsg->buf,
- pMsg->len,
- pMsg->coreID,
- pMsg->chID);
- ret = pMsg->len;
- channelSend->sendPos = CUR_SEND_POS(pMsg->coreID, pMsg->chID);
-
- asm volatile("dmb sy\n");
- }
- else
- {
- ret = RPMSG_SPACE_NOT_ENOUGH;
- goto exit;
- }
- if(pMsg->flag & RPMSG_WRITE_INT)
- ret = rpmsgTrigger(pMsg->coreID, pMsg->chID);
-
-exit:
- if(pMsg->flag & RPMSG_WRITE_IRQLOCK)
- rpmsg_irq_unlock(flags);
- else
- rpmsgPutMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].writeMutex));
-
- return ret;
-}
-
-int rpmsgCreateChannel (T_RpMsg_CoreID dstCoreID, T_RpMsg_ChID chID, unsigned int size)
-{
- T_RpMsg_ChInfo *channelSend;
-
- if (dstCoreID >= CORE_MAXID || chID >= CHANNEL_MAXID(dstCoreID))
- return RPMSG_INVALID_PARAMETER;
-
- if (!rpmsgConfig[dstCoreID].sendBase)
- return RPMSG_INVALID_PARAMETER;
-
- channelSend = rpmsgConfig[dstCoreID].sendBase + chID;
-
- if (channelSend->offset)
- return RPMSG_CHANNEL_ALREADY_EXIST;
-
-/*
- if (rpmsgConfig[dstCoreID].recvBase != 0)
- {
- rpmsgGetMutex(&rpmsgConfig[dstCoreID].chMutex);
- rpmsgInitSem(&rpmsgConfig[dstCoreID].chConfig[chID].recvSem);
- rpmsgInitMutex(&rpmsgConfig[dstCoreID].chConfig[chID].readMutex);
- init_waitqueue_head(&(rpmsgConfig[dstCoreID].chConfig[chID].waitq));
- rpmsgPutMutex(&rpmsgConfig[dstCoreID].chMutex);
- }
-*/
- size = ALIGN_RPMSG(size,RPMSG_ALIGN);
- rpmsgGetMutex(&rpmsgConfig[dstCoreID].chMutex);
-
- if (size > rpmsgConfig[dstCoreID].freeSize)
- {
- rpmsgPutMutex(&rpmsgConfig[dstCoreID].chMutex);
- return RPMSG_SPACE_NOT_ENOUGH;
- }
-
- channelSend->offset = rpmsgConfig[dstCoreID].cur_send_addr;// rpmsgConfig[dstCoreID].offset;
- channelSend->send_offset = rpmsgConfig[dstCoreID].offset;
- rpmsgConfig[dstCoreID].offset += size;
- rpmsgConfig[dstCoreID].cur_send_addr += size;
- rpmsgConfig[dstCoreID].freeSize -= size;
- rpmsgPutMutex(&rpmsgConfig[dstCoreID].chMutex);
- channelSend->size = size;
- channelSend->flag |= CHANNEL_FLAG;
-
- rpmsgInitMutex(&(rpmsgConfig[dstCoreID].chConfig[chID].writeMutex));
-
- icpdev_unmask_int(dstCoreID, chID);
-
- return RPMSG_SUCCESS;
-}
-
-int rpmsgRegCallBack(T_RpMsg_CoreID coreID, unsigned int chID, T_RpMsg_Callback callback)
-{
- if(coreID >= CORE_MAXID || chID >= CHANNEL_MAXID(coreID))
- return RPMSG_INVALID_PARAMETER;
-
- rpmsgConfig[coreID].chConfig[chID].fn = callback;
- if(callback != NULL)
- rpmsgDispatch(coreID, chID);
-
- icpdev_unmask_int(coreID, chID);
-
- return 0;
-}
-
-void rpmsgReadExit(T_RpMsg_CoreID coreID, T_RpMsg_ChID chID)
-{
- rpmsgConfig[coreID].chConfig[chID].readExit = 1;
-
- if(0 == rpmsgGetSemaCount(&rpmsgConfig[coreID].chConfig[chID].recvSem))
- rpmsgPutSem(&(rpmsgConfig[coreID].chConfig[chID].recvSem));
-}
-
-int rpmsgInit(T_RpMsg_CoreID coreID, struct device_node *np)
-{
- int ret = 0;
- T_RpMsg_Msg pMsg = {0};
- void * virAddr;
- unsigned int mem_size;
- struct resource res;
- unsigned int chan_cnt;
- T_RpMsg_ChConfig *chan_cfg;
- unsigned int *send_pos;
- int i;
- ret = of_property_read_u32(np, "icp-channels", &chan_cnt);
- if (!chan_cnt) {
- pr_err("%s: [ICP]Cannot get channel count %d\n", __func__, ret);
- return ret;
- }
- rpmsgConfig[coreID].chan_cnt = chan_cnt;
-
- /* send buffer */
- ret = of_address_to_resource(np, 1, &res);
- if (ret){
- pr_err("%s: [ICP]Cannot get IORESOURCE_MEM %d\n", __func__, ret);
- return ret;
- }
-
- mem_size = (unsigned int)resource_size(&res);
- virAddr = ioremap_wc(res.start, mem_size);
- if(virAddr == NULL)
- return RPMSG_ERROR;
-
- memset(virAddr, 0x0, mem_size);
- rpmsgConfig[coreID].sendBase = virAddr;
- rpmsgConfig[coreID].offset = chan_cnt * sizeof(T_RpMsg_ChInfo);
- rpmsgConfig[coreID].freeSize = mem_size - chan_cnt*sizeof(T_RpMsg_ChInfo);
- rpmsgInitMutex(&rpmsgConfig[coreID].chMutex);
- rpmsgConfig[coreID].cur_send_addr = res.start + chan_cnt*sizeof(T_RpMsg_ChInfo);
-
- /* recv buffer */
- ret = of_address_to_resource(np, 2, &res);
- if (ret){
- pr_err("%s: [ICP]Cannot get IORESOURCE_MEM %d\n", __func__, ret);
- return ret;
- }
-
- mem_size = resource_size(&res);
- virAddr = ioremap_wc(res.start, mem_size);
- if(virAddr == NULL)
- return RPMSG_ERROR;
-
- rpmsgConfig[coreID].recvBase = virAddr;
- rpmsgConfig[coreID].cur_rcv_addr = res.start;
-
- chan_cfg = kzalloc(sizeof(T_RpMsg_ChConfig)*chan_cnt, GFP_KERNEL);
- if (!chan_cfg)
- return -ENOMEM;
- rpmsgConfig[coreID].chConfig = chan_cfg;
-
- send_pos = kzalloc(sizeof(unsigned int)*chan_cnt, GFP_KERNEL);
- if (!send_pos)
- return -ENOMEM;
- rpmsgConfig[coreID].send_pos = send_pos;
-
- for (i=0; i<chan_cnt; i++) {
- rpmsgInitSem(&rpmsgConfig[coreID].chConfig[i].recvSem);
- rpmsgInitMutex(&rpmsgConfig[coreID].chConfig[i].readMutex);
- init_waitqueue_head(&(rpmsgConfig[coreID].chConfig[i].waitq));
- }
-
- if (!rpmsg_proc_inited)
- {
- rpmsgInitSem(&rpmsgProcSem);
-
- icpdev_register_callback(rpmsgIsr);
-
- rpmsgCreateThread("rpmsgProc", rpmsgProc, 0);
-
- rpmsg_proc_inited = true;
- }
-
- if (coreID == CORE_PS0)
- {
- rpmsgConfig[coreID].dev.id = coreID;
- ret = icp_rpmsg_device_register(&rpmsgConfig[coreID].dev, chan_cnt);
- }
-
- return RPMSG_SUCCESS;
-}
-
-int rpmsgReadWithId(u32 *pMsgId, const T_RpMsg_Msg *pMsg)
-{
- unsigned long flags;
- unsigned int offset;
- unsigned int result_len = 0;
- T_RpMsg_MsgHeader tmpMsgHeader;
- T_RpMsg_ChInfo *channelRecv = rpmsgConfig[pMsg->coreID].recvBase + pMsg->chID;
-
- printk("rpmsg_Read:actorID = %d, chID = %d\n",pMsg->coreID, pMsg->chID);
-
- if (pMsg == NULL || pMsg->coreID >= CORE_MAXID || pMsg->chID >= CHANNEL_MAXID(pMsg->coreID))
- return RPMSG_INVALID_PARAMETER;
-
- if (!channelRecv->offset)
- return RPMSG_CHANNEL_INEXISTANCE;
-
- if ((pMsg->flag & RPMSG_READ_POLL) && (rpmsg_IsRecvChEmpty(channelRecv) == 1))
- return RPMSG_NO_MSG;
-
- while (rpmsg_IsRecvChEmpty(channelRecv) == 1)/*È·±£Ã»ÓÐÐźÅÁ¿¶Ñ»ý*/
- {
- if(pMsg->flag & RPMSG_READ_ONCE || pMsg->flag & RPMSG_READ_IRQLOCK)
- return RPMSG_NO_MSG;
-
- if(rpmsgGetSem(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].recvSem)))
- return RPMSG_ERROR;
-
- if(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readExit == 1)
- {
- rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readExit = 0;
- return RPMSG_SUCCESS;
- }
- }
-
- if(pMsg->flag & RPMSG_READ_IRQLOCK)
- rpmsg_irq_lock(flags);
- else
- rpmsgGetMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readMutex));
-
- offset = channelRecv->offset - rpmsgConfig[pMsg->coreID].cur_rcv_addr;
-
- icp_rpmsg_read(channelRecv, rpmsgConfig[pMsg->coreID].recvBase, &tmpMsgHeader, sizeof(T_RpMsg_MsgHeader), offset);
- if (tmpMsgHeader.flag != RPMSG_MSGHEAD_FLAG)
- {
- result_len = RPMSG_CHANNEL_MSG_ERR;
- goto exit;
- }
-
- /* read msg_id */
- icp_rpmsg_read(channelRecv, rpmsgConfig[pMsg->coreID].recvBase, pMsgId, sizeof(u32), offset);
- tmpMsgHeader.len -= sizeof(u32);
-
- result_len = min(pMsg->len, (unsigned int)(tmpMsgHeader.len));
-
- icp_rpmsg_read(channelRecv, rpmsgConfig[pMsg->coreID].recvBase, pMsg->buf, result_len, offset);
- if((unsigned int)(tmpMsgHeader.len) > result_len)
- icp_rpmsg_move_recv_pos(channelRecv, (unsigned int)(tmpMsgHeader.len) - result_len - result_len%2);
-
-exit:
- if(pMsg->flag & RPMSG_READ_IRQLOCK)
- rpmsg_irq_unlock(flags);
- else
- rpmsgPutMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].readMutex));
-
- return result_len;
-}
-
-int rpmsgWriteWithId(u32 pMsgId, const T_RpMsg_Msg *pMsg)
-{
- int ret;
- unsigned int size = 0;
- T_RpMsg_MsgHeader tmpMsgHeader;
- unsigned int flags;
- T_RpMsg_ChInfo *channelSend = rpmsgConfig[pMsg->coreID].sendBase + pMsg->chID;
-
- if (pMsg == NULL || pMsg->coreID >= CORE_MAXID || pMsg->chID >= CHANNEL_MAXID(pMsg->coreID))
- return RPMSG_INVALID_PARAMETER;
-
- if (!channelSend->offset)
- return RPMSG_CHANNEL_INEXISTANCE;
-
- size = pMsg->len+ sizeof(T_RpMsg_MsgHeader) + sizeof(u32);
- size = ALIGN_RPMSG(size,RPMSG_ALIGN);
-
- if(pMsg->flag & RPMSG_WRITE_IRQLOCK)
- rpmsg_irq_lock(flags);//spin_lock_irq
- else
- rpmsgGetMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].writeMutex));
-
- if (rpmsg_IsChFreeSpace(channelSend, size) == 1){
-#if RPMSG_LARGE_MSG_HEADER
- tmpMsgHeader.flag = RPMSG_MSGHEAD_FLAG;
- tmpMsgHeader.len = pMsg->len + sizeof(u32);
-#else
- tmpMsgHeader.flag = (unsigned short)RPMSG_MSGHEAD_FLAG;
- tmpMsgHeader.len = (unsigned short)(pMsg->len) + sizeof(u32);
-#endif
- CUR_SEND_POS(pMsg->coreID, pMsg->chID) = channelSend->sendPos;
- icp_rpmsg_write(channelSend,
- rpmsgConfig[pMsg->coreID].sendBase,
- &tmpMsgHeader,
- sizeof(T_RpMsg_MsgHeader),
- pMsg->coreID,
- pMsg->chID);
- icp_rpmsg_write(channelSend,
- rpmsgConfig[pMsg->coreID].sendBase,
- &pMsgId,
- sizeof(u32),
- pMsg->coreID,
- pMsg->chID);
- icp_rpmsg_write(channelSend,
- rpmsgConfig[pMsg->coreID].sendBase,
- pMsg->buf,
- pMsg->len,
- pMsg->coreID,
- pMsg->chID);
- channelSend->sendPos = CUR_SEND_POS(pMsg->coreID, pMsg->chID);
- ret = pMsg->len;
-
- asm volatile("dmb sy\n");
- }
- else
- {
- ret = RPMSG_SPACE_NOT_ENOUGH;
- goto exit;
- }
- ret = rpmsgTrigger(pMsg->coreID, pMsg->chID);
-
-exit:
- if(pMsg->flag & RPMSG_WRITE_IRQLOCK)
- rpmsg_irq_unlock(flags);
- else
- rpmsgPutMutex(&(rpmsgConfig[pMsg->coreID].chConfig[pMsg->chID].writeMutex));
-
- return ret;
-}
-
-/*---------------------------------------------------------------------------*
- *-- interface for userspace ------------------------------------------------*
- *---------------------------------------------------------------------------*/
-int rpmsg_rcv_chan_size(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
-{
- T_RpMsg_ChInfo *channel_recv = rpmsgConfig[actorID].recvBase + chID;
-
- return rpmsg_ChUsedSpace(channel_recv);
-}
-
-int rpmsg_set_flag_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID, unsigned int flag)
-{
- T_RpMsg_ChInfo *channel_send = rpmsgConfig[actorID].sendBase + chID;;
-
- if(flag == 1)
- channel_send->flag |= CHANNEL_INT_FLAG;
- else if(flag == 0)
- channel_send->flag &= ~CHANNEL_INT_FLAG;
- else
- return RPMSG_ERROR;
-
- return RPMSG_SUCCESS;
-}
-
-int rpmsg_set_flag_poll(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID, unsigned int flag)
-{
- T_RpMsg_ChInfo *channel_send = rpmsgConfig[actorID].sendBase + chID;
-
- if(flag == 1)
- channel_send->flag |= CHANENL_POLL_FLAG;
- else if(flag == 0)
- channel_send->flag &= ~CHANENL_POLL_FLAG;
- else
- return RPMSG_ERROR;
-
- return RPMSG_SUCCESS;
-}
-
-unsigned int rpmsg_get_flag(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
-{
- T_RpMsg_ChInfo *channel_send = rpmsgConfig[actorID].sendBase + chID;
-
- return channel_send->flag;
-}
-
-int rpmsg_poll(struct file *file,
- T_ZDrvRpMsg_ActorID actorID,
- T_ZDrvRpMsg_ChID chID,
- struct poll_table_struct *wait)
-{
- T_RpMsg_ChInfo *channel_recv = rpmsgConfig[actorID].recvBase + chID;
-
- poll_wait(file, &(rpmsgConfig[actorID].chConfig[chID].waitq), wait);
-
- if (!rpmsg_IsRecvChEmpty(channel_recv))
- return POLLIN | POLLRDNORM;
-
- return 0;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg.h
deleted file mode 100644
index 5132bdb..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/**
- * @file icp_rpmsg.h
- * @brief
- *
- * Copyright (C) 2017 ZTE Co., Ltd.
- * @author Qing Wang
- * @ingroup
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- */
-
-#ifndef _ICP_RPMSG_H
-#define _ICP_RPMSG_H
-
-/*******************************************************************************
- * Include header files *
- ******************************************************************************/
-#include "icp_rpmsg_osa.h"
-#include <linux/soc/zte/rpmsg.h>
-
-#ifdef CONFIG_ZX29_ICP
-#include "zx29_icp.h"
-#else
-# error "You should include a soc icp header file here"
-#endif
-
-/*******************************************************************************
-* Extern variable definitions *
-*******************************************************************************/
-
-/*******************************************************************************
- * Macro definitions *
- ******************************************************************************/
-//#define SHARE_BUF_CACHABLE
-#ifdef CONFIG_ARCH_ZX297520V3
-#define RPMSG_LARGE_MSG_HEADER (0)
-#else
-#define RPMSG_LARGE_MSG_HEADER (1)
-#endif
-
-#define RPMSG_EVENT_LIST_MAX_NUM 10
-
-#define CHANNEL_MAXID(coreID) rpmsgConfig[coreID].chan_cnt
-
-/*******************************************************************************
- * Type definitions *
- ******************************************************************************/
-typedef struct _T_RpMsg_MsgHeader
-{
-#if RPMSG_LARGE_MSG_HEADER
- unsigned int flag;
- unsigned int len;
-#else
- unsigned short flag;
- unsigned short len;
-#endif
-}T_RpMsg_MsgHeader;
-
-typedef struct _T_RpMsg_Event
-{
- T_RpMsg_CoreID coreID;
- T_RpMsg_ChID chID;
-}T_RpMsg_Event;
-
-typedef struct _T_RpMsg_EvList
-{
- T_RpMsg_Event evList[RPMSG_EVENT_LIST_MAX_NUM];
- unsigned int startEvIndex;
- unsigned int endEvIndex;
-}T_RpMsg_EvList;
-
-/* MUST coherent between cores */
-#ifdef SHARE_BUF_CACHABLE
-typedef struct _T_RpMsg_ChInfo
-{
- unsigned int sendPos;
- unsigned int offset;
- unsigned int size;
- unsigned int flag;
- unsigned int rsv0[12];
- unsigned int recvPos;
- unsigned int rsv1[15];
-}T_RpMsg_ChInfo;
-#else
-typedef struct _T_RpMsg_ChInfo
-{
- unsigned int offset;
- unsigned int sendPos;
- unsigned int recvPos;
- unsigned int size;
- unsigned int flag;
- unsigned int send_offset;
-}T_RpMsg_ChInfo;
-#endif
-
-typedef struct _T_RpMsg_ChConfig
-{
- unsigned int readExit;
- rpmsg_mutex readMutex;
- rpmsg_mutex writeMutex;
- rpmsg_sema recvSem;
- wait_queue_head_t waitq;
- T_RpMsg_Callback fn;
-}T_RpMsg_ChConfig;
-
-typedef struct _T_RpMsg_CoreConfig
-{
- T_RpMsg_ChInfo *sendBase;
- T_RpMsg_ChInfo *recvBase;
-
- /* for v3 only */
- unsigned int cur_send_addr;
- unsigned int cur_rcv_addr;
-
- unsigned int offset;
- unsigned int freeSize;
- rpmsg_mutex chMutex;
-
- struct device dev;
-
- unsigned int chan_cnt;
- T_RpMsg_ChConfig *chConfig;
- unsigned int *send_pos;
-}T_RpMsg_CoreConfig;
-
-/*******************************************************************************
-* Extern function declarations *
-*******************************************************************************/
-
-/*******************************************************************************
- * Global variable declarations *
- ******************************************************************************/
-extern T_RpMsg_CoreConfig rpmsgConfig[];
-
-/*******************************************************************************
- * Global function declarations *
- ******************************************************************************/
-int rpmsgInit(T_RpMsg_CoreID coreID, struct device_node *np);
-int icp_rpmsg_device_register(struct device *dev, unsigned int channel_count);
-int rpmsg_rcv_chan_size(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID);
-int rpmsg_set_flag_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID, unsigned int flag);
-int rpmsg_set_flag_poll(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID, unsigned int flag);
-unsigned int rpmsg_get_flag(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID);
-int rpmsg_poll(struct file *file,
- T_ZDrvRpMsg_ActorID actorID,
- T_ZDrvRpMsg_ChID chID,
- struct poll_table_struct *wait);
-
-/*******************************************************************************
-* Inline function declarations *
-*******************************************************************************/
-
-#endif
-
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg_linux.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg_linux.c
deleted file mode 100644
index 4cc38a4..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg_linux.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/**
- * @file oss_ramdump_osa.c
- * @brief Implementation of Ramdump os adapter
- *
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * @author Qing Wang <wang.qing@sanechips.com.cn>
- * @ingroup si_ap_oss_ramdump_id
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- */
-
-/*******************************************************************************
- * Include header files *
-
- ******************************************************************************/
-#include "icp_rpmsg.h"
-#include "icp_rpmsg_osa.h"
-#include <linux/kthread.h>
-#include <uapi/linux/sched/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void rpmsgInitSem(rpmsg_sema *sem)
-{
- sema_init(sem, 0);
-}
-
-int rpmsgGetSem(rpmsg_sema *sem)
-{
- return down_interruptible(sem);
-}
-
-void rpmsgPutSem(rpmsg_sema *sem)
-{
- up(sem);
-}
-
-unsigned int rpmsgGetSemaCount(rpmsg_sema *sem)
-{
- return sem->count;
-}
-
-
-void rpmsgInitMutex(rpmsg_mutex *mutex)
-{
- mutex_init(mutex);
-}
-
-void rpmsgGetMutex(rpmsg_mutex *mutex)
-{
- mutex_lock(mutex);
-}
-
-void rpmsgPutMutex(rpmsg_mutex *mutex)
-{
- mutex_unlock(mutex);
-}
-
-
-//void *rpmsgCreateThread(const char *thread_name, void (*entry)(int), unsigned int priority)
-void rpmsgCreateThread(const char *thread_name, int (*entry)(void *), unsigned int priority)
-{
- struct task_struct *task;
- struct sched_param param;
-
- task = kthread_create(entry, NULL, thread_name);
-
- param.sched_priority = min(priority, MAX_USER_RT_PRIO - 1);
- param.sched_priority = MAX_USER_RT_PRIO - 1 - param.sched_priority;
- sched_setscheduler(task, SCHED_FIFO, ¶m);
-
- wake_up_process(task);
-
-// return task;
-}
-
-
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg_osa.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg_osa.h
deleted file mode 100644
index 7d117ad..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_rpmsg_osa.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/**
- * @file icp_ramdump_osa.h
- * @brief
- *
- * Copyright (C) 2017 ZTE Co., Ltd.
- * @author Qing Wang
- * @ingroup
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- */
-
-#ifndef _ICP_RPMSG_OSA_H
-#define _ICP_RPMSG_OSA_H
-
-/*******************************************************************************
- * Include header files *
- ******************************************************************************/
-#define OS_LINUX
-
-#ifdef OS_LINUX
-#include <linux/semaphore.h>
-#include <linux/mutex.h>
-#include <asm/io.h>
-#include <linux/poll.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-
-#elif defined OS_TOS
-#include "oss_api.h"
-#include "osa.h"
-#include "sup.h"
-#include "tos_typedef.h"
-
-#endif
-
-/*******************************************************************************
-* Extern variable definitions *
-*******************************************************************************/
-
-/*******************************************************************************
- * Macro definitions *
- ******************************************************************************/
-#ifdef OS_LINUX
-#define rpmsg_mutex struct mutex
-#define rpmsg_sema struct semaphore
-#define rpmsg_ioremap(addr, size) ioremap_wc(addr, size)
-#define rpmsg_panic() panic("rpmsg")
-#define rpmsg_irq_lock(flags) local_irq_save(flags)
-#define rpmsg_irq_unlock(flags) local_irq_restore(flags)
-
-#elif defined OS_TOS
-#define rpmsg_mutex tos_mutex_t
-#define rpmsg_sema tos_semaphore_t
-#define rpmsg_panic()
-#define rpmsg_irq_lock(flags) tos_irq_save(flags)
-#define rpmsg_irq_unlock(flags) tos_irq_restore(flags)
-
-#endif
-
-/*******************************************************************************
- * Type definitions *
- ******************************************************************************/
-
-/*******************************************************************************
-* Extern function declarations *
-*******************************************************************************/
-
-/*******************************************************************************
- * Global variable declarations *
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function declarations *
- ******************************************************************************/
-void rpmsgInitSem(rpmsg_sema *sem);
-int rpmsgGetSem(rpmsg_sema *sem);
-void rpmsgPutSem(rpmsg_sema *sem);
-unsigned int rpmsgGetSemaCount(rpmsg_sema *sem);
-void rpmsgInitMutex(rpmsg_mutex *mutex);
-void rpmsgGetMutex(rpmsg_mutex *mutex);
-void rpmsgPutMutex(rpmsg_mutex *mutex);
-void rpmsgCreateThread(const char *thread_name, int (*entry)(void *), unsigned int priority);
-
-/*******************************************************************************
-* Inline function declarations *
-*******************************************************************************/
-
-
-#endif // #ifndef _ICP_RPMSG_OSA_H
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_test.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_test.c
deleted file mode 100644
index 51086d7..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/icp_test.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * linux/arch/arm/mach-zx297520v2/debug.c
- *
- * Copyright (C) 2015 ZTE-TSP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/syscore_ops.h>
-#include <linux/gpio.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_runtime.h>
-#include <linux/soc/zte/common.h>
-
-#include "icp_rpmsg.h"
-#include "icp_dev.h"
-
-#define ICP_DRV_TEST 0
-#define ICP_COMM_TEST 1 /* ps0 */
-
-#define TEST_CORE CORE_PS0
-
-static unsigned int test_channel;
-
-extern T_RpMsg_CoreConfig rpmsgConfig[];
-extern void fake_icp_isr(T_RpMsg_CoreID src_core, T_RpMsg_CoreID dest_core, T_RpMsg_ChID ch);
-
-/*
-UINT32 get_cpuid(void)
-{
- UINT64 mpidr;
- UINT64 cluster;
- UINT64 core;
-
- __asm__ __volatile__("mrs %0, MPIDR_EL1\t\n":"=r"(mpidr));
-
- cluster = (mpidr >> 8) & 0xF;
- core = (mpidr & 0xFF);
- return ((cluster << 2) + core);
-}
-*/
-
-/* in zx29_icp, the event is from 0 to 63 */
-s32 drv_icp_send_to_arm(u32 dest_id, u32 src_id, u32 event)
-{
- icp_msg _icp_msg;
-#if 0
- s32 msg_num = 0;
- u32 poll_num = 0;
-#endif
- s32 ret = 0;
-#if 0
- do
- {
- poll_num ++;
- msg_num = icp_get_inbox_msg_num(dest_id);
- }while(((ICP_INBOX_DEPTH - msg_num) < 10) && (poll_num < 100));
-
-
- if ((ICP_INBOX_DEPTH - msg_num) >= 10)
-#else
- if (1)
-#endif
- {
- _icp_msg.src_id = src_id;
- _icp_msg.dest_core = dest_id; //1<<dest_id;
- _icp_msg.event_id = event;
- ret = icpdev_send_message(src_id, &_icp_msg);
- }
- else
- {
- ret = -ENXIO;
- }
-
- return ret;
-}
-
-#if ICP_DRV_TEST
-#else
-#define RPMSG_TEST_LEN 4
-static unsigned char rpmsg_test_buf[RPMSG_TEST_LEN + 1];
-static s32 rpmsg_send_test(u32 dest_id, u32 event, int data)
-{
- T_RpMsg_Msg rpmsg;
-
- rpmsg.coreID = dest_id;
- rpmsg.chID = event;
- rpmsg.len = RPMSG_TEST_LEN;
- rpmsg.buf = rpmsg_test_buf;
- rpmsg.flag = 0;
- rpmsg.flag |= RPMSG_WRITE_INT;
-#if ICP_COMM_TEST
- memcpy(rpmsg.buf, (unsigned char *)&data, sizeof(int));
-#else
- memset(rpmsg.buf, data, rpmsg.len);
-#endif
-
- return rpmsgWrite(&rpmsg);
-}
-
-static void fill_loopback_info(T_RpMsg_CoreID src_core, T_RpMsg_ChID ch, int data)
-{
- /* write some data to recv buf */
- T_RpMsg_ChInfo *channelRecv = rpmsgConfig[src_core].recvBase + ch;
- T_RpMsg_MsgHeader tmpMsgHeader;
- unsigned char *buf;
-
- if (channelRecv->offset == 0)
- {
- if (src_core == CORE_M0) {
- channelRecv->offset = 0x78; /* channel 0 */
- channelRecv->size = 0x300;
- } else {
- channelRecv->offset = 0x3C0;
- channelRecv->size = 0x300;
- }
- }
-
- tmpMsgHeader.flag = 0x5453;
- tmpMsgHeader.len = 7;
-
- /* header */
- buf = (unsigned char *)rpmsgConfig[src_core].recvBase + channelRecv->offset + \
- channelRecv->sendPos;
- memcpy(buf, &tmpMsgHeader, sizeof(T_RpMsg_MsgHeader));
- memset(buf + sizeof(T_RpMsg_MsgHeader), (u8)data, 7);
- channelRecv->sendPos += 7 + sizeof(T_RpMsg_MsgHeader);
-}
-
-#endif
-
-//test
-extern struct kobject *zx_test_kobj;
-extern int icp_int_count;
-static struct timer_list test_timer;
-static unsigned long test_timer_count = 0;
-static void test_timer_expired(struct timer_list *unused)
-{
- mod_timer(&test_timer, jiffies + msecs_to_jiffies(3*1000));
-
-// pr_info("[TEST]icp timer arrived:%lu \n", ++test_timer_count);
-
- if(test_timer_count%2)
- pr_info("drv_icp_send_to_arm(%d)(%d)\n", drv_icp_send_to_arm(TEST_CORE, CORE_AP, 0x5), ++test_timer_count);
- //;//pr_info("drv_icp_send_to_arm(%d)(%d)\n", drv_icp_send_to_arm(CORE_PHY0, CORE_AP, 0xA5), ++test_timer_count);
- else
- pr_info("drv_icp_send_to_arm(%d)(%d)\n", drv_icp_send_to_arm(TEST_CORE, CORE_AP, 0xA), ++test_timer_count);
-}
-
-void icp_test_cb(void *data)
-{
- icp_msg *p_icp_msg = data;
-
- pr_info("icp_test_cb src(%d) dest(%d) event(0x%x)\n", p_icp_msg->src_id,
- p_icp_msg->dest_core, p_icp_msg->event_id);
-}
-
-
-static ssize_t icp_test_show(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- return sprintf(buf, "icp_int_count:%d\n", icp_int_count);
-}
-
-static ssize_t icp_test_store(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t count)
-{
- unsigned int temp;
- int ret;
-
- if(sscanf(buf, "%u", &temp) != 1)
- {
- pr_info("temp=%d error", temp);
- return (count);
- }
-
- pr_info("temp=%d", temp);
-
-#if ICP_DRV_TEST /* test driver only */
- if(temp == 1)
- {
- mod_timer(&test_timer, jiffies + msecs_to_jiffies(3*1000));
- }
- else
- {
- del_timer(&test_timer);
- test_timer_count = 0;
- }
-#else
-
- if(temp == 99 || temp == 66) /* this value is used to loopback test */
- {
- fill_loopback_info(TEST_CORE, test_channel, temp);
-
-#if ICP_COMM_TEST
-#else
- fake_icp_isr(TEST_CORE, CORE_AP, test_channel);
-#endif
- return (count);
- }
-
- ret = rpmsg_send_test(TEST_CORE, test_channel, temp);
- if (ret)
- pr_info("rpmsg send to %d-%d failed(%d)\n", TEST_CORE, test_channel, ret);
-#endif
-
- return (count);
-}
-
-#if ICP_COMM_TEST
-const unsigned int test_send_back = 0x747365ff;
-const unsigned int test_rcv_flag = 0x74736574;
-#endif
-
-void ps0_cb(void *buf, unsigned int len)
-{
- int i;
- unsigned char *data;
-
- pr_info("ps0_cb, len = %d \n\n ", len);
-
- if (len==0)
- return ;
-
- data = (unsigned char *)buf;
- for (i=0; i<len; i++, data++)
- {
- printk("0x%2x", *data);
- }
- printk("\n\n");
-
-#if ICP_COMM_TEST
- if ((len == 4) && (*(unsigned int *)buf == test_rcv_flag))
- {
- rpmsg_send_test(TEST_CORE, test_channel, test_send_back);
- }
-#endif
-}
-
-void phy0_cb(void *buf, unsigned int len)
-{
-
-}
-
-
-// outbox 23 --> 01 send msg one by one (5s )
-static DEVICE_ATTR(icp_test,0600,icp_test_show, icp_test_store);
-static struct attribute *zx_icp_attributes[] = {
- &dev_attr_icp_test.attr,
- NULL,
-};
-
-static const struct attribute_group zx_icp_attribute_group = {
- .attrs = (struct attribute **) zx_icp_attributes,
-};
-
-int __init zx_icp_test_init(void)
-{
- int ret;
-
- ret = sysfs_create_group(zx_test_kobj, &zx_icp_attribute_group);
-
- test_channel = 1;
-
-#if ICP_DRV_TEST /* test driver only */
- icpdev_register_callback(icp_test_cb);
- timer_setup(&test_timer, test_timer_expired, 0);
-#else
- ret = rpmsgCreateChannel(TEST_CORE, test_channel, 100);
- if (ret)
- {
- pr_info("[DEBUG] rpmsgCreateChannel failed(%d).\n", ret);
-// return ret;
- }
-// ret = rpmsgCreateChannel(CORE_PHY0, channel_1, 1024);
-
- ret = rpmsgRegCallBack(TEST_CORE, test_channel, ps0_cb);
- if (ret)
- {
- pr_info("[DEBUG] rpmsgRegCallBack failed(%d).\n", ret);
- return ret;
- }
-
-// ret = rpmsgRegCallBack(CORE_PHY0, channel_1, phy0_cb);
-#endif
-
- pr_info("[DEBUG] create test icp sysfs interface OK.\n");
-
- return 0;
-}
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/rpmsg.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/rpmsg.c
deleted file mode 100644
index b0eebda..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/rpmsg.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2013, ZTE Corporation.
- *
- * File Name: icp.c
- * File Mark:
- * Description:
- * Others:
- * Version: V0.1
- * Author: ShiDeYou
- * Date: 2013-3-13
- * History 1:
- * Date:
- * Version:
- * Author:
- * Modification:
- * History 2:
- ******************************************************************************/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <crypto/internal/skcipher.h>
-#include <linux/cpumask.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-
-#include <linux/mm.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/uaccess.h>
-#include <linux/device.h>
-
-#include <linux/cdev.h>
-#include <linux/workqueue.h>
-
-#include <linux/fs.h>
-#include <linux/platform_device.h>
-
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/io.h>
-
-#include <linux/sched.h>
-#include <linux/poll.h>
-
-#include <linux/soc/zte/rpmsg.h>
-#include <uapi/linux/rpmsg/rpmsg_zx29.h>
-#include "icp_dev.h"
-#include "icp_rpmsg.h"
-
-typedef struct _zx29_rpmsg_channel
-{
- T_RpMsg_CoreID actorID;
- T_RpMsg_ChID chID;
- void * buf;
- unsigned int len;
-} zx29_rpmsg_channel;
-
-typedef struct _zx29_rpmsg_ser
-{
- struct kref kref; /* Reference management */
- struct cdev cdev;
- struct module *owner;
- const char *driver_name;
- const char *name;
- int name_base;
- int major;
- int minor_start;
- int num;
- int flags;
- int index;
- int count;
- zx29_rpmsg_channel *rpmsg_channel;
-
- const struct file_operations *ops;
-} zx29_rpmsg_ser;
-
-static int zx29_rpmsg_open(struct inode *inode, struct file *filp)
-{
- dev_t device = inode->i_rdev;
- T_RpMsg_ChID chID;
- zx29_rpmsg_ser *rpmsg_drv;
-
- rpmsg_drv = container_of (inode->i_cdev, zx29_rpmsg_ser, cdev);
-
- rpmsg_drv->count++;
- chID = (T_RpMsg_ChID)(MINOR(device) - rpmsg_drv->minor_start);
-
- filp->private_data = &(rpmsg_drv->rpmsg_channel[chID]);
-
- return 0;
-}
-
-static long zx29_rpmsg_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
-{
- int ret;
- T_RpMsg_Msg rpmsg;
-
- zx29_rpmsg_channel *rpmsg_channel = filp->private_data;
- rpmsg.coreID = rpmsg_channel->actorID;
- rpmsg.chID = rpmsg_channel->chID;
-
- switch(cmd)
- {
- case RPMSG_CREATE_CHANNEL:
- ret = rpmsgCreateChannel(rpmsg.coreID, rpmsg.chID, (unsigned int)arg);
- if(ret != RPMSG_SUCCESS)
- {
- printk("CreateChannel(actID=%d)(chId=%d) failed(%d). \n",
- rpmsg_channel->actorID, rpmsg_channel->chID, ret);
- return -ENXIO;
- }
- break;
-
- case RPMSG_GET_DATASIZE:
- ret = rpmsg_rcv_chan_size(rpmsg.coreID, rpmsg.chID);
-
- if (copy_to_user((void __user *)arg, &ret, sizeof(ret)))
- return -EFAULT;
-
- break;
-
- case RPMSG_SET_INT:
- icpdev_set_int(rpmsg.coreID, rpmsg.chID);
- break;
-
- case RPMSG_SET_INT_FLAG:
- rpmsg_set_flag_int(rpmsg.coreID, rpmsg.chID, 1);
- break;
-
- case RPMSG_CLEAR_INT_FLAG:
- rpmsg_set_flag_int(rpmsg.coreID, rpmsg.chID, 0);
- break;
-
- case RPMSG_SET_POLL_FLAG:
- rpmsg_set_flag_poll(rpmsg.coreID, rpmsg.chID, 1);
- break;
-
- case RPMSG_CLEAR_POLL_FLAG:
- rpmsg_set_flag_poll(rpmsg.coreID, rpmsg.chID, 0);
- break;
-
- default:
- return -EPERM;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_COMPAT
-static long zx29_rpmsg_ioctl_compat(struct file *filp, unsigned int cmd, unsigned long arg)
-{
- if (_IOC_TYPE(cmd) != RPMSG_IOC_MAGIC)
- return -ENOTTY;
-
- if (_IOC_SIZE(cmd) == sizeof(compat_uptr_t)) {
- cmd &= ~IOCSIZE_MASK;
- cmd |= sizeof(char *) << IOCSIZE_SHIFT;
- }
-
- return zx29_rpmsg_ioctl(filp, cmd, (unsigned long)compat_ptr(arg));
-}
-#endif
-
-static ssize_t zx29_rpmsg_write(struct file *filp, const char __user *ubuf,
- size_t len, loff_t *ppos)
-{
- int ret;
- unsigned int flag;
- T_RpMsg_Msg rpmsg;
-
- zx29_rpmsg_channel *rpmsg_channel = filp->private_data;
- rpmsg.coreID = rpmsg_channel->actorID;
- rpmsg.chID = rpmsg_channel->chID;
- rpmsg.len = len;
- rpmsg.flag = 0;
-
- rpmsg.buf = kmalloc(len, GFP_KERNEL);
- if (rpmsg.buf == NULL)
- {
- printk("zx29_rpmsg_write1 kmalloc failed\n");
- return 0;
- }
-
- ret = copy_from_user(rpmsg.buf, ubuf, len);
- if (ret<0)
- {
- printk("zx29_rpmsg_write1(actID=%d)(chId=%d) len=%d failed(%d). \n",
- rpmsg_channel->actorID, rpmsg_channel->chID, len, ret);
- kfree(rpmsg.buf);
- return -EFAULT;
- }
-
-
- flag = rpmsg_get_flag(rpmsg.coreID, rpmsg.chID);
- if (flag&CHANNEL_INT_FLAG)
- rpmsg.flag |= RPMSG_WRITE_INT;
-
- ret = rpmsgWrite(&rpmsg);
- kfree(rpmsg.buf);
-
- if (ret<0)
- {
- printk("zx29_rpmsg_write2(actID=%d)(chId=%d) len=%d failed(%d). \n",
- rpmsg_channel->actorID, rpmsg_channel->chID, len, ret);
- return 0;
- }
-
- return len;
-}
-
-static ssize_t zx29_rpmsg_read(struct file *filp, char __user *ubuf,
- size_t len, loff_t *offp)
-{
- unsigned int size;
- int ret;
- unsigned int flag;
- T_RpMsg_Msg rpmsg;
-
- zx29_rpmsg_channel *rpmsg_channel = filp->private_data;
- rpmsg.coreID = rpmsg_channel->actorID;
- rpmsg.chID = rpmsg_channel->chID;
- rpmsg.len = len;
- rpmsg.flag = 0;
-
- rpmsg.buf = kmalloc(len, GFP_KERNEL);
- if (rpmsg.buf == NULL)
- {
- printk("zx29_rpmsg_read1 kmalloc failed\n");
- return 0;
- }
-
- flag = rpmsg_get_flag(rpmsg.coreID, rpmsg.chID);
- if (flag&CHANENL_POLL_FLAG)
- rpmsg.flag |= RPMSG_READ_POLL;
-
- ret = rpmsgRead(&rpmsg);
- if (ret<0)
- {
- printk("zx29_rpmsg_read1(actID=%d)(chId=%d) len=%d failed(%d). \n",
- rpmsg_channel->actorID, rpmsg_channel->chID, len, ret);
- kfree(rpmsg.buf);
- return 0;
- }
- else
- size = ret;
-
- ret = copy_to_user(ubuf, rpmsg.buf, size);
- kfree(rpmsg.buf);
- if (ret<0)
- {
- printk("zx29_rpmsg_read2(actID=%d)(chId=%d) len=%d failed(%d). \n",
- rpmsg_channel->actorID, rpmsg_channel->chID, len, ret);
- return -EFAULT;
- }
-
- return size;
-}
-
-static unsigned int zx29_rpmsg_poll(struct file *file,
- struct poll_table_struct *wait)
-{
- zx29_rpmsg_channel *rpmsg_channel = file->private_data;
-
- return rpmsg_poll(file, rpmsg_channel->actorID, rpmsg_channel->chID, wait);
-}
-
-
-int zx29_rpmsg_release(struct inode *inode, struct file *filp)
-{
- filp->private_data = NULL;
-
- return 0;
-}
-
-static const struct file_operations rpmsg_zx29_ops = {
- .owner = THIS_MODULE,
- .open = zx29_rpmsg_open,
- .release = zx29_rpmsg_release,
- .write = zx29_rpmsg_write,
- .read = zx29_rpmsg_read,
- .unlocked_ioctl = zx29_rpmsg_ioctl,
-#ifdef CONFIG_COMPAT
- .compat_ioctl = zx29_rpmsg_ioctl_compat,
-#endif
- .poll = zx29_rpmsg_poll,
-};
-
-struct class *rpmsg_classes;
-
-zx29_rpmsg_ser rpmsg_zx29 = {
- .owner = THIS_MODULE,
- .driver_name = "armps_rpmsg",
- .name = "armps_rpmsgch", //ps_rpmsgch
- .major = 0,
- .minor_start = 30,
-};
-
-struct device *zx29_rpmsg_register_device(struct class *rpmsg_class, zx29_rpmsg_ser *driver, unsigned index,
- struct device *device)
-{
- char name[64];
- dev_t dev = MKDEV(driver->major, driver->minor_start) + index;
-
- if (index >= driver->num) {
- return ERR_PTR(-EINVAL);
- }
-
- sprintf(name, "%s%d", driver->name, index);
-
- return device_create(rpmsg_class, device, dev, NULL, name);
-}
-
-static int zx29_rpmsg_probe(struct device *dev)
-{
- int error;
- int i;
- dev_t rpmsg_devt;
- zx29_rpmsg_ser *rpmsg_ser ;
-
- rpmsg_ser = &rpmsg_zx29;
-
- rpmsg_ser->rpmsg_channel = devm_kcalloc(dev, rpmsg_ser->num,
- sizeof(zx29_rpmsg_channel),
- GFP_KERNEL);
- if (!rpmsg_ser->rpmsg_channel)
- return -ENOMEM;
-
- rpmsg_ser->ops = &rpmsg_zx29_ops;
- rpmsg_ser->count = 0;
-
- error = alloc_chrdev_region(&rpmsg_devt, rpmsg_ser->minor_start,
- rpmsg_ser->num, rpmsg_ser->name);
- if (!error) {
- rpmsg_ser->major = MAJOR(rpmsg_devt);
- rpmsg_ser->minor_start = MINOR(rpmsg_devt);
- }
-
- cdev_init(&rpmsg_ser->cdev, &rpmsg_zx29_ops);
- rpmsg_ser->cdev.owner = rpmsg_ser->owner;
-
- error = cdev_add(&rpmsg_ser->cdev, rpmsg_devt, rpmsg_ser->num);
- if (error) {
- unregister_chrdev_region(rpmsg_devt, rpmsg_ser->num);
- return error;
- }
-
- for (i = 0; i < rpmsg_ser->num; i++) {
- rpmsg_ser->rpmsg_channel[i].actorID = dev->id;
- rpmsg_ser->rpmsg_channel[i].chID = i;
- zx29_rpmsg_register_device(rpmsg_classes, rpmsg_ser, i, NULL);
- }
-
- return 0;
-}
-
-static struct attribute *rpmsg_zx29_dev_attrs[] = {
- NULL,
-};
-ATTRIBUTE_GROUPS(rpmsg_zx29_dev);
-
-struct bus_type icp_rpmsg_bus = {
- .name = "rpmsg_zx29",
-// .dev_groups = rpmsg_zx29_dev_groups,
-};
-
-static struct device_driver rpmsg_zx29_drv={
- .name = "icp_rpmsg2",
- .owner = THIS_MODULE,
- .bus= &icp_rpmsg_bus,
- .probe = zx29_rpmsg_probe,
-};
-
-void zx29_rpmsg_unregister_device(struct class *rpmsg_class, zx29_rpmsg_ser *driver, unsigned index)
-{
- dev_t dev = MKDEV(driver->major, driver->minor_start) + index;
-
- device_destroy(rpmsg_class, dev);
-}
-
-int icp_rpmsg_device_register(struct device *dev, unsigned int channel_count)
-{
- int ret;
-
- ret = bus_register(&icp_rpmsg_bus);
- if(ret < 0)
- return ret;
-
- rpmsg_zx29.num = channel_count;
-
- dev->bus = &icp_rpmsg_bus;
- dev_set_name(dev, "icp_rpmsg%d", dev->id);
- ret = device_register(dev);
-
- return ret;
-}
-
-static int __init zx29_rpmsg_init(void)
-{
- int ret = 0;
- rpmsg_classes = class_create(THIS_MODULE, "rpm");
-
- if (IS_ERR(rpmsg_classes))
- return PTR_ERR(rpmsg_classes);
-
- ret = driver_register(&rpmsg_zx29_drv);
- if(ret < 0)
- printk("rpmsg_zx29 init failed!");
-
- //rpmsg_sram_init();
-
- return ret;
-}
-
-static void __exit zx29_rpmsg_exit(void)
-{
- int i;
- zx29_rpmsg_ser *rpmsg_ser;
-
- rpmsg_ser = &rpmsg_zx29;
-
- for (i = 0; i < rpmsg_ser->num; i++)
- zx29_rpmsg_unregister_device(rpmsg_classes, rpmsg_ser, i);
-
- class_destroy(rpmsg_classes);
-}
-
-late_initcall(zx29_rpmsg_init);
-module_exit(zx29_rpmsg_exit);
-
-MODULE_AUTHOR("zte");
-MODULE_DESCRIPTION("zte rpmsg driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform: rpmsg");
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/zx29_icp.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/zx29_icp.c
deleted file mode 100644
index 379ff4a..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/zx29_icp.c
+++ /dev/null
@@ -1,404 +0,0 @@
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/syscore_ops.h>
-#include <linux/gpio.h>
-#include <linux/of_device.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_runtime.h>
-#include <linux/soc/zte/common.h>
-#include <linux/soc/zte/spinlock.h>
-
-#include "icp_dev.h"
-#include "zx29_icp.h"
-#include "icp_rpmsg.h"
-
-static icp_callback_fn _icp_fn;
-static T_HalIcp_Reg *icp_ap2m0_reg;
-static T_HalIcp_Reg *icp_ap2ps_reg;
-
-static inline T_HalIcp_Reg *icp_get_reg(T_ZDrvRpMsg_ActorID actor_id)
-{
- if (CORE_M0 == actor_id )
- return icp_ap2m0_reg;
- else if (CORE_PS0 == actor_id )
- return icp_ap2ps_reg;
- else
- BUG();
-}
-
-/*******************************************************************************
-* Function: icp_set_int
-* Description: This function is used for generating icp interrupt to inform remote cpu;
-* Parameters:
-* Input:
- actorID: id of remote cpu
- chID: id of channel
-* Output:None
-*
-* Returns:None
-*
-*
-* Others:
-********************************************************************************/
-static int icp_set_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
-{
- T_HalIcp_Reg *icp_reg;
-
- if ((actorID >= CORE_MAXID) || (chID >= CHANNEL_MAXID(actorID)))
- return -EINVAL;
-
- icp_reg = icp_get_reg(actorID);
-
- if(chID<32)
- icp_reg->control.low_word = (1<<chID);
- else
- icp_reg->control.high_word = (1<<(chID-32));
-
- return 0;
-}
-
-/*******************************************************************************
-* Function: icp_clear_int
-* Description: This function is used for clear icp interrupt from remote cpu;
-* Parameters:
-* Input:
- actorID: id of remote cpu
- chID: id of channel
-* Output:None
-*
-* Returns:None
-*
-*
-* Others:
-********************************************************************************/
-static void icp_clear_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
-{
- T_HalIcp_Reg *icp_reg = icp_get_reg(actorID);
-
- if(chID<32)
- icp_reg->clear.low_word = (1<<chID);
- else
- icp_reg->clear.high_word = (1<<(chID-32)) ;
-}
-
-/*******************************************************************************
-* Function: icp_get_int
-* Description: This function is used for get icp interrupt from remote cpu;
-* Parameters:
-* Input:
-* actorID: id of remote cpu
-* chID: id of channel
-* Output:None
-*
-* Returns:None
-*
-*
-* Others:
-********************************************************************************/
-static T_HalIcp_Dword icp_get_int(T_ZDrvRpMsg_ActorID actorID)
-{
- T_HalIcp_Dword IcpState;
- T_HalIcp_Reg *icp_reg;
-
- if (actorID >= CORE_MAXID)
- {
- IcpState.high_word = 0;
- IcpState.low_word = 0;
-
- return IcpState;
- }
-
- icp_reg = icp_get_reg(actorID);
-
- IcpState.high_word = icp_reg->state.high_word;
- IcpState.low_word = icp_reg->state.low_word;
-
- return IcpState;
-}
-
-/*******************************************************************************
-* Function: icp_get_int_state
-* Description: This function is used for get the state of icp interruptting of remote cpu;
-* Parameters:
-* Input:
- actorID: id of remote cpu
- chID: id of channel
-* Output:None
-*
-* Returns:None
-*
-*
-* Others:
-********************************************************************************/
-static int icp_get_int_state(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
-{
- T_HalIcp_Reg *icp_reg;
-
- icp_reg = icp_get_reg(actorID);
-
- if(chID<32)
- {
- if(icp_reg->in_state.low_word & (0x1<<chID))
- return true;
- }
- else
- {
- if(icp_reg->in_state.high_word & (0x1<<(chID-32)))
- return true;
- }
-
- return false;
-}
-
-/*******************************************************************************
-* Function: icp_mask_int
-* Description: This function is used for Mask interrupt of channel;
-* Parameters:
-* Input:
-* Output:
-*
-* Returns: NONE
-*
-*
-* Others:
-********************************************************************************/
-static int icp_mask_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
-{
- T_HalIcp_Reg *icp_reg;
-
- if ((actorID >= CORE_MAXID) || (chID >= CHANNEL_MAXID(actorID)))
- return -EINVAL;
-
- icp_reg = icp_get_reg(actorID);
-
- if(chID<32)
- icp_reg->mask.low_word |= (0x1<<chID);
- else
- icp_reg->mask.high_word |= (0x1<<(chID-32));
-
- return 0;
-}
-
-/*******************************************************************************
-* Function: icp_unmask_int
-* Description: This function is used for unmask interrupt of channel;
-* Parameters:
-* Input:
-* Output:
-*
-* Returns:
-* NONE
-*
-*
-* Others:
-********************************************************************************/
-static int icp_unmask_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
-{
- T_HalIcp_Reg *icp_reg;
-
- if ((actorID >= CORE_MAXID) || (chID >= CHANNEL_MAXID(actorID)))
- return -EINVAL;
-
- icp_reg = icp_get_reg(actorID);
-
- if(chID < 32)
- icp_reg->mask.low_word &= ~(0x1<<chID);
- else
- icp_reg->mask.high_word &= ~(0x1<<(chID-32));
-
- return 0;
-}
-
-int icp_int_count = 0;
-irqreturn_t icp_isr(int irq, void *data)
-{
- icp_msg _icp_msg;
- T_HalIcp_Dword IcpState;
- unsigned int i;
-
- _icp_msg.src_id = (unsigned int)data;
-
- IcpState = icp_get_int(_icp_msg.src_id);
-
- for(i=0; i<CHANNEL_MAXID(_icp_msg.src_id); i++)
- {
- if((((i<32)&&((IcpState.low_word>>i) & 0x1))||((i>=32)&&((IcpState.high_word>>(i-32)) & 0x1)))) {
- _icp_msg.event_id = i;
- if(_icp_fn)
- _icp_fn(&_icp_msg);
-
- icp_clear_int(_icp_msg.src_id, i);
- }
- }
-
- icp_int_count ++;
-
- return IRQ_HANDLED;
-}
-
-/*
- * for loopback test
- */
-void fake_icp_isr(T_RpMsg_CoreID src_core, T_RpMsg_CoreID dest_core, T_RpMsg_ChID ch)
-{
- icp_msg _icp_msg;
- unsigned int i;
-
- _icp_msg.src_id = src_core;
- _icp_msg.dest_core = dest_core;
- _icp_msg.event_id = ch;
-
- if(_icp_fn)
- _icp_fn(&_icp_msg);
-}
-
-static void icp_register_callback(icp_callback_fn cb)
-{
- _icp_fn = cb;
-}
-
-static int icp_send_message(unsigned int core_id, icp_msg *icp_msg)
-{
- if(icp_msg->dest_core > CORE_MAXID || !icp_msg)
- return -EINVAL;
-
- if(icp_get_int_state(icp_msg->dest_core, icp_msg->event_id)==false)
- {
- icp_set_int(icp_msg->dest_core, icp_msg->event_id);
- }
-
- return 0;
-}
-
-static t_icpdev_ops zx29_icp_ops = {
- .register_callback = icp_register_callback,
- .send_message = icp_send_message,
- .mask_int = icp_mask_int,
- .unmask_int = icp_unmask_int,
- .set_int = icp_set_int,
-};
-
-static int icp_ap2ps_init(struct device *dev)
-{
- void __iomem *reg_base;
- unsigned int irq;
- int ret;
- struct device_node *np = dev->of_node;
-
- reg_base = of_iomap(np, 0);
- if ( !reg_base ){
- pr_err("%s: [ICP]Cannot get IORESOURCE_MEM\n", __func__);
- return -ENOENT;
- }
-
- icp_ap2ps_reg = (T_HalIcp_Reg *)reg_base;
-
- irq = irq_of_parse_and_map(np, 0);
- if( !irq ){
- pr_err("%s: [ICP]Cannot get IORESOURCE_IRQ\n", __func__);
- return -ENOENT;
- }
-
- icp_ap2ps_reg->mask.high_word = 0xffffffff;
- icp_ap2ps_reg->mask.low_word = 0xffffffff;
-
- ret = request_irq(irq, icp_isr, 0, "zx_icp", CORE_PS0);
- if (ret)
- {
- pr_err("%s: [ICP]register irq failed\n", __func__);
- return ret;
- }
-
- enable_irq_wake(irq);
-
- icpdev_register_ops(&zx29_icp_ops);
-
- rpmsgInit(CORE_PS0, np);
-/*
- dev->id = CORE_PS0;
- ret = icp_rpmsg_device_register(dev);
-*/
- pr_info("%s: ok! irq(%d) icp_address(%llx \n", __func__, irq, reg_base );
-
- return ret;
-}
-
-static int icp_ap2m0_init(struct device *dev)
-{
- void __iomem *reg_base;
- unsigned int irq;
- int ret;
- struct device_node *np = dev->of_node;
-
- pr_info("%s: enter \n", __func__);
-
- reg_base = of_iomap(np, 0);
- if ( !reg_base ){
- pr_err("%s: [ICP]Cannot get IORESOURCE_MEM\n", __func__);
- return -ENOENT;
- }
-
- icp_ap2m0_reg = (T_HalIcp_Reg *)reg_base;
-
- irq = irq_of_parse_and_map(np, 0);
- if( !irq ){
- pr_err("%s: [ICP]Cannot get IORESOURCE_IRQ\n", __func__);
- return -ENOENT;
- }
-
- icp_ap2m0_reg->mask.high_word = 0xffffffff;
- icp_ap2m0_reg->mask.low_word = 0xffffffff;
-
- ret = request_irq(irq, icp_isr, 0, "zx_icp", CORE_M0);
- if (ret)
- {
- pr_err("%s: [ICP]register irq failed\n", __func__);
- return ret;
- }
-
- icpdev_register_ops(&zx29_icp_ops);
-
- rpmsgInit(CORE_M0, np);
-
- pr_info("%s: ok! irq(%d) icp_address(%llx \n", __func__, irq, reg_base );
-
- return 0;
-}
-
-static const struct of_device_id zx29_icp_dt_ids[] = {
- { .compatible = "zte,zx29-icp-ap2m0", .data = &icp_ap2m0_init },
- { .compatible = "zte,zx29-icp-ap2ps", .data = &icp_ap2ps_init },
- { /* sentinel */ }
-};
-
-static int zx29_icp_probe(struct platform_device *pdev)
-{
- int (*init_fn)(struct device *dev);
-
- init_fn = of_device_get_match_data(&pdev->dev);
- if (!init_fn) {
- dev_err(&pdev->dev, "Error: No device match found\n");
- return -ENODEV;
- }
-
- return init_fn(&pdev->dev);
-}
-
-static struct platform_driver zx29_icp_driver = {
- .driver = {
- .name = "zx29-icp",
- .owner = THIS_MODULE,
- .of_match_table = of_match_ptr(zx29_icp_dt_ids),
- },
- .probe = zx29_icp_probe,
-};
-
-builtin_platform_driver(zx29_icp_driver)
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/zx29_icp.h b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/zx29_icp.h
deleted file mode 100644
index 1cd7a79..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/rpmsg/zx29_icp.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*---------------------------------------------------------------------------------------------------------------------
- * °æȨËùÓÐ(C)2000-2017, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾
- *
- * ÎÄ ¼þ Ãû: zx29_icp.h
- *
- *
- * ½Ó¿ÚÃèÊö:
- * ICPÄ£¿éµÄ¼Ä´æÆ÷Í·Îļþ(zx29ϵÁÐоƬ)
- *
- * °æ ±¾: v0.0
- *
- *
- *-------------------------------------------------------------------------------------------------------------------*/
-
-
-#ifndef _ZX29_ICP_H
-#define _ZX29_ICP_H
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-#define MAX_MB_NAME_LEN (12)
-
-#define T_ZDrvRpMsg_ActorID T_RpMsg_CoreID
-#define T_ZDrvRpMsg_ChID T_RpMsg_ChID
-
-typedef struct _T_HalIcp_Dword{
- unsigned int low_word;
- unsigned int high_word;
-}T_HalIcp_Dword;
-
-typedef struct _T_HalIcp_Reg{
- volatile T_HalIcp_Dword control;
- T_HalIcp_Dword state;
- volatile T_HalIcp_Dword clear;
- volatile T_HalIcp_Dword mask;
- volatile T_HalIcp_Dword sfn;
- T_HalIcp_Dword in_state;
-} T_HalIcp_Reg;
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-
-#endif /* _ZX29_ICP_H */
-
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/spinlock/Kconfig b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/spinlock/Kconfig
deleted file mode 100644
index 7262f15..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/spinlock/Kconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-#
-#
-#
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/spinlock/Makefile b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/spinlock/Makefile
deleted file mode 100644
index b6df879..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/spinlock/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for the soc plat drivers
-#
-
-obj-$(CONFIG_ARCH_ZX298501) += spinlock.o
-obj-$(CONFIG_ARCH_ZX297520V3) += spinlock-zx297520v3.o
-#
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/spinlock/spinlock-zx297520v3.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/spinlock/spinlock-zx297520v3.c
deleted file mode 100644
index 99d3fb7..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/spinlock/spinlock-zx297520v3.c
+++ /dev/null
@@ -1,513 +0,0 @@
-/*
- * arch/arm/mach-zx297520v2/zx297520v2-clock.c
- *
- * Copyright (C) 2015 ZTE-TSP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/of_device.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/mutex.h>
-#include <linux/device.h>
-#include <linux/module.h>
-#include <linux/cdev.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/soc/zte/spinlock.h>
-
-#define USE_HW_SPINLOCK 1
-
-#define SHARED_DEVICE_REG1 (hwlock_reg_base + 0x170)
-#define SHARED_DEVICE_REG2 (hwlock_reg_base + 0x174)
-#define SHARED_DEVICE_REG3 (hwlock_reg_base + 0x178)
-#define SHARED_DEVICE_REG4 (hwlock_reg_base + 0x17C)
-
-#if USE_HW_SPINLOCK
-
-#define MACH_NR_SFLOCKS SFLOCK_NUM
-#define MACH_NR_HWLOCKS HWLOCK_NUM
-
-#define SELF_CORE_ID CORE_ID_AP
-
-/* now use 8*MACH_NR_SFLOCKS bytes */
-#define SOFTLOCK_DESC_BASE (sf_base)//(SPINLOCK_SOFTLOCK_BASE)
-
-#define SPINLOCK_DEBUG 1
-
-#if SPINLOCK_DEBUG
-#define zspinlock_debug(fmt, ...) \
- printk(KERN_INFO fmt, ##__VA_ARGS__)
-#else
-#define zspinlock_debug(fmt, ...)
-#endif
-
-#define zspinlock_assert(_EXP) BUG_ON(!_EXP)//ZDRV_ASSERT(_EXP)
-static DEFINE_MUTEX(zspinlock_mutex);
-static unsigned long s_hwSpinlockMsr;
-/****************************************************************************
-* Types
-****************************************************************************/
-struct zte_softlock_desc {
- unsigned long used;
- unsigned long owner;
-};
-/**************************************************************************
- * Global Variables *
- **************************************************************************/
-static volatile struct zte_softlock_desc *softlock_desc[MACH_NR_SFLOCKS];
-static void __iomem __force *hwlock_reg_base;
-static void __iomem __force *sf_base;
-static void __iomem __force *hwlock_regs[MACH_NR_HWLOCKS] ;
-/*
-=
-{
- SHARED_DEVICE_REG1,
- SHARED_DEVICE_REG2,
- SHARED_DEVICE_REG3,
- SHARED_DEVICE_REG4
-};
-*/
-extern void msleep(unsigned int msecs);
-
- /*******************************************************************************
- * Function: _hw_spin_lock
- * Description:»ñÈ¡Ó²¼þËø£¬id 0~3
- * Parameters:
- * Input:
- *
- * Output:
- *
- * Returns:
- *
- *
- * Others:
- ********************************************************************************/
- static void _hw_spin_lock(unsigned long hwid)
-{
- unsigned long tmp;
- unsigned long msr;
- local_irq_save(msr);
- s_hwSpinlockMsr = msr;
-
- while(ioread32(hwlock_regs[hwid])&0x1);
- tmp = ioread32(hwlock_regs[hwid]);
- tmp &= 0x00ffffff;
- tmp |= (SELF_CORE_ID&0xff)<<24;
- iowrite32(tmp, hwlock_regs[hwid]);
-
-}
-/*******************************************************************************
- * Function: _hw_spin_unlock
- * Description:ÊÍ·ÅÓ²¼þËø£¬id 0~3
- * Parameters:
- * Input:
- *
- * Output:
- *
- * Returns:
- *
- *
- * Others:
- ********************************************************************************/
-static void _hw_spin_unlock(unsigned long hwid)
-{
- unsigned long tmp;
-
-
- if(SELF_CORE_ID != (ioread32(hwlock_regs[hwid])&0xff000000)>>24){
- zspinlock_assert(0);
- }
- tmp = ioread32(hwlock_regs[hwid]);
- tmp &= 0x00fffffe;
- iowrite32(tmp, hwlock_regs[hwid]);
-
- local_irq_restore(s_hwSpinlockMsr);
-}
-/*******************************************************************************
- * Function: hw_spin_lock
- * Description:»ñÈ¡Ó²¼þËø£¬id 0~2£¬
- * id 3±£Áô¸øÈí¼þËøʹÓã¬ÍⲿÇý¶¯²»¿ÉÓá£
- * Parameters:
- * Input:
- *
- * Output:
- *
- * Returns:
- *
- *
- * Others:
- ********************************************************************************/
-void hw_spin_lock(emhw_lock_id hwid)
-{
- _hw_spin_lock(hwid);
-// zspinlock_debug("cpu %d gets %d hardware lock!/n",SELF_CORE_ID,hwid);
-}
-/*******************************************************************************
- * Function: hw_spin_unlock
- * Description:Çý¶¯ÊÍ·ÅÓ²¼þËø£¬id 0~2
- * Parameters:
- * Input:
- *
- * Output:
- *
- * Returns:
- *
- *
- * Others:
- ********************************************************************************/
-void hw_spin_unlock(emhw_lock_id hwid)
-{
- _hw_spin_unlock(hwid);
-// zspinlock_debug("cpu %d releases %d hardware lock!/n",SELF_CORE_ID,hwid);
-}
-/*******************************************************************************
- * Function: soft_spin_lock
- * Description:Çý¶¯»ñµÃÈí¼þËø½Ó¿Ú
- * Parameters:
- * Input: sfid: Èí¼þËøid¡£
- * coreid: ±£³ÖidºÅΪsfidÈí¼þËøµÄcpuid¡£
- * Output:
- *
- * Returns:
- *
- *
- * Others:
- ********************************************************************************/
-void soft_spin_lock(emsf_lock_id sfid)
-{
- static unsigned long lock_count = 0;
-
-softlock_loop:
- while(softlock_desc[sfid]->owner != SELF_CORE_ID && softlock_desc[sfid]->used)
- {
- lock_count++;
- if(lock_count == 1000)
- {
- lock_count = 0;
- msleep(5);
- }
- }
-
- _hw_spin_lock(SOFTLOCK_HWLOCK);
- if(softlock_desc[sfid]->owner != SELF_CORE_ID && softlock_desc[sfid]->used)
- {
- _hw_spin_unlock(SOFTLOCK_HWLOCK);
- goto softlock_loop;
- }
- softlock_desc[sfid]->used ++;
- softlock_desc[sfid]->owner = SELF_CORE_ID;
- _hw_spin_unlock(SOFTLOCK_HWLOCK);
- //zspinlock_debug("cpu %d releases %d software lock!/n",SELF_CORE_ID,sfid);
-
-}
-#if 1
-int soft_spin_lock_printf(emsf_lock_id sfid)
-{
- static unsigned long lock_count = 0;
-softlock_loop:
- while(softlock_desc[sfid]->owner != SELF_CORE_ID && softlock_desc[sfid]->used)
- {
- ndelay(1);
- lock_count++;
- if(lock_count >= 5000)
- {
- lock_count = 0;
- return -1;
- }
- }
- _hw_spin_lock(SOFTLOCK_HWLOCK);
- if(softlock_desc[sfid]->owner != SELF_CORE_ID && softlock_desc[sfid]->used)
- {
- _hw_spin_unlock(SOFTLOCK_HWLOCK);
- goto softlock_loop;
- }
- softlock_desc[sfid]->used ++;
- softlock_desc[sfid]->owner = SELF_CORE_ID;
- _hw_spin_unlock(SOFTLOCK_HWLOCK);
- return 0;
-}
-#endif
-/*******************************************************************************
- * Function: soft_spin_unlock
- * Description:Óësoft_spin_lock¶ÔÓ¦µÄÊÍ·ÅÈí¼þËø½Ó¿Ú¡£
- * Parameters:
- * Input:
- *
- * Output:
- *
- * Returns:
- *
- *
- * Others:
- ********************************************************************************/
- void soft_spin_unlock(emsf_lock_id sfid)
-{
- if(softlock_desc[sfid]->used){
- if(SELF_CORE_ID != softlock_desc[sfid]->owner){
- zspinlock_assert(0);
- }
- _hw_spin_lock(SOFTLOCK_HWLOCK);
- softlock_desc[sfid]->used --;
- if(softlock_desc[sfid]->used == 0) {
- softlock_desc[sfid]->owner = 0x0;
- }
- _hw_spin_unlock(SOFTLOCK_HWLOCK);
- //zspinlock_debug("cpu %d releases %d software lock!/n",SELF_CORE_ID,sfid);
- }
-}
-
-/*******************************************************************************
- * Function: soft_spin_lock_psm
- * Description:Çý¶¯»ñµÃÈí¼þËø½Ó¿Ú
- * Parameters:
- * Input: sfid: Èí¼þËøid¡£
- * coreid: ±£³ÖidºÅΪsfidÈí¼þËøµÄcpuid¡£
- * Output:
- *
- * Returns:
- *
- *
- * Others:
- ********************************************************************************/
-void soft_spin_lock_psm(emsf_lock_id sfid)
-{
-softlock_loop:
- while(softlock_desc[sfid]->owner != SELF_CORE_ID && softlock_desc[sfid]->used)
- {
-
- }
-
- _hw_spin_lock(SOFTLOCK_HWLOCK);
- if(softlock_desc[sfid]->owner != SELF_CORE_ID && softlock_desc[sfid]->used)
- {
- _hw_spin_unlock(SOFTLOCK_HWLOCK);
- goto softlock_loop;
- }
- softlock_desc[sfid]->used ++;
- softlock_desc[sfid]->owner = SELF_CORE_ID;
- _hw_spin_unlock(SOFTLOCK_HWLOCK);
- //zspinlock_debug("cpu %d releases %d software lock!/n",SELF_CORE_ID,sfid);
-
-}
-
-/*******************************************************************************
- * Function: soft_spin_unlock_psm
- * Description:Óësoft_spin_lock_psm¶ÔÓ¦µÄÊÍ·ÅÈí¼þËø½Ó¿Ú¡£
- * Parameters:
- * Input:
- *
- * Output:
- *
- * Returns:
- *
- *
- * Others:
- ********************************************************************************/
-void soft_spin_unlock_psm(emsf_lock_id sfid)
-{
- soft_spin_unlock(sfid);
-}
-
-/*******************************************************************************
- * Function: reg_spin_lock
- * Description:Çý¶¯»ñµÃ¼Ä´æÆ÷Ëø½Ó¿Ú
- * Parameters:
- * Input:
- * Output:
- *
- * Returns:
- *
- *
- * Others:
- ********************************************************************************/
-void reg_spin_lock(void)
-{
- _hw_spin_lock(REGLOCK_HWLOCK);
- softlock_desc[REG_SFLOCK]->owner = SELF_CORE_ID;
-}
-EXPORT_SYMBOL(reg_spin_lock);
-
-/*******************************************************************************
- * Function: reg_spin_unlock
- * Description:Óëreg_spin_lock¶ÔÓ¦µÄÊͷżĴæÆ÷Ëø½Ó¿Ú¡£
- * Parameters:
- * Input:
- *
- * Output:
- *
- * Returns:
- *
- *
- * Others:
- ********************************************************************************/
- void reg_spin_unlock(void)
-{
- softlock_desc[REG_SFLOCK]->owner = 0x0;
- _hw_spin_unlock(REGLOCK_HWLOCK);
-
-}
-EXPORT_SYMBOL(reg_spin_unlock);
-
-/*******************************************************************************
- * Function: softspinlock_init
- * Description:Èí¼þËø³õʼ»¯¡£
- * Parameters:
- * Input:
- *
- * Output:
- *
- * Returns:
- *
- *
- * Others:
- ********************************************************************************/
-int softspinlock_init(void)
-{
- int i;
-
- for(i = 0; i<MACH_NR_SFLOCKS; i++){
- softlock_desc[i] =
- (struct zte_softlock_desc *)(SOFTLOCK_DESC_BASE +i*sizeof(struct zte_softlock_desc));
- //softlock_desc[i]->used = 0;
- //softlock_desc[i]->owner= CORE_ID_NUM;
- }
- zspinlock_debug("softspinlock init success base=0x%x!",(int)SOFTLOCK_DESC_BASE);
- return 0;
-}
-
-typedef struct _zx29_softspinlock_ser
-{
- struct cdev cdev;
- struct module *owner;
- struct class *classes;
- const struct file_operations *ops;
-}zx29_softspinlock_ser;
-
-static zx29_softspinlock_ser softspinlock_zx29 = {
- .owner = THIS_MODULE,
-};
-
-int soft_spin_lock_get(emsf_lock_id sfid)
-{
- if(sfid>=SFLOCK_NUM)
- return -EFAULT;
-
- if(softlock_desc[sfid]->owner != SELF_CORE_ID && softlock_desc[sfid]->used)
- return 1;
- else
- return 0;
-}
-
-static long softspinlock_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
-{
- int ret = 0;
- char k_arg;
-
- switch(cmd)
- {
- case SPINLOCK_GET_STATUS:
- ret = copy_from_user(&k_arg, arg, sizeof(char));
- if (ret)
- return -EFAULT;
-
- if(k_arg>= SFLOCK_NUM)
- return -EFAULT;
-
- k_arg = (char)soft_spin_lock_get(k_arg);
- ret = copy_to_user(arg,&k_arg, sizeof(char));
- if (ret)
- return -EFAULT;
- break;
- default:
- return -EPERM;
- }
-
- return ret;
-}
-
-
-static const struct file_operations softspinlock_ops = {
- .owner = THIS_MODULE,
- .unlocked_ioctl = softspinlock_ioctl,
-};
-
-
-static int __init softspinlock_dev_init(void)
-{
- int ret = 0;
- dev_t dev;
-
- softspinlock_zx29.ops = &softspinlock_ops;
-
- ret = alloc_chrdev_region(&dev, 0, 1, "softspinlock");
- if (ret)
- {
- printk(KERN_ERR "%s: softspinlock failed to allocate char dev region\n",
- __FILE__);
- return ret;
- }
-
- cdev_init(&softspinlock_zx29.cdev, &softspinlock_ops);
- softspinlock_zx29.cdev.owner = softspinlock_zx29.owner;
-
- ret = cdev_add(&softspinlock_zx29.cdev, dev, 1);
- if (ret)
- {
- unregister_chrdev_region(dev, 1);
- printk(KERN_ERR "%s: softspinlock failed to add cdev\n",
- __FILE__);
- return ret;
- }
-
- softspinlock_zx29.classes = class_create(THIS_MODULE, "softspinlock");
- if (IS_ERR(softspinlock_zx29.classes))
- return PTR_ERR(softspinlock_zx29.classes);
-
- device_create(softspinlock_zx29.classes, NULL, dev, NULL, "softspinlock");
-
- printk("[xxx] softspinlock dev inited! \n");
-
- return ret;
-}
-
-void zx_spinlock_init(void __iomem *spinlock_base)
-{
- void __iomem **data = (void __iomem **)spinlock_base;
-
- hwlock_reg_base = data[0];
- sf_base = data[1];
-
- hwlock_regs[0] = SHARED_DEVICE_REG1;
- hwlock_regs[1] = SHARED_DEVICE_REG2;
- hwlock_regs[2] = SHARED_DEVICE_REG3;
- hwlock_regs[3] = SHARED_DEVICE_REG4;
-
- softspinlock_init();
-}
-
-//arch_initcall(softspinlock_init);
-#else
-int softspinlock_init(void){return 0;}
-void reg_spin_lock(void){}
-void reg_spin_unlock(void){}
-void soft_spin_lock(emsf_lock_id sfid){}
-void soft_spin_unlock(emsf_lock_id sfid){}
-void soft_spin_lock_psm(emsf_lock_id sfid){}
-void soft_spin_unlock_psm(emsf_lock_id sfid){}
-void hw_spin_lock(emhw_lock_id hwid){}
-void hw_spin_unlock(emhw_lock_id hwid){}
-static int __init softspinlock_dev_init(void){return 0;}
-#endif
-
-module_init(softspinlock_dev_init);
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/timer/Kconfig b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/timer/Kconfig
deleted file mode 100644
index 7262f15..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/timer/Kconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-#
-#
-#
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/timer/Makefile b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/timer/Makefile
deleted file mode 100644
index bfe9f4f..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/timer/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for the soc plat drivers
-#
-
-obj-$(CONFIG_ARCH_ZX298501) += timer-zx298501.o
-obj-$(CONFIG_ARCH_ZX297520V3) += timer-zx297520v3.o
-#
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/timer/timer-zx297520v3.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/timer/timer-zx297520v3.c
deleted file mode 100644
index 47b7414..0000000
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/soc/zte/timer/timer-zx297520v3.c
+++ /dev/null
@@ -1,742 +0,0 @@
-/*
- * drivers/soc/zte/timer/timer-zx29.c
- *
- * Copyright (C) 2015 ZTE-TSP
- *
- * -------------------------------------------------------------------------------------------------------------------- *//**
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/clocksource.h>
-#include <linux/sched_clock.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/syscore_ops.h>
-#include <linux/gpio.h>
-#include <linux/of_device.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_runtime.h>
-#include <linux/soc/zte/common.h>
-#include <dt-bindings/soc/zx297520v3-misc.h>
-
-#include <asm/mach/time.h>
-#include <linux/fs.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-
-/* timer register offset */
-#define CONFIG_REG (0x04)
-#define LOAD_REG (0x08)
-#define START_REG (0x0C)
-#define REFRESH_REG (0x10)
-#define ACK_REG (0x14)
-#define CUR_VALUE (0x18)
-
-#define TIMER_PRESCALE(ptv) (ptv << 5)
-#define TIMER_AUTORELOAD (1 << 1)
-
-#define NR_ZX_TIMER (5)
-#define ZX_TIMER_DEFAULT_RATE (26000000)
-#define ZX_TIMER_WIDTH (32)
-#define ZX_TIMER_MASK UINT_MAX
-
-typedef enum
-{
- TIMER0 = 0,
- TIMER1 = 1,
- NUM_TIMERS
-} zx_timer_id;
-
-typedef void (*zx_timer_cb)(unsigned long data);
-
-typedef struct
-{
- void __iomem *reg;
- struct clk *wclk;
- struct clk *pclk;
-
- unsigned int freq; /* wclk freq */
- unsigned int irq;
-
- unsigned int interval;
- unsigned int cycle_cnt;
- zx_timer_cb cb;
- unsigned long cb_param;
- struct clock_event_device clkevt;
- struct clocksource *cs;
-
- struct device_node *np;
-
- unsigned int func; /* ce cs dt or common */
-
-} t_timer_info;
-
-typedef struct
-{
- t_timer_info info[NR_ZX_TIMER];
- unsigned int nr;
-} t_timer_contexts;
-
-
-t_timer_contexts zx_timer_ctx = {0};
-
-/*
- *refresh configure register
- */
-static inline void refresh_config_reg(void __iomem *base)
-{
- unsigned int tmp=0;
- unsigned long flags;
- volatile int cnt;
-
- local_irq_save(flags);
-
- tmp=ioread32(base+REFRESH_REG);
-
- while(((ioread32(base+ACK_REG)>>4) & 0xf) != (tmp & 0xf))
- {
- cnt = 10;
- while(cnt--);
- }
-
- tmp ^=0xC;
- iowrite32(tmp,base+REFRESH_REG);
-
- local_irq_restore(flags);
-
-}
-
-/*
- *refresh load register
- */
-static inline void refresh_load_reg(void __iomem *base)
-{
- unsigned int tmp=0;
- unsigned long flags;
- volatile int cnt;
-
- local_irq_save(flags);
-
- tmp=ioread32(base+REFRESH_REG);
-
- while(((ioread32(base+ACK_REG)>>4) & 0xf) != (tmp & 0xf))
- {
- cnt = 10;
- while(cnt--);
- }
-
- tmp ^= 0x3;
- iowrite32(tmp,base+REFRESH_REG);
-
- local_irq_restore(flags);
-
-}
-
-/*
- *refresh load register and configure register
- */
-static inline void refresh_config_load_reg(void __iomem *base)
-{
- unsigned int tmp=0;
- unsigned long flags;
- volatile int cnt;
-
- local_irq_save(flags);
-
- tmp=ioread32(base+REFRESH_REG);
-
- while(((ioread32(base+ACK_REG)>>4) & 0xf) != (tmp & 0xf))
- {
- cnt = 10;
- while(cnt--);
- }
-
- tmp ^= 0xf;
- iowrite32(tmp,base+REFRESH_REG);
-
- local_irq_restore(flags);
-
-}
-
-/*
- * get cur_value of the timer
- */
-static inline u32 read_timer_clk(void __iomem *base)
-{
- return ioread32(base+CUR_VALUE);
-}
-
-/*
- * set reload mode
- */
-static inline void timer_set_mode(void __iomem *base, bool periodic)
-{
- unsigned int tmp = ioread32(base+CONFIG_REG);
-
- if(periodic)
- tmp |= TIMER_AUTORELOAD;
- else
- tmp &= ~TIMER_AUTORELOAD;
- iowrite32(tmp, base+CONFIG_REG);
-
- refresh_config_reg(base);
-}
-
-/*
- * start timer
- */
-static inline void timer_start(void __iomem *base)
-{
- iowrite32(0x1, base+START_REG);
-}
-
-/*
- * stop timer
- */
-static inline void timer_stop(void __iomem *base)
-{
- iowrite32(0x0, base+START_REG);
-}
-
-/*
- * set load value(unit is cycle)
- */
-static inline void timer_set_load(void __iomem *base, u32 load_val)
-{
- iowrite32(load_val, base+LOAD_REG);
- refresh_load_reg(base);
-}
-
-/*
- * set prescale, default is 0
- * 1--div 2 2--div 4 ...
- */
-static inline void timer_set_prescale(void __iomem *base, u32 prescale)
-{
- unsigned int tmp = ioread32(base+CONFIG_REG);
-
- tmp &= ~TIMER_PRESCALE(0x1F);
- tmp |= TIMER_PRESCALE(prescale);
-
- iowrite32(tmp, base+CONFIG_REG);
-
- refresh_config_reg(base);
-}
-
-
-/*-----------------------------------------------------------------------------
- *-------- timer helper functions --------------------------------------------
- *-----------------------------------------------------------------------------
- */
-static inline t_timer_info *zx_timer_alloc_info(void)
-{
- t_timer_info *info;
-
- info = &(zx_timer_ctx.info[zx_timer_ctx.nr]);
- zx_timer_ctx.nr ++;
-
- return info;
-}
-
-irqreturn_t zx_timer_isr(int irq, void *p)
-{
- t_timer_info *info = (t_timer_info *)p;
-
- if(info->cb)
- info->cb(info->cb_param);
-
- return IRQ_HANDLED;
-}
-
-static void zx_timer_configure_rate(struct device_node *np, t_timer_info *info)
-{
- /* clk */
- info->wclk = of_clk_get_by_name(np, "wclk");
- if (IS_ERR(info->wclk))
- BUG();
-
- info->pclk = of_clk_get_by_name(np, "pclk");
- if (IS_ERR(info->pclk))
- BUG();
- clk_prepare_enable(info->pclk);
-
- if (of_property_read_u32(np, "clock-frequency", &info->freq))
- info->freq = ZX_TIMER_DEFAULT_RATE;
-
- clk_set_rate(info->wclk, info->freq);
- clk_prepare_enable(info->wclk);
-
- pr_debug("wclk=%lu, parent=%s \n", clk_get_rate(info->wclk),
- __clk_get_name(clk_get_parent(info->wclk)));
-}
-
-static int zx_timer_set_callback(t_timer_info *info, zx_timer_cb cb, unsigned long param)
-{
- info->cb = cb;
- info->cb_param = param;
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------------
- *-------- common timer -----------------------------------------------------
- *-----------------------------------------------------------------------------
- */
-typedef struct
-{
- t_timer_info *info;
- u32 mult;
- u32 shift;
-
-} t_zx_common_timer;
-
-static t_zx_common_timer zx_common_timer;
-
-#define to_zx_timer_common() zx_common_timer.info
-#define for_zx_timer_common(x) zx_common_timer.info = x
-#define us_to_cyc(us) (((u64)us * zx_common_timer.mult) >> zx_common_timer.shift)
-
-int zx_timer_common_set_callback(zx_timer_cb cb, unsigned long param)
-{
- t_timer_info *info = to_zx_timer_common();
-
- return zx_timer_set_callback(info, cb, param);
-}
-
-/* expires -- unit is us */
-int zx_timer_common_start(unsigned int expires, bool periodic)
-{
- t_timer_info *info = to_zx_timer_common();
- unsigned int t0 = 1000;
- unsigned long cycles = us_to_cyc(expires);
-
- timer_set_load(info->reg, cycles);
-
-#if 0 /* when use 32k osc */
- /* wait data refresh finished. */
- t0=test_timer_read();
- while( (test_timer_read()-t0) < 4);
-#else
- while (t0--);
-#endif
-
- timer_set_mode(info->reg, periodic);
-
- timer_start(info->reg);
-
- enable_irq_wake(info->irq);
-
- return 0;
-}
-
-/* expires -- unit cycles */
-int zx_timer_common_start_cycles(unsigned int expires, bool periodic)
-{
- t_timer_info *info = to_zx_timer_common();
- unsigned int t0 = 1000;
- unsigned long cycles = expires;
-
- timer_set_load(info->reg, cycles);
-
-#if 0 /* when use 32k osc */
- /* wait data refresh finished. */
- t0=test_timer_read();
- while( (test_timer_read()-t0) < 4);
-#else
- while (t0--);
-#endif
-
- timer_set_mode(info->reg, periodic);
-
- timer_start(info->reg);
-
- enable_irq_wake(info->irq);
-
- return 0;
-}
-
-
-void zx_timer_common_stop(void)
-{
- t_timer_info *info = to_zx_timer_common();
-
- timer_stop(info->reg);
-
- disable_irq_wake(info->irq);
-}
-
-static int zx_timer_common_init(t_timer_info *info)
-{
- int ret;
- u64 sec;
-
- if (!(info->func & TIMER_FUNC_COMMON))
- return -ENODEV;
-
- for_zx_timer_common(info);
-
- sec = ZX_TIMER_MASK;
- do_div(sec, info->freq);
- if (!sec)
- sec = 1;
-
- clocks_calc_mult_shift(&zx_common_timer.mult, &zx_common_timer.shift, USEC_PER_SEC, info->freq, sec);
-
- timer_stop(info->reg);
-
- ret = request_irq(info->irq,
- zx_timer_isr,
- 0,
- "zx_timer_common",
- info);
- if(ret<0)
- BUG();
-
- enable_irq_wake(info->irq);
-
- return ret;
-}
-
-/****************************************************************
- *** wake timer(use common timer) ************************
- *** persistent timer(use cs timer) ************************
- ****************************************************************
- */
-#ifdef CONFIG_PM
-void zx29_set_wake_timer(unsigned long cycles)
-{
- zx_timer_common_start_cycles(cycles, false);
-}
-
-void zx29_stop_wake_timer(void)
-{
- zx_timer_common_stop();
-}
-#endif /*CONFIG_PM*/
-
-/*-----------------------------------------------------------------------------
- *-------- clock event ------------------------------------------------------
- *-----------------------------------------------------------------------------
- */
-#define to_zx_timer_clkevt(x) \
- container_of(x, t_timer_info, clkevt)
-
-static int zx_timer_clkevt_next_event(unsigned long evt,
- struct clock_event_device *clkevt)
-{
- t_timer_info *info = to_zx_timer_clkevt(clkevt);
-
- timer_stop(info->reg);
- timer_set_mode(info->reg, false);
- timer_set_load(info->reg, evt);
- timer_start(info->reg);
-
- return 0;
-}
-
-static int zx_timer_clkevt_set_periodic(struct clock_event_device *clkevt)
-{
- t_timer_info *info = to_zx_timer_clkevt(clkevt);
-
- timer_stop(info->reg);
- timer_set_mode(info->reg, true);
- timer_set_load(info->reg, DIV_ROUND_CLOSEST(info->freq, HZ));
- timer_start(info->reg);
-
- return 0;
-}
-
-static int zx_timer_clkevt_shutdown(struct clock_event_device *clkevt)
-{
- t_timer_info *info = to_zx_timer_clkevt(clkevt);
-
- timer_stop(info->reg);
-
- return 0;
-}
-
-void zx_timer_clkevt_cb(unsigned long data)
-{
- t_timer_info *info = (t_timer_info *)data;
- struct clock_event_device *ce = &info->clkevt;
-
- ce->event_handler(ce);
-}
-
-static struct clock_event_device *pm_ce;
-void clock_event_handler(void)
-{
- pm_ce->event_handler(pm_ce);
-}
-
-static int zx_timer_clkevt_init(t_timer_info *info)
-{
- int ret;
- struct clock_event_device *ce;
-
- if (!(info->func & TIMER_FUNC_CE))
- return -ENODEV;
-
- ce = &info->clkevt;
- pm_ce = ce;
-
- ce->name = info->np->full_name;
- ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- ce->set_next_event = zx_timer_clkevt_next_event;
- ce->set_state_shutdown = zx_timer_clkevt_shutdown;
- ce->set_state_periodic = zx_timer_clkevt_set_periodic;
- ce->set_state_oneshot = zx_timer_clkevt_shutdown;
- ce->tick_resume = zx_timer_clkevt_shutdown;
- ce->rating = 300;
- ce->irq = info->irq;
- ce->cpumask = cpu_possible_mask;
-
- zx_timer_set_callback(info, zx_timer_clkevt_cb, (unsigned long)info);
- clockevents_config_and_register(ce, info->freq, 1, 0x7fffffff);
-
- ret = request_irq(info->irq,
- zx_timer_isr,
- 0,
- "zx_timer_ce",
- info);
- if(ret<0)
- BUG();
-
- return ret;
-}
-
-/*-----------------------------------------------------------------------------
- *-------- clock source -----------------------------------------------------
- *-----------------------------------------------------------------------------
- */
-static void __iomem *zx_cs_sched_reg;
-
-/**
- * zx29_read_persistent_clock64 - Return time from a persistent clock.
- *
- * Reads the time from a source which isn't disabled during PM, the
- * 32k sync timer. Convert the cycles elapsed since last read into
- * nsecs and adds to a monotonically increasing timespec64.
- */
-static struct timespec64 persistent_ts;
-static cycles_t cycles;
-static unsigned int persistent_mult, persistent_shift;
-
-static void zx29_read_persistent_clock64(struct timespec64 *ts)
-{
- unsigned long long nsecs;
- cycles_t last_cycles;
-
- last_cycles = cycles;
- cycles = zx_cs_sched_reg ? readl_relaxed(zx_cs_sched_reg) : 0;
-
- nsecs = clocksource_cyc2ns(last_cycles - cycles,
- persistent_mult, persistent_shift);
-
- timespec64_add_ns(&persistent_ts, nsecs);
-
- *ts = persistent_ts;
-}
-
-static int zx29_timer_persistent_init(t_timer_info *info)
-{
- u64 sec;
-
- sec = 0x80000000;
- do_div(sec, info->freq);
- if (!sec)
- sec = 1;
-
- clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
- info->freq, NSEC_PER_SEC, (u32)sec);
-
- register_persistent_clock(zx29_read_persistent_clock64);
-
- return 0;
-}
-
-
-#ifdef CONFIG_PM
-int zx29_clocksource_suspend(void)
-{
- /*
- *nothing should be done here.
- *maybe clocksource should be stoped, but I don't do this
- *there is no effect on system running, even if clocksource is not suspended actually.
- *I can use clocksource in power off processing for debug.
- */
- return 0;
-}
-
-void zx29_clocksource_resume(void)
-{
-#if 0
- /*re-initiate the clocksource*/
- iowrite32(0x7fffffff,SOURCE_BASE_VA+LOAD_REG); // 2^31-1
-#ifdef CONFIG_ARCH_ZX297510FPGA
- iowrite32(0x02,SOURCE_BASE_VA+CONFIG_REG); // auto load
-#else
- iowrite32(0x22,SOURCE_BASE_VA+CONFIG_REG); // main clock/13/2 , auto load
- refresh_config_load_reg(SOURCE_BASE_VA); // refresh load reg and config reg
- iowrite32(0x1,SOURCE_BASE_VA+START_REG); // start timer
-#endif
-#endif
-}
-
-static struct syscore_ops zx29_clocksource_syscore_ops = {
- .suspend = zx29_clocksource_suspend,
- .resume = zx29_clocksource_resume,
-};
-#endif
-
-static u64 zx_timer_cs_read(struct clocksource *cs)
-{
- return ~(u64)readl_relaxed(zx_cs_sched_reg) & cs->mask;
-}
-
-static u64 notrace zx_timer_cs_read_sched_clock(void)
-{
- return ~(u64)readl_relaxed(zx_cs_sched_reg) & 0x7fffffff;
-}
-
-static int zx_timer_cs_init(t_timer_info *info)
-{
- int ret;
- struct clocksource *cs;
-
- if (!(info->func & TIMER_FUNC_CS))
- return -ENODEV;
-
- timer_set_mode(info->reg, true);
- timer_set_load(info->reg, 0x7fffffff);
- timer_start(info->reg);
-
- zx_cs_sched_reg = info->reg + CUR_VALUE;
-
- cs = kzalloc(sizeof(struct clocksource), GFP_KERNEL);
- if (!cs)
- return -ENOMEM;
-
- info->cs = cs;
- cs->name = info->np->full_name;
- cs->rating = 200;
- cs->read = zx_timer_cs_read;
- cs->mask = CLOCKSOURCE_MASK(31);
- cs->flags = CLOCK_SOURCE_IS_CONTINUOUS|CLOCK_SOURCE_SUSPEND_NONSTOP;
- clocksource_register_hz(cs, info->freq);
-
- sched_clock_register(zx_timer_cs_read_sched_clock, 31, info->freq);
-
-#ifdef CONFIG_PM
- register_syscore_ops(&zx29_clocksource_syscore_ops);
-#endif
-
- zx29_timer_persistent_init(info);
-
- return ret;
-}
-
-static int __init zx_timer_of_init(struct device_node *np)
-{
- t_timer_info *info;
-
- info = zx_timer_alloc_info();
-
- info->reg = of_iomap(np, 0);
- info->irq = irq_of_parse_and_map(np, 0);
- info->np = np;
-
- zx_timer_configure_rate(np, info);
-
- of_property_read_u32(np, "timer_function", &info->func);
- if (!info->func)
- return -EINVAL;
-
- zx_timer_clkevt_init(info);
-
- zx_timer_cs_init(info);
-
- zx_timer_common_init(info);
-
- return 0;
-}
-
-TIMER_OF_DECLARE(zx29_timer, "zte,zx29-timer", zx_timer_of_init);
-
-/*-----------------------------------------------------------------------------
- *-------- zx_timer_test -----------------------------------------------------
- *-----------------------------------------------------------------------------
- */
-extern struct kobject *zx_test_kobj;
-static unsigned int test_timer_count = 0;
-
-void test_timer_cb(unsigned long data)
-{
- test_timer_count ++;
- pr_info("test_timer_cb arrived(%d) \n", test_timer_count);
-}
-
-static ssize_t soc_timer_show(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- return sprintf(buf, "timer_int_count:%d\n", test_timer_count);
-}
-
-static ssize_t soc_timer_store(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t count)
-{
- unsigned int temp;
-
- if(sscanf(buf, "%u", &temp) != 1)
- {
- pr_info("temp=%d error", temp);
- return (count);
- }
-
- pr_info("temp=%d", temp);
-
- if(temp == 1)
- {
- zx_timer_common_set_callback((zx_timer_cb)test_timer_cb, 0);
- zx_timer_common_start(5*1000*1000, true); /* 5s */
- }
- else
- {
- zx_timer_common_stop();
- test_timer_count = 0;
- }
-
- return (count);
-}
-
-
-static DEVICE_ATTR(soc_timer, 0600, soc_timer_show, soc_timer_store);
-static struct attribute *zx_timer_attributes[] = {
- &dev_attr_soc_timer.attr,
- NULL,
-};
-
-static const struct attribute_group zx_timer_attribute_group = {
- .attrs = (struct attribute **) zx_timer_attributes,
-};
-
-int __init zx_timer_test_init(void)
-{
- int ret;
-
- ret = sysfs_create_group(zx_test_kobj, &zx_timer_attribute_group);
- if (!ret)
- pr_info("[DEBUG] create test timer sysfs interface OK.\n");
-
- return 0;
-}
-
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/spi/spi-zx29.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/spi/spi-zx29.c
index 7cb7f1a..5150a52 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/spi/spi-zx29.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/spi/spi-zx29.c
@@ -43,6 +43,7 @@
//#include <linux/soc/zte/pm/drv_idle.h>
#include "spi-zx29.h"
+#include "pub_debug_info.h"
struct zx29_ssp_device_of_data {
enum zx29_ssp_device_mode mode;
@@ -210,6 +211,9 @@
*/
#define SPI_SOD_DISABLED (1)
#define SPI_SOD_ENABLED (0)
+#define SPI_SLAVE_MODE (1)
+#define SPI_MASTER_MODE (0)
+
/*
* SPI TRANSFER DELAY CFG
@@ -1326,7 +1330,7 @@
u32 irqflags = ENABLE_ALL_INTERRUPTS;
struct spi_transfer *transfer = zx29spi->cur_transfer;
int ret = 0;
-
+ static int sc_debug_info_record_cnt[4] ={0};
if((void *)transfer->tx_dma != NULL){
zx29spi->tx = (void *)transfer->tx_dma;
zx29spi->tx_end = zx29spi->tx + zx29spi->cur_transfer->len;
@@ -1368,7 +1372,12 @@
ret = down_timeout(&zx29spi->sema_dma, msecs_to_jiffies(1500));
//printk("COM=0x%x,FMT=0x%x,FIFO_CTL=0x%x,FIFO_SR=0x%x\n",readl((SPI_COM_CTRL_OFFSET+zx29spi->virtbase)),readl((SPI_FMT_CTRL_OFFSET+zx29spi->virtbase)),readl((SPI_FIFO_CTRL_OFFSET+zx29spi->virtbase)),readl((SPI_FIFO_SR_OFFSET+zx29spi->virtbase)));
if (ret < 0) {
- panic("spi transfer timeout\n");
+ panic("spi transfer timeout,times(%d)\n",sc_debug_info_record_cnt[zx29spi->pdev->id]);
+ if(sc_debug_info_record_cnt[zx29spi->pdev->id] < 5) {
+ sc_debug_info_record(MODULE_ID_CAP_SPI, "%s transfer timeout:0x%x 0x%x 0x%x \n",zx29spi->pdev->name,readl((SPI_COM_CTRL_OFFSET+zx29spi->virtbase)),
+ readl((SPI_FIFO_SR_OFFSET+zx29spi->virtbase)),readl((SPI_INTR_SR_OFFSET+zx29spi->virtbase)));
+ }
+ sc_debug_info_record_cnt[zx29spi->pdev->id]++;
}
while (readl((SPI_FIFO_SR_OFFSET+zx29spi->virtbase)) & SPI_FIFO_SR_MASK_BUSY)
@@ -1427,11 +1436,13 @@
struct device *dev;
struct spi_transfer *transfer;
int ret = 0;
-
+ static int sc_debug_info_record_tx_cnt[4] ={0};
+ static int sc_debug_info_record_rx_cnt[4] ={0};
+
if(!zx29spi || !msg)
return -EFAULT;
- if (msg->is_dma_mapped || !msg->spi->dma_used) {
+ if (msg->is_dma_mapped || !msg->spi->dma_used || !zx29spi->master_info->enable_dma) {
return 0;
}
dev = &zx29spi->pdev->dev;
@@ -1444,18 +1455,24 @@
if (transfer->tx_buf != NULL) {
transfer->tx_dma = dma_map_single(dev,(void *)transfer->tx_buf, transfer->len, DMA_TO_DEVICE);
if (dma_mapping_error(dev, transfer->tx_dma)) {
- dev_err(dev, "dma_map_single spi Tx failed\n");
+ dev_err(dev, "dma_map_single spi Tx failed,times(%d)\n",sc_debug_info_record_tx_cnt[zx29spi->pdev->id]);
+ if(sc_debug_info_record_tx_cnt[zx29spi->pdev->id] < 5)
+ sc_debug_info_record(MODULE_ID_CAP_SPI, "%s tx_dma_map failed \n",zx29spi->pdev->name);
transfer->tx_dma = 0;
ret |= -ENOMEM;
+ sc_debug_info_record_tx_cnt[zx29spi->pdev->id]++;
}
}
if (transfer->rx_buf != NULL) {
transfer->rx_dma = dma_map_single(dev, transfer->rx_buf, transfer->len, DMA_FROM_DEVICE);
if (dma_mapping_error(dev, transfer->rx_dma)) {
- dev_err(dev, "dma_map_single spi Rx failed\n");
+ dev_err(dev, "dma_map_single spi Rx failed,times(%d)\n",sc_debug_info_record_rx_cnt[zx29spi->pdev->id]);
+ if(sc_debug_info_record_rx_cnt[zx29spi->pdev->id] < 5)
+ sc_debug_info_record(MODULE_ID_CAP_SPI, "%s rx_dma_map failed \n",zx29spi->pdev->name);
transfer->rx_dma = 0;
ret |= -ENOMEM;
+ sc_debug_info_record_rx_cnt[zx29spi->pdev->id]++;
}
if (!transfer->rx_dma && transfer->tx_dma && transfer->tx_buf) {
@@ -1475,7 +1492,7 @@
struct device *dev = &zx29spi->pdev->dev;
struct spi_transfer *transfer;
- if (msg->is_dma_mapped || !zx29spi->master_info->enable_dma)
+ if (msg->is_dma_mapped || !msg->spi->dma_used || !zx29spi->master_info->enable_dma)
return;
list_for_each_entry(transfer, &msg->transfers, transfer_list) {
@@ -2108,6 +2125,22 @@
EXPORT_SYMBOL(spi_gpio_3wire_read8);
+static void zx29_setup_to_regs(struct chip_data *chip,struct zx29_spi *zx29spi)
+{
+ unsigned int regval = 0;
+
+ regval = readl((SPI_COM_CTRL_OFFSET+zx29spi->virtbase)) & (~SPI_COM_CTRL_MASK_SSPE);
+ writel(regval, (SPI_COM_CTRL_OFFSET+zx29spi->virtbase));
+
+ writel(chip->fmt_ctrl, (SPI_FMT_CTRL_OFFSET+zx29spi->virtbase));
+ writel(chip->fifo_ctrl, (SPI_FIFO_CTRL_OFFSET+zx29spi->virtbase));
+ writel(chip->com_ctrl, (SPI_COM_CTRL_OFFSET + zx29spi->virtbase));
+ //writel(chip->timing, (SPI_TIMING_OFFSET + zx29spi->virtbase));
+
+ writel(readl((SPI_COM_CTRL_OFFSET+zx29spi->virtbase)) | SPI_COM_CTRL_MASK_SSPE, (SPI_COM_CTRL_OFFSET+zx29spi->virtbase));
+ while(((readl((SPI_COM_CTRL_OFFSET+zx29spi->virtbase))>> 4)&0x1) == 0);
+
+}
/**
* zx29_setup - setup function registered to SPI master framework
* @spi: spi device which is requesting setup
@@ -2281,7 +2314,12 @@
SPI_WRITE_BITS(chip->timing, spi->trans_gap_num, SPI_TIMING_MASK_T_CS_DESEL, 0);
/* Save controller_state */
spi_set_ctldata(spi, chip);
-
+ if(zx29spi->mode == ZX29_SSP_SLAVE_TYPE) {
+
+ SPI_WRITE_BITS(chip->com_ctrl, SPI_SLAVE_MODE, SPI_COM_CTRL_MASK_MS, 2);
+ zx29_setup_to_regs(chip,zx29spi);
+ }
+
return status;
err_config_params:
spi_set_ctldata(spi, NULL);
@@ -2690,8 +2728,10 @@
/* Get DMA channels */
if (platform_info->enable_dma) {
status = zx29_dma_probe(zx29spi);
- if (status != 0)
+ if (status != 0) {
platform_info->enable_dma = 0;
+ sc_debug_info_record(MODULE_ID_CAP_SPI, "%s dma probe failed \n",pdev->name);
+ }
}
#if SPI_PSM_CONTROL
@@ -2760,7 +2800,7 @@
return 0;
platform_info->bus_id = 0,
platform_info->num_chipselect = 1,
- platform_info->enable_dma = 0,
+ platform_info->enable_dma = 1,
platform_info->autosuspend_delay=0,
/* Allocate master with space for data */
@@ -2867,8 +2907,10 @@
/* Get DMA channels */
if (platform_info->enable_dma) {
status = zx29_dma_probe(zx29spi);
- if (status != 0)
+ if (status != 0) {
platform_info->enable_dma = 0;
+ sc_debug_info_record(MODULE_ID_CAP_SPI, "%s dma probe failed",pdev->name);
+ }
}
#if SPI_PSM_CONTROL
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/sanechips/zx29_ak4940.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
index 312ff9a..f730067 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
@@ -400,12 +400,7 @@
raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
}
#endif
-
- unsigned int armRegBit = 0;
- //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
- //armRegBit &= 0xfffffffe;
- //armRegBit |= 0x1;
- //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+
return 0;
}
@@ -427,11 +422,7 @@
if (snd_soc_dai_active(cpu_dai))
return;
- u32 armRegBit;
- //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
- //armRegBit &= 0xfffffffe;
- //armRegBit |= 0x0;
- //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+
}
@@ -454,11 +445,7 @@
if (snd_soc_dai_active(cpu_dai))
return;
- u32 armRegBit;
- //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
- //armRegBit &= 0xfffffffe;
- //armRegBit |= 0x0;
- //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+
}
static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
{
@@ -1887,8 +1874,6 @@
board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
if (!board)
return -ENOMEM;
- board->name = "zx29_ak4940";
- board->dev = &pdev->dev;
if (np) {
zx29_dai_link[0].cpus->dai_name = NULL;
@@ -1923,6 +1908,9 @@
id = of_match_device(of_match_ptr(zx29_ak4940_of_match), &pdev->dev);
if (id)
*board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_ak4940";
+ board->dev = &pdev->dev;
//platform_set_drvdata(pdev, board);
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/sanechips/zx29_voice.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/sanechips/zx29_voice.c
index 8307de7..3ce31ac 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/sanechips/zx29_voice.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/sanechips/zx29_voice.c
@@ -134,6 +134,16 @@
//extern T_DrvVoice_3G_Opt gDrvVoice_3G_Obj;
#endif
+struct zx29_voice_data {
+ const char *name;
+ struct device *dev;
+ struct mutex mutex;
+
+};
+
+static struct zx29_voice_data vdata = {
+ .name = "zx29_voice",
+};
static const struct snd_pcm_hardware dma_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
@@ -155,10 +165,37 @@
};
+static void zx29_voice_set_active(struct zx29_voice_data *data)
+{
+
+ print_audio("Alsa: Entered func %s\n", __func__);
+#ifdef CONFIG_PM
+ mutex_lock(&data->mutex);
+ pm_stay_awake(data->dev);
+ mutex_unlock(&data->mutex);
+#endif
+
+}
+
+static void zx29_voice_set_idle(struct zx29_voice_data *data)
+{
+
+ print_audio("Alsa: Entered func %s\n", __func__);
+#ifdef CONFIG_PM
+ mutex_lock(&data->mutex);
+ pm_relax(data->dev);
+ mutex_unlock(&data->mutex);
+#endif
+
+}
+
+
static int voice_hw_params(struct snd_soc_component *component,struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
+ print_audio("Alsa Entered func %s\n", __func__);
+
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
if (rtd->dai_link->name != NULL && (!strcmp(rtd->dai_link->name, "voice_3g"))) {
@@ -172,7 +209,7 @@
static int voice_hw_free(struct snd_soc_component *component,struct snd_pcm_substream *substream)
{
int ret = 0;
-// print_audio("Alsa Entered func %s\n", __func__);
+ print_audio("Alsa Entered func %s\n", __func__);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
if (rtd->dai_link->name != NULL && (!strcmp(rtd->dai_link->name, "voice_3g"))) {
@@ -185,7 +222,7 @@
static int voice_prepare(struct snd_soc_component *component,struct snd_pcm_substream *substream)
{
int ret = 0;
-// print_audio("Alsa Entered func %s\n", __func__);
+ print_audio("Alsa Entered func %s\n", __func__);
#if defined(USE_ALSA_VOICE_FUNC) && defined(CONFIG_VOICE_DRV)
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
@@ -204,13 +241,8 @@
static int voice_trigger(struct snd_soc_component *component,struct snd_pcm_substream *substream, int cmd)
{
int ret = 0;
-// print_audio("Alsa Entered func %s, cmd=%d\n", __func__, cmd);
+ print_audio("Alsa Entered func %s, cmd=%d\n", __func__, cmd);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
- if (rtd->dai_link->name != NULL && (!strcmp(rtd->dai_link->name, "voice_3g"))) {
-
- print_audio("Alsa Entered func %s 3g soft amr !\n", __func__);
- return 0;
- }
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
break;
@@ -226,7 +258,7 @@
static int voice_open(struct snd_soc_component *component,struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
-// print_audio("Alsa Entered func %s\n", __func__);
+ print_audio("Alsa Entered func %s\n", __func__);
int ret = 0;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
@@ -261,13 +293,15 @@
}
}
#endif
+ zx29_voice_set_active(&vdata);
+
return ret;
}
static int voice_close(struct snd_soc_component *component,struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
-// print_audio("Alsa Entered func %s\n", __func__);
+ print_audio("Alsa Entered func %s\n", __func__);
int ret = 0;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
#if defined(USE_ALSA_VOICE_FUNC) && defined(CONFIG_VOICE_DRV)
@@ -295,6 +329,7 @@
}
#endif
+ zx29_voice_set_idle(&vdata);
return ret;
}
@@ -403,6 +438,14 @@
return ret;
}
+ vdata.dev = &pdev->dev;
+#ifdef CONFIG_PM
+ mutex_init(&vdata.mutex);
+ device_init_wakeup(vdata.dev, true);
+ if(vdata.dev != NULL)
+ dev_info(&pdev->dev,"%s: device_init_wakeup dev driver_name=%s,dev_name=%s!\n",__func__,dev_driver_string(vdata.dev),dev_name(vdata.dev));
+
+#endif
dev_info(&pdev->dev,"%s end!\n", __func__);
pr_info( "voice_asoc_platform_probe end\n");
@@ -418,7 +461,7 @@
static const struct of_device_id voice_of_match[] = {
- { .compatible = "voice_audio", },
+ { .compatible = "voice_audio", .data = &vdata },
{},
};
MODULE_DEVICE_TABLE(of, voice_of_match);
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/ab_bootinfo/Makefile b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/ab_bootinfo/Makefile
index ba8e396..29d5251 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/ab_bootinfo/Makefile
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/ab_bootinfo/Makefile
@@ -13,7 +13,9 @@
#LDLIBS = -lnvram_sc -L$(LIB_DIR)/libnvram
-LDLIBS += -lpthread -lmtd -lnvram -lsofttimer -lupi_ab -lsoftap
+#LDLIBS += -lmtd
+LDLIBS += -lpthread -lnvram -lsofttimer -lupi_ab -lsoftap
+LDLIBS += -lcrypto
#LDLIBS += -lcrypto -L$(LIB_DIR)/libssl/install/lib
##############USER COMIZE END##################
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/ab_bootinfo/ab_bootinfo.c b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/ab_bootinfo/ab_bootinfo.c
old mode 100644
new mode 100755
index 94d3dfc..b0224de
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/ab_bootinfo/ab_bootinfo.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/ab_bootinfo/ab_bootinfo.c
@@ -14,14 +14,17 @@
switch (ret)
{
- case 1:
+ case Z_DUAL_SYSTEM:
printf("ab_bootinfo:ab_a\n");
+ ret = 1;
break;
- case 2:
+ case Z_DUAL_SYSTEM2:
printf("ab_bootinfo:ab_b\n");
+ ret = 2;
break;
default:
printf("[error]ab_bootinfo:%d\n", ret);
+ ret = 1;
break;
}
return ret;
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fota_upi_ab/Makefile b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fota_upi_ab/Makefile
index 694a25d..947728a 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fota_upi_ab/Makefile
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fota_upi_ab/Makefile
@@ -74,10 +74,11 @@
# SHA512 functions in libcrypto.a not libssl
#LDLIBS += -lssl
-#LDLIBS += -lcrypto
-#LDLIBS += -L$(zte_lib_path)/libssl/install/lib
-#LDLIBS += -L$(zte_lib_path)/libnvram
-#LDLIBS += -L$(zte_lib_path)/libsoftap
+# ap and cap then remove next four lines
+LDLIBS += -lcrypto
+LDLIBS += -L$(zte_lib_path)/libssl/install/lib
+LDLIBS += -L$(zte_lib_path)/libnvram
+LDLIBS += -L$(zte_lib_path)/libsoftap
#LDLIBS += -lcpnv -L$(LIB_DIR)/libcpnv
@@ -85,7 +86,8 @@
CFLAGS += -I$(LIB_DIR)/libsoftap
CFLAGS += -I$(LIB_DIR)/libsofttimer
-LDLIBS += -lmtd
+# ap and cap then open the next line
+#LDLIBS += -lmtd
LDLIBS += -lnvram -L$(LIB_DIR)/libnvram
LDLIBS += -lsofttimer -L$(LIB_DIR)/libsofttimer
LDLIBS += -latutils -L$(LIB_DIR)/libatutils
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fota_upi_ab/src/main.c b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fota_upi_ab/src/main.c
index b30ea01..e5f04dd 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fota_upi_ab/src/main.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fota_upi_ab/src/main.c
@@ -48,9 +48,10 @@
* Type definitions *
******************************************************************************/
-typedef struct {
- int option_value;
- int (*func)(char *);
+typedef struct
+{
+ int option_value;
+ int (*func)(char *);
} option_handle_t;
@@ -76,7 +77,7 @@
static int execute_command_get_upgrade_type(char *option_para);
static int execute_command_get_sync_status(char * option_para);
static int execute_command_set_sync_status(char * option_para);
-
+static int execute_command_config_package_path(char * option_para);
/*******************************************************************************
@@ -85,45 +86,49 @@
/*----------Command parser begin---------------------------------------------------------*/
-static char * g_short_string = "u:cgb:sio:t:qr:hvypne:";
+static char * g_short_string = "u:cgb:sio:t:qr:hvypne:a:";
-static struct option g_long_options[] = {
- {"upgrade", required_argument, NULL, 'u'},
- {"get-current", no_argument, NULL, 'c'},
- {"get-boot", no_argument, NULL, 'g'},
- {"set-boot", required_argument, NULL, 'b'},
- {"get-upgrade_status", no_argument, NULL, 's'},
- {"get-system-info", no_argument, NULL, 'i'},
- {"set-system1-status", required_argument, NULL, 'o'},
- {"set-system2-status", required_argument, NULL, 't'},
- {"get-fota-status", no_argument, NULL, 'q'},
- {"set-fota-status", required_argument, NULL, 'r'},
- {"help", no_argument, NULL, 'h'},
- {"version", no_argument, NULL, 'v'},
- {"sync", no_argument, NULL, 'y'},
- {"get-upgrade-type", no_argument, NULL, 'p'},
- {"get-sync-status", no_argument, NULL, 'n'},
- {"set-sync-status", required_argument, NULL, 'e'},
- {0, 0, 0, 0}
+static struct option g_long_options[] =
+{
+ {"upgrade", required_argument, NULL, 'u'},
+ {"get-current", no_argument, NULL, 'c'},
+ {"get-boot", no_argument, NULL, 'g'},
+ {"set-boot", required_argument, NULL, 'b'},
+ {"get-upgrade_status", no_argument, NULL, 's'},
+ {"get-system-info", no_argument, NULL, 'i'},
+ {"set-system1-status", required_argument, NULL, 'o'},
+ {"set-system2-status", required_argument, NULL, 't'},
+ {"get-fota-status", no_argument, NULL, 'q'},
+ {"set-fota-status", required_argument, NULL, 'r'},
+ {"help", no_argument, NULL, 'h'},
+ {"version", no_argument, NULL, 'v'},
+ {"sync", no_argument, NULL, 'y'},
+ {"get-upgrade-type", no_argument, NULL, 'p'},
+ {"get-sync-status", no_argument, NULL, 'n'},
+ {"set-sync-status", required_argument, NULL, 'e'},
+ {"config-package-path", required_argument, NULL, 'a'},
+ {0, 0, 0, 0}
};
-static option_handle_t g_option_handle[] = {
- {'u', excute_command_upgrade},
- {'c', excute_command_get_current_system},
- {'g', excute_command_get_boot_to_system},
- {'b', excute_command_set_boot_to_system},
- {'s', excute_command_get_status},
- {'i', excute_command_get_system_info},
- {'o', excute_command_set_system1_status},
- {'t', excute_command_set_system2_status},
- {'q', excute_command_get_fota_status},
- {'r', excute_command_set_fota_status},
- {'h', excute_command_help},
- {'v', execute_command_version},
- {'y', execute_command_sync},
- {'p', execute_command_get_upgrade_type},
- {'n', execute_command_get_sync_status},
- {'e', execute_command_set_sync_status}
+static option_handle_t g_option_handle[] =
+{
+ {'u', excute_command_upgrade},
+ {'c', excute_command_get_current_system},
+ {'g', excute_command_get_boot_to_system},
+ {'b', excute_command_set_boot_to_system},
+ {'s', excute_command_get_status},
+ {'i', excute_command_get_system_info},
+ {'o', excute_command_set_system1_status},
+ {'t', excute_command_set_system2_status},
+ {'q', excute_command_get_fota_status},
+ {'r', excute_command_set_fota_status},
+ {'h', excute_command_help},
+ {'v', execute_command_version},
+ {'y', execute_command_sync},
+ {'p', execute_command_get_upgrade_type},
+ {'n', execute_command_get_sync_status},
+ {'e', execute_command_set_sync_status},
+ {'a', execute_command_config_package_path}
};
@@ -140,215 +145,234 @@
static void usage(void)
{
- printf("fota_upi [-cgsiqhvypn] [-u <target>][-b <boot to system>][-otr <system info>][-e <sync status>]\n "
- " -u, --upgrade verify or update \n"
- " -c , --get-current get current system \n"
- " -g , --get-boot get boot to system \n"
- " -b, --set-boot set boot to system \n"
- " -s, --get-status get system status \n"
- " -i, --get-system-info get system info \n"
- " -o, --set-system1-status set system1 status info \n"
- " -t, --set-system2-status set system2 status info \n"
- " -q, --get-fota-status get fota status to show if need sync NV when next reboot, 0:no 1:yes \n"
- " -r, --set-fota-status set fota status to show if need sync NV when next reboot, 0:no 1:yes \n"
- " -h , --help show this usage text\n"
- " -v, --version show current version \n"
- " -y, --sync sync \n"
- " -p, --get-upgrade-type get upgrade type \n"
- " -n, --get-sync-status get sync status \n"
- " -e, --set-sync-status set sync status \n");
+ printf("fota_upi [-cgsiqhvypn] [-u <target>][-b <boot to system>][-otr <system info>][-e <sync status>]\n "
+ " -u, --upgrade verify or update \n"
+ " -c , --get-current get current system \n"
+ " -g , --get-boot get boot to system \n"
+ " -b, --set-boot set boot to system \n"
+ " -s, --get-status get system status \n"
+ " -i, --get-system-info get system info \n"
+ " -o, --set-system1-status set system1 status info \n"
+ " -t, --set-system2-status set system2 status info \n"
+ " -q, --get-fota-status get fota status to show if need sync NV when next reboot, 0:no 1:yes \n"
+ " -r, --set-fota-status set fota status to show if need sync NV when next reboot, 0:no 1:yes \n"
+ " -h , --help show this usage text\n"
+ " -v, --version show current version \n"
+ " -y, --sync sync \n"
+ " -p, --get-upgrade-type get upgrade type \n"
+ " -n, --get-sync-status get sync status \n"
+ " -e, --set-sync-status set sync status \n"
+ " -a, --config-package-path config package path \n");
}
z_upgrade_status_info_t g_upgrade_status;
void g_flush_upgrade_status(z_upgrade_status_info_t *p_status)
{
-// LOG_FUNC_BEGIN
- printf("Current status:%d \n", p_status->upgrade_status);
+ // LOG_FUNC_BEGIN
+ printf("Current status:%d \n", p_status->upgrade_status);
- printf("Total size:%d \n", p_status->total_size);
+ printf("Total size:%d \n", p_status->total_size);
- printf("Updated size:%d \n", p_status->upgraded_size);
-// LOG_FUNC_END
+ printf("Updated size:%d \n", p_status->upgraded_size);
+ // LOG_FUNC_END
}
/*----------Command parser function begin------------------------------------------------*/
static int excute_command_upgrade(char * option_para)
{
- int ret = -1;
-
- if (NULL == option_para) {
- usage();
- printf("Command input invalid! null input upgrade para, please choose verify or recovery or system! \n");
- return -1;
- }
+ int ret = -1;
-
- if (0 == strcmp(FOTA_UPI_VERIFY, option_para)) {
- printf("Begin to verify upgrade package \n");
- ret = zxic_dual_verify();
- } else if (0 == strcmp(FOTA_UPI_UPDATE, option_para)) {
-// ret = upi_update();
- z_upgrade_flush_status_t flush_status;
- z_upgrade_status_info_t status ;
- memset(&status, 0, sizeof(z_upgrade_status_info_t));
- flush_status.status = &status;
- flush_status.status_cb = &g_flush_upgrade_status;
- ret = zxic_dual_upgrade(&flush_status);
- } else {
- printf("Unknow input upgrade para, verify or update! \n");
- return -1;
- }
+ if (NULL == option_para)
+ {
+ usage();
+ printf("Command input invalid! null input upgrade para, please choose verify or recovery or system! \n");
+ return -1;
+ }
- return ret;
+ if (0 == strcmp(FOTA_UPI_VERIFY, option_para))
+ {
+ printf("Begin to verify upgrade package \n");
+ ret = zxic_dual_verify();
+ }
+ else if (0 == strcmp(FOTA_UPI_UPDATE, option_para))
+ {
+ // ret = upi_update();
+ z_upgrade_flush_status_t flush_status;
+ z_upgrade_status_info_t status ;
+ memset(&status, 0, sizeof(z_upgrade_status_info_t));
+ flush_status.status = &status;
+ flush_status.status_cb = &g_flush_upgrade_status;
+ ret = zxic_dual_upgrade(&flush_status);
+ }
+ else
+ {
+ printf("Unknow input upgrade para, verify or update! \n");
+ return -1;
+ }
+
+
+ return ret;
}
static int excute_command_get_current_system(char * option_para)
{
- int current = zxic_dual_get_current_system();
+ int current = zxic_dual_get_current_system();
- printf("Current system:0x%08X[%d] \n", current, current);
+ printf("Current system:0x%08X[%d] \n", current, current);
- return current;
+ return current;
}
static int excute_command_get_boot_to_system(char * option_para)
{
- int boot_to = zxic_dual_get_boot_to_system();
+ int boot_to = zxic_dual_get_boot_to_system();
- printf("Boot to system:0x%08X[%d]\n", boot_to, boot_to);
+ printf("Boot to system:0x%08X[%d]\n", boot_to, boot_to);
- return 0;
+ return 0;
}
static int excute_command_set_boot_to_system(char * option_para)
{
- int ret = 0;
+ int ret = 0;
- if (NULL == option_para) {
- usage();
- printf("Command input invalid value! null option parameters! \n");
- return -1;
- }
+ if (NULL == option_para)
+ {
+ usage();
+ printf("Command input invalid value! null option parameters! \n");
+ return -1;
+ }
- ret = zxic_dual_set_boot_to_system(atoi(option_para), 0);
- if(ret < 0){
- printf("Set boot to [%s] error \n", option_para);
- }
+ ret = zxic_dual_set_boot_to_system(atoi(option_para), 0);
+ if (ret < 0)
+ {
+ printf("Set boot to [%s] error \n", option_para);
+ }
- return ret;
+ return ret;
}
static int excute_command_get_status(char *option_para)
{
- z_upgrade_status_info_t status;
- if(zxic_dual_get_upgrade_status(&status) < 0){
- printf("Get upgrade status fail! \n");
- return -1;
- }
-
- printf("Current upgrade info: \n");
- printf("Current upgrade status:%d \n", status.upgrade_status);
- printf("Current upgrade total size:%d \n", status.total_size);
- printf("Current upgrade updated size:%d \n", status.upgraded_size);
-
+ z_upgrade_status_info_t status;
+ if (zxic_dual_get_upgrade_status(&status) < 0)
+ {
+ printf("Get upgrade status fail! \n");
+ return -1;
+ }
+
+ printf("Current upgrade info: \n");
+ printf("Current upgrade status:%d \n", status.upgrade_status);
+ printf("Current upgrade total size:%d \n", status.total_size);
+ printf("Current upgrade updated size:%d \n", status.upgraded_size);
+
return 0;
}
static int excute_command_get_system_info(char * option_para)
{
- z_upgrade_system_info_t system_info;
- if(zxic_dual_get_system_status(&system_info) < 0){
- printf("Get upgrade status fail! \n");
- return -1;
- }else{
- printf("System info: \n");
- printf("Boot to:0x%08X[%d] \n", system_info.boot_to, system_info.boot_to);
- printf("Fota status:%d \n", system_info.fota_status);
- printf("System1 system:0x%08X [%d] \n", system_info.system_1.system, system_info.system_1.system);
- printf("System1 status:%d \n", system_info.system_1.status);
- printf("System1 try_cnt:%d \n", system_info.system_1.try_cnt);
- printf("System2 system:0x%08X [%d] \n", system_info.system_2.system, system_info.system_2.system);
- printf("System2 status:%d \n", system_info.system_2.status);
- printf("System2 try_cnt:%d \n", system_info.system_2.try_cnt);
- }
+ z_upgrade_system_info_t system_info;
+ if (zxic_dual_get_system_status(&system_info) < 0)
+ {
+ printf("Get upgrade status fail! \n");
+ return -1;
+ }
+ else
+ {
+ printf("System info: \n");
+ printf("Boot to:0x%08X[%d] \n", system_info.boot_to, system_info.boot_to);
+ printf("Fota status:%d \n", system_info.fota_status);
+ printf("System1 system:0x%08X [%d] \n", system_info.system_1.system, system_info.system_1.system);
+ printf("System1 status:%d \n", system_info.system_1.status);
+ printf("System1 try_cnt:%d \n", system_info.system_1.try_cnt);
+ printf("System2 system:0x%08X [%d] \n", system_info.system_2.system, system_info.system_2.system);
+ printf("System2 status:%d \n", system_info.system_2.status);
+ printf("System2 try_cnt:%d \n", system_info.system_2.try_cnt);
+ }
- return 0;
+ return 0;
}
static int excute_command_set_system1_status(char * option_para)
{
- int ret = -1;
- if (NULL == option_para) {
- usage();
- printf("Command input invalid value! null option parameters! \n");
- return -1;
- }
-
- ret = zxic_dual_set_system_status(34650, atoi(option_para));
- if(ret < 0){
- printf("Set system 1 status to [%s] error \n", option_para);
- }
+ int ret = -1;
+ if (NULL == option_para)
+ {
+ usage();
+ printf("Command input invalid value! null option parameters! \n");
+ return -1;
+ }
- return ret;
+ ret = zxic_dual_set_system_status(34650, atoi(option_para));
+ if (ret < 0)
+ {
+ printf("Set system 1 status to [%s] error \n", option_para);
+ }
+
+ return ret;
}
static int excute_command_set_system2_status(char * option_para)
{
- int ret = -1;
- if (NULL == option_para) {
- usage();
- printf("Command input invalid value! null option parameters! \n");
- return -1;
- }
-
- ret = zxic_dual_set_system_status(39019, atoi(option_para));
- if(ret < 0){
- printf("Set system 2 status to [%s] error \n", option_para);
- }
+ int ret = -1;
+ if (NULL == option_para)
+ {
+ usage();
+ printf("Command input invalid value! null option parameters! \n");
+ return -1;
+ }
- return ret;
+ ret = zxic_dual_set_system_status(39019, atoi(option_para));
+ if (ret < 0)
+ {
+ printf("Set system 2 status to [%s] error \n", option_para);
+ }
+
+ return ret;
}
static int excute_command_get_fota_status(char * option_para)
{
- int status = zxic_dual_get_fota_status_for_nv();
+ int status = zxic_dual_get_fota_status_for_nv();
- printf("Fota status:%d \n", status);
+ printf("Fota status:%d \n", status);
- return 0;
+ return 0;
}
static int excute_command_set_fota_status(char * option_para)
{
- int ret = 0;
+ int ret = 0;
- if (NULL == option_para) {
- usage();
- printf("Command input invalid value! null option parameters! \n");
- return -1;
- }
+ if (NULL == option_para)
+ {
+ usage();
+ printf("Command input invalid value! null option parameters! \n");
+ return -1;
+ }
- ret = zxic_dual_set_fota_status_for_nv(atoi(option_para));
- if(ret < 0){
- printf("Set fota_status to [%s] error \n", option_para);
- }
+ ret = zxic_dual_set_fota_status_for_nv(atoi(option_para));
+ if (ret < 0)
+ {
+ printf("Set fota_status to [%s] error \n", option_para);
+ }
- return ret;
+ return ret;
}
static int excute_command_help(char * option_para)
{
- usage();
- return 0;
+ usage();
+ return 0;
}
@@ -357,10 +381,10 @@
static int execute_command_version(char *option_para)
{
- int version = 0;
+ int version = 0;
- return version;
+ return version;
}
@@ -369,11 +393,11 @@
static int execute_command_sync(char *option_para)
{
- int ret = -1;
+ int ret = -1;
- ret = zxic_dual_sync_system();
+ ret = zxic_dual_sync_system();
- return ret;
+ return ret;
}
@@ -382,48 +406,71 @@
static int execute_command_get_upgrade_type(char *option_para)
{
- int upgrade_type = -1;
-
- upgrade_type = zxic_dual_get_upgrade_type();
- printf("upgrade type is %d\n", upgrade_type);
+ int upgrade_type = -1;
- return 0;
+ upgrade_type = zxic_dual_get_upgrade_type();
+ printf("upgrade type is %d\n", upgrade_type);
+
+ return 0;
}
static int execute_command_get_sync_status(char * option_para)
{
- int sync_status = -2;
-
- zxic_dual_get_sync_status(&sync_status);
- printf("Current sync status is %d\n", sync_status);
+ int sync_status = -2;
- return 0;
+ zxic_dual_get_sync_status(&sync_status);
+ printf("Current sync status is %d\n", sync_status);
+
+ return 0;
}
static int execute_command_set_sync_status(char * option_para)
{
- int ret = -1;
-
- if (NULL == option_para) {
- usage();
- printf("Command input invalid value! null option parameters! \n");
-
- return ret;
- }
-
- ret = zxic_dual_set_sync_status(atoi(option_para));
- if (0 != ret)
- {
- printf("set sync status fail\n");
-
- return ret;
- }
-
- ret = 0;
-
- return ret;
+ int ret = -1;
+
+ if (NULL == option_para)
+ {
+ usage();
+ printf("Command input invalid value! null option parameters! \n");
+
+ return ret;
+ }
+
+ ret = zxic_dual_set_sync_status(atoi(option_para));
+ if (0 != ret)
+ {
+ printf("set sync status fail\n");
+
+ return ret;
+ }
+
+ ret = 0;
+
+ return ret;
+}
+
+
+static int execute_command_config_package_path(char * option_para)
+{
+ if (NULL == option_para)
+ {
+ printf("Invalid command input: NULL option parameters \n");
+ usage();
+
+ return -1;
+ }
+
+ if (-1 == zxic_dual_config_package_path(option_para, strlen(option_para)))
+ {
+ printf("Configure upgrade package path fail \n");
+ return -1;
+ }
+
+ printf("Configure upgrade package path success \n");
+
+ return 0;
}
@@ -440,21 +487,23 @@
*/
static void write_lockfile(char *filepath, char *setbuf)
{
- int f, len = 0;
+ int f, len = 0;
- f = open(filepath, O_RDWR | O_SYNC);
- if (f == -1) {
- perror("open lock failed\n");
- return;
- }
+ f = open(filepath, O_RDWR | O_SYNC);
+ if (f == -1)
+ {
+ perror("open lock failed\n");
+ return;
+ }
- len = strlen(setbuf);
+ len = strlen(setbuf);
- if (write(f, setbuf, len) != len) {
- perror("write lock failed\n");
- }
+ if (write(f, setbuf, len) != len)
+ {
+ perror("write lock failed\n");
+ }
- close(f);
+ close(f);
}
/*******************************************************************************
@@ -463,54 +512,61 @@
int main(int argc, char *argv[])
{
- int i = 0;
- int option_index = 0;
- int cmd_num = 0;
+ int i = 0;
+ int option_index = 0;
+ int cmd_num = 0;
- int ret = -1;
- int ch = -1;
+ int ret = -1;
+ int ch = -1;
printf("build date: %s %s\n", __DATE__, __TIME__);
-
- write_lockfile(POWER_WAKE_LOCK_FILE, FOTA_UPGRADE_LOCK);
- while ((ch = getopt_long(argc, argv, g_short_string, g_long_options, &option_index)) != -1) {
- for (i = 0; i < sizeof(g_option_handle) / sizeof(option_handle_t); i++) {
- if (ch != g_option_handle[i].option_value)
- continue;
+ write_lockfile(POWER_WAKE_LOCK_FILE, FOTA_UPGRADE_LOCK);
+
+ while ((ch = getopt_long(argc, argv, g_short_string, g_long_options, &option_index)) != -1)
+ {
+ for (i = 0; i < sizeof(g_option_handle) / sizeof(option_handle_t); i++)
+ {
+ if (ch != g_option_handle[i].option_value)
+ {
+ continue;
+ }
- cmd_num++;
+ cmd_num++;
- if (NULL == g_option_handle[i].func) {
- printf("Command short string is:%c, but option handle func is NULL", ch);
- break;
- }
+ if (NULL == g_option_handle[i].func)
+ {
+ printf("Command short string is:%c, but option handle func is NULL", ch);
+ break;
+ }
- ret = g_option_handle[i].func(optarg);
+ ret = g_option_handle[i].func(optarg);
- if (ret < 0) {
- ret = -1;
- goto end;
- }
- }
- }
+ if (ret < 0)
+ {
+ ret = -1;
+ goto end;
+ }
+ }
+ }
- if (0 == cmd_num) {
- printf("Can not find valid command!");
- usage();
- ret = -1;
- goto end;
- }
+ if (0 == cmd_num)
+ {
+ printf("Can not find valid command!");
+ usage();
+ ret = -1;
+ goto end;
+ }
- ret = 0;
+ ret = 0;
end:
- write_lockfile(POWER_WAKE_UNLOCK_FILE, FOTA_UPGRADE_LOCK);
+ write_lockfile(POWER_WAKE_UNLOCK_FILE, FOTA_UPGRADE_LOCK);
- return ret ;
+ return ret ;
}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fscheck/mtd.c b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fscheck/mtd.c
index c0d2b1b..fdcc42b 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fscheck/mtd.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/fscheck/mtd.c
@@ -589,12 +589,13 @@
printf("fs_check vol_id not match,vol_name:%s\n", p_fs->ubi_vol_name);
return -1;
}
-
+#if 0
if (mknod_ubi_device() < 0)
{
printf("fs_check ubi dev not found\n");
return -1;
}
+#endif
if (strcmp(p_fs->ubi_vol_name, "rootfs_data") == 0)
{
// openwrt
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/libsoftap/netapi.c b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/libsoftap/netapi.c
index a28620f..216fdfc 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/libsoftap/netapi.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/libsoftap/netapi.c
@@ -738,6 +738,7 @@
// read old data
sc_cfg_get("lan_ipaddr", lanIp_read, sizeof(lanIp_read));
sc_cfg_get("lan_netmask", lanNetmask_read, sizeof(lanNetmask_read));
+ sc_cfg_get("lan_netmask_cap", lanNetmask_read, sizeof(lanNetmask_read));
sc_cfg_get("dhcpStart", dhcpStart_read, sizeof(dhcpStart_read));
sc_cfg_get("dhcpEnd", dhcpEnd_read, sizeof(dhcpEnd_read));
sc_cfg_get("dhcpLease_hour", dhcpLeaseHour_read, sizeof(dhcpLeaseHour_read));
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/nvserver/Makefile b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/nvserver/Makefile
index eaaf617..2caae31 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/nvserver/Makefile
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/nvserver/Makefile
@@ -6,7 +6,7 @@
CFLAGS += -I$(LIB_DIR)/libnvram
CFLAGS += -I$(APP_DIR)/include
LDLIBS += -L$(LIB_DIR)/libnvram
-LDLIBS += -lpthread -lmtd -lnvram -lsofttimer -lupi_ab -lsoftap
+LDLIBS += -lpthread -lmtd -lnvram -lsofttimer -lupi_ab -lsoftap -lcrypto
all: $(EXEC)
$(EXEC): $(OBJS)
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/rtc-service/rtc-service.c b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/rtc-service/rtc-service.c
index 8772ad9..61722b1 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/rtc-service/rtc-service.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/platform/rtc-service/rtc-service.c
@@ -921,7 +921,7 @@
buf = (RTC_DATA_BUF *)pmsg_buf->aucDataBuf;
if (buf->cpu == RTC_CPU_AP) {
slog(RTC_PRINT, SLOG_NORMAL, "from ap: cmd:0x%x, module:0x%x, msg_id:0x%x, sec:%ld: %d, %d, %d \n", cmd, buf->module, buf->srcModule, buf->ulSec, buf->cpu, buf->is_utc, buf->wakeup);
- if((buf->module==RTC_ID_SC_TIMER)||(buf->module==RTC_ID_SC_ALARM))
+ if (buf->srcModule >= MODULE_ID_SDK_DYNAMIC_BASE)
{
send_rtc_msg(buf->srcModule,SC_RTC_MSG_CMD_TIMEOUT,(void *)buf, sizeof(RTC_DATA_BUF));
}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/data/sc_data.c b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/data/sc_data.c
index a4255cb..e803c4b 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/data/sc_data.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/data/sc_data.c
@@ -137,7 +137,7 @@
SCLOGI("scdata_timeout id=%d\n",id);
pthread_mutex_lock(&g_sc_datacall_mutex);
list_for_each_entry_safe(temp, temp1, &g_sc_datacall_list, list) {
- if(temp->id == (unsigned short)id){
+ if(temp->id == (unsigned short)id && temp->reconnect_mode != SCDATA_RECONN_NONE){
temp->action = SCDATA_ACTION_DOACT;
SCLOGI("scdata_timeout post id=%d\n",id);
sem_post(&g_sc_datacall_sem);
@@ -582,7 +582,7 @@
int cid = -1;
sc_pdp_info_t *temp = NULL;
sc_pdp_info_t *temp1 = NULL;
- char dev_name[16] = {0};
+ char dev_name[64] = {0};
SCLOGI("sc_data_call_get_pkt_stats start id=%d\n", id);
if(g_sc_datacall_thread == 0){
@@ -596,18 +596,19 @@
pthread_mutex_lock(&g_sc_datacall_mutex);
list_for_each_entry_safe(temp, temp1, &g_sc_datacall_list, list) {
if(temp->id == id){
- if(temp->req.act_type == SCDATA_ACT_TYPE_LOCAL)
+ //if(temp->req.act_type == SCDATA_ACT_TYPE_LOCAL)
cid = temp->rsp.c_id;
- else
- cid = 0;
+ //else
+ //cid = 0;
break;
}
}
pthread_mutex_unlock(&g_sc_datacall_mutex);
SCLOGI("call_get_stats cid=%d\n", cid);
- if(cid < 0){
+ if(cid < 0 || cid > CID_MAX_NUM){
return SC_ERR_BADPARAM;
}
+#if 0
snprintf(dev_name, sizeof(dev_name), "zvnet%d", cid);
getIfStatistic(dev_name, TXBYTE, &p_sta->tx_bytes);
getIfStatistic(dev_name, TXPACKET, &p_sta->tx_packets);
@@ -617,7 +618,20 @@
getIfStatistic(dev_name, RXPACKET, &p_sta->rx_packets);
getIfStatistic(dev_name, RXERR, &p_sta->rx_errors);
getIfStatistic(dev_name, RXDROP, &p_sta->rx_dropped);
-
+#else
+ char param[8][24] = {0};
+ void *p[] = {param[0], param[1], param[2], param[3], param[4], param[5], param[6], param[7]};
+ snprintf(dev_name, sizeof(dev_name), "AT+FLUXSTAT=wan%d\r\n", cid);
+ get_modem_info(dev_name, "%s,%s,%s,%s,%s,%s,%s,%s", (void **)p);
+ p_sta->tx_bytes = atoll(param[0]);
+ p_sta->tx_packets = atoll(param[1]);
+ p_sta->tx_errors = atoll(param[2]);
+ p_sta->tx_dropped = atoll(param[3]);
+ p_sta->rx_bytes = atoll(param[4]);
+ p_sta->rx_packets = atoll(param[5]);
+ p_sta->rx_errors = atoll(param[6]);
+ p_sta->rx_dropped = atoll(param[7]);
+#endif
return SC_ERR_SUCCESS;
}
@@ -632,7 +646,7 @@
SCLOGE("sc_data not init");
return SC_ERR_FAIL;
}
- if((mode != SCDATA_RECONN_LOOP && mode != SCDATA_RECONN_MULT) || num > MAX_TIME_LIST){//|| time_list == NULL
+ if((mode != SCDATA_RECONN_LOOP && mode != SCDATA_RECONN_MULT && mode != SCDATA_RECONN_NONE) || num > MAX_TIME_LIST){//|| time_list == NULL
SCLOGE("set_reconnect mode=%d list=%p num=%d null", mode, time_list, num);
return SC_ERR_BADPARAM;
}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/include/sc_data.h b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/include/sc_data.h
index 22b19be..eaf9aa3 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/include/sc_data.h
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/include/sc_data.h
@@ -96,10 +96,9 @@
/**
* @brief ¶¨Òå×Ô¶¯ÖØÁ¬ÀàÐÍ
-* @param SCDATA_RECONN_NONE ³õʼֵ£¬²»½øÐÐÈκβÙ×÷
+* @param SCDATA_RECONN_NONE ³õʼֵ,²»½øÐÐÈκβÙ×÷,¿É¹Ø±Õ×Ô¶¯ÖØÁ¬
* @param SCDATA_RECONN_LOOP ³¬Ê±Ê±¼äÑ»·,´ïµ½×îºóÒ»¸öºóÏ´ÎÓõÚÒ»¸ö³¬Ê±Ê±¼ä
* @param SCDATA_RECONN_MULT ³¬Ê±Ê±¼ä´ïµ½×îºóÒ»¸öʱһֱÓÃ×îºóÒ»¸ö³¬Ê±Ê±¼ä
-* @param SCDATA_AUTH_PAP_CHAP PAP+CHAPÈÏÖ¤
*/
typedef enum {
SCDATA_RECONN_NONE = 0,
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/include/sc_rtc_timer.h b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/include/sc_rtc_timer.h
index 94aba9f..d37dc17 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/include/sc_rtc_timer.h
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/include/sc_rtc_timer.h
@@ -3,12 +3,12 @@
* @brief RTC¶¨Ê±Æ÷½Ó¿Ú
*
* Copyright (C) 2023 Sanechips Technology Co., Ltd.
- * @author
- * @ingroup
- *
+ * @author
+ * @ingroup
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * published by the Free Software Foundation.
*
*/
#ifndef _SC_RTC_TIMER_H
@@ -37,45 +37,48 @@
******************************************************************************/
typedef struct
{
- int srcModule;
- unsigned int module;
- unsigned long ulSec;
- unsigned long time_val;
- int wakeup;
- int is_utc;
- int cpu;
-}sc_rtc_data_info;
+ int srcModule;
+ unsigned int module;
+ unsigned long ulSec;
+ unsigned long time_val;
+ int wakeup;
+ int is_utc;
+ int cpu;
+} sc_rtc_data_info;
-typedef struct{
- unsigned long time;
- unsigned int src_id;
+typedef struct
+{
+ unsigned long time;
+ unsigned int src_id;
} sc_rtc_user_t;
/****************************************************************************
* Timer expire callback function Definition
***************************************************************************/
-typedef int (*sc_rtc_timer_exp_cb)(unsigned int src_id);
+typedef int (*sc_rtc_timer_exp_cb)(unsigned int src_id, int rtc_id);
/****************************************************************************
* Get rtc time callback function Definition
***************************************************************************/
-typedef int (*sc_rtc_time_get_cb)(unsigned int src_id,unsigned long ulsec);
+typedef int (*sc_rtc_time_get_cb)(unsigned int src_id, unsigned long ulsec);
-typedef struct{
- struct list_head list;
- unsigned long time;
- unsigned int src_id;
- sc_rtc_time_get_cb rtc_time_get_cb;
- sc_rtc_timer_exp_cb rtc_timerout_cb;
+typedef struct
+{
+ struct list_head list;
+ unsigned long time;
+ unsigned int src_id;
+ unsigned int rtc_id;
+ sc_rtc_time_get_cb rtc_time_get_cb;
+ sc_rtc_timer_exp_cb rtc_timerout_cb;
} sc_rtc_user_cb_t;
/*******************************************************************************
* Global variable declarations *
******************************************************************************/
-
+
/*******************************************************************************
* Global function declarations *
******************************************************************************/
@@ -83,8 +86,8 @@
* @brief ³õʼ»¯¿Í»§¶ËRTC½Ó¿Ú·þÎñ¡£
* @param (in) ÎÞ¡£
* @param (out) ÎÞ¡£
- * @return 0 - ³É¹¦
- * ÆäËüʧ°Ü:
+ * @return ³É¹¦-·µ»Ø·ÖÅäµÄsrcid
+ * ʧ°Ü-·µ»Ø-1
* @note ×¢ÊÍ
* ×¢ÊÍ¡£
*/
@@ -95,7 +98,7 @@
* @param (in) ÎÞ¡£
* @param (out) ÎÞ¡£
* @return 0 - ³É¹¦
- * ÆäËüʧ°Ü:
+ * ÆäËû-ʧ°Ü
* @note ×¢ÊÍ
* ×¢ÊÍ¡£
*/
@@ -103,24 +106,24 @@
/**
* @brief ÉèÖÃrtc¶¨Ê±Æ÷¡£
- * @param (in) ulSec ¶¨Ê±Ê±¼ä£¨Ã룩¡£
- * srcid Óû§ID¡£
- * sc_rtc_idÔÝÎÞÓÃ
+ * @param (in) srcid Óû§IDΪµ÷ÓÃsc_rtc_timer_init¿Í»§¶Ë³õʼ»¯º¯Êý·ÖÅäµÄsrcid¼´¸Ãº¯Êý·µ»ØÖµ¡£
+ * rtc_id ¶¨Ê±Æ÷ID¡£
+ * ulSec ¶¨Ê±Ê±¼ä£¨Ã룩¡£
* rtc_notifyÓû§×¢²áµÄ»Øµ÷º¯Êý
* @param (out) ÎÞ¡£
* @return 0 - ³É¹¦
- * ÆäËüʧ°Ü:
+ * ÆäËû-ʧ°Ü
* @note ×¢ÊÍ
* ×¢ÊÍ¡£
*/
-int sc_rtc_timer_add(unsigned long ulSec, int srcid, sc_rtc_timer_exp_cb rtc_notify);
+int sc_rtc_timer_add(int srcid, int rtc_id, unsigned long ulSec, sc_rtc_timer_exp_cb rtc_notify);
/**
* @brief »ñÈ¡rtcʱ¼ä¡£
- * @param (in) srcid Óû§ID¡£
+ * @param (in) srcid Óû§IDΪµ÷ÓÃsc_rtc_timer_init¿Í»§¶Ë³õʼ»¯º¯Êý·ÖÅäµÄsrcid¼´¸Ãº¯Êý·µ»ØÖµ¡£
* @param (out) rtc_notifyÓû§×¢²áµÄ»Øµ÷º¯Êý¡£
* @return 0 - ³É¹¦
- * ÆäËüʧ°Ü:
+ * ÆäËû-ʧ°Ü
* @note ×¢ÊÍ
* ×¢ÊÍ¡£
*/
@@ -128,11 +131,10 @@
/**
* @brief ÉèÖÃrtcʱ¼ä¡£
- * @param (in) srcid Óû§ID¡£
- * ulsec ÔÝʱÎÞÓÃ.
- * @param (out) rtc_notifyÓû§×¢²áµÄ»Øµ÷º¯Êý¡£
+ * @param (in) srcid Óû§IDΪµ÷ÓÃsc_rtc_timer_init¿Í»§¶Ë³õʼ»¯º¯Êý·ÖÅäµÄsrcid¼´¸Ãº¯Êý·µ»ØÖµ¡£
+ * @param (out) ÎÞ¡£
* @return 0 - ³É¹¦
- * ÆäËüʧ°Ü:
+ * ÆäËû-ʧ°Ü
* @note ×¢ÊÍ
* ×¢ÊÍ¡£
*/
@@ -140,18 +142,30 @@
/**
* @brief ÉèÖÃrtc¶¨Ê±Æ÷(utc,¶¨Ê±µ½/Äê/ÔÂ/ÈÕ/ʱ/·Ö/Ãë)¡£
- * @param (in) utc_sec ¶¨Ê±Ê±¼ä£¨/Äê/ÔÂ/ÈÕ/ʱ/·Ö/Ã룩¡£
- * srcid Óû§ID¡£
- * sc_rtc_idÔÝÎÞÓÃ
+ * @param (in) srcid Óû§IDΪµ÷ÓÃsc_rtc_timer_init¿Í»§¶Ë³õʼ»¯º¯Êý·ÖÅäµÄsrcid¼´¸Ãº¯Êý·µ»ØÖµ¡£
+ * rtc_idÄÖÖÓID¼´¶¨Ê±Æ÷ID
+ * utc_sec¶¨Ê±Ê±¼ä£¨/Äê/ÔÂ/ÈÕ/ʱ/·Ö/Ã룩¡£
* wakeupÔÝÎÞÓÃ
* rtc_notifyÓû§×¢²áµÄ»Øµ÷º¯Êý
* @param (out) ÎÞ¡£
* @return 0 - ³É¹¦
- * ÆäËüʧ°Ü:
+ * ÆäËû-ʧ°Ü
* @note ×¢ÊÍ
* ×¢ÊÍ¡£
*/
-int sc_rtc_timer_add_utc(struct tm *utc_sec, int srcid, int wakeup,sc_rtc_timer_exp_cb rtc_notify);
+int sc_rtc_timer_add_utc(int srcid, int rtc_id, struct tm *utc_sec, int wakeup, sc_rtc_timer_exp_cb rtc_notify);
+
+/**
+ * @brief ɾ³ýÖ¸¶¨rtc¶¨Ê±Æ÷¡£
+ * @param (in) srcid Óû§IDΪµ÷ÓÃsc_rtc_timer_init¿Í»§¶Ë³õʼ»¯º¯Êý·ÖÅäµÄsrcid¼´¸Ãº¯Êý·µ»ØÖµ¡£
+ * rtc_id¶¨Ê±Æ÷ID
+ * @param (out) ÎÞ¡£
+ * @return 0 - ³É¹¦
+ * ÆäËû-ʧ°Ü
+ * @note ×¢ÊÍ
+ * ×¢ÊÍ¡£
+ */
+int sc_rtc_timer_del(int srcid, int rtc_id);
#ifdef __cplusplus
}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/rtc_timer/sc_rtc_timer.c b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/rtc_timer/sc_rtc_timer.c
index cfa1eff..7442b95 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/rtc_timer/sc_rtc_timer.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/libsctel/rtc_timer/sc_rtc_timer.c
@@ -22,134 +22,262 @@
static int sc_rtc_timer_have_init = 0;
sc_rtc_user_cb_t sc_rtc_cb;
+struct list_head sc_rtc_cb_list;
+pthread_mutex_t g_rtc_timer_mutex = PTHREAD_MUTEX_INITIALIZER;
+
+static sc_rtc_user_cb_t* sc_rtc_timer_find_by_id(int rtc_id)
+{
+ sc_rtc_user_cb_t *entry;
+ if (!list_empty(&sc_rtc_cb_list))
+ {
+ list_for_each_entry(entry, &sc_rtc_cb_list, list)
+ {
+ if (entry->rtc_id == rtc_id)
+ {
+ return entry;
+ }
+ }
+ }
+
+ return NULL;
+}
+
+static void sc_rtc_timer_free_by_id(int rtc_id)
+{
+ sc_rtc_user_cb_t *pTmp, *pTmp1;
+ if (!list_empty(&sc_rtc_cb_list))
+ {
+ list_for_each_entry_safe(pTmp, pTmp1, &sc_rtc_cb_list, list)
+ {
+ if (pTmp && pTmp->rtc_id == rtc_id)
+ {
+ list_del(&(pTmp->list));
+ free(pTmp);
+ }
+ }
+ }
+}
static int sc_rtc_timeout_cb(const sc_ipc_event* const pevt, const sc_ipc_msg* const pmsg)
{
- int ret = 0;
- sc_rtc_data_info *rtc_info = NULL;
- rtc_info = (sc_rtc_data_info*)pmsg->data;
+ int ret = 0;
+ sc_rtc_data_info *rtc_info = NULL;
+ rtc_info = (sc_rtc_data_info*)pmsg->data;
- ret = sc_rtc_cb.rtc_timerout_cb(rtc_info->srcModule);
- return SC_ERR_SUCCESS;
-}
+ sc_rtc_user_cb_t *timer_cb = NULL;
-static int sc_rtc_get_time_cb(const sc_ipc_event* const pevt, const sc_ipc_msg* const pmsg)
-{
- int ret = 0;
- sc_rtc_data_info *rtc_info = NULL;
- rtc_info = (sc_rtc_data_info*)pmsg->data;
+ pthread_mutex_lock(&g_rtc_timer_mutex);
- ret = sc_rtc_cb.rtc_time_get_cb(rtc_info->srcModule,rtc_info->ulSec);
+ timer_cb = sc_rtc_timer_find_by_id(rtc_info->module);
+
+ if (NULL != timer_cb)
+ {
+ if (timer_cb->rtc_timerout_cb)
+ {
+ timer_cb->rtc_timerout_cb(rtc_info->srcModule, rtc_info->module);
+ }
+
+ sc_rtc_timer_free_by_id(rtc_info->module);
+ }
+ else
+ {
+ SCLOGD("Don't find callback function! \n");
+ }
+ pthread_mutex_unlock(&g_rtc_timer_mutex);
return SC_ERR_SUCCESS;
}
-static sc_ipc_event rtc_timer_auto_notify_evt[] = {
- {0, 1, 0, SC_RTC_MSG_CMD_GET_TIME_RSP, sc_rtc_get_time_cb, NULL, NULL},
- {0, 1, 0, SC_RTC_MSG_CMD_TIMEOUT, sc_rtc_timeout_cb, NULL, NULL},
+static int sc_rtc_get_time_cb(const sc_ipc_event* const pevt, const sc_ipc_msg* const pmsg)
+{
+ int ret = 0;
+ sc_rtc_data_info *rtc_info = NULL;
+ rtc_info = (sc_rtc_data_info*)pmsg->data;
+
+ ret = sc_rtc_cb.rtc_time_get_cb(rtc_info->srcModule, rtc_info->ulSec);
+ return SC_ERR_SUCCESS;
+}
+
+static sc_ipc_event rtc_timer_auto_notify_evt[] =
+{
+ {0, 1, 0, SC_RTC_MSG_CMD_GET_TIME_RSP, sc_rtc_get_time_cb, NULL, NULL},
+ {0, 1, 0, SC_RTC_MSG_CMD_TIMEOUT, sc_rtc_timeout_cb, NULL, NULL},
};
static int sc_rtc_timer_connect(void)
{
- int rtc_client_id = -1;
- int ret = -1;
- rtc_client_id = sc_ipc_get_self_fd();
+ int rtc_client_id = -1;
+ int ret = -1;
+ rtc_client_id = sc_ipc_get_self_fd();
- if(rtc_client_id!=-1)
- {
- sc_rtc_cb.src_id = rtc_client_id;
- ret = 0;
- }
- else
- {
- return -1;
- }
-
- return ret;
+ if (rtc_client_id != -1)
+ {
+ sc_rtc_cb.src_id = rtc_client_id;
+ ret = 0;
+ }
+ else
+ {
+ return -1;
+ }
+
+ return ret;
}
int sc_rtc_timer_init(void)
{
- if(sc_rtc_timer_have_init)
- {
- return SC_ERR_SUCCESS;
- }
- sc_ipc_start_loop(NULL);
-
- /* 注册主动上报消息处理*/
- sc_ipc_register_events(rtc_timer_auto_notify_evt, sizeof(rtc_timer_auto_notify_evt) / sizeof(sc_ipc_event));
-
- if(0 == sc_rtc_timer_connect( ))
- {
- SCLOGD("sc_rtc_timer_init connect success.\n");
- SCLOGD("sc_rtc_timer_init finish\n");
-
- return sc_rtc_cb.src_id;
- }
-
- return -1;
+ if (sc_rtc_timer_have_init)
+ {
+ return SC_ERR_SUCCESS;
+ }
+ sc_ipc_start_loop(NULL);
+
+ /* 注册主动上报消息处理*/
+ sc_ipc_register_events(rtc_timer_auto_notify_evt, sizeof(rtc_timer_auto_notify_evt) / sizeof(sc_ipc_event));
+
+ /*初始化回调链表*/
+ INIT_LIST_HEAD(&sc_rtc_cb_list);
+
+ if (0 == sc_rtc_timer_connect( ))
+ {
+ SCLOGD("sc_rtc_timer_init connect success.\n");
+ SCLOGD("sc_rtc_timer_init finish\n");
+
+ return sc_rtc_cb.src_id;
+ }
+
+ return -1;
}
int sc_rtc_timer_uninit(void)
{
- int i;
-
- sc_ipc_event *pevt;
-
- sc_rtc_timer_have_init = 0;
-
- for(i = 0; i < sizeof(rtc_timer_auto_notify_evt) / sizeof(sc_ipc_event); i ++)
- {
- pevt = &rtc_timer_auto_notify_evt[i];
- sc_ipc_event_del(pevt);
- }
-
- SCLOGD("sc_rtc_timer_uninit finish\n");
- return SC_ERR_SUCCESS;
+ int i;
+
+ sc_ipc_event *pevt;
+
+ sc_rtc_timer_have_init = 0;
+
+ for (i = 0; i < sizeof(rtc_timer_auto_notify_evt) / sizeof(sc_ipc_event); i ++)
+ {
+ pevt = &rtc_timer_auto_notify_evt[i];
+ sc_ipc_event_del(pevt);
+ }
+
+ SCLOGD("sc_rtc_timer_uninit finish\n");
+ return SC_ERR_SUCCESS;
}
int sc_rtc_time_set(int srcid)
-{
- int ret = -1;
+{
+ int ret = -1;
- ret = rtc_set_time(srcid);
-
- return ret;
+ ret = rtc_set_time(srcid);
+
+ return ret;
}
-int sc_rtc_timer_add(unsigned long ulSec, int srcid, sc_rtc_timer_exp_cb rtc_notify)
+int sc_rtc_timer_add(int srcid, int rtc_id, unsigned long ulSec, sc_rtc_timer_exp_cb rtc_notify)
{
- int ret = -1;
+ int ret = -1;
- if(ulSec<=0)
- {
- return ret;
- }
+ if (ulSec <= 0)
+ {
+ return ret;
+ }
- sc_rtc_cb.rtc_timerout_cb = rtc_notify;
- ret = rtc_timer_add(ulSec,RTC_ID_SC_TIMER,srcid);
+ sc_rtc_user_cb_t *rtc_cb = NULL;
+ sc_rtc_user_cb_t *rtc_cb_exist = NULL;
+ sc_rtc_user_cb_t *pTmp, *pTmp1;
- return ret;
+ pthread_mutex_lock(&g_rtc_timer_mutex);
+
+ rtc_cb_exist = sc_rtc_timer_find_by_id(rtc_id);
+
+ if (!rtc_cb_exist) //不存在
+ {
+ rtc_cb = malloc(sizeof(sc_rtc_user_cb_t));
+ if (rtc_cb == NULL)
+ {
+ pthread_mutex_unlock(&g_rtc_timer_mutex);
+ return -1;
+ }
+ rtc_cb->src_id = srcid;
+ rtc_cb->rtc_id = rtc_id;
+ rtc_cb->time = ulSec;
+ rtc_cb->rtc_timerout_cb = rtc_notify;
+ list_add_tail(&rtc_cb->list, &sc_rtc_cb_list);
+ }
+ else
+ {
+ SCLOGD("rtc timer already exists,adding timer failed!\n");
+ pthread_mutex_unlock(&g_rtc_timer_mutex);
+ return -1;
+ }
+ pthread_mutex_unlock(&g_rtc_timer_mutex);
+
+ ret = rtc_timer_add(ulSec, rtc_id, srcid);
+
+ return ret;
}
-int sc_rtc_timer_add_utc(struct tm *utc_sec, int srcid, int wakeup,sc_rtc_timer_exp_cb rtc_notify)
+int sc_rtc_timer_add_utc(int srcid, int rtc_id, struct tm *utc_sec, int wakeup, sc_rtc_timer_exp_cb rtc_notify)
{
- time_t ulsec = 0;
- int ret = -1;
-
- ulsec = mktime(utc_sec);
- sc_rtc_cb.rtc_timerout_cb = rtc_notify;
- ret = rtc_timer_add_utc(utc_sec,RTC_ID_SC_ALARM,srcid,wakeup);
+ int ret = -1;
- return ret;
+ sc_rtc_user_cb_t *rtc_cb = NULL;
+ sc_rtc_user_cb_t *rtc_cb_exist = NULL;
+ sc_rtc_user_cb_t *pTmp, *pTmp1;
+
+ pthread_mutex_lock(&g_rtc_timer_mutex);
+
+ rtc_cb_exist = sc_rtc_timer_find_by_id(rtc_id);
+
+ if (!rtc_cb_exist) //²»´æÔÚ
+ {
+ rtc_cb = malloc(sizeof(sc_rtc_user_cb_t));
+ if (rtc_cb == NULL)
+ {
+ pthread_mutex_unlock(&g_rtc_timer_mutex);
+ return -1;
+ }
+ rtc_cb->src_id = srcid;
+ rtc_cb->rtc_id = rtc_id;
+ rtc_cb->rtc_timerout_cb = rtc_notify;
+ list_add_tail(&rtc_cb->list, &sc_rtc_cb_list);
+ }
+ else
+ {
+ SCLOGD("rtc timer already exists,adding timer failed!\n");
+ pthread_mutex_unlock(&g_rtc_timer_mutex);
+ return -1;
+ }
+ pthread_mutex_unlock(&g_rtc_timer_mutex);
+
+ ret = rtc_timer_add_utc(utc_sec, rtc_id, srcid, wakeup);
+
+ return ret;
}
int sc_rtc_time_get(int srcid, sc_rtc_time_get_cb rtc_notify)
{
- int ret =-1;
+ int ret = -1;
- sc_rtc_cb.rtc_time_get_cb = rtc_notify;
- ret = rtc_get_time(srcid);
-
- return ret;
+ sc_rtc_cb.rtc_time_get_cb = rtc_notify;
+ ret = rtc_get_time(srcid);
+
+ return ret;
+}
+
+int sc_rtc_timer_del(int srcid, int rtc_id)
+{
+ int ret = -1;
+
+ ret = rtc_timer_del(rtc_id, srcid);
+
+ pthread_mutex_lock(&g_rtc_timer_mutex);
+
+ sc_rtc_timer_free_by_id(rtc_id);
+
+ pthread_mutex_unlock(&g_rtc_timer_mutex);
+
+ return ret;
}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/dma/zte/Kconfig b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/ril/nanopb-c/tests/special_characters/funny-proto+name has.characters.proto
old mode 100644
new mode 100755
similarity index 100%
rename from cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/dma/zte/Kconfig
rename to cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/sdk/ril/nanopb-c/tests/special_characters/funny-proto+name has.characters.proto
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/crc_api/crc_api.c b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/crc_api/crc_api.c
index a15d226..0a6badf 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/crc_api/crc_api.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/crc_api/crc_api.c
@@ -82,7 +82,7 @@
exit(1);
}
}
-
+#if 0
int32_t com_Convbaud(uint32_t iBaudrate)
{
switch(iBaudrate)
@@ -110,12 +110,12 @@
}
}
-
+#endif
static int zUP_SetPort(int32_t iFd , int iBaud, int iDelay)
{
int ret = 0;
- attr_set.baudrate = com_Convbaud(iBaud);
-
+ attr_set.baudrate = iBaud;//com_Convbaud(iBaud);
+ printf("zUP_SetPort, iBaud:%d\n", iBaud );
ret = sc_uart_set_termios(iFd, &attr_set);
if(ret != 0)
{
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/ethtest/ethtest.c b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/ethtest/ethtest.c
old mode 100644
new mode 100755
index 34fbe0c..2185078
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/ethtest/ethtest.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/ethtest/ethtest.c
@@ -165,7 +165,8 @@
default:
printf("\nInvalid Case");
- break;
+ return 0;
}
+ return 0;
}
}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/rtc_timer_demo/sc_rtc_timer_main.c b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/rtc_timer_demo/sc_rtc_timer_main.c
index 62ffac2..b1332a7 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/rtc_timer_demo/sc_rtc_timer_main.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/rtc_timer_demo/sc_rtc_timer_main.c
@@ -21,259 +21,294 @@
#define CMD_SET "set\n"
#define CMD_GET "get\n"
#define CMD_HELP "?\n"
+#define CMD_DEL "del\n"
#define CMD_Q "q\n"
-static int year=0;
-static int mouth=0;
-static int date=0;
-static int hour=0;
-static int minute=0;
-static int seconds=0;
-static int wakeup=0;
-static int demo=0;
-static int timer_sec=0;
+static int year = 0;
+static int mouth = 0;
+static int date = 0;
+static int hour = 0;
+static int minute = 0;
+static int seconds = 0;
+static int wakeup = 0;
+static int demo = 0;
+static int timer_sec = 0;
static void printUsage(const char *Opt)
{
- printf("Usage: %s\n", Opt);
- printf("-Y<Year> set year,please input number\n");
- printf("-M<Mouth> set mouth,please input number\n");
- printf("-D<Date> set date,please input number\n");
- printf("-h<hour> set hour,please input number\n");
- printf("-m<minute> set minute,please input number\n");
- printf("-s<sec> set seconds,please input number\n");
- printf("-w<wakeup> set timer wakeup\n");
- printf("-d<callback demo> set callback demo,please input number\n");
- printf("add add rtc timer\n");
- printf("add_utc add rtc utc timer\n");
- printf("set set rtc time\n");
- printf("get get rtc time\n");
- printf("q exit rtc-timer-demo\n");
+ printf("Usage: %s\n", Opt);
+ printf("-Y<Year> set year,please input number\n");
+ printf("-M<Mouth> set mouth,please input number\n");
+ printf("-D<Date> set date,please input number\n");
+ printf("-h<hour> set hour,please input number\n");
+ printf("-m<minute> set minute,please input number\n");
+ printf("-s<sec> set seconds,please input number\n");
+ printf("-w<wakeup> set timer wakeup\n");
+ printf("-d<callback demo> set callback demo,please input number\n");
+ printf("add add rtc timer\n");
+ printf("add_utc add rtc utc timer\n");
+ printf("set set rtc time\n");
+ printf("get get rtc time\n");
+ printf("q exit rtc-timer-demo\n");
}
-static int parseOpts(int argc, char *argv[])
+static int parseOpts(int argc, char *argv[])
{
- int rc = 0;
+ int rc = 0;
int c;
- while ((c = getopt(argc, argv, "?Y:M:D:h:m:s:w:d:t:")) != -1) {
- switch (c) {
- case 'Y':
- year = atoi(optarg);
- break;
- case 'M':
- mouth = atoi(optarg);
- break;
- case 'D':
- date = atoi(optarg);
- break;
- case 'h':
- hour = atoi(optarg);
- break;
- case 'm':
- minute = atoi(optarg);
- break;
- case 's':
- seconds = atoi(optarg);
- break;
- case 'w':
- wakeup = atoi(optarg);
- break;
- case 'd':
- demo = atoi(optarg);
- break;
- case 't':
- timer_sec = atoi(optarg);
- break;
- case '?':
- default:
- printUsage(argv[0]);
- return -1;
+ while ((c = getopt(argc, argv, "?Y:M:D:h:m:s:w:d:t:")) != -1)
+ {
+ switch (c)
+ {
+ case 'Y':
+ year = atoi(optarg);
+ break;
+ case 'M':
+ mouth = atoi(optarg);
+ break;
+ case 'D':
+ date = atoi(optarg);
+ break;
+ case 'h':
+ hour = atoi(optarg);
+ break;
+ case 'm':
+ minute = atoi(optarg);
+ break;
+ case 's':
+ seconds = atoi(optarg);
+ break;
+ case 'w':
+ wakeup = atoi(optarg);
+ break;
+ case 'd':
+ demo = atoi(optarg);
+ break;
+ case 't':
+ timer_sec = atoi(optarg);
+ break;
+ case '?':
+ default:
+ printUsage(argv[0]);
+ return -1;
}
}
return rc;
}
-int rtc_get_time_cb_demo0(unsigned int srcid,unsigned long ulsec)
+int rtc_get_time_cb_demo0(unsigned int srcid, unsigned long ulsec)
{
- struct tm rtc_time = {0};
- time_t tmp = 0;
+ struct tm rtc_time = {0};
+ time_t tmp = 0;
- tmp = (time_t)ulsec;
-
- rtc_time = *localtime(&tmp);
-
- printf("user id(srcid):0x%x,callback(rtc_get_time_cb_demo0) is success,%ld-%d-%d,%d:%d:%d!\n",srcid,rtc_time.tm_year+1900,rtc_time.tm_mon+1,rtc_time.tm_mday,rtc_time.tm_hour,rtc_time.tm_min,rtc_time.tm_sec);
+ tmp = (time_t)ulsec;
+
+ rtc_time = *localtime(&tmp);
+
+ printf("user id(srcid):0x%x,callback(rtc_get_time_cb_demo0) is success,%ld-%d-%d,%d:%d:%d!\n", srcid,
+ rtc_time.tm_year + 1900, rtc_time.tm_mon + 1, rtc_time.tm_mday, rtc_time.tm_hour, rtc_time.tm_min, rtc_time.tm_sec);
}
-int rtc_get_time_cb_demo1(unsigned int srcid,unsigned long ulsec)
+int rtc_get_time_cb_demo1(unsigned int srcid, unsigned long ulsec)
{
- struct tm rtc_time = {0};
- time_t tmp = 0;
+ struct tm rtc_time = {0};
+ time_t tmp = 0;
- tmp = (time_t)ulsec;
-
- rtc_time = *localtime(&tmp);
-
- printf("user id:0x%x,callback(rtc_get_time_cb_demo1) is success,%ld-%d-%d,%d:%d:%d!\n",srcid,rtc_time.tm_year+1900,rtc_time.tm_mon+1,rtc_time.tm_mday,rtc_time.tm_hour,rtc_time.tm_min,rtc_time.tm_sec);
+ tmp = (time_t)ulsec;
+
+ rtc_time = *localtime(&tmp);
+
+ printf("user id:0x%x,callback(rtc_get_time_cb_demo1) is success,%ld-%d-%d,%d:%d:%d!\n", srcid, rtc_time.tm_year + 1900,
+ rtc_time.tm_mon + 1, rtc_time.tm_mday, rtc_time.tm_hour, rtc_time.tm_min, rtc_time.tm_sec);
}
-int sc_rtc_timer_id_exp_cb_demo0(unsigned int src_id)
+int sc_rtc_timer_id_exp_cb_demo0(unsigned int src_id, int rtc_id)
{
- int ret =0;
+ int ret = 0;
- printf("user id:0x%x,callback(sc_rtc_timer_exp_cb_demo0) is success!\n",src_id);
+ printf("user id:0x%x,rtc id:%d,callback(sc_rtc_timer_exp_cb_demo0) is success!\n", src_id, rtc_id);
- return ret;
+ return ret;
}
-int sc_rtc_timer_id_exp_cb_demo1(unsigned int src_id)
+int sc_rtc_timer_id_exp_cb_demo1(unsigned int src_id, int rtc_id)
{
- int ret =0;
+ int ret = 0;
- printf("user id:0x%x,callback(sc_rtc_timer_exp_cb_demo1) is success!\n",src_id);
+ printf("user id:0x%x,rtc id:%d,callback(sc_rtc_timer_exp_cb_demo1) is success!\n", src_id, rtc_id);
- return ret;
+ return ret;
}
static int rtc_timer_init(void)
{
- int ret = 0;
-
- ret = sc_rtc_timer_init( );
- if(ret <= 0 ) {
- return -1;
- }
-
- return ret;
+ int ret = 0;
+
+ ret = sc_rtc_timer_init( );
+ if (ret <= 0 )
+ {
+ return -1;
+ }
+
+ return ret;
}
static int rtc_timer_deinit(void)
{
- return sc_rtc_timer_uninit();
+ return sc_rtc_timer_uninit();
}
-static int sc_rtc_timer_add_utc_demo(struct tm *utc_sec, int src_id, int wakeup,sc_rtc_timer_exp_cb rtc_cb)
+static int sc_rtc_timer_add_utc_demo(struct tm *utc_sec, int src_id, int rtc_id, int wakeup, sc_rtc_timer_exp_cb rtc_cb)
{
- int iRet = -1;
-
- printf("sc_rtc_timer_add_utc_demo test \n");
-
- iRet = sc_rtc_timer_add_utc(utc_sec, src_id, wakeup, rtc_cb);
-
- printf("iRet=%d\n", iRet);
-
- return 0;
+ int iRet = -1;
+
+ printf("sc_rtc_timer_add_utc_demo test \n");
+
+ iRet = sc_rtc_timer_add_utc(src_id, rtc_id, utc_sec, wakeup, rtc_cb);
+
+ printf("iRet=%d\n", iRet);
+
+ return 0;
}
-static int sc_rtc_timer_add_demo(int srcid,unsigned long ulsec,sc_rtc_timer_exp_cb rtc_cb)
+static int sc_rtc_timer_add_demo(int srcid, int rtc_id, unsigned long ulsec, sc_rtc_timer_exp_cb rtc_cb)
{
- int iRet = -1;
+ int iRet = -1;
- printf("sc_rtc_timer_add_demo test \n");
-
- iRet = sc_rtc_timer_add(ulsec, srcid, rtc_cb);
-
- printf("iRet=%d\n", iRet);
+ printf("sc_rtc_timer_add_demo test \n");
- return 0;
+ iRet = sc_rtc_timer_add(srcid, rtc_id, ulsec, rtc_cb);
+
+ printf("iRet=%d\n", iRet);
+
+ return 0;
+}
+
+static int sc_rtc_timer_del_demo(int srcid, int rtc_id)
+{
+ int iRet = -1;
+
+ printf("sc_rtc_timer_del_demo test \n");
+
+ iRet = sc_rtc_timer_del(srcid, rtc_id);
+
+ printf("iRet=%d\n", iRet);
+
+ return 0;
}
static int sc_rtc_set_time_demo(int src_id)
{
- int iRet = -1;
+ int iRet = -1;
- printf("sc_rtc_set_time_demo test \n");
-
- iRet = sc_rtc_time_set(src_id);
-
- printf("iRet=%d\n", iRet);
+ printf("sc_rtc_set_time_demo test \n");
- return 0;
+ iRet = sc_rtc_time_set(src_id);
+
+ printf("iRet=%d\n", iRet);
+
+ return 0;
}
-static int sc_rtc_get_time_demo(int src_id,sc_rtc_time_get_cb rtc_cb)
+static int sc_rtc_get_time_demo(int src_id, sc_rtc_time_get_cb rtc_cb)
{
- int iRet = -1;
+ int iRet = -1;
- printf("sc_rtc_get_time_demo test \n");
-
- iRet = sc_rtc_time_get(src_id,rtc_cb);
-
- printf("iRet=%d\n", iRet);
+ printf("sc_rtc_get_time_demo test \n");
- return 0;
+ iRet = sc_rtc_time_get(src_id, rtc_cb);
+
+ printf("iRet=%d\n", iRet);
+
+ return 0;
}
int main(int argc, char *argv[])
{
- char atstr[15] = {0};
- int len = 0;
- int srcid = 0 ;
- printf("sc_rtc_timer_demo:Demo go.\n");
+ char atstr[15] = {0};
+ int len = 0;
+ int srcid = 0 ;
+ printf("sc_rtc_timer_demo:Demo go.\n");
- if(parseOpts(argc,argv) == -1)
- {
- printf("sc_rtc_timer_demo:Arg error.\n");
- return -1;
- }
+ if (parseOpts(argc, argv) == -1)
+ {
+ printf("sc_rtc_timer_demo:Arg error.\n");
+ return -1;
+ }
- if((srcid = rtc_timer_init( )) <= 0)
- {
- printf("rtc_timer_demo:rtc_timer_init fail!\n");
- return 0;
- }
- printf("srcid:0x%x\n",srcid);
- while(1)
- {
- memset(atstr,0,sizeof(atstr));
- printf("Please input an at command:\n");
- if(NULL != fgets(atstr,15 - 1,stdin))
- {
- if(0 == strcmp(CMD_ADD,atstr))
- {
- if(demo==1)
- {sc_rtc_timer_add_demo(srcid,timer_sec,sc_rtc_timer_id_exp_cb_demo1);}
- else
- {sc_rtc_timer_add_demo(srcid,timer_sec,sc_rtc_timer_id_exp_cb_demo0);}
- }
- else if(0 == strcmp(CMD_GET,atstr))
- {
- if(demo==1)
- {sc_rtc_get_time_demo(srcid,rtc_get_time_cb_demo1);}
- else
- {sc_rtc_get_time_demo(srcid,rtc_get_time_cb_demo0);}
- }
- else if(0 == strcmp(CMD_SET,atstr))
- {
- sc_rtc_set_time_demo(srcid);
- }
- else if(0 == strcmp(CMD_ADD_UTC,atstr))
- {
- struct tm sec = {0};
- sec.tm_year = year-1900;
- sec.tm_mon = mouth-1;
- sec.tm_mday = date;
- sec.tm_hour = hour;
- sec.tm_min = minute;
- sec.tm_sec = seconds;
- if(demo==1)
- {sc_rtc_timer_add_utc_demo(&sec,srcid,wakeup,sc_rtc_timer_id_exp_cb_demo1);}
- else
- {sc_rtc_timer_add_utc_demo(&sec,srcid,wakeup,sc_rtc_timer_id_exp_cb_demo0);}
- }
- else if(0 == strcmp(CMD_HELP,atstr))
- {
- printUsage(atstr);
- }
- else if(0 == strcmp(CMD_Q,atstr))
- {
- break;
- }
- }
- }
-
- rtc_timer_deinit( );
- printf("sc_rtc_timer_demo:Demo over.\n");
- return 0;
+ if ((srcid = rtc_timer_init( )) <= 0)
+ {
+ printf("rtc_timer_demo:rtc_timer_init fail!\n");
+ return 0;
+ }
+ printf("srcid:0x%x\n", srcid);
+ while (1)
+ {
+ memset(atstr, 0, sizeof(atstr));
+ printf("Please input an at command:\n");
+ if (NULL != fgets(atstr, 15 - 1, stdin))
+ {
+ if (0 == strcmp(CMD_ADD, atstr))
+ {
+ if (demo == 1)
+ {
+ sc_rtc_timer_add_demo(srcid, 1, timer_sec, sc_rtc_timer_id_exp_cb_demo1);
+ }
+ else
+ {
+ sc_rtc_timer_add_demo(srcid, 0, timer_sec, sc_rtc_timer_id_exp_cb_demo0);
+ }
+ }
+ else if (0 == strcmp(CMD_GET, atstr))
+ {
+ if (demo == 1)
+ {
+ sc_rtc_get_time_demo(srcid, rtc_get_time_cb_demo1);
+ }
+ else
+ {
+ sc_rtc_get_time_demo(srcid, rtc_get_time_cb_demo0);
+ }
+ }
+ else if (0 == strcmp(CMD_SET, atstr))
+ {
+ sc_rtc_set_time_demo(srcid);
+ }
+ else if (0 == strcmp(CMD_ADD_UTC, atstr))
+ {
+ struct tm sec = {0};
+ sec.tm_year = year - 1900;
+ sec.tm_mon = mouth - 1;
+ sec.tm_mday = date;
+ sec.tm_hour = hour;
+ sec.tm_min = minute;
+ sec.tm_sec = seconds;
+ if (demo == 1)
+ {
+ sc_rtc_timer_add_utc_demo(&sec, srcid, 2, wakeup, sc_rtc_timer_id_exp_cb_demo1);
+ }
+ else
+ {
+ sc_rtc_timer_add_utc_demo(&sec, srcid, 3, wakeup, sc_rtc_timer_id_exp_cb_demo0);
+ }
+ }
+ else if (0 == strcmp(CMD_DEL, atstr))
+ {
+ sc_rtc_timer_del_demo(srcid, 0);
+ }
+ else if (0 == strcmp(CMD_HELP, atstr))
+ {
+ printUsage(atstr);
+ }
+ else if (0 == strcmp(CMD_Q, atstr))
+ {
+ break;
+ }
+ }
+ }
+
+ rtc_timer_deinit( );
+ printf("sc_rtc_timer_demo:Demo over.\n");
+ return 0;
}
diff --git a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/spitest/test_spidev.c b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/spitest/test_spidev.c
index b281d1d..3a507ea 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/spitest/test_spidev.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/zxic_app_open/test/spitest/test_spidev.c
@@ -6,13 +6,13 @@
#include <sys/types.h>
#include <linux/spi/spidev.h>
-#define SPI_DEV_0 "/dev/spidev1.0"
-#define SPI_DEV_1 "/dev/spidev1.0"
+#define SPI_DEV_0 "dev/spidev1.0"
+#define SPI_DEV_1 "dev/spidev2.0"
#define PACK_HEAD 0xA5
#define PACK_TAIL 0x7e
#define CHECK_PAY_LOAD 3
-int spi_dev_fd[2] = {-1};
+int spi_dev_fd[4] = {-1};
static struct info
{
@@ -300,11 +300,8 @@
return ret;
}
- if(num == 0) {
- spi_dev_fd[num] = sc_spi_open(path,0, 8,speed, O_RDWR);
- } else {
- spi_dev_fd[num] = open(path,O_RDWR);
- }
+ spi_dev_fd[num] = sc_spi_open(path,0, 8,speed, O_RDWR);
+
if(spi_dev_fd[num] < 0) {
printf("%s open failed \r\n",path);
@@ -314,9 +311,124 @@
return ret;
}
+
+static int spi_trans( int fp, unsigned char *buf, int len)
+
+{
+ int frame_sum = len/768;
+ struct spi_ioc_transfer tr[768]={0};
+ int i = 0;
+
+ if(len % 768) {
+ frame_sum++;
+ }
+
+ if(frame_sum > 16) {
+ frame_sum = 16;
+ }
+
+ for(;i<frame_sum;++i) {
+ tr[i].tx_buf=(unsigned long)&buf[i*768];
+ tr[i].rx_buf=(unsigned long)&buf[i*768];
+ tr[i].len=((i+1)*768)<=len?768:(len%768);
+ tr[i].delay_usecs = 1;
+ tr[i].speed_hz=4800000;
+ tr[i].cs_change=0;
+ }
+
+ return ioctl(fp,SPI_IOC_MESSAGE(frame_sum),&tr);
+}
+
+
+static void ioctl_test(char *path,int num,int count,int speed)
+{
+
+ int mode = 3; //CPOL=0, CPHA=1
+ int times = count;
+ int ret;
+ char buffer[1024] = {0};
+ if(num > 2 && num < 0) {
+ printf("parm err %d \r\n",num);
+ return;
+ }
+
+ spi_dev_fd[num] = open(path,O_RDWR);
+ if(spi_dev_fd[num] < 0) {
+ printf("%s open failed \r\n",path);
+ return;
+ }
+ printf("%s open fd:%d \r\n",path,spi_dev_fd[num]);
+
+ //ÉèÖÃģʽ
+ ret = ioctl( spi_dev_fd[num], SPI_IOC_WR_MODE, &mode );
+ printf("spidev: set WR mode(%d) ret :%d\n", mode, ret);
+ mode = 0;
+ ret = ioctl( spi_dev_fd[num], SPI_IOC_RD_MODE, &mode );
+ printf("spidev: get RD mode(%d) ret :%d\n", mode, ret);
+
+ //ÉèÖÃƵÂÊ
+ speed = 4800000; //4.8MHz
+ ret = ioctl( spi_dev_fd[num], SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+ printf("spidev: set max speed %d Hz, ret:%d\n", speed, ret);
+ speed = 0 ;
+ ret = ioctl( spi_dev_fd[num], SPI_IOC_RD_MAX_SPEED_HZ, &speed);
+ printf("spidev: get max speed(%d) ret :%d\n", speed, ret);
+
+
+ srand(time(0));
+ for(int i = 0; i<1024; i++)
+ buffer[i] = rand()&0xFF;
+
+ while(times > 0) {
+ ret = spi_trans(spi_dev_fd[num], buffer, 768);
+ printf("spidev: times %d spi_trans len %d !\n",times,ret);
+ times--;
+ }
+ close(spi_dev_fd[num]);
+ spi_dev_fd[num]= -1;
+}
+
+static void ioctl_set_parm_test(char *path,int num,int mode,int speed)
+{
+
+ //int mode = 1; //CPOL=0, CPHA=1
+ int ret;
+ char buffer[1024] = {0};
+ if(num > 2 && num < 0) {
+ printf("parm err %d \r\n",num);
+ return;
+ }
+
+ spi_dev_fd[num] = open(path,O_RDWR);
+ if(spi_dev_fd[num] < 0) {
+ printf("%s open failed \r\n",path);
+ return;
+ }
+ printf("%s open fd:%d \r\n",path,spi_dev_fd[num]);
+
+ //ÉèÖÃģʽ
+ ret = ioctl( spi_dev_fd[num], SPI_IOC_WR_MODE, &mode );
+ printf("spidev: set WR mode(%d) ret :%d\n", mode, ret);
+ mode = 0;
+ ret = ioctl( spi_dev_fd[num], SPI_IOC_RD_MODE, &mode );
+ printf("spidev: get RD mode(%d) ret :%d\n", mode, ret);
+
+ //ÉèÖÃƵÂÊ
+ speed = 4800000; //4.8MHz
+ ret = ioctl( spi_dev_fd[num], SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+ printf("spidev: set max speed %d Hz, ret:%d\n", speed, ret);
+ speed = 0 ;
+ ret = ioctl( spi_dev_fd[num], SPI_IOC_RD_MAX_SPEED_HZ, &speed);
+ printf("spidev: get max speed(%d) ret :%d\n", speed, ret);
+
+ close(spi_dev_fd[num]);
+ spi_dev_fd[num]= -1;
+}
+
+
/*
cmd:
- argv[1] = "0"|"1" master||
+ argv[1] = "dev_id" /dev/spidev%d.0
argv[2] = "send"|"recv" direction
argv[3] = "0"~"4096-3" len buf[0],buf[1],buf[len-1] used for check
argv[4] = "0"~"40M" speed /slave no need/
@@ -324,6 +436,7 @@
int main(int argc,char *argv[])
{
int i,dev_id,len,speed,ret = 0;
+ char name[32] = {0};
for(i = 0;i<argc;i++) {
printf("%s \n",argv[i]);
@@ -332,25 +445,40 @@
dev_id = atoi(argv[1]);
len = atoi(argv[3]);
speed = atoi(argv[4]);
-
- if(dev_id == 0)
- ret = spi_dev_open(SPI_DEV_0,dev_id,speed);
- else
- ret = spi_dev_open(SPI_DEV_1,dev_id,speed);
- if(ret < 0) {
- printf("%d return \n",__LINE__);
- return ret;
- }
+
+ sprintf(name,"/dev/spidev%d.0",dev_id);
+ printf("dev name: %s \n",name);
if(!strcmp("send",argv[2])) {
+ ret = spi_dev_open(name,dev_id,speed);
+ if(ret < 0) {
+ printf("%d return \n",__LINE__);
+ return ret;
+ }
ret = send_thread_init(dev_id,len);
}else if(!strcmp("recv",argv[2])) {
+ ret = spi_dev_open(name,dev_id,speed);
+ if(ret < 0) {
+ printf("%d return \n",__LINE__);
+ return ret;
+ }
ret = recv_thread_init(dev_id,len);
}else if(!strcmp("send_recv",argv[2])) {
+ ret = spi_dev_open(name,dev_id,speed);
+ if(ret < 0) {
+ printf("%d return \n",__LINE__);
+ return ret;
+ }
ret = send_recv_thread_init(dev_id,len);
+ }else if(!strcmp("ioctl_test",argv[2])) {
+ int times = len;
+ ioctl_test(name,dev_id,times,speed);
+ }else if(!strcmp("set_parm",argv[2])) {
+ int mode = len;
+ ioctl_set_parm_test(name,dev_id,mode,speed);
}else {
printf("cmd invalid \n",argv[2]);
ret = -1;
}
-
+
return 0;
}
diff --git a/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.bin b/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.bin
index f7609a6..c9113dd 100755
--- a/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.bin
+++ b/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.bin
Binary files differ
diff --git a/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.map b/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.map
index e634332..809e146 100755
--- a/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.map
+++ b/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.map
@@ -771,32 +771,24 @@
T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o) (_zDrvEfuse_IsSpe)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(32.o)
T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (___modhi3)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(adddf3_v2.o)
- T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o) (___adddf3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Add.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___addsf3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(compare_IEEE.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___lthf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(convert.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___floatunshihf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(convertqi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___floatqihf2)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(div.o)
T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rtx.o) (___divqi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Div.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___divsf3)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(divzi3_v2.o)
T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (___divzi3_v2)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_Add.o)
- T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___addsf3)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_compare_IEEE.o)
- T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___lthf2)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_convert.o)
- T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___floatunshihf2)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_convertqi.o)
- T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___floatqihf2)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_Div.o)
- T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___divsf3)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_errno.o)
- C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_Add.o) (_ierrno)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_ftou.o)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(errno.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Add.o) (_ierrno)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ftou.o)
T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___ieee754_ftou)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_Mul.o)
- T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___mulsf3)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_pnan.o)
- C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_Add.o) (___ieee754_propagate_nan)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_Sub.o)
- T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___subsf3)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcmp.o)
T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o) (_memcmp)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcpy16.o)
@@ -809,6 +801,10 @@
T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_afc.o) (___modqi3)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(modzi3_v2.o)
T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o) (___modzi3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Mul.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___mulsf3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(pnan.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Add.o) (___ieee754_propagate_nan)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(sprintf.o)
T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o) (_sprintf)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strchr.o)
@@ -819,8 +815,8 @@
T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o) (_strcpy)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strlen.o)
T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o) (_strlen)
-C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(subdf3_v2.o)
- T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_(short, bool __restrict, double, float, _v2))
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Sub.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___subsf3)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(udiv.o)
T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rtx_rx.o) (___udivqi3)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(udivzi3_v2.o)
@@ -831,6 +827,8 @@
T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (___umodzi3_v2)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(vsprintf.o)
T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_uart.o) (_vsprintf)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___adddf3_v2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o) (___adddf3_v2)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___fixsfhi.o)
T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (___fixsfhi)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___floatsisf.o)
@@ -843,8 +841,10 @@
T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o) (___gtsf2)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o)
T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (___muldf3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_packFloat64.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_packFloat64)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_addFloat64Sigs.o)
- C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(adddf3_v2.o) (_staticFunc_addFloat64Sigs)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___adddf3_v2.o) (_staticFunc_addFloat64Sigs)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_normalizeFloat64Subnormal.o)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_staticFunc_normalizeFloat64Subnormal)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_normalizeRoundAndPackFloat64.o)
@@ -854,7 +854,9 @@
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_roundAndPackFloat64.o)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_staticFunc_roundAndPackFloat64)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_subFloat64Sigs.o)
- C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(adddf3_v2.o) (_staticFunc_subFloat64Sigs)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___adddf3_v2.o) (_staticFunc_subFloat64Sigs)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___subdf3_v2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_(short, bool __restrict, double, float, _v2))
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(sprintf.o) (__vfsprintf_sdsp)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(lshrli3.o)
@@ -862,9 +864,13 @@
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(lshrzi3.o)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(lshrli3.o) (___lshrzi3)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(mul64To128.o)
- C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_mul64To128_v2)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_mul64To128)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(shift64RightJamming.o)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_addFloat64Sigs.o) (_shift64RightJamming_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_data.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_roundAndPackFloat64.o) (_float_rounding_mode)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_extractFloat64Exp.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___fixsfhi.o) (_extractFloat64Exp)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_float64_is_nan.o)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_propagateFloat64NaN.o) (_float64_is_nan)
C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_float64_is_signaling_nan.o)
@@ -1081,7 +1087,7 @@
0x4e4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
_g_sdRLMATQOut 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
_g_L1LteAIsrTaskPid
- 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
_g_dwPucchPrintCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
_g_s_tMeasGapResReq
0x3b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_gap.o)
@@ -1239,6 +1245,8 @@
_g_L1l_LpmCaliCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
_g_tRarCtrlDB 0x14 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
_g_dwNextX 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_zPHY_ecsrc_tEarfcnTable_B28
+ 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
_g_asdwL1eRxCrsRsrp
0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
_g_awSpecPrachNum 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
@@ -2422,7 +2430,7 @@
LOAD C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a
0x10000000 . = 0x10000000
-.text 0x10000000 0xd49e6
+.text 0x10000000 0xd491d
0x10000000 _stext = .
*(.ddr_vectors)
.ddr_vectors 0x10000000 0x8 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
@@ -2855,9517 +2863,9521 @@
0x1000608b 0x21 _L1_DrvL1CacheFlushI
0x100060ac 0x2d _L1_DrvL1CacheFlush
0x100060d9 0x1b _L1_DrvL1CacheSetWT
- .text 0x100060f4 0x3d C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_disableall.o)
- 0x100060f4 0x3d _ZSP_ICacheDisableAllWays
- .text 0x10006131 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enable.o)
- 0x10006131 0x17 _ZSP_ICacheEnable
- .text 0x10006148 0x3c C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enableall.o)
- 0x10006148 0x3c _ZSP_ICacheEnableAllWays
- .text 0x10006184 0x56 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_flush.o)
- 0x10006184 0x56 _ZSP_ICacheFlush
- .text 0x100061da 0x4d C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_loadtcm.o)
- 0x100061da 0x4d _ZSP_ICacheLoadNCSRAM
- .text 0x10006227 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_use_dcfgr_describe.o)
- 0x10006227 0x15 _ZSP_ICacheUseICFGRDescribe
- .text 0x1000623c 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_noncacheable_disable.o)
- 0x1000623c 0x12 _ZSP_ICacheNonCacheableDisable
- .text 0x1000624e 0x3d C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_disableall.o)
- 0x1000624e 0x3d _ZSP_DCacheDisableAllWays
- .text 0x1000628b 0x3c C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_enableall.o)
- 0x1000628b 0x3c _ZSP_DCacheEnableAllWays
- .text 0x100062c7 0x56 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_flush.o)
- 0x100062c7 0x56 _ZSP_DCacheFlush
- .text 0x1000631d 0x24 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_loadtcm.o)
- 0x1000631d 0x24 _ZSP_DCacheLoadNCSRAM
- .text 0x10006341 0x56 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_clean.o)
- 0x10006341 0x56 _ZSP_DCacheClean
- .text 0x10006397 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_setwritethruregion.o)
- 0x10006397 0x15 _ZSP_DCacheSetWriteThruRegion
- .text 0x100063ac 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writeallocate_enable.o)
- 0x100063ac 0x12 _ZSP_DCacheWriteAllocateEnable
- .text 0x100063be 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_enable.o)
- 0x100063be 0x12 _ZSP_DCacheWriteThruEnable
- .text 0x100063d0 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_disable.o)
- 0x100063d0 0x12 _ZSP_DCacheWriteThruDisable
- .text 0x100063e2 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_noncacheable_enable.o)
- 0x100063e2 0x12 _ZSP_DCacheNonCacheableEnable
- .text 0x100063f4 0x13 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_extranoncacheable_enable.o)
- 0x100063f4 0x13 _ZSP_DCacheExtraNonCacheableEnable
- .text 0x10006407 0x175 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1td_init.o)
- 0x10006407 0x54 _L1td_TaskPrioEng
- 0x1000645b 0xd _HW_Init
- 0x10006468 0x114 _TD_L1_Init
- .text 0x1000657c 0xcc T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_nv_param.o)
- 0x1000657c 0x4c _L1_AtNvInit
- 0x100065c8 0x80 _HW_InitZspReadNvPara
- .text 0x10006648 0x1e T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hspadldec.o)
- 0x10006648 0x1e _L1_HspaDlDecTask
- .text 0x10006666 0x1097 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rfc.o)
- 0x10006666 0x1 _L1_DevRfcMulModeTopRegCfg
- 0x10006667 0x1 _L1_DevRfcTopRegCfg
- 0x10006668 0x3 _L1_DevRfcMaxTadvToPc
- 0x1000666b 0x3 _L1_DevRfcCsGetMaxAgcNum
- 0x1000666e 0x3 _L1_DevRfcGapGetRdbOpenOffset
- 0x10006671 0x26 _L1_DevRfcIntInd
- 0x10006697 0x3a _L1_DevRfcIsBandSupported
- 0x100066d1 0xf _L1_DevRfcPowerOverFlow
- 0x100066e0 0x33 _L1_DevRfcPaModeSelect
- 0x10006713 0x7 _L1_DevRfcPcSetTadv
- 0x1000671a 0x7 _L1_DevRfcGetTadv
- 0x10006721 0x60 _L1_DevRfcPcSetPwr
- 0x10006781 0x2e _L1_DevRfcSetTxBandMaxPwr
- 0x100067af 0x7 _L1_DevRfcUpSlotCfg
- 0x100067b6 0x1c _L1_DevRfcHsdpaConfig
- 0x100067d2 0xe _L1_DevRfcGetUnsyncSlotEstPwr
- 0x100067e0 0x3 _L1_DevRfcGetAgcRefPwr
- 0x100067e3 0x7 _L1_DevRfcGetRfSleepState
- 0x100067ea 0x59 _L1_DevRfcReset
- 0x10006843 0x19 _L1_DevRfcInit
- 0x1000685c 0x43 _L1_DevRfcWaitUntilMsgCome
- 0x1000689f 0x4f _L1_DevRfcWaitUntilRfIntCome
- 0x100068ee 0xa1 _L1_DevRfcRdbCalUnSyncAgc
- 0x1000698f 0x14 _L1_DevRfcTs0FreqDif
- 0x100069a3 0x32 _L1_DevRfcGetNvHarmonicIndex
- 0x100069d5 0x6f _L1_DevRfcNotchHandle
- 0x10006a44 0xa3 _L1_DevRfcIntSlotCtrl
- 0x10006ae7 0x63 _L1_DevRfcSetFpachFlag
- 0x10006b4a 0xa8 _L1_DevRfcSlotAdd
- 0x10006bf2 0x3c _L1_DevRfcUnsyncRamEnSet
- 0x10006c2e 0xa _L1_DevRfcSetLogRegData
- 0x10006c38 0x8 _L1_DevRfcTempDacToIram
- 0x10006c40 0x4c _L1_DevRfcGetRegData
- 0x10006c8c 0x64 _L1_DevRfcRegReadBack
- 0x10006cf0 0x3c _L1_DevRfcReadTmp
- 0x10006d2c 0x7 _L1_DevRfcGetRfState
- 0x10006d33 0x26 _L1_DevRfcResetCnf
- 0x10006d59 0x26 _L1_DevRfcInitCnf
- 0x10006d7f 0x1b _L1_DevRfcWAkeUpStateMove
- 0x10006d9a 0x15 _L1_DevRfcWorkSlotStateCheck
- 0x10006daf 0xd8 _L1_DevRfcL1sOpenRfcMsgProc
- 0x10006e87 0x96 _L1_DevRfcRdbOpenCfg
- 0x10006f1d 0x5 _L1_DevRfcRfCloseRx
- 0x10006f22 0x57 _L1_DevRfcRdbCloseProc
- 0x10006f79 0x8e _L1_DevRfcRdbStateMsgProc
- 0x10007007 0x4d _L1_DevRfcSleepProc
- 0x10007054 0x7e _L1_DevRfcIntSyncAgcCalcCtrl
- 0x100070d2 0x40 _L1_DevRfcTs0EventAdj
- 0x10007112 0x51 _L1_DevRfcWakeUpProc
- 0x10007163 0x1c _L1_DevRfcDeltaPowerDb
- 0x1000717f 0xdf _L1_DevRfcHalfIntProc
- 0x1000725e 0x12e _L1_DevRfcFullIntProc
- 0x1000738c 0x24 _L1_DevRestoreReq
- 0x100073b0 0x3b _L1_DevRfcReusedReSourceRestore
- 0x100073eb 0x312 _L1_RfcTask
- .text 0x100076fd 0x2f7 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hspa.o)
- 0x100076fd 0x37 _L1_DevHspaReset
- 0x10007734 0x3d _L1_DevHspaInit
- 0x10007771 0x3a _L1_DevHsupaTpuSlotIntProc
- 0x100077ab 0x44 _L1_DevHspaHdtrIntProc
- 0x100077ef 0x21 _L1_DevHspaCmnMsgProc
- 0x10007810 0xcc _L1_DevHsupaMsgProc
- 0x100078dc 0x62 _L1_DevHsdpaMsgProc
- 0x1000793e 0x71 _L1_DevHspaPlusMsgProc
- 0x100079af 0x45 _L1_HspaTask
- .text 0x100079f4 0x3f00 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rtx_rx.o)
- 0x100079f4 0xf _L1_DevRtxRxReset
- 0x10007a03 0xf _L1_DevRtxRxInit
- 0x10007a12 0xe0 _L1_DevRtxRxRecMsgProc
- 0x10007af2 0x73 _L1_DevRtxRxRevBchCfgReq
- 0x10007b65 0x51 _L1_DevRtxRxRevPichCfgReq
- 0x10007bb6 0x37 _L1_DevRtxRxRevPchCfgReq
- 0x10007bed 0x57 _L1_DevRtxRxRevFpachCfgReq
- 0x10007c44 0x37 _L1_DevRtxRxRevFachCfgReq
- 0x10007c7b 0x24 _L1_DevRtxRxRevFachAbortReq
- 0x10007c9f 0x76 _L1_DevRtxRxRevDpchCfgReq
- 0x10007d15 0x53 _L1_DevRtxRxRevHsscchCfgReq
- 0x10007d68 0x53 _L1_DevRtxRxRevEagchCfgReq
- 0x10007dbb 0x76 _L1_DevRtxRxRevEhichCfgReq
- 0x10007e31 0x3f _L1_DevRtxRxRevHsdschCfgReq
- 0x10007e70 0x24 _L1_DevRtxRxSaveBchCfgPara
- 0x10007e94 0x27 _L1_DevRtxRxSavePichCfgPara
- 0x10007ebb 0x6e _L1_DevRtxRxSavePchCfgPara
- 0x10007f29 0x36 _L1_DevRtxRxSaveFpachCfgPara
- 0x10007f5f 0x6e _L1_DevRtxRxSaveFachCfgPara
- 0x10007fcd 0xc4 _L1_DevRtxRxSaveDpchCfgPara
- 0x10008091 0x26 _L1_DevRtxRxSaveHsscchCfgPara
- 0x100080b7 0x22 _L1_DevRtxRxSaveEagchCfgPara
- 0x100080d9 0x43 _L1_DevRtxRxSaveHsdschCfgPara
- 0x1000811c 0x3c _L1_DevRtxRxSaveEhichCfgPara
- 0x10008158 0xc4 _L1_DevRtxHandleTs6TpuEvent
- 0x1000821c 0x92 _L1_DevRtxRxBchTs6Handle
- 0x100082ae 0x3d _L1_DevRtxRxPichTs6Handle
- 0x100082eb 0x6e _L1_DevRtxRxPchTs6Handle
- 0x10008359 0x2c _L1_DevRtxRxFpachTs6Handle
- 0x10008385 0x45 _L1_DevRtxRxDtrTurboCfg
- 0x100083ca 0x75 _L1_DevRtxRxFachTs6Handle
- 0x1000843f 0x112 _L1_DevRtxRxDpchTs6Handle
- 0x10008551 0x7d _L1_DevRtxRxHsscchTs6Handle
- 0x100085ce 0xc9 _L1_DevRtxRxHsdschTs6Handle
- 0x10008697 0x7e _L1_DevRtxRxEhichTs6Handle
- 0x10008715 0x71 _L1_DevRtxRxEagchTs6Handle
- 0x10008786 0x6b _L1_DevRtxRxHandleSleep
- 0x100087f1 0x11a _L1_DevRtxHandleTs1TpuEvent
- 0x1000890b 0x3c _L1_DevDtrBchCfg
- 0x10008947 0x37 _L1_DevRxBchCfg
- 0x1000897e 0x3a _L1_DevRxPichCfg
- 0x100089b8 0x40 _L1_DevDtrPchCfg
- 0x100089f8 0x40 _L1_DevDtrFachCfg
- 0x10008a38 0x3a _L1_DevRxPchCfg
- 0x10008a72 0x3a _L1_DevRxFachCfg
- 0x10008aac 0x2b _L1_DevDtrDchCfg
- 0x10008ad7 0x37 _L1_DevRxDchCfg
- 0x10008b0e 0x24 _L1_DevDtrHsccchCfg
- 0x10008b32 0x23 _L1_DevDtrEagchCfg
- 0x10008b55 0x110 _L1_DevRxHsscchCfg
- 0x10008c65 0xe9 _L1_DevRxEagchCfg
- 0x10008d4e 0x65 _L1_DevRxEhichCfg
- 0x10008db3 0x6d _L1_DevRxHsdschCfg
- 0x10008e20 0x58 _L1_DevRxHsdschRel
- 0x10008e78 0x3e _L1_DevRtxCalcRxHsscchPara
- 0x10008eb6 0x40 _L1_DevRtxCalcRxEagchPara
- 0x10008ef6 0x2e _L1_DevRtxCalcRxEhichPara
- 0x10008f24 0x4c _L1_DevRtxCalcRxDchPara
- 0x10008f70 0x36 _L1_DevFachPchConfigStep2
- 0x10008fa6 0x36 _L1_DevDchConfigStep2
- 0x10008fdc 0xe _L1_DevRtxRxSelectCodinMode
- 0x10008fea 0xf1 _L1_DevRtxCalcDtrFachPchS2Para
- 0x100090db 0x11b _L1_DevRtxCalcDtrDchS2Para
- 0x100091f6 0x41 _L1_DevRtxCalcRmPara
- 0x10009237 0x109 _L1_DevRtxUncodedCovRM
- 0x10009340 0x2 _L1_DevRtxCalcAbs
- 0x10009342 0x11 _L1_DevRtxCalcGcd
- 0x10009353 0x19f _L1_DevRtxTurboRM
- 0x100094f2 0x99 _L1_DevRtxCalcDeltaNi
- 0x1000958b 0xa3 _L1_DevRtxCalcFachPchNdata
- 0x1000962e 0xec _L1_DevRtxCalcDchNdata
- 0x1000971a 0xbb _L1_DevRtxCalcCodingPara
- 0x100097d5 0x10 _L1_DevRtxCalcExpTti
- 0x100097e5 0x5f _L1_DevRxPchRel
- 0x10009844 0x5f _L1_DevRxFachRel
- 0x100098a3 0x58 _L1_DevRxDchRel
- 0x100098fb 0x5c _L1_DevRxHsscchRel
- 0x10009957 0x78 _L1_DevRxHsupaRel
- 0x100099cf 0x1f _L1_DevRtxCalcDtrPchPara
- 0x100099ee 0x1f _L1_DevRtxCalcDtrFachPara
- 0x10009a0d 0x37 _L1_DevRtxCalcDtrDlDchS1Para
- 0x10009a44 0x38 _L1_DevRtxCalcRxPchPara
- 0x10009a7c 0x4d _L1_DevRtxCalcDtrHsscchPara
- 0x10009ac9 0x7a _L1_DevRtxCalcDtrEagchPara
- 0x10009b43 0x38 _L1_DevRtxCalcRxFachPara
- 0x10009b7b 0x46 _L1_RtxCalcSlotFormat
- 0x10009bc1 0x26 _L1_DevDtrFpachCfg
- 0x10009be7 0x3b _L1_DevRxFpachCfg
- 0x10009c22 0x1a _L1_DevRtxCalcDtrFpachPara
- 0x10009c3c 0x3d _L1_DevRtxCalcRxFpachPara
- 0x10009c79 0x18 _L1_DevRtxCalcDtrBchPara
- 0x10009c91 0x11 _L1_DevRtxCalcRxBchPara
- 0x10009ca2 0x11 _L1_DevRtxCalcBchEini
- 0x10009cb3 0x40 _L1_DevRtxCalcRxPichPara
- 0x10009cf3 0x42 _L1_DevRxBchRel
- 0x10009d35 0x5e _L1_DevRxPichRel
- 0x10009d93 0x5e _L1_DevRxFpachRel
- 0x10009df1 0x48 _L1_DevRtxIntraCellCfg
- 0x10009e39 0x34 _L1_DevRtxHandleRxInt
- 0x10009e6d 0xe1 _L1_DevRtxHandleFpachInt
- 0x10009f4e 0x153 _L1_DevRtxHandleMcheInt
- 0x1000a0a1 0x135 _L1_DevRtxHandleJdcoreInt
- 0x1000a1d6 0xd9 _L1_DevRtxHandlePichData
- 0x1000a2af 0x56 _L1_DevRtxCalcPi
- 0x1000a305 0x2c _L1_DevRtxHandleHwacdInt
- 0x1000a331 0xa1 _L1_DevRtxHandleEhichInt
- 0x1000a3d2 0x121 _L1_DevRtxHandleTfciInt
- 0x1000a4f3 0x3b _L1_DevRtxHandleTtiInt
- 0x1000a52e 0xc _L1_DevRtxCalcMinCode
- 0x1000a53a 0x25 _L1_DevRtxCalWinNo
- 0x1000a55f 0xae _L1_DevRtxCalcDstData
- 0x1000a60d 0x55 _L1_DevRtxSelectMcheData
- 0x1000a662 0x2a7 _L1_DevRtxCalcSir
- 0x1000a909 0x51 _L1_DevRtxCalcRscp
- 0x1000a95a 0x1c _L1_DevRtxCalcActiveCodeNum
- 0x1000a976 0x2d _L1_DevRtxCalcAcd
- 0x1000a9a3 0x3a _L1_DevRtxMcheShift
- 0x1000a9dd 0x3f _L1_DevRtxCalcWinPower
- 0x1000aa1c 0xd9 _L1_DevRtxCalcDataFoe
- 0x1000aaf5 0x15 _L1_DevRtxGetLowTwoCode
- 0x1000ab0a 0x64 _L1_DevRtxRxBchDataReport
- 0x1000ab6e 0x198 _L1_DevRtxHandleTrchOut
- 0x1000ad06 0x14 _L1_DevRtxRxCalcCrcOkTbNum
- 0x1000ad1a 0x7b _L1_DevRtxRxDlTrchDataReport
- 0x1000ad95 0x84 _L1_DevRtxCmpPchUeId
- 0x1000ae19 0x3c9 _L1_DevRtxHandleCctrchOut
- 0x1000b1e2 0x4a _L1_DevCalcHsdschPhyInfo
- 0x1000b22c 0x31 _L1_RtxCalcCommonWinNo
- 0x1000b25d 0xf _L1_RtxCalcCodeNum
- 0x1000b26c 0xe _L1_DevRtxCalcLastCode
- 0x1000b27a 0x10 _L1_RtxCalcMinRm
- 0x1000b28a 0x58 _L1_DevRxGetTpcSs
- 0x1000b2e2 0x1a _L1_DevRtxJudgeChannel
- 0x1000b2fc 0x43 _L1_DevRtxSetSirForMeas
- 0x1000b33f 0x58 _L1_DevRtxSetSirForDs
- 0x1000b397 0x12c _L1_DevRtxSetSirForPc
- 0x1000b4c3 0x21 _L1_RxRefreshDchPara
- 0x1000b4e4 0x34 _L1_DevRtxSirGet
- 0x1000b518 0xb8 _L1_DevRtxHsDschCfg
- 0x1000b5d0 0xd _L1_DevRxMoveCctrchPara
- 0x1000b5dd 0x45 _L1_DevRxSelectMaxSir
- 0x1000b622 0x2b _L1_DevRxGetCctrchCellInfo
- 0x1000b64d 0xbe _L1_DevRtxDchDtxChkNullFrm
- 0x1000b70b 0xdc _L1_DevRtxDchDtxChkSBFrm
- 0x1000b7e7 0x33 _L1_DevRtxDchDtxStateUpdate
- 0x1000b81a 0x73 _L1_DevRtxDchDtxCalcSBBit
- 0x1000b88d 0x18 _L1_DevRtxDchDtxSBBitErrCnt
- 0x1000b8a5 0x45 _L1_DevRtxDchDtxIsDtxNullFrm
- 0x1000b8ea 0xa _L1_DevRtxRxSfn2Ssfn
- .text 0x1000b8f4 0x11a8 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rtx.o)
- 0x1000b8f4 0xf _L1_DevRtxReset
- 0x1000b903 0xf _L1_DevRtxInit
- 0x1000b912 0x62 _L1_DevRtxBchConfigReq
- 0x1000b974 0x39 _L1_DevRtxPichConfigReq
- 0x1000b9ad 0x39 _L1_DevRtxPchConfigReq
- 0x1000b9e6 0x2b _L1_DevRtxUppchConfigReq
- 0x1000ba11 0x50 _L1_DevRtxFpachConfigReq
- 0x1000ba61 0x39 _L1_DevRtxFachConfigReq
- 0x1000ba9a 0x33 _L1_DevRtxUldchConfigReq
- 0x1000bacd 0x44 _L1_DevRtxDldchConfigReq
- 0x1000bb11 0x21 _L1_DevRtxUlResetReq
- 0x1000bb32 0x21 _L1_DevRtxDlResetReq
- 0x1000bb53 0x2a _L1_DevRtxBchInfoInd
- 0x1000bb7d 0x26 _L1_DevRtxPichInd
- 0x1000bba3 0x26 _L1_DevRtxFpachDetectInd
- 0x1000bbc9 0x21 _L1_DevRtxRachFinishInd
- 0x1000bbea 0x3b _L1_DevRtxUppchPcCfg
- 0x1000bc25 0x3a _L1_DevRtxFpachPcCnf
- 0x1000bc5f 0x3b _L1_DevRtxPrachPcCfg
- 0x1000bc9a 0x21 _L1_DevRtxRachAbort
- 0x1000bcbb 0x24 _L1_DevRtxFachAbort
- 0x1000bcdf 0x1e9 _L1_DevRtxHardIntInd
- 0x1000bec8 0x7c _L1_DevRtxEagchRcvReq
- 0x1000bf44 0x70 _L1_DevRtxHsscchRcvReq
- 0x1000bfb4 0x50 _L1_DevRtxHssichSendReq
- 0x1000c004 0x63 _L1_DevRtxEhichRcvReq
- 0x1000c067 0x63 _L1_DevRtxHsDschRcvReq
- 0x1000c0ca 0x29 _L1_DevRtxDchSyncStartReq
- 0x1000c0f3 0x21 _L1_DevRtxDchSyncStopReq
- 0x1000c114 0x21 _L1_DevRtxPcTxEnReq
- 0x1000c135 0x21 _L1_DevRtxPcTxDisEnReq
- 0x1000c156 0x45 _L1_DevRtxDsInit
- 0x1000c19b 0x54 _L1_DevRtxDsSaveSIR
- 0x1000c1ef 0x84 _L1_DevRtxDsSaveCRC
- 0x1000c273 0xa9 _L1_DevRtxDsStep1Handle
- 0x1000c31c 0x48 _L1_DevRtxDsStep2SbSirCalc
- 0x1000c364 0x37 _L1_DevRtxDsStep2SirCalc
- 0x1000c39b 0x57 _L1_DevRtxDsStep2TdmSirCalc
- 0x1000c3f2 0x29 _L1_DevRtxDsStep2CrcCalc
- 0x1000c41b 0x136 _L1_DevRtxDsStep2Handle
- 0x1000c551 0xaf _L1_DevRtxDsStartWorking
- 0x1000c600 0xa9 _L1_DevRtxDsHandle
- 0x1000c6a9 0xb7 _L1_DevRtxCmnRecMsgProc
- 0x1000c760 0x5b _L1_DevRtxRxPcchBitRead
- 0x1000c7bb 0x3e _L1_DevRtxRxImsiGsm
- 0x1000c7f9 0x2f _L1_DevRtxRxTmsiGsm
- 0x1000c828 0x2f _L1_DevRtxRxPTmsiGsm
- 0x1000c857 0xf _L1_DevRtxRxImsiDs41
- 0x1000c866 0xf _L1_DevRtxRxTmsiDs41
- 0x1000c875 0x3d _L1_DevRtxRxPagRecCnId
- 0x1000c8b2 0x44 _L1_DevRtxRxPagRecUtranId
- 0x1000c8f6 0x4e _L1_DevRtxRxPagRec2UtranSingUeId
- 0x1000c944 0x28 _L1_DevRtxRxPagRec2UtranGrpId
- 0x1000c96c 0x28 _L1_DevRtxRxPagingRecList
- 0x1000c994 0x28 _L1_DevRtxRxPagingRec2ListR5
- 0x1000c9bc 0x12 _L1_DevRtxRxPagingV590ExtIE
- 0x1000c9ce 0x10 _L1_DevRtxRxPagingV860ExtIE
- 0x1000c9de 0x47 _L1_DevRtxRxPagingType1
- 0x1000ca25 0x19 _L1_DevRtxRxPcchMsgType
- 0x1000ca3e 0x17 _L1_DevRtxRxDecodePcch
- 0x1000ca55 0x47 _L1_RtxTask
- .text 0x1000ca9c 0x2154 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hsdpa.o)
- 0x1000ca9c 0x2c _L1_DevHsdpaCalc2ndRmEini
- 0x1000cac8 0x33 _L1_DevHsdpaCalcCodeBlockPara
- 0x1000cafb 0x1e _L1_DevHsdpaCalc1stRmPara
- 0x1000cb19 0xfa _L1_DevHsdpaCalcRmPara
- 0x1000cc13 0xea _L1_DevHsdpaCalcHdtrPara
- 0x1000ccfd 0x4d _L1_DevHsdpaCalcCqiDelta
- 0x1000cd4a 0x7a _L1_DevHsdpaSetHarqInfo
- 0x1000cdc4 0x6a _L1_DevHsdpaSetHssichSendInf
- 0x1000ce2e 0x38 _L1_DevHsdpaSetHssichAckInf
- 0x1000ce66 0x3b _L1_DevHsdpaSetHssichCqiInf
- 0x1000cea1 0x30 _L1_DevHsdpaClrHssichSendInf
- 0x1000ced1 0x44 _L1_DevHsdpaGetHssichSendInf
- 0x1000cf15 0x70 _L1_DevHsdpaSearchHssichSendInf
- 0x1000cf85 0x23 _L1_DevHsdpaHssichSendInfReset
- 0x1000cfa8 0x22 _L1_DevHsdpaHssichSendInfInit
- 0x1000cfca 0x66 _L1_DevHsdpaReset
- 0x1000d030 0x27 _L1_DevHsdpaNvInit
- 0x1000d057 0x5a _L1_DevHsdpaParaInit
- 0x1000d0b1 0x37 _L1_DevHsdpaInit
- 0x1000d0e8 0x19 _L1_DevHsdpaSetHdtrCallback
- 0x1000d101 0xa _L1_DevHsdpaSetGdtrCallback
- 0x1000d10b 0x1f1 _L1_DevHsdpaConfigProc
- 0x1000d2fc 0x29 _L1_DevHsdpaReleaseProc
- 0x1000d325 0x22 _L1_DevHsdpaIntraCellIndProc
- 0x1000d347 0xf _L1_DevHsdpaHarqNewDataPrint
- 0x1000d356 0xe2 _L1_DevHsdpaGetHsdschResInfo
- 0x1000d438 0x1e _L1_DevHsdpaDelta2Change2One
- 0x1000d456 0x1c _L1_DevHsdpaDelta2Change2Two
- 0x1000d472 0xda _L1_DevHsdpaCalDelta2
- 0x1000d54c 0x8c _L1_DevHsdpaHsscchIndProc
- 0x1000d5d8 0x11 _L1_DevHsdpaDschDataCheck
- 0x1000d5e9 0x6c _L1_DevHsdpaHdtrTtiIntPrint
- 0x1000d655 0x160 _L1_DevHsdpaHdtrTtiIntProc
- 0x1000d7b5 0x43 _L1_DevHsdpaCalcCqiSnr
- 0x1000d7f8 0x2b _L1_DevHsdpaCalcCqiRefPoint
- 0x1000d823 0xe _L1_DevHsdpaCalCqiTbs
- 0x1000d831 0x17 _L1_DevHsdpaCalCqiRtbs
- 0x1000d848 0x2 _L1_DevHsdpaFixRmf
- 0x1000d84a 0x136 _L1_DevHsdpaHdtrCqiIntProc
- 0x1000d980 0x28 _L1_DevHsdpaCfgHdtr
- 0x1000d9a8 0x65 _L1_DevHsdpaCfgHdtrTpuIntProc
- 0x1000da0d 0xd _L1_DevHsdpaDmaIntProc
- 0x1000da1a 0x33 _L1_DevHsdpaConfigReq
- 0x1000da4d 0x21 _L1_DevHsdpaRelReq
- 0x1000da6e 0x2d _L1_DevHsdpaHsscchInd
- 0x1000da9b 0x26 _L1_DevHsdpaHdtrIntInd
- 0x1000dac1 0x45 _L1_DevHsdpaIntraCellInd
- 0x1000db06 0x30 _L1_DevHsdpaScchTypeAnalyze
- 0x1000db36 0x19 _L1_DevHsdpaScchMissRecord
- 0x1000db4f 0xcc _L1_DevHsdpaScchType1Filter
- 0x1000dc1b 0x11f _L1_DevHsdpaScchType1Proc
- 0x1000dd3a 0xec _L1_DevHsdpaDschRecCfg
- 0x1000de26 0x27 _L1_DevHsdpaHsdschRcvReq
- 0x1000de4d 0x33 _L1_DevHsdpaPchConfigReq
- 0x1000de80 0x21 _L1_DevHsdpaPchRelReq
- 0x1000dea1 0x33 _L1_DevHsdpaFachConfigReq
- 0x1000ded4 0x21 _L1_DevHsdpaFachRelReq
- 0x1000def5 0x21 _L1_DevHsdpaFachCellReselReq
- 0x1000df16 0x29 _L1_DevHsdpaFachHrntiUpdateInd
- 0x1000df3f 0x21 _L1_DevHsdpaUlSyncOrderReq
- 0x1000df60 0x27 _L1_DevHsdpaSpsPatternInd
- 0x1000df87 0x21 _L1_DevHsdpaSpsRelOrderReq
- 0x1000dfa8 0x21 _L1_DevHsdpaDrxActOrderReq
- 0x1000dfc9 0x21 _L1_DevHsdpaDrxDeactOrderReq
- 0x1000dfea 0x21 _L1_DevHsdpaPchDschRcvInd
- 0x1000e00b 0x26 _L1_DevHsdpaTs0ReschedInd
- 0x1000e031 0x21 _L1_DevHsdpaFachScchDrxActiveInd
- 0x1000e052 0x21 _L1_DevHsdpaShareChInSyncInd
- 0x1000e073 0x21 _L1_DevHsdpaShareChOutSyncInd
- 0x1000e094 0x11 _L1_DevHsdpaSearchNextHssich
- 0x1000e0a5 0xd7 _L1_DevHsdpaPchConfigProc
- 0x1000e17c 0x14 _L1_DevHsdpaPchRelProc
- 0x1000e190 0xab _L1_DevHsdpaFachConfigProc
- 0x1000e23b 0x14 _L1_DevHsdpaFachRelProc
- 0x1000e24f 0xcc _L1_DevHsdpaDschRcvReqProc
- 0x1000e31b 0x2a _L1_DevHsdpaHsdschResInd
- 0x1000e345 0x3f _L1_DevHsdpaDschResIndProc
- 0x1000e384 0x19 _L1_DevHsdpaCellReSelProc
- 0x1000e39d 0x35 _L1_DevHsdpaFachHrntiUpd
- 0x1000e3d2 0x4d _L1_DevHsdpaPchGetDschResInfo
- 0x1000e41f 0x5e _L1_DevHsdpaSpsGetDschResInfo
- 0x1000e47d 0x69 _L1_DevHsdpaScch3GetDschResInfo
- 0x1000e4e6 0x7e _L1_DevHsdpaScchOrderProc
- 0x1000e564 0x52 _L1_DevHsdpaScchType2Filter
- 0x1000e5b6 0x91 _L1_DevHsdpaScchType2Proc
- 0x1000e647 0x48 _L1_DevHsdpaScchType3Filter
- 0x1000e68f 0xd7 _L1_DevHsdpaScchType3Proc
- 0x1000e766 0x24 _L1_DevHsdpaPchScchTypeAnalyze
- 0x1000e78a 0x31 _L1_DevHsdpaFachScchTypeAnalyze
- 0x1000e7bb 0x51 _L1_DevHsdpaDchScchTypeAnalyze
- 0x1000e80c 0x2d _L1_DevHsdpaResCheck
- 0x1000e839 0x1d _L1_DevHsdpaGetTs0ResState
- 0x1000e856 0x17 _L1_DevHsdpaClrResState
- 0x1000e86d 0x4f _L1_DevHsdpaScchType2SaveSpsInfo
- 0x1000e8bc 0xbb _L1_DevHsdpaSetHarqInfoWithSps
- 0x1000e977 0x1a _L1_DevHsdpaIsNeedSendSich
- 0x1000e991 0x4 _L1_DevHsdpaDschUsedTs0
- 0x1000e995 0x55 _L1_DevHsdpaSpsSearchHarqId
- 0x1000e9ea 0xe _L1_DevHsdpaCcsAnalyse
- 0x1000e9f8 0x24 _L1_DevHsdpaModSub
- 0x1000ea1c 0x1d _L1_DevHsdpaHarqHistoryInfoUpd
- 0x1000ea39 0x2c _L1_DevHsdpaCalcModuleType
- 0x1000ea65 0x2e _L1_DevHsdpaTs0ReschedProc
- 0x1000ea93 0x40 _L1_DevHsdpaSyncParaCfg
- 0x1000ead3 0x43 _L1_DevHsdpaInSyncCheck
- 0x1000eb16 0x3e _L1_DevHsdpaOutSyncCheck
- 0x1000eb54 0x9c _L1_DevHsdpaEverySubfrmProc
- .text 0x1000ebf0 0x3ce T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls.o)
- 0x1000ebf0 0x26 _L1_DevDlsSendnitMsg
- 0x1000ec16 0x24 _L1_DevDlsSendCnf
- 0x1000ec3a 0x21 _L1_DevDlsReset
- 0x1000ec5b 0x15 _L1_DevDlsInit
- 0x1000ec70 0x15 _L1_DevDlsCsrReset
- 0x1000ec85 0x23 _L1_DevDlsCsrInt
- 0x1000eca8 0xa5 _L1_DevDlsTpuInt
- 0x1000ed4d 0x80 _L1_DevDlsTimingSetReqHandle
- 0x1000edcd 0x1f1 _L1_DlsTask
- .text 0x1000efbe 0x986 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_hsupa.o)
- 0x1000efbe 0x36 _L1_DevPcHsupaStart
- 0x1000eff4 0xb _L1_DevPcHsupaStop
- 0x1000efff 0x17 _L1_DevPcHsupaResetDb
- 0x1000f016 0x50 _L1_DevPcEagchOuterCfg
- 0x1000f066 0x16 _L1_DevPcNonSchEpuchTpcCfg
- 0x1000f07c 0x52 _L1_DevPcEagchInnerCfg
- 0x1000f0ce 0xb5 _L1_DevPcEpuchCfg
- 0x1000f183 0x4c _L1_DevPcHsupaCloseLoopPro
- 0x1000f1cf 0x31 _L1_DevPcHsupaGetRxInfo
- 0x1000f200 0x65 _L1_DevPcGetEagchFromDb
- 0x1000f265 0x5a _L1_DevPcHsupaGetEagch
- 0x1000f2bf 0x6c _L1_DevPcHsupaGetEhich
- 0x1000f32b 0x5e _L1_DevPcEagchOuterPro
- 0x1000f389 0x44 _L1_DevPcEagchInnerPro
- 0x1000f3cd 0x84 _L1_DevPcEpuchTpcSsMerge
- 0x1000f451 0xc3 _L1_DevPcEpuchCloseLoopPro
- 0x1000f514 0x1ea _L1_DevPcEpuchPro
- 0x1000f6fe 0x91 _L1_DevPcErucchPro
- 0x1000f78f 0x74 _L1_DevPcErucchPwr
- 0x1000f803 0xf _L1_DevPcEhichTpcSsCmdToBit
- 0x1000f812 0x15 _L1_DevPcGetRefBetaE
- 0x1000f827 0x2b _L1_DevPcCalcUph
- 0x1000f852 0x30 _L1_DevPcSaveUph
- 0x1000f882 0x50 _L1_DevPcSetUph
- 0x1000f8d2 0x36 _L1_DevPcLinearAverage
- 0x1000f908 0x2b _L1_DevPcGetSpreadingGain
- 0x1000f933 0x11 _L1_DevPcSetEpuchPwr
- .text 0x1000f944 0x216 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_comm_int.o)
- 0x1000f944 0x2d _L1_DevDrvAllIntClear
- 0x1000f971 0x3b _L1_DevDrvRestoreAllInt
- 0x1000f9ac 0x4e _CSR_JD_DTR_ISR
- 0x1000f9fa 0xac _RFC_AFC_DST_ISR
- 0x1000faa6 0xc _L1T_RFC_AFC_DST_L1W_CSR_DTR_PSR_ISR
- 0x1000fab2 0x17 _ICP_PS2TD_UPA_ISR
- 0x1000fac9 0x58 _ICP_PS2TD_WAKEUP_ISR
- 0x1000fb21 0x28 _L1_TD_LPM_T3_ISR
- 0x1000fb49 0x11 _DMA_ISR_0
- .text 0x1000fb5a 0x6fd T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc.o)
- 0x1000fb5a 0x28 _L1_DevPcReset
- 0x1000fb82 0x3d _L1_DevPcInit
- 0x1000fbbf 0x15 _L1_DevPcErrorHandle
- 0x1000fbd4 0x99 _L1_DevPcSetRfcPwr
- 0x1000fc6d 0x18 _L1_DevPcGetDlTpcCmd
- 0x1000fc85 0xf _L1_DevPcDlTpc2Symbol
- 0x1000fc94 0x4a _L1_DevPcDlpcLimit
- 0x1000fcde 0x17 _L1_DevPcAdjTpcSsCmd
- 0x1000fcf5 0x14 _L1_DevPcUlOpenLoopPwr
- 0x1000fd09 0x7 _L1_DevPcUlCloseLoopPwr
- 0x1000fd10 0xb _L1_DevPcPathLossUpdate
- 0x1000fd1b 0x121 _L1_DevPcTxReq
- 0x1000fe3c 0xc _L1_DevPcSendOnOffToRtx
- 0x1000fe48 0x1d _L1_DevPcErucchReq
- 0x1000fe65 0x40 _L1_DevPcFpachCnf
- 0x1000fea5 0x24 _L1_DevPcUlDpchReq
- 0x1000fec9 0x1f _L1_DevPcDlDpchReq
- 0x1000fee8 0x25 _L1_DevPcHsdpaTypeReq
- 0x1000ff0d 0x25 _L1_DevPcHsupaTypeReq
- 0x1000ff32 0xd2 _L1_DevPcDchHspaGapPro
- 0x10010004 0xc6 _L1_PcTask
- 0x100100ca 0x36 _L1_DevPcUlDpchCfgReq
- 0x10010100 0x43 _L1_DevPcDlDpchCfgReq
- 0x10010143 0x7 _L1_DevPcSetTadv
- 0x1001014a 0x19 _L1_DevPcGetTadv
- 0x10010163 0x2c _L1_DevPcTadvUpdate
- 0x1001018f 0x3c _L1_DevPcHsupaErucchCfg
- 0x100101cb 0x35 _L1_DevPcHsdpaCfg
- 0x10010200 0x35 _L1_DevPcHsupaCfg
- 0x10010235 0x22 _L1_DevPcRtxTxReq
- .text 0x10010257 0x4f0 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_eng.o)
- 0x10010257 0xa7 _L1_EngTask
- 0x100102fe 0x36 _L1_DevEngPaConfig
- 0x10010334 0x3c _L1_DevEngLogNVParaCfg
- 0x10010370 0x21 _L1_DevEngLogFilter
- 0x10010391 0xcb _L1_DevEngDisplay
- 0x1001045c 0x6d _L1_DevEngTrace
- 0x100104c9 0x100 _L1_DevEngWriteDataToBuffer
- 0x100105c9 0x4e _L1_DevEngDataDump
- 0x10010617 0x64 _L1_DevEngDmacMem2Uart
- 0x1001067b 0x19 _L1_DevEngCopyMem2Dpram
- 0x10010694 0x2e _L1_DevEngErrorHandler
- 0x100106c2 0x84 _L1_DevEngDmaIntProc
- 0x10010746 0x1 _L1_DevLogFilter
- .text 0x10010747 0x848 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_tpu.o)
- 0x10010747 0x71 _L1_DevTpuReset
- 0x100107b8 0xe _L1_DevTpuSetAdvTime
- 0x100107c6 0xc _L1_DevTpuSetNetTime
- 0x100107d2 0x5 _L1_DevTpuSetQuaterNetTime
- 0x100107d7 0x7 _L1_DevTpuGetQuaterNetTime
- 0x100107de 0xe _L1_DevTpuSubFrmSlide
- 0x100107ec 0xe _L1_DevTpuSfnSet
- 0x100107fa 0x2d _L1_DevTpuSetDoff
- 0x10010827 0x7 _L1_DevTpuGetDoff
- 0x1001082e 0x20 _L1_DevTpuSfn2Cfn
- 0x1001084e 0x40 _L1_DevTpuCfn2Sfn
- 0x1001088e 0x3a _L1_DevTpuGetRealTime
- 0x100108c8 0x59 _L1_DevTpuGetSSFN
- 0x10010921 0x57 _L1_DevTpuGetNetTime
- 0x10010978 0x41 _L1_DevTpuGetAllTime
- 0x100109b9 0x42 _L1_DevTpuAddFixedEvent
- 0x100109fb 0x4f _L1_DevTpuDelFixedEvent
- 0x10010a4a 0x92 _L1_DevTpuAddVarChipEvent
- 0x10010adc 0x8a _L1_DevTpuDelVarChipEvent
- 0x10010b66 0x40 _L1_DevTpuNtToRt
- 0x10010ba6 0x37 _L1_DevTpuCalNT2RTOffset
- 0x10010bdd 0x15 _L1_DevTpuSleepFrmHeadSave
- 0x10010bf2 0x3e _L1_DevTpuNtToRtCnt
- 0x10010c30 0x9a _L1_DevTpuSleepWaite32KClkEdge
- 0x10010cca 0x51 _L1_DevTpuSleepSetNtChipZero
- 0x10010d1b 0x8 _L1_DevTpuSetSSFN
- 0x10010d23 0x70 _L1_DevTpuSleepFrmHeadRestore
- 0x10010d93 0x7 _L1_DevTpuSfn2Ssfn
- 0x10010d9a 0xa _L1_DevTpuCfn2Ssfn
- 0x10010da4 0x34 _L1_DevTpuSSfnCfnUpdate
- 0x10010dd8 0xc _L1_DevTpuGapSSfnUpdate
- 0x10010de4 0x25 _L1_DevTpuRtSSfnUpdate
- 0x10010e09 0xa1 _L1_DevTpuNTEventProc
- 0x10010eaa 0x6a _L1_DevTpuRTEventProc
- 0x10010f14 0x11 _L1_DevTpuTaskIdTransForm
- 0x10010f25 0x6a _TPU_ISR
- .text 0x10010f8f 0x897 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(L1_dev_rfc_db.o)
- 0x10010f8f 0xd _L1_DevRfcAgcDbInit
- 0x10010f9c 0x1f _L1_DevRfcAgcDbFreqPosInAgcInfo
- 0x10010fbb 0x4e _L1_DevRfcAgcDbFindOldestFreqPos
- 0x10011009 0x4d _L1_DevRfcAgcDbFindFreqPos
- 0x10011056 0x6b _L1_DevRfcAgcDbLockCheck
- 0x100110c1 0x39 _L1_DevRfcAgcDbGetAgcGain
- 0x100110fa 0x3d _L1_DevRfcEstimDschAgc
- 0x10011137 0x23 _L1_DevRfcAgcDbReliableCheck
- 0x1001115a 0x75 _L1_DevRfcAgcDbGetRssi
- 0x100111cf 0x29 _L1_DevRfcAgcDbHspaTs0AgcSet
- 0x100111f8 0x34 _L1_DevRfcAgcDbRdbCalcRssi
- 0x1001122c 0x28 _L1_DevRfcAgcGetRdbRssi
- 0x10011254 0x46 _L1_DevRfcAgcDbSet
- 0x1001129a 0x37 _L1_DevRfcAgcDbLockInfoCalc
- 0x100112d1 0x92 _L1_DevRfcAgcDbHspaTs0AgcCalc
- 0x10011363 0x55 _L1_DevRfcTargetAgcInfoGet
- 0x100113b8 0x98 _L1_DevRfcAgcDbAgcCalc
- 0x10011450 0x95 _L1_DevRfcAgcDbGetDwDelta
- 0x100114e5 0xaa _L1_DevRfcAgcDbSetCtrlInfo
- 0x1001158f 0x3b _L1_L1_DevRfcAgcPreFirstSlotGet
- 0x100115ca 0x4b _L1_DevRfcAgcPerGet
- 0x10011615 0x3e _L1_DevRfcAgcDbSaveRdbInfo
- 0x10011653 0xc _L1_DevRfcCtrlDbInit
- 0x1001165f 0x76 _L1_DevRfcCtrlDbFndMatchPatn
- 0x100116d5 0x62 _L1_DevRfcCtrlDbOperCodeGen
- 0x10011737 0x14 _L1_DevRfcCtrlDbGetLogFreq
- 0x1001174b 0x77 _L1_DevRfcCtrlDbRfcOpenMsgProc
- 0x100117c2 0x22 _L1_DevRfcCtrlDbGetPatternInfo
- 0x100117e4 0x42 _L1_DevRfcCtrlDbWakeUpMsgProc
- .text 0x10011826 0x561 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_meas.o)
- 0x10011826 0x40 _L1_DevMeasInit
- 0x10011866 0x3a _L1_DevMeasReset
- 0x100118a0 0x3e _L1_DevMeasStartRscpMeas
- 0x100118de 0x32 _L1_DevMeasStartIscpMeas
- 0x10011910 0x16f _L1_DevMeasRscpIntProc
- 0x10011a7f 0xbd _L1_DevMeasIscpIntProc
- 0x10011b3c 0x13 _L1_DevMeasIntProc
- 0x10011b4f 0x33 _L1_DevMeasRscpMeasCnf
- 0x10011b82 0x32 _L1_DevMeasIscpMeasCnf
- 0x10011bb4 0x1e _L1_DevMEASRscpGrouped
- 0x10011bd2 0x13 _L1_DevMEASIscpGrouped
- 0x10011be5 0x81 _L1_DevMeasTpuHandle
- 0x10011c66 0x40 _L1_DevMeasIntInd
- 0x10011ca6 0xe1 _L1_MeasTask
- .text 0x10011d87 0x1e12 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hsupa.o)
- 0x10011d87 0x1a _L1_DevHsupaCalcUpperLimit
- 0x10011da1 0x1e _L1_DevHsupaCalcMod
- 0x10011dbf 0x4b _L1_DevHsupaCalcMidambleUeId
- 0x10011e0a 0x35 _L1_DevHsupaCalcCodeBlockPara
- 0x10011e3f 0xf6 _L1_DevHsupaCalcRmPara
- 0x10011f35 0xb4 _L1_DevHsupaCalcEutrPara
- 0x10011fe9 0x108 _L1_DevHsupaCalcEtxPara
- 0x100120f1 0x99 _L1_DevHsupaCalcEhichRcvPara
- 0x1001218a 0x3a _L1_DevHsupaSetEhichRcvInf
- 0x100121c4 0x27 _L1_DevHsupaClrEhichRcvInf
- 0x100121eb 0x3a _L1_DevHsupaGetEhichRcvInf
- 0x10012225 0x42 _L1_DevHsupaSearchEhichRcvInf
- 0x10012267 0xb _L1_DevHsupaEhichRcvInfReset
- 0x10012272 0xd _L1_DevHsupaEhichRcvInfInit
- 0x1001227f 0x22 _L1_DevHsupaSetEpuchDataReady
- 0x100122a1 0x22 _L1_DevHsupaClrEpuchDataReady
- 0x100122c3 0x5a _L1_DevHsupaSearchEpuchSendInf
- 0x1001231d 0xa _L1_DevHsupaEpuchDataReadyReset
- 0x10012327 0xa _L1_DevHsupaEpuchDataReadyInit
- 0x10012331 0x4f _L1_DevHsupaParaInit
- 0x10012380 0x6e _L1_DevHsupaReset
- 0x100123ee 0x19 _L1_DevHsupaInit
- 0x10012407 0x189 _L1_DevHsupaSendDataProc
- 0x10012590 0x24 _L1_DevHsupaCalcNonSchEhichResId
- 0x100125b4 0x113 _L1_DevHsupaRcvEhichProc
- 0x100126c7 0x96 _L1_DevHsupaSetSchInfo
- 0x1001275d 0x8b _L1_DevHsupaSetNonSchInfo
- 0x100127e8 0x2b _L1_DevHsupaSetSpsInfo
- 0x10012813 0x34 _L1_DevHsupaSetSpsInitGrant
- 0x10012847 0x90 _L1_DevHsupaSetSpsGrantInfo
- 0x100128d7 0x3e _L1_DevHsupaSpsEagchAnalyze
- 0x10012915 0x9e _L1_DevHsupaEagchType2RdiProc
- 0x100129b3 0x89 _L1_DevHsupaEagchType2NoRdiProc
- 0x10012a3c 0x27 _L1_DevHsupaSendSpsPatternInd
- 0x10012a63 0xa7 _L1_DevHsupaEagchType2RrpiProc
- 0x10012b0a 0x21 _L1_DevHsupaSendSpsRelOrder
- 0x10012b2b 0x3b _L1_DevHsupaEagchOrderProc
- 0x10012b66 0x136 _L1_DevHsupaConfigProc
- 0x10012c9c 0x1f _L1_DevHsupaReleaseProc
- 0x10012cbb 0x2a _L1_DevHsupaByteSwitch
- 0x10012ce5 0x3 _L1_DevHsupaClrDpramBufFlag
- 0x10012ce8 0x3f _L1_DevHsupaEpuchDataPrint
- 0x10012d27 0x53 _L1_DevHsupaMbxIntErucchDataProc
- 0x10012d7a 0x1a1 _L1_DevHsupaMbxIntEdchDataProc
- 0x10012f1b 0x80 _L1_DevHsupaMbxIntProc
- 0x10012f9b 0x48 _L1_DevHsupaDmaIntProc
- 0x10012fe3 0xf _L1_DevHsupaEutrIntProc
- 0x10012ff2 0x66 _L1_DevHsupaEagchIsInvalid
- 0x10013058 0x5f _L1_DevHsupaEagchAnalyze
- 0x100130b7 0xca _L1_DevHsupaEagchType1Proc
- 0x10013181 0xd4 _L1_DevHsupaEagchIndProc
- 0x10013255 0xe9 _L1_DevHsupaEhichIndProc
- 0x1001333e 0x32 _L1_DevHsupaRdiTti
- 0x10013370 0x13 _L1_DevHsupaGetSichDpchErucchTs
- 0x10013383 0x6d _L1_DevHsupaSetSchGrantInfo
- 0x100133f0 0x1f _L1_DevHsupaSetNonSchGrantInfo
- 0x1001340f 0x33 _L1_DevHsupaSetHarqInfo
- 0x10013442 0x151 _L1_DevHsupaReportToPs
- 0x10013593 0x16 _L1_DevHsupaReportToPsCallBack
- 0x100135a9 0x26 _L1_DevHsupaSendErucchCnf
- 0x100135cf 0x3e _L1_DevHsupaFachSelCommonErnti
- 0x1001360d 0xe _L1_DevHsupaFachErucchAffixErnti
- 0x1001361b 0x26 _L1_DevHsupaSendCommonErntiInd
- 0x10013641 0x142 _L1_DevHsupaErucchSendProc
- 0x10013783 0x19 _L1_DevHsupaActivateErucch
- 0x1001379c 0x1b _L1_DevHsupaAbortErucch
- 0x100137b7 0x22 _L1_DevHsupaIntraCellIndProc
- 0x100137d9 0x20 _L1_DevHsupaCalcTxOffset
- 0x100137f9 0x54 _L1_DevHsupaGenPNSeq
- 0x1001384d 0x2f _L1_DevHsupaConfigReq
- 0x1001387c 0x21 _L1_DevHsupaRelReq
- 0x1001389d 0x21 _L1_DevHsupaErucchReq
- 0x100138be 0x21 _L1_DevHsupaErucchAbortReq
- 0x100138df 0x6c _L1_DevHsupaErucchSendReq
- 0x1001394b 0x2d _L1_DevHsupaEagchInd
- 0x10013978 0x27 _L1_DevHsupaEhichInd
- 0x1001399f 0x2c _L1_DevHsupaMbxIntInd
- 0x100139cb 0x21 _L1_DevHsupaEutrIntInd
- 0x100139ec 0x45 _L1_DevHsupaIntraCellInd
- 0x10013a31 0xb7 _L1_DevHsupaFachConfigProc
- 0x10013ae8 0x14 _L1_DevHsupaFachReleaseProc
- 0x10013afc 0x31 _L1_DevHsupaFachConfigReq
- 0x10013b2d 0x21 _L1_DevHsupaFachRelReq
- 0x10013b4e 0x10 _L1_DevHsupaEagchMissCntDebug
- 0x10013b5e 0x3b _L1_DevHsupaGetNack
- .text 0x10013b99 0xaa4 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_sleep.o)
- 0x10013b99 0x28 _L1t_SetTdsLpcMacroValue
- 0x10013bc1 0x8 _L1_DevSleepSetCfunFlg
- 0x10013bc9 0x7f _L1t_DevSleepNoLpc
- 0x10013c48 0x7 _L1t_DevLpcSetDwFinger
- 0x10013c4f 0x7 _L1t_DevLpcGetDwFinger
- 0x10013c56 0x45 _L1t_DevLpcPwrCtrl
- 0x10013c9b 0x1c _L1t_DevLpcDvfs
- 0x10013cb7 0xec _L1t_DevLpcPwrFreqCtrl
- 0x10013da3 0x3b _L1t_DevLpcIcpSendForPsm
- 0x10013dde 0x1b _L1t_DevLpcSendIcpInOneSfn
- 0x10013df9 0xf _L1t_DevLpcGetL1sRecPSMsgPerm
- 0x10013e08 0x46 _L1t_DevLpcWakeupRfResUpdate
- 0x10013e4e 0x1e _L1t_DevLpcWakeDpramSfnUpdate
- 0x10013e6c 0x8 _L1t_DevLpcSetAbleToCfgPsLpm
- 0x10013e74 0x8 _L1t_DevLpcGetAbleToCfgPsLpm
- 0x10013e7c 0xa _L1t_DevLpcGetWakeUpType
- 0x10013e86 0x8 _L1t_DevLpcSetPiResultFlg
- 0x10013e8e 0x8 _L1t_DevLpcGetPiResultFlg
- 0x10013e96 0xe _L1t_DevLpcSetPreIcpFlg
- 0x10013ea4 0x8 _L1t_DevLpcGetPreIcpFlg
- 0x10013eac 0x8 _L1t_DevLpcDrxLongFlg
- 0x10013eb4 0x16 _L1t_DevLpcRemoveSchedAgc
- 0x10013eca 0x1 _L1t_DevLpcWakeNotAgcPro
- 0x10013ecb 0x8 _L1t_DevLpcSetQuickWakeFlg
- 0x10013ed3 0x2 _L1t_DevLpcGetQuickWakeFlg
- 0x10013ed5 0x8 _L1t_DevLpcSetMcsValidFlg
- 0x10013edd 0x8 _L1t_DevLpcGetMcsValidFlg
- 0x10013ee5 0x8 _L1t_DevLpcSetPichRcvPos
- 0x10013eed 0x2 _L1t_DevLpcCheckRfQuickOpen
- 0x10013eef 0x69 _L1t_DevLpcSendWakeRfMsg
- 0x10013f58 0x1 _L1t_DevLpcWakeUpOpenRf
- 0x10013f59 0x8 _L1t_DevLpcSetPorcState
- 0x10013f61 0x8 _L1t_DevLpcGetPorcState
- 0x10013f69 0x7 _L1t_DevLpcSetGapInfo
- 0x10013f70 0x74 _L1t_DevLpcGetTdsSleepLen
- 0x10013fe4 0x10 _L1t_DevLpcWakeupClrModemInt
- 0x10013ff4 0x42 _L1t_DevLpcRestoreSFN
- 0x10014036 0x55 _L1t_DevLpcWakeupTpuCheck
- 0x1001408b 0x3 _L1t_DevLpcMasterWakeAhead
- 0x1001408e 0x73 _L1t_DevLpcCalcWakeTimeFcCc
- 0x10014101 0x1 _L1t_DevLpcWdtdipPrwCtrl
- 0x10014102 0x8 _L1t_GetNtSsfn
- 0x1001410a 0xa _L1t_DevLpcWorkSfnCnt
- 0x10014114 0x7e _L1t_DevLpcInit
- 0x10014192 0x7d _L1t_DevLpcCfgSocWkupInt
- 0x1001420f 0x14 _L1t_DevLpcDisSocWkupInt
- 0x10014223 0x17 _L1t_DevLpcSetWakeupFlag
- 0x1001423a 0x1e3 _L1t_ModemLpcSleep
- 0x1001441d 0x220 _L1t_ModemLpcWakeup
- .text 0x1001463d 0xb52 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_afc.o)
- 0x1001463d 0x42 _L1_DevDlsAfcGlobInit
- 0x1001467f 0x11 _L1_DevDlsAfcMaStart
- 0x10014690 0x5e _L1_DevDlsAfcProc
- 0x100146ee 0x34 _L1_DevDlsAfcFoeAdjStatSel
- 0x10014722 0x1b _L1_DevDlsAfcSlotIntProc
- 0x1001473d 0xaa _L1_DevDlsAfcDataFoeProc
- 0x100147e7 0x54 _L1_DevDlsAfcFoeCalProc
- 0x1001483b 0x38 _L1_DevAfcNormalToAfc
- 0x10014873 0x22 _L1_DevAfcToNormal
- 0x10014895 0x10b _L1_DevAfcCalcPhaseErr
- 0x100149a0 0x5c _L1_DevAfcDiv
- 0x100149fc 0x7c _L1_DevAfcAdd
- 0x10014a78 0x1c _L1_DevAfcMultip
- 0x10014a94 0xd _L1_DevAfcCompABS
- 0x10014aa1 0x2d _L1_DevDlsAfcFactorSel
- 0x10014ace 0xc8 _L1_DevDlsAfcReport
- 0x10014b96 0x74 _L1_DevAfcLockCheck
- 0x10014c0a 0x2a _L1_DevAfcLockReport
- 0x10014c34 0x2b _L1_DevAfcSendFreqMsgToL1s
- 0x10014c5f 0x3b _L1_DevAfcFreqAdjReport
- 0x10014c9a 0x73 _L1_DevAfcCellInfoSet
- 0x10014d0d 0x28 _L1_DevDlsAfcReset
- 0x10014d35 0x3e _L1_DevDlsAfcInit
- 0x10014d73 0x9 _L1_DevAfcStartCal
- 0x10014d7c 0x9 _L1_DevAfcActive
- 0x10014d85 0x18 _L1_DevAfcFingerCfg
- 0x10014d9d 0x38 _L1_DevAfcMAStart
- 0x10014dd5 0x5f _L1_DevAfcMAFingerIQCal
- 0x10014e34 0x35 _L1_DevAfcMAFoeConfig
- 0x10014e69 0x4a _L1_DevAfcMADel
- 0x10014eb3 0x14 _L1_DevAfcRdbReset
- 0x10014ec7 0x50 _L1_DevAfcRdbMaFoeCal
- 0x10014f17 0x21 _L1_DevAfcMADataStore
- 0x10014f38 0x48 _L1_DevAfcReadMid
- 0x10014f80 0xf _L1_DevAfcFormatCheck
- 0x10014f8f 0x43 _L1_DevDlsMaFoeReq
- 0x10014fd2 0x42 _L1_DevDlsDataFoeReq
- 0x10015014 0x6 _L1_DevAfcSgnData
- 0x1001501a 0x121 _L1_DevAfcCalcIqData
- 0x1001513b 0x33 _L1_DevDlsDataAdjFoeReq
- 0x1001516e 0x21 _L1_DevDLSAFCIntInd
- .text 0x1001518f 0xa2b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_db.o)
- 0x1001518f 0xb7 _L1_DevDbInit
- 0x10015246 0x23 _L1_DevDbCalcTrchCfgMaxTti
- 0x10015269 0x3f _L1_DevDbGetTrchCfgMaxTti
- 0x100152a8 0x25 _L1_DevDbCalcTrchCfgMinTti
- 0x100152cd 0x3f _L1_DevDbGetTrchCfgMinTti
- 0x1001530c 0x40 _L1_DevDbSetCctrchQualitytData
- 0x1001534c 0xb _L1_DevDbClearCctrchQualitytData
- 0x10015357 0x34 _L1_DevDbGetCctrchQualitytData
- 0x1001538b 0x35 _L1_DevDbSetEhichTpcSsInfo
- 0x100153c0 0xbf _L1_DevDbSetRxInfo
- 0x1001547f 0x28 _L1_DevDbGetRxInfo
- 0x100154a7 0x2e _L1_DevDbSetSbInfo
- 0x100154d5 0x2e _L1_DevDbGetSbInfo
- 0x10015503 0x2b _L1_DevDbSetFpachData
- 0x1001552e 0x2b _L1_DevDbGetFpachData
- 0x10015559 0x48 _L1_DevDbSetDchCrcInfo
- 0x100155a1 0x2d _L1_DevDbGetDchCrcInfo
- 0x100155ce 0x8 _L1_DevDbSetTxPcEn
- 0x100155d6 0x8 _L1_DevDbSetTxPcDisEn
- 0x100155de 0x7 _L1_DevDbGetTxPcEn
- 0x100155e5 0x85 _L1_DevDbSetTxInfo
- 0x1001566a 0x2c _L1_DevDbGetTxInfo
- 0x10015696 0x3e _L1_DevDbSetHsscchInfo
- 0x100156d4 0x34 _L1_DevDbGetHsscchInfo
- 0x10015708 0x3e _L1_DevDbSetEagchInfo
- 0x10015746 0x2a _L1_DevDbGetEagchInfo
- 0x10015770 0x3a _L1_DevDbSetMcheData
- 0x100157aa 0x19 _L1_DevDbGetMcheDataAddr
- 0x100157c3 0x1f _L1_DevDbSetDagcResult
- 0x100157e2 0x21 _L1_DevDbGetDagcResult
- 0x10015803 0x63 _L1_DevDbSetJdoutData
- 0x10015866 0x3b _L1_DevDbGetJdoutData
- 0x100158a1 0x1a _L1_DevDbGetJdoutAddr
- 0x100158bb 0x40 _L1_DevDbGetOneChanJdoutData
- 0x100158fb 0x2b _L1_DevDbSetTpcSsData
- 0x10015926 0x2a _L1_DevDbGetTpcSsData
- 0x10015950 0x2b _L1_DevDbSetCodePwrData
- 0x1001597b 0x2a _L1_DevDbGetCodePwrData
- 0x100159a5 0x36 _L1_DevDbResetRxIntData
- 0x100159db 0x18 _L1_DevDbResetTxInfo
- 0x100159f3 0x1f _L1_DevDbResetRxCrcInfo
- 0x10015a12 0x14 _L1_DevDbResetHsscchInfo
- 0x10015a26 0x14 _L1_DevDbResetEagchInfo
- 0x10015a3a 0xc _L1_DevDbResetInfoForPc
- 0x10015a46 0x7 _L1_DevDbSetUlDataFlag
- 0x10015a4d 0x7 _L1_DevDbGetUlDataFlag
- 0x10015a54 0x17 _L1_DevDbResetUlDpchInfo
- 0x10015a6b 0x1f _L1_DevDbResetDlDpchInfo
- 0x10015a8a 0x28 _L1_DevDbResetDpchInfo
- 0x10015ab2 0x25 _L1_DevDbResetHsdpaInfo
- 0x10015ad7 0x23 _L1_DevDbResetHsupaInfo
- 0x10015afa 0xb _L1_DevDbReadRtxSirValue
- 0x10015b05 0xc _L1_DevDbSaveRtxSirValue
- 0x10015b11 0xc _L1_DevDbSetRtx2RfcSirFlag
- 0x10015b1d 0xb _L1_DevDbGetRtx2RfcSirFlag
- 0x10015b28 0x6 _L1_DevDbGetPageParaAddr
- 0x10015b2e 0x6 _L1_DevDbGetFachParaAddr
- 0x10015b34 0x7 _L1_DevDbSetMeasRscp
- 0x10015b3b 0x7 _L1_DevDbGetMeasRscp
- 0x10015b42 0x4b _L1_DevDbSetUlData
- 0x10015b8d 0x7 _L1_DevDbSetDlDataOk
- 0x10015b94 0x7 _L1_DevDbGetDlDataOk
- 0x10015b9b 0x7 _L1_DevDbGetUlMinTti
- 0x10015ba2 0x6 _L1_DevDbGetUlDataAddr
- 0x10015ba8 0x9 _L1_DevDbSetSirThresIndex
- 0x10015bb1 0x9 _L1_DevDbGetSirThresIndex
- .text 0x10015bba 0x3c2 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_tadv.o)
- 0x10015bba 0x10 _L1_DevPcGetTpuOffset
- 0x10015bca 0xd7 _L1_DevPcTadvAdjProtect
- 0x10015ca1 0x23 _L1_DevPcCctrchSsCmd
- 0x10015cc4 0x43 _L1_DevPcUlTadvPriStrategyCalc
- 0x10015d07 0xa _L1_DevPcUlTimingSsCmd
- 0x10015d11 0x28 _L1_DevPcUlTimingFollowTpu
- 0x10015d39 0x48 _L1_DevPcUlGetTadvInit
- 0x10015d81 0x40 _L1_DevPcUlGetErucchTadv
- 0x10015dc1 0x3a _L1_DevPcUlSetTadvPara
- 0x10015dfb 0xe _L1_DevPcGetUlTadvCmd
- 0x10015e09 0xa4 _L1_DevPcUlAdjustTadv
- 0x10015ead 0x4c _L1_DevPcUlRecfgSwitchTadv
- 0x10015ef9 0x83 _L1_DevPcUlTimingPro
- .text 0x10015f7c 0x654 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_ulpwr.o)
- 0x10015f7c 0x71 _L1_DevPcUlPwrPro
- 0x10015fed 0x70 _L1_DevPcUlMultiChanPwrPro
- 0x1001605d 0x24b _L1_DevPcUlPwrGetParam
- 0x100162a8 0x95 _L1_DevPcUlTriChanPwrPro
- 0x1001633d 0x14 _L1_DevPcUlPwrGetPwrLimit
- 0x10016351 0x30 _L1_DevPcPwrSetDpchScale
- 0x10016381 0x16 _L1_DevPcPwrSetHssichScale
- 0x10016397 0x16 _L1_DevPcPwrSetErucchScale
- 0x100163ad 0x31 _L1_DevPcPwrSetEpuchScale
- 0x100163de 0x70 _L1_DevPcUlPwrSetScale
- 0x1001644e 0xd6 _L1_DevPcUlPwrCalcPwrScale
- 0x10016524 0x1e _L1_DevPcDb2Linear
- 0x10016542 0x19 _L1_DevPcLinear2Db
- 0x1001655b 0x75 _L1_DevPcUlPwrCalcSqrt
- .text 0x100165d0 0x29f T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_dst.o)
- 0x100165d0 0xad _L1_DrvDstInitial
- 0x1001667d 0x90 _L1_DrvDstInitial2
- 0x1001670d 0xa _L1_DrvDstRdAfcMaxPath
- 0x10016717 0x35 _L1_DrvDstWrAfcCellInfo
- 0x1001674c 0x52 _L1_DrvDstCfgCoarCellInfo
- 0x1001679e 0x24 _L1_DrvDstCoarStart
- 0x100167c2 0x2b _L1_DrvDstCfgInterf
- 0x100167ed 0x4f _L1_DrvDstStartDwPtsSync
- 0x1001683c 0x2a _L1_DrvDstStartMcheSync
- 0x10016866 0x9 _L1_DrvDSTReadMaxPath
- .text 0x1001686f 0x26b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_sleep.o)
- 0x1001686f 0xe _L1t_DrvLpcSetSleepFlag
- 0x1001687d 0xe _L1t_DrvLpcSetCampOnFlg
- 0x1001688b 0x10 _L1t_DrvLpcNotPageSetLpmIntTime
- 0x1001689b 0x10 _L1t_DrvLpcPageSetLpmIntTime
- 0x100168ab 0x7 _L1t_DrvLpcLpm10MIntSet
- 0x100168b2 0x7 _L1t_DrvLpcLpm32kIntSet
- 0x100168b9 0xf _L1t_DrvLpcSocWkTimeCfg
- 0x100168c8 0xf _L1t_DrvLpcModemWkTimeCfg
- 0x100168d7 0x10 _L1t_DrvLpcSocWakeUpIntCtrl
- 0x100168e7 0x11 _L1t_DrvLpcModemWakeUpIntCtrl
- 0x100168f8 0xca _L1t_DrvLpcCfgModemWkupInt
- 0x100169c2 0x8 _L1t_DrvLpcPsLpm8xClkEnCtr
- 0x100169ca 0x17 _L1t_DrvLpcCloseClk
- 0x100169e1 0x16 _L1t_DrvLpcOpenClk
- 0x100169f7 0xc _L1t_DrvLpcAfcAgcIntOpen
- 0x10016a03 0xe _L1t_DrvLpcDstAfcAgcIntCls
- 0x10016a11 0x1c _L1t_DrvLpcTdsModemIntCtrl
- 0x10016a2d 0x10 _L1t_DrvLpcGetLpmNT
- 0x10016a3d 0xe _L1t_DrvLpcGetLpmRT
- 0x10016a4b 0x32 _L1t_DrvLpcModemSave
- 0x10016a7d 0x4d _L1t_DrvLpcModemStdDrxRestore
- 0x10016aca 0xf _L1t_DrvLpcModemDpaRestore
- 0x10016ad9 0x1 _L1t_DrvLpcClrTopRfTpuReg
- .text 0x10016ada 0x344 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_csr.o)
- 0x10016ada 0x1b _L1_DrvCsrStop
- 0x10016af5 0x20 _L1_DrvCsrRdbReset
- 0x10016b15 0x1b _L1_DrvCsrSetSample
- 0x10016b30 0x10 _L1_DrvCsrSetTimeBase
- 0x10016b40 0x9 _L1_DrvCsrGetTimeBase
- 0x10016b49 0xe _L1_DrvCsrSyncidCutMode
- 0x10016b57 0xf _L1_DrvCsrMidIdCutMode
- 0x10016b66 0x22 _L1_DrvCsrEngParaCfg
- 0x10016b88 0x16 _L1_DrvCsrEngPosParaCfg
- 0x10016b9e 0x19 _L1_DrvCsrSyncParaCfg
- 0x10016bb7 0xe _L1_DrvCsrSyncCorrModeCfg
- 0x10016bc5 0xc _L1_DrvCsrSyncMaskCfg
- 0x10016bd1 0x27 _L1_DrvCsrSyncM1StateRdRst
- 0x10016bf8 0xa _L1_DrvCsrStartEng
- 0x10016c02 0xa _L1_DrvCsrStartSyncDl
- 0x10016c0c 0x10 _L1_DrvCsrMidIterate
- 0x10016c1c 0xf _L1_DrvCsrMidSyncNum
- 0x10016c2b 0x101 _L1_DrvCsrSetMidInput
- 0x10016d2c 0xa _L1_DrvCSRStartMid
- 0x10016d36 0x11 _L1_DrvCSROpenIntMask
- 0x10016d47 0x1f _L1_DrvCsrGetDpramEngPeak
- 0x10016d66 0x80 _L1_DrvCSRGetSyncM1Power
- 0x10016de6 0x9 _L1_DrvCsrGetEngIterate
- 0x10016def 0x9 _L1_DrvCsrGetSyncIterate
- 0x10016df8 0x9 _L1_DrvCsrGetSyncMode
- 0x10016e01 0x9 _L1_DrvCsrGetSampRat
- 0x10016e0a 0x14 _L1_DrvCsrGetDpramMidPeak
- .text 0x10016e1e 0x968 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rfc.o)
- 0x10016e1e 0x11 _L1_DrvTxRRC
- 0x10016e2f 0x11 _L1_DrvRxRRC
- 0x10016e40 0x7 _L1_DrvRfcRamEnCtrl
- 0x10016e47 0x9 _L1_DrvRfcGetWorkingRamIndex
- 0x10016e50 0x7 _L1_DrvRfcSetRAMStartTime
- 0x10016e57 0x9 _L1_DrvRfcGetWorkStatus
- 0x10016e60 0x23 _L1_DrvRfcSetIntTime
- 0x10016e83 0x9 _L1_DrvRfcGetIntType
- 0x10016e8c 0x12 _L1_DrvRfcInterEnCtrl
- 0x10016e9e 0x79 _L1_DrvRfcNotchCordicCfg
- 0x10016f17 0x9 _L1_DrvRfcGetEstimatePwr
- 0x10016f20 0x65 _L1_DrvRfcGetMaxPower
- 0x10016f85 0x27 _L1_DrvRfcRtxRegInit
- 0x10016fac 0x20 _L1_DrvRfcMipiRffeWrite
- 0x10016fcc 0x20 _L1_DrvRfcMipiRffeDoubleWrite
- 0x10016fec 0x14 _L1_DrvRfcGpioWrite
- 0x10017000 0x30 _L1_DrvRfcSpiWrite
- 0x10017030 0x2f _L1_DrvRfcAbbSpiWrite
- 0x1001705f 0x61 _L1_DrvRfcDirectRamSwitch
- 0x100170c0 0x3b _L1_DrvRfcRamEventWrt
- 0x100170fb 0x1b _L1_DrvRfcEventDataWrt
- 0x10017116 0x1e _L1_DrvRfcSwPaWrite
- 0x10017134 0x1f _L1_DrvRfcGetTxSwData
- 0x10017153 0x1f _L1_DrvRfcGetRxSwData
- 0x10017172 0x21 _L1_DrvRfcGetSwIdleData
- 0x10017193 0x2d _L1_DrvRfcGetPaCtrlData
- 0x100171c0 0x1f _L1_DrvRfcGetPaIdleCtrlData
- 0x100171df 0x33 _L1_DrvRfcEventOffsetWrt
- 0x10017212 0xa7 _L1_DrvRfcEventRamInitSet
- 0x100172b9 0x6b _L1_DrvRfcUnavailEvntInit
- 0x10017324 0x9 _L1_DrvRfcSyncModeSwitchEnable
- 0x1001732d 0xf _L1_DrvRfcNormalRamInit
- 0x1001733c 0xb _L1_DrvRfcUnSyncRamDisable
- 0x10017347 0x41 _L1_DrvRfcEventEnable
- 0x10017388 0x25 _L1_DrvRfcEventDisable
- 0x100173ad 0x32 _L1_DrvRfcSlotEventDisable
- 0x100173df 0x70 _L1_DrvRfcModeSwitch
- 0x1001744f 0x53 _L1_DrvRfcTs0EventOffsetAdj
- 0x100174a2 0xb _L1_DrvRfcSlotUpCheck
- 0x100174ad 0x63 _L1_DrvRfcTxEventOffsetAdjust
- 0x10017510 0x7 _L1_DrvRfcTs6Ts0FreqDiff
- 0x10017517 0x80 _L1_DrvRfcReset
- 0x10017597 0x80 _L1_DrvRfcInit
- 0x10017617 0x40 _L1_DrvRfcGetAfcCtrlWord
- 0x10017657 0x42 _L1_DrvRfcCheckDACTable
- 0x10017699 0x2 _L1_DrvRfcApcTmpCmp
- 0x1001769b 0x2d _L1_DrvRfcFreqCmpSearchNvIdx
- 0x100176c8 0x3c _L1_DrvRfcApcFreCmp
- 0x10017704 0x2c _L1_DrvRfcAgcFreCmp
- 0x10017730 0x56 _L1_DrvRfcRestore
- .text 0x10017786 0x253 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_tpu.o)
- 0x10017786 0x13 _L1_DrvTpuReset
- 0x10017799 0x31 _L1_DrvTpuInit
- 0x100177ca 0x10 _L1_DrvTpuMaskIntEnableCfg
- 0x100177da 0x8 _L1_DrvTpuMaskIntDisableCfg
- 0x100177e2 0x1c _L1_DrvTpuSoftResetCfg
- 0x100177fe 0xe _L1_DrvTpuNTIntEnable
- 0x1001780c 0xf _L1_DrvTpuNTIntDisable
- 0x1001781b 0xe _L1_DrvTpuRTIntEnable
- 0x10017829 0xf _L1_DrvTpuRTIntDisable
- 0x10017838 0x84 _L1_DrvTpuNTSyncQuaterChipCfg
- 0x100178bc 0x22 _L1_DrvTpuNTSyncSubFrmCfg
- 0x100178de 0x14 _L1_DrvTpuNTSyncSubFrmSlipCfg
- 0x100178f2 0x10 _L1_DrvTpuLatchTimeCfg
- 0x10017902 0x23 _L1_DrvTpuRdNTTiming
- 0x10017925 0x13 _L1_DrvTpuRdRTTiming
- 0x10017938 0x1a _L1_DrvTpuNTIntParaCfg
- 0x10017952 0x1a _L1_DrvTpuRTIntParaCfg
- 0x1001796c 0x35 _L1_DrvTpuSaveReg
- 0x100179a1 0x38 _L1_DrvTpuRestorReg
- .text 0x100179d9 0x6f9 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_tx.o)
- 0x100179d9 0xc _L1_DrvTxLogTwo
- 0x100179e5 0x2e _L1_DrvTxReset
- 0x10017a13 0x2b _L1_DrvTxUppchConfig
- 0x10017a3e 0xd _L1_DrvTxUppchStop
- 0x10017a4b 0x28 _L1_DrvTxHssichStop
- 0x10017a73 0x1c _L1_DrvTxPrachEnable
- 0x10017a8f 0x1d _L1_DrvTxDpchEnable
- 0x10017aac 0x14 _L1_DrvTxClose
- 0x10017ac0 0x104 _L1_DrvTxPrachConfig
- 0x10017bc4 0x81 _L1_DrvTxClearTsPara
- 0x10017c45 0xd9 _L1_DrvTxDpchConfig
- 0x10017d1e 0xe9 _L1_DrvTxDpchCh1Cfg
- 0x10017e07 0xd3 _L1_DrvTxDpchCh2Cfg
- 0x10017eda 0x77 _L1_DrvTxHssichConfig
- 0x10017f51 0x11 _L1_DrvTxUpTimingCfg
- 0x10017f62 0x10 _L1_DrvTxUpDataScale
- 0x10017f72 0x1c _L1_DrvTxOffsetCfg
- 0x10017f8e 0x6c _L1_DrvTxTxTpcBitCfg
- 0x10017ffa 0x27 _L1_DrvTxTsChScale
- 0x10018021 0x1a _L1_DrvTxHssichTsChScale
- 0x1001803b 0x9 _L1_DrvTxHssichTpcBitCfg
- 0x10018044 0x36 _L1_DrvTxRegClear
- 0x1001807a 0x22 _L1_DrvTxSoftModeCfg
- 0x1001809c 0x1b _L1_DrvTxSoftModeClear
- 0x100180b7 0x1b _L1_DrvTxSoftCh1BitsCfg
- .text 0x100180d2 0x240 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_meas.o)
- 0x100180d2 0x28 _L1_DrvMeasInit
- 0x100180fa 0x5 _L1_DrvMeasStop
- 0x100180ff 0x56 _L1_DrvMeasStart
- 0x10018155 0x4c _L1_DrvMeasRscpIntProc
- 0x100181a1 0x12e _L1_DrvMeasIscpIntProc
- 0x100182cf 0x5 _L1_DrvMeasGetBs
- 0x100182d4 0x8 _L1_DrvMeasGetBitshiftrm
- 0x100182dc 0x36 _Meas_Arith_CountQ8Db
- .text 0x10018312 0x3d1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_hsupa.o)
- 0x10018312 0xa _L1_DrvHsupaEutrEnable
- 0x1001831c 0xa _L1_DrvHsupaEutrDisable
- 0x10018326 0x124 _L1_DrvHsupaEutrConfig
- 0x1001844a 0xe _L1_DrvHsupaEtxEnable
- 0x10018458 0xa _L1_DrvHsupaEtxDisable
- 0x10018462 0xfd _L1_DrvHsupaEtxConfig
- 0x1001855f 0x37 _L1_DrvHsupaEpuchScaleConfig
- 0x10018596 0xa _L1_DrvHsupaErucchEnable
- 0x100185a0 0x12 _L1_DrvHsupaErucchDisable
- 0x100185b2 0x99 _L1_DrvHsupaErucchConfig
- 0x1001864b 0x18 _L1_DrvHsupaErucchScaleConfig
- 0x10018663 0xe _L1_DrvHsupaTpcConfig
- 0x10018671 0x1f _L1_DrvHsupaTxOffsetConfig
- 0x10018690 0xc _L1_DrvHsupaRegClear
- 0x1001869c 0xa _L1_DrvHsupaEnableInt
- 0x100186a6 0xa _L1_DrvHsupaMaskInt
- 0x100186b0 0x17 _L1_DrvHsupaGetHarqRamOffset
- 0x100186c7 0x1c _L1_DrvHsupaGetHarqRamAddr
- .text 0x100186e3 0x298 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_dpram.o)
- 0x100186e3 0x21 _L1_DrvDpramStructInit
- 0x10018704 0x38 _L1_DrvDpramInit
- 0x1001873c 0x29 _L1_DrvDpramIsEmpty
- 0x10018765 0x43 _L1_DrvDpramReadMsg
- 0x100187a8 0x1 _L1_DrvDpramUpdateMsgPos
- 0x100187a9 0x1 _L1_DrvDpramQueMemRead
- 0x100187aa 0x1a _L1_DrvICPSend
- 0x100187c4 0x36 _L1_DrvDpramWriteMsg
- 0x100187fa 0x2e _L1_DrvDpramGetRdDataPtr
- 0x10018828 0x27 _L1_DrvDpramUpdateRdDataPos
- 0x1001884f 0x3e _L1_DrvDpramGetWrDataPtr
- 0x1001888d 0x3d _L1_DrvDpramUpdateWrDataPos
- 0x100188ca 0x24 _L1_DpramTxReadClearData
- 0x100188ee 0x27 _L1_DrvDpramSleepCheck
- 0x10018915 0xa _L1_DrvDpramCheckA2DMsg
- 0x1001891f 0xa _L1_DrvDpramCheckD2AMsg
- 0x10018929 0x2 _L1_DrvDpramReadL1tQueueFlag
- 0x1001892b 0x8 _L1_DrvDpramWriteSfnDpramFlg
- 0x10018933 0x7 _L1_DrvDpramReadIcpIntState
- 0x1001893a 0x7 _L1_DrvDpramClrIcpIntState
- 0x10018941 0xa _L1_DrvDpramMaskIcpInt
- 0x1001894b 0x9 _L1_DrvDpramDemaskIcpInt
- 0x10018954 0x11 _L1S_DrvDpramWriteTiming
- 0x10018965 0x7 _L1_DrvDpramWriteUph
- 0x1001896c 0x7 _L1_DrvDpramWriteSnpl
- 0x10018973 0x8 _L1_DrvDpramAbnomalRst
- .text 0x1001897b 0xace T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rx.o)
- 0x1001897b 0x4d _L1_DrvRxReset
- 0x100189c8 0x167 _L1_DrvRxInit
- 0x10018b2f 0x12 _L1_DrvRxAmmse
- 0x10018b41 0xb _L1_DrvRxReadAmmse
- 0x10018b4c 0xb _L1_DrvRxGetDenoiseFactor
- 0x10018b57 0x2a _L1_DrvRxSetDenoiseFactor
- 0x10018b81 0x1fd _L1_DrvRxSlotParaCfg
- 0x10018d7e 0x73 _L1_DrvRxSlotParaRel
- 0x10018df1 0x61 _L1_DrvRxIntraCellSlotCfg
- 0x10018e52 0x22 _L1_DrvRxReadMcheIntInd
- 0x10018e74 0x8 _L1_DrvRxReadMcheDataAddr
- 0x10018e7c 0xa _L1_DrvRxReadDagcResultAddr
- 0x10018e86 0x3f _L1_DrvRxReadJdcoreIntInd
- 0x10018ec5 0xa _L1_DrvRxReadJdoutDataAddr
- 0x10018ecf 0xa _L1_DrvRxReadTpcSsDataAddr
- 0x10018ed9 0xa _L1_DrvRxReadCodePwrDataAddr
- 0x10018ee3 0x21 _L1_DrvRxReadHichIntInd
- 0x10018f04 0x3f _L1_DrvRtxReadRxIntResult
- 0x10018f43 0x4a _L1_DrvRtxReadJdOut
- 0x10018f8d 0x26 _L1_DrvRxForcedCfg
- 0x10018fb3 0xb7 _L1_DrvRxCctrchReCfg
- 0x1001906a 0x68 _L1_DrvRxCctrchParaCfg
- 0x100190d2 0x21 _L1_DrvRxReadEHichRegInfo
- 0x100190f3 0x18 _L1_DrvRxReadMcheWinPower
- 0x1001910b 0x1d _L1_DrvRxReadCctrchSBValue
- 0x10019128 0x30 _L1_DrvRxReadHwacdIntInd
- 0x10019158 0x59 _L1_DrvRxConfigFcCodeReg
- 0x100191b1 0x50 _L1_DrvRxHspaCodeCfg
- 0x10019201 0x21 _L1_DrvRxSetDtxFactor
- 0x10019222 0x19 _L1_DrvRxRecfgRscpGf
- 0x1001923b 0x2a _L1_DrvRx2MeasRscpResult
- 0x10019265 0x22 _L1_DrvRx2MeasRscpInit
- 0x10019287 0xd _L1_DrvRx2MeasRscpStop
- 0x10019294 0x32 _L1_DrvRx2MeasRscpCfg
- 0x100192c6 0x9 _L1_DrvRx2MeasJdCellIdAddr
- 0x100192cf 0x9 _L1_DrvRx2MeasJdResultAddr
- 0x100192d8 0x2 _L1_DrvRx2MeasGetBs
- 0x100192da 0x36 _L1_DrvRxSetDagcPara
- 0x10019310 0x57 _L1_DrvRxReadJdCctrchCfg
- 0x10019367 0x71 _L1_DrvRxSaveReg
- 0x100193d8 0x71 _L1_DrvRxRestorReg
- .text 0x10019449 0x9b1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_dtr.o)
- 0x10019449 0x36 _L1_DrvDtrReset
- 0x1001947f 0xae _L1_DrvDtrInit
- 0x1001952d 0xd _L1_DrvDtrRegSet1Update
- 0x1001953a 0x83 _L1_DrvDtrBchCfg
- 0x100195bd 0x23 _L1_DrvDtrBchRel
- 0x100195e0 0x4e _L1_DrvDtrFachPchS1Cfg
- 0x1001962e 0x25 _L1_DrvDtrFachPchRel
- 0x10019653 0x67 _L1_DrvDtrFpachCfg
- 0x100196ba 0x1e _L1_DrvDtrFpachRel
- 0x100196d8 0x165 _L1_DrvDtrFachPchS2Cfg
- 0x1001983d 0x90 _L1_DrvDtrDlDchS1Cfg
- 0x100198cd 0xd _L1_DrvDtrTurboCfg
- 0x100198da 0x22 _L1_DrvDtrTurboReset
- 0x100198fc 0x25 _L1_DrvDtrDchS1Rel
- 0x10019921 0x1dd _L1_DrvDtrDchS2Cfg
- 0x10019afe 0x52 _L1_DrvDtrS2Rel
- 0x10019b50 0x90 _L1_DrvDtrHsscchCfg
- 0x10019be0 0x44 _L1_DrvDtrHsscchRel
- 0x10019c24 0x88 _L1_DrvDtrEagchCfg
- 0x10019cac 0x44 _L1_DrvDtrEagchRel
- 0x10019cf0 0xd _L1_DrvDtrTfUpdate
- 0x10019cfd 0x1c _L1_DrvDtrReadTfciIntInd
- 0x10019d19 0x24 _L1_DrvDtrReadTtiIntInd
- 0x10019d3d 0x37 _L1_DrvDtrReadTrchData
- 0x10019d74 0x14 _L1_DrvDtrReadTrchOutState2
- 0x10019d88 0xe _L1_DrvDtrGetCrcMode
- 0x10019d96 0x11 _L1_DrvDtrGetTtiType
- 0x10019da7 0x21 _L1_DrvDtrCfgMaxTti
- 0x10019dc8 0x20 _L1_DrvDtrSetDoffMode
- 0x10019de8 0x12 _L1_DrvDtrClearDoffMode
- .text 0x10019dfa 0x1402 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rfc_zx220a1.o)
- 0x10019dfa 0x2e _L1_DrvRfcApcTableSel
- 0x10019e28 0x1a2 _L1_DrvRfcAbbCsfHpfCfg
- 0x10019fca 0x1 _L1_DrvRfcNvInit
- 0x10019fcb 0x29 _L1_DrvRfcCalcFracFreq
- 0x10019ff4 0x5 _L1_DrvRfcCalcIntFreq
- 0x10019ff9 0x39 _L1_DrvRfcGetFreqData
- 0x1001a032 0xcc _L1_DrvRfcRfTxOpenForever
- 0x1001a0fe 0xb1 _L1_DrvRfcRfRxOpenForever
- 0x1001a1af 0xa _L1_DrvRfcDeviceInit
- 0x1001a1b9 0x31 _L1_DrvRfcPaIdleSet
- 0x1001a1ea 0x2a _L1_DrvRfcDmSwCfg
- 0x1001a214 0xda _L1_DrvRfcFreqSet
- 0x1001a2ee 0x11 _L1_DrvRfcInitAfcSet
- 0x1001a2ff 0x2c _L1_DrvRfcAfcCtrl
- 0x1001a32b 0x7a _L1_DrvRfcApcSet
- 0x1001a3a5 0x4f _L1_DrvRfcSwPaIdleNvGet
- 0x1001a3f4 0x65 _L1_DrvRfcPaSet
- 0x1001a459 0xa0 _L1_DrvRfcFindApcTable
- 0x1001a4f9 0x1b _L1_DrvRfcApcGainCheck
- 0x1001a514 0x21 _L1_DrvRfcApcFreCmpIdxGet
- 0x1001a535 0x21 _L1_DrvRfcAgcFreCmpIdxGet
- 0x1001a556 0x29 _L1_DrvRfcApcCtrl
- 0x1001a57f 0x4e _L1_DrvRfcAgcNvTableCheck
- 0x1001a5cd 0x18 _L1_DrvRfcAgcGainCheck
- 0x1001a5e5 0xb2 _L1_DrvRfcCfgAgc
- 0x1001a697 0x19 _L1_DrvRfcIdleToRxUnSyncEnable
- 0x1001a6b0 0x1b _L1_DrvRfcRxToRxUnSyncEnable
- 0x1001a6cb 0x12 _L1_DrvRfcQKUnSyncEnable
- 0x1001a6dd 0xbb _L1_DrvRfcNormalUnSynRamInit
- 0x1001a798 0xef _L1_DrvRfcNormalSynRamInit
- 0x1001a887 0x13 _L1_DrvRfcRdbRamEnable
- 0x1001a89a 0x6d _L1_DrvRfcRdbUnSynRamInit
- 0x1001a907 0x2 _L1_DrvRfcRdbRamInit
- 0x1001a909 0x88 _L1_DrvRfcIdleToTx
- 0x1001a991 0x59 _L1_DrvRfcTxToIdle
- 0x1001a9ea 0x8c _L1_DrvRfcIdleToRx
- 0x1001aa76 0x49 _L1_DrvRfcRxToIdle
- 0x1001aabf 0x54 _L1_DrvRfcTxToTx
- 0x1001ab13 0x6f _L1_DrvRfcRxToRx
- 0x1001ab82 0x1 _L1_DrvRfcRxToTx
- 0x1001ab83 0x8a _L1_DrvRfcT3R4
- 0x1001ac0d 0x60 _L1_DrvRfcSlotEventCtrl
- 0x1001ac6d 0x32 _L1_DrvRfcRfBandData
- 0x1001ac9f 0x63 _L1_DrvRfcRfCloseRx
- 0x1001ad02 0x88 _L1_DrvRfcRfCloseTx
- 0x1001ad8a 0x3b _L1_DrvRfcTxSlotTadvAdj
- 0x1001adc5 0xdf _L1_DrvRfcMainRegRdBack
- 0x1001aea4 0x1 _L1_DrvRfcAllRegRdBack
- 0x1001aea5 0x19 _L1_DrvRfcSpiReadData
- 0x1001aebe 0x3c _L1_DrvRfcReadTmpEventSet
- 0x1001aefa 0x1 _L1_DrvRfcReadRegEventSet
- 0x1001aefb 0x99 _L1_DrvRfcRdbEventCfg
- 0x1001af94 0x25 _L1_DrvRfcRegRead
- 0x1001afb9 0x81 _L1_DrvRfcAmtTxInit
- 0x1001b03a 0x49 _L1_DrvRfcRfIdle
- 0x1001b083 0x32 _L1_DrvRfcAmtAfcCtrl
- 0x1001b0b5 0x46 _L1_DrvRfcAfcCfg
- 0x1001b0fb 0xa _L1_DrvRfcTmpRbCfg
- 0x1001b105 0x42 _L1_DrvRfcApcCfg
- 0x1001b147 0x41 _L1_DrvRfcApcDcocCfg
- 0x1001b188 0x13 _L1_DrvRfcGetApcCtrlWord
- 0x1001b19b 0x2b _L1_DrvRfcAgcDataGet
- 0x1001b1c6 0x36 _L1_DrvRfcFdtApcSet
- .text 0x1001b1fc 0x114 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rdb.o)
- 0x1001b1fc 0x20 _L1_DrvRdbReset
- 0x1001b21c 0x52 _L1_StartRdbNoneTimingWrite
- 0x1001b26e 0x3b _L1_RdbReadCsr
- 0x1001b2a9 0x22 _L1_RdbStop
- 0x1001b2cb 0x1e _L1_RdbStopRead
- 0x1001b2e9 0x12 _L1_DrvRdbInterEnCtrl
- 0x1001b2fb 0x15 _L1_DrvRdbZspView
- .text 0x1001b310 0x14c T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_top.o)
- 0x1001b310 0x20 _L1td_DrvMcuIntMask
- 0x1001b330 0x20 _L1td_DrvMcuIntUnmask
- 0x1001b350 0x9 _L1td_DrvMcuIntIreqClr
- 0x1001b359 0x47 _L1td_DrvTopIntMask
- 0x1001b3a0 0x3d _L1td_DrvTopIntMaskRestore
- 0x1001b3dd 0x13 _L1td_DrvTopIntClr
- 0x1001b3f0 0x44 _L1td_DrvTopSaveReg
- 0x1001b434 0x28 _L1td_DrvTopRestorReg
- .text 0x1001b45c 0xe4 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_afc.o)
- 0x1001b45c 0x3e _L1_DrvAfcReset
- 0x1001b49a 0x1c _L1_DrvAfcCellIqReadResult
- 0x1001b4b6 0x5d _L1_DrvAfcCellFigParaCfg
- 0x1001b513 0x11 _L1_DrvAfcSetHwParaCfg
- 0x1001b524 0xe _L1_DrvAfcInterStart
- 0x1001b532 0xe _L1_DrvAfcInterStop
- .text 0x1001b540 0x41c T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_hsdpa.o)
- 0x1001b540 0xa _L1_DrvHsdpaOpenHdtrInt
- 0x1001b54a 0x2c _L1_DrvHsdpaHdtrTurboOpen
- 0x1001b576 0x16 _L1_DrvHsdpaHdtrTurboClose
- 0x1001b58c 0x1c _L1_DrvHsdpaHdtrTurboReset
- 0x1001b5a8 0xa _L1_DrvHsdpaMaskHdtrInt
- 0x1001b5b2 0x20 _L1_DrvHsdpaHdtrReset
- 0x1001b5d2 0x86 _L1_DrvHsdpaHdtrFrmSlotConfig
- 0x1001b658 0xa _L1_DrvHsdpaHdtrFrmSlotClear
- 0x1001b662 0x44 _L1_DrvHsdpaHdtrHarqAddrConfig
- 0x1001b6a6 0x1a0 _L1_DrvHsdpaHdtrDecodeConfig
- 0x1001b846 0x25 _L1_DrvHsdpaHdtrGetCrcResult
- 0x1001b86b 0x47 _L1_DrvHsdpaHdtrGetCqiInfo
- 0x1001b8b2 0xaa _L1_DrvHsdpaRegRead
- .text 0x1001b95c 0x1264 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_main.o)
- 0x1001b95c 0x2b _L1_SEND_RST_REQ
- 0x1001b987 0x2b _L1_SEND_INIT_REQ
- 0x1001b9b2 0x44 _L1_SEND_LOG_FILTER_REQ
- 0x1001b9f6 0x42 _L1_SEND_LOG_CHANNEL_REQ
- 0x1001ba38 0x57 _L1_SEND_LOG_TDPHY_DEBUG_REQ
- 0x1001ba8f 0x14e _L1S_Reset
- 0x1001bbdd 0x12c _L1S_Init
- 0x1001bd09 0xa3 _L1S_TD_Release
- 0x1001bdac 0x2c _L1sAmtRxRel
- 0x1001bdd8 0x106 _L1S_PSCommonMsgCtrl
- 0x1001bede 0x247 _L1_PsToPhyMsgEngDisplay
- 0x1001c125 0x1ed _L1_PhyToPsMsgEngDisplay
- 0x1001c312 0xef _L1S_ReadPSMsg
- 0x1001c401 0x1b _L1S_InnerCmd
- 0x1001c41c 0x1f _L1S_ProcSend2PS
- 0x1001c43b 0x1e _L1S_ProcAftSchedHandler
- 0x1001c459 0x1e0 _L1S_RfDevCtrl
- 0x1001c639 0x5c _L1S_DlsDevCtrl
- 0x1001c695 0x11 _L1S_CommonDevCtrl
- 0x1001c6a6 0x76 _L1S_ReadPsData
- 0x1001c71c 0x75 _L1S_AmtNstReadPsData
- 0x1001c791 0xe3 _L1S_SubFrameInt
- 0x1001c874 0x104 _L1S_DevResultProc
- 0x1001c978 0x248 _L1_SchedMainTask
- .text 0x1001cbc0 0x68a T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_sync.o)
- 0x1001cbc0 0x73 _L1_SerCellTimeFrmMeas
- 0x1001cc33 0x19 _L1_SetOtdOriCellInfo
- 0x1001cc4c 0xd0 _L1_GetCellTimingInfo
- 0x1001cd1c 0xad _L1_GetCellAfcValue
- 0x1001cdc9 0x8a _L1_SetCellTimingInfo
- 0x1001ce53 0x45 _L1_SetSysAfcValue
- 0x1001ce98 0x13 _L1_ResetSysSynDb
- 0x1001ceab 0x22 _L1_ClearUNconfInfo
- 0x1001cecd 0x161 _L1_UpdateSysSyncState
- 0x1001d02e 0x14a _L1_UpdateSysSyncInfo
- 0x1001d178 0x64 _L1_GetCellUnSyncPeriod
- 0x1001d1dc 0x7 _L1_GetSysSyncState
- 0x1001d1e3 0x7 _L1_GetUnConfSysSyncState
- 0x1001d1ea 0x58 _L1_GetCellOtdValue
- 0x1001d242 0x8 _L1_SetSysUnconfsyncState
- .text 0x1001d24a 0x2b69 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_meas_db.o)
- 0x1001d24a 0x1e _L1_SchedMeasProcAllCellCmp
- 0x1001d268 0x16 _L1_SchedMeasProcDbFreqSearch
- 0x1001d27e 0x19 _L1_SchedMeasProcSchedFreqSearch
- 0x1001d297 0x1d _L1_SchedMeasProcResetSync
- 0x1001d2b4 0x9a _L1_SchedMeasProcIntraDetCell
- 0x1001d34e 0x25 _L1_SchedMeasProcUpdateDeteDb
- 0x1001d373 0x12f _L1_SchedMeasGetDchIntraCell
- 0x1001d4a2 0xd _L1_SchedMeasDbReset
- 0x1001d4af 0x18 _L1_SchedMeasProcSetHighPriReq
- 0x1001d4c7 0x49 _L1_SchedMeasProcGetHighPriReq
- 0x1001d510 0xe _L1_SchedMeasProcSetHighTime
- 0x1001d51e 0x33 _L1_SchedMeasProcRscpLinerFilter
- 0x1001d551 0x9c _L1_SchedMeasProcSetHighResult
- 0x1001d5ed 0x1c _L1_SchedMeasProcGetHighResult
- 0x1001d609 0x56 _L1_SchedMeasProcIntraIscpNeed
- 0x1001d65f 0x3f _L1_SchedMeasProcInterIscpNeed
- 0x1001d69e 0x98 _L1_SchedMeasProcDelDbListByFreq
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- 0x10027425 0x30 _L1_SchedHsupaEagchDrxIsActive
- 0x10027455 0x51 _L1_SchedHsupaUlSyncInd
- 0x100274a6 0x1b _L1_SchedHsupaIsActive
- 0x100274c1 0xd _L1_SchedHsupaFachIsActive
- 0x100274ce 0x66f _L1_SchedHsupaPlusIsActive
- 0x10027b3d 0x39 _L1_SchedHsupaErucchSend2PS
- 0x10027b76 0x22 _L1_SchedHsdpaHsscchTsCmp
- 0x10027b98 0x48 _L1_SchedHsdpaSearchHsscchList
- 0x10027be0 0x45 _L1_SchedHsdpaSortHsscchList
- 0x10027c25 0x24 _L1_SchedHsdpaMcHsscchTsCmp
- 0x10027c49 0x2a2 _L1_SchedHsdpaSortMcHsscchList
- 0x10027eeb 0x2d _L1_SchedHsdpaSpsUpdate
- 0x10027f18 0x11 _L1_SchedHspaSetDrxActiveFlag
- 0x10027f29 0x14 _L1_SchedHspaEnableDrx
- 0x10027f3d 0x10a _L1_SchedHsdpaStartInactTimer
- 0x10028047 0x4c _L1_SchedHsdpaHscchChInfo
- 0x10028093 0x6e9 _L1_SchedHsdpaIsActive
- 0x1002877c 0x10 _L1_SchedHspaProcPSCmd
- 0x1002878c 0x8 _L1_SchedHspaProcSched
- 0x10028794 0x8 _L1_SchedHspaProcPreSched
- 0x1002879c 0xbf _L1_SchedHspaProcSend2PS
- 0x1002885b 0x8 _L1_SchedHspaProcInit
- 0x10028863 0x1a _L1_SchedHspaProcReset
- 0x1002887d 0xf _L1_SchedHspaResume
- 0x1002888c 0x7 _L1_SchedHsupaSetNextSubFrmMode
- 0x10028893 0x7 _L1_SchedHsupaGetNextSubFrmMode
- 0x1002889a 0xa _L1_SchedHspaGetTsBitmap
- 0x100288a4 0x67 _L1_SchedHspaErucchSfCheck
- 0x1002890b 0xdb _L1_SchedHspaGetHssichDpchTs
- 0x100289e6 0x42 _L1_SchedHsdpaPchPichInd
- 0x10028a28 0xd _L1_SchedHsdpaFachStartT321Timer
- 0x10028a35 0x328 _L1_SchedHspaPlusPSCmd
- 0x10028d5d 0x1b0 _L1_SchedHspaPlusPreSched
- 0x10028f0d 0x216 _L1_SchedHspaPlusSched
- 0x10029123 0x8f _L1_SchedHspaPlusAfterSched
- 0x100291b2 0x84 _L1_SchedHspaPlusSend2PS
- 0x10029236 0x8 _L1_SchedHspaUlSyncStateInd
- 0x1002923e 0x19 _L1_SchedHspaSetReschedInd
- 0x10029257 0x9 _L1_SchedHspaGetReschedInd
- 0x10029260 0xc _L1_SchedGetEhichResStat
- .text 0x1002926c 0x63f T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_page.o)
- 0x1002926c 0x15 _L1_SchedPageProcGetPageInfo
- 0x10029281 0x1ff _L1_SchedPageProcGetPiPos
- 0x10029480 0x1d _L1_SchedPageProcSend2PS
- 0x1002949d 0xba _L1_SchedPageReqCmdProc
- 0x10029557 0x47 _L1_SchedPageTrchCmdProc
- 0x1002959e 0x32 _L1_SchedPageRelCmdProc
- 0x100295d0 0x2e _L1_SchedPageProcPSCmd
- 0x100295fe 0x1d _L1_SchedPageProcL1Cmd
- 0x1002961b 0x5b _L1_SchedPageProcInnerReqTd
- 0x10029676 0xc _L1_SchedPageProcInnerRelTd
- 0x10029682 0x65 _L1_SchedPageProcPichResult
- 0x100296e7 0x181 _L1_SchedPageProcSched
- 0x10029868 0xc _L1_SchedPageProcReset
- 0x10029874 0x37 _L1_SchedPageProcInit
- .text 0x100298ab 0xaf6 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_dch.o)
- 0x100298ab 0x2a _L1_SchedDchProcReptInfoGet
- 0x100298d5 0x7e _L1_SchedDchProcUlSlotInfoOrder
- 0x10029953 0x22 _L1_SchedDchProcSetUlTsBitmap
- 0x10029975 0x62 _L1_SchedDchProcDlSlotInfoOrder
- 0x100299d7 0x39 _L1_SchedDchResWinCal
- 0x10029a10 0xbf _L1_ShedDchProcUlSync
- 0x10029acf 0x106 _L1_SchedDchProcUlActive
- 0x10029bd5 0x142 _L1_SchedDchProcDlActive
- 0x10029d17 0xff _L1_SchedDchUlDtxCheck
- 0x10029e16 0x168 _L1_SchedDchProcPSCmd
- 0x10029f7e 0x27f _L1_SchedDchProcSched
- 0x1002a1fd 0x60 _L1_SchedDchProcPreSchedHandler
- 0x1002a25d 0xe2 _L1_SchedDchProcSend2PS
- 0x1002a33f 0x34 _L1_SchedDchProcInit
- 0x1002a373 0xc _L1_SchedDchProcReset
- 0x1002a37f 0x8 _L1_SchedDchProcSetUlSyncInd
- 0x1002a387 0x6 _L1_SchedDchGetDlMinTti
- 0x1002a38d 0xc _L1_SchedDchGetUpShift
- 0x1002a399 0x8 _L1_SchedDchGetUlTsBitmap
- .text 0x1002a3a1 0x238 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_fach.o)
- 0x1002a3a1 0x173 _L1_SchedFachProcPSCmd
- 0x1002a514 0x73 _L1_SchedFachProcSched
- 0x1002a587 0x24 _L1_SchedFachProcSend2PS
- 0x1002a5ab 0x22 _L1_SchedFachProcInit
- 0x1002a5cd 0xc _L1_SchedFachProcReset
- .text 0x1002a5d9 0x1a3d T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_gap.o)
- 0x1002a5d9 0x16 _L1_SchedGapSetRfSegStartAndEnd
- 0x1002a5ef 0x1f _L1_SchedGapAllGsmUseRfSegUpdate
- 0x1002a60e 0x6c _L1_SchedGapProcInit
- 0x1002a67a 0x2 _L1_SchedGapProcReset
- 0x1002a67c 0x15f _L1_SchedGapProcSched
- 0x1002a7db 0x22b _L1_SchedGapProcPSCmd
- 0x1002aa06 0x19d _L1_SchedGapProcSend2PS
- 0x1002aba3 0xf6 _L1t_SchedGapTstampCalc
- 0x1002ac99 0x6a _L1t_SchedGapTstampEng
- 0x1002ad03 0x24 _L1_SchedGapGetLastRfResPos
- 0x1002ad27 0xbf _L1_SchedGapSuspendRf
- 0x1002ade6 0x43 _L1_SchedGap3SfnRfGsmUse
- 0x1002ae29 0x22 _L1_SchedGapAllTdUseRfSegUpdate
- 0x1002ae4b 0x36 _L1_SchedGapPageSetRfState
- 0x1002ae81 0x1f _L1_SchedGapGetRfTdState
- 0x1002aea0 0xb6 _L1_SchedGapQueryRptGap
- 0x1002af56 0x6 _L1_SchedGapProcGetRfFromRes
- 0x1002af5c 0x6d _L1_SchedGapProcAgeRepSlotGap
- 0x1002afc9 0x104 _L1_SchedGapProcFormatRepSlotGap
- 0x1002b0cd 0x4f _L1_SchedGapProcFormatFrameGap
- 0x1002b11c 0x41 _L1_SchedGapProcFormatRepGap
- 0x1002b15d 0x4b _L1_SchedGapProcRfInfoUpdate
- 0x1002b1a8 0x3a _L1_SchedGapGetLongGapCheck
- 0x1002b1e2 0x4d _L1_SchedGapMcsResValid
- 0x1002b22f 0x7e _L1_SchedGapQueryLongGap
- 0x1002b2ad 0xb _L1_SchedGapUpdataLongGap
- 0x1002b2b8 0x18 _L1_SchedGapSetForbidGap
- 0x1002b2d0 0xe _L1_SchedGapSearchForbid
- 0x1002b2de 0xcb _L1_SchedGapGetLongGapInfo
- 0x1002b3a9 0xe7 _L1_SchedGapAfterSched
- 0x1002b490 0x50 _L1td_SchedGapRecvDmo
- 0x1002b4e0 0x71 _L1td_SchedGapDmoResReq
- 0x1002b551 0xb0 _L1td_SchedGapDmoProc
- 0x1002b601 0x31 _L1_SchedGapInitRDB_LEN
- 0x1002b632 0x30 _L1_SchedGapCtrRDBClose
- 0x1002b662 0x17 _L1_SchedGapAbortGapCnf
- 0x1002b679 0x24 _L1_SchedGapMsgRebuild
- 0x1002b69d 0x71 _L1_SchedGapGetRfBitmap
- 0x1002b70e 0x79 _L1_SchedGapIratGapPos
- 0x1002b787 0x6c _L1_SchedGapToutSendMsgToL1S
- 0x1002b7f3 0x46 _L1_SchedGapGetIsCsMeasResReq
- 0x1002b839 0x85 _L1_SchedGapSetRDBOpenMsg
- 0x1002b8be 0x54 _L1_SchedGapCheckCurGapLenth
- 0x1002b912 0xb3 _L1_SchedGapACPSendRDBOpenTime
- 0x1002b9c5 0x8 _L1_SchedGapSetGSMGapInfo
- 0x1002b9cd 0x22 _L1_SchedGapTHSaveToutSig
- 0x1002b9ef 0x12 _L1_SchedGapSaveToutSig
- 0x1002ba01 0x55 _L1_SchedGapGetToutSig
- 0x1002ba56 0x1ba _L1_SchedGapToutHandle
- 0x1002bc10 0xa _L1_SchedGapProcGetGapType
- 0x1002bc1a 0x8 _L1_SchedGapGetIratGapType
- 0x1002bc22 0x5f _L1_SchedGapResSet
- 0x1002bc81 0x36 _L1_SchedGapTdSlaveOpenRDBPEvt
- 0x1002bcb7 0x60 _L1_SchedGapOpenRdb
- 0x1002bd17 0x3 _L1_SchedGapCloseRdb
- 0x1002bd1a 0xa4 _L1_SchedGapSendRdbMsg
- 0x1002bdbe 0x3d _L1_SchedGapAddChipEvent
- 0x1002bdfb 0x24 _L1_SchedGapGetRdbTime
- 0x1002be1f 0xc _L1_SchedGapGetRdbStatus
- 0x1002be2b 0x24 _L1_SchedGapCloseRf
- 0x1002be4f 0x3e _L1_SchedGapIsRfNeedSleep
- 0x1002be8d 0x7b _L1_SchedGapRfSleep
- 0x1002bf08 0xf _L1_SchedGapTdRelCloseRf
- 0x1002bf17 0x9 _L1_SchedGapResetRdbRtStartChip
- 0x1002bf20 0x1c _L1_SchedGapIdleStatGapReport
- 0x1002bf3c 0x3c _L1_SchedGapRdbStartAdjust
- 0x1002bf78 0x8 _L1_SchedGapIsBetweenAbtReqCnf
- 0x1002bf80 0x3d _L1_SchedGapRfResumeRes
- 0x1002bfbd 0x9 _L1_SchedGapSetGapChangeFlag
- 0x1002bfc6 0x9 _L1_SchedGapClrGapChangeFlag
- 0x1002bfcf 0x8 _L1_SchedGapGetGapChangeFlag
- 0x1002bfd7 0xe _L1_SchedGapSetSleepGapCheckFlag
- 0x1002bfe5 0x31 _L1_SchedGapForSlaveLpUpdateRf
- .text 0x1002c016 0x156 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_fmo.o)
- 0x1002c016 0x31 _L1_SchedFmoProcCalcFmoStartTick
- 0x1002c047 0x24 _L1_SchedFmoProcInit
- 0x1002c06b 0xf _L1_SchedFmoProcReset
- 0x1002c07a 0x8a _L1_SchedFmoProcPSCmd
- 0x1002c104 0x68 _L1_SchedFmoProcSched
- .text 0x1002c16c 0xc40 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_fs.o)
- 0x1002c3a5 0x8 _L1_SchedFSProcInit
- 0x1002c3ad 0x33b _L1_SchedFSProcPSCmd
- 0x1002c6e8 0x82 _L1_SchedFSProcSchedReady
- 0x1002c76a 0x35 _L1_SchedFSProcSchedWorkInit
- 0x1002c79f 0x65 _L1_SchedFSProcSchedDwSrch
- 0x1002c804 0xe _L1_SchedFSProcSchedAdjustTpu
- 0x1002c812 0x139 _L1_SchedFSProcSchedSetFreqPoint
- 0x1002c94b 0xd9 _L1_SchedFSProcSchedCalcRssi
- 0x1002ca24 0x63 _L1_SchedFSProcSched
- 0x1002ca87 0x25 _L1_SchedFSProcPreSchedWorkInit
- 0x1002caac 0x110 _L1_SchedFSProcPreSchedDwInd
- 0x1002cbbc 0xe _L1_SchedFSProcPreSchedAdjustTpu
- 0x1002cbca 0x44 _L1_SchedFSProcPreSchedHandler
- 0x1002cc0e 0x4f _L1_SchedFSProcSendAbortCnfMsg
- 0x1002cc5d 0xc5 _L1_SchedFSProcSendIndMsg
- 0x1002cd22 0x6a _L1_SchedFSProcSendAbormalIndMsg
- 0x1002cd8c 0x20 _L1_SchedFSProcSend2PS
- .text 0x1002cdac 0x47c T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_math.o)
- 0x1002cdac 0x7e _L1_MathWord2Float
- 0x1002ce2a 0x82 _L1_MathDword2Float
- 0x1002ceac 0x2a _L1_MathFloatDiv
- 0x1002ced6 0x27 _L1_MathDivEx
- 0x1002cefd 0x34 _L1_MathFloatAdd
- 0x1002cf31 0x5c _L1_MathFloatSub
- 0x1002cf8d 0x2e _L1_MathFloatMul
- 0x1002cfbb 0x12 _L1_MathFloatCmp
- 0x1002cfcd 0xaf _L1_MathLog
- 0x1002d07c 0x187 _L1_MathQuickSort
- 0x1002d203 0x11 _L1_BitReverse
- 0x1002d214 0xa _L1_GetNonZeroBitNum
- 0x1002d21e 0x3 _L1_MathRxSlotId2Index
- 0x1002d221 0x7 _memset_16bit
- .text 0x1002d228 0x18a T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_td_dbg.o)
- 0x1002d228 0x47 _L1_AtDebugInfoRead
- 0x1002d26f 0x13 _L1_AtDebugInfoWrite
- 0x1002d282 0x14 _L1_CmnAtDebugInfoHandler
- 0x1002d296 0x1e _L1_AtDebugInfoHandler
- 0x1002d2b4 0xfe _ose_assert
- .text 0x1002d3b2 0x1b12 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rtx_tx.o)
- 0x1002d3b2 0x5e _L1_DevRtxTxRecMsgProc
- 0x1002d410 0xf _L1_DevRtxTxReset
- 0x1002d41f 0x1b _L1_DevRtxTxInit
- 0x1002d43a 0x2e _L1_DevRtxTxRevUlResetReq
- 0x1002d468 0xce _L1_DevRtxTxRevUpCfgReq
- 0x1002d536 0x5e _L1_DevRtxTxRevDchCfgReq
- 0x1002d594 0x16 _L1_DevRtxTxGetMaxTti
- 0x1002d5aa 0x98 _L1_DevRtxTxRevSichCfgReq
- 0x1002d642 0x18 _L1_DevRtxTxRevAbortRaReq
- 0x1002d65a 0x35 _L1_DevRtxTxRevFpachTtiInt
- 0x1002d68f 0x26 _L1_DevRtxTxTs1IntHandle
- 0x1002d6b5 0xae _L1_DevRtxTxTs6IntHandle
- 0x1002d763 0x71 _L1_DevRtxTxSavePcParaForUppch
- 0x1002d7d4 0xa1 _L1_DevRtxTxSavePcParaForRach
- 0x1002d875 0x81 _L1_DevRtxTxSaveRachCfgPara
- 0x1002d8f6 0x7e _L1_DevRtxTxSaveDchCfgPara
- 0x1002d974 0x7a _L1_DevRtxTxDataHandler
- 0x1002d9ee 0x38 _L1_DevRtxTxCalcNi
- 0x1002da26 0xb8 _L1_DevRtxTxCalcNiOfActiveTrch
- 0x1002dade 0x2b _L1_DevRtxTxRmInit
- 0x1002db09 0x84 _L1_DevRtxTxRmGetNdata
- 0x1002db8d 0xf _L1_DevRtxTxSavePhyPara
- 0x1002db9c 0x43 _L1_DevRtxTxSaveRachPhyPara
- 0x1002dbdf 0x10d _L1_DevRtxTxSaveDchPhyPara
- 0x1002dcec 0x7 _L1_DevRtxTxRmDataCmp
- 0x1002dcf3 0xea _L1_DevRtxTxRmCalcDeltaN
- 0x1002dddd 0x5f _L1_DevRtxTxRmSelAlgorithm
- 0x1002de3c 0x10c _L1_DevRtxTxUncodedCovRM
- 0x1002df48 0x45 _L1_DevRtxTxTurboRm
- 0x1002df8d 0xec _L1_DevRtxTxTurboRmFirst
- 0x1002e079 0xf1 _L1_DevRtxTxTurboRmSecond
- 0x1002e16a 0x51 _L1_DevRtxTxCalcSArrayTurbo
- 0x1002e1bb 0x4c _L1_DevRtxTxCalcSArrayUncodeCov
- 0x1002e207 0x42 _L1_DevRtxTxRmCalcEpara
- 0x1002e249 0x28 _L1_DevRtxTxRmGCD
- 0x1002e271 0x31 _L1_DevRtxTxRmGetSIndex
- 0x1002e2a2 0x43 _L1_DevRtxTxRmCalcZi
- 0x1002e2e5 0x3b _L1_DevRtxTxMidShift
- 0x1002e320 0x7b _L1_DevRtxTxRelRach
- 0x1002e39b 0x42 _L1_DevRtxTxRelDch
- 0x1002e3dd 0x113 _L1_DevRtxTxRachHandle
- 0x1002e4f0 0xf6 _L1_DevRtxTxRachCfg
- 0x1002e5e6 0x108 _L1_DevRtxTxDchIntHandle
- 0x1002e6ee 0x74 _L1_DevRtxTxWithData
- 0x1002e762 0x28 _L1_DevRtxTxNonData
- 0x1002e78a 0x6f _L1_DevRtxTxSetDchparaForPc
- 0x1002e7f9 0xf0 _L1_DevRtxTxDchDataSend
- 0x1002e8e9 0x8f _L1_DevRtxTxDchSbSend
- 0x1002e978 0x116 _L1_DevRtxTxDchCfg
- 0x1002ea8e 0x78 _L1_DevRtxTxHssichHandle
- 0x1002eb06 0x28 _L1_DevRtxTxFpachRel
- 0x1002eb2e 0x70 _L1_DevRtxTxFpachAckHandle
- 0x1002eb9e 0x13 _L1_DevRtxTxFpachNackHandle
- 0x1002ebb1 0x2a _L1_DevRtxTxSsTpcHandle
- 0x1002ebdb 0x80 _L1_DevRtxTxPrachIntHandle
- 0x1002ec5b 0x43 _L1_DevRtxTxUppchIntHandle
- 0x1002ec9e 0x92 _L1_DevRtxTxHssichIntHandle
- 0x1002ed30 0xae _L1_DevRtxTxRmStaticSf
- 0x1002edde 0xbf _L1_DevRtxTxRmDynamicSf
- 0x1002ee9d 0x27 _L1_DevRtxTxGetErucchTti
- .text 0x1002eec4 0x120e T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_dst.o)
- 0x1002eec4 0x67 _L1_DevDlsDstMcsSetPara
- 0x1002ef2b 0x37 _L1_DevDlsDstReset
- 0x1002ef62 0x50 _L1_DevDlsRtxTimingTraceREQ
- 0x1002efb2 0xfc _L1_DrvDstChangeDataToBit8
- 0x1002f0ae 0xad _L1_DevDstHandleMultiFinger
- 0x1002f15b 0x6 _L1_DevDstCalFingerWinStartPos
- 0x1002f161 0x53 _L1_DevL1_DevDstReadInterfDP
- 0x1002f1b4 0x39 _L1_DevDstCalAvDP
- 0x1002f1ed 0x3d _L1_DevDstCalMulFingerTh
- 0x1002f22a 0x56 _L1_DevDstSelectMultiFinger
- 0x1002f280 0x74 _L1_DevDstGetFingerCluster
- 0x1002f2f4 0x99 _L1_DevDlsDstStartMcheSyncProc
- 0x1002f38d 0x15a _L1_DevDlsDstMcheSyncIntProc
- 0x1002f4e7 0x9e _L1_DevDlsDstStartDwPtsDlProc
- 0x1002f585 0x82 _L1_DevDlsDstOtdMeasRpt
- 0x1002f607 0x1c2 _L1_DevDlsDstDwPtsSirCal
- 0x1002f7c9 0x10 _L1_DevDlsDstDwPtsMaxPathSrch
- 0x1002f7d9 0xfe _L1_DevDlsDstDwPtsCellTimingEst
- 0x1002f8d7 0x74 _L1_DevDlsDstDwPtsDlSyncIntProc
- 0x1002f94b 0xae _L1_DevDlsDstDbUpdate
- 0x1002f9f9 0x22 _L1_DevDlsMcheReqDataProc
- 0x1002fa1b 0x51 _L1_DevDlsDstDwptsProc
- 0x1002fa6c 0x8c _L1_DevDlsDstMcheProc
- 0x1002faf8 0x39 _L1_DevDlsDstOtdProc
- 0x1002fb31 0x4f _L1_DevDlsDstMaFoeProc
- 0x1002fb80 0x23b _L1_DevDlsDstProc
- 0x1002fdbb 0xa6 _L1_DevDstOptSendTimingAdjToL1s
- 0x1002fe61 0x36 _L1_DevDstDwptsTraceReq
- 0x1002fe97 0x33 _L1_DevDstSendToAFC
- 0x1002feca 0x58 _L1_DevDstIntInd
- 0x1002ff22 0x70 _L1_DevDlsIsHeaderSfnEquToSave
- 0x1002ff92 0x20 _L1_DevDlsBaseTimeChange
- 0x1002ffb2 0xf7 _L1_DevDlsDstAreaCondition
- 0x100300a9 0x29 _L1_DevDstTs0McheReq
- .text 0x100300d2 0x118b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_csr.o)
- 0x100300d2 0x29 _L1_DevDlsCsrInit
- 0x100300fb 0x7 _L1_DevGetSlavePlmnFlg
- 0x10030102 0x7 _L1_DevSetSlavePlmnFlg
- 0x10030109 0x48 _L1_DevDlsStartDwPosSrchReq
- 0x10030151 0x80 _L1_DevDlsStartSyncIdSrchReq
- 0x100301d1 0x80 _L1_DevDlsStartMidSrchReq
- 0x10030251 0x44 _L1_DevDlsCsrEngCfg
- 0x10030295 0x5 _L1_DevCsrSetTimeBase
- 0x1003029a 0x5 _L1_DevCsrGetTimeBase
- 0x1003029f 0x2d _L1_DevCsrReciprocal
- 0x100302cc 0xa _L1_DevCsrFindMaxEng
- 0x100302d6 0x8e _L1_DevDlsCsrEngIntProc
- 0x10030364 0x45 _L1_DevCsrCalcP0m
- 0x100303a9 0x20 _L1_DevCsrCalcP1m
- 0x100303c9 0x7e _L1_DevCsrCalcP2m
- 0x10030447 0x19 _L1_DevCsrCalcP3m
- 0x10030460 0xa0 _L1_DevCsrCalcRm
- 0x10030500 0x4f _L1_DevCsrIdentifyRm
- 0x1003054f 0x3e _L1_DevCsrIsPeak
- 0x1003058d 0x30 _L1_DevCsrCalcRmThresh
- 0x100305bd 0x54 _L1_DevCsrSelectSortRm
- 0x10030611 0x4f _L1_DevCsrSelPosTable
- 0x10030660 0x84 _L1_DevCsrSelPosTableCombine
- 0x100306e4 0x1f _L1_DevCsrIsSameEngPos
- 0x10030703 0x88 _L1_DevCsrSelectEngPos
- 0x1003078b 0xf8 _L1_DevCsrDoEngResult
- 0x10030883 0x5b _L1_DevDlsCsrSyncidCfg
- 0x100308de 0x83 _L1_DevDlsCsrSyncIntProc
- 0x10030961 0x53 _L1_DevCsrSyncM1TblCombine
- 0x100309b4 0x56 _L1_DevCsrSyncM1TblCombineInsert
- 0x10030a0a 0x91 _L1_DevCsrSyncM1SelCandidate
- 0x10030a9b 0x8e _L1_DevCsrSyncM1FiltrateTH
- 0x10030b29 0x6a _L1_DevCsrSyncM1CalTH
- 0x10030b93 0x111 _L1_DevCsrSyncM1Sel8Pos
- 0x10030ca4 0x3b _L1_DevCsrDoSync1Result
- 0x10030cdf 0x96 _L1_DevDlsCsrMidCfg
- 0x10030d75 0xd4 _L1_DevCsrSyncM1Sort8Pos
- 0x10030e49 0x3f _L1_DevCsrMidSelSync
- 0x10030e88 0x91 _L1_DevDlsCsrMidIntProc
- 0x10030f19 0x110 _L1_DevCsrMidSelCandidate
- 0x10031029 0x64 _L1_DevCsrMidSelCandidateSort
- 0x1003108d 0x28 _L1_DevCsrNoiThFiltrate
- 0x100310b5 0x4f _L1_DevCsrMidFiltrateTH
- 0x10031104 0x4a _L1_DevCsrCalMidTH
- 0x1003114e 0x5f _L1_DevCsrSetMidResult
- 0x100311ad 0x60 _L1_DevCsrDoSearchResult
- 0x1003120d 0x2a _L1_DevCsrDoSearchFailResult
- 0x10031237 0x26 _L1_DevCsrIntInd
- .text 0x1003125d 0xd11 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_dpch.o)
- 0x1003125d 0x2e _L1_DevPcUlDpchPwrCalc
- 0x1003128b 0x4e _L1_DevPcGetTxPower
- 0x100312d9 0x7e _L1_DevPcDlDpchTrchSequ
- 0x10031357 0x96 _L1_DevPcDlDpchTpcSsCfg
- 0x100313ed 0xa8 _L1_DevPcDlDpchOlpcInit
- 0x10031495 0x47 _L1_DevPcDlDpchDlpcInit
- 0x100314dc 0x109 _L1_DevPcUlDpchInit
- 0x100315e5 0xbb _L1_DevPcUlDpchCfg
- 0x100316a0 0x89 _L1_DevPcDlDpchCfg
- 0x10031729 0x20 _L1_DevPcUlDpchRst
- 0x10031749 0x5 _L1_DevPcDlDpchRst
- 0x1003174e 0x17 _L1_DevPcDpchCfg
- 0x10031765 0x8 _L1_DevPcDpchRst
- 0x1003176d 0x39 _L1_DevPcDpchMapFunc
- 0x100317a6 0x27 _L1_DevPcDlDpchSyncPro
- 0x100317cd 0x58 _L1_DevPcDlDpchDataOlpc
- 0x10031825 0x41 _L1_DevPcDlDpchOuterAdj
- 0x10031866 0xb7 _L1_DevPcDlDpchOuterPro
- 0x1003191d 0x54 _L1_DevPcDlDpchGetDlTpc
- 0x10031971 0x4a _L1_DevPcDlDpchInnerPro
- 0x100319bb 0x30 _L1_DevPcDlDpchNonTrustUlCmd
- 0x100319eb 0xe4 _L1_DevPcDlDpchGetSlotUlCmd
- 0x10031acf 0x8b _L1_DevPcDlDpchGetUlCmd
- 0x10031b5a 0x3b _L1_DevPcUlDpchMapDlTpc
- 0x10031b95 0x80 _L1_DevPcUlDpchSetDlTpc
- 0x10031c15 0x86 _L1_DevPcUlDpchMapUlTpc
- 0x10031c9b 0x50 _L1_DevPcUlDpchParseUlCmd
- 0x10031ceb 0x99 _L1_DevPcUlDpchCloseLoopPwr
- 0x10031d84 0x38 _L1_DevPcDlDpchCloseLoopPro
- 0x10031dbc 0x56 _L1_DevPcUlDpchCloseLoopPro
- 0x10031e12 0x59 _L1_DevPcDpchCloseLoopPro
- 0x10031e6b 0xf7 _L1_DevPcUlDpchPro
- 0x10031f62 0xc _L1_DevPcSetUlDpchPwr
- .text 0x10031f6e 0x505 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_hsdpa.o)
- 0x10031f6e 0xe _L1_DevPcHsdpaTpcSsMerge
- 0x10031f7c 0x64 _L1_DevPcDschTpcSsCalcMerge
- 0x10031fe0 0xa _L1_DevPcTpcCmd2Symbol
- 0x10031fea 0x52 _L1_DevPcHssichInit
- 0x1003203c 0x47 _L1_DevPcHsscchClsInit
- 0x10032083 0x55 _L1_DevPcHsscchOuterInit
- 0x100320d8 0x65 _L1_DevPcHsdpaInit
- 0x1003213d 0x5 _L1_DevPcHsdpaRst
- 0x10032142 0x5a _L1_DevPcHsscchClsPro
- 0x1003219c 0x5a _L1_DevPcHsscchOuterPro
- 0x100321f6 0x71 _L1_DevPcGetHssichTpcSsCmd
- 0x10032267 0x5e _L1_DevPcHssichCloseLoopPro
- 0x100322c5 0x2f _L1_DevPcHsdpaDownPro
- 0x100322f4 0x90 _L1_DevPcHsdpaCloseLoopPro
- 0x10032384 0xde _L1_DevPcHssichPro
- 0x10032462 0x11 _L1_DevPcSetHssichPwr
- .text 0x10032473 0x2a1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_ra.o)
- 0x10032473 0xb7 _L1_DevPcUppchPwr
- 0x1003252a 0x3b _L1_DevPcUppchTiming
- 0x10032565 0xa0 _L1_DevPcPrachPwr
- 0x10032605 0x6a _L1_DevPcUppchPro
- 0x1003266f 0x59 _L1_DevPcPrachPro
- 0x100326c8 0x2b _L1_DevPcGetUppchPwr
- 0x100326f3 0x21 _L1_DevPcGetPrachPwr
- .text 0x10032714 0x79b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_utr.o)
- 0x10032714 0x43 _L1_DrvUtrReset
- 0x10032757 0xc _L1_DrvUtrInit
- 0x10032763 0xf6 _L1_DrvUtrDchConfig
- 0x10032859 0x60 _L1_DrvUtrRachConfig
- 0x100328b9 0xe _L1_DrvUtrEnable
- 0x100328c7 0x1c _L1_DrvUtrClose
- 0x100328e3 0x8a _L1_DrvUtrTbAndCbConfig
- 0x1003296d 0x124 _L1_DrvUtrRMConfig
- 0x10032a91 0x7 _L1_DrvUtrGetRamAddr
- 0x10032a98 0x1b _L1_DrvUtrClearRmPara
- 0x10032ab3 0xd _L1_DrvUtrRegClear
- 0x10032ac0 0xe _L1_DrvUtrGetCrcMode
- 0x10032ace 0xe _L1_DrvUtrGetCodingType
- 0x10032adc 0xe _L1_DrvUtrGetRamData
- 0x10032aea 0x9 _L1_DrvUtrGetInterlv1RamStateTd
- 0x10032af3 0x11 _L1_DrvFdtUtrCfgCleanReg
- 0x10032b04 0x3ab _L1_DrvFdtUtrCfgUlReg
- .text 0x10032eaf 0xaad T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_rach.o)
- 0x10033314 0x48 _L1_SchedRachProcPSCmd
- 0x1003335c 0x55 _L1_SchedRachProcL1Cmd
- 0x100333b1 0xcd _L1_SchedRachProcPreSchedHandler
- 0x1003347e 0x5d _L1_SchedRachProcUpSendFailCmd
- 0x100334db 0xb3 _L1_SchedRachProcIdleStCmd
- 0x1003358e 0xad _L1_SchedRachProcIRecFpachStCmd
- 0x1003363b 0x128 _L1_SchedRachProcIWaitFpachStCmd
- 0x10033763 0xe _L1_SchedRachProcISendRachStCmd
- 0x10033771 0x4d _L1_SchedRachProcSched
- 0x100337be 0x5a _L1_SchedRachProcSend2PS
- 0x10033818 0xa8 _L1_SchedRachProcL1InnerReq
- 0x100338c0 0x9 _L1_SchedRachProcL1InnerAbort
- 0x100338c9 0x10 _L1_SchedRachProcReset
- 0x100338d9 0x60 _L1_SchedRachProcInit
- 0x10033939 0xa _L1_SchedRachSetwUarFcn
- 0x10033943 0x9 _L1_SchedRachSetFachRel
- 0x1003394c 0x8 _L1_SchedRachSetUppchflg
- 0x10033954 0x8 _L1_SchedRachGetUppchflg
- .text 0x1003395c 0x92 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_common.o)
- 0x1003395c 0x4e _L1_SchedDchActiveSsfnCalc
- 0x100339aa 0x44 _L1_ShedCmnCalResWinInfo
- .text 0x100339ee 0x145 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
- 0x100339ee 0x54 _L1w_TaskPrioEng
- 0x10033a42 0xf1 _L1w_ModemDrvInit
- .text 0x10033b33 0x8e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
- 0x10033b33 0x46 _L1w_AtNvInit
- 0x10033b79 0x48 _L1w_NvDataInit
- .text 0x10033bc1 0x13d5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o)
- 0x10033bc1 0x2e _L1w_DevBchBchSchedReq
- 0x10033bef 0x2c _L1w_DevBchAfcSupplyReq
- 0x10033c1b 0x26 _L1w_DevBchAfcLockCnf
- 0x10033c41 0x2e _L1w_DevBchIntInd
- 0x10033c6f 0x3f _L1w_BchTask
- 0x10033cae 0x45 _L1w_DevBchTimeDecrease
- 0x10033cf3 0xa _L1w_DevBchClearAfcInfo
- 0x10033cfd 0x1d _L1w_DevBchPiSymbol2Float
- 0x10033d1a 0x53 _L1w_DevBchPiReset
- 0x10033d6d 0x3e _L1w_DevBchReset
- 0x10033dab 0x35 _L1w_DevBchInit
- 0x10033de0 0x1f _L1w_DevBchTpuIntHandle
- 0x10033dff 0x82 _L1w_DevBchPichSched
- 0x10033e81 0x222 _L1w_DevBchPichRxCfg
- 0x100340a3 0x97 _L1w_DevBchBchSched
- 0x1003413a 0x1b4 _L1w_DevBchBchRxCfg
- 0x100342ee 0xa8 _L1w_DevBchAfcSupply
- 0x10034396 0xca _L1w_DevBchCpichRxCfg
- 0x10034460 0x23 _L1w_DevBchAfcLockHandle
- 0x10034483 0x57 _L1w_DevBchPichIntHandle
- 0x100344da 0xf8 _L1w_DevBchBchIntHandle
- 0x100345d2 0x80 _L1w_DevBchCpichIntHandle
- 0x10034652 0x24 _L1w_DevBchTimeConflict
- 0x10034676 0x56 _L1w_DevBchCalcFingerAdj
- 0x100346cc 0x32 _L1w_DevBchCalcFingerBound
- 0x100346fe 0x6c _L1w_DevBchAddTpuEvent
- 0x1003476a 0x7e _L1w_DevBchBchAfcProc
- 0x100347e8 0x54 _L1w_DevBchPichAfcProc
- 0x1003483c 0x14d _L1w_DevBchAdjustFinger
- 0x10034989 0x2d _L1w_DevBchCpichIntMask
- 0x100349b6 0x16 _L1w_DevBchClearAfcData
- 0x100349cc 0xf _L1w_DevBchReadSfnResult
- 0x100349db 0x5c _L1w_DevBchFindBchRxCfgBuf
- 0x10034a37 0x5c _L1w_DevBchRtCfgTimeValid
- 0x10034a93 0x49 _L1w_DevBchPichIntPostProc
- 0x10034adc 0x15 _L1w_DevBchCalcFingerDist
- 0x10034af1 0xc7 _L1w_DevBchSigProc
- 0x10034bb8 0x3a _L1w_DevBchCalcChipDist
- 0x10034bf2 0x25 _L1w_DevBchStopBchDecode
- 0x10034c17 0x7b _L1w_DevBchSetIQRotate
- 0x10034c92 0x26 _L1w_DevBchNCellAfcFeedback
- 0x10034cb8 0x60 _L1w_DevBchCaclRtSfnOffset
- 0x10034d18 0xcf _L1w_DevBchFingerManage
- 0x10034de7 0x42 _L1w_DevBchFingerUpdate
- 0x10034e29 0x21 _L1w_DevBchStopBchDecodeReq
- 0x10034e4a 0xe6 _L1w_DevBchPiaiAfcHandle
- 0x10034f30 0x66 _L1w_DevBchFilterFinger
- .text 0x10034f96 0x2301 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
- 0x10034f96 0x41 _L1w_DevMeasInit
- 0x10034fd7 0x41 _L1w_DevMeasReset
- 0x10035018 0xd _L1w_DevMeasJudgeBufStateFull
- 0x10035025 0xe _L1w_DevMeasJudgeBufState
- 0x10035033 0x2cc _L1w_DevMeasConfigHw
- 0x100352ff 0x40 _L1w_DevMeasCpichMeasCnf
- 0x1003533f 0x139 _L1w_DevMeasSideSupres
- 0x10035478 0x94 _L1w_DevMeasPathDetct
- 0x1003550c 0xd2 _L1w_DevMeasDeleteSttdDetctCell
- 0x100355de 0xc1 _L1w_DevMeasSttdDetct
- 0x1003569f 0x4f _L1w_DevMeasCalcFingerPeakSum
- 0x100356ee 0x5f _L1w_DevMeasCalcSearchWindowSum
- 0x1003574d 0x29 _L1w_DevMeasSortFirstFinger
- 0x10035776 0xd _L1w_DevMeasIsSearchWindowPath
- 0x10035783 0x25 _L1w_DevMeasSelNewWindow
- 0x100357a8 0xa8 _L1w_DevMeasSelWinFinInfo
- 0x10035850 0xbe _L1w_DevMeasAdrWindowUpdate
- 0x1003590e 0x104 _L1w_DevMeasTimeAdjust
- 0x10035a12 0x5f _L1w_DevMeasLOG10Cal
- 0x10035a71 0x146 _L1w_DevMeasCalRssi
- 0x10035bb7 0x17a _L1w_DevMeasSaveCnfCellInfo
- 0x10035d31 0x35 _L1w_DevMeasEcIoClaib
- 0x10035d66 0x104 _L1w_DevMeasGetRscpNew
- 0x10035e6a 0xc0 _L1w_DevMeasGetRscp
- 0x10035f2a 0x249 _L1w_DevMeasCalRscp1New
- 0x10036173 0x2dd _L1w_DevMeasCalRscp1
- 0x10036450 0xed _L1w_DevMeasPreSyncFingerCmp
- 0x1003653d 0xee _L1w_DevMeasAddPreSyncFingernew
- 0x1003662b 0x14d _L1w_DevMeasAddPreSyncFinger
- 0x10036778 0x2f _L1w_DevMeasSetPreSyncInfo
- 0x100367a7 0x4 _L1w_DevMeasPreSyncHandler
- 0x100367ab 0x134 _L1w_DevMeasRscpHandler
- 0x100368df 0x25 _L1w_DevMeasIntMissHandle
- 0x10036904 0xb2 _L1w_DevMeasGetTpuEvtTim
- 0x100369b6 0x50 _L1w_DevMeasSetAbnormalIntInfo
- 0x10036a06 0x1b6 _L1w_DevMeasReqProc
- 0x10036bbc 0x216 _L1w_DevMeasIntProc
- 0x10036dd2 0x62 _L1w_DevMeasTpuHandler
- 0x10036e34 0x48 _L1w_DevMeasIntInd
- 0x10036e7c 0x33 _L1w_DevMeasGetPreSyncInfo
- 0x10036eaf 0xf _L1w_DevMeasCheckWorkSt
- 0x10036ebe 0xe7 _L1w_DevMeasSetAgcStartTime
- 0x10036fa5 0x3e _L1w_DevMeasAgcTrans
- 0x10036fe3 0x2d _L1w_DevMeasSetAgc
- 0x10037010 0x18 _L1w_DevMeasOfflinedataStartTime
- 0x10037028 0xc _L1w_DevMeasGetOfflinedataEndtTime
- 0x10037034 0x2d _L1w_DevMeasOfflinedataSavedReq
- 0x10037061 0xe7 _L1w_DevMeasCfgOfflineData
- 0x10037148 0x15 _L1w_DevMeasSaveAgcValue
- 0x1003715d 0x16 _L1w_DevMeasSaveAgcStartTime
- 0x10037173 0x63 _L1w_DevMeasJugeIsSaveAgcInfo
- 0x100371d6 0xe _L1w_DevMeasClearOfflineDataInfo
- 0x100371e4 0xb3 _L1w_MeasTask
- .text 0x10037297 0x2bc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
- 0x10037297 0x8 _L1w_DevHsdpaActiveFlgGet
- 0x1003729f 0x8 _L1w_DevHsdpaActiveFlgSet
- 0x100372a7 0x8 _L1w_DevHsdpaHdtrUseTurboFlgGet
- 0x100372af 0x8 _L1w_DevHsdpaHdtrUseTurboFlgSet
- 0x100372b7 0x8 _L1w_DevHsdpaGetAgcDownFlg
- 0x100372bf 0x7 _L1w_DevHspaFachSetEdchActive
- 0x100372c6 0x7 _L1w_DevHspaFachGetEdchActive
- 0x100372cd 0x18 _L1w_DevHspaFachSubFrmInt
- 0x100372e5 0x47 _L1w_DevHspaReset
- 0x1003732c 0x3e _L1w_DevHspaInit
- 0x1003736a 0x18 _L1w_DevHspaCmnMsgProc
- 0x10037382 0x3c _L1w_DevHsupaFachMsgProc
- 0x100373be 0x4a _L1w_DevHsdpaFachMsgProc
- 0x10037408 0x5e _L1w_DevHsupaMsgProc
- 0x10037466 0x83 _L1w_DevHsdpaMsgProc
- 0x100374e9 0x6a _L1w_HspaTask
- .text 0x10037553 0x951 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
- 0x10037553 0x15 _L1w_DevRtxReset
- 0x10037568 0xf _L1w_DevRtxInit
- 0x10037577 0x44 _L1w_DevRtxInitCfgMsgHandle
- 0x100375bb 0x1 _L1w_DevRtxTxRfOperate
- 0x100375bc 0x95 _L1w_DevRtxRxCfgTpuIntHandle
- 0x10037651 0xce _L1w_DevRtxTpuIntUlRfHandle
- 0x1003771f 0xfa _L1w_DevRtxTpuIntHandle
- 0x10037819 0x24 _L1w_DevRtxResetInd
- 0x1003783d 0x24 _L1w_DevRtxInitInd
- 0x10037861 0x21 _L1w_DevRtxTxPrachAbortReq
- 0x10037882 0x1 _L1w_DevRtxTxDpcchOfHspaCfgReq
- 0x10037883 0x48 _L1w_DevRtxUlRfCtrlSendReq
- 0x100378cb 0x2c _L1w_DevRtxRxFingerCfgReq
- 0x100378f7 0x32 _L1w_DevRtxRxPchCfgReq
- 0x10037929 0x21 _L1w_DevRtxRxAichRelReq
- 0x1003794a 0x31 _L1w_DevRtxRxFachCfgReq
- 0x1003797b 0x21 _L1w_DevRtxRxFachRelReq
- 0x1003799c 0x2f _L1w_DevRtxRxDlCmCfgReq
- 0x100379cb 0x21 _L1w_DevRtxRxDlCmAbortReq
- 0x100379ec 0x2d _L1w_DevRtxRxHsscchCfgReq
- 0x10037a19 0x2f _L1w_DevRtxRxEagchCfgReq
- 0x10037a48 0x21 _L1w_DevRtxRxEagchRelReq
- 0x10037a69 0x35 _L1w_DevRtxRxDrxUpdateReq
- 0x10037a9e 0x2a _L1w_DevRtxRxPlusCpichCfgReq
- 0x10037ac8 0x26 _L1w_DevRtxRxPlusCpichRelReq
- 0x10037aee 0x2e _L1w_DevRtxRxRgHiCfgReq
- 0x10037b1c 0x21 _L1w_DevRtxRxRgHiRelReq
- 0x10037b3d 0x21 _L1w_DevRtxTxTimingAdjustInd
- 0x10037b5e 0x19 _L1w_DevRtxRxTpcPilotIntInd
- 0x10037b77 0x18 _L1w_DevRtxRxHwTpcPlIntInd
- 0x10037b8f 0x2f _L1w_DevRtxRxHwPiAiIntInd
- 0x10037bbe 0x9 _L1w_DevRtxRxHwRakeIntInd
- 0x10037bc7 0x1a _L1w_DevRtxRxHwDtrIntInd
- 0x10037be1 0x22 _L1w_DevRtxRxPichIntInd
- 0x10037c03 0x22 _L1w_DevRtxRxAichIntInd
- 0x10037c25 0x102 _L1w_DevRtxRxTpcIntInd
- 0x10037d27 0x3e _L1w_DevRtxRxTpcIntReq
- 0x10037d65 0x66 _L1w_DevRtxRxPilotIntInd
- 0x10037dcb 0x21 _L1w_DevRtxRxTfciIntInd
- 0x10037dec 0x22 _L1w_DevRtxRxTtiIntInd
- 0x10037e0e 0x21 _L1w_DevRtxRxAgchFactorIntInd
- 0x10037e2f 0x1 _L1w_DevRtxErrHandle
- 0x10037e30 0x6 _L1w_DevRtxInfoGet
- 0x10037e36 0x6e _L1w_RtxTask
- .text 0x10037ea4 0x152c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
- 0x10037ea4 0x49 _L1w_DevRfcAtSetDebug
- 0x10037eed 0x5 _L1w_DevRfcGetAfcHz
- 0x10037ef2 0x1 _L1w_DevRfcRbdpRegCfg
- 0x10037ef3 0x6a _L1w_DevRfcReadMrtr
- 0x10037f5d 0x2a _L1w_DevRfSleepInfo
- 0x10037f87 0xc7 _L1w_DevRfcReset
- 0x1003804e 0x29 _L1w_DevRfcInit
- 0x10038077 0x8f _L1w_NvDataCheck
- 0x10038106 0x24 _L1w_DevRfcResetCnf
- 0x1003812a 0x24 _L1w_DevRfcInitCnf
- 0x1003814e 0x53 _L1w_DevRfcSchedOpenReq
- 0x100381a1 0x23 _L1w_DevRestoreReq
- 0x100381c4 0x2e _L1w_DevRfcIntInd
- 0x100381f2 0x34 _L1w_DevRfcDpaInfoCtrl
- 0x10038226 0x30 _L1w_DevRfcAntExchange
- 0x10038256 0x2c _L1w_DevRfcAntSel
- 0x10038282 0x5e _L1w_DevRfcDiversityCtrl
- 0x100382e0 0x35 _L1w_DevRfcChgeInfoCtrlTx
- 0x10038315 0x82 _L1w_DevRfcNotchHandle
- 0x10038397 0xfd _L1w_DevRfcChgeInfoCtrlRx
- 0x10038494 0x21 _L1W_DevRfcWaitForRfClose
- 0x100384b5 0xa6 _L1W_DevRfcSoltCtrlRfClose
- 0x1003855b 0x71 _L1w_DevRfcSlotCtrl
- 0x100385cc 0xc6 _L1w_DevRfcFdtTrigCtrl
- 0x10038692 0x56 _L1w_DevRfcFdtGetAgc
- 0x100386e8 0xbc _L1w_DevRfcFdtFreqCtrl
- 0x100387a4 0x67 _L1w_DevRfcFdtApcCwPaHighCtrl
- 0x1003880b 0x6e _L1w_DevRfcFdtApcCwPaLowCtrl
- 0x10038879 0x67 _L1w_DevRfcFdtStartCtrl
- 0x100388e0 0x91 _L1w_DevRfcNstTRXOpenCtrl
- 0x10038971 0x42 _L1w_DevRfcNstTRXCloseCtrl
- 0x100389b3 0x6a _L1w_DevRfcNstTRXFreqChge
- 0x10038a1d 0x52 _L1w_DevRfcAmtCtrl
- 0x10038a6f 0x46 _L1w_DevRfcAgcRefPowLogUpdate
- 0x10038ab5 0x29 _L1w_DevRfcIntTimeLogUpdate
- 0x10038ade 0x19 _L1w_DevRfcMrtrConfLogUpdate
- 0x10038af7 0x91 _L1w_DevRfcAgcRxStateLogUpdate
- 0x10038b88 0x8 _L1w_DevRfcTempDacToIram
- 0x10038b90 0x31 _L1w_DevRfcIntLogUpdate
- 0x10038bc1 0x25 _L1w_DevRfcIntAgcDcCalc
- 0x10038be6 0x2f _L1w_DevRfcIntNotchCfg
- 0x10038c15 0x48 _L1w_DevRfc_RpiCfg
- 0x10038c5d 0x18 _L1w_DevRfc_RpiSet
- 0x10038c75 0x56 _L1w_DevRfc_RpiPwrCtrl
- 0x10038ccb 0x5e _L1w_DevRfcIntAgcDcSet
- 0x10038d29 0x25 _L1w_DevRfcIntAfcSet
- 0x10038d4e 0x63 _L1w_DevRfcRfRegReadCtrl
- 0x10038db1 0x2b _L1w_DevRfcSleepStatusSet
- 0x10038ddc 0x6b _L1w_DevRfcIntProc
- 0x10038e47 0x45 _L1w_DevRfcSetTxBandMaxPwr
- 0x10038e8c 0x8f _L1w_DevRfcTxPowerSet
- 0x10038f1b 0x3f _L1w_DevRfcAfcHz2PPM
- 0x10038f5a 0x4d _L1w_DevRfcPpm2Hz
- 0x10038fa7 0x50 _L1w_DevRfcAfcUpdate
- 0x10038ff7 0x1c _L1w_DevRfcOpenCtrl
- 0x10039013 0x33 _L1w_DevRfcReusedReSourceRestore
- 0x10039046 0x1 _L1w_DevRfcTxTestMode
- 0x10039047 0x389 _L1w_RfcTask
- .text 0x100393d0 0x1c63 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
- 0x100393d0 0x1f _L1w_DevPcDpchReset
- 0x100393ef 0x1 _L1w_DevPcDpchInit
- 0x100393f0 0x94 _L1w_DevPcDpcchPowerFilter
- 0x10039484 0x38 _L1w_DevPcDeltaPilotPro
- 0x100394bc 0x28 _L1w_DevPcPowerItpPro
- 0x100394e4 0x1c _L1w_DevPcGapTpcJudge
- 0x10039500 0x4b _L1w_DevPcCmPowerPro
- 0x1003954b 0x60 _L1w_DevPcDpcchPowerCalc
- 0x100395ab 0x40 _L1w_DevPcDeltaPilotPowerCalc
- 0x100395eb 0x3c _L1w_DevPcDeltaResumeCalc
- 0x10039627 0x3c _L1w_DevPcRppPowerCalc
- 0x10039663 0x59 _L1w_DevPcGetDeltaPilotCalcMode
- 0x100396bc 0x2a _L1w_DevPcSigmaLastCalc
- 0x100396e6 0xe0 _L1w_DevPcAjCalc
- 0x100397c6 0x5d _L1w_DevPcFindNearBeltaC
- 0x10039823 0x6b _L1w_DevPcFindNearBeltaD
- 0x1003988e 0x47 _L1w_DevPcAjToBelta
- 0x100398d5 0x11 _L1w_DevPcDpchCurTfciBeltaCD
- 0x100398e6 0x1f5 _L1w_DevPcBeltaCBeltaDCalc
- 0x10039adb 0xf0 _L1w_DevPcBeltaCBeltaDUpdate
- 0x10039bcb 0xcc _L1w_DevPcSecCmBetalUpd
- 0x10039c97 0x18 _L1w_DlIlpc_reset
- 0x10039caf 0x8 _L1w_Olpc_reset
- 0x10039cb7 0x10 _L1w_DevPcOlpcCntReset
- 0x10039cc7 0xf _L1w_DevPcTpcGenReset
- 0x10039cd6 0xc _L1w_DevPcWindupReset
- 0x10039ce2 0x42 _L1w_DevPcDlSirCmAdjust
- 0x10039d24 0x90 _L1w_DevPcDlSirTargetCalc
- 0x10039db4 0xec _L1w_DevPcFdpchSirCal
- 0x10039ea0 0x111 _L1w_DevPcDpchSirCal
- 0x10039fb1 0x49 _L1w_DevPcDlWindUpMode
- 0x10039ffa 0x3c _L1w_DevPcSirSfAdjust
- 0x1003a036 0x95 _L1w_DevPcTpcGenDpcMode1
- 0x1003a0cb 0xd4 _L1w_DevPcDlTpcCmdGen
- 0x1003a19f 0x26 _L1w_DevFdpchRscpCalc
- 0x1003a1c5 0x37 _L1w_DevDpchParaECal
- 0x1003a1fc 0x88 _L1w_DevDpchRscpCalc
- 0x1003a284 0x9a _L1w_DevPcPilotIntInd
- 0x1003a31e 0x75 _L1w_DevPcRlsSetStaticAndSirThJudge
- 0x1003a393 0xb2 _L1w_DevPcSetTpcSoftBit
- 0x1003a445 0xc5 _L1w_DevPcTpcCombine
- 0x1003a50a 0x14 _L1w_DevPcTpcSingleRlPca1Calc
- 0x1003a51e 0x11 _L1w_DevPcTpcSingleRlPca2Calc
- 0x1003a52f 0x89 _L1w_DevPcTpcMultiRlsPca1Calc
- 0x1003a5b8 0x51 _L1w_DevPcTpcMultiRlsPca2Calc
- 0x1003a609 0x46 _L1w_DevPcTpcSingleRlCombine
- 0x1003a64f 0x4d _L1w_DevPcTpcMultiRlCombine
- 0x1003a69c 0x7e _L1w_DevPcTpcMultiRlsCombine
- 0x1003a71a 0x18 _L1w_DevPcSirReset
- 0x1003a732 0x5 _L1w_DevPcBetalSeqalCal
- 0x1003a737 0x58 _L1w_DevPcCurSlotPowCalc
- 0x1003a78f 0x1f _L1w_DevPcIsOverPwr
- 0x1003a7ae 0x2a _L1w_DevPcSerachTfci
- 0x1003a7d8 0x31 _L1w_DevPcCurSlotOverPowProc
- 0x1003a809 0x40 _L1w_DevPcMaxPowerUpdate
- 0x1003a849 0xf _L1w_DevPcUlTfcOverEstCmp
- 0x1003a858 0xe9 _L1w_DevPcUlTfcOverEstRlt
- 0x1003a941 0x22 _L1w_DevPcUphFrmAvrCalc
- 0x1003a963 0x5 _L1w_DevPcUphMapRep
- 0x1003a968 0x32 _L1w_DevPcUphResult
- 0x1003a99a 0x8 _L1w_DevPcGetUphValue
- 0x1003a9a2 0xab _L1w_DevPcUphProc
- 0x1003aa4d 0x91 _L1w_DevPcCfgInfoUpd
- 0x1003aade 0x83 _L1w_DevPcDchInfoGet
- 0x1003ab61 0x1e _L1w_DevDchOlpcBlerTargetMapping
- 0x1003ab7f 0x8f _L1w_DevPcDchOlpcThParamGet
- 0x1003ac0e 0x59 _L1w_DevPcEfachBeltacCal
- 0x1003ac67 0x104 _L1w_DevPcDchStartReqHandle
- 0x1003ad6b 0x1a _L1w_DevPcUldpchTfciInfoHandle
- 0x1003ad85 0x27 _L1w_DevPcFDpchOutLoopAdj
- 0x1003adac 0x55 _L1w_DevPcDpchOutLoopAdj
- 0x1003ae01 0x69 _L1w_DevPcDlRefTrchSel
- 0x1003ae6a 0x68 _L1w_DevPcOlpcInit
- 0x1003aed2 0x3f _L1w_DevPcDtrBlerInfoHandle
- 0x1003af11 0x14 _L1w_DevPcTpcBerCal
- 0x1003af25 0x27 _L1w_DevPcRlsTpcBerPro
- 0x1003af4c 0x7e _L1w_DevPcMutlRlsTpcBerCal
- 0x1003afca 0x33 _L1w_DevPcTpcBerCtr
- 0x1003affd 0x36 _L1w_DevPcOlpcCtrl
- .text 0x1003b033 0x1bca T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
- 0x1003b033 0x64 _L1w_DevHsdpaStartPc
- 0x1003b097 0x27 _L1w_DevHspdaHwReset
- 0x1003b0be 0x1b _L1w_DevHsdpaHwInit
- 0x1003b0d9 0xa3 _L1w_DevHsdpaReset
- 0x1003b17c 0x1 _L1w_DevHsdpaNvInit
- 0x1003b17d 0x10d _L1w_DevHsdpaParaInit
- 0x1003b28a 0x187 _L1w_DevHsdpaRegTpuEvent
- 0x1003b411 0x1ac _L1w_DevHsdpaCfgProc
- 0x1003b5bd 0x6e _L1w_DevHsdpaRelProc
- 0x1003b62b 0xc4 _L1w_DevHsdpaIcSymModProc
- 0x1003b6ef 0xa1 _L1w_DevHsdpaAdrCirIntProc
- 0x1003b790 0xeb _L1w_DevHsdpaAdrCpichIntProc
- 0x1003b87b 0x30 _L1w_DevHsdpaHsscchPart1IntProc
- 0x1003b8ab 0x4d _L1w_DevHsdpaHsscchPart2IntProc
- 0x1003b8f8 0x30 _L1w_DevHsdpaHdtrIntProc
- 0x1003b928 0x3a _L1w_DevHsdpaCfn2SfnTime
- 0x1003b962 0x37 _L1w_DevHsdpaOrderActProc
- 0x1003b999 0x152 _L1w_DevHsdpaDchTpuProc
- 0x1003baeb 0x42f _L1w_DevHsdpaTpuTraceLog
- 0x1003bf1a 0xfb _L1w_DevHsdpaIsJudgechangjing3
- 0x1003c015 0xe0 _L1w_DevHsdpaTpuProc
- 0x1003c0f5 0xb4 _L1w_DevHsdpaCompareCellInfo
- 0x1003c1a9 0x173 _L1w_DevHsdpaIsJudgePsrOver512
- 0x1003c31c 0x105 _L1w_DevHsdpaPsrOver512
- 0x1003c421 0x2a _L1w_DevHsdpaPsrFingerOldDaNew
- 0x1003c44b 0x2a _L1w_DevHsdpaPsrFingerNewXiaoOld
- 0x1003c475 0xea _L1w_DevHsdpaPsrIschangjing3
- 0x1003c55f 0x1d0 _L1w_DevHsdpaTxTpuProc
- 0x1003c72f 0x56 _L1w_DevHsdpaPsrUpdateProc
- 0x1003c785 0x3f _L1w_DevHsdpaCmUpdateProc
- 0x1003c7c4 0x4a _L1w_DevHsdpaCfgReq
- 0x1003c80e 0x29 _L1w_DevHsdpaRelReq
- 0x1003c837 0x29 _L1w_DevHsdpaIcSymModIntInd
- 0x1003c860 0x29 _L1w_DevHsdpaAdrCirIntInd
- 0x1003c889 0x29 _L1w_DevHsdpaAdrCpichIntInd
- 0x1003c8b2 0x29 _L1w_DevHsdpaHsscchPart1IntInd
- 0x1003c8db 0x29 _L1w_DevHsdpaHsscchPart2IntInd
- 0x1003c904 0x29 _L1w_DevHsdpaHdtrIntInd
- 0x1003c92d 0x3b _L1w_DevDlsHsdpaPsrUpdateReq
- 0x1003c968 0x35 _L1w_DevHsdpaCmUpdateReq
- 0x1003c99d 0x3b _L1w_DevHsdpaHsscchOrdInd
- 0x1003c9d8 0x4c _L1w_DevHsdpaFachCfgReq
- 0x1003ca24 0x26 _L1w_DevHsdpaFachRelReq
- 0x1003ca4a 0x29 _L1w_DevHsdpaFachRcvReq
- 0x1003ca73 0x26 _L1w_DevHsdpaFachHrntiUpdateReq
- 0x1003ca99 0x21 _L1w_DevHsdpaFachDataInd
- 0x1003caba 0x4b _L1w_DevHsdpaPchCfgReq
- 0x1003cb05 0x21 _L1w_DevHsdpaPchRelReq
- 0x1003cb26 0x26 _L1w_DevHsdpaRtxPiInd
- 0x1003cb4c 0x28 _L1w_DevHsdpaDmaIntInd
- 0x1003cb74 0x39 _L1w_DevHsdpaDataDmaCpy
- 0x1003cbad 0x24 _L1w_DevHsdpaCurTime2SfnTime
- 0x1003cbd1 0x2c _L1w_DevHsdpaGetCurSfnTime
- .text 0x1003cbfd 0x16ff T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
- 0x1003cbfd 0x20 _L1w_DevHsdpaLessIsAct
- 0x1003cc1d 0xa5 _L1w_DevHsdpaLessParaInit
- 0x1003ccc2 0x2f _L1w_DevHsdpaLessOrdIndProc
- 0x1003ccf1 0x33 _L1w_DevHsdpaLessTimeRcd
- 0x1003cd24 0x5f _L1w_DevHsdpaLessCfgTraceLog
- 0x1003cd83 0xc _L1w_DevHsdpaLessCfgAllTb
- 0x1003cd8f 0x23 _L1w_DevHsdpaLessFindIdleHarq
- 0x1003cdb2 0x231 _L1w_DevHsdpaPart2Type2Proc
- 0x1003cfe3 0xc5 _L1w_DevHsdpaDchLessProc
- 0x1003d0a8 0x7e _L1w_DevHsdpaPart2LessProc
- 0x1003d126 0x23 _L1w_DevHsdpaIsLessValid
- 0x1003d149 0x18 _L1w_DevHsdpaLessFindHsdschTti
- 0x1003d161 0x1c9 _L1w_DevHsdpaDchLessHdtrIntProc
- 0x1003d32a 0x24 _L1w_DevHsdpaLessHdtrIntProc
- 0x1003d34e 0x6b _L1w_DevHsdpaPchSaveAdrInitCfg
- 0x1003d3b9 0x51 _L1w_DevHsdpaPchSaveHsscchInitCfg
- 0x1003d40a 0x7d _L1w_DevHsdpaPchRxInitRcvProc
- 0x1003d487 0xae _L1w_DevHsdpaPchSaveLessPara
- 0x1003d535 0x8e _L1w_DevHsdpaPchSaveAdrSubFrmCfg
- 0x1003d5c3 0x42 _L1w_DevHsdpaPchSaveIcPsrCfg
- 0x1003d605 0x9a _L1w_DevHsdpaPchRxSubFrmProc
- 0x1003d69f 0x5f _L1w_DevHsdpaPchCfgProc
- 0x1003d6fe 0x2d _L1w_DevHsdpaPchRelProc
- 0x1003d72b 0x18 _L1w_DevHsdpaPchTpuProc
- 0x1003d743 0x62 _L1w_DevHsdpaPchSavePart1IntCfg
- 0x1003d7a5 0x66 _L1w_DevHsdpaPchPart2Type1Proc
- 0x1003d80b 0x12d _L1w_DevHsdpaPchHdtrIntProc
- 0x1003d938 0x92 _L1w_DevHsdpaPchLessProc
- 0x1003d9ca 0x16d _L1w_DevHsdpaPchLessHdtrIntProc
- 0x1003db37 0xa1 _L1w_DevHsdpaRtxPiIndProc
- 0x1003dbd8 0x71 _L1w_DevHsdpaFachStartPc
- 0x1003dc49 0x4e _L1w_DevHsdpaFachSaveHsdpcchAckCfg
- 0x1003dc97 0x5c _L1w_DevHsdpaFachSaveHsdpcchCqiCfg
- 0x1003dcf3 0x4d _L1w_DevHsdpaFachCqiSendCtrl
- 0x1003dd40 0x6e _L1w_DevHsdpaFachSaveAdrInitCfg
- 0x1003ddae 0x4a _L1w_DevHsdpaFachSaveHsscchInitCfg
- 0x1003ddf8 0x52 _L1w_DevHsdpaFachRxInitRcvProc
- 0x1003de4a 0x2e _L1w_DevHsdpaFachTxInitSendProc
- 0x1003de78 0x81 _L1w_DevHsdpaFachSaveAdrSubFrmCfg
- 0x1003def9 0x83 _L1w_DevHsdpaFachRxSubFrmProc
- 0x1003df7c 0x56 _L1w_DevHsdpaFachTxSubFrmProc
- 0x1003dfd2 0x68 _L1w_DevHsdpaFachCfgProc
- 0x1003e03a 0x44 _L1w_DevHsdpaFachRelProc
- 0x1003e07e 0x22 _L1w_DevHsdpaFachTpuProc
- 0x1003e0a0 0x2e _L1w_DevHsdpaFachSavePart1IntCfg
- 0x1003e0ce 0x131 _L1w_DevHsdpaFachHdtrIntProc
- 0x1003e1ff 0x3c _L1w_DevHsdpaFachRcvProc
- 0x1003e23b 0x28 _L1w_DevHsdpaFachHrntiUpdateProc
- 0x1003e263 0x79 _L1w_DevHsdpaFachEdchIndProc
- 0x1003e2dc 0x20 _L1w_DevHsdpaFachSetHsdpcchFlg
- .text 0x1003e2fc 0x1019 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o)
- 0x1003e2fc 0x60 _L1w_DevRtxRxFingerCfg
- 0x1003e35c 0xe2 _L1w_DevRtxRxCpichCfg
- 0x1003e43e 0x4f _L1w_DevRtxRxPichCfg
- 0x1003e48d 0x12 _L1w_DevRtxRxPichRel
- 0x1003e49f 0x50 _L1w_DevRtxRxPchCfg
- 0x1003e4ef 0x24 _L1w_DevRtxRxPchRel
- 0x1003e513 0x2f _L1w_DevRtxRxAichRakeCfg
- 0x1003e542 0x26 _L1w_DevRtxRxAichCfg
- 0x1003e568 0x5 _L1w_DevRtxRxAichRel
- 0x1003e56d 0x2e _L1w_DevRtxRxFachRakeCfg
- 0x1003e59b 0x46 _L1w_DevRtxRxFachCfg
- 0x1003e5e1 0x21 _L1w_DevRtxRxFachRel
- 0x1003e602 0xa5 _L1w_DevRtxRxDlDpchRakeCfg
- 0x1003e6a7 0x40 _L1w_DevRtxRxDlDpchCfg
- 0x1003e6e7 0x26 _L1w_DrvDpramRxWriteClearData
- 0x1003e70d 0x39 _L1w_DevRtxRxDlDpchRel
- 0x1003e746 0x16d _L1w_DevRtxRxDlCmSlotCfg
- 0x1003e8b3 0xe5 _L1w_DevRtxRxDlCmSlotRel
- 0x1003e998 0x63 _L1w_DevRtxRxDlCmCfgTpuIntHandle
- 0x1003e9fb 0x1ff _L1w_DevRtxRxDlCmCfg
- 0x1003ebfa 0x6f _L1w_DevRtxRxFdpchRakeCfg
- 0x1003ec69 0x3d _L1w_DevRtxRxFdpchCfg
- 0x1003eca6 0x5 _L1w_DevRtxRxFdpchRel
- 0x1003ecab 0x34 _L1w_DevRtxRxHsscchRakeCfg
- 0x1003ecdf 0x39 _L1w_DevRtxRxHsscchCfg
- 0x1003ed18 0x5 _L1w_DevRtxRxHsscchRel
- 0x1003ed1d 0x38 _L1w_DevRtxRxEagchRakeCfg
- 0x1003ed55 0x34 _L1w_DevRtxRxEagchCfg
- 0x1003ed89 0xf _L1w_DevRtxRxEagchRel
- 0x1003ed98 0xbc _L1w_DevRtxRxRgHiRakeCfg
- 0x1003ee54 0x4b _L1w_DevRtxRxRgHiCfg
- 0x1003ee9f 0x5 _L1w_DevRtxRxRgHiRel
- 0x1003eea4 0x6b _L1w_DevRtxRxCctrchCfgHandle
- 0x1003ef0f 0x11b _L1w_DevRtxRxCfgHandle
- 0x1003f02a 0x2f _L1w_DevRtxRxDlTpcPlCfg
- 0x1003f059 0x7e _L1w_DevRtxRxIntFingerCfg
- 0x1003f0d7 0x69 _L1w_DevRtxRxIntCfg
- 0x1003f140 0x6e _L1w_DevRtxRxDpchSlotForm
- 0x1003f1ae 0x71 _L1w_DevRtxRxSccpchSlotForm
- 0x1003f21f 0x5a _L1w_DevRtxRxComparaSlotForm
- 0x1003f279 0x34 _L1w_DevRtxRxCmASlotForm
- 0x1003f2ad 0x34 _L1w_DevRtxRxCmBSlotForm
- 0x1003f2e1 0x34 _L1w_DevRtxRxNormalSlotForm
- .text 0x1003f315 0x92c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
- 0x1003f315 0x13 _L1w_DevRtxTimeCmp
- 0x1003f328 0x2d _L1w_DevRtxUlRfcReq
- 0x1003f355 0x37 _L1w_DevRtxUlRfTblInit
- 0x1003f38c 0x2f _L1w_DevRtxUlRfGetNodeFromUnusedQ
- 0x1003f3bb 0x17 _L1w_DevRtxUlRfPutNode2UnusedQ
- 0x1003f3d2 0x31 _L1w_DevRtxUlRfQueueInsert
- 0x1003f403 0x41 _L1w_DevRtxUlRfQueueGet
- 0x1003f444 0xf _L1w_DevRtxUlRfQueueSearch
- 0x1003f453 0x67 _L1w_DevRtxUlRfStartSched
- 0x1003f4ba 0x262 _L1w_DevRtxUlRfCtrlReq
- 0x1003f71c 0x1de _L1w_DevRtxUlRfSchedPick
- 0x1003f8fa 0x81 _L1w_DevRtxUlRfSchedLink
- 0x1003f97b 0x12f _L1w_DevRtxUlRfSchedMerge
- 0x1003faaa 0x18a _L1w_DevRtxUlRfSched
- 0x1003fc34 0xd _L1w_DevRtxUlRfStopSched
- .text 0x1003fc41 0xf38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
- 0x1003fc41 0x7 _L1w_DevTxGetDchState
- 0x1003fc48 0x11 _L1w_DevTxGetRfCtrlPara
- 0x1003fc59 0x15 _L1w_DevTxDchReset
- 0x1003fc6e 0x39 _L1w_DevTxOpenRfc
- 0x1003fca7 0x39 _L1w_DevTxCloseRfc
- 0x1003fce0 0x68 _L1w_DevTxCmRfcCfg
- 0x1003fd48 0x50 _L1w_DevTxNormalSlotForm
- 0x1003fd98 0x5e _L1w_DevTxCmSlotForm
- 0x1003fdf6 0x1c _L1w_DevTxCalcCmPliot
- 0x1003fe12 0x39 _L1w_DevTxGetUlMaxMinTti
- 0x1003fe4b 0x10e _L1w_DevTxGetDchParam
- 0x1003ff59 0x75 _L1w_DevTxUlCmTfciAnalysis
- 0x1003ffce 0x29 _L1w_DevTxHsupaTransInd
- 0x1003fff7 0x16b _L1w_DevTxDchToPcStart
- 0x10040162 0x26 _L1w_DevTxDchToPcStop
- 0x10040188 0x64 _L1w_DevTxDchCmParaToPc
- 0x100401ec 0x27 _L1w_DevTxDpcchPreambleToPc
- 0x10040213 0x2a _L1w_DevTxDpdchTfciToPc
- 0x1004023d 0x177 _L1w_DevTxDataUpdate
- 0x100403b4 0x55 _L1w_DevTxGetUtrPara
- 0x10040409 0x115 _L1w_DevTxDchUtrCfg
- 0x1004051e 0x77 _L1w_DevTxDchCmProc
- 0x10040595 0x154 _L1w_DevTxDchSendCfg
- 0x100406e9 0xad _L1w_DevTxDchPreambleSendProc
- 0x10040796 0x29 _L1w_DevTxDchPostVerifyFailProc
- 0x100407bf 0x94 _L1w_DevTxDchPreambleIntHandle
- 0x10040853 0xd9 _L1w_DevTxDpchSendCndCheck
- 0x1004092c 0x59 _L1w_DevTxDpchIntHandle
- 0x10040985 0x54 _L1w_DevTxDchTpuIntHandle
- 0x100409d9 0x65 _L1w_DevTxDchRelMsgHandle
- 0x10040a3e 0x8b _L1w_DevTxCmCfgMsgHandle
- 0x10040ac9 0xb0 _L1w_DevTxDchCfgMsgHandle
- .text 0x10040b79 0x6e4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
- 0x10040b79 0xf _L1W_DevHsupaInitMacro
- 0x10040b88 0xc _L1W_DevHsupaCalCBNum
- 0x10040b94 0x21 _L1W_DevHsupaCalcCBLength
- 0x10040bb5 0xa _L1W_DevHsupaCalInterleavingRow
- 0x10040bbf 0x3a _L1W_DevHsupaCalCodeBlockConf
- 0x10040bf9 0x1c _L1w_DevHsupaCalMaxNej
- 0x10040c15 0x99 _L1W_DevHsupaCalSfOneEtfc
- 0x10040cae 0xfd _L1W_DevHsupaCalAllSFConf
- 0x10040dab 0x12a _L1W_DevHsupaCalSFConf
- 0x10040ed5 0x94 _L1W_DevHsupaCalRmRv
- 0x10040f69 0x9b _L1W_DevHsupaCalRmPara
- 0x10041004 0x41 _L1W_DevHsupaCalChannelCodeConf
- 0x10041045 0x7a _L1W_DevHsupaCalInterleavingConf
- 0x100410bf 0x37 _L1W_DevHsupaReTransBitmapTtiTen
- 0x100410f6 0x6b _L1W_DevHsupaCalEtxBitmap
- 0x10041161 0x48 _L1W_DevHsupaCalEUTRConf
- 0x100411a9 0x6e _L1W_DevHsupaCalETXConf
- 0x10041217 0x46 _L1W_DevHsupaCalULConf
- .text 0x1004125d 0x1358 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
- 0x1004125d 0xb _L1w_DevRfcCtrlDbChgeInfoSet
- 0x10041268 0xf _L1w_DevRfcCtrlDbChgeInfoInit
- 0x10041277 0x2 _L1w_DevRfcCtrlDbSlotEndSet
- 0x10041279 0x17 _L1w_DevRfcCtrlDbSlotInfoInit
- 0x10041290 0x61 _L1w_DevRfcCtrlDbInit
- 0x100412f1 0x10 _L1w_DevRfcCtrlDbInitAll
- 0x10041301 0x37 _L1w_DevRfcCtrlDbTimeContCheck
- 0x10041338 0x33 _L1w_DevRfcCtrlDbSlotChgeInfoWr
- 0x1004136b 0x16 _L1w_DevRfcCtrlDbGetDbInd
- 0x10041381 0x35 _L1w_DevRfcCtrlDbFrameChgeInfoWr
- 0x100413b6 0x2d _L1w_DevRfcCtrlDbGetSegLen
- 0x100413e3 0x9f _L1w_DevRfcCtrlDbSlotEndUpdate
- 0x10041482 0x5c _L1w_DevRfcCtrlDbCtrlInfoUpdate
- 0x100414de 0x117 _L1w_DevRfcCtrlDbSchedUpdate
- 0x100415f5 0x9c _L1w_DevRfcCtrlDbStPo2Chge
- 0x10041691 0x6d _L1w_DevRfcCtrlDbStPo1Chge
- 0x100416fe 0x93 _L1w_DevRfcCtrlDbStPi2Chge
- 0x10041791 0x27 _L1w_DevRfcCtrlDbStPi1Chge
- 0x100417b8 0x63 _L1w_DevRfcCtrlDbStPi0Chge
- 0x1004181b 0x49 _L1w_DevRfcCtrlDbStartInsert
- 0x10041864 0xeb _L1w_DevRfcCtrlDbEndPo2Chge
- 0x1004194f 0x5d _L1w_DevRfcCtrlDbEndPo1Chge
- 0x100419ac 0xf _L1w_DevRfcCtrlDbEndPo0Chge
- 0x100419bb 0x3f _L1w_DevRfcCtrlDbEndInsert
- 0x100419fa 0xf9 _L1w_DevRfcCtrlDbDrvOpenUpdate
- 0x10041af3 0xd _L1w_DevRfcCtrlDbGetAdr
- 0x10041b00 0x4a _L1w_DevRfcCtrlDbChgeInfoHandle
- 0x10041b4a 0x10e _L1w_DevRfcCtrlDbGetSlotChgeInfo
- 0x10041c58 0x39 _L1w_DevRfcAgcDbInit
- 0x10041c91 0x29 _L1w_DevRfcAfcDbInit
- 0x10041cba 0x14 _L1w_DevRfcAgcDbFreqSearch
- 0x10041cce 0xe _L1w_DevRfcAgcDbSetFreqChgeFlag
- 0x10041cdc 0x21 _L1w_DevRfcAgcDbFindOldestPos
- 0x10041cfd 0x58 _L1w_DevRfcAgcDbFindFreqPos
- 0x10041d55 0x21 _L1w_DevRfcAgcDbGetFreqInd
- 0x10041d76 0x35 _L1w_DevRfcAgcDbFastAgcCond
- 0x10041dab 0xd0 _L1w_DevRfcAgcDbAgcSet
- 0x10041e7b 0x3b _L1w_DevRfcAgcDbLockInfoUpdate
- 0x10041eb6 0x3a _L1w_DevRfcAgcCalcInfoUpdateCmn
- 0x10041ef0 0x2e _L1w_DevRfcAgcCalcInfoUpdateDpa
- 0x10041f1e 0x58 _L1w_DevRfcAgcDbAgcStepCtrl
- 0x10041f76 0x48 _L1w_DevRfcAgcDbAgcUpdate
- 0x10041fbe 0x6e _L1w_DevRfcAgcDbAgcCalcSingleCh
- 0x1004202c 0x37 _L1w_DevRfcAgcDbAfterFastAgcSet
- 0x10042063 0x38 _L1w_DevRfcAgcDbFastAgcValUpdate
- 0x1004209b 0x60 _L1w_DevRfcAgcDb2RMainChAdjCond
- 0x100420fb 0x6b _L1w_DevRfcAgcDb2RAgcHandle
- 0x10042166 0x124 _L1w_DevRfcAgcDbAgcCalc
- 0x1004228a 0x1c _L1w_DevRfcAgcDbAgcEstEn
- 0x100422a6 0x3d _L1w_DevRfcAfcDbAfcSet
- 0x100422e3 0x13 _L1w_DevRfcAfcDbGetAfcDbVal
- 0x100422f6 0x1e _L1w_DevRfcSetRefFreq
- 0x10042314 0x43 _L1w_DevRfcAgcDbGetFreqAgcInfo
- 0x10042357 0x62 _L1w_DevRfcAgcDbGetRssi
- 0x100423b9 0x9e _L1w_DevRfcAgcDbGetMeanpwr
- 0x10042457 0x35 _L1w_DevRfcAgcDbAuxChInitSet
- 0x1004248c 0x42 _L1w_DevRfcAgcDbGetTableInd
- 0x100424ce 0x7a _L1w_DevRfcAgcDbFdtAgcInit
- 0x10042548 0x43 _L1w_DevRfcAgcDbNstAgcInit
- 0x1004258b 0x15 _L1w_DevRfcAgcDbTxChgeInfoWr
- 0x100425a0 0x15 _L1w_DevRfcAgcDbRxChgeInfoWr
- .text 0x100425b5 0x2cb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
- 0x100425b5 0x26 _L1w_DevDlsSendIntMsg
- 0x100425db 0x24 _L1w_DevDlsSendCnf
- 0x100425ff 0xf _L1w_DevDlsReset
- 0x1004260e 0xf _L1w_DevDlsInit
- 0x1004261d 0x263 _L1w_DlsTask
- .text 0x10042880 0x12a5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
- 0x10042880 0x89 _L1w_DevHsdpaSubFrmIsInCm
- 0x10042909 0x78 _L1w_DevHsdpaCalcTimingInfo
- 0x10042981 0x2d _L1w_DevHsdpaCalcAckNackPos
- 0x100429ae 0x52 _L1w_DevHsdpaCalcTbSizeByTbs
- 0x10042a00 0x23 _L1w_DevHsdpaCalcTbSizeByTbsIdx
- 0x10042a23 0xd _L1w_DevHsdpaCalcRvB
- 0x10042a30 0x3a _L1w_DevHsdpaCalcCodeBlockPara
- 0x10042a6a 0x25 _L1w_DevHsdpaCalc1stRmPara
- 0x10042a8f 0x37 _L1w_DevHsdpaCalc2ndRmEini
- 0x10042ac6 0xf9 _L1w_DevHsdpaCalcRmPara
- 0x10042bbf 0x9f _L1w_DevHsdpaCalcVelcity
- 0x10042c5e 0xd _L1w_DevHsdpaCalcSymPower
- 0x10042c6b 0x79 _L1w_DevHsdpaCalcFingerMaskStep1
- 0x10042ce4 0xba _L1w_DevHsdpaCalcFingerMaskStep2
- 0x10042d9e 0x45 _L1w_DevHsdpaCalcFingerMaskStep3
- 0x10042de3 0x5d _L1w_DevHsdpaCalcAntFingerMask
- 0x10042e40 0x11f _L1w_DevHsdpaFingerMaskBufUpdate
- 0x10042f5f 0x8c _L1w_DevHsdpaCalcFingerMask
- 0x10042feb 0xb8 _L1w_DevHsdpaSnrLowRstJudge
- 0x100430a3 0x1b0 _L1w_DevHsdpaCalcNoiseSinr
- 0x10043253 0x47 _L1w_DevHsdpaCalcNoiseFactor
- 0x1004329a 0xc3 _L1w_DevHsdpaCalcCirPower
- 0x1004335d 0xba _L1w_DevHsdpaCalcEqNoise
- 0x10043417 0x34 _L1w_DevHsdpaCalcNoise
- 0x1004344b 0x2d _L1w_DevHsdpaIsExceedFinWin
- 0x10043478 0x6b _L1w_DevHsdpaPsrFingerFilter
- 0x100434e3 0x56 _L1w_DevHsdpaCalcFrameHeadPos
- 0x10043539 0x87 _L1w_DevHsdpaCalcIntraCellSfnOffset
- 0x100435c0 0xfc _L1w_DevHsdpaCalcFingerSort
- 0x100436bc 0x24 _L1w_DevHsdpaCalcJudgeResetFlg
- 0x100436e0 0x27c _L1w_DevHsdpaCalcCellFingerSort
- 0x1004395c 0x1b _L1w_DevHsdpaCalcAntChe4xPos
- 0x10043977 0xef _L1w_DevHsdpaCalcChe4xPos
- 0x10043a66 0xbf _L1w_DevHsdpaCalcAdrPsrInfo
- .text 0x10043b25 0x3d4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o)
- 0x10043b25 0x3f _L1w_DevDrvAllIntClear
- 0x10043b64 0x54 _L1w_DevDrvRestoreAllInt
- 0x10043bb8 0x9e _L1W_TPU_RAKE_ISR
- 0x10043c56 0x70 _L1W_RAKE_DFE_RFC_ISR
- 0x10043cc6 0xac _L1W_TPU_CSR_ADR_HSSCCH_ISR
- 0x10043d72 0x89 _L1W_CSR_DTR_PSR_ISR
- 0x10043dfb 0x27 _L1w_DevCommGetTop19IntStatus
- 0x10043e22 0x26 _L1W_ICP_UPA_DATA_ISR
- 0x10043e48 0x5c _L1W_ICP_SLEEP_WAKEUP_ISR
- 0x10043ea4 0x1c _L1W_EDCP_ISR
- 0x10043ec0 0x39 _L1_W_LPM_T3_ISR
- .text 0x10043ef9 0x2265 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
- 0x10043ef9 0x8 _L1w_DevCsrSetStep1Clk
- 0x10043f01 0x8 _L1w_DevCsrGetStep1Clk
- 0x10043f09 0x6 _L1w_DevGetPeakThreshold
- 0x10043f0f 0x1 _L1w_DevGetFsThreshold
- 0x10043f10 0x1e _L1w_DevCsrStep1Cmp
- 0x10043f2e 0xa _L1w_DevCsrF2W
- 0x10043f38 0xf _L1w_DevCsrW2F
- 0x10043f47 0x15 _L1w_DevCsrCompare
- 0x10043f5c 0x87 _L1w_DevCsrComputeWin
- 0x10043fe3 0x2a _L1w_DevCsrInitReq
- 0x1004400d 0x98 _L1w_DevCsrStep1Req
- 0x100440a5 0x75 _L1w_DevCsrFsReq
- 0x1004411a 0x27 _L1w_DevCsrResetCnf
- 0x10044141 0x27 _L1w_DevCsrInitCnf
- 0x10044168 0x65 _L1w_DevCsrStep1Cnf
- 0x100441cd 0x4f _L1w_DevCsrFsCnf
- 0x1004421c 0x2d _L1w_DevCsrIntInd
- 0x10044249 0x5d _L1w_DevCsrStep1CalConfigIndex4_1
- 0x100442a6 0x3d _L1w_DevCsrSaveDateMrtr
- 0x100442e3 0x138 _L1w_DevCsrIcCfg
- 0x1004441b 0xe _L1w_DevCsrSetFsAbort
- 0x10044429 0x1ac _L1w_DevCsrStep1Abort
- 0x100445d5 0x272 _L1w_DevCsrStep1Pro
- 0x10044847 0xa _L1w_DevCsrClrFsSt
- 0x10044851 0x7d _L1w_DevCsrFsPro
- 0x100448ce 0xbf _L1w_DevCsrPeakFilter
- 0x1004498d 0xb8 _L1w_DevCsrPeakSearch
- 0x10044a45 0x95 _L1w_DevCsrFsReqCfg
- 0x10044ada 0x113 _L1w_DevCsrIcFilter
- 0x10044bed 0x1312 _L1w_DevCsrStep1Int
- 0x10045eff 0x125 _L1w_DevCsrFsInt
- 0x10046024 0x1a _L1w_DevCsrStep1IsBusy
- 0x1004603e 0x13 _L1w_DevCsrReset
- 0x10046051 0x10 _L1w_DevCsrStFsSt
- 0x10046061 0xfd _L1w_CsrTask
- .text 0x1004615e 0x220d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
- 0x1004615e 0x30 _L1w_DevPcWord64ToFloat
- 0x1004618e 0x40 _L1w_DevPcFloatToWord
- 0x100461ce 0x2e _L1w_PcLog2FindTable
- 0x100461fc 0x80 _L1w_DevPcFloatSirAndBlerToWord32
- 0x1004627c 0x28 _L1w_DevPcDiv
- 0x100462a4 0x71 _L1w_DevPcLog10
- 0x10046315 0xe6 _L1w_DevPc10xPower10expOld
- 0x100463fb 0x2c _L1w_DevPc10xPower10exp
- 0x10046427 0x65 _L1w_DevSirBlerPcDiv
- 0x1004648c 0x38 _L1w_DevPcFloatAdd
- 0x100464c4 0x3b _L1w_DevPcUlAlphaDiv
- 0x100464ff 0x62 _L1w_DevPcPowerLimit
- 0x10046561 0x86 _L1w_DevPcSumBeltaIQmap
- 0x100465e7 0x81 _L1w_DevPcCalcSquareBetaHs
- 0x10046668 0x22 _L1w_DevPcP1P2LogCalc
- 0x1004668a 0x19 _L1w_DevPcP1P2Calc
- 0x100466a3 0xd _L1w_DevPcBetalRatioProc
- 0x100466b0 0x9d _L1w_DevPcCodeRatioCalc
- 0x1004674d 0x14 _L1w_DevPcGetTxpowerForMeas
- 0x10046761 0x99 _L1w_DevPcConfigTxReg
- 0x100467fa 0x92 _L1w_DevPcTtiUpdDpaBeta
- 0x1004688c 0xe4 _L1w_DevPcTtiUpdEdchBeta
- 0x10046970 0x23 _L1w_DevPcNoDpdchPro
- 0x10046993 0xb5 _L1w_DevPcTtiUpdDpchBeta
- 0x10046a48 0x35 _L1w_DevPcBetaEdAllSquareCalc
- 0x10046a7d 0xc _L1w_DevPcSumSquareCalc
- 0x10046a89 0x56 _L1w_DevPcSquareCalc
- 0x10046adf 0x110 _L1w_DevPcIQMap
- 0x10046bef 0x1b _L1w_DevPcRangeAdjust
- 0x10046c0a 0x32 _L1w_DevPcCalcCm
- 0x10046c3c 0x146 _L1w_DevPcMprCalPro
- 0x10046d82 0x2f _L1w_DevPcMprAdjust
- 0x10046db1 0x39 _L1w_DevPcMprCalCtrl
- 0x10046dea 0x116 _L1w_DevPcCodeRatioAndTotalPowerCalc
- 0x10046f00 0x33 _L1w_DevPcPwrValadjust
- 0x10046f33 0x94 _L1w_DevPcGainTorAdjust
- 0x10046fc7 0x89 _L1w_DevPcCalPvalue
- 0x10047050 0x3f _L1w_DevPcGaintorHalf
- 0x1004708f 0x4b _L1w_DevPcMaxPwrSetProc
- 0x100470da 0x178 _L1w_DevPcTxAndRfSet
- 0x10047252 0x54 _L1w_DevPcTpuCallBack
- 0x100472a6 0x1d _L1w_DevPcRegFrmTpu
- 0x100472c3 0x88 _L1w_DevPcUlRegTpu
- 0x1004734b 0x1c _L1w_DevPcIsBeltaEdAllEquReduce
- 0x10047367 0xff _L1w_DevPcSetLastBelta
- 0x10047466 0x25 _L1w_DevPcPmaxReLimt
- 0x1004748b 0x7d _L1w_DevPcPmaxReCalc
- 0x10047508 0x2d _L1w_DevPcBeltaReCalcBeltaEdReducedMin
- 0x10047535 0x43 _L1w_DevPcBeltaReCalcEtfciBoost
- 0x10047578 0x97 _L1w_DevPcBeltaReCalc
- 0x1004760f 0x21 _L1w_DevPcMaxPowerLimit
- 0x10047630 0x14 _L1w_DevPcMinPowerLimit
- 0x10047644 0xe0 _L1w_DevPcCMInfoUpdate
- 0x10047724 0x46 _L1w_DevPcFrmEventHandle
- 0x1004776a 0x51 _L1w_DevPcPreCalc
- 0x100477bb 0x63 _L1w_DevPcStopHandle
- 0x1004781e 0xdd _L1w_DevPc3SymbolIntHandle
- 0x100478fb 0x4d _L1w_DevPcGaintorCalc
- 0x10047948 0x46 _L1w_DevPcTpuTpcSlotHandle
- 0x1004798e 0x1c _L1w_DevPcSlotModeGet
- 0x100479aa 0x15 _L1w_DevPcDlGapPatternJudge
- 0x100479bf 0x9 _L1w_DevPcWriteCmBitMap
- 0x100479c8 0xa _L1w_DevPcIsUlCmFrm
- 0x100479d2 0x15 _L1w_DevPcIsCmFrmOnlyGap
- 0x100479e7 0x2d _L1w_DevPcIsCmFrm
- 0x10047a14 0x7a _L1w_DevPcSlotModeSet
- 0x10047a8e 0x2d _L1w_DevPcUlCmInfoHandle
- 0x10047abb 0x24 _L1w_DevPcDlCmInfoHandle
- 0x10047adf 0x48 _L1w_DevPcCmStopHandle
- 0x10047b27 0x12 _L1w_DevPcCmStopReqHandle
- 0x10047b39 0x32 _L1w_DevPcStopReqHandle
- 0x10047b6b 0x11c _L1w_DevPcWriteSubFrmIntInfo
- 0x10047c87 0x74 _L1w_DevPcReset
- 0x10047cfb 0xcb _L1w_DevPcInit
- 0x10047dc6 0x7b _L1w_DevPcOutSyncEng
- 0x10047e41 0xef _L1w_DevPcEngPrintf
- 0x10047f30 0x63 _L1w_DevPcWriteDpramMsg
- 0x10047f93 0x27 _L1w_DevPcResetCnf
- 0x10047fba 0x27 _L1w_DevPcInitCnf
- 0x10047fe1 0x2c _L1w_DevRtxPcPrachStartReq
- 0x1004800d 0x28 _L1w_DevRtxPcPrachPreambleReq
- 0x10048035 0x30 _L1w_DevRtxPcPrachMessageReq
- 0x10048065 0x39 _L1w_DevRtxPcDchStartReq
- 0x1004809e 0x2c _L1w_DevRtxPcUlDpchCmInfoReq
- 0x100480ca 0x2c _L1w_DevRtxPcDlDpchCmInfoReq
- 0x100480f6 0x29 _L1w_DevRtxPcDpchCmStopReq
- 0x1004811f 0x2e _L1w_DevRtxPcBlerReq
- 0x1004814d 0x2d _L1w_DevHsdpaPcStartReq
- 0x1004817a 0x28 _L1w_DevHsdpaPcTtiReq
- 0x100481a2 0x21 _L1w_DevHsdpaPcStoptReq
- 0x100481c3 0x11 _L1w_DevDchPcSetPara
- 0x100481d4 0x2a _L1w_DevHsupaPcStartReq
- 0x100481fe 0x2d _L1w_DevHsupaPcTtiReq
- 0x1004822b 0x21 _L1w_DevHsupaPcStopReq
- 0x1004824c 0x11f _L1w_PcTask
- .text 0x1004836b 0x29a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
- 0x1004836b 0x1 _L1w_DevEngInitAddr
- 0x1004836c 0x19 _L1w_EngTaskInit
- 0x10048385 0x7 _L1w_DevEngSetFlag
- 0x1004838c 0x12 _L1w_log_track_init
- 0x1004839e 0x8e _L1w_DevEngDisplay
- 0x1004842c 0x46 _L1w_EngTrace
- 0x10048472 0xaa _L1w_DevEngLogHeaderUpdate
- 0x1004851c 0xc6 _L1w_DevEngWriteDataToBuffer
- 0x100485e2 0x22 _L1w_DevEngCopyMem2Dpram
- 0x10048604 0x1 _L1w_DevEngUartTransmit
- .text 0x10048605 0xde T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o)
- 0x10048605 0x9 _L1w_DevTxFirstTpuIntSet
- 0x1004860e 0xc _L1w_DevTxFirstTpuIntDelete
- 0x1004861a 0x82 _L1w_DevRtxTxCfgMsgHandle
- 0x1004869c 0x16 _L1w_DevTxTpuIntHandle
- 0x100486b2 0x15 _L1w_DevRtxTxReset
- 0x100486c7 0x1c _L1w_DevRtxTxInit
- .text 0x100486e3 0x1cc0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
- 0x100486e3 0x6b _L1w_DevRtxRxBlindAnalyse
- 0x1004874e 0x77 _L1w_DevRtxRxTfcParaCalc
- 0x100487c5 0xd5 _L1w_DevRtxRxJudgeCsRam
- 0x1004889a 0x115 _L1w_DevRtxRxTrchParaCalc
- 0x100489af 0x33 _L1w_DevRtxRxDtrCtfcSort
- 0x100489e2 0x81 _L1w_DevRtxRxSccpchDtrParam
- 0x10048a63 0x3b _L1w_DevRtxRxJudgeRrm
- 0x10048a9e 0x2f _L1w_DevRtxRxV3BlindTbs49Change
- 0x10048acd 0x25 _L1w_DevRtxRxV3BlindTbsChange
- 0x10048af2 0xc4 _L1w_DevRtxRxV3BlindTfcPatch
- 0x10048bb6 0xd2 _L1w_DevRtxRxDpchDtrParam
- 0x10048c88 0x11 _L1w_DevRtxRxTtiModeGet
- 0x10048c99 0xe _L1w_DevRtxRxCrcModeGet
- 0x10048ca7 0x16 _L1w_DevRtxRxCodingGet
- 0x10048cbd 0x89 _L1w_DevRtxRxTrchInfoCfg
- 0x10048d46 0x51 _L1w_DevRtxRxDpchDtrCmCfg
- 0x10048d97 0x74 _L1w_DevRtxRxDlDpchDtrCfg
- 0x10048e0b 0x6d _L1w_DevRtxRxDlSccpchDtrCfg
- 0x10048e78 0x36 _L1w_DevRtxRxAgchDtrCfg
- 0x10048eae 0x83 _L1w_DevRtxRxAgchCmDtrCfg
- 0x10048f31 0x45 _L1w_DevRtxRxCfgABUpdate
- 0x10048f76 0x34 _L1w_DevRtxRxDeilBaseSort
- 0x10048faa 0x9f _L1w_DevRtxRxTfciS2Cfg
- 0x10049049 0xb1 _L1w_DevRtxRxTfcAnalyse
- 0x100490fa 0x58 _L1w_DevRtxRxBlindGuidCfg
- 0x10049152 0x37 _L1w_DevRtxRxPn9BerCheckStart
- 0x10049189 0xa1 _L1w_DevRtxRxPn9Get244Bit
- 0x1004922a 0x42 _L1w_DevRtxRxPn9BerRltReport
- 0x1004926c 0xc5 _L1w_DevRtxRxPn9DataCheck
- 0x10049331 0x81 _L1w_DevRtxRxAllBlindHandle
- 0x100493b2 0xda _L1w_DevRtxRxBlindDtrCfg
- 0x1004948c 0x17a _L1w_DevRtxRxBlindCrcHandle
- 0x10049606 0xc3 _L1w_DevRtxRxBlindDataHandle
- 0x100496c9 0x21 _L1w_DevRtxRxBlindStateCheck
- 0x100496ea 0xeb _L1w_DevRtxRxBlindTfcAnalyse
- 0x100497d5 0x3a _L1w_DevRtxRxTfcDataCmpHandle
- 0x1004980f 0x38 _L1w_DevRtxRxTfciFWHT
- 0x10049847 0x126 _L1w_DevRtxRxTfciCoding
- 0x1004996d 0x1f1 _L1w_DevRtxRxTfciIntHandle
- 0x10049b5e 0x18 _L1w_DevRtxRxGetGsmVal
- 0x10049b76 0x76 _L1w_DevRtxRxCmpPchUeId
- 0x10049bec 0x55 _L1w_DevRtxRxPchUeIdHandle
- 0x10049c41 0x114 _L1w_DevRtxRxTtiBlindHandle
- 0x10049d55 0xab _L1w_DevRtxRxTrchCrcStatic
- 0x10049e00 0xbd _L1w_DevRtxRxTtiCrcStatic
- 0x10049ebd 0xb _L1w_DevRtxRxTtiCrcStatForAfc
- 0x10049ec8 0x63 _L1w_DevRtxRxTtiTrchInfoHandle
- 0x10049f2b 0x8d _L1w_DevRtxRxTtiBdTrchInfoHandle
- 0x10049fb8 0x64 _L1w_DevRtxRxNoBdTtiHandle
- 0x1004a01c 0x54 _L1w_DevRtxRxBlindTtiHandle
- 0x1004a070 0x49 _L1w_DevRtxRxPchTtiHandle
- 0x1004a0b9 0x68 _L1w_DevRtxRxTtiIntAfterHandle
- 0x1004a121 0x25e _L1w_DevRtxRxTtiIntHandle
- 0x1004a37f 0x24 _L1w_DevRtxRxDtrRel
- .text 0x1004a3a3 0x5db T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_cqi.o)
- 0x1004a3a3 0x8b _L1w_DevHsdpaCqiCalcPos
- 0x1004a42e 0x1b1 _L1w_DevHsdpaCalcCqiSnr
- 0x1004a5df 0x6b _L1w_DevHsdpaSnrLimitAdj
- 0x1004a64a 0xbf _L1w_DevHsdpaCqiSnrAdj
- 0x1004a709 0x68 _L1w_DevHsdpaCalcSnrVal
- 0x1004a771 0x20d _L1w_DevHsdpaSnrMapToCqiVal
- .text 0x1004a97e 0x2f5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_pcch.o)
- 0x1004a97e 0x5b _L1w_DevRtxRxPcchBitRead
- 0x1004a9d9 0x3e _L1w_DevRtxRxImsiGsm
- 0x1004aa17 0x2f _L1w_DevRtxRxTmsiGsm
- 0x1004aa46 0x2f _L1w_DevRtxRxPTmsiGsm
- 0x1004aa75 0xf _L1w_DevRtxRxImsiDs41
- 0x1004aa84 0xf _L1w_DevRtxRxTmsiDs41
- 0x1004aa93 0x3d _L1w_DevRtxRxPagRecCnId
- 0x1004aad0 0x44 _L1w_DevRtxRxPagRecUtranId
- 0x1004ab14 0x4e _L1w_DevRtxRxPagRec2UtranSingUeId
- 0x1004ab62 0x28 _L1w_DevRtxRxPagRec2UtranGrpId
- 0x1004ab8a 0x28 _L1w_DevRtxRxPagingRecList
- 0x1004abb2 0x28 _L1w_DevRtxRxPagingRec2ListR5
- 0x1004abda 0x12 _L1w_DevRtxRxPagingV590ExtIE
- 0x1004abec 0x10 _L1w_DevRtxRxPagingV860ExtIE
- 0x1004abfc 0x47 _L1w_DevRtxRxPagingType1
- 0x1004ac43 0x19 _L1w_DevRtxRxPcchMsgType
- 0x1004ac5c 0x17 _L1w_DevRtxRxDecodePcch
- .text 0x1004ac73 0x18da T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
- 0x1004ac73 0x22 _L1w_HspaCalcMod
- 0x1004ac95 0xb _L1w_DevHsupaEdchReadyInit
- 0x1004aca0 0x11 _L1w_DevHsupaInitUlDataInfo
- 0x1004acb1 0x18 _L1w_DevHsupaUlReset
- 0x1004acc9 0x5c _L1w_DevHsupaParaInit
- 0x1004ad25 0x45 _L1w_DevHsupaInit
- 0x1004ad6a 0x15 _L1w_DevHsupaHwRel
- 0x1004ad7f 0x8f _L1w_DevHsupaReset
- 0x1004ae0e 0x5f _L1w_DevHsupaGetDlChanInfo
- 0x1004ae6d 0x34 _L1w_DevHsupaCalcDisEagchEdch
- 0x1004aea1 0x10 _L1w_DevHsupaCalcDisEhichEdch
- 0x1004aeb1 0x21 _L1w_DevHsupaCalcDisErgchEdch
- 0x1004aed2 0x1a _L1w_DevHsupaCalcInitNo
- 0x1004aeec 0x3a _L1w_DevHsupaCalcInitSwNo
- 0x1004af26 0x64 _L1w_DevHsupaCalcIscpSlotId
- 0x1004af8a 0x9a _L1w_DevHsupaCalcDlChanInitNo
- 0x1004b024 0x5e _L1w_DevHsupaConfigReq
- 0x1004b082 0x2b _L1w_DevHsupaCpEdpdchInfo
- 0x1004b0ad 0x3d _L1w_DevHsupaCpErntiInfo
- 0x1004b0ea 0x65 _L1w_DevHsupaCpRxEagchCfg
- 0x1004b14f 0x42 _L1w_DevHsupaRtxEagchCfg
- 0x1004b191 0x8 _L1w_DevHsupaGetErgchFrameType
- 0x1004b199 0x7e _L1w_DevHsupaCpRxRgHiCfg
- 0x1004b217 0x77 _L1w_DevHsupaRtxRgHiCfg
- 0x1004b28e 0x23 _L1w_DevHsupaRtxCfg
- 0x1004b2b1 0xca _L1w_DevHsupaCpDlRcvInfo
- 0x1004b37b 0x20 _L1w_DevHsupaCfgTxInit
- 0x1004b39b 0x22 _L1w_DevHsupaEagchInt2Ps
- 0x1004b3bd 0x97 _L1w_DevHsupaCalAgRgHiIntNo
- 0x1004b454 0x4f _L1w_DevHsupaNorm2TpuBase
- 0x1004b4a3 0x79 _L1w_DevHsupaFachNt2CfnTime
- 0x1004b51c 0x84 _L1w_DevHsupaSaveTpuTime
- 0x1004b5a0 0x2d _L1w_DevHsupaCalcSwTtiCntIntOff
- 0x1004b5cd 0x73 _L1w_DevHsupaGetCfnTime
- 0x1004b640 0x25 _L1w_DevHsupaCalcSwTtiCntIntOn
- 0x1004b665 0x114 _L1w_DevHsupaEagchIntProc
- 0x1004b779 0x18 _L1w_DevHsupaEagchIntInd
- 0x1004b791 0x4c _L1w_DevHuspaSaveAG
- 0x1004b7dd 0x12 _L1w_DevHuspaUpaTransFlgToMac
- 0x1004b7ef 0x1c _L1w_DevHuspaGrantHarqToMac
- 0x1004b80b 0xb9 _L1w_DevHsupaReportPsStatistic
- 0x1004b8c4 0x65 _L1w_DevHsupaStdlogThroughput
- 0x1004b929 0x82 _L1w_DevHsupaStdlogPacketInfo
- 0x1004b9ab 0x40 _L1w_DevHsupaReportToMac
- 0x1004b9eb 0x71 _L1w_DevHsupaRptHarqFlag
- 0x1004ba5c 0x5b _L1w_DevHsupaDchIsMacTrans
- 0x1004bab7 0x14 _L1w_DevHsupaFachIsMacTrans
- 0x1004bacb 0x22 _L1w_DevHsupaIsMacTrans
- 0x1004baed 0x37 _L1w_DevHsupaPcCfg
- 0x1004bb24 0x1 _L1w_DevHsupaAgRgHiIndCallBack
- 0x1004bb25 0x3a _L1w_DevHsupaAddTpu
- 0x1004bb5f 0x9 _L1w_DevHsupaGetPhyMinSfMaxChan
- 0x1004bb68 0x9e _L1w_DevHsupaDisplayCfgInfo
- 0x1004bc06 0x6a _L1w_DevHsupaSaveStdlogPacket
- 0x1004bc70 0x35 _L1w_DevHsupaCfgToPsrInd
- 0x1004bca5 0x125 _L1w_DevHsupaConfigProc
- 0x1004bdca 0x2c _L1w_DevHsupaIcpIntInd
- 0x1004bdf6 0x2c _L1w_DevHsupaEdcpIntInd
- 0x1004be22 0x59 _L1w_DevHsupaIcpIntProc
- 0x1004be7b 0xea _L1w_DevHsupaEdcpIntProc
- 0x1004bf65 0x26 _L1w_DevHsupaCfgPcTti
- 0x1004bf8b 0x2c _L1w_DevHsupaEtxIntInd
- 0x1004bfb7 0x2d _L1w_DevHsupaCalcNtx1Info
- 0x1004bfe4 0x23 _L1w_DevHsupaCmInfoClr
- 0x1004c007 0xf1 _L1w_DevHsupaEtxIntProc
- 0x1004c0f8 0x21 _L1w_DevHsupaRelReq
- 0x1004c119 0xf _L1w_DevHsupaRtxRelReq
- 0x1004c128 0x4e _L1w_DevHsupaReleaseProc
- 0x1004c176 0xc _L1w_DevHsupaIfHarqIdValid
- 0x1004c182 0x66 _L1w_DevHsupaTestCurFrameNum
- 0x1004c1e8 0x37 _L1w_DevHsupaCalcEdchCfn
- 0x1004c21f 0x2a _L1w_DevHsupaGetCurFrameNum
- 0x1004c249 0x2d _L1w_DevHsupaCalcNextTtiFrameNum
- 0x1004c276 0x2b _L1w_DevHsupaCmPatternUpdateReq
- 0x1004c2a1 0x5c _L1w_DevHsupaCalcDlCm
- 0x1004c2fd 0x69 _L1w_DevHsupaCmPatternUpdateProc
- 0x1004c366 0x31 _L1w_DevHsupaCalChLen
- 0x1004c397 0x7 _L1w_DevHsupaSetHsdschCfg
- 0x1004c39e 0x77 _L1w_DevHsupaActive
- 0x1004c415 0xf1 _L1w_DevHsupaTpuProc
- 0x1004c506 0x3b _L1w_DevHsupaTransIndProc
- 0x1004c541 0xc _L1w_DevHsupaIsDchActive
- .text 0x1004c54d 0x18b3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
- 0x1004c54d 0xb _L1w_DevRtxRxIntDataInit
- 0x1004c558 0x13 _L1w_DevRtxRxIntReset
- 0x1004c56b 0x12 _L1w_DevRtxRxFix2Sword32
- 0x1004c57d 0x13 _L1w_DevRtxRxFix2Sword16
- 0x1004c590 0x6e _L1w_DevRtxRxRcvFingerSlotwt
- 0x1004c5fe 0x38 _L1w_DevRtxRxRcvFingerAfc
- 0x1004c636 0x5b _L1w_DevRtxRxRcvFingerNoise
- 0x1004c691 0x27 _L1w_DevRtxRxCalcFingerIscp
- 0x1004c6b8 0x9c _L1w_DevRtxRxRcvOffLInePiResult
- 0x1004c754 0x88 _L1w_DevRtxRxRcvPiData
- 0x1004c7dc 0xcc _L1w_DevRtxRxPichIntHandle
- 0x1004c8a8 0x25 _L1w_DevRtxRxGetBuffIdx
- 0x1004c8cd 0xb2 _L1w_DevRtxRxRcvAiData
- 0x1004c97f 0xdd _L1w_DevRtxRxCalcAiCpichPower
- 0x1004ca5c 0x51 _L1w_DevRtxRxCalcAiCpichPrIIR
- 0x1004caad 0x10 _L1w_DevRtxRxGetAiDeltaPac
- 0x1004cabd 0x31 _L1w_DevRtxRxCalcAiThreshold
- 0x1004caee 0x24 _L1w_DevRtxRxCalcAiSignCorr
- 0x1004cb12 0x26 _L1w_DevRtxRxCalcAiVal
- 0x1004cb38 0x26 _L1w_DevRtxRxAiDataPreHandle
- 0x1004cb5e 0x2e _L1w_DevRtxRxEAiResCfgMap
- 0x1004cb8c 0x4b _L1w_DevRtxRxNewCalcAiVal
- 0x1004cbd7 0x5e _L1w_DevRtxRxNewEAiCalc
- 0x1004cc35 0x122 _L1w_DevRtxRxNewAichIntHandle
- 0x1004cd57 0x2b _L1w_DevRtxRxCalcFbiFingerPr
- 0x1004cd82 0x34 _L1w_DevRtxRxCalcFbiRlPr
- 0x1004cdb6 0xed _L1w_DevRtxRxCalcFbiTotalPr
- 0x1004cea3 0x23 _L1w_DevRtxRxCalcFbiValue
- 0x1004cec6 0xc6 _L1w_DevRtxRxCalcFbi
- 0x1004cf8c 0x4a _L1w_DevRtxRxIntParaUpdate
- 0x1004cfd6 0x6 _L1w_DevRtxRxGetTpcIData
- 0x1004cfdc 0x5 _L1w_DevRtxRxGetTpcQData
- 0x1004cfe1 0x6 _L1w_DevRtxRxGetTpcIExp
- 0x1004cfe7 0x5 _L1w_DevRtxRxGetTpcQExp
- 0x1004cfec 0x58 _L1w_DevRtxRxDchTpcSirCalc
- 0x1004d044 0xcf _L1w_DevRtxRxDchTpcIntHandle
- 0x1004d113 0x9 _L1w_DevRtxRxDchPilotIntHandle
- 0x1004d11c 0x6f _L1w_DevRtxRxFdpchTpcIntHandle
- 0x1004d18b 0x46 _L1w_DevRtxRxTpcIntHandle
- 0x1004d1d1 0x4c _L1w_DevRtxRxFactorCheck
- 0x1004d21d 0x84 _L1w_DevRtxRxFactorDataGet
- 0x1004d2a1 0x44 _L1w_DevRtxRxFactorHandle
- 0x1004d2e5 0x61 _L1w_DevRtxRxAgchFactorHandle
- 0x1004d346 0x50 _L1w_DevRtxRxSccpchFactorCalc
- 0x1004d396 0x13b _L1w_DevRtxRxPchFactorHandle
- 0x1004d4d1 0x109 _L1w_DevRtxRxFachFactorHandle
- 0x1004d5da 0x2f _L1w_DevRtxRxCalcIscp
- 0x1004d609 0x1dd _L1w_DevRtxRxFingerDataHandle
- 0x1004d7e6 0x8a _L1w_DevRtxRxNoiseDataCheck
- 0x1004d870 0x67 _L1w_DevRtxRxSetAfcInfo
- 0x1004d8d7 0x119 _L1w_DevRtxRxCpich2ndFingerPrint
- 0x1004d9f0 0xf3 _L1w_DevRtxRxCpichTpuIntPrint
- 0x1004dae3 0xea _L1w_DevRtxRxCpichTpuIntAllPrint
- 0x1004dbcd 0x5a _L1w_DevRtxRxCpichTpuIntIscpErrPrint
- 0x1004dc27 0x45 _L1w_DevRtxRxCpichTpuIntUpaParaUpdate
- 0x1004dc6c 0x167 _L1w_DevRtxRxCpichTpuIntHandle
- 0x1004ddd3 0x1 _L1w_DevRtxRxPilotIntHandle
- 0x1004ddd4 0x2c _L1w_DevRtxRxIntHandle
- .text 0x1004de00 0x3556 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
- 0x1004de00 0x5 _L1w_DevDlsPsrReset
- 0x1004de05 0xb8 _L1w_DevDlsintialGlobalVariable
- 0x1004debd 0x30 _L1w_DevDlsPsrIntialHardWare
- 0x1004deed 0x8 _L1w_DevDlsPsrIntial
- 0x1004def5 0xd _L1w_DevDlsSaveOldUlTiming
- 0x1004df02 0x64 _L1w_DevDlsStop
- 0x1004df66 0x3a _L1w_DevPsrIntEventProc
- 0x1004dfa0 0x35 _L1w_DevPsrSendTimingInfoToL1s
- 0x1004dfd5 0x3d _L1w_DevPsrAddTpuFixedEvent
- 0x1004e012 0x27 _L1w_DevPsrDchStopReq
- 0x1004e039 0x39 _L1w_DevPsrMeasStartReq
- 0x1004e072 0x12d _L1w_DevPsrDchJudgeNcellSave
- 0x1004e19f 0x177 _L1w_DevPsrSetRlNcellFlag
- 0x1004e316 0x36 _L1w_DevPsrEfachStartReq
- 0x1004e34c 0x32 _L1w_DevPsrEfachFdpchOffsetReq
- 0x1004e37e 0x22 _L1w_DevPsrEfachStopReq
- 0x1004e3a0 0x25 _L1w_DevPsrFmoStopReq
- 0x1004e3c5 0x3b _L1w_DevDlsPsrHsdpaReq
- 0x1004e400 0x32 _L1w_DevPsrDchUpaExistReq
- 0x1004e432 0x6c _L1w_DevPsrEfachUlDpcchFBConfig
- 0x1004e49e 0x54 _L1w_DevPsrUlDpcchFBConfig
- 0x1004e4f2 0x1 _L1w_DevPsrCommParaCfg
- 0x1004e4f3 0x3c _L1w_DevPsrSaveCmInfo
- 0x1004e52f 0x21 _L1w_DevPsrTransDpchCm2Cpich
- 0x1004e550 0xa8 _L1w_DevPsrRtxFirstFingerConfigS
- 0x1004e5f8 0x196 _L1w_DevPsrSelectMasterRl
- 0x1004e78e 0x6c _L1w_DevPsrSaveLastTimingTrace
- 0x1004e7fa 0x110 _L1w_DevPsrDchSelectUpaCell
- 0x1004e90a 0x160 _L1w_DevPsrDchConfigHardware
- 0x1004ea6a 0xf8 _L1w_DevPsrDchReqConfig
- 0x1004eb62 0xfa _L1w_DevPsrHardWorkTimeConfig
- 0x1004ec5c 0x53 _L1w_DevPsrRlPosAndCodeConfig
- 0x1004ecaf 0xc8 _L1w_DevPsrFachReqConfig
- 0x1004ed77 0x29 _L1w_DevDlsCalcHandOverNtAdjPos
- 0x1004eda0 0x2f _L1w_DevDlsCalcAdjPos
- 0x1004edcf 0x1d9 _L1w_DevDlsCalcRegConfigTimingAndReport
- 0x1004efa8 0x15a _L1w_DevDlsCalcRlTimingAndReport
- 0x1004f102 0x58 _L1w_DevDlsPsrUpdateULInfo
- 0x1004f15a 0x125 _L1w_DevDlsFachTimingMaintain
- 0x1004f27f 0x1c _L1w_DevDlsTimingMaintain
- 0x1004f29b 0x34 _L1w_DevDlsDchJudgeAdustSpeed
- 0x1004f2cf 0x42 _L1w_DevDlsDchTimingMaintain
- 0x1004f311 0x48 _L1w_DevDlsPsrSelectDpaId
- 0x1004f359 0x63 _L1w_DevDlsPsrChangeDpaIdCell
- 0x1004f3bc 0xc8 _L1w_DevDlsPsrGetAntNumAndJudgeConfig
- 0x1004f484 0xa _L1w_DevDlsPsrClearCopyFingernfo
- 0x1004f48e 0x3a _L1w_DevDlsPsrDpaIsChangjing1
- 0x1004f4c8 0x11a _L1w_DevDlsPsrJudgeFingerOver512
- 0x1004f5e2 0x2df _L1w_DevDlsPsrWholeHandleS
- 0x1004f8c1 0x24 _L1w_DevPsrTpuIntHandle
- 0x1004f8e5 0x4a _L1w_DevPsrRlCpichTimingAdujst
- 0x1004f92f 0x5b _L1w_DevPsrSoftHandOverTimingAdj
- 0x1004f98a 0x5a _L1w_DevPsrIsCmCfgBug
- 0x1004f9e4 0x66 _L1w_DevPsrCmHandle
- 0x1004fa4a 0x50 _L1w_DevPsrCalcRlsTxRxTimeDiff
- 0x1004fa9a 0x9a _L1w_DevPsrTimingAdj
- 0x1004fb34 0x182 _L1w_DevPsrUpdateRlPos
- 0x1004fcb6 0x53 _L1w_DevPsrFmoHandle
- 0x1004fd09 0x170 _L1w_DevPsrRdPeakInfoS
- 0x1004fe79 0xaf _L1w_DevDlsPsrSidelobeSurp
- 0x1004ff28 0x10 _L1w_DevDlsPsrFingerSidelobeSurp
- 0x1004ff38 0xb2 _L1w_DevDlsPsrCorasePathDetect
- 0x1004ffea 0x3d _L1w_DevDlsPsrFindStrongFiger
- 0x10050027 0x46 _L1w_DevDlsPsrUpdateFigerTable
- 0x1005006d 0x152 _L1w_DevDlsPsrStrongFigerPathDetect
- 0x100501bf 0x149 _L1w_DevDlsPsrPathDect
- 0x10050308 0x3b _L1w_DevPsrRssiNormal
- 0x10050343 0x99 _L1w_DevDlsPsrUpdateFingerPos
- 0x100503dc 0x12 _L1w_DevDlsPsrCalcMrtrDiff
- 0x100503ee 0x23 _L1w_DevDlsPsrCalcMrtrAver
- 0x10050411 0x31 _L1w_DevDlsPsrSortMinRange
- 0x10050442 0x31 _L1w_DevDlsPsrSortMinRange1
- 0x10050473 0x70 _L1w_DevDlsPsrSynProtect
- 0x100504e3 0x24 _L1w_DevPsrBackWardProtect
- 0x10050507 0x26 _L1w_DevPsrForwardProtect
- 0x1005052d 0x19b _L1w_DevDlsPsrFingerPeakUpdate
- 0x100506c8 0x18 _L1w_DevPsrSortMinValue
- 0x100506e0 0x18 _L1w_DevDlsPsrSortMaxValue
- 0x100506f8 0x14c _L1w_DevPsrCandidatefingerUpdate
- 0x10050844 0xb3 _L1w_DevDlsPsrFingerPeakSelect
- 0x100508f7 0x72 _L1w_DevDlsPsrCalcDpchTiming
- 0x10050969 0x2f _L1w_DevPsrFinPeakNormal
- 0x10050998 0x38 _L1w_DevPsrAntFinPeakNormal
- 0x100509d0 0x3b _L1w_DevDlsPsrSelectValidFinger
- 0x10050a0b 0x98 _L1w_DevDlsPsrCalcDpchBaseTiming
- 0x10050aa3 0x47 _L1w_DevDlsPsrSortRtxFinger
- 0x10050aea 0xb _L1w_DevPsrGetDchStartPsrFlag
- 0x10050af5 0x150 _L1w_DevDlsPsrSelectRtxFinger
- 0x10050c45 0x93 _L1w_DevDlsPsrSelectNcellFinger
- 0x10050cd8 0xc8 _L1w_DevDlsPsrSortDpaFirst
- 0x10050da0 0xf6 _L1w_DevDlsPsrNewFingerMapping
- 0x10050e96 0xd4 _L1w_DevDlsPsrAdrWindowUpdateS
- 0x10050f6a 0xc _L1w_DevDlsPsrSendAdrFingerInfoS
- 0x10050f76 0xd0 _L1w_DevPsrSelSeaWindowFinInfoS
- 0x10051046 0x47 _L1w_DevPsrSelNewSearchWindowS
- 0x1005108d 0x21 _L1w_DevPsrIsSearchWindowPath
- 0x100510ae 0x28 _L1w_DevPsrCalcSearchWindowSum
- 0x100510d6 0x15 _L1w_DevDlsPsrCalcFingerPeakSum
- 0x100510eb 0x38 _L1w_DevPsrSortFirstFinger
- 0x10051123 0x23 _L1w_DevDlscalcPosOff
- 0x10051146 0x1e3 _L1w_DevDlsChangedMasterRlTiming
- 0x10051329 0x13 _L1w_DevDlsPsrFingerCmp
- 0x1005133c 0x12 _L1w_DevDlsPsrFingerLessThan
- 0x1005134e 0x8 _TestZero
- .text 0x10051356 0x5c1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_plus.o)
- 0x10051356 0x8 _L1w_DevHsupaFachFdpchOffset
- 0x1005135e 0xb _L1w_DevHsupaIsEfachActive
- 0x10051369 0x35 _L1w_DevHsupaRtxEdchResInd
- 0x1005139e 0x16 _L1w_DevHsupaFachToPsrInd
- 0x100513b4 0x52 _L1w_DevHsupaFachConfigReq
- 0x10051406 0x3c _L1w_DevHsupaFachCpErntiInfo
- 0x10051442 0xa5 _L1w_DevHsupaFachConfigProc
- 0x100514e7 0x21 _L1w_DevHsupaFachRelReq
- 0x10051508 0x46 _L1w_DevHsupaFachRelProc
- 0x1005154e 0x26 _L1w_DevHsupaErntiUpdateReq
- 0x10051574 0x24 _L1w_DevHsupaErntiUpdateProc
- 0x10051598 0x21 _L1w_DevHsupaFachNoDataReq
- 0x100515b9 0x7e _L1w_DevHsupaFachNoDataProc
- 0x10051637 0x96 _L1w_DevHsupaFachGetRgHiChanInfo
- 0x100516cd 0x4a _L1w_DevHsupaFachCfn2NetTime
- 0x10051717 0x9b _L1w_DevHsupaFachAddTpu2ms
- 0x100517b2 0x6b _L1w_DevHsupaFachAddTpu10ms
- 0x1005181d 0x22 _L1w_DevHsupaFachAddTpu
- 0x1005183f 0xe _L1w_DevHsupaFachIsMacInitTrans
- 0x1005184d 0x1d _L1w_DevHsupaFachAddTpuSubInt
- 0x1005186a 0x88 _L1w_DevHsupaFachEdchResProc
- 0x100518f2 0x25 _L1w_DevHsupaFachReset
- .text 0x10051917 0x1833 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
- 0x10051917 0x21 _L1w_SetWmodeLpcMacroValue
- 0x10051938 0x8 _L1w_DevSleepSetCfunFlg
- 0x10051940 0x13 _L1w_PosCmp
- 0x10051953 0x1c _L1w_DevLpcDvfs
- 0x1005196f 0x2b _L1W_DevSleepLpmInspectInit
- 0x1005199a 0x87 _L1w_DevUeTurnOn3sNoLpc
- 0x10051a21 0xe _l1w_DevLpcSetAdjLpmFrmIntFlg
- 0x10051a2f 0xe _l1w_DevLpcGetAdjLpmFrmIntFlg
- 0x10051a3d 0xf _L1w_DevLpcSetSleepSubSt
- 0x10051a4c 0x10 _L1w_DevLpcGetSleepFlg
- 0x10051a5c 0x85 _L1w_DevLpcDpaRecover
- 0x10051ae1 0x1f _L1w_DevLpcDrxRecover
- 0x10051b00 0x93 _L1w_DevLpcClkDevCtrl
- 0x10051b93 0x3d _l1w_DevLpcClkInit
- 0x10051bd0 0xa4 _L1w_DevLpcPwrDevCtrl
- 0x10051c74 0x2d _l1w_DevLpcPwrInit
- 0x10051ca1 0x7d _L1w_DevSleepNoLpc
- 0x10051d1e 0xa2 _L1w_DevLpcLpmIntCheck
- 0x10051dc0 0x124 _L1w_DevLpcSendIcp
- 0x10051ee4 0x10 _L1w_DevLpcGetWakeUpType
- 0x10051ef4 0x2f _L1w_LpcRegionJudge
- 0x10051f23 0x4a _L1w_DevLpcSerIdleLen
- 0x10051f6d 0x6 _L1w_LpcGetLpcDbAddress
- 0x10051f73 0x23 _L1w_LpcCalcLen
- 0x10051f96 0x46 _L1w_LpcPosMove
- 0x10051fdc 0xb5 _L1w_DevLpcCalPreSyncInfo
- 0x10052091 0x43 _L1w_DevLpcIsPiPchOffsetLen
- 0x100520d4 0x1ac _L1w_SchedGapGetSleepEnLen
- 0x10052280 0x77 _L1w_DevLpcCalSleepInfo
- 0x100522f7 0x7b _L1W_DevLpcGetWSleepLen
- 0x10052372 0x92 _L1w_DevLpcUpdateWakeFlg
- 0x10052404 0x14e _L1w_DevLpcSyncWkUpOpenRf
- 0x10052552 0xa _L1w_DevSleepGetPiEndPos
- 0x1005255c 0x7d _L1W_LPNoSleepAPeriod
- 0x100525d9 0x8f _L1W_DevLpcPwrPrintInfo
- 0x10052668 0x18 _L1w_DevSleepCloseIsAbleSleep
- 0x10052680 0x2a9 _L1W_DevSleepLpmInspect
- 0x10052929 0x4f _L1w_DevLpcWakeTimeCheck
- 0x10052978 0x9 _L1W_LPNoSleepEndSsfnInit
- 0x10052981 0x5e _L1W_LPDataInit
- 0x100529df 0x71 _L1W_LPInit
- 0x10052a50 0x37 _L1W_LpcCfgSocWkupInt
- 0x10052a87 0x1b _L1W_LpcDisSocWkupInt
- 0x10052aa2 0x16 _L1W_WakeupIsr
- 0x10052ab8 0x8 _L1W_GetNtSsfn
- 0x10052ac0 0x4 _L1w_DevSleepPreSyncPiOffset
- 0x10052ac4 0xd _L1W_DevSleepQueryAllowbit
- 0x10052ad1 0x335 _L1W_ModemLpcSleep
- 0x10052e06 0x344 _L1W_ModemLpcWakeup
- .text 0x1005314a 0x1519 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
- 0x1005314a 0x39 _L1w_DevDlsAfcReset
- 0x10053183 0x19 _L1w_DevDlsAfcInit
- 0x1005319c 0x56 _L1w_DevAfcBchCorrCalEachSlot
- 0x100531f2 0x23 _L1w_DevAfcNormalToAfc
- 0x10053215 0x20 _L1w_DevAfcToNormal
- 0x10053235 0xf _L1w_DevAfcFormatCheck
- 0x10053244 0x6 _L1w_DevAfcSubFunc1ForAdd
- 0x1005324a 0x27 _L1w_DevAfcSubFunc2ForAdd
- 0x10053271 0x75 _L1w_DevAfcAdd
- 0x100532e6 0x60 _L1w_DevAfcDiv
- 0x10053346 0x24 _L1w_DevAfcMultip
- 0x1005336a 0xf _L1w_DevAfcCompABS
- 0x10053379 0xfe _L1w_DevAfcCalcPhaseErr
- 0x10053477 0x36 _L1w_DevAfcCalcFreqcenErr
- 0x100534ad 0x1c _L1w_DevAfcLockCheck
- 0x100534c9 0xa6 _L1w_DevAfcBchFoePostProc
- 0x1005356f 0x44 _L1w_DevDlsAfcResultValid
- 0x100535b3 0x31 _L1w_DevAfcFoeAdjResultLim
- 0x100535e4 0x42 _L1w_DevAfcFoeResultLimit
- 0x10053626 0x1c _L1w_DevAfcIQFilterProc
- 0x10053642 0x72 _L1w_DevAfcForBchProc
- 0x100536b4 0x26 _L1w_DevAfcStateTransfer
- 0x100536da 0x64 _L1w_DevAfcRxFoePostProc
- 0x1005373e 0x13 _L1w_DevAfcCalcFingerPower
- 0x10053751 0xab _L1w_DevAfcFingerFoeAdp
- 0x100537fc 0x7b _L1w_DevAfcFingerSortByPeak
- 0x10053877 0x27b _L1w_DevAfcForRxProc
- 0x10053af2 0x27 _L1w_DevAfcSendFreqMsgToL1s
- 0x10053b19 0x29 _L1w_DevAfcBchReq
- 0x10053b42 0x2c _L1w_DevAfcRxReq
- 0x10053b6e 0x26 _L1w_DevAfcRxCrcFlagReq
- 0x10053b94 0x28 _L1w_DevAfcStateChangeReq
- 0x10053bbc 0x97 _L1w_DevAfcRxDataAccu
- 0x10053c53 0xa _L1w_DevAfcVcoTimeSet
- 0x10053c5d 0xb5 _L1w_DevAfcCalcParam
- 0x10053d12 0xd _L1w_DevAfcIsInStableSt
- 0x10053d1f 0x11 _L1w_DevAfcRxCrcFlagProc
- 0x10053d30 0x37 _L1w_DevAfcLockHandle
- 0x10053d67 0x4d _L1w_DevAfcNeedAdj
- 0x10053db4 0x72 _L1w_DevAfcSaveStableVco
- 0x10053e26 0x21 _L1w_DevAfcMasteStChange
- 0x10053e47 0x11 _L1w_DevAfcGetRxCrc
- 0x10053e58 0x31 _L1w_DevAfcGetAfcCellEcIo
- 0x10053e89 0x43 _L1w_DevAfcRxDataReqProc
- 0x10053ecc 0x52 _L1w_DevAfcGetNCellAfcPt
- 0x10053f1e 0xa _L1w_DevAfcGetSystemAfc
- 0x10053f28 0xb _L1w_DevAfcGetNCellAbsAfc
- 0x10053f33 0x1b _L1w_DevAfcGetNCellRelativeAfc
- 0x10053f4e 0x58 _L1w_DevAfcUpdateNCellAfc
- 0x10053fa6 0x8 _L1w_DevAfcSetWorkCellInfo
- 0x10053fae 0xa _L1w_DevAfcGetWorkCellInfo
- 0x10053fb8 0x50 _L1w_DevAfcIsSystemAfc
- 0x10054008 0xa2 _L1w_DevAfcNcellAfcPostProc
- 0x100540aa 0x3 _L1w_DevAfcSetNCellAbsAfc
- 0x100540ad 0xa5 _L1w_DevAfcRlsAloneProc
- 0x10054152 0x131 _L1w_DevAfcCalcRlOwnFoe
- 0x10054283 0xf _L1w_DevAfcClearNcellAfc
- 0x10054292 0x1e _L1w_DevAfcCalcFilterPara
- 0x100542b0 0x66 _L1w_DevAfcDpaIqRotateProc
- 0x10054316 0x1d _L1w_DevAfcNcellAdjLimit
- 0x10054333 0xc _L1w_DevAfcNormDiffValue
- 0x1005433f 0x11 _L1w_DevAfcSaveDpaInfo
- 0x10054350 0x38 _L1w_DevAfcSetDpaIqRotate
- 0x10054388 0x4f _L1w_DevAfcCalcSlotWeight
- 0x100543d7 0x15 _L1w_DevAfcInitNcellData
- 0x100543ec 0x2e _L1w_DevAfcNcellUpByEcIo
- 0x1005441a 0x1f _L1w_DevAfcRestartReq
- 0x10054439 0x22 _L1w_DevAfcRestartLockCheck
- 0x1005445b 0x29 _L1w_DevAfcWriteBackVco
- 0x10054484 0x4f _L1w_DevAfcSaveWMode
- 0x100544d3 0xa7 _L1w_DevAfcSlaveAfcMangement
- 0x1005457a 0x15 _L1w_DevAfcLimitSlaveVco
- 0x1005458f 0x15 _L1w_CleanSlaveAfcIRAMBuf
- 0x100545a4 0x32 _L1w_WriteMasterAfcInfo
- 0x100545d6 0x20 _L1w_ReadMasterAfcInfo
- 0x100545f6 0x6d _L1w_DevChangeAndUpdateAfc
- .text 0x10054663 0xf2e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
- 0x10054663 0x129 _L1w_DevTpuRt1SampleCompst
- 0x1005478c 0x77 _L1w_DevTpuReset
- 0x10054803 0x10 _L1w_DevTpuTaskIdTransForm
- 0x10054813 0x5e _L1w_DevTpuAddFixedEvent
- 0x10054871 0x1a _L1w_DevTpuAddFixedCycleEvent
- 0x1005488b 0x15 _L1w_DevTpuDelFixedCycleEvent
- 0x100548a0 0x21 _L1w_DevTpuUpdateVarNtEvent
- 0x100548c1 0x20 _L1w_DevTpuUpdateVarRtEvent
- 0x100548e1 0xfd _L1w_DevTpuAddVarNtEvent
- 0x100549de 0xdf _L1w_DevTpuAddVarRtEvent
- 0x10054abd 0x46 _L1w_DevTpuDelFixedEvent
- 0x10054b03 0x62 _L1w_DevTpuDelVarNtEvent
- 0x10054b65 0x3e _L1w_DevTpuDelVarRtEvent
- 0x10054ba3 0x65 _L1w_DevTpuGetRealTime
- 0x10054c08 0x8e _L1w_DevTpuGetRtForWakeUp
- 0x10054c96 0x50 _L1w_DevTpuGetNetTime
- 0x10054ce6 0xa4 _L1w_DevTpuGetAllTime
- 0x10054d8a 0x80 _L1w_DevTpuNtFixedEventProc
- 0x10054e0a 0xdd _L1w_DevTpuNtVarEventProc
- 0x10054ee7 0xf6 _L1w_DevTpuRtEventProc
- 0x10054fdd 0x59 _L1w_DevTpuMacroAdjust
- 0x10055036 0x56 _L1w_DevTpuMicroAdjust
- 0x1005508c 0x1a _L1w_DevTpuMicroAdjustForSleep
- 0x100550a6 0x56 _L1w_DevTpuMicroAdjSetPreSyncFlag
- 0x100550fc 0x5 _L1w_DevTpuAdjEventProc
- 0x10055101 0xb _L1w_DevTpuSetDoff
- 0x1005510c 0x7 _L1w_DevTpuGetDoff
- 0x10055113 0xa _L1w_DevTpuSfn2Cfn
- 0x1005511d 0x25 _L1w_DevTpuCfn2Sfn
- 0x10055142 0x1b _L1w_DevTpuGetNtSSFN
- 0x1005515d 0x1c _L1w_DevTpuGetRtSSFN
- 0x10055179 0x17 _L1w_DevTpuGetSSFN
- 0x10055190 0xe _L1w_DevTpuGetCurCFN
- 0x1005519e 0x7 _L1w_DevTpuSfn2Ssfn
- 0x100551a5 0x7 _L1w_DevTpuCfn2Ssfn
- 0x100551ac 0x27 _L1w_DevTpuRt2Nt
- 0x100551d3 0x69 _L1w_DevTpuAddCnt
- 0x1005523c 0x34 _L1w_DevTpuCalNt2RtOffset
- 0x10055270 0x2c _L1w_DevTpuMicroSsfnJumpPatch
- 0x1005529c 0x7a _L1w_DevTpuCheckMicroSsfnJump
- 0x10055316 0x21 _L1w_DevTpuMicroSsfnJumpPro
- 0x10055337 0x77 _L1w_DevTpuCheckMicroSsfnBack
- 0x100553ae 0x1f _L1w_DevTpuMicroSsfnBackPro
- 0x100553cd 0x32 _L1w_DevTpuNtSSfnCfnUpdate
- 0x100553ff 0x14 _L1w_DevTpuRtSSfnUpdate
- 0x10055413 0x32 _L1w_DevTpuCalcNtUpdateTime
- 0x10055445 0x31 _L1w_DevTpuCalcRtUpdateTime
- 0x10055476 0x1e _L1w_DevTpuBase2Norm
- 0x10055494 0x43 _L1w_DevTpuNorm2Base
- 0x100554d7 0x17 _L1w_DevTpuCalRt2NtOffset
- 0x100554ee 0x27 _L1w_DevTpuNt2Rt
- 0x10055515 0x7c _L1w_DevTpuSubCnt
- .text 0x10055591 0x9a4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
- 0x10055591 0x6 _L1w_DevDbAfcAddrGet
- 0x10055597 0x6 _L1w_DevDbIscpAddrGet
- 0x1005559d 0x6f _L1w_DevDbRtxUpaRlIscpReport
- 0x1005560c 0xa _L1w_DevDbRtxPcRlIscpReport
- 0x10055616 0x7 _L1w_DevDbSetHsdpaInd
- 0x1005561d 0xb _L1w_DevDbReSetHsdpaInd
- 0x10055628 0x3d _L1w_DevDbUpdateHsdpaInd
- 0x10055665 0x6 _L1w_DevDbGetHsdpaInd
- 0x1005566b 0x26 _L1w_DevDbRtxRxSirSet
- 0x10055691 0x26 _L1w_DevDbRtxRxSirGet
- 0x100556b7 0x2d _L1w_DevDbBchWriteAfcData
- 0x100556e4 0x34 _L1w_DevAfcReadDataFromBch
- 0x10055718 0x3a9 _L1w_DevDlsAfcReadDataFromRx
- 0x10055ac1 0x43 _L1w_DevDbGetInitXValue
- 0x10055b04 0x42 _L1w_DevDbGetInitYValue
- 0x10055b46 0x1e _L1w_DevDbGetInitValue
- 0x10055b64 0x45 _L1w_DevDbCodingPara
- 0x10055ba9 0x43 _L1w_DevDbTrchTtiMap
- 0x10055bec 0x28 _L1w_DevDbTrchMaxMinTti
- 0x10055c14 0x7 _L1w_DevDbTrchMaxTtiGet
- 0x10055c1b 0x8 _L1w_DevDbTrchMinTtiGet
- 0x10055c23 0x6 _L1w_DevDbGetPichCfg
- 0x10055c29 0x6 _L1w_DevDbGetPchCfg
- 0x10055c2f 0x6 _L1w_DevDbGetFachCfg
- 0x10055c35 0x6 _L1w_DevDbGetDldpchCfg
- 0x10055c3b 0x6 _L1w_DevDbGetFdpchCfg
- 0x10055c41 0x32 _L1w_DevDbGetSchCodeGrp
- 0x10055c73 0x3a _L1w_DevDbSaveCirData
- 0x10055cad 0xb _L1w_DevDbClearCirData
- 0x10055cb8 0x6 _L1w_DevDbGetCirDataAddr
- 0x10055cbe 0x6 _L1w_DevDbGetFingerMaskBufAddr
- 0x10055cc4 0x1b _L1w_DevDbRtxReportToMac
- 0x10055cdf 0x21 _L1w_DevDbHspaReportToMac
- 0x10055d00 0x1d _L1w_DevDbSetHsdpaToMacInfo
- 0x10055d1d 0x21 _L1w_DevDbSetHsupaToMacInfo
- 0x10055d3e 0xb _L1w_DevDbClrHspaToMacInfo
- 0x10055d49 0x1 _L1w_DevDbPcReportToMac
- 0x10055d4a 0x9 _L1w_SchedResIsBand8Freq
- 0x10055d53 0x15 _L1w_DevDbGetAiSignSeries
- 0x10055d68 0x27 _L1w_DevDbPiValHandle
- 0x10055d8f 0x26 _L1w_DevDbCalcPiVal
- 0x10055db5 0x1c _L1w_DevRtxRxPiAiFloatAdd
- 0x10055dd1 0x6 _L1w_DevDbGetHspaPlusFachPsCmd
- 0x10055dd7 0x12 _L1w_DevDbPsSubFrmInt
- 0x10055de9 0x24 _L1w_DevDbSubFrmInt
- 0x10055e0d 0xe _L1w_DevDbSetHarqFlag
- 0x10055e1b 0xc _L1w_DevDbInitHsdpaAntSwitchInfo
- 0x10055e27 0x7 _L1w_DevDbSetHsdpaAntSwitchFlg
- 0x10055e2e 0x7 _L1w_DevDbGetHsdpaAntSwitchFlg
- 0x10055e35 0x8 _L1w_DevDbSetHsdpaAntNum
- 0x10055e3d 0x8 _L1w_DevDbGetHsdpaAntNum
- 0x10055e45 0x1a _L1w_DevDbHsdpaJudge2Rto1R
- 0x10055e5f 0x1c _L1w_DevDbHsdpaJudge1Rto2R
- 0x10055e7b 0x9 _L1w_DevDbAddHsscchCnt
- 0x10055e84 0x17 _L1w_DevDbHsscchSchedCnt
- 0x10055e9b 0x9 _L1w_DevDbAddHsscchCorrectCnt
- 0x10055ea4 0xa _L1w_DevDbAddHsscchErrorCnt
- 0x10055eae 0x9 _L1w_DevDbClearHsscchErrorCnt
- 0x10055eb7 0xa _L1w_DevDbAddSnrHighCnt
- 0x10055ec1 0x9 _L1w_DevDbClearSnrHighCnt
- 0x10055eca 0xa _L1w_DevDbAddSnrLowCnt
- 0x10055ed4 0x9 _L1w_DevDbClearSnrLowCnt
- 0x10055edd 0xd _L1w_DevDbSet1R2RState
- 0x10055eea 0xc _L1w_DevDbSetLas1R2RState
- 0x10055ef6 0x11 _L1w_DevDbIs1RTo2R
- 0x10055f07 0x7 _L1w_DevDbGet1R2RState
- 0x10055f0e 0xb _L1w_DevDbGet1R2RAntNum
- 0x10055f19 0x7 _L1w_DevSetSystemAntNum
- 0x10055f20 0x7 _L1w_DevGetSystemAntNum
- 0x10055f27 0x7 _L1w_DevDbSetTxPower
- 0x10055f2e 0x7 _L1w_DevDbGetTxPower
- .text 0x10055f35 0x1833 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
- 0x10055f35 0xf _L1w_DevRtxRxInit
- 0x10055f44 0x29 _L1w_DevRtxRxReset
- 0x10055f6d 0x87 _L1w_DevRtxRxAddTpuEvent
- 0x10055ff4 0x36 _L1w_DevRtxRxDelTpuEvent
- 0x1005602a 0x1c _L1w_DevRtxRxDelFactorTpuInt
- 0x10056046 0x80 _L1w_DevRtxRxSwapFinger
- 0x100560c6 0x10f _L1w_DevRtxRxFingerSort
- 0x100561d5 0x72 _L1w_DevRtxRxFingerSelect
- 0x10056247 0x75 _L1w_DevRtxRxFingerMsgHandle
- 0x100562bc 0x27 _L1w_DevRtxOfflinePichRelHanlde
- 0x100562e3 0x38 _L1w_DevRtxSetPchCfgState
- 0x1005631b 0x65 _L1w_DevRtxRxPchCfgReqHandle
- 0x10056380 0x5f _L1w_DevRtxRxCompareConfigTime
- 0x100563df 0x1a1 _L1w_DevRtxRxOffLinePichCfg
- 0x10056580 0xcd _L1w_DevRtxRxPichCfgMsgHandle
- 0x1005664d 0x3e _L1w_DevRtxRxPichRelMsgHandle
- 0x1005668b 0x187 _L1w_DevRtxRxPchCfgMsgHandle
- 0x10056812 0x26 _L1w_DevRtxRxPchRelMsgHandle
- 0x10056838 0x157 _L1w_DevRtxRxAichCfgMsgHandle
- 0x1005698f 0x38 _L1w_DevRtxRxAichRelMsgHandle
- 0x100569c7 0x123 _L1w_DevRtxRxFachCfgMsgHandle
- 0x10056aea 0x38 _L1w_DevRtxRxFachRelMsgHandle
- 0x10056b22 0x219 _L1w_DevRtxRxDlDpchCfgMsgHandle
- 0x10056d3b 0x36 _L1w_DevRtxRxDlDpchRelMsgHandle
- 0x10056d71 0x119 _L1w_DevRtxRxFdpchCfgMsgHandle
- 0x10056e8a 0x87 _L1w_DevRtxRxPlusCpCfgMsgHandle
- 0x10056f11 0x38 _L1w_DevRtxRxFdpchRelMsgHandle
- 0x10056f49 0x3 _L1w_DevRtxRxPlusFachTpuHandle
- 0x10056f4c 0x1cc _L1w_DevRtxRxPlusFachCfg
- 0x10057118 0x15b _L1w_DevRtxRxCmCfgMsgHandle
- 0x10057273 0x26 _L1w_DevRtxRxCmAbortMsgHandle
- 0x10057299 0x5a _L1w_DevRtxRxHsscchCfgMsgHandle
- 0x100572f3 0x51 _L1w_DevRtxRxEagchCfgMsgHandle
- 0x10057344 0x9 _L1w_DevRtxRxEagchRelMsgHandle
- 0x1005734d 0x63 _L1w_DevRtxRxRgHiCfgMsgHandle
- 0x100573b0 0x9 _L1w_DevRtxRxRgHiRelMsgHandle
- 0x100573b9 0x45 _L1w_DevRtxRxDrxMsgHandle
- 0x100573fe 0x12e _L1w_DevRtxRxMsgHandle
- 0x1005752c 0x6 _L1w_DevRtxRxTrchInfoGet
- 0x10057532 0x16 _L1w_DevRtxRxTurboUse
- 0x10057548 0xed _L1w_DevRtxRxDlStatEng
- 0x10057635 0x6 _L1w_DevRtxRxDpchPhyInfoGet
- 0x1005763b 0x6 _L1w_DevRtxRxIntCfgParaGet
- 0x10057641 0xf _L1w_DevRtxRxDrxSlotCheck
- 0x10057650 0x28 _L1w_DevRtxRxCmSlotCheck
- 0x10057678 0x8c _L1w_DevRtxRxCpCmSlotCheck
- 0x10057704 0x19 _L1w_DevRtxRxGetSlotId
- 0x1005771d 0xa _L1w_DevRtxRxDrxSlotClr
- 0x10057727 0x6 _L1w_DevRtxRxTpcInfoGet
- 0x1005772d 0x6 _L1w_DevRtxRxSccpchPhyInfoGet
- 0x10057733 0x6 _L1w_DevRtxRxAgchPhyInfoGet
- 0x10057739 0x6 _L1w_DevRtxRxCfgInfoGet
- 0x1005773f 0xd _L1w_DevRtxRxCfgRlCntGet
- 0x1005774c 0x1c _L1w_DevRtxRxRlPrimSrcGet
- .text 0x10057768 0x516 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_ds.o)
- 0x10057768 0xd _L1w_DevRtxRxDsReset
- 0x10057775 0x25 _L1w_DevRtxDsMsgHandle
- 0x1005779a 0x72 _L1w_DevRtxDsStageHandle
- 0x1005780c 0x84 _L1w_DevRtxDsStart
- 0x10057890 0x9 _L1w_DevRtxDsStop
- 0x10057899 0x3d _L1w_DevRtxDsCrcCalc
- 0x100578d6 0x62 _L1w_DevRtxDsStep1Handle
- 0x10057938 0x7c _L1w_DevRtxDsQosStep1
- 0x100579b4 0x41 _L1w_DevRtxDsStep2Handle
- 0x100579f5 0xcc _L1w_DevRtxDsQosStep2
- 0x10057ac1 0x2a _L1w_DevRtxRxDsPostInd
- 0x10057aeb 0x3d _L1w_DevRtxDsInsyncInd
- 0x10057b28 0x41 _L1w_DevRtxDsOutsyncInd
- 0x10057b69 0x19 _L1w_DevRtxRxDsIsCrcExist
- 0x10057b82 0x1f _L1w_DevRtxRxDsIsCrcOk
- 0x10057ba1 0x16 _L1w_DevRtxRxDsCurTtiParaClr
- 0x10057bb7 0x16 _L1w_DevRtxRxDsLast20CrcFalse
- 0x10057bcd 0xb _L1w_DevRtxRxDsIsPostOk
- 0x10057bd8 0x14 _L1w_DevRtxRxDsIsN312Ok
- 0x10057bec 0x31 _L1w_DevRtxRxDsSetTpcData
- 0x10057c1d 0x1d _L1w_DevRtxRxDsGetSyncSt
- 0x10057c3a 0x44 _L1w_DevRtxRxDsUlSendState
- .text 0x10057c7e 0x37c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
- 0x10057c7e 0xe _L1w_DrvRfcSingedDataMaxLimit
- 0x10057c8c 0xc _L1w_DrvRfcUnSingedDataMaxLimit
- 0x10057c98 0x26 _L1w_DrvRfcS16ToFastFloat
- 0x10057cbe 0x3e _L1w_DrvRfcS16FastFloatDiv
- 0x10057cfc 0xd _L1w_DrvRfcFastFloatToS16
- 0x10057d09 0x3e _L1w_DrvRfcAgcgain2ManExp
- 0x10057d47 0x71 _L1w_DrvRfcDcCalcSingleCh
- 0x10057db8 0x29 _L1w_DrvRfcDcCalc
- 0x10057de1 0x37 _L1w_DrvRfcDcSet
- 0x10057e18 0x1c _L1w_DevRfcDcEstEn
- 0x10057e34 0xac _L1w_DrvRfcIQCalcSingleCh
- 0x10057ee0 0x2e _L1w_DrvRfcIQSet
- 0x10057f0e 0x11 _L1w_DrvRfcIQCalc
- 0x10057f1f 0x4f _L1w_DrvRfcDagcCalc
- 0x10057f6e 0x8c _L1w_DrvRfcDagcSet
- .text 0x10057ffa 0x421 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o)
- 0x10057ffa 0xa _L1w_DrvPIAIClkGateEnable
- 0x10058004 0xa _L1w_DrvPIAIClkGateDisable
- 0x1005800e 0x10 _L1w_DrvPIAISttdCfg
- 0x1005801e 0xc _L1w_DrvAiOnLineEn
- 0x1005802a 0xa _L1w_DrvAIonLineDisable
- 0x10058034 0xc _L1w_DrvPIAfcoffLineEnable
- 0x10058040 0x12 _L1w_DrvPIAfcoffLineDisable
- 0x10058052 0xf _L1w_DrvPiAfcIntModeCfg
- 0x10058061 0xe _L1w_DrvGetPiAiEnPara
- 0x1005806f 0x9 _L1w_DrvGetPiAiIntMode
- 0x10058078 0xe _L1w_DrvGetConfigState
- 0x10058086 0xf _L1w_DrvPiAIFirOrderCfg
- 0x10058095 0x21 _L1w_DrvPiSysmbolLenCfg
- 0x100580b6 0x9 _L1w_DrvAlphaCfg
- 0x100580bf 0xa _L1w_DrvAfcCompensateEnable
- 0x100580c9 0xa _L1w_DrvAfcCompensateDisable
- 0x100580d3 0x14 _L1w_DrvAfcRotateParaCfg
- 0x100580e7 0xd _L1w_DrvPiAiFingerParaCfg
- 0x100580f4 0x16 _L1w_DrvPiOffsetCfg
- 0x1005810a 0x23 _L1w_DrvPiAiOvsfCfg
- 0x1005812d 0xf _L1w_DrvAfcBestFingerIndexCfg
- 0x1005813c 0x16 _L1w_DrvAiSeqIndexCfg
- 0x10058152 0xa _L1w_DrvPiAiCfgOver
- 0x1005815c 0x15 _L1w_DrvReadCpichPower
- 0x10058171 0xd _L1w_DrvReadAiResult
- 0x1005817e 0x3b _L1w_DrvReadConfigTime
- 0x100581b9 0x3e _L1w_DrvSetConfigTime
- 0x100581f7 0x1f _L1w_DrvPiAiReadCpichRam
- 0x10058216 0xa _L1w_DrvPiAiReadAiSymbolRam
- 0x10058220 0x1b _L1w_DrvPiAiReadSymbolRam
- 0x1005823b 0xa _L1w_DrvEAiReadAmRam
- 0x10058245 0x18 _L1w_DrvAiReadAmRam
- 0x1005825d 0xff _L1w_DrvPiAiAichCfg
- 0x1005835c 0x12 _L1w_DrvPiAiAichRel
- 0x1005836e 0x82 _L1w_DrvOffPichCfg
- 0x100583f0 0x2b _L1w_DrvOffPichRel
- .text 0x1005841b 0x2b7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_sleep.o)
- 0x1005841b 0x9 _L1w_DrvSleepLpmCtrPwrOn
- 0x10058424 0x1c _L1w_DrvLpcModemIntCtrl
- 0x10058440 0x3d _L1w_DrvLpcLpmConfPosCal
- 0x1005847d 0x38 _L1W_DrvLpcCfgSocWkupInt
- 0x100584b5 0x15 _L1W_DrvLpcCfgModemWkupInt
- 0x100584ca 0xe _L1w_DrvLpcModemWakeUpIntCtrl
- 0x100584d8 0xe _L1w_DrvLpcSocWakeUpIntCtrl
- 0x100584e6 0x17 _L1w_DrvLpcLpmSoftReset
- 0x100584fd 0x1a _L1w_DrvLpcClearInt
- 0x10058517 0xe _L1w_DrvLpcLpmSfIntCtrl
- 0x10058525 0x9 _L1w_DrvLpcIsLpmSfIntEn
- 0x1005852e 0x8c _L1w_DrvLpcSetLpmFrmInt
- 0x100585ba 0x2b _L1w_DrvLpcSetLpmAdjustFactor
- 0x100585e5 0x87 _L1w_DrvLpcLpmIntPwrCtrl
- 0x1005866c 0x1f _L1w_DrvLpcGetWNtTimeFromLpm
- 0x1005868b 0x2a _L1w_DrvLpcIcpSendForPsm
- 0x100586b5 0xe _L1w_DrvLpcSetCampOnFlg
- 0x100586c3 0x8 _L1w_DrvLpcSetSleepFlag
- 0x100586cb 0x7 _L1w_DrvLpcGetSleepFlag
- .text 0x100586d2 0x39d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o)
- 0x100586d2 0x1c _L1_DrvCsrInit
- 0x100586ee 0x30 _L1_DrvCsrReset
- 0x1005871e 0x1c _L1w_DevCsrStep1Reset
- 0x1005873a 0x5f _L1w_DrvCsrTopCfg
- 0x10058799 0x82 _L1w_DrvCsrSlotSyncCfg
- 0x1005881b 0x4b _L1w_DrvCsrIcCfg
- 0x10058866 0x1 _L1w_DrvCsrFrameSyncCfg2A
- 0x10058867 0x1 _L1w_DrvCsrFrameSyncCfg2B
- 0x10058868 0x1 _L1w_DrvCsrScrambleSrchCfg
- 0x10058869 0x66 _L1w_DrvCsrFullscanKscCfg
- 0x100588cf 0x44 _L1w_DrvCsrFullscanUnKscCfg
- 0x10058913 0x83 _L1w_DrvCsrFullscanCfg
- 0x10058996 0x94 _L1w_DrvCsrReadSlotSync
- 0x10058a2a 0x1 _L1w_DrvCsrStep1ReadMaxPos
- 0x10058a2b 0x1 _L1w_DrvCsrReadFrameSync2A
- 0x10058a2c 0x1 _L1w_DrvCsrReadFrameSync2B
- 0x10058a2d 0x1d _L1w_DrvCsrCmpFloat
- 0x10058a4a 0x1 _L1w_DrvCsrReadScrambleCode
- 0x10058a4b 0x24 _L1w_DrvCsrReadFs
- .text 0x10058a6f 0x306 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
- 0x10058a6f 0x9 _L1w_DrvSetTop01GdtrHdtrBitSet
- 0x10058a78 0xa _L1w_DrvSetTop01GdtrHdtrBitclr
- 0x10058a82 0x9 _L1w_DrvSetTopEDmaIntBypassBitSet
- 0x10058a8b 0xa _L1w_DrvSetTopEDmaIntBypassBitclr
- 0x10058a95 0x1c _L1w_DrvResetTopViterbi
- 0x10058ab1 0x6 _L1w_DrvGetTop0OSoftResetRegAddr
- 0x10058ab7 0x9 _L1w_DrvTop00SoftResetBitSet
- 0x10058ac0 0xa _L1w_DrvTop00SoftResetBitClr
- 0x10058aca 0x9 _L1w_DrvTop10TpuRakeIntMaskBitSet
- 0x10058ad3 0xa _L1w_DrvTop10TpuRakeIntMaskBitClr
- 0x10058add 0x9 _L1w_DrvTop11RakeDfeRfcIntMaskBitSet
- 0x10058ae6 0xa _L1w_DrvTop11RakeDfeRfcIntMaskBitClr
- 0x10058af0 0x9 _L1w_DrvTop12TpuCsrAdrHsscchIntMaskBitSet
- 0x10058af9 0xa _L1w_DrvTop12TpuCsrAdrHsscchIntMaskBitClr
- 0x10058b03 0x9 _L1w_DrvTop13CsrDtrPsrIntMaskBitSet
- 0x10058b0c 0xa _L1w_DrvTop13CsrDtrPsrIntMaskBitClr
- 0x10058b16 0x9 _L1w_DrvTop14TpuRakeIntStateMaskBitSet
- 0x10058b1f 0xa _L1w_DrvTop14TpuRakeIntStateMaskBitClr
- 0x10058b29 0x9 _L1w_DrvTop15RakeDfeRfcIntStateMaskBitSet
- 0x10058b32 0xa _L1w_DrvTop15RakeDfeRfcIntStateMaskBitClr
- 0x10058b3c 0x9 _L1w_DrvTop16TpuCsrAdrHsscchIntStateMaskBitSet
- 0x10058b45 0xa _L1w_DrvTop16TpuCsrAdrHsscchIntStateMaskBitClr
- 0x10058b4f 0x9 _L1w_DrvTop17CsrDtrPsrIntStateMaskBitSet
- 0x10058b58 0xa _L1w_DrvTop17CsrDtrPsrIntStateMaskBitClr
- 0x10058b62 0xe _L1w_DrvTopCsrDtrPsrIntOpen
- 0x10058b70 0xe _L1w_DrvTopCsrDtrPsrIntClose
- 0x10058b7e 0x8 _L1w_DrvTopGetTop10High16b
- 0x10058b86 0x7 _L1w_DrvTopGetTop10Low16b
- 0x10058b8d 0x8 _L1w_DrvTopGetTop14High16b
- 0x10058b95 0x7 _L1w_DrvTopGetTop14Low16b
- 0x10058b9c 0x7 _L1w_DrvTopGetTop11Low16b
- 0x10058ba3 0x7 _L1w_DrvTopGetTop15Low16b
- 0x10058baa 0x9 _L1w_DrvTopLpcOpenGateClk
- 0x10058bb3 0xa _L1w_DrvTopLpcCloseGateClk
- 0x10058bbd 0xb _L1w_DrvTopClkIsOpen
- 0x10058bc8 0x13 _L1W_DrvTopLpcRegSave
- 0x10058bdb 0x23 _L1W_DrvTopLpcRegRestore
- 0x10058bfe 0x26 _L1w_DrvMcuIntMask
- 0x10058c24 0x26 _L1w_DrvMcuIntUnmask
- 0x10058c4a 0xa _L1w_DrvMcuIntIreqClr
- 0x10058c54 0x5f _L1w_DrvTopIntMask
- 0x10058cb3 0x4f _L1w_DrvTopIntMaskRestore
- 0x10058d02 0x1a _L1w_DrvTopIntClr
- 0x10058d1c 0x59 _L1w_DrvTopIntEng
- .text 0x10058d75 0x20d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
- 0x10058d75 0x25 _L1w_DrvTpuSoftResetCfg
- 0x10058d9a 0x39 _L1w_DrvTpuReset
- 0x10058dd3 0x28 _L1w_DrvTpuInit
- 0x10058dfb 0x39 _L1w_DrvTpuNTIntEnable
- 0x10058e34 0x3a _L1w_DrvTpuNTIntDisable
- 0x10058e6e 0x14 _L1w_DrvTpuRTIntEnable
- 0x10058e82 0x15 _L1w_DrvTpuRTIntDisable
- 0x10058e97 0x11 _L1w_DrvTpuLatchTimeCfg
- 0x10058ea8 0x8 _L1w_DrvTpuRdNTTiming
- 0x10058eb0 0x8 _L1w_DrvTpuRdRTTiming
- 0x10058eb8 0x11 _L1w_DrvTpuNTIntParaCfg
- 0x10058ec9 0x11 _L1w_DrvTpuRTIntParaCfg
- 0x10058eda 0xa _L1w_DrvTpuMacroIntDisble
- 0x10058ee4 0x7 _L1w_DrvTpuMicroAdjParaCfg
- 0x10058eeb 0x8 _L1w_DrvTpuGetNT2RtOffset
- 0x10058ef3 0x8 _L1w_DrvTpuGetNTssfn
- 0x10058efb 0x8 _L1w_DrvTpuGetRTssfn
- 0x10058f03 0x32 _L1w_DrvTpuMacroAdjParaCfg
- 0x10058f35 0x28 _L1W_DrvTpuLpcRegRestore
- 0x10058f5d 0x25 _L1W_DrvTpuLpcRegSave
- .text 0x10058f82 0x431 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o)
- 0x10058f82 0x26 _L1w_DrvTxReset
- 0x10058fa8 0xb _L1w_DrvTxClear
- 0x10058fb3 0x16 _L1w_DrvTxDpxchEnCfg
- 0x10058fc9 0x10 _L1w_DrvTxRamLpEnCfg
- 0x10058fd9 0x10 _L1w_DrvTxScramFixRotateEnCfg
- 0x10058fe9 0x10 _L1w_DrvTxModeTypeCfg
- 0x10058ff9 0x10 _L1w_DrvTxGateClkDisableCfg
- 0x10059009 0x2b _L1w_DrvTxDpxchOffsetCfg
- 0x10059034 0x31 _L1w_DrvTxPreamblePhchCfg
- 0x10059065 0xa _L1w_DrvTxPreamblePhchDisable
- 0x1005906f 0x2d _L1w_DrvTxPrachPhchCfg
- 0x1005909c 0xa _L1w_DrvTxPrachPhchEnable
- 0x100590a6 0xa _L1w_DrvTxPrachPhchDisable
- 0x100590b0 0x10 _L1w_DrvTxSampleTxRegTimeCfg
- 0x100590c0 0x10 _L1w_DrvTxDpcchFbiCfg
- 0x100590d0 0x16 _L1w_DrvTxDpcchTpcCfg
- 0x100590e6 0x43 _L1w_DrvTxDpxchPhchCfg
- 0x10059129 0x30 _L1w_DrvTxPrachSpreaderCfg
- 0x10059159 0x22 _L1w_DrvTxScramblerCfg
- 0x1005917b 0x2a _L1w_DrvTxDpxchOrPrachPwrCfg
- 0x100591a5 0x18 _L1w_DrvTxHsDpcchPwrCfg
- 0x100591bd 0x18 _L1w_DrvTxEdpcchPwrCfg
- 0x100591d5 0x49 _L1w_DrvTxEdpdchPwrCfg
- 0x1005921e 0xc _L1w_DrvTxPreamblePwrCfg
- 0x1005922a 0x111 _L1_DrvTxRfcTest
- 0x1005933b 0x13 _L1w_DrvGetTxDpxchOffset
- 0x1005934e 0x39 _L1w_DrvTxCordicAdjustCfg
- 0x10059387 0x9 _L1w_DrvTxCordicDisable
- 0x10059390 0x23 _L1w_DrvTxCordicEnable
- .text 0x100593b3 0x381 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
- 0x100593b3 0x27 _L1w_DrvMeasReset
- 0x100593da 0x57 _L1w_DrvMeasCfgCellCode
- 0x10059431 0x19 _L1w_DrvMeasParaOverCfg
- 0x1005944a 0x6e _L1w_DrvMeasCfgSpsrStartTime
- 0x100594b8 0x8 _L1w_DrvMeasCfgClkGating
- 0x100594c0 0x60 _L1w_DrvMeasReadResult
- 0x10059520 0x1a _L1w_DrvMeasReadAgc
- 0x1005953a 0xa _L1w_DrvMeasReadSpsrIntSeqNum
- 0x10059544 0x5f _L1w_DrvMeasCompareConfigTime
- 0x100595a3 0x14 _L1w_DrvMeasReadSpsrstatus
- 0x100595b7 0x8 _L1w_DrvMeasOffLineRamparaCfg
- 0x100595bf 0x8 _L1w_DrvMeasOffLineRamMrtrCfg
- 0x100595c7 0x9 _L1w_DrvMeasMeasBufUpdateCfg
- 0x100595d0 0x8 _L1w_DrvMeasWorkModeCfg
- 0x100595d8 0x8 _L1w_DrvMeasOnLineStartSpsrCfg
- 0x100595e0 0xe _L1w_DrvMeasOnLineGetSpsrCfg
- 0x100595ee 0x10 _L1w_DrvMeasOnLineAgc0paraCfg
- 0x100595fe 0x10 _L1w_DrvMeasOnLineAgc1paraCfg
- 0x1005960e 0x35 _L1w_DrvMeasOnLineAgc0StartMrtrCfg
- 0x10059643 0x35 _L1w_DrvMeasOnLineAgc1StartMrtrCfg
- 0x10059678 0x4f _L1w_DrvMeasFrameBoundaryCfg
- 0x100596c7 0x2d _L1w_DrvMeasSpsrParaCfg
- 0x100596f4 0x1c _L1w_DrvMeasCellSttdModeCfg
- 0x10059710 0xa _L1w_DrvMeasClkGatingCfg
- 0x1005971a 0x9 _L1w_DrvMeasSoftPatternCfg
- 0x10059723 0x9 _L1w_DrvMeasPatternModeCfg
- 0x1005972c 0x8 _L1w_DrvMeasCfgOfflineSpsrStartTime
- .text 0x10059734 0x55d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o)
- 0x10059734 0x22 _L1w_DrvHsupaEutrEnable
- 0x10059756 0xa _L1w_DrvHsupaEutrDisable
- 0x10059760 0xe _L1w_DrvHsupaEutrSoftRst
- 0x1005976e 0x13 _L1w_DrvHsupaEutrHarqRamMode
- 0x10059781 0x10 _L1w_DrvHsupaEutrHarqId
- 0x10059791 0xb _L1w_DrvHsupaEutrTtiTwoFlg
- 0x1005979c 0xb _L1w_DrvHsupaEutrTbSize
- 0x100597a7 0x47 _L1w_DrvHsupaEutrCodeSize
- 0x100597ee 0x3e _L1w_DrvHsupaEutrPhchPara
- 0x1005982c 0x2d _L1w_DrvHsupaEutrRmSysPara
- 0x10059859 0x2d _L1w_DrvHsupaEutrRmP1Para
- 0x10059886 0x2d _L1w_DrvHsupaEutrRmP2Para
- 0x100598b3 0x55 _L1w_DrvHsupaEutrInterPara
- 0x10059908 0x60 _L1w_DrvHsupaEutrConfig
- 0x10059968 0xb _L1w_DrvHsupaEutrReadHarqStatus
- 0x10059973 0x23 _L1w_DrvHsupaEtxEnable
- 0x10059996 0x12 _L1w_DrvHsupaEtxDisable
- 0x100599a8 0x19 _L1w_DrvHsupaEtxCfgTti
- 0x100599c1 0x2a _L1w_DrvHsupaCfgEtxInt
- 0x100599eb 0x12 _L1w_DrvHsupaTopEtxIntEnable
- 0x100599fd 0xb _L1w_DrvHsupaEtxDisInt
- 0x10059a08 0x1b _L1w_DrvHsupaTopMaskEtxInt
- 0x10059a23 0x31 _L1w_DrvHsupaRakeReadRgHi
- 0x10059a54 0xa _L1w_DrvHsupaCalLogTwo
- 0x10059a5e 0x42 _L1w_DrvHsupaEtxInterPara
- 0x10059aa0 0x34 _L1w_DrvHsupaEtxChCfgReg2
- 0x10059ad4 0x54 _L1w_DrvHsupaEtxEdpxchPara
- 0x10059b28 0x25 _L1w_DrvHsupaEtxSpreadReg
- 0x10059b4d 0x29 _L1w_DrvHsupaEtxConf
- 0x10059b76 0xb _L1w_DrvHsupaEtxReadTtiCnt
- 0x10059b81 0x20 _L1w_DrvHsupaTopGetIntState
- 0x10059ba1 0x1 _L1w_DrvHsupaTopMaskEutrInt
- 0x10059ba2 0xf _L1w_DrvHsupaTopMaskRgHiState
- 0x10059bb1 0xf _L1w_DrvHsupaTopMaskRgHiInt
- 0x10059bc0 0x17 _L1w_DevHsupaTopMaskAgInt
- 0x10059bd7 0x2 _L1w_DrvHsupaTopMaskRgchHichInt
- 0x10059bd9 0x23 _L1w_DrvHsupaMaskInt
- 0x10059bfc 0x2d _L1w_DrvHsupaTopEagchRst
- 0x10059c29 0x7 _L1w_DrvHsupaRdAgIntStateMask
- 0x10059c30 0x7 _L1w_DrvHsupaWtAgIntStateMask
- 0x10059c37 0x7 _L1w_DrvHsupaRdAgIntEnable
- 0x10059c3e 0x7 _L1w_DrvHsupaWtAgIntEnable
- 0x10059c45 0x7 _L1w_DrvHsupaRdRgHiIntStateMask
- 0x10059c4c 0x7 _L1w_DrvHsupaWtRgHiIntStateMask
- 0x10059c53 0x7 _L1w_DrvHsupaRdRgHiIntEnable
- 0x10059c5a 0x7 _L1w_DrvHsupaWtRgHiIntEnable
- 0x10059c61 0x17 _L1w_DrvHsupaEnableAgInt
- 0x10059c78 0x13 _L1w_DrvHsupaPcEtxEdpdchDisable
- 0x10059c8b 0x6 _L1w_DrvEutrGetRamAddr
- .text 0x10059c91 0x506 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
- 0x10059c91 0x1 _L1w_DrvDpramEngDisplay
- 0x10059c92 0x4a _L1w_DrvDpramStructInit
- 0x10059cdc 0x25 _L1w_DrvDpramIsEmpty
- 0x10059d01 0x42 _L1w_DrvDpramReadMsg
- 0x10059d43 0x1 _L1w_DrvDpramUpdateMsgPos
- 0x10059d44 0x5 _L1w_DrvDpramQueMemRead
- 0x10059d49 0x37 _L1w_DrvDpramWriteMsg
- 0x10059d80 0x23 _L1w_DrvDpramGetRdDataPtr
- 0x10059da3 0x1f _L1w_DrvDpramUpdateRdDataPos
- 0x10059dc2 0x24 _L1w_DrvDpramTxReadClearData
- 0x10059de6 0x31 _L1w_DrvDpramGetWrDataPtr
- 0x10059e17 0x8 _L1w_DrvDpramGetWrCnt
- 0x10059e1f 0x2c _L1w_DrvDpramUpdateWrDataPos
- 0x10059e4b 0x1a _L1w_DrvICPSendForPsSched
- 0x10059e65 0xa _L1w_DrvDpramIsD2AEmpty
- 0x10059e6f 0xa _L1w_DrvDpramSleepCheck
- 0x10059e79 0x8 _L1w_DrvDpramWriteSfnDpramFlg
- 0x10059e81 0x7 _L1w_DrvDpramWriteDoff2Dpram
- 0x10059e88 0x7 _L1w_DrvDpramReadEdcpIntState
- 0x10059e8f 0xa _L1w_DrvDpramClrEdcpIntState
- 0x10059e99 0x7 _L1w_DrvDpramClrIcpIntState
- 0x10059ea0 0xa _L1w_DrvDpramMaskIcpInt
- 0x10059eaa 0x9 _L1w_DrvDpramDemaskIcpInt
- 0x10059eb3 0x49 _L1w_DrvDpramPrintLog
- 0x10059efc 0x104 _L1w_DrvDpramUpdateTpu
- 0x1005a000 0x26 _L1w_DrvDpramWriteGrantHarq
- 0x1005a026 0x26 _L1w_DrvDpramWriteUlPower
- 0x1005a04c 0x41 _L1w_DrvDpramGetEutrCtrlInfo
- 0x1005a08d 0xa _L1w_DrvDpramSetRachDchTransFlg
- 0x1005a097 0xa _L1w_DrvDpramGetRachDchTransFlg
- 0x1005a0a1 0x20 _L1w_DrvDpramSetUpaTransInfo
- 0x1005a0c1 0x1f _L1w_DrvDpramGetGrantMonitorReq
- 0x1005a0e0 0xe _L1w_DrvDpramHsupaSetActiveInfos
- 0x1005a0ee 0xa _L1w_DrvDpramSetCmPattern
- 0x1005a0f8 0x9 _L1w_DrvDpramSetUph
- 0x1005a101 0x2f _L1w_DrvDpramWriteEtfcRestrictInfo
- 0x1005a130 0x3e _L1w_DrvDpramWriteCmNtrInfo
- 0x1005a16e 0x29 _L1w_DrvDpramGetEdchHarqId
- .text 0x1005a197 0x1984 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
- 0x1005a197 0x81 _L1w_DrvRxTpcPlCombTimeInit
- 0x1005a218 0x83 _L1w_DrvRxInit
- 0x1005a29b 0x50 _L1w_DrvRxReset
- 0x1005a2eb 0x2c _L1w_DrvRxSoftReset
- 0x1005a317 0x35 _L1w_DrvRxCalcExp2
- 0x1005a34c 0xe _L1w_DrvRxFingerCfg
- 0x1005a35a 0x2c _L1w_DrvRxSetTfciIntTime
- 0x1005a386 0x8 _L1w_DrvRxGetTfciIntTime
- 0x1005a38e 0x191 _L1w_DrvRxCpichCfg
- 0x1005a51f 0x16 _L1w_DrvRxCpichRel
- 0x1005a535 0x109 _L1w_DrvRxPichCfg
- 0x1005a63e 0x3a _L1w_DrvRxPichRel
- 0x1005a678 0x123 _L1w_DrvRxAichCfg
- 0x1005a79b 0x3a _L1w_DrvRxAichRel
- 0x1005a7d5 0x11d _L1w_DrvRxPchCfg
- 0x1005a8f2 0x11 _L1w_DrvRxPchRel
- 0x1005a903 0x126 _L1w_DrvRxFachCfg
- 0x1005aa29 0x3b _L1w_DrvRxFachRel
- 0x1005aa64 0x10e _L1w_DrvRxDlDpchCodeCfg
- 0x1005ab72 0x33 _L1w_DrvRxDlTpcPilotCfg
- 0x1005aba5 0x29 _L1w_DrvRxFdpchTpcCfg
- 0x1005abce 0xa4 _L1w_DrvRxDlDpchCfg
- 0x1005ac72 0x6f _L1w_DrvRxDlDpchRel
- 0x1005ace1 0x31 _L1w_DrvRxDlFbiCfg
- 0x1005ad12 0x15b _L1w_DrvRxFdpchCfg
- 0x1005ae6d 0x3b _L1w_DrvRxFdpchRel
- 0x1005aea8 0x16a _L1w_DrvRxHsscchCfg
- 0x1005b012 0x65 _L1w_DrvRxHsscchRel
- 0x1005b077 0x103 _L1w_DrvRxEagchCfg
- 0x1005b17a 0x40 _L1w_DrvRxEagchRel
- 0x1005b1ba 0x333 _L1w_DrvRxRgHiCfg
- 0x1005b4ed 0x3c _L1w_DrvRxRgHiRel
- 0x1005b529 0x15 _L1w_DrvRxEdchTtiCfg
- 0x1005b53e 0x5b _L1w_DrvRxRgHichPostCmCfg
- 0x1005b599 0x10 _L1w_DrvRxDpchFactorCfg
- 0x1005b5a9 0xf _L1w_DrvRxAgchFactorCfg
- 0x1005b5b8 0x77 _L1w_DrvRxDlCmCfnCfg
- 0x1005b62f 0x8c _L1w_DrvRxDlCmSymbCfg
- 0x1005b6bb 0x64 _L1w_DrvRxDlCmPostCfg
- 0x1005b71f 0x1f _L1w_DrvRxDlCmSymbRel
- 0x1005b73e 0x16 _L1w_DrvRxDlCmPostRel
- 0x1005b754 0x24 _L1w_DrvRxRakeCpChangRel
- 0x1005b778 0x8e _L1w_DrvRxRakeChipCfg
- 0x1005b806 0x119 _L1w_DrvRxRakeSymbCfg
- 0x1005b91f 0x4a _L1w_DrvRxRakePostCfg
- 0x1005b969 0x18 _L1w_DrvRxRakeCfg
- 0x1005b981 0xc _L1w_DrvRxSymbCpichStRead
- 0x1005b98d 0xc _L1w_DrvRxSymbPilotStRead
- 0x1005b999 0x9 _L1w_DrvRxCombPiAiIntRead
- 0x1005b9a2 0x9 _L1w_DrvRxCombPilotIntRead
- 0x1005b9ab 0x9 _L1w_DrvRxCombTpcIntRead
- 0x1005b9b4 0x15 _L1w_DrvRxCombTpcPlStIntRead
- 0x1005b9c9 0x8 _L1w_DrvRxCombFdpchIntRead
- 0x1005b9d1 0xa _L1w_DrvRxCombDpchFactorDataRead
- 0x1005b9db 0xa _L1w_DrvRxCombAgchFactorDataRead
- 0x1005b9e5 0x27 _L1w_DrvRxRamPiAiRead
- 0x1005ba0c 0xa _L1w_DrvRxRamDpchPilotRead
- 0x1005ba16 0xa _L1w_DrvRxRamDpchTpcRead
- 0x1005ba20 0x43 _L1w_DrvRxRamFdpchTpcRead
- 0x1005ba63 0x15 _L1w_DrvRxRamSlotwtRead
- 0x1005ba78 0x15 _L1w_DrvRxRamNoiseRead
- 0x1005ba8d 0x1f _L1w_DrvRxRamRawCpichRead
- 0x1005baac 0x15 _L1w_DrvRxRamAfcRead
- 0x1005bac1 0x1c _L1w_DrvRxRamRawPilotRead
- 0x1005badd 0x1f _L1w_DrvRxRgchIntInfoRead
- 0x1005bafc 0x1f _L1w_DrvRxHichIntInfoRead
- .text 0x1005bb1b 0xa62 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dtr.o)
- 0x1005bb1b 0x11 _L1w_DrvDtrBitReverse
- 0x1005bb2c 0xa _L1w_DrvDtrTurboInit
- 0x1005bb36 0x1d _L1w_DrvDtrTurboReset
- 0x1005bb53 0x11 _L1w_DrvDtrSetCsServiceFlg
- 0x1005bb64 0x3b _L1w_DrvDtrReset
- 0x1005bb9f 0x5e _L1w_DrvDtrInit
- 0x1005bbfd 0x3e _L1w_DrvDtrTrchCmCfg
- 0x1005bc3b 0x4c _L1w_DrvDtrTrchSlotFormCfg
- 0x1005bc87 0x171 _L1w_DrvDtrTrchTfciS1Cfg
- 0x1005bdf8 0x24 _L1w_DrvDtrTrchTfciS1Clear
- 0x1005be1c 0xb _L1w_DrvDtrTrchCfnSet
- 0x1005be27 0xa _L1w_DrvDtrTrchCfnGet
- 0x1005be31 0xf _L1w_DrvDtrTrchRegRel
- 0x1005be40 0xa _L1w_DrvDtrTrchTfciS2Update
- 0x1005be4a 0xa _L1w_DrvDtrTrchDemultiplexUpdate
- 0x1005be54 0x9f _L1w_DrvDtrS1CfgPrint
- 0x1005bef3 0x1d7 _L1w_DrvDtrS2CfgPrint
- 0x1005c0ca 0xb0 _L1w_DrvDtrTrchTfciS2Cfg
- 0x1005c17a 0xb _L1w_DrvDtrTrchTfciS2Clear
- 0x1005c185 0x42 _L1w_DrvDtrTrchBlindS1Cfg
- 0x1005c1c7 0xa5 _L1w_DrvDtrTrchBlindGuidCfg
- 0x1005c26c 0xc _L1w_DrvDtrTrchBlindGuidUpdate
- 0x1005c278 0xa _L1w_DrvDtrTrchTfciRead
- 0x1005c282 0x2d _L1w_DrvDtrTrchTfciDataReadV3
- 0x1005c2af 0x30 _L1w_DrvDtrTrchBlindRead
- 0x1005c2df 0x6 _L1w_DrvDtrTrchBlindDataAddrGet
- 0x1005c2e5 0x24 _L1w_DrvDtrTrchDecodeInfoRead
- 0x1005c309 0x6 _L1w_DrvDtrTrchDecodeAddrGet
- 0x1005c30f 0x1bb _L1w_DrvDtrTrchDecodeDataRead
- 0x1005c4ca 0x61 _L1w_DrvDtrEagchCfg
- 0x1005c52b 0xe _L1w_DrvDtrEagchCmCfg
- 0x1005c539 0x9 _L1w_DrvDtrEagchRel
- 0x1005c542 0x3b _L1w_DrvDtrAgchIntDataRead
- .text 0x1005c57d 0x572 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_bch.o)
- 0x1005c57d 0x2d _L1w_DrvBchInit
- 0x1005c5aa 0xe _L1w_DrvBchReset
- 0x1005c5b8 0x2d _L1w_DrvBchRecover
- 0x1005c5e5 0xd _L1w_DrvBchSetFingerAdjust
- 0x1005c5f2 0xe _L1w_DrvBchGeViterbiOut
- 0x1005c600 0x56 _L1w_DrvBchGePichSymbol
- 0x1005c656 0xa _L1w_DrvBchGeCrcResult
- 0x1005c660 0x2b _L1w_DrvBchGeCpichOut
- 0x1005c68b 0xf8 _L1w_DrvBchBchRxCfg
- 0x1005c783 0xcd _L1w_DrvBchPichRxCfg
- 0x1005c850 0x9b _L1w_DrvBchCpichRxCfg
- 0x1005c8eb 0xc _L1w_DrvBchSetFingerEn
- 0x1005c8f7 0xc _L1w_DrvBchSetRuntime
- 0x1005c903 0xe _L1w_DrvBchGetFingerPos
- 0x1005c911 0x10 _L1w_DrvBchSetS5TestMode
- 0x1005c921 0xa _L1w_DrvBchSetTxdMode
- 0x1005c92b 0x7 _L1w_DrvBchSetBchPichSel
- 0x1005c932 0x7 _L1w_DrvBchSetTtiSync
- 0x1005c939 0x7 _L1w_DrvBchSetWindowTh
- 0x1005c940 0x7 _L1w_DrvBchSetPichOvsfk
- 0x1005c947 0xc _L1w_DrvBchSetContexSel
- 0x1005c953 0xd _L1w_DrvBchSetFingerPos
- 0x1005c960 0x19 _L1w_DrvBchSetScramCode
- 0x1005c979 0x16 _L1w_DrvBchSetStartMode
- 0x1005c98f 0xc _L1w_DrvBchSetPiAfcNum
- 0x1005c99b 0x31 _L1w_DrvBchSetPiPos
- 0x1005c9cc 0xe _L1w_DrvBchGetFingerSt
- 0x1005c9da 0xd _L1w_DrvBchHasInvalidSymbol
- 0x1005c9e7 0xe _L1w_DrvBchGetBufIndex
- 0x1005c9f5 0xe _L1w_DrvBchGetSlotIndex
- 0x1005ca03 0xe _L1w_DrvBchGetBurstPattern
- 0x1005ca11 0xa _L1w_DrvBchGeTotalSt
- 0x1005ca1b 0x16 _L1w_DrvBchIsHwBusy
- 0x1005ca31 0x13 _L1w_DrvBchSetIQSel
- 0x1005ca44 0x12 _L1w_DrvBchSetRotatePara
- 0x1005ca56 0x21 _L1w_DrvBchSetRotateEn
- 0x1005ca77 0xf _L1w_DrvBchSetRotateGateCtrl
- 0x1005ca86 0xb _L1w_DrvBchIsIqRotateEn
- 0x1005ca91 0x36 _L1w_DrvBchStopIqRotate
- 0x1005cac7 0x12 _L1w_DrvBchSetFingerAnt
- 0x1005cad9 0x16 _L1w_DrvBchSetAdjFingerInfo
- .text 0x1005caef 0x2f1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_utr.o)
- 0x1005caef 0xc _L1w_DrvUtrLogTwo
- 0x1005cafb 0x31 _L1w_DrvUtrReset
- 0x1005cb2c 0x1c _L1w_DrvUtrRamSoftReset
- 0x1005cb48 0x3 _L1w_DrvUtrInit
- 0x1005cb4b 0xac _L1w_DrvUtrDchConfig
- 0x1005cbf7 0x32 _L1w_DrvUtrRachConfig
- 0x1005cc29 0xa _L1w_DrvUtrEnable
- 0x1005cc33 0xe _L1w_DrvUtrClose
- 0x1005cc41 0x8 _L1w_DrvUtrGetRamAddr
- 0x1005cc49 0x5f _L1w_DrvUtrTbAndCbConfig
- 0x1005cca8 0xac _L1w_DrvUtrRMConfig
- 0x1005cd54 0x2d _L1w_DrvUtrGetCrcMode
- 0x1005cd81 0x20 _L1w_DrvUtrGetCodingType
- 0x1005cda1 0x1a _L1w_DrvUtrClearRmPara
- 0x1005cdbb 0xc _L1w_DrvUtrRegClear
- 0x1005cdc7 0x11 _L1w_DrvUtrGetRamData
- 0x1005cdd8 0x8 _L1_DrvUtrGetInterlv1RamState
- .text 0x1005cde0 0x1dda T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o)
- 0x1005cde0 0x5e _L1w_DrvRfcApcTableSel
- 0x1005ce3e 0x1d2 _L1w_DrvRfcAbbCsfHpfCfg
- 0x1005d010 0x5 _L1w_DrvRfcCalcIntFreq
- 0x1005d015 0x29 _L1w_DrvRfcCalcFracFreq
- 0x1005d03e 0x51 _L1w_DrvRfcGetFreqData
- 0x1005d08f 0x19 _L1w_DrvRfcGetBandData
- 0x1005d0a8 0x9d _L1w_DrvRfcFreqSetTx
- 0x1005d145 0x12a _L1w_DrvRfcFreqSetRx
- 0x1005d26f 0x84 _L1w_DrvRfcGetBandNvIndex
- 0x1005d2f3 0x79 _L1w_DrvRfcAuxRxCtrlSet
- 0x1005d36c 0x1c _L1w_DrvRfcAuxRxIdleSet
- 0x1005d388 0x20 _L1w_DrvRfcRegReadBackSet
- 0x1005d3a8 0x1 _L1w_DrvRfcChSel
- 0x1005d3a9 0x1 _L1w_DrvRfcTransceiverInit
- 0x1005d3aa 0x2e _L1w_DrvRfcAgcSet
- 0x1005d3d8 0x2f _L1w_DrvRfcApcTableFreqSel
- 0x1005d407 0xbc _L1w_DrvRfcApcSet
- 0x1005d4c3 0x2d _L1w_DrvRfcFreqCompGetNvIdx
- 0x1005d4f0 0x7c _L1w_DrvRfcApcFreqComp
- 0x1005d56c 0x38 _L1w_DrvRfcApcTmpComp
- 0x1005d5a4 0x100 _L1w_DrvRfcApcCalibTableCheck
- 0x1005d6a4 0x4f _L1w_DrvRfcApcDefaultTableCheck
- 0x1005d6f3 0x77 _L1w_DrvRfcAgcFreqComp
- 0x1005d76a 0x71 _L1w_DrvRfcAgcCalibTableCheck
- 0x1005d7db 0x46 _L1w_DrvRfcAgcDefaultTableCheck
- 0x1005d821 0x2a _L1w_DrvRfcRxNotchEn
- 0x1005d84b 0x2a _L1w_DrvRfcRxNotchDisEn
- 0x1005d875 0x2b _L1w_DrvRfcAntExChangeSelEn
- 0x1005d8a0 0x2b _L1w_DrvRfcAntOriginSelEn
- 0x1005d8cb 0x2a _L1w_DrvRfcRxStartDivEn
- 0x1005d8f5 0x2b _L1w_DrvRfcRxStopDivEn
- 0x1005d920 0x2a _L1w_DrvRfcAuxRxSwCtrlEn
- 0x1005d94a 0x2b _L1w_DrvRfcAuxRxSwIdleEn
- 0x1005d975 0x38 _L1w_DrvRfcIdleToTxEn
- 0x1005d9ad 0x36 _L1w_DrvRfcTxToRxTxEn
- 0x1005d9e3 0x3a _L1w_DrvRfcTxToIdleEn
- 0x1005da1d 0x36 _L1w_DrvRfcRxTxToTxEn
- 0x1005da53 0x36 _L1w_DrvRfcIdleToRxEn
- 0x1005da89 0x38 _L1w_DrvRfcRxToRxTxEn
- 0x1005dac1 0x2b _L1w_DrvRfcSwAllIdleEn
- 0x1005daec 0x40 _L1w_DrvRfcRxToIdleEn
- 0x1005db2c 0x2d _L1w_DrvRfcRxTxToRxEn
- 0x1005db59 0x37 _L1w_DrvRfcRxFreqChangeEn
- 0x1005db90 0x38 _L1w_DrvRfcTxFreqChangeEn
- 0x1005dbc8 0x32 _L1w_DrvRfcIdleToTxHandle
- 0x1005dbfa 0x48 _L1w_DrvRfcTxToIdleHandle
- 0x1005dc42 0x45 _L1w_DrvRfcIdleToRxHandle
- 0x1005dc87 0x55 _L1w_DrvRfcRxToIdleHandle
- 0x1005dcdc 0x53 _L1w_DrvRfcRxFreqChangeHandle
- 0x1005dd2f 0xd _L1w_DrvRfcTxFreqChangeHandle
- 0x1005dd3c 0x41 _L1w_DrvRfcSlotCtrlDiv
- 0x1005dd7d 0x2a _L1w_DrvRfcSlotCtrlAntSel
- 0x1005dda7 0x29 _L1w_DrvRfcAgcEstEn
- 0x1005ddd0 0x29 _L1w_DrvRfcAgcSetEn
- 0x1005ddf9 0x35 _L1w_DrvRfcApcEn
- 0x1005de2e 0x3c _L1w_DrvRfcAfcSetEn
- 0x1005de6a 0x29 _L1w_DrvRfcDcEstEn
- 0x1005de93 0x29 _L1w_DrvRfcDcSetEn
- 0x1005debc 0x29 _L1w_DrvRfcRegReadBackEn
- 0x1005dee5 0x29 _L1w_DrvRfcStartAuxAdcEn
- 0x1005df0e 0x29 _L1w_DrvRfcStopAuxAdcEn
- 0x1005df37 0x1c _L1w_DrvRfcDcxoAuxAdcStart
- 0x1005df53 0x1d _L1w_DrvRfcDcxoAuxAdcStop
- 0x1005df70 0x1f _L1w_DrvRfcAuxAdcCtrlEn
- 0x1005df8f 0x41 _L1w_DrvRfcAbbCsfWriteEn
- 0x1005dfd0 0x33 _L1w_DrvRfcCtrlRamTxInit
- 0x1005e003 0x33 _L1w_DrvRfcCtrlRamRx0Init
- 0x1005e036 0x204 _L1w_DrvRfcCtrlRamSwitchNvInit
- 0x1005e23a 0xea _L1w_DrvRfcCtrlRamPaNvInit
- 0x1005e324 0x8 _L1w_DrvRfcCtrlRamNvEventInit
- 0x1005e32c 0x38 _L1w_DrvRfcFastAgcCwTableInit
- 0x1005e364 0x4c _L1w_DrvRfcFastAgcRamInit
- 0x1005e3b0 0xda _L1w_DrvRfcOpenTx
- 0x1005e48a 0xf7 _L1w_DrvRfcOpenRx
- 0x1005e581 0xa _L1w_DrvRfcDiversityCtrl
- 0x1005e58b 0x12 _L1w_DrvRfcAfcCw2Hz
- 0x1005e59d 0x6a _L1w_DrvRfcRfRegRead
- 0x1005e607 0xce _L1w_DrvRfcAllRegReadBack
- 0x1005e6d5 0x54 _L1w_DrvRfcGetDCXOTmp
- 0x1005e729 0x3b _L1w_DrvRfcReadTmp
- 0x1005e764 0x15 _L1w_DrvRfcAptWrite
- 0x1005e779 0x21 _L1w_DrvRfcDcocWrite
- 0x1005e79a 0x18 _L1w_DrvRfcAgcWrite
- 0x1005e7b2 0x8d _L1w_DrvRfcCloseTx
- 0x1005e83f 0x6d _L1w_DrvRfcCloseRx
- 0x1005e8ac 0x7e _L1w_DrvRfcDirFreqSetTx
- 0x1005e92a 0x7c _L1w_DrvRfcDirFreqSetRx
- 0x1005e9a6 0x32 _L1w_DrvRfcPowerApcSet
- 0x1005e9d8 0x43 _L1w_DrvRfcIndexApcSet
- 0x1005ea1b 0x177 _L1w_DrvRfcFdtTxApcSet
- 0x1005eb92 0x22 _L1w_DrvRfcHdtGetTxApcTable
- 0x1005ebb4 0x6 _L1w_DrvRfcHdtGetRxAgcTable
- .text 0x1005ebba 0xb8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_psr.o)
- 0x1005ebba 0x8 _L1w_DrvPsrStartPosCfg
- 0x1005ebc2 0xb _L1w_DrvPsrRlMrtrPosMrtrConfig
- 0x1005ebcd 0xb _L1w_DrvPsrSrcAndChanCodeCfg
- 0x1005ebd8 0x8 _L1w_DrvPsrClkGatePassCfg
- 0x1005ebe0 0x9 _L1w_DrvPsrPilotPatternCfg
- 0x1005ebe9 0x8 _L1w_DrvPsrCmModeCfg
- 0x1005ebf1 0x9 _L1w_DrvPsrRlPosStartCfgOver
- 0x1005ebfa 0x9 _L1w_DrvPsrSuspendCfg
- 0x1005ec03 0x12 _L1w_DrvPsrTopMaskIntCfg
- 0x1005ec15 0x1c _L1w_DrvPsrResetCfg
- 0x1005ec31 0x8 _L1w_DrvPsrPeriodCfg
- 0x1005ec39 0x8 _L1w_DrvPsrDoubleAntOpencfg
- 0x1005ec41 0x8 _L1w_DrvPsrStartWinPosCfg
- 0x1005ec49 0x8 _L1w_DrvPsrRlOpenCloseCfg
- 0x1005ec51 0x8 _L1w_DrvPsrMasterRlCfg
- 0x1005ec59 0x8 _L1w_DrvPsrSttdCfg
- 0x1005ec61 0x8 _L1w_DrvPsrIntInfoCfg
- 0x1005ec69 0x9 _L1w_DrvPsrCmOverCfg
- .text 0x1005ec72 0xaff T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
- 0x1005ec72 0x3c _L1w_DrvRfcGetFreqOffset
- 0x1005ecae 0x17 _L1w_DrvRfcNextSlotGet
- 0x1005ecc5 0x16 _L1w_DrvRfcPreSlotGet
- 0x1005ecdb 0x20 _L1w_DrvRfcFindSlot
- 0x1005ecfb 0x8 _L1w_DrvRfcGetTxFirDlyNum
- 0x1005ed03 0x31 _L1w_DrvRfcSpiWrite
- 0x1005ed34 0x31 _L1w_DrvRfcAbbSpiWrite
- 0x1005ed65 0x12 _L1w_DrvRfcGpioWrite
- 0x1005ed77 0x14 _L1w_DrvRfcRffeWrite
- 0x1005ed8b 0x38 _L1w_DrvRfcFindBandNumFromTable
- 0x1005edc3 0x41 _L1w_DrvRfcGetFreqBand
- 0x1005ee04 0x22 _L1w_DrvRfcRxDfeIntfCfg
- 0x1005ee26 0x2f _L1w_DrvRfcPaModeSel
- 0x1005ee55 0x25 _L1w_DrvRfcGetPaCtrlData
- 0x1005ee7a 0x1a _L1w_DrvRfcGetPaIdleData
- 0x1005ee94 0x2a _L1w_DrvRfcGetApcCtrlWord
- 0x1005eebe 0xa3 _L1w_DrvRfcGetTxPowerCtrlWord
- 0x1005ef61 0x14 _L1w_DrvRfcPaCtrl
- 0x1005ef75 0x25 _L1w_DrvRfcGetAgcCtrlWord
- 0x1005ef9a 0x27 _L1w_DrvRfcGetAfcDacCtrlWord
- 0x1005efc1 0x2c _L1w_DrvRfcDCXOGetTempDegree
- 0x1005efed 0xb _L1w_DrvRfcAfcSet
- 0x1005eff8 0x1a _L1w_DrvRfcGetTxSwData
- 0x1005f012 0x29 _L1w_DrvRfcGetRxSwData
- 0x1005f03b 0x1a _L1w_DrvRfcGetTxSwIdleData
- 0x1005f055 0x29 _L1w_DrvRfcGetRxSwIdleData
- 0x1005f07e 0x1a _L1w_DrvRfcGetSwAllIdleData
- 0x1005f098 0x27 _L1w_DrvRfcSwitchPaCwWr
- 0x1005f0bf 0x37 _L1w_DrvRfcSwitchCtrl
- 0x1005f0f6 0x55 _L1w_DrvRfcSwPaIdleNvGet
- 0x1005f14b 0x12 _L1w_DrvRfcGetCfgMrtr
- 0x1005f15d 0x54 _L1w_DrvRfcTuEventMrtrWr
- 0x1005f1b1 0x21 _L1w_DrvRfcTuEventCtrlDataWr
- 0x1005f1d2 0x54 _L1w_DrvRfcTuEventEn
- 0x1005f226 0x27 _L1w_DrvRfcCtrlRamFmtDataWr
- 0x1005f24d 0x28 _L1w_DrvRfcCtrlRamFmtInfoWr
- 0x1005f275 0x20 _L1w_DrvRfcCtrlRamDataTypeWr
- 0x1005f295 0x40 _L1w_DrvRfcCtrlRamEn
- 0x1005f2d5 0xe _L1w_DrvRfcAgcRamDataWr
- 0x1005f2e3 0x1c _L1w_DrvRfcFastAgcEn
- 0x1005f2ff 0x1a _L1w_DrvRfcFastAgcDisEn
- 0x1005f319 0x15 _L1w_DrvRfcIntCfg
- 0x1005f32e 0x15 _L1w_DrvRfcSpiFormatCfg
- 0x1005f343 0x9 _L1w_DrvRfcRffeFormatCfg
- 0x1005f34c 0x2 _L1w_DrvRfcRbdpCfg
- 0x1005f34e 0x1c _L1w_DrvRfcDagcCfg
- 0x1005f36a 0x13 _L1w_DrvRfcDcCfg
- 0x1005f37d 0xd _L1w_DrvRfcFcCordicCfg
- 0x1005f38a 0x1a _L1w_DrvRfcNotchCordicCfg
- 0x1005f3a4 0x21 _L1w_DrvRfcReadNotchCordicAVal
- 0x1005f3c5 0xb8 _L1w_DrvRfcNotchRegCfg
- 0x1005f47d 0x52 _L1w_DrvRfcFastAgcCfg
- 0x1005f4cf 0x4f _L1w_DrvRfcCtrlRamEventInit
- 0x1005f51e 0x84 _L1w_DrvRfcAbbCsfCtrlRamInit
- 0x1005f5a2 0x21 _L1w_DrvRfcEventTableInit
- 0x1005f5c3 0x41 _L1w_DrvRfcReset
- 0x1005f604 0x8f _L1w_DrvRfcGsmIntNotchCalc
- 0x1005f693 0x73 _L1w_DrvRfcInit
- 0x1005f706 0x9 _L1w_DrvRfcDfeTxInit
- 0x1005f70f 0x30 _L1w_DrvRfcTxTone
- 0x1005f73f 0x28 _L1w_DrvRfcAfcCwSet
- 0x1005f767 0x1 _L1w_DrvRfcAfcCwGet
- 0x1005f768 0x9 _L1w_DrvRfcRestore
- .text 0x1005f771 0x1594 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
- 0x1005f771 0x38 _L1w_DrvHsdpaIcReset
- 0x1005f7a9 0x2f _L1w_DrvHsdpaIcTpuCfgOver
- 0x1005f7d8 0x30 _L1w_DrvHsdpaIcTxTpuCfgOver
- 0x1005f808 0x28 _L1w_DrvHsdpaIcInit
- 0x1005f830 0x12 _L1w_DrvHsdpaIcIntOpen
- 0x1005f842 0x12 _L1w_DrvHsdpaIcIntMask
- 0x1005f854 0x17 _L1w_DrvHsdpaIcEnable
- 0x1005f86b 0x18 _L1w_DrvHsdpaIcStaticCfg
- 0x1005f883 0x273 _L1w_DrvHsdpaIcTpuAntPsrCfg
- 0x1005faf6 0x1d8 _L1w_DrvHsdpaIcTxTpuAntPsrCfg
- 0x1005fcce 0xa9 _L1w_DrvHsdpaIcTpuSubFrmCfg
- 0x1005fd77 0x97 _L1w_DrvHsdpaIcTxTpuSubFrmCfg
- 0x1005fe0e 0x69 _L1w_DrvHsdpaIcModeEnableCfg
- 0x1005fe77 0x5b _L1w_DrvHsdpaIcLambdaCfg
- 0x1005fed2 0x5b _L1w_DrvHsdpaIcSymModulusRead
- 0x1005ff2d 0x34 _L1w_DrvHsdpaAdrReset
- 0x1005ff61 0x18 _L1w_DrvHsdpaAdrInit
- 0x1005ff79 0x12 _L1w_DrvHsdpaAdrIntOpen
- 0x1005ff8b 0x12 _L1w_DrvHsdpaAdrIntMask
- 0x1005ff9d 0xd6 _L1w_DrvHsdpaAdrStaticCfg
- 0x10060073 0x83 _L1w_DrvHsdpaAdrInitRcvCfg
- 0x100600f6 0x4b _L1w_DrvHsdpaAdrFcCfg
- 0x10060141 0x10 _L1w_DrvHsdpaAdrEnableCfg
- 0x10060151 0x172 _L1w_DrvHsdpaAdrSubFrmCfg
- 0x100602c3 0x10 _L1w_DrvHsdpaAdrHsscchCfg
- 0x100602d3 0x2e _L1w_DrvHsdpaAdrHsdschCfg
- 0x10060301 0xa _L1w_DrvHsdpaAdrDisable
- 0x1006030b 0x2d _L1w_DrvHsdpaAdrCltd1Cfg
- 0x10060338 0x74 _L1w_DrvHsdpaAdrCirIntRead
- 0x100603ac 0x11 _L1w_DrvHsdpaAdrGetCirDataAddr
- 0x100603bd 0x20 _L1w_DrvHsdpaAdrCpichIntRead
- 0x100603dd 0x2e _L1w_DrvHsdpaHsscchReset
- 0x1006040b 0x21 _L1w_DrvHsdpaHsscchInit
- 0x1006042c 0x12 _L1w_DrvHsdpaHsscchIntOpen
- 0x1006043e 0x12 _L1w_DrvHsdpaHsscchIntMask
- 0x10060450 0x11 _L1w_DrvHsdpaHsscchStaticCfg
- 0x10060461 0x65 _L1w_DrvHsdpaHsscchInitRcvCfg
- 0x100604c6 0x2d _L1w_DrvHsdpaHsscchPart1Cfg
- 0x100604f3 0x3b _L1w_DrvHsdpaHsscchPart2Cfg
- 0x1006052e 0x1b _L1w_DrvHsdpaHsscchDisable
- 0x10060549 0xeb _L1w_DrvHsdpaHsscchPart1IntRead
- 0x10060634 0x31 _L1w_DrvHsdpaHsscchPart2IntRead
- 0x10060665 0x30 _L1w_DrvHsdpaHdtrReset
- 0x10060695 0x1a _L1w_DrvHdtrTurboReset
- 0x100606af 0x1b _L1w_DrvHdtrLessTurboReset
- 0x100606ca 0x2e _L1w_DrvHsdpaHdtrInit
- 0x100606f8 0x12 _L1w_DrvHsdpaHdtrIntOpen
- 0x1006070a 0x12 _L1w_DrvHsdpaHdtrIntMask
- 0x1006071c 0x25 _L1w_DrvHsdpaHdtrStaticCfg
- 0x10060741 0xa _L1w_DrvHsdpaHdtrInitRcvCfg
- 0x1006074b 0x3b _L1w_DrvHsdpaHdtrDemoduleCfg
- 0x10060786 0x183 _L1w_DrvHsdpaHdtrDecodeCfg
- 0x10060909 0x83 _L1w_DrvHsdpaHdtrHwCfg
- 0x1006098c 0xa _L1w_DrvHsdpaHdtrGetCurCfgSubFrm
- 0x10060996 0x76 _L1w_DrvHsdpaHdtrIntRead
- 0x10060a0c 0x6 _L1w_DrvHsdpaHdtrGetRamDataAddr
- 0x10060a12 0x3b _L1w_DrvHsdpaHsdpcchInitSendCfg
- 0x10060a4d 0x39 _L1w_DrvHsdpaHsdpcchAckNackCfg
- 0x10060a86 0x3c _L1w_DrvHsdpaHsdpcchCqiPciCfg
- 0x10060ac2 0x10 _L1w_DrvHsdpaHsdpcchCqiPciCfgEn
- 0x10060ad2 0x10 _L1w_DrvHsdpaHsdpcchDisable
- 0x10060ae2 0x19 _L1w_DrvHsdpaLessStaticCfg
- 0x10060afb 0x20a _L1w_DrvHsdpaLessCfgAllTb
- .text 0x10060d05 0x2951 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
- 0x10060d05 0x2f _L1W_SEND_RST_REQ
- 0x10060d34 0x2f _L1W_SEND_INIT_REQ
- 0x10060d63 0x1d _L1W_RegTpuTS0IntEvent
- 0x10060d80 0xc _L1W_ResetTpu
- 0x10060d8c 0x18d _L1W_Reset
- 0x10060f19 0x125 _L1W_Init
- 0x1006103e 0x35 _L1w_SchedMeasRelease
- 0x10061073 0x120 _L1W_W_Release
- 0x10061193 0x1c _L1W_SetSecSchedId
- 0x100611af 0x8 _L1W_CampOnSetFlag
- 0x100611b7 0x75 _L1W_CampOnOrReconfig
- 0x1006122c 0xad _L1W_DchIn1R2RCtrl
- 0x100612d9 0x1e _L1W_Only1RCtrl
- 0x100612f7 0xa9 _L1W_Sch1R2RAntCtrl
- 0x100613a0 0xd8 _L1w_TpuAdjScByDchCfgScene
- 0x10061478 0xa8 _L1W_DlDpchReconfig
- 0x10061520 0x1c _L1W_DchRelTpuAdj
- 0x1006153c 0x6e _L1w_AmtFsmProc
- 0x100615aa 0x89 _L1w_AmtNSTSetUlDpchParm
- 0x10061633 0x72 _L1w_AmtNSTSetDlDpchParm
- 0x100616a5 0x5b _L1W_WRelDelayHandle
- 0x10061700 0x4af _L1W_PSCommonMsgCtrl
- 0x10061baf 0x5 _L1w_HsupaSubIntCallBack
- 0x10061bb4 0x111 _L1W_ReadPSMsg
- 0x10061cc5 0x1d _L1W_RegTpuSubFrmIntEvent
- 0x10061ce2 0x42 _L1W_SubFrmSchedStateCtrl
- 0x10061d24 0x1b _L1W_InnerCmd
- 0x10061d3f 0x55 _L1W_ActiveProcHandler
- 0x10061d94 0x1f _L1W_ProcSend2PS
- 0x10061db3 0x34 _L1W_ProcAftSchedHandler
- 0x10061de7 0x26f _L1W_RfDevCtrl
- 0x10062056 0xa3 _L1W_DlsDevCtrl
- 0x100620f9 0x64 _L1W_SlaveSetRFStartEnd
- 0x1006215d 0x9e _L1W_CommonDevCtrl
- 0x100621fb 0x1ce _L1W_BeforeTpuAdjHandler
- 0x100623c9 0x19f _L1W_StateChanging
- 0x10062568 0x8d _L1W_NorSubFrmIntHandle
- 0x100625f5 0x150 _L1W_FrameInt
- 0x10062745 0x29 _L1w_SchedResBaseOffUpdate
- 0x1006276e 0x1a1 _L1W_PichIntHandle
- 0x1006290f 0xe3 _L1W_PreSyncSleepSched
- 0x100629f2 0x583 _L1W_DevIntHandle
- 0x10062f75 0x1bd _L1W_DevMeasResultHnd
- 0x10063132 0x18d _L1W_DevResultProc
- 0x100632bf 0x1c2 _L1w_MainTs0Log
- 0x10063481 0x12 _L1w_MainSetCloseLog
- 0x10063493 0x3a _L1w_SchedAntSet
- 0x100634cd 0x189 _L1w_SchedMainTask
- .text 0x10063656 0x7c7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_rach.o)
- 0x10063656 0x36 _L1w_SchedRachProcInit
- 0x1006368c 0x14 _L1w_SchedRachProcReset
- 0x100636a0 0x9c _L1w_SchedRachProcRanSelSig
- 0x1006373c 0x52 _L1w_SchedRachFindAvailableAS
- 0x1006378e 0xab _L1w_SchedRachNeedDeleteRtFrameEndAichSlot
- 0x10063839 0x170 _L1w_SchedRachProcRanSelAS
- 0x100639a9 0x49 _L1w_SchedRachProcActive
- 0x100639f2 0x2f _L1w_SchedRachProcDeactive
- 0x10063a21 0xce _L1w_SchedRachConfigRtx
- 0x10063aef 0xb9 _L1w_SchedRachProcPSCmd
- 0x10063ba8 0x33 _L1w_SchedRachProcL1Cmd
- 0x10063bdb 0x2e _L1w_SchedRachProcPreSched
- 0x10063c09 0x4d _L1w_SchedRachProcCfgHandle
- 0x10063c56 0x27 _L1w_SchedRachAiResultHandle
- 0x10063c7d 0xea _L1w_SchedRachProcSched
- 0x10063d67 0x28 _L1w_SchedRachProcSend2PS
- 0x10063d8f 0x36 _L1w_SchedRachProcL1InnerReq
- 0x10063dc5 0x9 _L1w_SchedRachProcL1InnerAbort
- 0x10063dce 0x8 _L1w_SchedRachProcDevFachEnable
- 0x10063dd6 0x1b _L1W_SchedRachProcConfigCheck
- 0x10063df1 0x2c _L1w_SchedRachProcIsNextFmo
- .text 0x10063e1d 0x1181 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o)
- 0x10063e1d 0xd _L1w_SchMeasDbInit
- 0x10063e2a 0x30 _L1w_SchMeasU16Filter
- 0x10063e5a 0x17 _L1w_SchMeasFingerPosOffset
- 0x10063e71 0x74 _L1w_SchMeasChooseFilterFinger
- 0x10063ee5 0xc8 _L1w_SchMeasDbUpdPreSyncInfo
- 0x10063fad 0x1d _L1w_SchedMeasReturnCsrSlot
- 0x10063fca 0x27f _L1w_SchMeasDbSaveSyncCelReslt
- 0x10064249 0xbb _L1w_SchedMeasSetInnerReq
- 0x10064304 0x91 _L1w_SchedMeasSetInnerResult
- 0x10064395 0x17 _L1w_SchedMeasClearInnerDb
- 0x100643ac 0x37 _L1w_SchedMeasGetInnerResult
- 0x100643e3 0x15 _L1w_SchedMeasQueryInnerSt
- 0x100643f8 0x12 _L1w_SchedMeasGetAfcCel
- 0x1006440a 0x25 _L1w_SchedMeasGetInnerCelInfo
- 0x1006442f 0x14f _L1w_SchedMeasGetInnerFreq
- 0x1006457e 0x13d _L1w_SchedMeasSaveCsResult
- 0x100646bb 0x9a _L1w_SchedMeasQuerySyncInfo
- 0x10064755 0xc0 _L1w_SchedMeasSyncSetFreq
- 0x10064815 0x48 _L1w_SchedMeasGetScellResult
- 0x1006485d 0x2db _L1w_SchedMeasGetIntraResult
- 0x10064b38 0x1a _L1w_SchedMeasFilterRscp
- 0x10064b52 0x2a4 _L1w_SchedMeasGetInterResult
- 0x10064df6 0xbf _L1w_SchMeasQueryCellInfo
- 0x10064eb5 0x3a _L1w_SchMeasAdjustSfn
- 0x10064eef 0x4e _L1w_SchMeasSetCellSfnInfo
- 0x10064f3d 0x37 _L1w_SchMeasSetCellSttdInfo
- 0x10064f74 0x2a _L1w_SchMeasGetUeInternalRssi
- .text 0x10064f9e 0x8b4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
- 0x10064f9e 0x30 _L1W_RegisterProcedure
- 0x10064fce 0x49 _L1W_SetIcsStateProcs
- 0x10065017 0x68 _L1W_SetIdleStateProcs
- 0x1006507f 0x40 _L1W_SetPageStateProcs
- 0x100650bf 0x50 _L1W_SetFachStateProcs
- 0x1006510f 0x50 _L1W_SetEFachStateProcs
- 0x1006515f 0x48 _L1W_SetDchStateProcs
- 0x100651a7 0x14 _L1W_SetAmtHdtStateProcs
- 0x100651bb 0x14 _L1W_SetAmtFdtStateProcs
- 0x100651cf 0x40 _L1W_SetAmtThCalibStateProcs
- 0x1006520f 0x40 _L1W_SetAmtNstStateProcs
- 0x1006524f 0x32 _L1W_SetWSlaveModeProcs
- 0x10065281 0x1 _L1W_SetCloseStateProcs
- 0x10065282 0xb _L1W_GetDchActState
- 0x1006528d 0x6f _L1W_NotifyFSM
- 0x100652fc 0x142 _L1W_WMasteStateCtrl
- 0x1006543e 0xc0 _L1W_ModeCtrl
- 0x100654fe 0x4d _L1W_L1StateCtrl
- 0x1006554b 0x87 _L1W_SetProc
- 0x100655d2 0x42 _L1W_GetPriId
- 0x10065614 0x97 _L1w_SetMasterState
- 0x100656ab 0x30 _L1w_ResetCountForLog
- 0x100656db 0x1b _L1w_AddSlaveStateCntForLog
- 0x100656f6 0x3a _L1w_AddMasterStateCntForLog
- 0x10065730 0xb4 _L1w_CheckMsgToAddProcCntForLog
- 0x100657e4 0xa _L1w_SetDLULTimingForLog
- 0x100657ee 0x64 _L1w_PrintStandLog
- .text 0x10065852 0x7b8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o)
- 0x10065852 0x8 _L1w_SchedCs1ProcGetFreq
- 0x1006585a 0x7 _L1w_SchedCs1ProcGetCsProcState
- 0x10065861 0x6 _L1w_Cs1GetInnerInfo
- 0x10065867 0x12 _L1w_SchedCs1ProcInit
- 0x10065879 0x21 _L1_SchedCs1ProcReset
- 0x1006589a 0x22 _L1w_Cs1WriteFullscanResult
- 0x100658bc 0x17 _L1w_SchedCs1AbortInnerReq
- 0x100658d3 0xf _L1w_Cs1GetInnerReqByActReason
- 0x100658e2 0x2 _L1w_SchedCs1ProcPSCmd
- 0x100658e4 0x1 _L1w_SchedCs1ProcSend2PS
- 0x100658e5 0xa2 _L1w_SchedCs1ProcActive
- 0x10065987 0x79 _L1w_SchedCs1ProcDeactive
- 0x10065a00 0x19 _L1w_SchedCs1ProcFsm
- 0x10065a19 0x1 _L1w_Cs1InitSched
- 0x10065a1a 0x2 _L1w_Cs1InitPreSchedHandler
- 0x10065a1c 0x1 _L1w_Cs1InitAfcSched
- 0x10065a1d 0x2 _L1w_Cs1InitAfcPreSchedHandler
- 0x10065a1f 0xe _L1w_Cs1Step1ResClear
- 0x10065a2d 0x2d4 _L1w_Cs1Step1Sched
- 0x10065d01 0x75 _L1w_Cs1Step1PreSchedHandler
- 0x10065d76 0x52 _L1w_Cs1FullscanPreSchedHandler
- 0x10065dc8 0x94 _L1w_Cs1FullscanSched
- 0x10065e5c 0x6c _L1w_Cs1ReportResultSched
- 0x10065ec8 0x3e _L1w_SchedCs1ProcSched
- 0x10065f06 0x34 _L1w_SchedCs1ProcPreSchedHandler
- 0x10065f3a 0x4a _L1w_SchedCs1ProcInnerActive
- 0x10065f84 0x44 _L1w_SchedCs1ProcInnerDeactive
- 0x10065fc8 0x42 _L1w_SchedCs1ProcInnerResultGet
- .text 0x1006600a 0x79c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
- 0x1006600a 0x10 _L1w_DevResultClear
- 0x1006601a 0x24 _L1w_ReadDevResult
- 0x1006603e 0x35 _L1w_ReadDevResultNeedFlg
- 0x10066073 0x3c _L1w_ReadDevMultResultNedFlg
- 0x100660af 0x2e _L1w_ReadDevMultiResult
- 0x100660dd 0x49 _L1w_WriteDevResult
- 0x10066126 0x27 _L1w_SrvCellDbClear
- 0x1006614d 0x51 _L1w_SchedDbInit
- 0x1006619e 0x18 _L1w_ReadPsMsgFromDb_Opt
- 0x100661b6 0x22 _L1w_ReadPsMsgFromDb
- 0x100661d8 0x6 _L1w_GetPsMsgAddress
- 0x100661de 0x3 _L1w_GetPsMsgMaxLen
- 0x100661e1 0x16 _L1w_SetSrvCellInfo
- 0x100661f7 0x16 _L1w_GetSrvCellInfo
- 0x1006620d 0x1b _L1w_GetSpecifiedSrvCell
- 0x10066228 0x49 _L1w_SrvMeasProcInfoInd
- 0x10066271 0x23 _L1w_CsSetSrvSyncState
- 0x10066294 0x22 _L1w_CsGetSrvSyncState
- 0x100662b6 0x25 _L1w_SetSrvCellTiming
- 0x100662db 0x2c _L1w_GetSrvCellTiming
- 0x10066307 0x23 _L1w_SetMainCellTiming
- 0x1006632a 0xb _L1w_BackUpMrtrOffset
- 0x10066335 0x1a _L1w_BackUpSrvCellInfo
- 0x1006634f 0x1b _L1w_ReStoreSrvCellInfo
- 0x1006636a 0x9 _L1w_GetMrtrOffset
- 0x10066373 0x14 _L1w_SetSrvCellAgeTime
- 0x10066387 0x23 _L1w_GetMainCellTiming
- 0x100663aa 0x90 _L1w_SetDchProcInfo
- 0x1006643a 0xd _L1w_GetSrvCpichSttdMode
- 0x10066447 0x1f _L1w_GetDpaCellCpichSttdMode
- 0x10066466 0x12 _L1W_TimingCalcSFNOff
- 0x10066478 0x56 _L1w_SetSysTimingInfo
- 0x100664ce 0x22 _L1w_GetCellMrtrOffset
- 0x100664f0 0x31 _L1w_GetCellRscpInfo
- 0x10066521 0xa5 _L1w_SetHsdpaCellInfo
- 0x100665c6 0x23 _L1w_GetHsdpaCellHsscchFrm
- 0x100665e9 0xa _L1w_SetSysInfoAfc
- 0x100665f3 0x8 _L1w_GetSysInfoAfc
- 0x100665fb 0x17 _L1w_GetActiveCellScrCode
- 0x10066612 0x86 _L1w_GetCellInfo
- 0x10066698 0x5 _L1w_SetCellSfnInfo
- 0x1006669d 0x5 _L1w_SetCellSttdInfo
- 0x100666a2 0x19 _L1w_IsSaCell
- 0x100666bb 0x22 _L1w_GetSaCellTiming
- 0x100666dd 0x53 _L1w_DbPrintCellTiming
- 0x10066730 0x31 _L1w_DbSkipFrmEnd
- 0x10066761 0x45 _L1w_UpdateMrtrOffset
- .text 0x100667a6 0x50c2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas.o)
- 0x100667a6 0xf _L1w_SchedMeasProcActive
- 0x100667b5 0x34 _L1w_SchedMeasProcDeactive
- 0x100667e9 0x8 _L1w_SchedMeasDpaExist
- 0x100667f1 0x9f _L1w_SchedMeasReqCellQuery
- 0x10066890 0x72 _L1w_SchedMeasGetCells
- 0x10066902 0x16 _L1w_SchedMeasCellInfoQuery
- 0x10066918 0x38 _L1w_SchedMeasSyncFreqQuery
- 0x10066950 0x1e _L1w_SchedMeasSyncCellQuery1
- 0x1006696e 0x4c _L1w_SchedMeasSyncCellQuery2
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- 0x10079986 0xa6 _L1w_DevRmCalcUlTurboRm
- 0x10079a2c 0x65 _L1w_DevRmCalcUlTrchRmPara
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- 0x10079ad7 0x8a _L1w_DevRmCalcDlNimax
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- 0x10079ec5 0x63 _L1w_DevRmCalcDlUncodeRm
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- 0x1007e3cf 0x26 _zPHY_AtGetResidualBler
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- .text 0x1007e40f 0xbb9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
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- 0x1007e8e5 0x13 _L1L_TpuDevRelativeCBTimerRegister
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- 0x1007eb45 0x40 _L1L_TpuMrtrSub
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- .text 0x1007efc8 0x677 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
- 0x1007efc8 0x40 _zPHY_ecsi_HNoDMA
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- 0x1007f07f 0x9b _zPHY_ecsi_PCellDediParmUpdate
- 0x1007f11a 0xb7 _zPHY_ecsi_PCellHOParmUpdate
- 0x1007f1d1 0xd3 _zPHY_ecsi_MsgResponse
- 0x1007f2a4 0x2d _zPHY_ecsi_ctrl_GetNodeTXAttennaNum
- 0x1007f2d1 0x8c _zPHY_ecsi_CbResSetGet
- 0x1007f35d 0x2c _zPHY_ecsi_PerCqiParaGet
- 0x1007f389 0x23 _zPHY_ecsi_CqiRowAParaCalc
- 0x1007f3ac 0x5c _zPHY_ecsi_PcellCsiRepParaDediGet
- 0x1007f408 0x3f _zPHY_ecsi_ScellCsiRepParaDediGet
- 0x1007f447 0x12 _zPHY_ecsi_CsiRsParaGet
- 0x1007f459 0x28 _zPHY_ecsi_CSITimeUpdate
- 0x1007f481 0xac _zPHY_ecsi_FlowPrint
- 0x1007f52d 0x1 _zPHY_ecsi2dl_CHECfg
- 0x1007f52e 0xab _zPHY_ecsi_Start
- 0x1007f5d9 0x66 _zPHY_ecsi_CSIAThreadEntry
- .text 0x1007f63f 0x104d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
- 0x1007f63f 0x26 _L1e_DevDlsGetTbCrc
- 0x1007f665 0x16 _L1e_DevDlsGetTbCbCrc
- 0x1007f67b 0x9c _L1e_DevDlsSetDlHarqFlag
- 0x1007f717 0x43 _L1e_DevDlsGetDdtrWorkSf
- 0x1007f75a 0x89 _zPHY_edls_ProCwCrcGeneration
- 0x1007f7e3 0xfa _zPHY_edls_ProTddCwCrcFeedback
- 0x1007f8dd 0x56 _zPHY_edls_ProFddCwCrcFeedback
- 0x1007f933 0x115 _zPHY_edls_ProHarqFeedbackInfo
- 0x1007fa48 0x11e _zPHY_edls_ProDdtrHbitInt
- 0x1007fb66 0xb3 _zPHY_edls_ProDdtrIntDtch
- 0x1007fc19 0xa2 _zPHY_edls_ProDdtrIntSibPch
- 0x1007fcbb 0x64 _L1e_DbgDlsDecPchInfo
- 0x1007fd1f 0x2d _L1e_DevDlsPageMatch
- 0x1007fd4c 0x5e _L1e_DevDlsPchMessagePro
- 0x1007fdaa 0x5b _L1e_DevDlsPchReportInd
- 0x1007fe05 0x56 _zPHY_edls_ProPchDataProc
- 0x1007fe5b 0x48 _zPHY_edls_ProSibDataProc
- 0x1007fea3 0x5b _zPHY_edls_ProPchStatAndPrint
- 0x1007fefe 0x53 _zPHY_edls_ProSibStatAndPrint
- 0x1007ff51 0x75 _zEumacdl_CrExist
- 0x1007ffc6 0x285 _L1e_DevDlsCfgMacPduCtrlInfo
- 0x1008024b 0x32 _L1e_DevDlsReportMacPdu
- 0x1008027d 0x1dc _zPHY_edls_ProDschIntThread
- 0x10080459 0x5c _zPHY_edls_ProMsg2RaRntiMacPdu
- 0x100804b5 0x36 _zPHY_edls_PDschIsr
- 0x100804eb 0x7f _L1e_DbgDlsAckNakRptInfo
- 0x1008056a 0x122 _L1e_DbgDlsDecStatInfo
- .text 0x1008068c 0x6f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
- 0x1008068c 0x51 _zPHY_edls_ProPdcchIntThread
- 0x100806dd 0x44 _zPHY_edls_ProMsg4CRntiPdcch
- 0x10080721 0x6a _zPHY_edls_DciIsr
- 0x1008078b 0xc _zPHY_edls_ProSetVoLteTime
- 0x10080797 0x23 _zLtePsPhy_RemoteMalloc
- 0x100807ba 0x35 _zPHY_edls_ProStoreSpsInfo
- 0x100807ef 0x17 _L1e_DevDlsRstRxRbBmpReg
- 0x10080806 0x42 _L1e_DevDlsRefSenCntPro
- 0x10080848 0x72 _L1e_DevDlsRefSenPro
- 0x100808ba 0xf _L1e_DevDlsBfInd
- 0x100808c9 0x39 _zPHY_edls_DdtrHwIdleState
- 0x10080902 0x25 _L1x_DevDlsInOutJudge
- 0x10080927 0x4e _L1e_DbgDlsCommDecInfo
- 0x10080975 0xce _L1e_DbgDlsDciInfo
- 0x10080a43 0x51 _L1e_DbgDlsDecErr
- 0x10080a94 0x1 _L1e_DbgDlsValidRptInfo
- 0x10080a95 0x58 _zPHY_edls_ProDbgSpsDciDetInfo
- 0x10080aed 0x291 _zPHY_edls_DbgHarqDdrClose
- .text 0x10080d7e 0x2d38 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
- 0x10080d7e 0x3a _zPHY_erfc_ProSetRamSFNumForLargeAdj
- 0x10080db8 0x46 _zPHY_erfc_ProGetMeas0RamNum
- 0x10080dfe 0x37 _zPHY_erfc_ProGetTxRamNum
- 0x10080e35 0x34 _zPHY_erfc_ProGetNextSubFrameOffset
- 0x10080e69 0x96 _zPHY_erfc_SupLteTxEnableCtrl
- 0x10080eff 0xc _zPHY_erfc_ProSpecSubfrmCheck
- 0x10080f0b 0x23 _zPHY_erfc_ProTxSendCtrl
- 0x10080f2e 0x25 _zPHY_erfc_SupDFESubframeStartCtl
- 0x10080f53 0x311 _zPHY_erfc_ProRamCtrl
- 0x10081264 0x1 _zPHY_erfc_ProPrintProcess
- 0x10081265 0x27 _zPHY_erfc_ProNotchProCtrl
- 0x1008128c 0x10 _zPHY_erfc_ProGetFreqBandNum
- 0x1008129c 0x238 _zPHY_erfc_TDDProRFABB_RxToRx
- 0x100814d4 0xe1 _zPHY_erfc_TDDProRFABB_RxToIdle
- 0x100815b5 0x4c _zPHY_erfc_TDDProRFABB_RxToTx
- 0x10081601 0x31 _zPHY_erfc_TDDProRFABB_IdleToTx
- 0x10081632 0x2ee _zPHY_erfc_TDDProRFABB_IdleToRx
- 0x10081920 0x1 _zPHY_erfc_TDDProRFABB_IdleToIdle
- 0x10081921 0x30 _zPHY_erfc_TDDProRFABB_TxToIdle
- 0x10081951 0x108 _zPHY_erfc_TDDProRFABB_TxToRx
- 0x10081a59 0x1 _zPHY_erfc_TDDProRFABB_TxToTx
- 0x10081a5a 0x58 _zPHY_erfc_ATSetAndReadRfReg
- 0x10081ab2 0x534 _zPHY_erfc_ProRFABBCtrl
- 0x10081fe6 0xa07 _zPHY_erfc_ProRFABBCtrl_FDD
- 0x100829ed 0x5b _zPHY_erfc_Pro_IFTempNeedFix
- 0x10082a48 0x343 _zPHY_erfc_ProRFCWork
- 0x10082d8b 0x58 _zPHY_erfc_ProRxOffsetAutoCtrl
- 0x10082de3 0x10 _zPHY_erfc_ProTAOffsetAutoCtrl
- 0x10082df3 0x3b8 _zPHY_erfc_ProTxAndRxOffsetCtrl
- 0x100831ab 0xe _zPHY_erfc_ProRFSDInit
- 0x100831b9 0xa _zPHY_erfc_ProRFCSA_CSRConfig
- 0x100831c3 0xe _zPHY_erfc_ProRFCSA_RXConfig
- 0x100831d1 0xa _zPHY_erfc_ProRFCSA_TXConfig
- 0x100831db 0x95 _zPHY_erfc_ProRFSDAndRFCSAInit
- 0x10083270 0x4b _zPHY_erfc_RpiCfg
- 0x100832bb 0x1d _zPHY_erfc_RpiSet
- 0x100832d8 0x5d _zPHY_erfc_RpiPwrCtrl
- 0x10083335 0x72 _zPHY_erfc_ProRFCSAInit
- 0x100833a7 0x68 _zPHY_erfc_ProRFCInit
- 0x1008340f 0x54 _zPHY_erfc_ProRFCInitPointer
- 0x10083463 0x18d _zPHY_erfc_ProRfsdCheck_FDD
- 0x100835f0 0x3f _zPHY_erfc_CheckNextSccRfcToIdle
- 0x1008362f 0x17 _zPHY_erfc_ProGetRFCCurrentState
- 0x10083646 0x1e2 _zPHY_erfc_ThreadEntry
- 0x10083828 0x16 _zPHY_erfc_GetRfcMeasStatus
- 0x1008383e 0x19 _zPHY_erfc_TjpAlgorithm
- 0x10083857 0x3d _zPHY_erfc_CalcMeasSubfNum
- 0x10083894 0x3f _zPHY_erfc_CalcSyncSubfNum
- 0x100838d3 0x1a _zPHY_erfc_IntraFrameTimeComp
- 0x100838ed 0x1 _zPHY_erfc_ProCleanHWTable
- 0x100838ee 0x47 _zPHY_erfc_LTXTxTaConfig
- 0x10083935 0x36 _zPHY_erfc_ProCopyTxPccParaToScc
- 0x1008396b 0x1 _zPHY_erfc_RXTX_PathTest
- 0x1008396c 0x27 _zPHY_erfc_MainSlave_InterSwitch
- 0x10083993 0x5b _zPHY_erfc_GetTxTabAdjust
- 0x100839ee 0xa _zPHY_erfc_GetFixDlDelay
- 0x100839f8 0xd _L1l_DevRfcRxOffsetGet
- 0x10083a05 0xd _L1l_DevRfcTaTimingGet
- 0x10083a12 0x9 _L1l_DevRfcRatModeSet
- 0x10083a1b 0xc _L1l_DevRfcTmpReadEn
- 0x10083a27 0x81 _L1l_DevRfcTmpReadCtrl
- 0x10083aa8 0x7 _L1l_DevRfcSetOffsetFlag
- 0x10083aaf 0x7 _L1l_DevRfcGetOffsetFlag
- .text 0x10083ab6 0x2c1d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
- 0x10083ab6 0xf _zPHY_eCSI_Calc_MultiPmiAddr_Init
- 0x10083ac5 0x8 _OSMemCopy16
- 0x10083acd 0x6 _OSMemCopy32
- 0x10083ad3 0x23 _IsTM9_PMIRIEn_CSIRS_2_4
- 0x10083af6 0x16 _IsTM8_PMIRIEn
- 0x10083b0c 0x1a _zPHY_eCSI_Calc_Sort
- 0x10083b26 0x27 _zPHY_eCSI_Calc_MaxM
- 0x10083b4d 0x16 _zPHY_eCSI_Calc_CapMaxVal
- 0x10083b63 0x20 _zPHY_eCSI_Calc_GetSubbandIdx
- 0x10083b83 0x6c _zPHY_eCSI_Calc_eesm
- 0x10083bef 0x59 _zPHY_eRLM_Calc_eesm
- 0x10083c48 0x161 _zPHY_eCSI_Calc_LookupCqiTable
- 0x10083da9 0x47 _zPHY_eCSI_Calc_WideTotalCapCalc
- 0x10083df0 0x33 _zPHY_eCSI_Calc_WideTotalCapCalc_PerRI
- 0x10083e23 0x8e _zPHY_eCSI_Calc_WideHigh2UESubCap
- 0x10083eb1 0x10c _zPHY_eCSI_Calc_BPMI
- 0x10083fbd 0x3e _zPHY_eCSI_Calc_SPMI
- 0x10083ffb 0x185 _zPHY_eCSI_Calc_RI_TM3
- 0x10084180 0x127 _zPHY_eCSI_Calc_WPMI_TM4_LastRI
- 0x100842a7 0x2d0 _zPHY_eCSI_Calc_RI_WPMI_TM4
- 0x10084577 0xe5 _zPHY_eCSI_Adjust_RI_PMI
- 0x1008465c 0x2e4 _zPHY_eCSI_Calc_RI_PMI
- 0x10084940 0xd6 _zPHY_eCSI_Calc_WbCQICalc
- 0x10084a16 0x98 _zPHY_eCSI_Calc_NoPmiGetMsbIdx
- 0x10084aae 0x82 _zPHY_eCSI_Calc_MsbCqiCalc
- 0x10084b30 0xc1 _zPHY_eCSI_Calc_SbCqiCalc
- 0x10084bf1 0x16 _zPHY_eCSI_Calc_Curr_SBSize_Get
- 0x10084c07 0xcf _zPHY_eCSI_Calc_BpCqiCalc
- 0x10084cd6 0x6d _zPHY_eCSI_Calc_AperSbCqiUpDown
- 0x10084d43 0xb7 _zPHY_eCSI_Calc_AperCQI
- 0x10084dfa 0x9e _zPHY_eCSI_Calc_PerCQI
- 0x10084e98 0x33 _zPHY_eCSI_Calc_Radio_Monitor
- 0x10084ecb 0x19 _zPHY_eCSI_Calc_BitReversal
- 0x10084ee4 0xf _zPHY_eCSI_Calc_GetPmiBitNum
- 0x10084ef3 0x13 _zPHY_eCSI_Calc_GetMSubbandDifferentCqiValue
- 0x10084f06 0xf _zPHY_eCSI_Calc_GetSubbandDifferentCqiValue
- 0x10084f15 0x30 _zPHY_eCSI_CalcMSubbandPosition
- 0x10084f45 0x18 _zPHY_eCSI_FindDiffCQI
- 0x10084f5d 0x297 _zPHY_eCSI_PER_BagPack
- 0x100851f4 0x5ea _zPHY_eCSI_APER_BagPack
- 0x100857de 0x29 _zPHY_eCSI_PER_PmiBitLen_Estimate
- 0x10085807 0x52 _zPHY_eCSI_APER_PmiBitLen_Estimate
- 0x10085859 0x1d _zPHY_ecqi_GetLookTableSNR
- 0x10085876 0x70 _zPHY_ecsi_Calc_Pow10_inDiv10
- 0x100858e6 0x3e _zPHY_ecsi_Calc_Get_InvRow_feedA
- 0x10085924 0x49 _zPHY_ecqi_Calc_Get_InvRowB_lin
- 0x1008596d 0x243 _zPHY_ecqi_Calc_CSIRltPrint
- 0x10085bb0 0x8e _zPHY_eCSI_Calc_ParaInitInDedi
- 0x10085c3e 0x211 _zPHY_ecqi_SnrConv
- 0x10085e4f 0x1 _zPHY_ecqi_CQISnrPrint
- 0x10085e50 0x1 _zPHY_ecqi_RlmSnrPrint
- 0x10085e51 0x1 _zPHY_ecqi_RiCapPrint
- 0x10085e52 0x60 _zPHY_ecqi_CQIFilter
- 0x10085eb2 0x88 _zPHY_ecqi_Sqrt
- 0x10085f3a 0x126 _zPHY_ecsi_Calc_EstiFormatTransform
- 0x10086060 0x11 _zPHY_ecsi_Calc_LTE_RICapFollowHw0
- 0x10086071 0x12 _zPHY_ecsi_Calc_LTE_RICapFollowHw1
- 0x10086083 0x16 _zPHY_ecsi_Calc_LTE_RICapFollowHw2
- 0x10086099 0x1c _zPHY_ecsi_Calc_LTE_RICapFollowHw4
- 0x100860b5 0x149 _zPHY_ecsi_Calc_LTE_RICloseLoop
- 0x100861fe 0x18b _zPHY_ecsi_Calc_LTE_RIOpenLoop
- 0x10086389 0x90 _zPHY_ecsi_Calc_LTE_2Tx2Rx2LWbPMI
- 0x10086419 0xb1 _zPHY_ecsi_Calc_LTE_PeriodWBPmi
- 0x100864ca 0x79 _zPHY_ecsi_Calc_LTE_GetCQICalcFunc
- 0x10086543 0xab _zPHY_ecsi_Calc_LTE_GetCQISNR
- 0x100865ee 0x16 _zPHY_ecsi_Calc_LTE_PerCQISNRCalc
- 0x10086604 0x94 _zPHY_ecsi_Calc_LTE_AperCQISNRCalc
- 0x10086698 0x3b _zPHY_ecsi_Calc_LTE_RLMSNRCalc
- .text 0x100866d3 0x1592 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
- 0x100866d3 0x1b _zPHY_Dl_HwReset
- 0x100866ee 0x2a0 _zPHY_epbch_ThreadEntry
- 0x1008698e 0x9a _L1e_Bch_UpdateRxRegs
- 0x10086a28 0xa _L1e_Bch_ResetProc
- 0x10086a32 0x19 _L1e_Bch_ClkPowerCtrl
- 0x10086a4b 0x2e _L1e_Bch_JudgeSlavePbch
- 0x10086a79 0x6 _L1e_Bch_GetMaxAntCnt
- 0x10086a7f 0x1b _L1e_Bch_BwValid
- 0x10086a9a 0x10 _L1e_Bch_AntValid
- 0x10086aaa 0x7 _L1e_Bch_FrmTyeValid
- 0x10086ab1 0x7 _L1e_Bch_SpecPatValid
- 0x10086ab8 0x8e _L1e_Bch_UpdateDb
- 0x10086b46 0x72 _L1e_Bch_CellSync
- 0x10086bb8 0x2b _L1e_Bch_UpRxCtrlOps
- 0x10086be3 0x8 _L1e_Bch_ClrSyncOps
- 0x10086beb 0x7 _L1e_Bch_QuerySyncOps
- 0x10086bf2 0x45 _L1e_Bch_PreDecProc
- 0x10086c37 0x3f _L1e_Bch_UpRxState
- 0x10086c76 0x2d _L1e_Bch_InitAllGVar
- 0x10086ca3 0x2a _L1e_Bch_AddSpecTpuEvt
- 0x10086ccd 0x2d _L1e_Bch_DelAllTpuEvt
- 0x10086cfa 0x1d _L1e_Bch_DelSpecTpuEvt
- 0x10086d17 0x1a _L1e_Bch_QueryTpuEvt
- 0x10086d31 0x31 _L1e_Bch_CalStartAddr
- 0x10086d62 0x1b _L1e_Bch_GetTpuOffset
- 0x10086d7d 0x43 _L1e_Bch_CalBodryDis
- 0x10086dc0 0x1c _L1e_Bch_RegRxNewFrmEvt
- 0x10086ddc 0x1 _L1e_Bch_SaveRfcSyncTable
- 0x10086ddd 0x5e _L1e_Bch_UpRfcCfg
- 0x10086e3b 0x39 _L1e_Bch_RegTpuAdjEvt
- 0x10086e74 0x86 _L1e_Bch_InitBchRegFile
- 0x10086efa 0x72 _L1e_Bch_GenRxRsScrm
- 0x10086f6c 0xc9 _L1e_Bch_InitRxRegFile
- 0x10087035 0x6e _L1e_Bch_GetSfnOffset
- 0x100870a3 0x5d _L1e_Bch_StopMibProc
- 0x10087100 0x64 _L1e_Bch_Decode
- 0x10087164 0x89 _L1e_Bch_RltReport
- 0x100871ed 0x11 _L1e_Bch_StartMib
- 0x100871fe 0xe _L1e_Bch_GetMibIntCnt
- 0x1008720c 0x2b _L1e_Bch_ModifyParaForBldDetect
- 0x10087237 0x2a _L1e_Bch_StartAnr
- 0x10087261 0x45 _L1e_Bch_AnrDecPorc
- 0x100872a6 0xa7 _L1e_Bch_FrmIntCheck
- 0x1008734d 0xc _L1e_Bch_FristBchFrm
- 0x10087359 0xe2 _L1e_Bch_NewFrmDecPorc
- 0x1008743b 0x1a _L1e_Bch_EnableSF0RxRcv
- 0x10087455 0x9a _L1e_Bch_AdjTpuTime
- 0x100874ef 0x18 _L1e_Bch_GetMibResult
- 0x10087507 0x14 _L1e_Bch_CalcInitFrm
- 0x1008751b 0x1c _L1e_Bch_MibInfoCheck
- 0x10087537 0x3a _L1e_Bch_HandleCrcResult
- 0x10087571 0x18 _L1e_Bch_NxtBranchCtrl
- 0x10087589 0xf0 _L1e_Bch_StartNxtDecode
- 0x10087679 0x66 _L1e_Bch_DecideNxtDecode
- 0x100876df 0x5c _L1e_Bch_IntHandle
- 0x1008773b 0x49 _L1e_Bch_SaveDlapara
- 0x10087784 0x47 _L1e_Bch_ResumeDlapara
- 0x100877cb 0x53 _L1e_Bch_GetNCellRsNullInd
- 0x1008781e 0x2e _L1e_Bch_GetNCellRsNullValid
- 0x1008784c 0x17 _L1e_Bch_WriteIntraMeasResult
- 0x10087863 0x90 _L1e_Bch_GetIntraMeasResult
- 0x100878f3 0x6f _L1e_Bch_SortIntraMeasResult
- 0x10087962 0x8 _L1e_Bch_GetMibProc
- 0x1008796a 0x6d _L1e_Bch_Performance
- 0x100879d7 0x17 _L1e_Bch_ErrorMoniter
- 0x100879ee 0xc4 _L1e_Bch_RxRsrpMoniter
- 0x10087ab2 0x38 _L1e_Bch_MibReqMonitor
- 0x10087aea 0x59 _L1e_Bch_RfcTpuMonitor
- 0x10087b43 0x67 _L1e_Bch_IntRptMonitor
- 0x10087baa 0x6c _L1e_Bch_CrcRltMonitor
- 0x10087c16 0x32 _L1e_Bch_RxParaMonitor
- 0x10087c48 0x1d _L1e_Bch_SerPbchRead
- .text 0x10087c65 0x9e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
- 0x10087c65 0x7b _zPHY_edls_DlHarqReport
- 0x10087ce0 0x35 _zPHY_edls_ProDlHarqInit
- 0x10087d15 0x6d _zPHY_edls_ProGvInit
- 0x10087d82 0x8c _zPHY_edls_ProCommDlschParaInit
- 0x10087e0e 0x42 _zPHY_edls_ProSwInit
- 0x10087e50 0xc _zPHY_edls_ProMcReleaseMsg
- 0x10087e5c 0x4c _zPHY_edls_ProMsg4AckFeedback
- 0x10087ea8 0xc _zPHY_edls_ProMcResetMsg
- 0x10087eb4 0x23 _zPHY_edls_ProMcMacResetMsg
- 0x10087ed7 0x27 _zPHY_edls_CheckHarqGroupNum
- 0x10087efe 0x116 _zPHY_edls_ThreadEntry
- 0x10088014 0x4a _zPHY_edls_ProCommDlschParaCal
- 0x1008805e 0x1 _L1e_DevDlsDdtrAxiReset
- 0x1008805f 0x1 _L1e_DevDlsProcAxiReset
- 0x10088060 0xbe _L1e_DevDlsUeRacpParamInit
- 0x1008811e 0x4b _L1e_DevDlsDecoderInit
- 0x10088169 0x3e _L1e_DevDlsHarqHwInit
- 0x100881a7 0x6c _L1e_DevDlsDdtrHwInit
- 0x10088213 0x17 _L1e_DevDlsRxTMIndCfg
- 0x1008822a 0x1f _L1e_DevDlsSpsParamCfg
- 0x10088249 0x45 _L1e_DevDlsCsiRsParamCfg
- 0x1008828e 0x6d _L1e_DevDlsProcCommonMsg
- 0x100882fb 0x5e _L1e_DevDlsProcDedicatedMsg
- 0x10088359 0xa5 _L1e_DevDlsProcHandoverMsg
- 0x100883fe 0x8 _zPHY_edls_ProSetSpsMode
- 0x10088406 0x8 _zPHY_edls_ProGetSpsMode
- 0x1008840e 0xe _L1e_DevDlsSetTimeInfo
- 0x1008841c 0xd _L1e_DevDlsSetCellParam1
- 0x10088429 0xd _L1e_DevDlsSetCellparam2
- 0x10088436 0xd _L1e_DevDlsSetRntiInfo
- 0x10088443 0xf _L1e_DevDlsGetTimeInfo
- 0x10088452 0x1a _L1e_DevDlsGetCellParam1
- 0x1008846c 0x1a _L1e_DevDlsGetCellParam2
- 0x10088486 0x1a _L1e_DevDlsGetRntiInfo
- 0x100884a0 0x19 _L1e_DevDlsSetDciF1aPld
- 0x100884b9 0x10 _L1e_DevDlsSetDciF1cPld
- 0x100884c9 0x10 _L1e_DevDlsSetDciFxxPld
- 0x100884d9 0xe _L1e_DevDlsSetDciCifSize
- 0x100884e7 0xe _L1e_DevDlsSetDciRaHeaderSize
- 0x100884f5 0x10 _L1e_DevDlsSetDciRbaSize
- 0x10088505 0xe _L1e_DevDlsSetDciHarqIdSize
- 0x10088513 0xe _L1e_DevDlsSetDciDaiSize
- 0x10088521 0xe _L1e_DevDlsSetDciTpmiSize
- 0x1008852f 0xe _L1e_DevDlsSetDciScidSize
- 0x1008853d 0xe _L1e_DevDlsSetDciSrsReqSize
- 0x1008854b 0x1a _L1e_DevDlsGetDciF1aPld
- 0x10088565 0x10 _L1e_DevDlsGetDciF1cPld
- 0x10088575 0x10 _L1e_DevDlsGetDciFxxPld
- 0x10088585 0xd _L1e_DevDlsGetDciCifSize
- 0x10088592 0xd _L1e_DevDlsGetDciRaHeaderSize
- 0x1008859f 0x11 _L1e_DevDlsGetDciRbaSize
- 0x100885b0 0xd _L1e_DevDlsGetDciHarqIdSize
- 0x100885bd 0xd _L1e_DevDlsGetDciDaiSize
- 0x100885ca 0xd _L1e_DevDlsGetDciTpmiSize
- 0x100885d7 0xd _L1e_DevDlsGetDciScidSize
- 0x100885e4 0xd _L1e_DevDlsGetDciSrsReqSize
- 0x100885f1 0x8 _L1e_DevDlsDdtrUpdateCntCbInit
- 0x100885f9 0xc _L1e_DevDlsDdtrUpdateCntInc
- 0x10088605 0xc _L1e_DevDlsDdtrUpdateCntClr
- 0x10088611 0x9 _L1e_DevDlsGetDdtrCcUpdateCnt
- 0x1008861a 0x7 _L1e_DevDlsGetDdtrUpdateCnt
- 0x10088621 0x7 _L1e_DevDlsSetMsg4RaConflictCnt
- 0x10088628 0x7 _L1e_DevDlsGetMsg4RaConflictCnt
- 0x1008862f 0x9 _L1e_DevDlsMsg4RaConflictCntDec
- 0x10088638 0x8 _L1e_DevDlsMsg4RaConflictCntClr
- 0x10088640 0x8 _L1e_DevDlsGetTransMode
- .text 0x10088648 0xbf2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
- 0x10088648 0x69 _zPHY_ecsi_ctrl_Init
- 0x100886b1 0x80 _zPHY_ecsi_StaticBandParaUpdata
- 0x10088731 0x28 _zPHY_ecsi_ctrl_PeriodParaUpdate
- 0x10088759 0x7a _zPHY_ecsi_ctrl_AperiodParaUpdate
- 0x100887d3 0x7d _zPHY_ecsi_ctrl_AperRepJudge
- 0x10088850 0x3f _zPHY_ecsi_ctrl_GetSubbandIdx
- 0x1008888f 0x51 _zPHY_ecsi_ctrl_CqiPmiConfigIndexCalcTDD
- 0x100888e0 0x57 _zPHY_ecsi_ctrl_CqiPmiConfigIndexCalcFDD
- 0x10088937 0x32 _zPHY_ecsi_ctrl_RiConfigIndexCalc
- 0x10088969 0x6b _zPHY_ecsi_ctrl_GetPeriodPara
- 0x100889d4 0x14a _zPHY_ecsi_ctrl_GetPeriodRepType
- 0x10088b1e 0xcb _zPHY_ecsi_ctrl_LastRIInit
- 0x10088be9 0x4a _zPHY_ecsi_ctrl_GetMaxLayerNum
- 0x10088c33 0x71 _zPHY_ecsi_ctrl_SecondCfg
- 0x10088ca4 0x8 _zPHY_ecsi_ctrl_SentCqiRlmProMsg
- 0x10088cac 0xc _zPHY_ecsi_ctrl_RlmProEn
- 0x10088cb8 0x87 _zPHY_ecsi_ctrl_FirIntPrint
- 0x10088d3f 0xa9 _zPHY_ecsi_ctrl_FdBkFirst_IntIsr
- 0x10088de8 0x1e _zPHY_ecsi_ctrl_FdBkSecond_IntIsr
- 0x10088e06 0x1b _zPHY_ecsi_ctrl_FdBk_IntIsr
- 0x10088e21 0x5c _zPHY_ecsi_ctrl_First_GetEnStep1
- 0x10088e7d 0x69 _zPHY_ecsi_ctrl_FdBkFirCfgAper
- 0x10088ee6 0xbd _zPHY_ecsi_ctrl_FdBkFirCfgPer
- 0x10088fa3 0xcd _zPHY_ecsi_ctrl_First_FdBkCfg
- 0x10089070 0x3a _zPHY_ecsi_ctrl_ULGetCSI_Callback
- 0x100890aa 0x71 _zPHY_ecsi_Ctrl_CqiRlmCalc
- 0x1008911b 0x2f _zPHY_ecsi_ctrl_PreBagPack
- 0x1008914a 0x33 _zPHY_ecsi_ctrl_FindPreDlSfn
- 0x1008917d 0xbd _zPHY_ecsi_ctrl_DrxRfZspCtrl
- .text 0x1008923a 0x1aac T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
- 0x1008923a 0x7 _L1e_DevRxGetAveSinr
- 0x10089241 0x1d _zPHY_erxp_convert_RbNum_to_BWIdx
- 0x1008925e 0x7 _L1e_DevRxCirSetIdleAccessReqInd
- 0x10089265 0x7 _L1e_DevRxCirGetIdleAccessReqInd
- 0x1008926c 0x1b2 _zPHY_erxph_ThreadEntry
- 0x1008941e 0x173 _L1e_DevRxPowerPrepare
- 0x10089591 0x55 _L1e_DevRxGetSnrFilterFactor
- 0x100895e6 0xa0 _zPHY_erxp_PowerFilterInit
- 0x10089686 0x97 _zPHY_erxp_ProPowerFilter
- 0x1008971d 0x149 _zPHY_erxp_ProSnrMake
- 0x10089866 0x64 _zPHY_erxp_ProSnrDB
- 0x100898ca 0x54 _zPHY_erxp_ProLog2
- 0x1008991e 0x19e _L1e_DevRxProcPwrNbnb
- 0x10089abc 0x8a _L1e_DevRxCalcRsrpPwr
- 0x10089b46 0x36 _L1e_DevRxProcSnrPwrFilter
- 0x10089b7c 0x50 _L1e_DevRxCalcLinearSnr
- 0x10089bcc 0x3e _L1e_DevRxCalcLinearSinr
- 0x10089c0a 0x5c _L1e_DevRxConvertSnrDbValue
- 0x10089c66 0x88 _L1e_DevRxCalcAveSnr
- 0x10089cee 0xa _L1e_DevRxGetAveSnr
- 0x10089cf8 0xa _L1e_DevRxGetNeiAveSnr
- 0x10089d02 0x14 _L1e_DevRxCalSign
- 0x10089d16 0xa6 _L1e_DevRxCalcMod
- 0x10089dbc 0x6e _L1e_DevRxDbgMsgRxCrsPwr
- 0x10089e2a 0x91 _L1e_DevRxDbgMsgRxDrsPwr
- 0x10089ebb 0x56 _L1e_DevRxDbgMsgRxSnrInfo
- 0x10089f11 0x81 _L1e_DevRxDbgMsgSyncInfo
- 0x10089f92 0x48 _L1e_LogDevRxMbsfnCsiInfo
- 0x10089fda 0x54 _L1e_DevRxDbgMsgRxHResult
- 0x1008a02e 0x54 _L1e_DevRxDbgMsgRxPrbN0
- 0x1008a082 0x17 _L1e_DevRxExpInfo
- 0x1008a099 0x1c _L1e_DevRxRssiRead
- 0x1008a0b5 0x2b _L1e_DevRxRspRead
- 0x1008a0e0 0x25 _L1e_DevRxRsrpRead
- 0x1008a105 0x43 _L1e_DevRxN0Read
- 0x1008a148 0x15 _L1e_DevRxMrsN0Read
- 0x1008a15d 0x7a _L1e_DevRxGetRxLogInfo
- 0x1008a1d7 0x20 _L1e_DevRxGetDfeAgcGain
- 0x1008a1f7 0x14 _L1e_DevRxGetRxAntNum
- 0x1008a20b 0x7 _L1e_DevRxSetSingleAntInd
- 0x1008a212 0x7 _L1e_DevRxGetSingleAntInd
- 0x1008a219 0x9 _L1e_DevRxSetNbNbSinrCalInd
- 0x1008a222 0x9 _L1e_DevRxGetNbNbSinrCalInd
- 0x1008a22b 0x9 _L1e_DevRxSetDrsAccNum
- 0x1008a234 0x9 _L1e_DevRxGetDrsAccNum
- 0x1008a23d 0x9 _L1e_DevRxSetBfDagcFlag
- 0x1008a246 0x9 _L1e_DevRxGetBfDagcFlag
- 0x1008a24f 0x5f _L1e_DevRxProcBfDagcFlag
- 0x1008a2ae 0x7 _L1e_DevRxPrintCtrlCfg
- 0x1008a2b5 0x7 _L1e_DevRxPrintCtrlGet
- 0x1008a2bc 0x9 _L1e_DevRxPrintCtrlCnt
- 0x1008a2c5 0x22c _L1e_DevRxCalcCsi
- 0x1008a4f1 0x11c _L1e_DevRxCsiLog
- 0x1008a60d 0xe _L1e_DevRxSetAntChangeInd
- 0x1008a61b 0xd _L1e_DevRxGetAntChangeInd
- 0x1008a628 0xb4 _zPHY_erxp_RX_DFE_UERS
- 0x1008a6dc 0x10 _zPHY_erxp_RX_SNR
- 0x1008a6ec 0xe _L1e_DevRxSetCfoWorkInd
- 0x1008a6fa 0xd _L1e_DevRxGetCfoWorkInd
- 0x1008a707 0x1f _L1e_DevRxSetSinrInd
- 0x1008a726 0x10 _L1e_DevRxGetSinrInd
- 0x1008a736 0x2b _L1e_DevRxGetLowSinrInd
- 0x1008a761 0x11 _L1e_DevReadSnr
- 0x1008a772 0x8 _L1e_DevRxClearFilterInd
- 0x1008a77a 0x42 _L1e_DevGetNeiBorCellMaxSnr
- 0x1008a7bc 0x7 _L1e_DevRxGetCellComponState
- 0x1008a7c3 0x7 _L1e_DevRxSetCellComponState
- 0x1008a7ca 0x7 _L1e_DevRxSetAdaptAntProcInd
- 0x1008a7d1 0x7 _L1e_DevRxGetAdaptAntProcInd
- 0x1008a7d8 0xaa _L1e_DevRxAdaptAntProc
- 0x1008a882 0x44 _L1e_DevRxAdaptAntResult
- 0x1008a8c6 0x3a _L1e_DevRxAdaptAntUpdate
- 0x1008a900 0x36 _L1e_DevRxAdaptSinrAcc
- 0x1008a936 0x101 _L1e_DevRxAdaptCalSinr
- 0x1008aa37 0x34 _L1e_DevRxAdaptAgcGainAcc
- 0x1008aa6b 0x10 _L1e_DevRxAdaptGetAveResult
- 0x1008aa7b 0x8 _L1e_DevRxAdaptGetRsrpRange
- 0x1008aa83 0x58 _L1e_DevRxAdaptSetRsrpInterval
- 0x1008aadb 0x13 _L1e_DevRxClrAdaptAntInfo
- 0x1008aaee 0xa _L1e_DevRxAdaptBetaUpdate
- 0x1008aaf8 0x26 _L1e_DevRxAdaptJudge
- 0x1008ab1e 0xa _L1e_DevRxIncN1Timer
- 0x1008ab28 0x8 _L1e_DevRxGetN1Timer
- 0x1008ab30 0x9 _L1e_DevRxClrN1Timer
- 0x1008ab39 0x8 _L1e_DevRxSetN1StartInd
- 0x1008ab41 0x8 _L1e_DevRxGetN1StartInd
- 0x1008ab49 0xa _L1e_DevRxIncN2Timer
- 0x1008ab53 0x9 _L1e_DevRxClrN2Timer
- 0x1008ab5c 0x8 _L1e_DevRxGetN2Timer
- 0x1008ab64 0x8 _L1e_DevRxSetN2StartInd
- 0x1008ab6c 0x8 _L1e_DevRxGetN2StartInd
- 0x1008ab74 0x8 _L1e_DevRxSetAdaptStartInd
- 0x1008ab7c 0xa _L1e_DevRxGetDLTimer
- 0x1008ab86 0x8 _L1e_DevRxGetAdaptStartInd
- 0x1008ab8e 0x8 _L1e_DevRxGetAdaptResult
- 0x1008ab96 0x8 _L1e_DevRxSetAdaptResult
- 0x1008ab9e 0x8 _L1e_DevRxSetAdaptChangeInd
- 0x1008aba6 0x8 _L1e_DevRxGetAdaptChangeInd
- 0x1008abae 0x64 _L1e_DevRxDbgAdptAntInfo
- 0x1008ac12 0x6f _L1e_DevRxDbgAdptchangeInfo
- 0x1008ac81 0x65 _L1e_DevRxAntInfoGetForTool
- .text 0x1008ace6 0x1d43 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
- 0x1008ace6 0x69 _zPHY_LteaSysInfoPrint
- 0x1008ad4f 0x1d _L1L_elpc_Dvfs
- 0x1008ad6c 0x107 _zPHY_elpc_LtePhyTaskStateInfo
- 0x1008ae73 0x9 _zPHY_elpc_SetCfunFlg
- 0x1008ae7c 0x42 _zPHY_elpc_SetLteCamonFlag
- 0x1008aebe 0x22 _zPHY_elpc_SetLteConnectFlag
- 0x1008aee0 0x28 _zPHY_elpc_SetIratGapReportFlag
- 0x1008af08 0x19 _L11_DrvLpcModemIntCtrl
- 0x1008af21 0xe _zPHY_elpc_SetlLtePhySleepFlag
- 0x1008af2f 0x1f _zPHY_elpc_LteIdleTaskStateCtrl
- 0x1008af4e 0x264 _zPHY_elpc_UpdateLteSubFrameNum
- 0x1008b1b2 0x24 _L1L_UpdateAwakeTimer
- 0x1008b1d6 0x1e _L1L_SetAwakeTimer
- 0x1008b1f4 0xc _L1L_IsAwakeTimerEnable
- 0x1008b200 0x38 _zPHY_elpc_ProKeepAwakeTimer
- 0x1008b238 0x87 _zPHY_elpc_ProSleepTimer
- 0x1008b2bf 0x33 _L1_TdSleepInfoPrint
- 0x1008b2f2 0x18 _zPHY_eLpc_GetLpm32KCALIPara
- 0x1008b30a 0x339 _L1_CpuPhySleepInfo
- 0x1008b643 0x34 _L1L_PrintPwrCtrlInfo
- 0x1008b677 0x29 _L1L_PrintModemClkCtrlInfo
- 0x1008b6a0 0x8e _zPHY_elpc_LpmCalibrationLog
- 0x1008b72e 0x50 _zPHY_elpc_GetLpmCaliIdx
- 0x1008b77e 0x7e _zPHY_elpc_LpmCalibrationProc
- 0x1008b7fc 0x11 _zPHY_elpc_LpmCalibrationParaUpdate
- 0x1008b80d 0x40 _zPHY_eLpc_RecordTpuMrtrForCaliTest
- 0x1008b84d 0xf _zPHY_elpc_IsRfStateIdle
- 0x1008b85c 0x1 _zPHY_elpc_RficSccSleepCtrl
- 0x1008b85d 0x63 _zPHY_eLpc_Lpm32KCALIInfor
- 0x1008b8c0 0xf1 _zPHY_eLpc_PintCpuAxiFreq
- 0x1008b9b1 0x17 _zPHY_eLpc_PrintIcpResult
- 0x1008b9c8 0x19b _zPHY_eLpc_ChipCfgInfor
- 0x1008bb63 0x8e _zPHY_eLpc_TimeSysInfo
- 0x1008bbf1 0x4b4 _zPHY_elpc_CaliTempCompensate
- 0x1008c0a5 0xb _L1L_eLpc_AsynMsgProc
- 0x1008c0b0 0x2c1 _L1L_elpc_WakeupMsgFlow
- 0x1008c371 0x23a _L1L_elpc_LpmWakeupFlow
- 0x1008c5ab 0x94 _L1L_LPInit
- 0x1008c63f 0x2 _zPHY_elpc_Init
- 0x1008c641 0x6d _L1L_LpcCfgSocWkupInt
- 0x1008c6ae 0x14 _L1L_LpcDisSocWkupInt
- 0x1008c6c2 0x15 _L1L_WakeupIsr
- 0x1008c6d7 0x2b4 _L1L_ModemLpcSleep
- 0x1008c98b 0x9e _L1L_ModemLpcWakeup
- .text 0x1008ca29 0xfab T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
- 0x1008ca2b 0x3d _zPHY_erfc_DrvCheckNVBandWithRFBand
- 0x1008ca68 0x3b _zPHY_erfc_FindNVBandWithRFBand
- 0x1008caa3 0x3e _zPHY_erfc_DrvCheckTpCompNV
- 0x1008cae1 0x2a _zPHY_erfc_SupBinarySearchNv
- 0x1008cb0b 0xad _zPHY_erfc_SupSampleRateSet
- 0x1008cbb8 0x85 _zPHY_erfc_SupNVBandIndexInit
- 0x1008cc3d 0x1b _zPHY_erfc_SupGlobalVarInit
- 0x1008cc58 0x18e _zPHY_erfc_InitTableByDma
- 0x1008cde6 0x1 _zPHY_erfc_SupIntTxTable
- 0x1008cde7 0x129 _zPHY_erfc_SupIntRFC
- 0x1008cf10 0x1e _zPHY_erfc_SupBinarySearchAdc
- 0x1008cf2e 0x39 _zPHY_erfc_SupCalcDiffpower
- 0x1008cf67 0x38 _zPHY_erfc_SupCalcDiffpower7510ACP
- 0x1008cf9f 0x36 _zPHY_erfc_SupEventRxoffsetEn
- 0x1008cfd5 0x1c _zPHY_erfc_SupTxSymbSend
- 0x1008cff1 0xa _zPHY_erfc_SupTxFclkCtrl
- 0x1008cffb 0x2e _zPHY_erfc_SupDFEFrontEsti
- 0x1008d029 0x11 _zPHY_erfc_SupDFEpath0RxControl
- 0x1008d03a 0x1a _zPHY_erfc_SupDFERxDAGC0estiControl
- 0x1008d054 0x27 _zPHY_erfc_SupDFERxRemovCpControl
- 0x1008d07b 0x11 _zPHY_erfc_SupDFEpath1Meas0Control
- 0x1008d08c 0x1f5 _zPHY_erfc_SupDFEMeas0RemovCpControl
- 0x1008d281 0x66 _zPHY_erfc_SupDFEMeas0eICICControl
- 0x1008d2e7 0x21 _zPHY_erfc_SupDFEpath2CellSearchControl
- 0x1008d308 0x2b _zPHY_erfc_SupDFECellSearchDAGC2estiControl
- 0x1008d333 0x1 _zPHY_erfc_SupDFEMeas0DAGC1estiControl
- 0x1008d334 0x3a _zPHY_erfc_SupDFESubframeStart
- 0x1008d36e 0x14 _zPHY_erfc_SupDFEFrameStart
- 0x1008d382 0x1 _zPHY_erfc_SupSetTDDFDD
- 0x1008d383 0x24 _zPHY_erfc_SupEnterLowPower
- 0x1008d3a7 0x296 _zPHY_erfc_SupLeaveLowPower
- 0x1008d63d 0x1 _zPHY_erfc_SupRfGPIOOpen
- 0x1008d63e 0x41 _zPHY_erfc_SupRfRxOpen
- 0x1008d67f 0x1 _zPHY_erfc_SupRfGPIOClose
- 0x1008d680 0x1 _zPHY_erfc_SupRfRxClose
- 0x1008d681 0x23 _zPHY_erfc_SupRfEnterLightSleep
- 0x1008d6a4 0x26 _zPHY_erfc_SupRfEnterDeepSleep
- 0x1008d6ca 0x22 _zPHY_erfc_SupRfLeaveLightSleep
- 0x1008d6ec 0x23 _zPHY_erfc_SupRfLeaveDeepSleep
- 0x1008d70f 0x2c _zPHY_erfc_SupRfLeaveSleep
- 0x1008d73b 0x24 _zPHY_erfc_SupRfWakeUpRxOpen
- 0x1008d75f 0x1e _zPHY_erfc_SupRfRxCloseSleep
- 0x1008d77d 0x4d _zPHY_erfc_SupGetUserNVBandIndex
- 0x1008d7ca 0x3a _zPHY_erfc_SupGetCaliNVBandIndex
- 0x1008d804 0x6f _zPHY_erfc_SupNotchEn
- 0x1008d873 0xa _zPHY_erfc_SupWriteTempCompDacToIram
- 0x1008d87d 0x157 _zPHY_erfc_SupGetRBESF
- .text 0x1008d9d4 0x5f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
- 0x1008d9d4 0x12 _zPHY_ecsrm_ProReset
- 0x1008d9e6 0x17 _zPHY_ecsrm_InitialGlobalVar
- 0x1008d9fd 0x55 _zPHY_ecsrm_IsBlackCell
- 0x1008da52 0x88 _zPHY_ecsrm_BuffGetEveryRfcOpenTime
- 0x1008dada 0xe3 _zPHY_ecsrm_GetRfcOpenTime
- 0x1008dbbd 0xba _zPHY_ecsrm_GetRfcOpenTimeFddIdle
- 0x1008dc77 0x8 _zPHY_ecsrm_SetDdMode
- 0x1008dc7f 0x94 _zPHY_ecsrm_CfgRfcData
- 0x1008dd13 0x2 _zPHY_ecsrm_OnReset
- 0x1008dd15 0x4a _zPHY_ecsrm_OnSearchMeasStart
- 0x1008dd5f 0x12 _zPHY_ecsrm_OnSearchMeasReset
- 0x1008dd71 0x21 _zEcsm_PreEvent
- 0x1008dd92 0x38 _L1e_csrm_SfProc
- 0x1008ddca 0x1fe _zPHY_ecsrm_WriteRfcEventTabNew
- .text 0x1008dfc8 0x1eef T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
- 0x1008dfc8 0x3d _zPHY_ecsrm_AveMeasResult
- 0x1008e005 0x18 _zPHY_ecsrm_AveValLog
- 0x1008e01d 0x8 _zPHY_ecsrm_CalSint16ResVal
- 0x1008e025 0x2 _zPHY_ecsrm_PointToInt
- 0x1008e027 0x21 _zPHY_ecsrm_CalApproValLog
- 0x1008e048 0x8 _zPHY_ecsrm_ClearMeasResult
- 0x1008e050 0xd _zPHY_ecsrm_InitialMeasCommPara
- 0x1008e05d 0x9 _zPHY_ecsrm_RegistPeriodSfInt
- 0x1008e066 0xc _L1e_csrm_ClearCurCellInfo
- 0x1008e072 0xfa _zPHY_ecsrm_JudgeMeasState
- 0x1008e16c 0x1f _zPHY_escrm_GetFbRelatn
- 0x1008e18b 0x2b _zPHY_ecsrm_GetRsNumLogIndex
- 0x1008e1b6 0x34 _zPHY_ecsrm_CalModVal
- 0x1008e1ea 0x59 _zPHY_ecsrm_Q8log2
- 0x1008e243 0x3c _zPHY_ecsrm_Logarithm
- 0x1008e27f 0x3b _zPHY_ecsrm_GetAntAgcCsrm
- 0x1008e2ba 0x17 _zPHY_ecsrm_CfgDfeBandCsr
- 0x1008e2d1 0x3b _zPHY_ecsrm_GetAntAgcRx
- 0x1008e30c 0x119 _zPHY_ecsrm_ReadRsrpNvInfo
- 0x1008e425 0x19 _zPHY_ecsrm_CalLog
- 0x1008e43e 0x25 _zPHY_ecsrm_ReadCaliNvPoint
- 0x1008e463 0x26 _zPHY_ecsrm_WriteMeasResult
- 0x1008e489 0xa4 _zPHY_ecsrm_CalRsrpOffset
- 0x1008e52d 0x1ee _zPHY_ecsrm_CalRsrpRssi
- 0x1008e71b 0xe3 _zPHY_ecsrm_CalRsrpForRx
- 0x1008e7fe 0x18 _zPHY_ecsrm_ReadRealOffet
- 0x1008e816 0xf1 _zPHY_ecsrm_CalSinr
- 0x1008e907 0x9 _zPHY_ecrsm_DelAllTpuInt
- 0x1008e910 0x2e _zPHY_ecsrm_Buffer_TDDMode
- 0x1008e93e 0x36 _zPHY_ecsrm_Idle_Buffer_FddMode
- 0x1008e974 0x29 _zPHY_ecsrm_Idle_FddMode
- 0x1008e99d 0x2c _zPHY_ecsrm_Idle_FddScheInAny
- 0x1008e9c9 0x31 _zPHY_ecsrm_Idle_FddReadInAny
- 0x1008e9fa 0x26 _zPHY_ecsrm_ClearMeasCellInfo
- 0x1008ea20 0x40 _zPHY_ecsrm_ClearBuffInfo
- 0x1008ea60 0x34 _zPHY_ecsrm_half_FrameBoundrySub
- 0x1008ea94 0x25 _zPHY_ecsrm_BuffSlaveHFS
- 0x1008eab9 0x44 _zPHY_ecsrm_BuffSlaveMaxBdySub
- 0x1008eafd 0x13 _zPHY_ecsrm_GetCurrCellId
- 0x1008eb10 0x97 _zPHY_ecsrm_UpdateResIntoDbNew
- 0x1008eba7 0x2e _zPHY_ecsrm_ClearMeasResultNew
- 0x1008ebd5 0x5d _zPHY_ecsrm_UpdateMeasResultNew
- 0x1008ec32 0x2a _zPHY_ecsrm_Half_Frame_Bdy_Sub
- 0x1008ec5c 0x25 _zPHY_ecsrm_GetBuffSlaveOpenSfNum
- 0x1008ec81 0x3d _zPHY_ecsrm_GetBuffMeasSfNum
- 0x1008ecbe 0x2c _zPHY_ecsrm_GetMeasSfNum
- 0x1008ecea 0x10a _zPHY_ecsrm_CalRsrpNew
- 0x1008edf4 0x29 _zPHY_ecsrm_GetNextSchTime
- 0x1008ee1d 0x1c _zPHY_ecsrm_ClearMeasSch
- 0x1008ee39 0x6a _zPHY_ecsrm_DiscardMeas
- 0x1008eea3 0x81 _GetMeasInfo
- 0x1008ef24 0x50 _SetMeasAgeInfo
- 0x1008ef74 0xbf _zPHY_ecsrm_MeasGetCell
- 0x1008f033 0x10e _zPHY_ecsrm_GetCsrmRegParaNew
- 0x1008f141 0x69 _zPHY_ecsrm_GetDFEBuffFbRelatn
- 0x1008f1aa 0xc8 _zPHY_ecsrm_GetDFEBuffRegPara
- 0x1008f272 0xb7 _zPHY_ecsrm_GetDFECellMeasPara_FDD
- 0x1008f329 0xf7 _zPHY_ecsrm_GetDFECellMeasPara_TDD
- 0x1008f420 0x97 _zPHY_ecsrm_HandleCsrHWNormalNew
- 0x1008f4b7 0x12 _zPHY_ecsrm_Need_Wait_Cnditon
- 0x1008f4c9 0x9d _zPHY_ecsrm_Wait_MeasPeriodProc
- 0x1008f566 0x9a _zPHY_ecsrm_HandleMeasResultNormalNew
- 0x1008f600 0x123 _zPHY_ecsrm_MeasSeekToWorkTime
- 0x1008f723 0xb _zPHY_ecsrm_OnMeasStart
- 0x1008f72e 0x4a _zPHY_ecsrm_MulmGapCheck
- 0x1008f778 0x162 _zPHY_ecsrm_MeasConfigHw
- 0x1008f8da 0xc0 _zPHY_ecsrm_MeasReadResult
- 0x1008f99a 0x23 _zPHY_ecsrm_BufferScene
- 0x1008f9bd 0x32 _zPHY_ecsrm_CsrFingerSort
- 0x1008f9ef 0x4 _zPHY_ecsrc_RemoveMrtrFrame
- 0x1008f9f3 0x58 _zPHY_ecsrm_half_FrameBoundryCenter
- 0x1008fa4b 0x4e _zPHY_ecsrm_GetBdyMeasCell
- 0x1008fa99 0x215 _zPHY_ecsrm_GetMeasmodeAndCell
- 0x1008fcae 0x25 _zPHY_ecsrm_GetMeasCellEarfcn
- 0x1008fcd3 0xd3 _eL1_CalCellCfgCont
- 0x1008fda6 0x2c _zPHY_ecsrm_GetSF0SF5
- 0x1008fdd2 0x2d _zPHY_ecsrm_BeforeBufferMeas
- 0x1008fdff 0x95 _zPHY_ecsrm_MeasNextCell
- 0x1008fe94 0x7 _zPHY_ecsrm_SetCaIndex
- 0x1008fe9b 0x10 _zPHY_ecsrm_MeasNeedPrimary
- 0x1008feab 0xc _l1e_csrm_GetMeasFalg
- .text 0x1008feb7 0x31e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
- 0x1008feb7 0x1c1 _zPHY_UL_CSI_CombThreadEntry
- 0x10090078 0x15d _zPHY_DLA_ULSL_CombThreadEntry
- .text 0x100901d5 0x1861 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
- 0x100901d5 0x27 _L1e_DevRxFssSetModIdx
- 0x100901fc 0xcd _zPHY_eMBMS_CirSearchWinPos_Calc
- 0x100902c9 0x27 _L1e_DevRxDoubleAntCheckOnlyOneValid
- 0x100902f0 0x3d _L1e_DevCirPreSyncAcc
- 0x1009032d 0x5e _L1e_DevCirPreSyncProtect
- 0x1009038b 0x43 _zPHY_erxp_CirProc
- 0x100903ce 0x25 _zPHY_erxp_CirAdjBorderOfSubframe
- 0x100903f3 0x9 _zPHY_eCir_PccPdsch_DmaCallback
- 0x100903fc 0x9 _zPHY_eCir_SccPdsch_DmaCallback
- 0x10090405 0x9 _zPHY_eCir_PccEicic_DmaCallback
- 0x1009040e 0x8 _L1e_DevRxSetMbsfnCirIntInt
- 0x10090416 0x1a _L1e_DevRxMbmsCirIntProc
- 0x10090430 0x44 _L1e_DevRxFssMainAntFlagSet
- 0x10090474 0xd _L1e_DevRxFssMainAntFlagGet
- 0x10090481 0xe _L1e_DevRxRefSenDecodeCnt
- 0x1009048f 0xd _L1e_DevRxRefSenDecodeCntGet
- 0x1009049c 0xd _L1e_DevRxRefSenDecodeCntClr
- 0x100904a9 0xe _L1e_DevRxRefSenCnt
- 0x100904b7 0xd _L1e_DevRxRefSenCntGet
- 0x100904c4 0xd _L1e_DevRxRefSenCntClr
- 0x100904d1 0xe _L1e_DevRxRefSenIndCfg
- 0x100904df 0xd _L1e_DevRxRefSenIndGet
- 0x100904ec 0x16 _L1e_devRxMrsFIUpdateIndSet
- 0x10090502 0x16 _L1e_devRxMrsBetaUpdateIndSet
- 0x10090518 0x18 _L1e_devRxMrsFIUpdateIndGet
- 0x10090530 0x18 _L1e_devRxMrsBetaUpdateIndGet
- 0x10090548 0x23 _L1e_devRxMrsFIDataAddrGet
- 0x1009056b 0x19 _L1e_devRxMrsBetaGet
- 0x10090584 0x93e _zPHY_eMBMS_CirInitFftSeq
- 0x10090ec2 0xa8 _zPHY_ecir_SW_DynFiRegUdate
- 0x10090f6a 0x135 _zPhy_eMBMS_cir_nomarlize_fir_coeff
- 0x1009109f 0x16a _zPHY_ecir_Apply_Triangle_Window
- 0x10091209 0xcb _zPhy_ecir_CalcBeta_R01
- 0x100912d4 0x95 _zPHY_erxp_BchNormalCirCtrl
- 0x10091369 0x23 _zPHY_erxp_CirCfgForBch
- 0x1009138c 0x577 _L1e_DevRxCirCtrlCfg
- 0x10091903 0x63 _L1e_DevRxSetRxOffsetAdjTiMode
- 0x10091966 0x7 _zPHY_ecir_CellChangeSet
- 0x1009196d 0xc9 _zPHY_ecir_CellChangeGet
- *fill* 0x10091a36 0x80000002 00
- .text 0x10091a38 0x203 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
- 0x10091a38 0xc4 _zPHY_ecir_Fft256
- 0x10091afc 0xb _zPhy_ecir_continuous_add
- 0x10091b07 0x17 _zPhy_ecir_search_max_value
- 0x10091b1e 0xa _zPhy_ecir_acquire_fir_coeff
- 0x10091b28 0x35 _zPhy_eMBMS_cir_midify_nosieEff
- 0x10091b5d 0x2d _zPhy_ecir_generet_fir_coeff
- 0x10091b8a 0x37 _zPhy_ecir_midify_nosieEff
- 0x10091bc1 0x7a _Asm_CIR_FIRCoeffNorm
- .text 0x10091c3b 0x55a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
- 0x10091c3b 0x9 _L1e_DevRxSetRsrpIntInd
- 0x10091c44 0x9 _L1e_DevRxGetRsrpIntInd
- 0x10091c4d 0x1f _L1e_DevRxSetServingCellInd
- 0x10091c6c 0x10b _zPHY_erxp_Cfo_Isr
- 0x10091d77 0x44 _L1e_DevCFOPreSyncAcc
- 0x10091dbb 0x4e _L1e_DevCfoFilterCoeffAdapt
- 0x10091e09 0x1e _L1e_DevCfoCfgTempRead
- 0x10091e27 0x59 _L1e_DevSetCfoCoeffK
- 0x10091e80 0xfb _L1e_DevGetCfoCoeffK
- 0x10091f7b 0xa _L1e_DevRxRsrpFilterFlagInit
- 0x10091f85 0x3f _L1e_DevRxGetRsrpFilterCoeff
- 0x10091fc4 0x116 _zPHY_erxp_CalRsrpFilter
- 0x100920da 0x92 _zPHY_erxp_RsrpFilter
- 0x1009216c 0xd _L1e_DevRxGetFastCfoConvergenceCnt
- 0x10092179 0xe _L1e_DevRxSetFastCfoConvergenceCnt
- 0x10092187 0xe _L1e_DevRxDecreaseFastCfoCnt
- .text 0x10092195 0x200d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
- 0x10092195 0x249 _zPHY_edfe_SupInitDFE
- 0x100923de 0x24 _zPHY_edfe_WriteSnrTh
- 0x10092402 0x71 _zPHY_edfe_DCOffsetCal
- 0x10092473 0xea _zPHY_edfe_SupNormalHandleDCOffset
- 0x1009255d 0xa9 _zPHY_edfe_IQImbaCal
- 0x10092606 0x77 _zPHY_edfe_SupHandleIQImba
- 0x1009267d 0x51 _zPHY_edfe_NormalNotSyncAgcIntHandle
- 0x100926ce 0x8 _zPHY_edfe_SupInt0Handle
- 0x100926d6 0x14 _zPHY_edfe_SupInt1Handle
- 0x100926ea 0x15 _zPHY_edfe_SupInt2Handle
- 0x100926ff 0x39 _zPHY_edfe_ProDfeInt
- 0x10092738 0x27 _zPHY_edfe_ConfigRXBandwidth
- 0x1009275f 0x22 _zPHY_edfe_ConfigCSRMBandwidth
- 0x10092781 0x7d _zPHY_edfe_CompesateCFO
- 0x100927fe 0x72 _zPHY_edfe_CalMeasTotalAGCGain
- 0x10092870 0x4c _zPHY_edfe_TotalAGCCsrm
- 0x100928bc 0x4c _zPHY_edfe_TotalAGCRx
- 0x10092908 0x2e _zPHY_edfe_SupResetDfeForRelease
- 0x10092936 0xe _zPHY_edfe_RegsTpuIntForDfe
- 0x10092944 0x91 _zPHY_edfe_RegsTpuIntForDfeCtrl
- 0x100929d5 0x1ab _zPHY_edfe_SupDfeIntCheckCtrl
- 0x10092b80 0xb4 _zPHY_edfe_PlmnSaveServCellAgcAndDagc
- 0x10092c34 0x26 _zPHY_edfe_PlmnResumeServCellAgcAndDagc
- 0x10092c5a 0x76 _zPHY_edfe_PlmnBackUpAgcPara
- 0x10092cd0 0x20 _zPHY_edfe_PlmnResumeAgcAndAfc
- 0x10092cf0 0xa _zPHY_edfe_ClearPlmnAgcPara
- 0x10092cfa 0x1ed _zPHY_edfe_SupNotSyncAGCInitCtrl
- 0x10092ee7 0x17e _zPHY_edfe_TMTPrintForFreqScan
- 0x10093065 0x8d _zPHY_edfe_ConfigAgcWorkState
- 0x100930f2 0x1b5 _zPHY_edfe_ConfigAgcCalcPara
- 0x100932a7 0xf6 _zPHY_edfe_SupInitAgcDagcGainDB
- 0x1009339d 0x5c _zPHY_edfe_SupHandleRxDagcInt
- 0x100933f9 0x1b0 _zPHY_edfe_SupHandleAgcInt
- 0x100935a9 0x43 _zPHY_edfe_StateChangeSetAgcGain
- 0x100935ec 0x12a _zPHY_edfe_GetTotalAGCGainOpt
- 0x10093716 0x67 _zPHY_edfe_SupCsrcDagcLoseDataCtrl
- 0x1009377d 0xbe _zPHY_edfe_PhySlaveDfeIntCtrlOpt
- 0x1009383b 0x2c _zPHY_edfe_TotalSubFramePwr
- 0x10093867 0x21 _zPHY_edfe_CSRSetFSNewState
- 0x10093888 0x48 _zPHY_edfe_CSRSetAGCGain
- 0x100938d0 0xfa _zPHY_edfe_SupFSNewSetRF
- 0x100939ca 0x2d _zPHY_edfe_SupNotSyncAgcIntHandle
- 0x100939f7 0x72 _zPHY_edfe_FSDCOffsetCal
- 0x10093a69 0x17 _zPHY_edfe_FSDCOffsetClear
- 0x10093a80 0x86 _zPHY_edfe_SupFSHandleDCOffset
- 0x10093b06 0x12 _zPHY_edfe_SupHandleDCOffset
- 0x10093b18 0xa9 _zPHY_edfe_SupSingAntNVControl
- 0x10093bc1 0x9 _zPHY_edfe_ConfigSingAnt
- 0x10093bca 0x86 _zPHY_edfe_SupCalAGCGainBalance
- 0x10093c50 0xfa _L1l_DevDfeNotchDbInit
- 0x10093d4a 0x3 _L1l_DevRfcNotchDbReset
- 0x10093d4d 0x14 _L1l_DevDfeNotchAgcGainSave
- 0x10093d61 0x4c _L11_DevDfeNotchBwAndSampRateGet
- 0x10093dad 0x186 _L1l_DevDfeNotchStartJudge
- 0x10093f33 0xd3 _L1l_DevDfeNotchEvtGet
- 0x10094006 0xb7 _L1l_DevDfeNotchRegSet
- 0x100940bd 0xc7 _L1l_DevDfeNotchProc
- 0x10094184 0xb _L1l_DevRfcSemiStaticAgcConvCheck
- 0x1009418f 0x13 _L1l_DevRfcAgcValGet
- .text 0x100941a2 0x1f9a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
- 0x100941a2 0xfc _zPHY_eula_Entry
- 0x1009429e 0xf9 _zPHY_eula_TpuInt1MsgPro
- 0x10094397 0x9e _zPHY_eula_TpuInt2MsgPro
- 0x10094435 0x58e _zPHY_eula_TPU_INT1_process
- 0x100949c3 0x360 _zPHY_eula_TPU_INT2_process
- 0x10094d23 0x98 _zPHY_eula_ResetDB
- 0x10094dbb 0x17 _zPHY_eula_ResetReqPro
- 0x10094dd2 0x2d4 _zPHY_eula_HandoverReqPro
- 0x100950a6 0x160 _zPHY_eula_Release
- 0x10095206 0xd7 _zPHY_eula_MACReset
- 0x100952dd 0x12d _zPHY_eula_ComCfgReqPro
- 0x1009540a 0x16d _zPHY_eula_CommRelatedParasCalc
- 0x10095577 0x156 _zPHY_eula_DediCfgReqPro
- 0x100956cd 0x51 _zPHY_eula_GetScellInfo
- 0x1009571e 0xca _zPHY_eula_DediRelatedParasCalc
- 0x100957e8 0x169 _zPHY_eula_PSGenAllWithCellID
- 0x10095951 0x5c _zPHY_eula_FuncHopCalculation
- 0x100959ad 0x5c _zPHY_eula_FuncHopCalculation_Scell
- 0x10095a09 0x35 _zPHY_eula_UlBandSampleCoeffCfg
- 0x10095a3e 0x46 _zPHY_eula_SetSampleAndFFT
- 0x10095a84 0x15 _zPHY_eula_GetSysTimeInfo
- 0x10095a99 0x13 _zPHY_eula_GetChannelType
- 0x10095aac 0x29 _zPHY_eula_GetHarqProcessId
- 0x10095ad5 0xe _zPHY_eula_CheckPuschInGap
- 0x10095ae3 0x52 _zPHY_eula_HarqNewTransNoData
- 0x10095b35 0xb0 _zPHY_eula_UL_Conflict_GAP
- 0x10095be5 0x6b _zPHY_eula_HarqSendDataCopy
- 0x10095c50 0x18 _zPHY_eula_TXInt_Pulse_Isr
- 0x10095c68 0x13 _zPHY_eula_Isr
- 0x10095c7b 0x91 _zPHY_eula_lpcHwRestoreBackupCtrl
- 0x10095d0c 0x2e6 _zPHY_eula_AMTCalcPara
- 0x10095ff2 0x106 _zPHY_amt_Lte_Tx_Create_CommonMsg
- 0x100960f8 0x44 _zPHY_PrintLocalMrtr
- .text 0x1009613c 0x121f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
- 0x1009613c 0x1a7 _zPHY_edla_Entry
- 0x100962e3 0x3e _L1e_Dla_UpBchNormalPara
- 0x10096321 0x1f7 _zPHY_edla_CdtrCfgProc
- 0x10096518 0x1a2 _zPHY_edla_GetSiRnti
- 0x100966ba 0x6a _zPHY_edla_QueryDb
- 0x10096724 0x1e _zPHY_edla_ProCalYk
- 0x10096742 0x1a9 _zPHY_edla_GetRntiInfo
- 0x100968eb 0xa8 _zPHY_edla_GetCellInfo
- 0x10096993 0x20 _zPHY_edla_GetVcInfo
- 0x100969b3 0x1a _zPHY_edla_ErrorTmGuard
- 0x100969cd 0x2c _zPHY_edla_SetDefaultTM
- 0x100969f9 0x2e _zPHY_edla_GetTimingInfo
- 0x10096a27 0x31 _L1e_DevDlaGetPhichMi
- 0x10096a58 0x1b _zPHY_edla_CommRegParaProc
- 0x10096a73 0xbe _zPHY_edla_CdtrCfgCaApply
- 0x10096b31 0x24 _zPHY_edla_CdtrCfgApply
- 0x10096b55 0xf7 _zPHY_edla_InfoCaPrepare
- 0x10096c4c 0x9 _zPHY_edla_InfoPrepare
- 0x10096c55 0x4a _zPHY_edla_IndInfoCaSet
- 0x10096c9f 0x9 _zPHY_edla_IndInfoSet
- 0x10096ca8 0x46 _zPHY_edla_ResetDcb
- 0x10096cee 0x3e _zPHY_edla_Init
- 0x10096d2c 0x1e _zPHY_edla_HwInit
- 0x10096d4a 0x1c _zPHY_edla_CacheCtrlReset
- 0x10096d66 0x3b _zPHY_edla_SaveWorkCachePara
- 0x10096da1 0x1a _zPHY_edla_UpdateRBGSize
- 0x10096dbb 0x3d _zPHY_edla_UpdateNGap1
- 0x10096df8 0x15 _zPHY_edla_UpdateNrbStep
- 0x10096e0d 0x8 _zPHY_edla_ResetCommonInfo
- 0x10096e15 0xfc _zPHY_edla_UpdateCommonInfo
- 0x10096f11 0x55 _zPHY_edla_ProCommReqMsg
- 0x10096f66 0x60 _zPHY_edla_ProDediReqMsg
- 0x10096fc6 0x56 _zPHY_edla_ProHoReqMsg
- 0x1009701c 0x24 _zPHY_edla_HoReqEx
- 0x10097040 0xd _zPHY_edla_LteAmtUpdateEarfcnInfo
- 0x1009704d 0xb _L1e_DevRxInitLpConvergeCb
- 0x10097058 0xf _L1e_DevRxSetLpConvergeInd
- 0x10097067 0x10 _L1e_DevRxGetLpConvergeInd
- 0x10097077 0x10 _L1e_DevRxSetWorkTimer
- 0x10097087 0x10 _L1e_DevRxGetWorkTimer
- 0x10097097 0x13 _L1e_DevRxIncWorkTimer
- 0x100970aa 0x27 _zPHY_edla_DebugPrint
- 0x100970d1 0x43 _zPHY_edla_ProDbgMsgRecvCommMsg
- 0x10097114 0x43 _zPHY_edla_ProDbgMsgRecvHOMsg
- 0x10097157 0x43 _zPHY_edla_ProDbgMsgRstRelMacRstMsg
- 0x1009719a 0x52 _zPHY_edla_ProDbgStateSwitchPrint
- 0x100971ec 0x3a _zPHY_edla_ProDbgMsgFuncRetErr
- 0x10097226 0x77 _zPHY_edla_ProDlCtrlChStatInfoMonitor
- 0x1009729d 0x25 _zPHY_edla_ProDlCtrlChDecodeMonitor
- 0x100972c2 0x1 _zPHY_edla_ProDlCtrlChConfigMonitor
- 0x100972c3 0x4e _zPHY_edla_PlmnReflashDlaConfig
- 0x10097311 0x1a _L1e_DevRxLpcHwRecover
- 0x1009732b 0x17 _L1e_DevDlaSetDlWorkIndBmp
- 0x10097342 0xc _L1e_DevDlaGetDlWorkIndBmp
- 0x1009734e 0xd _L1e_DevDlaGetDlBandWidth
- .text 0x1009735b 0x2ed3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
- 0x1009735b 0x1cd _zPHY_eula_ProInitial
- 0x10097528 0x68 _zPHY_eula_RegistLutrSymb
- 0x10097590 0x130 _zPHY_eula_UlDataSendCtrlInfoProcess
- 0x100976c0 0x26a _zPHY_eula_LtxParas_ACKMultiplexing
- 0x1009792a 0xec _zPHY_eula_LutrLtxParas_RIMultiplexing
- 0x10097a16 0xb _zPHY_eula_CalcInterMatrixColNumber
- 0x10097a21 0x93 _zPHY_eula_CalcRMOutputParas
- 0x10097ab4 0x8 _zPHY_eula_CalcRMOutputParasForPuschWithoutData
- 0x10097abc 0xd0 _zPHY_eula_SchdPhichRecInSad
- 0x10097b8c 0x65 _zPHY_eula_DeterMineHWChanType
- 0x10097bf1 0x194 _zPHY_eula_LTXParasCalc
- 0x10097d85 0x2c _zPHY_eula_LtxParas_wNRsZcDmrs
- 0x10097db1 0x21 _zPHY_eula_LargestPrimeNumber
- 0x10097dd2 0x28 _zPHY_eula_LtxParas_DmrsOCC
- 0x10097dfa 0x71 _zPHY_eula_LtxParas_adwQDivNRsZcDmrs
- 0x10097e6b 0x28 _zPHY_eula_LtxParas_awNcscell
- 0x10097e93 0x16 _zPHY_eula_LtxParas_acUPucch
- 0x10097ea9 0x113 _zPHY_eula_LtxParas_PucchFormat1Spec
- 0x10097fbc 0x232 _zPHY_eula_LtxParas_PucchFormat3Spec
- 0x100981ee 0x13 _zPHY_eula_LtxParas_dwX2Cinit
- 0x10098201 0x3e _zPHY_eula_LtxParas_awNcs2
- 0x1009823f 0x9e _zPHY_eula_LtxParas_ResMappingPucch
- 0x100982dd 0x14 _zPHY_eula_711712ClosePsmStub
- 0x100982f1 0x46c _zPHY_eula_RfcConfigure
- 0x1009875d 0xe7 _zPHY_eula_LutrRegConfigure
- 0x10098844 0x3da _zPHY_eula_LtxConfigure
- 0x10098c1e 0x63 _zPHY_eula_LTXTxTaConfig
- 0x10098c81 0x50 _zPHY_eula_LTXTimingFirstFlag
- 0x10098cd1 0x53 _zPHY_eula_LTXTimingLastFlag
- 0x10098d24 0x17 _zPHY_eula_ResetSrInfo
- 0x10098d3b 0x100 _zPHY_eula_SetPuchFilterCoeff1
- 0x10098e3b 0x66 _zPHY_eula_SetPrachFilterCoeff2
- 0x10098ea1 0x34 _zPHY_eula_SetPucchScale
- 0x10098ed5 0xf _zPHY_eula_GetCsiInfo
- 0x10098ee4 0x2 _zPHY_eula_FDDGetHarqAckInfo
- 0x10098ee6 0x25 _zPHY_euls_GetPucchHarqAckInfo
- 0x10098f0b 0x83 _zPHY_eula_GetPucchHarqAckLen
- 0x10098f8e 0xf7 _zPHY_eula_PucchUciProcess
- 0x10099085 0x2bc _zPHY_eula_TDD_PucchAckProcess
- 0x10099341 0x1a _zPHY_eula_FDD_PucchAckProcess
- 0x1009935b 0x70 _zPHY_eula_PucchCSI
- 0x100993cb 0x271 _zPHY_eula_PucchAckParasCalc
- 0x1009963c 0x34 _zPHY_eula_PucchN1pucchCalc
- 0x10099670 0xaa _zPHY_eula_FDD_PucchAckParasCalc
- 0x1009971a 0x25 _zPHY_eula_PSGeneration
- 0x1009973f 0x7a _zPHY_eula_SrProcess
- 0x100997b9 0x566 _zPHY_eula_LtxStub
- 0x10099d1f 0x213 _zPHY_eula_LutrStub
- 0x10099f32 0x15a _zPHY_eula_UlTwoAntenHWChanTypeDeterm
- 0x1009a08c 0xc _zPHY_eula_TATimerStop
- 0x1009a098 0x25 _zPHY_eula_PucchTwoAntenActivedDetermine
- 0x1009a0bd 0x12f _zPHY_eula_NextAckParasProcess
- 0x1009a1ec 0x3b _zPHY_eula_GetTQCfgFlg
- 0x1009a227 0x7 _zPHY_eula_PucchAntennaSelect
- .text 0x1009a22e 0x38e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
- 0x1009a22e 0x2d _zPHY_eintc_IntDispatchProcess_ICP
- 0x1009a25b 0x47 _zPHY_eintc_EnableInt
- 0x1009a2a2 0x50 _zPHY_eintc_ClearInt
- 0x1009a2f2 0x1c _L1l_DrvTopIntClr
- 0x1009a30e 0x46 _zPHY_eintc_InthInit
- 0x1009a354 0x1a _L1_LTE_LPM_T1_ISR
- 0x1009a36e 0x1 _zPHY_eintc_NullIsr
- 0x1009a36f 0xd _zPHY_DMA_CallBack_M
- 0x1009a37c 0xd _zPHY_DMA_CallBack_S
- 0x1009a389 0xd _zPHY_DMA_CallBack_CSILte
- 0x1009a396 0xd _L1e_DevCmnIntPbchIntProc
- 0x1009a3a3 0x36 _L1e_DevCmnIntCfoIntProc
- 0x1009a3d9 0x1c _L1e_DevCmnIntCrsCirIntProc
- 0x1009a3f5 0x31 _L1e_DevCmnIntCdtrIntProc
- 0x1009a426 0x24 _L1e_DevCmnIntDdtrIntProc
- 0x1009a44a 0x39 _L1e_CmnCheCqiInt
- 0x1009a483 0xe _L1e_CmnTpuSubFrameInt
- 0x1009a491 0x7 _L1e_CmnTpuAdjInt
- 0x1009a498 0xb _L1e_CmnTxPulseInt
- 0x1009a4a3 0x2d _L1e_CmnPdcchIntPcc
- 0x1009a4d0 0x3d _L1e_CmnDfeInt
- 0x1009a50d 0x2f _L1e_CmnDfeDcInt
- 0x1009a53c 0x2c _L1e_CmnPdcchPccInt
- 0x1009a568 0xd _L1e_CmnCsrDebugInt
- 0x1009a575 0xd _L1e_CmnPbchInt
- 0x1009a582 0xf _L1e_CmnPdschPccCirInt
- 0x1009a591 0x1e _L1e_CmnDdtrPccInt
- 0x1009a5af 0xd _L1e_CmnPbchIcInt
- .text 0x1009a5bc 0x1419 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
- 0x1009a5bc 0x1e9 _zPHY_eulpc_GetConfigParas
- 0x1009a7a5 0x46 _zPHY_eulpc_InitialProc
- 0x1009a7eb 0x3a _zPHY_eulpc_DeltaTcEUtraBandNoDeterm
- 0x1009a825 0x278 _zPHY_eulpc_SingleCarrierMprDeterm
- 0x1009aa9d 0x4e9 _zPHY_eulpc_NoCaAMprDeterm
- 0x1009af86 0x82 _zPHY_eulpc_PcmaxCalc
- 0x1009b008 0x132 _zPHY_eulpc_PucchTpcProc
- 0x1009b13a 0x104 _zPHY_eulpc_PuschTpcProc
- 0x1009b23e 0x44 _zPHY_eulpc_RarTpcProc
- 0x1009b282 0x6d _zPHY_eulpc_PowCtrlConfigParasCalc
- 0x1009b2ef 0x96 _zPHY_eulpc_TpcCommandsProc
- 0x1009b385 0x110 _zPHY_eulpc_CloseLoopPowCtrlProc
- 0x1009b495 0xb2 _zPHY_eulpc_Type1PhrCalc
- 0x1009b547 0x27 _zPHY_eulpc_PhrCalcProc
- 0x1009b56e 0xb7 _zPHY_eulpc_Sqrt
- 0x1009b625 0x10d _zPHY_eulpc_PowScaleValCalc
- 0x1009b732 0x37 _zPHY_eulpc_LinearValToPowDB
- 0x1009b769 0x142 _zPHY_eulpc_UlaRelativeProc
- 0x1009b8ab 0x29 _zPHY_eulpc_UlPowerStub
- 0x1009b8d4 0x1c _zPHY_eulpc_ReSetParameters
- 0x1009b8f0 0xba _zPHY_eulpc_TempMaxPowerBackoff
- 0x1009b9aa 0x2b _zPHY_eulpc_GetLatestPower
- .text 0x1009b9d5 0x134 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
- 0x1009b9d5 0x9 _L1l_DevEngInitAddr
- 0x1009b9de 0x12 _L1l_log_track_init
- 0x1009b9f0 0x46 _L1l_DevEngTrace
- 0x1009ba36 0xd1 _L1l_DevEngWriteDataToBuffer
- 0x1009bb07 0x1 _L1l_DevEngUartTransmit
- 0x1009bb08 0x1 _L1l_DevEngSwapHook
- .text 0x1009bb09 0x35a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o)
- 0x1009bb09 0x38 _zEasn1p_DcT_zEurrc_OctString
- 0x1009bb41 0x46 _zEasn1p_DcT_zEurrc_S_TMSI
- 0x1009bb87 0x5b _zEasn1p_DcT_zEurrc_IMSI
- 0x1009bbe2 0x42 _zEasn1p_DcT_zEurrc_PagingUE_Identity
- 0x1009bc24 0x56 _zEasn1p_DcT_zEurrc_PagingRecord
- 0x1009bc7a 0x4a _zEasn1p_DcT_zEurrc_PagingRecordList
- 0x1009bcc4 0x4e _zEasn1p_DcT_zEurrc_Paging_v920_IEs
- 0x1009bd12 0x49 _zEasn1p_DcT_zEurrc_Paging_v890_IEs
- 0x1009bd5b 0x8f _zEasn1p_DcT_zEurrc_Paging
- 0x1009bdea 0x36 _zEasn1p_DcT_zEurrc_PCCH_MessageType_c1
- 0x1009be20 0x3a _zEasn1p_DcT_zEurrc_PCCH_MessageType
- 0x1009be5a 0x9 _zEasn1p_DcT_zEurrc_PCCH_Message
- .text 0x1009be63 0xe7e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
- 0x1009be63 0x27 _L1e_DevDlaCalcTotRegNum
- 0x1009be8a 0x75 _L1e_DevDlaCalcSearchSpace
- 0x1009beff 0xdd _L1e_DevDlaProcPdcchSearchSpace
- 0x1009bfdc 0x11c _zPHY_edla_PdcchBldRntiEnRegProc
- 0x1009c0f8 0x6f _zPHY_edla_PdcchBldPayLoadRegProc
- 0x1009c167 0x82 _zPHY_edla_PdcchBlindDetectCaProc
- 0x1009c1e9 0xd _zPHY_edla_PdcchBlindDetectProc
- 0x1009c1f6 0x20 _zPHY_edla_GetBandWidthIdx
- 0x1009c216 0x1c _zPHY_edla_GetAmbitiousBits
- 0x1009c232 0x8c _zPHY_edla_PreDciInfo
- 0x1009c2be 0x20d _zPHY_edla_GetDciSize
- 0x1009c4cb 0x809 _zPHY_edla_PdcchDemappingCaProc
- 0x1009ccd4 0xd _zPHY_edla_PdcchDemappingProc
- .text 0x1009cce1 0x9b9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
- 0x1009cce1 0xa0 _zPHY_erfc_SupACP405ToRx
- 0x1009cd81 0x6f _zPHY_erfc_SupACP405ToIdle
- 0x1009cdf0 0x7f _zPHY_erfc_SupACP405ToTx
- 0x1009ce6f 0x82 _zPHY_erfc_SupACP405ToRxTx
- 0x1009cef1 0x1 _zPHY_erfc_SupACP405McroWriteAGC
- 0x1009cef2 0x1c _zPHY_erfc_SupGetRealWorkFreq
- 0x1009cf0e 0x46 _zPHY_erfc_ATAptPointAdjust
- 0x1009cf54 0x22 _zPHY_erfc_TxPowerAdjust
- 0x1009cf76 0xb7 _zPHY_erfc_SupGetPATuRegInfo
- 0x1009d02d 0x87 _zPHY_erfc_ProTxTempCompensate
- 0x1009d0b4 0x1d3 _zPHY_erfc_SupAPCControl
- 0x1009d287 0x6f _zPHY_erfc_SupClosePA
- 0x1009d2f6 0x1 _zPHY_erfc_SupAptReload
- 0x1009d2f7 0x109 _L1l_DevRfcAfcFreqOffsetSet
- 0x1009d400 0xd8 _zPHY_erfc_SupAfcEventSet
- 0x1009d4d8 0x43 _zPHY_erfc_SupFreqOffseToDacValue
- 0x1009d51b 0x52 _zPHY_erfc_SupDacValueToFreqOffset
- 0x1009d56d 0x36 _zPHY_erfc_SupBandNumToVcxoBitPerHz
- 0x1009d5a3 0x55 _zPHY_erfc_SupAfcVxcoInitWord
- 0x1009d5f8 0x24 _L1l_DevRfcAfcFreqOffsetGet
- 0x1009d61c 0x2e _zPHY_erfc_DCXOCordicCfg
- 0x1009d64a 0x50 _zPHY_erfc_DCXOAfcParaGet
- .text 0x1009d69a 0x45e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
- 0x1009d69a 0x20 _zPHY_edls_AdaJudgePdschTrans
- 0x1009d6ba 0x7a _zPHY_edls_AdaDecodePdcchOrder
- 0x1009d734 0x89 _zPHY_edls_AdaDecodeDciF1C
- 0x1009d7bd 0x71 _zPHY_edls_AdaCalSiRntiNdiRv
- 0x1009d82e 0x72 _zPHY_edls_AdaCalSibDecodeParas
- 0x1009d8a0 0x5e _zPHY_edls_AdaRbDmpType0Bw25Rb
- 0x1009d8fe 0x56 _zPHY_edls_AdaRbDmpType0Bw15Rb
- 0x1009d954 0x46 _zPHY_edls_AdaRbDmpType0Bw6Rb
- 0x1009d99a 0x26 _L1e_DevDlsGetMLSMTbs
- 0x1009d9c0 0x1f _L1e_DevDlsTbsBinarySearch
- 0x1009d9df 0x25 _L1e_DevDlsCalcRmCtrlParam
- 0x1009da04 0xe9 _zPHY_edls_AdaCalRarDecodeParas
- 0x1009daed 0xb _L1e_DevDlsCalcRmBbClk
- .text 0x1009daf8 0xf0b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
- 0x1009daf8 0x7 _L1e_DevRxGetPrevRxStatus
- 0x1009daff 0x7 _L1e_DevRxGetCurrRxStatus
- 0x1009db06 0xc _L1e_DevRxSwitchPrevStatus
- 0x1009db12 0x9 _L1e_DevRxSetCurrRxStatus
- 0x1009db1b 0xa6 _zPHY_edla_PageSubFrmJudge
- 0x1009dbc1 0x17 _zPHY_edla_RxVshiftConfig
- 0x1009dbd8 0xde _L1e_DevRxSfTypeCfg
- 0x1009dcb6 0x18 _L1e_DevRxRsN0FactorCtrl
- 0x1009dcce 0x17c _L1e_DevRxCRsN0ModeCtrl
- 0x1009de4a 0x7e _L1e_DevRxProcRsCinit
- 0x1009dec8 0x5d _zPHY_edla_RxBandTxRxPortConfig
- 0x1009df25 0x113 _zPHY_edla_RxPhichMatrixConfig
- 0x1009e038 0xf _zPHY_edla_RxCtrlChannelMimoModeConfig
- 0x1009e047 0x6 _zPHY_edla_RxCalIndicatorConfig
- 0x1009e04d 0x44 _zPHY_edla_RxCarrierInfoConfig
- 0x1009e091 0x85 _zPHY_edla_CheProc
- 0x1009e116 0xb _zPHY_edla_RxRbDemappingProc
- 0x1009e121 0x25c _zPHY_edla_RbDemappingSubProc
- 0x1009e37d 0x20 _zPHY_edla_WriteRxRbDemapRegFile
- 0x1009e39d 0x2b _L1e_DevRxNormalN0ModCfg
- 0x1009e3c8 0x25 _L1e_DevRxNCellRsNullCfg
- 0x1009e3ed 0x9 _L1e_DevRxSetCirTiCtlFlg
- 0x1009e3f6 0x9 _L1e_DevRxGetCirTiCtlFlg
- 0x1009e3ff 0x70 _L1e_DevRxSinrLowInd
- 0x1009e46f 0x53 _L1e_DevNSIOT_8242_Ind
- 0x1009e4c2 0x41 _L1e_DevRxSinrTiCloseInd
- 0x1009e503 0x7 _L1e_DevRxCrsIIRIndSet
- 0x1009e50a 0x7 _L1e_DevRxCrsIIRIndGet
- 0x1009e511 0x8f _L1e_DevRxCrsIIRCfg
- 0x1009e5a0 0x5d _L1e_DevRxSnrModeTiAdptProc
- 0x1009e5fd 0x1c _L1e_DevRxSetTiAlgoMode
- 0x1009e619 0x9 _L1e_DevRxGetNCellRsNullEnInd
- 0x1009e622 0x9 _L1e_DevRxSetNCellRsNullEnInd
- 0x1009e62b 0x59 _L1e_DevRxTempPro
- 0x1009e684 0x25b _zPHY_edla_RxRegCfgApply
- 0x1009e8df 0x30 _L1e_DrvRxAgcCalandConfig
- 0x1009e90f 0xf4 _L1e_DbgRxCtrlInfo
- .text 0x1009ea03 0x25e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pucch.o)
- 0x1009ea05 0x217 _zPHY_eulpc_PucchPowCtrl
- 0x1009ec1c 0x45 _zPHY_eulpc_HNcqiNharqNsrCalc
- .text 0x1009ec61 0x287 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_ddtr.o)
- 0x1009ec61 0x8 _L1e_DrvDdtrResetCfg
- 0x1009ec69 0x8 _L1e_DrvDdtrResetGet
- 0x1009ec71 0x7 _L1e_DrvDtrScaleResetCfg
- 0x1009ec78 0x8 _L1e_DrvDtrScaleEnCfg
- 0x1009ec80 0xb _L1e_DrvDtrScaleDtchEnCfg
- 0x1009ec8b 0x19 _L1e_DrvDtrScaleReset
- 0x1009eca4 0x8 _L1e_DrvDdtrModeCfg
- 0x1009ecac 0x8 _L1e_DrvDdtrTurboLpCtrlRegCfg
- 0x1009ecb4 0x8 _L1e_DrvDdtrSubfNumCfg
- 0x1009ecbc 0x8 _L1e_DrvDdtrHarqCtrlCfg
- 0x1009ecc4 0x8 _L1e_DrvDdtrHarqIramCtrlCfg
- 0x1009eccc 0xb _L1e_DrvDdtrHarqPriorityCfg
- 0x1009ecd7 0x8 _L1e_DrvDdtrHarqBurstCtrlCfg
- 0x1009ecdf 0x8 _L1e_DrvDdtrIntTimerCfg
- 0x1009ece7 0x8 _L1e_DrvDdtrLpCtrlCfg
- 0x1009ecef 0x8 _L1e_DrvDdtrUpdateCfg
- 0x1009ecf7 0xd _L1e_DrvDdtrTbCrcRead
- 0x1009ed04 0x9 _L1e_DrvDdtrSibPchCrcRead
- 0x1009ed0d 0x9 _L1e_DrvDdtrSubfNumRead
- 0x1009ed16 0x9 _L1e_DrvDdtrIdleStateRead
- 0x1009ed1f 0x9 _L1e_DrvDdtrErrorIndRead
- 0x1009ed28 0x1 _L1e_DrvDdtrTurboLpCtrlCfg
- 0x1009ed29 0xb _L1e_DrvDdtrPdschEnCfg
- 0x1009ed34 0xb _L1e_DrvDdtrPdschEnRead
- 0x1009ed3f 0xb _L1e_DrvDdtrSwapFlagCfg
- 0x1009ed4a 0xb _L1e_DrvDdtrSwapFlagGet
- 0x1009ed55 0xe _L1e_DrvDdtrCwCinitCfg
- 0x1009ed63 0xb _L1e_DrvDdtrTurboCtrlCfg
- 0x1009ed6e 0xb _L1e_DrvDdtrPchBchTurboCtrlCfg
- 0x1009ed79 0x5d _L1e_DrvDdtrTbParamCfg
- 0x1009edd6 0x8 _L1e_DrvDdtrPchCinitCfg
- 0x1009edde 0x11 _L1e_DrvDdtrPchParamCfg
- 0x1009edef 0x8 _L1e_DrvDdtrSibCinitCfg
- 0x1009edf7 0x11 _L1e_DrvDdtrSibParamCfg
- 0x1009ee08 0x1d _L1e_DrvDdtrTurboReset
- 0x1009ee25 0x9 _L1e_DrvDdtrGetAxiInfo
- 0x1009ee2e 0x39 _L1e_DrvDdtrPatchCfg
- 0x1009ee67 0x8 _L1e_DrvDdtrDbgGetDdtrMode
- 0x1009ee6f 0x8 _L1e_DrvDdtrDbgGetTopErrInd
- 0x1009ee77 0x8 _L1e_DrvDdtrDbgGetAxiInfo
- 0x1009ee7f 0x8 _L1e_DrvDdtrDbgGetIdleState
- 0x1009ee87 0x8 _L1e_DrvDdtrDbgGetSubfNum
- 0x1009ee8f 0xb _L1e_DrvDdtrDbgGetTurboCtrl
- 0x1009ee9a 0xb _L1e_DrvDdtrDbgGetTbCbCrc
- 0x1009eea5 0xa _L1e_DrvDdtrGetDbgMontor1
- 0x1009eeaf 0xa _L1e_DrvDdtrGetDbgMontor2
- 0x1009eeb9 0xf _L1e_DrvDdtrDbgSelCfg
- 0x1009eec8 0x8 _L1e_DrvDdtrDbgSelCfgread
- 0x1009eed0 0x8 _L1e_DrvDdtrDbgSelCfgread0
- 0x1009eed8 0x8 _L1e_DrvDdtrDbgSelCfgread1
- 0x1009eee0 0x8 _L1e_DrvDdtrDbgSelCfgread2
- .text 0x1009eee8 0x454 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
- 0x1009eee8 0x1c _zPHY_DrvTopIntAbleBitSet
- 0x1009ef04 0x1f _zPHY_DrvTopIntMaskBitSet
- 0x1009ef23 0xc _zPHY_DrvTopIntMaskRegWR
- 0x1009ef2f 0xc _zPHY_DrvTopIntMaskRegRD
- 0x1009ef3b 0xc _zPHY_DrvGetTopIntStaus
- 0x1009ef47 0xc _zPHY_DrvGetTopIntVec
- 0x1009ef53 0xc _zPHY_DrvTopIntClear
- 0x1009ef5f 0x1f _zPHY_DrvTopIntEnable
- 0x1009ef7e 0x5a _zPHY_eintc_IntRegPrint
- 0x1009efd8 0x2c _zPHY_DrvTopIntReg_Print
- 0x1009f004 0x1 _zPHY_DrvModemTopClkGate
- 0x1009f005 0x1 _zPHY_DrvModemTopClkSel
- 0x1009f006 0x11 _zPHY_LteModemTopClkCfg
- 0x1009f017 0x1b _zPHY_ResetModemHw
- 0x1009f032 0x33 _zPHY_LteaModemTopCfgBackup
- 0x1009f065 0x4a _zPHY_LteaModemTopCfgRecover
- 0x1009f0af 0x9 _zPHY_DrvTop_Reg_Set
- 0x1009f0b8 0x9 _zPHY_DrvTop_IntReg_Set
- 0x1009f0c1 0x9 _zPHY_DrvTop_IntReg_Get
- 0x1009f0ca 0x28 _L1l_DrvMcuIntMask
- 0x1009f0f2 0x28 _L1l_DrvMcuIntUnmask
- 0x1009f11a 0xa _L1l_DrvMcuIntIreqClr
- 0x1009f124 0x3a _L1l_DrvTopIntMask
- 0x1009f15e 0x39 _L1l_DrvTopIntRestore
- 0x1009f197 0x48 _L1l_DrvTopIntEng
- 0x1009f1df 0x1 _zPHY_DrvTOP_DFE_ClkPrintf
- 0x1009f1e0 0x1 _zPHY_DrvTOP_CSR_ClkPrintf
- 0x1009f1e1 0x7 _zPHY_DrvTOP_GetHarkRamSel
- 0x1009f1e8 0x7 _zPHY_DrvTOP_GetTDHarkRamSel
- 0x1009f1ef 0x1 _zPHY_DrvTOP_Ddtr_ClkAndLpramPrintf
- 0x1009f1f0 0x37 _zPHY_DrvLteaPwrClkCtrl
- 0x1009f227 0x6 _zPHY_DrvPhyLteModemSel
- 0x1009f22d 0x7 _zPHY_DrvRmHarqRamLteModeClkSelCfg
- 0x1009f234 0x5 _zPHY_DrvTurboModeSel
- 0x1009f239 0x58 _zPHY_DrvLteTpuClkSet
- 0x1009f291 0xe _zPHY_DrvLteTpuClkInit
- 0x1009f29f 0x19 _zPHY_DrvChipTopRegInit
- 0x1009f2b8 0x8 _zPHY_DrvTopCLKRegPOWGAT
- 0x1009f2c0 0x9 _zPHY_DrvTopCLKReg2m1SCfg
- 0x1009f2c9 0x9 _zPHY_DrvTopCLKRegRfcCfg
- 0x1009f2d2 0xb _zPHY_DrvTop_RFInitReg_Set
- 0x1009f2dd 0x5f _zPHY_DMA_Cfg
- .text 0x1009f33c 0x2b6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
- 0x1009f33c 0x58 _L1L_TpuDrvReset
- 0x1009f394 0x33 _L1L_TpuDrvSuspend
- 0x1009f3c7 0x3f _L1L_TpuDrvResume
- 0x1009f406 0x7 _L1L_TpuDrvCpModeGet
- 0x1009f40d 0x46 _L1L_TpuDrvCpModeSet
- 0x1009f453 0x1c _L1L_TpuDrvLocalMrtrGet
- 0x1009f46f 0x1c _L1L_TpuDrvMrtrGet
- 0x1009f48b 0xe _L1L_TpuDrvMrtrOffsetGet
- 0x1009f499 0x47 _L1L_TpuDrvTpuRegister
- 0x1009f4e0 0x1b _L1L_TpuDrvMicroAdj
- 0x1009f4fb 0x6 _L1L_TpuDrvMacroAdj
- 0x1009f501 0x20 _L1L_TpuDrvHwBackup
- 0x1009f521 0xb _L1L_TPUDrvCPModeGet
- 0x1009f52c 0xb _L1L_TPUDrvCPModeSet
- 0x1009f537 0xa _L1L_TPUDrvMrtrOffGet
- 0x1009f541 0x8 _L1L_TPUDrvMrtrOffSet
- 0x1009f549 0x8 _L1L_TPUDrvAdjTimeSet
- 0x1009f551 0xc _L1L_TPUDrvCPMrtrOffStore
- 0x1009f55d 0xa _L1L_TPUDrvMRTRTransfer
- 0x1009f567 0x8 _L1L_TPUDrvLocalMrtrGet
- 0x1009f56f 0x8 _L1L_TPUDrvMrtrGet
- 0x1009f577 0xb _L1L_TPUDrvHWResetCfg
- 0x1009f582 0xf _L1L_TpuDrvRAMCtrl
- 0x1009f591 0x8 _L1L_TPUDrvInttoArmIndexGet
- 0x1009f599 0x9 _L1L_TpuDrvIntECTRamSel
- 0x1009f5a2 0x50 _L1L_TPUDrvIntECTInit
- .text 0x1009f5f2 0x242 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
- 0x1009f5f2 0xea _zPHY_emc_DlDataReport
- 0x1009f6dc 0x27 _zPHY_emc_RdUlDataSendCtrlInfo
- 0x1009f703 0x20 _zPHY_emc_wrUlReportBlerInfo
- 0x1009f723 0x53 _zPHY_emc_WrUlSchedInfo
- 0x1009f776 0x25 _zPHY_emc_InitRpMsgCh
- 0x1009f79b 0x8 _zPHY_emc_MaskRpMsgCh
- 0x1009f7a3 0x8 _zPHY_emc_UnMaskRpMsgCh
- 0x1009f7ab 0x9 _L1e_DrvGetIramTempCtrlBit
- 0x1009f7b4 0x12 _L1e_DrvGetLteTempCtrlLimitInd
- 0x1009f7c6 0xa _L1e_DrvGetDlSibPduCrcBaseAddr
- 0x1009f7d0 0xb _L1e_DrvGetDlSibPduDataBaseAddr
- 0x1009f7db 0xa _L1e_DrvGetDlPchPduCrcBaseAddr
- 0x1009f7e5 0xb _L1e_DrvGetDlPchPduDataBaseAddr
- 0x1009f7f0 0xa _L1e_DrvGetDlRarPduCrcBaseAddr
- 0x1009f7fa 0xb _L1e_DrvGetDlRarPduDataBaseAddr
- 0x1009f805 0x17 _L1e_DrvGetDlMacPduHarqBaseAddr
- 0x1009f81c 0xb _L1e_DrvGetDlMacPduCrcBaseAddr
- 0x1009f827 0xd _L1e_DrvSetIslandAddr
- .text 0x1009f834 0x57c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
- 0x1009f834 0x7 _zPHY_elpc_DrvDelay
- 0x1009f83b 0x85 _L1l_DrvLpcGetSleepLen
- 0x1009f8c0 0x32 _L1l_DrvLpcGetRemainCaliTime
- 0x1009f8f2 0x8c _zPHY_elpc_LpmTimerCtrl
- 0x1009f97e 0x26 _L1_LTE_GetLpmTimerIsEn
- 0x1009f9a4 0x4 _L1L_DrvLpcSocWakeUpIntCtrl
- 0x1009f9a8 0x1d _L1L_DrvLpcModemWakeUpIntCtrl
- 0x1009f9c5 0x1b _L1L_DrvLpcCfgSocWkupInt
- 0x1009f9e0 0x23 _L1L_DrvLpcCfgModemWkupInt
- 0x1009fa03 0x16 _L1l_DrvLpcGetLpmNT
- 0x1009fa19 0x4b _L1l_DrvLpcWaitLpmMrtrChange
- 0x1009fa64 0x19 _zPHY_elpc_DrvLpmCaliCfg
- 0x1009fa7d 0x10 _zPHY_elpc_DrvPdLteaCsrBackup
- 0x1009fa8d 0x6 _zPHY_elpc_DrvPdLteaTxBackup
- 0x1009fa93 0x1e _zPHY_elpc_DrvPdLteaCsrRecover
- 0x1009fab1 0x6 _zPHY_elpc_DrvPdLteaTxRecover
- 0x1009fab7 0x11 _zPHY_elpc_DrvPdLteaRfcDfeBackup
- 0x1009fac8 0x16 _zPHY_elpc_DrvPdLteaRfcDfeRecover
- 0x1009fade 0x5 _zPHY_elpc_DrvPdLteaRxRecover
- 0x1009fae3 0xf _zPHY_elpc_DrvPdLteaMimoCdtrRecover
- 0x1009faf2 0x5 _zPHY_elpc_DrvPdLteaDdtrHarqRecover
- 0x1009faf7 0x19 _zPHY_elpc_DrvPdLteaStdbyCtrl
- 0x1009fb10 0x47 _zPHY_elpc_DrvPdHwIsBusy
- 0x1009fb57 0x1a _zPHY_elpc_DrvLteaPwrScenarioCtrlLog
- 0x1009fb71 0x37 _zPHY_elpc_DrvLteaPwrHwBackup
- 0x1009fba8 0x12e _zPHY_elpc_DrvLteaPwrScenarioCtrl
- 0x1009fcd6 0xc1 _zPHY_elpc_DrvLteaPwrCtrl
- 0x1009fd97 0x19 _zPHY_eLpc_DrvClearLteaModemInt
- .text 0x1009fdb0 0x802 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
- 0x1009fdb0 0x24 _zPHY_eltx_SoftReset
- 0x1009fdd4 0x10 _zPHY_eltx_GetHWVersion
- 0x1009fde4 0x10 _zPHY_eltx_GetStatus
- 0x1009fdf4 0x42 _zPHY_eltx_Clk_En
- 0x1009fe36 0xa _zPHY_eltx_SetCPType
- 0x1009fe40 0x12 _zPHY_eltx_SetChannelType
- 0x1009fe52 0x27 _zPHY_eltx_SetSysBandwidth
- 0x1009fe79 0xc _zPHY_eltx_SetTxTa
- 0x1009fe85 0x9 _zPHY_eltx_SetPortSel
- 0x1009fe8e 0x14 _zPHY_eltx_SetFirstSfFlag
- 0x1009fea2 0xf _zPHY_eltx_SetConsecutiveSFLast
- 0x1009feb1 0x1e _zPHY_eltx_SetFirstLastMode
- 0x1009fecf 0xa _zPHY_eltx_SetSendMode
- 0x1009fed9 0xe _zPHY_eltx_SetAbbSampleRate
- 0x1009fee7 0x14 _zPHY_eltx_SetInterMatrixInfo
- 0x1009fefb 0xc _zPHY_eltx_SetPuschScreamblePara
- 0x1009ff07 0xe _zPHY_eltx_SetPuschModulationMode
- 0x1009ff15 0xc _zPHY_eltx_SetPuschDFTPointNumber
- 0x1009ff21 0x9 _zPHY_eltx_SetPrecodingCodeBook
- 0x1009ff2a 0x19 _zPHY_eltx_SetAckRiInfo
- 0x1009ff43 0x4c _zPHY_eltx_SetRiMultiplexingInfo
- 0x1009ff8f 0x77 _zPHY_eltx_SetAckMultiplexingInfo
- 0x100a0006 0xc _zPHY_eltx_SetPucchScreambleCint
- 0x100a0012 0x24 _zPHY_eltx_SetPucchHarqAckinfo
- 0x100a0036 0x1c _zPHY_eltx_SetPucchCqiInfo
- 0x100a0052 0xe _zPHY_eltx_SetPucchFmt
- 0x100a0060 0x20 _zPHY_eltx_SetPucchCommonReg
- 0x100a0080 0x20 _zPHY_eltx_SetPucchZCParas
- 0x100a00a0 0x7f _zPHY_eltx_SetPucchNcsParas
- 0x100a011f 0x72 _zPHY_eltx_SetPuschDmrsParas
- 0x100a0191 0x68 _zPHY_eltx_SetSrsParas
- 0x100a01f9 0x3c _zPHY_eltx_SetPrachParas
- 0x100a0235 0x3e _zPHY_eltx_SetScale
- 0x100a0273 0x2b _zPHY_eltx_SetPuschReMappingParas
- 0x100a029e 0x1c _zPHY_eltx_SetPucchReMappingParas
- 0x100a02ba 0x4b _zPHY_eltx_TxCalibrationPreIQOrDC
- 0x100a0305 0x4b _zPHY_eltx_SetTxCalibrationParas
- 0x100a0350 0x19 _zPHY_eltx_SetFilter1Coeff
- 0x100a0369 0x19 _zPHY_eltx_SetFilter2Coeff
- 0x100a0382 0x19 _zPHY_eltx_SetFilter3Coeff
- 0x100a039b 0xc _zPHY_eltx_SetByPass
- 0x100a03a7 0x9 _zPHY_eltx_SetFiFO
- 0x100a03b0 0xb _zPHY_eltx_SetAntPhaseClkDelay
- 0x100a03bb 0xc _zPHY_eltx_SetAntFrameDlyNum
- 0x100a03c7 0x2 _zPHY_eltx_SetPucchFormat3Paras
- 0x100a03c9 0xe _zPHY_eltx_Enable
- 0x100a03d7 0x9 _zPHY_eltx_SetDebugMode
- 0x100a03e0 0x9 _zPHY_eltx_SetDebugBusSel
- 0x100a03e9 0x9 _zPHY_eula_SetTXIntPulse
- 0x100a03f2 0xa _zPHY_eltx_SetLTXIntSymbol
- 0x100a03fc 0x30 _zPHY_eltx_SetPRS1Paras
- 0x100a042c 0x31 _zPHY_eltx_GetPRS1Result
- 0x100a045d 0x30 _zPHY_eltx_SetPRS2Paras
- 0x100a048d 0x2f _zPHY_eltx_GetPRS2Result
- 0x100a04bc 0x62 _zPHY_eula_TxRFCDBB_Interface
- 0x100a051e 0x9 _zPHY_eula_SetTxDmaConfig
- 0x100a0527 0xb _zPHY_eula_SetLtxFreqCompBypass
- 0x100a0532 0xb _zPHY_eula_SetLtxFreqCompTheta
- 0x100a053d 0xb _zPHY_eula_SetLtxFreqCompTheta0
- 0x100a0548 0x48 _zPHY_eula_TxFreqCompValGet
- 0x100a0590 0x11 _zPHY_eula_TxCordicInit
- 0x100a05a1 0x11 _zPHY_eula_TxCordicCfg
- .text 0x100a05b2 0x165 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
- 0x100a05b2 0x19 _zPHY_ecsrm_MeasHwReset
- 0x100a05cb 0x77 _zPHY_ecsrm_MeasHwConfig
- 0x100a0642 0x79 _zPHY_ecsrm_MeasResultRead
- 0x100a06bb 0x45 _zPHY_ecsrm_GetMeasDoneFlag
- 0x100a0700 0xb _zPHY_ecsrm_GetRspCnt
- 0x100a070b 0xc _zPHY_ecsrm_ClearMeasDoneFlag
- .text 0x100a0717 0x8de T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
- 0x100a0717 0x1b _L1e_DrvRxResetHW
- 0x100a0732 0xd1 _L1e_DrvRxCcRegInit
- 0x100a0803 0x92 _L1e_DrvRxPccRegInit
- 0x100a0895 0x30 _L1e_DrvRxWriteRamCosWinCoeff
- 0x100a08c5 0x10 _L1e_DrvRxTransformFirCoeff
- 0x100a08d5 0x1c _L1e_DrvRxInitMrsFirCoeff
- 0x100a08f1 0x61 _L1e_DrvRxWriteRamFICoeff
- 0x100a0952 0x14 _zPHY_Drv_Rx_HwInit
- 0x100a0966 0x18 _L1e_DrvRxWritePcfichPosRegFile
- 0x100a097e 0x19 _zPHY_Drv_Rx_WritePhichPosRegFile
- 0x100a0997 0x1 _zPHY_Drv_Rx_ClkPrintf
- 0x100a0998 0x8 _L1e_DrvRxGateCtrlRead
- 0x100a09a0 0x8 _L1e_DrvRxClkSwitch0Cfg
- 0x100a09a8 0x8 _L1e_DrvRxClkSwitch0Read
- 0x100a09b0 0x8 _L1e_DrvRxPort5PatchCfg
- 0x100a09b8 0x8 _L1e_DrvRxPccCsiCheTimeRead
- 0x100a09c0 0x8 _L1e_DrvRxPbchCtrlCfg
- 0x100a09c8 0x8 _L1e_DrvRxPbchCtrlRead
- 0x100a09d0 0x8 _L1e_DrvRxCarrierInfoCfg
- 0x100a09d8 0x8 _L1e_DrvRxCarrierInfoRead
- 0x100a09e0 0xb _L1e_DrvRxRxModeCfg
- 0x100a09eb 0xb _L1e_DrvRxRxModeRead
- 0x100a09f6 0xb _L1e_DrvRxRatModeCfg
- 0x100a0a01 0xb _L1e_DrvRxCpModeCfg
- 0x100a0a0c 0xb _L1e_DrvRxCpModeRead
- 0x100a0a17 0xb _L1e_DrvRxVshiftCfg
- 0x100a0a22 0xb _L1e_DrvRxVshiftRead
- 0x100a0a2d 0xe _L1e_DrvRxPcfichRegPosCfg
- 0x100a0a3b 0xe _L1e_DrvRxPhichRegPosCfg
- 0x100a0a49 0x18 _L1e_DrvRxCellInfoCfg
- 0x100a0a61 0xb _L1e_DrvRxCellInfoRead
- 0x100a0a6c 0xe _L1e_DrvRxSfnTypeCfg
- 0x100a0a7a 0xe _L1e_DrvRxSfnTypeRead
- 0x100a0a88 0x13 _L1e_DrvRxTmIndCfg
- 0x100a0a9b 0xb _L1e_DrvRxMbsfnCfiCfg
- 0x100a0aa6 0xb _L1e_DrvRxMbsfnTm9IndCfg
- 0x100a0ab1 0xb _L1e_DrvRxCirAccCtrlCfg
- 0x100a0abc 0xb _L1e_DrvRxCirAccCtrlRead
- 0x100a0ac7 0xb _L1e_DrvRxMrsCirAccCtrlCfg
- 0x100a0ad2 0xb _L1e_DrvRxMrsCirAccCtrlRead
- 0x100a0add 0xb _L1e_DrvRxN0FgtFactorlCfg
- 0x100a0ae8 0x8 _L1e_DrvRxN0FgtFactorRead
- 0x100a0af0 0xb _L1e_DrvRxN0ModeCfg
- 0x100a0afb 0xb _L1e_DrvRxN0ModeRead
- 0x100a0b06 0xb _L1e_DrvRxSwN0ValCfg
- 0x100a0b11 0xb _L1e_DrvRxSwN0ValRead
- 0x100a0b1c 0xb _L1e_DrvRxMbsfnN0FgtCfg
- 0x100a0b27 0xb _L1e_DrvRxMbsfnN0FgtRead
- 0x100a0b32 0xb _L1e_DrvRxEicicModeCfg
- 0x100a0b3d 0xb _L1e_DrvRxEicicModeRead
- 0x100a0b48 0xb _L1e_DrvRxBniCtrlCfg
- 0x100a0b53 0x1 _L1e_DrvRxNbnbCtrlCfg
- 0x100a0b54 0x2 _L1e_DrvRxNbnbCtrlRead
- 0x100a0b56 0xb _L1e_DrvRxCchModuModeCfg
- 0x100a0b61 0xb _L1e_DrvRxCchModuModeRead
- 0x100a0b6c 0xb _L1e_DrvRxCchPcVolCfg
- 0x100a0b77 0xb _L1e_DrvRxCchPcPowCfg
- 0x100a0b82 0xb _L1e_DrvRxCsiRsCfg
- 0x100a0b8d 0xb _L1e_DrvRxHijRptModeCfg
- 0x100a0b98 0xb _L1e_DrvRxTiCrsRptModeCfg
- 0x100a0ba3 0xb _L1e_DrvRxTiCrsRptModeRead
- 0x100a0bae 0xb _L1e_DrvRxPhichMatrixCfg
- 0x100a0bb9 0xb _L1e_DrvRxCchWorkModeCfg
- 0x100a0bc4 0xb _L1e_DrvRxTiModeCfg
- 0x100a0bcf 0xb _L1e_DrvRxTiModeRead
- 0x100a0bda 0x10 _L1e_DrvRxAgcBalanceCfg
- 0x100a0bea 0xe _L1e_DrvRxAgcBalanceRead
- 0x100a0bf8 0xb _L1e_DrvRxZpCsiBmpCfg
- 0x100a0c03 0xe _L1e_DrvRxZpCsiPosCfg
- 0x100a0c11 0xe _L1e_DrvRxCrsCinitCfg
- 0x100a0c1f 0xe _L1e_DrvRxCrsCinitRead
- 0x100a0c2d 0xe _L1e_DrvRxCsiRsCinitCfg
- 0x100a0c3b 0xb _L1e_DrvRxRsParamCfg
- 0x100a0c46 0xe _L1e_DrvRxIcCrsCinitCfg
- 0x100a0c54 0xb _L1e_DrvRxIcRsParamCfg
- 0x100a0c5f 0x26 _L1e_DrvRxN0BetaCfg
- 0x100a0c85 0x27 _L1e_DrvRxN0BetaRead
- 0x100a0cac 0xb _L1e_DrvRxSwFirUpdateCfg
- 0x100a0cb7 0x8 _L1e_DrvRxFixFirUpdateCfg
- 0x100a0cbf 0xb _L1e_DrvRxDrsGenStateCfg
- 0x100a0cca 0xb _L1e_DrvRxDrsCinitCfg
- 0x100a0cd5 0xb _L1e_DrvRxDrsParamCfg
- 0x100a0ce0 0xb _L1e_DrvRxRbBmpValidCfg
- 0x100a0ceb 0x13 _L1e_DrvRxRbBmpCfg
- 0x100a0cfe 0xb _L1e_DrvRxPrbBundlingBmpCfg
- 0x100a0d09 0xb _L1e_DrvRxCsiRsDelCtrlCfg
- 0x100a0d14 0xb _L1e_DrvRxCsiRsDelCtrlRead
- 0x100a0d1f 0xb _L1e_DrvRxPdschModuModeCfg
- 0x100a0d2a 0xb _L1e_DrvRxPdschModuModeRead
- 0x100a0d35 0xb _L1e_DrvRxPdschMimoModeCfg
- 0x100a0d40 0xb _L1e_DrvRxPdschMimoModeRead
- 0x100a0d4b 0xb _L1e_DrvRxPdschRbMaskCfg
- 0x100a0d56 0xb _L1e_DrvRxPdschTpmiCfg
- 0x100a0d61 0x10 _L1e_DrvRxDchPcVolCfg
- 0x100a0d71 0x10 _L1e_DrvRxDchPcPowCfg
- 0x100a0d81 0xb _L1e_DrvRxPcEnCfg
- 0x100a0d8c 0xb _L1e_DrvRxPort7IndCfg
- 0x100a0d97 0xb _L1e_DrvRxMimoAlgoCfg
- 0x100a0da2 0xb _L1e_DrvRxBfAlgoCfg
- 0x100a0dad 0xb _L1e_DrvRxPdschValidCfg
- 0x100a0db8 0x13 _L1e_DrvRxCrsRssiRead
- 0x100a0dcb 0x13 _L1e_DrvRxCrsRspRead
- 0x100a0dde 0x16 _L1e_DrvRxCrsRsrpRead
- 0x100a0df4 0xb _L1e_DrvRxCfoPhaseRead
- 0x100a0dff 0x13 _L1e_DrvRxMbsfnRssiRead
- 0x100a0e12 0x13 _L1e_DrvRxMbsfnRspRead
- 0x100a0e25 0x13 _L1e_DrvRxMbsfnRsrpRead
- 0x100a0e38 0x1c _L1e_DrvRxN0Read
- 0x100a0e54 0x1e _L1e_DrvRxCirPeakPosRead
- 0x100a0e72 0x22 _L1e_DrvRxDrsRsrpRead
- 0x100a0e94 0x24 _L1e_DrvRxDrsRspRead
- 0x100a0eb8 0xb _L1e_DrvRxDrsAccNumRead
- 0x100a0ec3 0xc _L1e_DrvRxGetGenStateInd
- 0x100a0ecf 0x6 _L1e_DrvRx_CqiHRx0
- 0x100a0ed5 0x6 _L1e_DrvRx_CqiNo0
- 0x100a0edb 0x6 _L1e_DrvRx_R
- 0x100a0ee1 0xd _L1e_DrvRxTpmiRamCfg
- 0x100a0eee 0xd _L1e_DrvRxFirFixRamCfg
- 0x100a0efb 0x6 _L1e_DrvRxFirFixRamRec
- 0x100a0f01 0x16 _L1e_DrvRxFirDynRamCfg
- 0x100a0f17 0x1 _L1e_DrvRxFftBitmapRamCfg
- 0x100a0f18 0x1 _L1e_DrvRxTiAptRamRead
- 0x100a0f19 0x28 _L1e_DrvRxCirRamDataRead
- 0x100a0f41 0xb4 _L1e_DrvRxDbgLogRxCheReg
- .text 0x100a0ff5 0x209 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
- 0x100a0ff5 0x1d _zPHY_elutr_SoftReset
- 0x100a1012 0x12 _zPHY_elutr_GetHWVersion
- 0x100a1024 0x1f _zPHY_elutr_HarqRam_Harness
- 0x100a1043 0x2b _zPHY_elutr_HarqRam_NoHarness
- 0x100a106e 0x3a _zPHY_elutr_Clk_En
- 0x100a10a8 0xe _zPHY_elutr_Enable
- 0x100a10b6 0x9 _zPHY_elutr_GetHWStatus
- 0x100a10bf 0x13 _zPHY_elutr_CommonReg
- 0x100a10d2 0xc _zPHY_elutr_Modulation
- 0x100a10de 0xc _zPHY_elutr_SetTBLength
- 0x100a10ea 0x24 _zPHY_elutr_SetTBSegParas
- 0x100a110e 0x1a _zPHY_elutr_SetTurboParas
- 0x100a1128 0x25 _zPHY_elutr_SetRateMatchParas
- 0x100a114d 0xc _zPHY_elutr_SetInterMatrixColNumber
- 0x100a1159 0x24 _zPHY_elutr_SetPuschAckParas
- 0x100a117d 0xe _zPHY_elutr_SetPuschAckUpdate
- 0x100a118b 0x15 _zPHY_elutr_SetPuschRiParas
- 0x100a11a0 0xe _zPHY_elutr_SetPuschRiUpdate
- 0x100a11ae 0x25 _zPHY_elutr_SetPuschCqiParas
- 0x100a11d3 0xc _zPHY_elutr_SetPuschSubCarrierNumber
- 0x100a11df 0x1f _zPHY_elutr_SetRiMultiplexingInfo
- .text 0x100a11fe 0x22a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
- 0x100a11fe 0x1b _L1e_DrvRxMimoReset
- 0x100a1219 0x19 _L1e_DrvPbchCdtrViterbiReset
- 0x100a1232 0x1b _L1e_DrvPbchHWReset
- 0x100a124d 0x2 _L1e_DrvPbchInit
- 0x100a124f 0x6a _L1e_DrvPbchConfigPbchReg
- 0x100a12b9 0xde _L1e_DrvPbchConfigRxReg
- 0x100a1397 0x22 _L1e_DrvPbchGenRxSubFrmHead
- 0x100a13b9 0x23 _L1e_DrvPbchScGeneration
- 0x100a13dc 0x8 _L1e_DrvPbchCdtrViterbiClkRead
- 0x100a13e4 0x8 _L1e_DrvPbchResultRead
- 0x100a13ec 0x8 _L1e_DrvPbchAntSfnRead
- 0x100a13f4 0x8 _L1e_DrvPbchStateRead
- 0x100a13fc 0x9 _L1e_DrvPbchCdtrViterbiCtrl
- 0x100a1405 0x9 _L1e_DrvPbchCdtrVtbRamLpCtrl
- 0x100a140e 0x8 _L1e_DrvPbchLpcCfg
- 0x100a1416 0x9 _L1e_DrvCdtrlkEn
- 0x100a141f 0x9 _L1e_DrvPbchClkEn
- .text 0x100a1428 0x36f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
- 0x100a1428 0x7 _L1e_DrvMimoCaRstCfg
- 0x100a142f 0xb _L1e_DrvMimoIrcModeCfg
- 0x100a143a 0xb _L1e_DrvMimoIrcModeRead
- 0x100a1445 0x8 _L1e_DrvMimoUpdateCfg
- 0x100a144d 0x8 _L1e_DrvMimoUpdateRead
- 0x100a1455 0x8 _L1e_DrvCdtrResetCfg
- 0x100a145d 0x1b _L1e_DrvCdtrHwReset
- 0x100a1478 0x19 _L1e_DrvMimoReset
- 0x100a1491 0x43 _L1e_DrvCdtrHwInit
- 0x100a14d4 0x8 _L1e_DrvCdtrTopClkSelCfg
- 0x100a14dc 0x26 _L1e_DrvCdtrTopRegCfg
- 0x100a1502 0x9 _L1e_DrvCdtrLpcCtrl
- 0x100a150b 0x1b _L1e_DrvCdtrPcfichRegCfg
- 0x100a1526 0x3b _L1e_DrvCdtrPhichRegCfg
- 0x100a1561 0x93 _L1e_DrvCdtrPdcchBldRegCfg
- 0x100a15f4 0x54 _L1e_DrvCdtrPdcchDmpRegCfg
- 0x100a1648 0xb _L1e_DrvCdtrPhichNumCfg
- 0x100a1653 0xb _L1e_DrvCdtrCchEnableCfg
- 0x100a165e 0xc _L1e_DrvCdtrRntiEnRead
- 0x100a166a 0xc _L1e_DrvCdtrCfiValueRead
- 0x100a1676 0xc _L1e_DrvCdtrHiNumRead
- 0x100a1682 0xf _L1e_DrvCdtrHiValueRead
- 0x100a1691 0xc _L1e_DrvCdtrDciPld1Read
- 0x100a169d 0xc _L1e_DrvCdtrDciPld2Read
- 0x100a16a9 0x1d _L1e_DrvCdtrDciRead
- 0x100a16c6 0x17 _L1e_DrvCdtrDciInfoRead
- 0x100a16dd 0xc _L1e_DrvCdtrDciValidRead
- 0x100a16e9 0xc _L1e_DrvCdtrUePortRead
- 0x100a16f5 0x8 _L1e_DrvCdtrDbgGetIntType
- 0x100a16fd 0xb _L1e_DrvCdtrDbgGetDlDciInfo
- 0x100a1708 0x11 _L1e_DrvCdtrDbgGetDlDciFlag
- 0x100a1719 0x11 _L1e_DrvCdtrDbgGetSiDciFlag
- 0x100a172a 0x11 _L1e_DrvCdtrDbgGetPmDciFlag
- 0x100a173b 0x11 _L1e_DrvCdtrDbgGetRaDciFlag
- 0x100a174c 0x4b _L1e_DrvCdtrPdcchBmpRamCfg
- .text 0x100a1797 0x7f8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
- 0x100a1797 0x38 _zPHY_erfc_DrvGetSubFrameAddr
- 0x100a17cf 0xd1 _zPHY_erfc_DrvRealwokEventEn
- 0x100a18a0 0x62 _zPHY_erfc_DrvInitAllEventEnArray
- 0x100a1902 0x186 _zPHY_erfc_DrvWriteAllEventEnArrayToHwReg
- 0x100a1a88 0x1 _zPHY_erfc_DrvWriteAllEventEnArrayToHwReg_Slave
- 0x100a1a89 0x87 _zPHY_erfc_DrvAFCEventEn
- 0x100a1b10 0x10 _zPHY_erfc_DrvSpiWrite
- 0x100a1b20 0x59 _zPHY_erfc_DrvSetAgcSpiReg
- 0x100a1b79 0xa _zPHY_erfc_DrvRbdp_RxIQInvert
- 0x100a1b83 0xa _zPHY_erfc_DrvRbdp_TxIQInvert
- 0x100a1b8d 0x1 _zPHY_erfc_DrvRbdpModeCfg
- 0x100a1b8e 0x1 _zPHY_erfc_DrvTopRBDPGPIOConfig
- 0x100a1b8f 0x1 _zPHY_erfc_DrvTopSSCConfig
- 0x100a1b90 0xa _zPHY_erfc_DrvMasterModeTopGPIOConfig
- 0x100a1b9a 0x1 _zPHY_erfc_DrvEventRamLeaveLP
- 0x100a1b9b 0x50 _zPHY_erfc_DrvRfcRegInit
- 0x100a1beb 0x1 _zPHY_erfc_DrvRfcRegInit_Slave
- 0x100a1bec 0x91 _zPHY_erfc_DrvRFEventRamInit
- 0x100a1c7d 0x1b _zPHY_erfc_DrvSoftwareReset
- 0x100a1c98 0x18 _zPHY_erfc_DrvResetHw
- 0x100a1cb0 0xe _zPHY_erfc_DrvWriteCmdEvent
- 0x100a1cbe 0xe _zPHY_erfc_DrvDBBEventSet
- 0x100a1ccc 0x6 _zPHY_erfc_GetDfeSampleRateAddr
- 0x100a1cd2 0x2c _zPHY_erfc_GetRfcShadowEventTableAddr
- 0x100a1cfe 0x33 _zPHY_erfc_GetRfcEventTableAddr
- 0x100a1d31 0x33 _zPHY_erfc_GetRfcBackupDDREventTableAddr
- 0x100a1d64 0x30 _zPHY_erfc_DrvGetRamState
- 0x100a1d94 0x85 _zPHY_erfc_DrvEvtTabStart
- 0x100a1e19 0x12 _zPHY_erfc_DrvGPIOEventSet
- 0x100a1e2b 0xb _zPHY_erfc_DrvOpenfilter0
- 0x100a1e36 0xb _zPHY_erfc_DrvClosefilter0
- 0x100a1e41 0xb _zPHY_erfc_DrvOpenfilter1
- 0x100a1e4c 0xb _zPHY_erfc_DrvClosefilter1
- 0x100a1e57 0xe _zPHY_erfc_DrvOpenfilter2
- 0x100a1e65 0xb _zPHY_erfc_DrvClosefilter2
- 0x100a1e70 0x10 _zPHY_erfc_DrvDfeRXBandWidthEn
- 0x100a1e80 0x10 _zPHY_erfc_DrvDfeMeas0BandWidthEn
- 0x100a1e90 0xb _zPHY_erfc_DrvGetfilter2State
- 0x100a1e9b 0x7 _zPHY_erfc_DrvGetfilterState
- 0x100a1ea2 0x7 _zPHY_erfc_DrvGetSpiReadData
- 0x100a1ea9 0x7 _zPHY_erfc_DrvGetMipiReadData
- 0x100a1eb0 0x9 _zPHY_erfc_DrvSetRxRemovCpOffset
- 0x100a1eb9 0x54 _zPHY_erfc_DrvEvtSetTableOffset
- 0x100a1f0d 0x9 _zPHY_erfc_DrvEnTxCalibration
- 0x100a1f16 0x1 _zPHY_erfc_DrvSlaveModeTopGPIOConfig
- 0x100a1f17 0xb _zPHY_erfc_DrvRfcRXBandWidthEn
- 0x100a1f22 0xb _zPHY_erfc_DrvRfcMeas0BandWidthEn
- 0x100a1f2d 0x1a _zPHY_erfc_DrvInitTuRamTxEnReg
- 0x100a1f47 0x25 _zPHY_erfc_DrvInitTuRamTxTable
- 0x100a1f6c 0x23 _zPHY_erfc_DrvInitTuRegTxTable
- .text 0x100a1f8f 0x1ad1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
- 0x100a1f8f 0xcb _sin_wave_test_dfe
- 0x100a205a 0x5a _zPHY_erfc_DrvRfcRffeWrite
- 0x100a20b4 0x7a _zPHY_erfc_MIPI_Config
- 0x100a212e 0x1 _zPHY_erfc_DrvRfcRffeSwitchInit
- 0x100a212f 0x9f _zPHY_erfc_DrvDFESetAcp405Gain
- 0x100a21ce 0x25 _zPHY_erfc_DrvSpiCtrlWordPreDef
- 0x100a21f3 0x4b _zPHY_erfc_DrvPaAndAntOpenForRX
- 0x100a223e 0x7b _zPHY_erfc_DrvPaAndAntOpenForTX
- 0x100a22b9 0x8e _zPHY_erfc_Idle2TDRX
- 0x100a2347 0x82 _zPHY_erfc_Idle2TDTX
- 0x100a23c9 0x2f _zPHY_erfc_TxDbbSingleTone
- 0x100a23f8 0xc _zPHY_erfc_TransToRX
- 0x100a2404 0xe _zPHY_erfc_TransToTX
- 0x100a2412 0x1 _zPHY_erfc_DrvACP405GpioTest
- 0x100a2413 0xc _zPHY_erfc_DrvACP405Spi32BitWrReg
- 0x100a241f 0x11 _zPHY_erfc_ZTERfSPIWrite
- 0x100a2430 0x20 _zPHY_erfc_ZTERfSPIRead
- 0x100a2450 0x1f _zPHY_erfc_ZTERfMIPIRead
- 0x100a246f 0x1f _zPHY_erfc_ZTEAbbSPIRead
- 0x100a248e 0xa _zPHY_erfc_DrvZTE110RegSet
- 0x100a2498 0x49 _zPHY_erfc_DrvZTE110RxBandAndWidthConf
- 0x100a24e1 0x10 _zPHY_erfc_DrvZTE120TxDACEn
- 0x100a24f1 0x10 _zPHY_erfc_DrvZTE120TxDTXModeEn
- 0x100a2501 0xf _zPHY_erfc_DrvZTE120TxDACClk
- 0x100a2510 0x33 _zPHY_erfc_DrvCalcFracFreq
- 0x100a2543 0x72 _zPHY_erfc_ZTE110_RxRegConfig
- 0x100a25b5 0x65 _zPHY_erfc_ZTE110_TxRegConfig
- 0x100a261a 0x3a _zPHY_erfc_ZTE120_RxRegConfig
- 0x100a2654 0x36 _zPHY_erfc_ZTE120_TxRegConfig
- 0x100a268a 0x8c _zPHY_erfc_GetOpenRxRamNum
- 0x100a2716 0x1c5 _zPHY_erfc_EventOpenRx
- 0x100a28db 0x89 _zPHY_erfc_EventOpenRxAntenna
- 0x100a2964 0x18c _zPHY_erfc_EventOpenTx
- 0x100a2af0 0x65 _zPHY_erfc_EventOpenTxAntenna
- 0x100a2b55 0x92 _zPHY_erfc_GetOpenRxAntennaIndex
- 0x100a2be7 0xe9 _zPHY_erfc_GetOpenRxIndex
- 0x100a2cd0 0x30 _zPHY_erfc_GetOpenTxIndex
- 0x100a2d00 0x35 _zPHY_erfc_GetOpenTxAntennaIndex
- 0x100a2d35 0x26 _zPHY_erfc_GetOpenTxRamNum
- 0x100a2d5b 0xdc _zPHY_erfc_GetOpenRxLineIndex
- 0x100a2e37 0x70 _zPHY_erfc_GetOpenRxLineData
- 0x100a2ea7 0x55 _zPHY_erfc_GetNorTxOpenIndex
- 0x100a2efc 0x57 _zPHY_erfc_GetOpenTxLineIndex
- 0x100a2f53 0x6d _zPHY_erfc_GetOpenTxLineData
- 0x100a2fc0 0xb6 _zPHY_erfc_EventTableOpenRx
- 0x100a3076 0xae _zPHY_erfc_TxTableOpenTx
- 0x100a3124 0xd8 _zPHY_erfc_GetCloseAntennaIndex
- 0x100a31fc 0xdf _zPHY_erfc_GetRfToIdleIndex
- 0x100a32db 0x75 _zPHY_erfc_GetRfToIdleData
- 0x100a3350 0x97 _zPHY_erfc_EventAntennaToIdle
- 0x100a33e7 0xb9 _zPHY_erfc_EventRfToIdle
- 0x100a34a0 0x2d _zPHY_erfc_GetCloseRfRamNum
- 0x100a34cd 0x54 _zPHY_erfc_EventTableToIdle
- 0x100a3521 0x111 _zPHY_erfc_GetPAIndex
- 0x100a3632 0x7d _zPHY_erfc_AmtRfFrontSet
- 0x100a36af 0x2f _zPHY_erfc_RfAntenna_set
- 0x100a36de 0x6b _zPHY_erfc_RfPAFrontSet
- 0x100a3749 0x25 _zPHY_erfc_ATSetAptFixVoltage
- 0x100a376e 0xe8 _zPHY_erfc_GetRfVGACtrlWord
- 0x100a3856 0x14 _zPHY_erfc_LittleTabWritePATrigEna
- 0x100a386a 0x14 _zPHY_erfc_LittleTabWritePATrigLoad
- 0x100a387e 0x14 _zPHY_erfc_LittleTabWritePATrigDisa
- 0x100a3892 0x13e _zPHY_erfc_LittleTabWritePaAndVga
- 0x100a39d0 0x49 _zPHY_erfc_SupCheckPAMode
- 0x100a3a19 0x1 _zPHY_erfc_RxSinToneTest
- 0x100a3a1a 0x1 _zPHY_erfc_TxSinToneTest
- 0x100a3a1b 0x1 _zPHY_erfc_DrvRfNvInit
- 0x100a3a1c 0x44 _zPHY_erfc_GetRfDCOC_CalVaue
- .text 0x100a3a60 0x204 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
- 0x100a3a60 0x21 _zPHY_erfc_DrvRfcTxSampleRateSet
- 0x100a3a81 0x34 _zPHY_erfc_DrvRfcDfeSampleRateSet
- 0x100a3ab5 0x4c _zPHY_erfc_DrvInitMainSyncTable
- 0x100a3b01 0xa5 _zPHY_erfc_DrvInitMeasTable0
- 0x100a3ba6 0x45 _zPHY_erfc_DrvInitTxSendTable
- 0x100a3beb 0x42 _zPHY_erfc_DrvEventTableBoundaryInit
- 0x100a3c2d 0xc _zPHY_erfc_IRAM_Set
- 0x100a3c39 0x1a _zPHY_erfc_IRAM_Get
- 0x100a3c53 0x10 _zPHY_erfc_DrvDBBDely
- 0x100a3c63 0x1 _zPHY_erfc_DrvRfTopIntfInit
- .text 0x100a3c64 0xb70 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
- 0x100a3c64 0x4a _zPHY_edfe_DrvInitInt
- 0x100a3cae 0x53 _zPHY_edfe_DrvResetHw
- 0x100a3d01 0x3b _zPHY_edfe_DrvConfigRXBandwidth
- 0x100a3d3c 0x3b _zPHY_edfe_DrvConfigCSRMBandwidth
- 0x100a3d77 0x1f _zPHY_edfe_DrvGetDCOffsetEsti
- 0x100a3d96 0x2c _zPHY_edfe_DrvConfigDCOffset
- 0x100a3dc2 0x1f _zPHY_edfe_DrvGetIQEstiSum
- 0x100a3de1 0x1f _zPHY_edfe_DrvGetIQEstiCPSum
- 0x100a3e00 0x30 _zPHY_edfe_DrvConfigIQImbal
- 0x100a3e30 0x6a _zPHY_edfe_DrvConfigAGCPara
- 0x100a3e9a 0x14 _zPHY_edfe_DrvGetAGCMeanPower
- 0x100a3eae 0x12 _zPHY_edfe_DrvGetAGCLFOutVal
- 0x100a3ec0 0xa _zPHY_edfe_DrvGetAGCHWGainValue
- 0x100a3eca 0xa _zPHY_edfe_DrvCompesateCFO
- 0x100a3ed4 0x27 _zPHY_edfe_DrvDcIqParaInit
- 0x100a3efb 0x8a _zPHY_edfe_DrvConfigFIRCoeff
- 0x100a3f85 0x50 _zPHY_edfe_DrvConfigDAGCPara
- 0x100a3fd5 0x31 _zPHY_edfe_DrvGetDAGCMeanPower
- 0x100a4006 0x12 _zPHY_edfe_DrvGetMbsfnDAGCMeanPower
- 0x100a4018 0x52 _zPHY_edfe_DrvConfigDAGCSWGainValue
- 0x100a406a 0x3b _zPHY_edfe_DrvConfigMbsfnRxDAGCSWGainValue
- 0x100a40a5 0x1 _zPHY_edfe_DrvAGCGainConvertTableInit
- 0x100a40a6 0x7e _zPHY_edfe_DrvInitDFE
- 0x100a4124 0x72 _zPHY_edfe_DrvDcIqCfoDagcApplyEn
- 0x100a4196 0xd0 _zPHY_edfe_DrvRxCPModeConfig
- 0x100a4266 0x1 _zPHY_edfe_DrvCsrmCPModeConfig
- 0x100a4267 0x29 _zPHY_edfe_DrvAgcExtModeConfig
- 0x100a4290 0x22 _zPHY_edfe_DrvDfeAbbSamplingRateConfig
- 0x100a42b2 0x1a _zPHY_edfe_DrvMbsfnTwoAgcDagcEn
- 0x100a42cc 0xb _zPHY_edfe_DrvMbsfnTimingOffset
- 0x100a42d7 0x14 _zPHY_edfe_DrvTxCaliConfig
- 0x100a42eb 0x1e _zPHY_edfe_DrvMeasBufferModeComnParaConfig
- 0x100a4309 0x15 _zPHY_edfe_DrvMeasBufferModeCellParaConfig
- 0x100a431e 0x9 _zPHY_edfe_DrvMeasBufferModeRamReadEn
- 0x100a4327 0x29 _zPHY_edfe_DrvMeasMode
- 0x100a4350 0x15 _zPHY_edfe_DrvMeasClock
- 0x100a4365 0xe _zPHY_edfe_DrvMeasClockClose
- 0x100a4373 0x15 _zPHY_edfe_DrvMeasReset
- 0x100a4388 0x14 _zPHY_edfe_DrvGetMbsfnAGCMeanPower
- 0x100a439c 0x29 _zPHY_edfe_DrvConfigMbsfnAGCSWGainValue
- 0x100a43c5 0x14 _zPHY_edfe_DrvLpcSaveRegForCsr
- 0x100a43d9 0x2a _zPHY_edfe_DrvLpcSaveRegForRxCommon
- 0x100a4403 0xe8 _zPHY_edfe_DrvLpcResumeRxCommon
- 0x100a44eb 0x3 _zPHY_edfe_DrvLpcResumePower1Public
- 0x100a44ee 0x68 _zPHY_edfe_DrvLpcResumeCsr
- 0x100a4556 0x20 _zPHY_edfe_DrvLpcResumePower0Public
- 0x100a4576 0x12 _zPHY_edfe_DrvAgcLenStepConfig
- 0x100a4588 0xb _zPHY_edfe_DrvDagc2LenStepConfig
- 0x100a4593 0x13 _zPHY_edfe_DrvAntModeConfig
- 0x100a45a6 0x26 _zPHY_edfe_DrvAgcIntStateConfig
- 0x100a45cc 0x8 _zPHY_edfe_DrvConfigAgcCalControl
- 0x100a45d4 0x18 _zPHY_edfe_DrvGetEverySampMeanPower
- 0x100a45ec 0x1 _zPHY_edfe_DrvRfcDfeInterfaceSet
- 0x100a45ed 0x1 _zPHY_edfe_DrvPrsMeasModeComnParaConfig
- 0x100a45ee 0x1 _zPHY_edfe_DrvCsrInputSelect
- 0x100a45ef 0x2 _zPHY_edfe_DrvGetCsrInputSelState
- 0x100a45f1 0x54 _zPHY_edfe_DrvResetPwr0
- 0x100a4645 0xa _zPHY_edfe_DrvDfeIntfSel
- 0x100a464f 0x16 _zPHY_edfe_DrvCPAddLenConfig
- 0x100a4665 0x30 _zPHY_edfe_DrvCsrDDrCatchDataEn
- 0x100a4695 0xd _zPHY_edfe_DrvCsrDDrCatchDataStop
- 0x100a46a2 0x1f _zPHY_edfe_DrvPwr0RestCsrSyncHw
- 0x100a46c1 0x3c _L1l_DrvDfeCalcNotchParaA
- 0x100a46fd 0x8 _L1l_DrvDfeNotchSetBypass
- 0x100a4705 0xa _L1l_DrvDfeNotchSetA_First
- 0x100a470f 0xa _L1l_DrvDfeNotchSetA_Second
- 0x100a4719 0xa _L1l_DrvDfeNotchSetA_Third
- 0x100a4723 0xc _L1l_DrvDfeNotchSetT_A
- 0x100a472f 0xc _L1l_DrvDfeNotchSetT_B
- 0x100a473b 0xe _L1l_DrvDfeNotchSetK_A
- 0x100a4749 0xe _L1l_DrvDfeNotchSetK_B
- 0x100a4757 0xf _zPHY_edfe_DrvEnableDcInt
- 0x100a4766 0x5 _zPHY_edfe_ClkPrintf
- 0x100a476b 0x69 _zPHY_edfe_LteBuffRegPrint
- .text 0x100a47d4 0x879 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
- 0x100a47d4 0x2a _zEcsr_CurrentGapTime
- 0x100a47fe 0x1d _zEcsr_CurrentGapSuperTime
- 0x100a481b 0x3c _zEcsr_GetGapStateEx
- 0x100a4857 0x13 _zEcsr_GetLteGapState
- 0x100a486a 0x9 _zEcsr_GetGapState
- 0x100a4873 0x16 _zEcsr_GetIratGapState
- 0x100a4889 0x23 _zEcsr_GapCnt
- 0x100a48ac 0x48 _zEcsr_GetLastGapTime
- 0x100a48f4 0x42 _zEcsr_GetGapStartTime
- 0x100a4936 0x4b _zEcsr_GetNeartGapTime
- 0x100a4981 0x76 _zEcsr_GetTimeBeforeIratGap
- 0x100a49f7 0x42 _zEcsr_GetTimeBeforeGapEx
- 0x100a4a39 0x8 _zEcsr_GetTimeBeforeGap
- 0x100a4a41 0x12 _zEcsr_GetTimeBeforeLteGap
- 0x100a4a53 0x19 _zEcsr_Compare
- 0x100a4a6c 0xb _zEcsr_GapTimeCompare
- 0x100a4a77 0x7 _zEcsr_TimeCompare
- 0x100a4a7e 0x40 _zEcsr_BeforeGapHalfFrame
- 0x100a4abe 0x40 _zEcsr_AfterGapHalfFrame
- 0x100a4afe 0x33 _zEcsr_GetGapOffsetEx
- 0x100a4b31 0x8 _zEcsr_GetGapOffset
- 0x100a4b39 0x60 _zEcsr_GetGapType
- 0x100a4b99 0x32 _zEcsr_IsValidGapTime
- 0x100a4bcb 0x61 _zEcsr_GetGapDistance
- 0x100a4c2c 0x89 _zEcsr_GapType
- 0x100a4cb5 0x13 _zEcsr_GetLteGapOffset
- 0x100a4cc8 0x14 _zEcsr_IsAroundGap
- 0x100a4cdc 0x14 _zEcsr_IsAroundLteGap
- 0x100a4cf0 0x54 _zEcsr_CurrentGapType
- 0x100a4d44 0x3d _zEcsr_CurrentGapStartTime
- 0x100a4d81 0x10 _zEcsr_CurrentGapFrame
- 0x100a4d91 0x18 _zEcsr_NextGapFrame
- 0x100a4da9 0xd _zEcsr_GapSubFrame
- 0x100a4db6 0xe _zEcsr_LteGapGapAvai
- 0x100a4dc4 0xc _zEcsr_CurrentGapStartMrtr
- 0x100a4dd0 0x19 _zEcsr_CurrentMrtrUpper
- 0x100a4de9 0x2a _zEcsr_NextHalfFrame
- 0x100a4e13 0x2d _zEcsr_TimeToMrtr
- 0x100a4e40 0x12 _zEcsr_MrtrToTime
- 0x100a4e52 0xb _zEcsr_TimeToTs
- 0x100a4e5d 0x57 _zEcsr_TimeOnGapConfig
- 0x100a4eb4 0x1a _zEcsr_TimeInit
- 0x100a4ece 0x7 _zPHY_ecsrc_CtrltTime2Ts
- 0x100a4ed5 0x1f _zPHY_ecsrc_TimeAdd
- 0x100a4ef4 0x25 _zPHY_ecsrc_TimeSub
- 0x100a4f19 0x16 _zPHY_ecsrc_MrtrAddTs
- 0x100a4f2f 0x19 _zPHY_ecsrc_MrtrAddSlot
- 0x100a4f48 0x1c _zPHY_ecsrc_MrtrSubTs
- 0x100a4f64 0x1f _zPHY_ecsrc_MrtrSubSlot
- 0x100a4f83 0x2b _zPHY_ecsrc_MrtrAddSignTs
- 0x100a4fae 0x24 _zPHY_ecsrc_GetCurTime
- 0x100a4fd2 0x18 _zPHY_ecsrc_Mrtr2LocalMrtr
- 0x100a4fea 0x18 _zPHY_ecsrc_LocalMrtr2Mrtr
- 0x100a5002 0x4 _zPHY_ecsrc_RemoveMrtrTs
- 0x100a5006 0x23 _zPHY_ecsrc_MakeMrtr
- 0x100a5029 0x24 _zPHY_ecsrc_TsToLocalTs
- .text 0x100a504d 0x571 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc.o)
- 0x100a504d 0x571 _zPHY_erapc_ThreadEntry
- .text 0x100a55be 0x12ff T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
- 0x100a55be 0xcf _zPHY_ecsrc_InitMeasOnIdle
- 0x100a568d 0x31 _zPHY_ecsrc_ConfigRfcOffset
- 0x100a56be 0x96 _zPHY_ecsrc_CtrlCampOnProcess
- 0x100a5754 0x9a _zPHY_ecsrc_CtrlMeasConfigProcess
- 0x100a57ee 0x141 _zPHY_ecsrc_CtrlMeasSetProcess
- 0x100a592f 0x37 _zPHY_ecsrc_SetMeasAge
- 0x100a5966 0x7c _L1e_csrc_IdleSetAgeThrold
- 0x100a59e2 0x147 _L1e_csrc_ConnectSetAgeThrold
- 0x100a5b29 0x46 _zPHY_ecsrc_CtrlSetSearchMeasAgeThrold
- 0x100a5b6f 0x73 _zPHY_ecsrc_ReadRxMeas
- 0x100a5be2 0x47 _zPHY_ecsrc_ReadServCellRxMeas
- 0x100a5c29 0x23 _zPHY_ecsrc_GetCellMeasReslut
- 0x100a5c4c 0x96 _zPHY_ecsrc_CtrlWriteServingCellResult
- 0x100a5ce2 0x3d _zPHY_ecsrc_SetMeasResultValue
- 0x100a5d1f 0x3c _zPHY_ecsrc_WriteNeibMeasResult
- 0x100a5d5b 0x10 _zPHY_ecsrc_CtrlWritePccMeasResult
- 0x100a5d6b 0x14d _zPHY_ecsrc_CtrlMeasFilterReq
- 0x100a5eb8 0x13 _zPHY_ecsrc_ConnAcquireIntraMeas
- 0x100a5ecb 0x70 _zPHY_ecsrc_AcquireInterMeas
- 0x100a5f3b 0x16 _zPHY_ecsrc_AcquireServMeas
- 0x100a5f51 0xd _zPHY_ecsrc_ReportMeasReslutIntra
- 0x100a5f5e 0x50 _zPHY_ecsrc_ReportMeasReslutInter
- 0x100a5fae 0x2b _zPHY_ecsrc_UpdateRsrpKByFlagCounter
- 0x100a5fd9 0x38 _zPHY_ecsrc_AdaptFilterFactor
- 0x100a6011 0xb5 _zPHY_ecsrc_FreqFilter
- 0x100a60c6 0x33 _zPHY_ecsrc_FilterNoResult
- 0x100a60f9 0x30 _zPHY_ecsrc_DelInvalidCell
- 0x100a6129 0x9b _zPHY_ecsrc_InterMeasFilter
- 0x100a61c4 0x72 _zPHY_ecsrc_IntraMeasFilter
- 0x100a6236 0x69 _zPHY_ecsrc_FilterMeasRank
- 0x100a629f 0x42 _zPHY_ecsrc_ReportMeasRank
- 0x100a62e1 0x34 _zPHY_ecsrc_UpdateFreqReport
- 0x100a6315 0x7a _zPHY_ecsrc_UpdateIntraReport
- 0x100a638f 0x9 _zPHY_ecsrc_GetFilterIntraMeasRsrp
- 0x100a6398 0x70 _zPHY_ecsrc_UpdateInterReport
- 0x100a6408 0x12 _zPHY_ecsrc_ClearNeibCellRsrp
- 0x100a641a 0x1c _zPHY_ecsrc_ClearIntraFilter
- 0x100a6436 0x23 _L1e_csrc_SetIdleFilterFactor
- 0x100a6459 0x2e _zPHY_ecsrc_SetFilterFactor
- 0x100a6487 0x62 _zPHY_ecsrc_FilterMeasCfg
- 0x100a64e9 0x4 _zPHY_ecsrc_FilterComnCfg
- 0x100a64ed 0xc _zPHY_ecsrc_InitInterFilter
- 0x100a64f9 0x36 _zPHY_ecsrc_InitInterFilterFreq
- 0x100a652f 0x60 _zPHY_ecsrc_InitIntraFilter
- 0x100a658f 0x47 _zPHY_ecsrc_InterMeasIndPrint
- 0x100a65d6 0x49 _zPHY_ecsrc_CtrlIntraMeasInfoPrint
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- 0x100a6872 0x10 _L1e_DevCsrGetMeasResult
- 0x100a6882 0x3b _zPHY_ecsrc_CtrlIdleSetInterFilterFact
- .text 0x100a68bd 0x21b2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
- 0x100a68bd 0x8 _L1e_Sir_RxMeasMask
- 0x100a68c5 0x8 _L1e_Sir_QuryRxMeasMask
- 0x100a68cd 0x27f _L1e_Sir_MainCtrlFlow
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- 0x100a6b7f 0x31 _L1e_Sir_LpcAndTurboCtrl
- 0x100a6bb0 0x30 _L1e_Sir_AddTpuEvt
- 0x100a6be0 0x28 _L1e_Sir_DelAllTpuEvt
- 0x100a6c08 0x26 _L1e_Sir_QueryTpuEvt
- 0x100a6c2e 0x33 _L1e_Sir_DelTpuEvt
- 0x100a6c61 0x4a _L1e_Sir_RegDelayEvt
- 0x100a6cab 0x21 _L1e_Sir_PreProc
- 0x100a6ccc 0x8 _L1e_Sir_MainState
- 0x100a6cd4 0x8 _L1e_Sir_StepState
- 0x100a6cdc 0x8 _L1e_Sir_SyncState
- 0x100a6ce4 0x19 _L1e_Sir_CommInSiProc
- 0x100a6cfd 0x34 _L1e_Sir_SetState
- 0x100a6d31 0x98 _L1e_Sir_UpSib1Para
- 0x100a6dc9 0x75 _L1e_Sir_UpSiPara
- 0x100a6e3e 0x15 _L1e_Sir_UpSerPara
- 0x100a6e53 0x2d _L1e_Sir_UpDecPara
- 0x100a6e80 0x8 _L1e_Sir_UpDecState
- 0x100a6e88 0xd _L1e_Sir_QurySerSir
- 0x100a6e95 0xc _L1e_Sir_QurySib1State
- 0x100a6ea1 0xd _L1e_Sir_QurySiState
- 0x100a6eae 0x1a _L1e_Sir_QueryRptEn
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- 0x100a6f55 0x4e _L1e_Sir_UpSchedPara
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- 0x100a7cd2 0x1e _L1e_Sir_GetNeiBorSibState
- 0x100a7cf0 0x2d _L1e_Sir_GetNeiBorSib1ReportState
- 0x100a7d1d 0x1c _L1e_Sir_GetSerSibState
- 0x100a7d39 0x12 _L1e_Sir_GetNeiBorSiBackState
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- 0x100a7d58 0x8 _L1e_Sir_GetSiSubFrmPat
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- 0x100a7e19 0x80 _L1e_Sir_PreSyncSched
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- 0x100a7eae 0x7 _L1e_Sir_GetSiSyncSchedState
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- 0x100a7fc4 0x8 _L1e_Anr_ProcIndGet
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- 0x100a866a 0x2f _L1e_Sir_ErrMonitor
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- 0x100a87c0 0x43 _L1e_Sir_MibCnfMonitor
- 0x100a8803 0x2c _L1e_Sir_RxRcvCtrlMonitor
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- 0x100a8a0f 0x32 _L1e_Anr_GapPrintf
- 0x100a8a41 0x2e _L1e_Anr_ErrProcMonitor
- .text 0x100a8a6f 0x3f87 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
- 0x100a8a6f 0x27 _zPHY_emc_DvfsPatch
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- 0x100a8aa8 0x12 _zPHY_emc_PhyMsgIdFindIndex
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- 0x100a8eb6 0x5a _zPHY_emc_ProPhy2PsMsgLog
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- 0x100aa32a 0x1fd _zPHY_emc_ProTASchedFlow
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- 0x100abcdd 0xd _L1e_SchedMc_StoreFreqScan
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- 0x100ac1a3 0x32 _zPHY_emc_ATCheckSinrRsrp
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- .text 0x100ac9f6 0x4e1e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
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- 0x100acade 0x14 _zPHY_ecsrc_SchedFreq2Earfcn
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- 0x100acba4 0x12 _zPHY_ecsrc_CtrlRsrqTrans
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- 0x100acbf8 0x37 _zPHY_ecsrc_SendCfoStartReq
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- 0x100acce2 0x51 _zPHY_ecsrc_SendMibReadReq
- 0x100acd33 0x2c _zPHY_ecsrc_SendTpuMacroAdjReq
- 0x100acd5f 0x2a _zPHY_ecsrc_SendFreqScanReq
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- 0x100acd96 0x8 _zPHY_ecsrc_SetAllRxMaskFlag
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- 0x100acebe 0x13 _zPHY_ecsrc_ProReset
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- 0x100acee6 0x10 _zPHY_emc_SetPhyMode
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- 0x100acf4a 0x3a _zPHY_ecsrc_TpuEventMark
- 0x100acf84 0x1b _zPHY_ecsrc_TpuEventCheck
- 0x100acf9f 0x4c _zPHY_ecsrc_DelTpuEvent
- 0x100acfeb 0x1c _zPHY_ecsrc_TpuEventClean
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- 0x100ad00e 0x22 _zPHY_ecsrc_GetBandIdx
- 0x100ad030 0x2b _zPHY_ecsrc_MibInfoOutput
- 0x100ad05b 0x23 _zPHY_ecsrc_FilterOut
- 0x100ad07e 0x62 _zPHY_ecsrc_CtrlReleaseProcess
- 0x100ad0e0 0x69 _zPHY_ecsrc_CfgRfcFreqBand
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- 0x100ad165 0x2d _zPHY_ecsrc_RecoverToServingFreq
- 0x100ad192 0x1c _zPHY_ecsrc_ResetSearchMeas
- 0x100ad1ae 0x71 _zPHY_ecsrc_StopInterSearchMeas
- 0x100ad21f 0x40 _L1e_csrc_PreWakeUpPS
- 0x100ad25f 0x18 _zPHY_ecsrc_TsDelayMsgRegister
- 0x100ad277 0x34 _zPHY_ecsrc_DelayMsgRegister
- 0x100ad2ab 0x4d _zPHY_ecsrc_RegTpuAdjDelay
- 0x100ad2f8 0x118 _zPHY_ecsrc_CtrlConnectedIntraReportEvent
- 0x100ad410 0x4a _zPHY_ecsrc_CtrlConnectedInterReportEvent
- 0x100ad45a 0x38 _zPHY_ecsrc_CtrlConnectAgingProcess
- 0x100ad492 0x17 _zPHY_ecsrc_CfgRfcSynState
- 0x100ad4a9 0x37 _zPHY_ecsrc_GetInterReportPeriod
- 0x100ad4e0 0x88 _zPHY_ecsrc_CtrlConnectedMeasSchedule
- 0x100ad568 0x31 _zPHY_ecsrc_OpenSubFrameInt
- 0x100ad599 0x15 _zPHY_ecsrc_DelSfInt
- 0x100ad5ae 0x18 _zPHY_ecsrc_InitGapCnt
- 0x100ad5c6 0x19 _zPHY_ecsrc_UpdateGapCnt
- 0x100ad5df 0x3d _zPHY_ecsrc_DrxRefreshGapCnt
- 0x100ad61c 0x48 _zPHY_ecsrc_DrxSetIntraWorkPeriod
- 0x100ad664 0x80 _zPHY_ecsrc_DrxSetInterWorkPeriod
- 0x100ad6e4 0x13 _zPHY_ecsrc_DrxSetInterRprtPeriod
- 0x100ad6f7 0x8d _L1e_csrc_RegConEvent
- 0x100ad784 0x6f _zPHY_ecsrc_CtrlDedicateConfigProcess
- 0x100ad7f3 0x48 _zPHY_ecsrc_CtrlConncetGapConfigProcess
- 0x100ad83b 0x100 _zPHY_ecsrc_CtrlConnectedSetInterFreq
- 0x100ad93b 0xa6 _zPHY_ecsrc_CtrlConnectedScheduleInterFreq
- 0x100ad9e1 0xc7 _zPHY_ecsrc_CtrlHandoverSearch
- 0x100adaa8 0x25 _zPHY_ecsrc_CtrlHandoverCfoEn
- 0x100adacd 0x1f _zPHY_ecsrc_CtrlHandoverMibInd
- 0x100adaec 0x112 _zPHY_ecsrc_CtrlHandoverPro
- 0x100adbfe 0x114 _zPHY_ecsrc_CtrlHandoverSearchTimeEvent
- 0x100add12 0x49 _zPHY_ecsrc_CtrlHandoverPbchTimeEvent
- 0x100add5b 0x38 _zPHY_ecsrc_LteAmtULEarfchTableInfo
- 0x100add93 0x38 _zPHY_ecsrc_LteAmtDLEarfchTableInfo
- 0x100addcb 0x3a _zPHY_ecsrc_LteAmtFDTEarfchTableInfo
- 0x100ade05 0x15 _zPHY_ecsrc_AmtUpdateEarfcnBand
- 0x100ade1a 0x2d _zPHY_ecsrc_RegDrxNoUseEvent
- 0x100ade47 0x24 _zPHY_ecsrc_DelDrxNoUseEvent
- 0x100ade6b 0xc _zPHY_ecsrc_IsDrxUsed
- 0x100ade77 0x29 _zPHY_ecsrc_IsWorkGap
- 0x100adea0 0x34 _zPHY_ecsrc_WaitIratGap
- 0x100aded4 0x42 _zPHY_ecsrc_IntraFreqEnable
- 0x100adf16 0x5e _zPHY_ecsrc_InterFreqEnable
- 0x100adf74 0xb8 _zPHY_ecsrc_CalIntraWorkTime
- 0x100ae02c 0x4d _zPHY_ecsrc_SetSearchPhase
- 0x100ae079 0x4c _zPHY_ecsrc_GetSearchPhase
- 0x100ae0c5 0x1b _zPHY_ecsrc_ClearSearchEnable
- 0x100ae0e0 0x49 _zPHY_ecsrc_FindEnableFreq
- 0x100ae129 0x3a _zPHY_ecsrc_UpdateSearchEnable
- 0x100ae163 0x2f _zPHY_ecsrc_IsSearchDone
- 0x100ae192 0x4b _zPHY_ecsrc_RecoverEnableFlag
- 0x100ae1dd 0x90 _zPHY_ecsrc_CalRemainTime
- 0x100ae26d 0x1cf _zPHY_ecsrc_FindUndoneFreq
- 0x100ae43c 0x1b _L1e_csrc_FindEnableInterFreq
- 0x100ae457 0x1d5 _L1e_csrc_FindUndoFreq
- 0x100ae62c 0x6c _L1e_csrc_DrxIntraReport
- 0x100ae698 0x4e _L1e_csrc_DrxInterReport
- 0x100ae6e6 0xb7 _L1e_csrc_DrxSchdEnd
- 0x100ae79d 0x3b _L1e_csrc_DrxIntraSchd
- 0x100ae7d8 0x42 _L1e_csrc_DrxInterSchd
- 0x100ae81a 0x6e _L1e_csrc_ShortDrxIntraSchd
- 0x100ae888 0x40 _L1e_csrc_ShortDrxInterSchd
- 0x100ae8c8 0x49 _L1e_csrc_AbortDrxSchd
- 0x100ae911 0x15 _L1e_csrc_CsrIsWork
- 0x100ae926 0x127 _zPHY_ecsrc_DrxCheckEvent
- 0x100aea4d 0x8 _L1e_csrc_GetStopMeas
- 0x100aea55 0xe _L1e_csrc_CfgGapCnt
- 0x100aea63 0xca _L1e_csrc_ShortDrxSchd
- 0x100aeb2d 0x30 _L1e_csrc_ShortDrxReSchd
- 0x100aeb5d 0x104 _zPHY_ecsrc_CnnDrxStartSchedule
- 0x100aec61 0x48 _zPHY_ecsrc_CnnDrxSetup
- 0x100aeca9 0x1b _zPHY_ecsrc_CnnDrxRelease
- 0x100aecc4 0x41 _L1e_csrc_ShortDrxSchdFlag
- 0x100aed05 0x8 _L1e_csrc_GetDfeValidFlag
- 0x100aed0d 0x87 _zPHY_ecsrc_CtrlAbortMeasProcess
- 0x100aed94 0x8 _zPHY_ecsrc_ReadSubframeOffset
- 0x100aed9c 0x15 _zPHY_ecsrc_SubframeOffsetToRfc
- 0x100aedb1 0x8 _zPHY_ecsrc_SetFddAdjust
- 0x100aedb9 0x30 _zPHY_ecsrc_ClearRfcSFData
- 0x100aede9 0x12 _zPHY_ecsrc_ClearRfTable
- 0x100aedfb 0x12 _L1e_csrc_ClearRfMeasState
- 0x100aee0d 0x2c _zPHY_ecsrc_SetFreq
- 0x100aee39 0xa _zPHY_ecsrc_SetInterFreq
- 0x100aee43 0x15 _zPHY_ecsrc_FindEvent
- 0x100aee58 0x43 _zPHY_ecsrc_RegisterEvent
- 0x100aee9b 0x1d _zPHY_ecsrc_CancelEvent
- 0x100aeeb8 0x12 _zPHY_ecsrc_CancelAllEvent
- 0x100aeeca 0x7b _zPHY_ecsrc_CheckEvent
- 0x100aef45 0x40 _zPHY_ecsrc_ConnCheckEvent
- 0x100aef85 0x44 _zPHY_ecsrc_ExcuteEvent
- 0x100aefc9 0x3e _zPHY_ecsrc_ChangeIntraReportPeriod
- 0x100af007 0x33 _zPHY_ecsrc_ChangeIntraReportPeriodDrx
- 0x100af03a 0x7 _zPHY_ecsrc_OnSetMode
- 0x100af041 0x25 _zPHY_ecsrc_OnIratIdlePeriodRepReq
- 0x100af066 0x37 _zPHY_ecsrc_OnInactiveTimeReportInt
- 0x100af09d 0x19 _zPHY_ecsrc_OnFreqListConfigReq
- 0x100af0b6 0x2e _zPHY_ecsrc_OnIratMeasConfigReq
- 0x100af0e4 0x32 _zPHY_ecsrc_OnIratMeasReportInt
- 0x100af116 0xf1 _zPHY_ecsrc_OnIratGapConfigReq
- 0x100af207 0x6f _zPHY_ecsrc_OnIratGapConfigDelayInt
- 0x100af276 0x24 _zPHY_ecsrc_OnRfStartDealSfInt
- 0x100af29a 0x14 _zPHY_ecsrc_OnRfCloseDealSfInt
- 0x100af2ae 0x2f _zPHY_ecsrc_OnReset
- 0x100af2dd 0x4e _zPHY_ecsrc_OnCellSearchReq
- 0x100af32b 0x39 _zPHY_ecsrc_InitOnCellSearchReq
- 0x100af364 0xae _zPHY_ecsrc_CtrlAppointSearchPbchTimeEvent
- 0x100af412 0x52 _zPHY_ecsrc_CtrlAppointSearchTimeEvent
- 0x100af464 0x2a _zPHY_ecsrc_CtrlAppointSearchPbchEndEvent
- 0x100af48e 0xd _zPHY_ecsrc_AppointCellSearchType
- 0x100af49b 0x17 _zPHY_ecsrc_NeibCellSearchType
- 0x100af4b2 0x99 _zPHY_ecsrc_IdleOnCellSearchReq
- 0x100af54b 0x16 _zPHY_ecsrc_SlaveOnCellSearchReq
- 0x100af561 0x1a _zPHY_ecsrc_OnCtrlIniSearchCnf
- 0x100af57b 0x19 _zPHY_ecsrc_OnTimeDelayInt
- 0x100af594 0x19 _zPHY_ecsrc_OnSssUpdateCounterCnf
- 0x100af5ad 0xd _zPHY_ecsrc_OnIniMeasTimeEvent
- 0x100af5ba 0x1c _zPHY_ecsrc_OnAbortCellSearchReq
- 0x100af5d6 0x27 _zPHY_ecsrc_OnCommonConfigReq
- 0x100af5fd 0x4e _zPHY_ecsrc_OnMeasConfigReq
- 0x100af64b 0x130 _zPHY_ecsrc_SaveMask
- 0x100af77b 0x98 _zPHY_ecsrc_OnMeasMaskSetReq
- 0x100af813 0x30 _zPHY_ecsrc_OnAbortMeasReq
- 0x100af843 0x3e _zPHY_ecsrc_OnChangeMeasPeriodReq
- 0x100af881 0x11 _zPHY_ecsrc_OnIdleInterRfChangeFinishedEvent
- 0x100af892 0x39 _zPHY_ecsrc_OnIratMeasGapConfigReq
- 0x100af8cb 0x1f _zPHY_ecsrc_OnFreqScanReq
- 0x100af8ea 0x3b _zPHY_ecsrc_InitOnFreqScanReq
- 0x100af925 0x53 _zPHY_ecsrc_IdleOnFreqScanReq
- 0x100af978 0x27 _zPHY_ecsrc_SlaveOnFreqScanReq
- 0x100af99f 0x21 _zPHY_ecsrc_OnCtrlSearchFreqScanCnf
- 0x100af9c0 0x1c _zPHY_ecsrc_OnHandoverReq
- 0x100af9dc 0x10 _zPHY_ecsrc_OnPlmnResumeSrvCellTpu
- 0x100af9ec 0x2c _zPHY_ecsrc_OnPlmnPeriodTpuIntIn
- 0x100afa18 0x26 _zPHY_ecsrc_FreqScanSubFrameIntDelay
- 0x100afa3e 0x47 _zPHY_ecsrc_RunningCheck
- 0x100afa85 0x8d _zPHY_ecsrc_OnArfcnListInfo
- 0x100afb12 0x47 _zPHY_amt_Lte_Set_EarfcnInfo
- 0x100afb59 0xf _L1e_csrc_HandoverSuccPro
- 0x100afb68 0x1b _zPHY_ecsrc_StartProc
- 0x100afb83 0x15f _zPHY_ecsrc_ComProc
- 0x100afce2 0x15 _zPHY_ecsrc_InitProc
- 0x100afcf7 0x6f _zPHY_ecsrc_IdleProc
- 0x100afd66 0x21 _zPHY_ecsrc_ConnProc
- 0x100afd87 0x91 _zPHY_ecsrc_SlaveProc
- 0x100afe18 0x5b _zPHY_ecsrc_Ctrl
- 0x100afe73 0x46 _zPHY_ecsrc_ThreadEntry
- 0x100afeb9 0xc8 _zEcsrc_PreEvent
- 0x100aff81 0x38 _zEcsrc_OnEvent
- 0x100affb9 0x52 _zPHY_ecsrc_ReadSnr
- 0x100b000b 0xd6 _zPHY_ecsrc_ReadSearctT
- 0x100b00e1 0x1e _zPHY_ecsrc_ReadIntraSearctT
- 0x100b00ff 0x1e _zPHY_ecsrc_ReadSpeedSearctT
- 0x100b011d 0x1d _zPHY_ecsrc_ReadCfoUpdateT
- 0x100b013a 0x2a _zPHY_ecsrc_GetDestTime
- 0x100b0164 0x1c _zPHY_ecsrc_CalDestTimeOffset
- 0x100b0180 0x19 _zPHY_ecsrc_GetNonHighPrioFreqNum
- 0x100b0199 0x19 _zPHY_ecsrc_GetHighPrioFreqNum
- 0x100b01b2 0x13 _zPHY_ecsrc_GetReportNum
- 0x100b01c5 0x31 _zPHY_ecsrc_NeedIntraSearchStep
- 0x100b01f6 0x2e _zPHY_ecsrc_NeedIntraSearchStepNormal
- 0x100b0224 0x45 _zPHY_ecsrc_NeedIntraSearch
- 0x100b0269 0x22 _zPHY_ecsrc_IsNonHighPrioWorkDrx
- 0x100b028b 0xaa _zPHY_ecsrc_NeedWork
- 0x100b0335 0x54 _zPHY_ecsrc_CalcInitDrxNum
- 0x100b0389 0x7f _zPHY_ecsrc_CalcWorkDrxNum
- 0x100b0408 0x22 _zPHY_ecsrc_NeedInterSearch
- 0x100b042a 0x9 _zPHY_ecsrc_NeedInterMeas
- 0x100b0433 0x52 _zPHY_ecsrc_NeedIntraMeas
- 0x100b0485 0x3f _zPHY_ecsrc_FreqIndexAcc
- 0x100b04c4 0x37 _zPHY_ecsrc_IsLastFreqInDrx
- 0x100b04fb 0x72 _L1e_csrc_SRCellRank
- 0x100b056d 0x9a _L1e_csrc_SaveSRCellInfo
- 0x100b0607 0x52 _L1e_csrc_SetSRCellInfo
- 0x100b0659 0x121 _L1e_csrc_GetMobileCxtFlag
- 0x100b077a 0x47 _zPHY_ecsrc_CtrlIdleIntraMeasEndEventNew
- 0x100b07c1 0x37 _zPHY_ecsrc_GetReportDrxNum
- 0x100b07f8 0x2 _zPHY_ecsrc_EverTrue
- 0x100b07fa 0x10 _zPHY_ecsrc_StartDelayTimer
- 0x100b080a 0x9 _zPHY_ecsrc_WaitEvent
- 0x100b0813 0x1d _zPHY_ecsrc_SchedInit
- 0x100b0830 0x1f _zPHY_ecsrc_SchedStop
- 0x100b084f 0x8 _zPHY_ecsrc_SchedStart
- 0x100b0857 0x15 _zPHY_ecsrc_NeedWorkInReportPeriod
- 0x100b086c 0xbc _zPHY_ecsrc_OnStartPi
- 0x100b0928 0x63 _zPHY_ecsrc_OnEndPi
- 0x100b098b 0x9b _zPHY_ecsrc_ReportOneFreq
- 0x100b0a26 0x7c _zPHY_ecsrc_ReportPreValue
- 0x100b0aa2 0x2f _zPHY_ecsrc_ReportInra
- 0x100b0ad1 0x57 _zPHY_ecsrc_DoReportIner
- 0x100b0b28 0x11 _zPHY_ecsrc_ReportInter
- 0x100b0b39 0x12 _zPHY_ecsrc_OneFreqModeWork
- 0x100b0b4b 0x1a _zPHY_ecsrc_OneFreqIntraWork
- 0x100b0b65 0x27 _zPHY_ecsrc_IntraSearchInLowSnr
- 0x100b0b8c 0x33 _zPHY_ecsrc_FixedStrongSearch
- 0x100b0bbf 0x8 _zPHY_ecsrc_GetFixedStrongSearchFlag
- 0x100b0bc7 0x30 _zPHY_ecsrc_NeedSearchInLowSnr
- 0x100b0bf7 0x25 _zPHY_ecsrc_NeedSearchInRA
- 0x100b0c1c 0x14 _zPHY_ecsrc_OneFreqInterWork
- 0x100b0c30 0x11 _zPHY_ecsrc_GerFreqNumPerDrx
- 0x100b0c41 0x3c _zPHY_ecsrc_NextInterFreqInDrx
- 0x100b0c7d 0x23 _zPHY_ecsrc_IntraWorkInDrx
- 0x100b0ca0 0x20 _zPHY_ecsrc_InterFinishInDrx
- 0x100b0cc0 0x35 _zPHY_ecsrc_RecordInterDoneInDrx
- 0x100b0cf5 0x65 _zPHY_ecsrc_InterSchedInitPerDrx
- 0x100b0d5a 0x9b _zPHY_ecsrc_GetIntraSearchTime
- 0x100b0df5 0x2e _zPHY_ecsrc_GetInterSearchTime
- 0x100b0e23 0x7f _zPHY_ecsrc_GetIntraMeasTime
- 0x100b0ea2 0xa1 _zPHY_ecsrc_GetInterMeasTime
- 0x100b0f43 0x4d _zPHY_ecsrc_GetIntraWorkTime
- 0x100b0f90 0x15 _zPHY_ecsrc_GetInterWorkTime
- 0x100b0fa5 0x69 _zEcsr_GetWorkTimeInCurDrx
- 0x100b100e 0x71 _zPHY_ecsrc_ChangeMeasMode
- 0x100b107f 0x36 _zPHY_ecsrc_IntraMeasStart
- 0x100b10b5 0x3 _zPHY_ecsrc_InterMeasStart
- 0x100b10b8 0x15 _zPHY_ecsrc_IntraSearchStart
- 0x100b10cd 0xd _zPHY_ecsrc_SetIntraWorkTime
- 0x100b10da 0x1e _zPHY_ecsrc_SetInterWorkTime
- 0x100b10f8 0x12 _zPHY_ecsrc_ServCellStart
- 0x100b110a 0x26 _zPHY_ecsrc_SearchInMeasConfig
- 0x100b1130 0x21 _zPHY_ecsrc_ReadIndexInSchedContext
- 0x100b1151 0x21 _zPHY_ecsrc_IntraFreqStart
- 0x100b1172 0x11c _zPHY_ecsrc_InterFreqStart
- 0x100b128e 0xb4 _zPHY_ecsrc_OneFreqStart
- 0x100b1342 0x26 _zPHY_ecsrc_NeedSchedInter
- 0x100b1368 0x1 _zPHY_ecsrc_BeforeInter
- 0x100b1369 0x15 _zPHY_ecsrc_BeforeOneFreq
- 0x100b137e 0x24 _zPHY_ecsrc_NeedInitial
- 0x100b13a2 0x49 _zPHY_ecsrc_ChangeMeasPeriodIdle
- 0x100b13eb 0x32 _zPHY_ecsrc_ReportNoInactiveTime
- 0x100b141d 0x7 _zPHY_ecsrc_NeedAdjustBndFrmCfo
- 0x100b1424 0x5e _zPHY_ecsrc_AdjustBndFrmCfo
- 0x100b1482 0x15 _zPHY_ecsrc_SetShortDrxState
- 0x100b1497 0x12 _zPHY_ecsrc_CfgRfcRxOffset
- 0x100b14a9 0x2b _zPHY_ecsrc_AdjustSrvTpu
- 0x100b14d4 0x7 _zPHY_ecsrc_BackupCFOFreqOffset
- 0x100b14db 0x8 _l1e_csrc_GetDrxCnt
- 0x100b14e3 0x3b _zPHY_ecsrc_DrxReStartSearchMeas
- 0x100b151e 0x2a _zPHY_ecsrc_ReadPrio
- 0x100b1548 0x85 _zPHY_ecsrc_WakeupPs
- 0x100b15cd 0x8 _L1e_csrc_GetCurCtx
- 0x100b15d5 0x8 _L1e_csrc_GetMeasBit
- 0x100b15dd 0x94 _L1e_csrc_TempRead
- 0x100b1671 0xd0 _L1e_ecsrc_UpdateBackBchBnd
- 0x100b1741 0xa _L1e_csrc_AtZepcgSetLowPower
- 0x100b174b 0x20 _L1e_csrc_AtZepcgSetPhyCfg
- 0x100b176b 0x6b _L1e_csrc_GetFreqOffset
- 0x100b17d6 0x29 _L1e_csrc_SetDisableAfcReloadFlag
- 0x100b17ff 0x15 _L1e_csrc_SetScanFailNum
- .text 0x100b1814 0x212 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_fsm.o)
- 0x100b1814 0x212 _zPHY_emc_ProPhyStateCtrl
- .text 0x100b1a26 0xb29 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_db.o)
- 0x100b1a26 0x7 _zPHY_ecsrc_SatAdd
- 0x100b1a2d 0x9 _zPHY_ecsrc_SatSub
- 0x100b1a36 0x18 _zPHY_ecsrc_CellDatabaseReset
- 0x100b1a4e 0x2b _zPHY_ecsrc_GetCellInfo
- 0x100b1a79 0x48 _zPHY_ecsrc_GetAddCell
- 0x100b1ac1 0x61 _zPHY_ecsrc_DeleteCell
- 0x100b1b22 0x4d _zPHY_ecsrc_DeleteOldCell
- 0x100b1b6f 0x69 _zPHY_ecsrc_DeleteAllCell
- 0x100b1bd8 0x4d _zPHY_ecsrc_DeleteNoCfgCell
- 0x100b1c25 0x1a _L1e_Csrc_IsServcell
- 0x100b1c3f 0x13 _L1e_Csrc_IsServcellEarfcn
- 0x100b1c52 0x42 _zPHY_ecsrc_FindCell
- 0x100b1c94 0x29 _zPHY_ecsrc_ClearOtherCell
- 0x100b1cbd 0x12 _zPHY_ecsrc_FindServCell
- 0x100b1ccf 0x4e _zPHY_ecsrc_CtrlICPWriteMeasPriority
- 0x100b1d1d 0x9e _zPHY_ecsrc_SearchAddCellToDatabase
- 0x100b1dbb 0x8d _zPHY_ecsrc_CtrlRefreshDataBase
- 0x100b1e48 0x54 _zPHY_ecsrc_CtrlUpdateBoundary
- 0x100b1e9c 0x49 _zPHY_ecsrc_AdjustCellAge
- 0x100b1ee5 0x3a _zPHY_ecsrc_CtrlGetStrongestCell
- 0x100b1f1f 0xc _zPHY_ecsrc_ScellDatabaseReset
- 0x100b1f2b 0x44 _zPHY_ecsrc_CtrlCellDatabaseAging
- 0x100b1f6f 0x2a _zPHY_ecsrc_ClearSearchNewCellFlag
- 0x100b1f99 0x2e _zPHY_ecsrc_ClearAppointCellFlag
- 0x100b1fc7 0x23 _zPHY_ecsrc_ClearValidCellFlag
- 0x100b1fea 0x22 _zEcsrc_FindFreq
- 0x100b200c 0x13 _zEcsrc_IsIcp
- 0x100b201f 0x40 _zEcsrc_GetMeasBand
- 0x100b205f 0x19 _zEcsrc_GetMeasTimes
- 0x100b2078 0x2c _zPHY_ecsrc_ClearFreqInfo
- 0x100b20a4 0x34 _zPHY_ecsrc_ClearNoCfgFreqInfo
- 0x100b20d8 0x1f _zPHY_ecsrc_FindFreqInfo
- 0x100b20f7 0x60 _zPHY_ecsrc_ExChangeFreqInfo
- 0x100b2157 0x9e _zPHY_ecsrc_SaveFreqInfo
- 0x100b21f5 0x4d _zPHY_ecsrc_ReadRsrpCaliInfo
- 0x100b2242 0x4a _zPHY_ecsrc_UpdateTimeOffset
- 0x100b228c 0x41 _zPHY_ecsrc_RecoverTimeOffset
- 0x100b22cd 0x48 _zPHY_ecsrc_ChangeTimeOffset
- 0x100b2315 0x23 _zPHY_ecsrc_ReadTimeOffset
- 0x100b2338 0x1e _zPHY_ecsrc_GetCellNum
- 0x100b2356 0xb _L1e_Csrc_UpdateServCell
- 0x100b2361 0x10 _L1e_Csrc_ServCellChange
- 0x100b2371 0xc _L1e_Csrc_ChangeNeiConfigFlag
- 0x100b237d 0x7e _zPHY_ecsrc_DealSrvBndFrmCfo
- 0x100b23fb 0x25 _L1e_csrc_SetMeasState
- 0x100b2420 0x87 _zPHY_ecsrc_GetMeasCell
- 0x100b24a7 0x4b _zPHY_ecsrc_GetMeasCellNum
- 0x100b24f2 0x12 _zPHY_ecsrc_GetFddBufferMode
- 0x100b2504 0x1e _zPHY_ecsrc_GetIndexInFreqMeasMode
- 0x100b2522 0x11 _zPHY_ecsrc_GetMeasAge
- 0x100b2533 0x1c _zPHY_ecsrc_GetFreqOffset
- .text 0x100b254f 0x2bfc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
- 0x100b254f 0xb _zPHY_ecsrc_CtrlShiftSlaveFunState
- 0x100b255a 0x14 _zPHY_ecsrc_CtrlShiftSlaveSynState
- 0x100b256e 0xa _zPHY_ecsrc_MulmSetRfWorkSet
- 0x100b2578 0x65 _zPHY_ecsrc_MulmCfgRFCModem7510
- 0x100b25dd 0x5f _zPHY_ecsrc_MulmRegRFStartClose
- 0x100b263c 0xf7 _zPHY_ecsrc_MulmIratIdlePeriodRepProcess7510
- 0x100b2733 0x44 _zEcsr_UpdateSiReadState
- 0x100b2777 0x35 _zPHY_ecsrc_MulmCtrlSetMode
- 0x100b27ac 0xa3 _zPHY_ecsrc_MulmSlaveReset
- 0x100b284f 0x14 _zPHY_ecsrc_MulmFreqListConfigProcess
- 0x100b2863 0x60 _L1e_Mulm_ReadSearchT
- 0x100b28c3 0x58 _L1e_Mulm_NeedSearch
- 0x100b291b 0x34 _L1e_Mulm_NeedMeas
- 0x100b294f 0x47 _zPHY_ecsrc_MulmIratMeasScheduleProcess
- 0x100b2996 0x3c _zPHY_ecsrc_MulmIratAddMeasReport
- 0x100b29d2 0x77 _zPHY_ecsrc_MulmMeasReset
- 0x100b2a49 0xe5 _zPHY_ecsrc_MulmIratMeasConfigProcess
- 0x100b2b2e 0x72 _zPHY_ecsrc_MulmReportFreqMeasResult
- 0x100b2ba0 0x5d _zPHY_ecsrc_MulmIratMeasResultHandle
- 0x100b2bfd 0x9 _zPHY_ecsrc_MulmIratResetMeasCnt
- 0x100b2c06 0x8d _zPHY_ecsrc_MulmIratMeasReportIntHandle
- 0x100b2c93 0xaf _zPHY_ecsrc_MulmIratMeasFilter
- 0x100b2d42 0x88 _zPHY_ecsrc_MulmIratFreqFilter
- 0x100b2dca 0x72 _zPHY_ecsrc_MulmIratUpdateMeasInd
- 0x100b2e3c 0x34 _zPHY_ecsrc_MulmIratUpdateFreqReport
- 0x100b2e70 0x40 _zPHY_ecsrc_MulmIratSetFilterFact
- 0x100b2eb0 0x2a _zPHY_ecsrc_MulmIratReadPrio
- 0x100b2eda 0x55 _zPHY_ecsrc_MulmIratSearchMeasureStartSchedule
- 0x100b2f2f 0x17 _zPHY_ecsrc_MulmSlaveCfgRfcMeas1Offset7510
- 0x100b2f46 0x37 _zPHY_ecsrc_MulmSlaveGapStartOffsetCfg7510
- 0x100b2f7d 0x43 _zPHY_ecsrc_MulmSlaveGapEndOffsetCfg7510
- 0x100b2fc0 0x36 _zPHY_ecsrc_MulmRegTpuSingleEvent
- 0x100b2ff6 0x63 _zPHY_ecsrc_MulmGetGapType
- 0x100b3059 0x28 _zPHY_ecsrc_MulmRegTpuEvent
- 0x100b3081 0xed _zPHY_ecsrc_MulmIratGapSchedFlow
- 0x100b316e 0x62 _zPHY_ecsrc_ReRegistGapConfigDelag
- 0x100b31d0 0x62 _zPHY_ecsrc_MulmIratGapSchedFlowProtect
- 0x100b3232 0x56 _zPHY_ecsrc_MulmBlackCellFilter
- 0x100b3288 0x60 _zPHY_ecsrs_MulmRemainTimeInGap
- 0x100b32e8 0x2d _zPHY_ecsrs_MulmProtectTimeBeforeGap
- 0x100b3315 0x1a _zPHY_ecsrc_MulmCalMeasTime
- 0x100b332f 0x5b _zPHY_ecsrc_MulmCalSearchTime
- 0x100b338a 0x104 _zPHY_ecsrc_MulmTpuCnf
- 0x100b348e 0x13 _zPHY_ecsrc_MulmCsr2TpuUpdateCounterCnfHandle
- 0x100b34a1 0x4a _zPHY_ecsrc_MulmSlavePlmnSearchStart
- 0x100b34eb 0x2a _zPHY_ecsrc_MulmSlavePlmnSearchFinHandle
- 0x100b3515 0x42 _zPHY_ecsrc_MulmSlavePlmnMeasureTimerIntHandle
- 0x100b3557 0x2e _zPHY_ecsrc_MulmSlavePlmnAbortCellSearchHandle
- 0x100b3585 0x45 _zPHY_ecsrs_MulmPlmnSib1InGap
- 0x100b35ca 0x45 _zPHY_ecsrc_MulmRegNotSynSubFrameInt
- 0x100b360f 0x2c _zPHY_ecsrc_MulmRegCsrmSfInt
- 0x100b363b 0xaa _zPHY_ecsrc_MulmIratGapStartTpuIntHandle
- 0x100b36e5 0x20 _zPHY_ecsrc_MulmUnRegistSearchMeasInt
- 0x100b3705 0x42 _zPHY_ecsrc_MulmIratGapEndTpuIntHandle
- 0x100b3747 0x50 _zPHY_ecsrc_MulmSlaveAbortGapProtectTimerEnable
- 0x100b3797 0x48 _zPHY_ecsrc_MulmIratMeasDoneHandle
- 0x100b37df 0x6e _zPHY_ecsrc_MulmIratAbortGapHandle
- 0x100b384d 0x68 _zPHY_ecsrc_MulmIratAbortGapProtectTimerHandle
- 0x100b38b5 0x97 _zPHY_ecsrs_MulmIratGapPositionCheck
- 0x100b394c 0x27 _zPHY_ecsrs_MulmGapCoverTime
- 0x100b3973 0x42 _zPHY_ecsrm_MulmPbchStartCheck
- 0x100b39b5 0x27 _zPHY_ecsrs_MulmEnableRfcEventTable
- 0x100b39dc 0x26 _zPHY_ecsrs_Mulm6MSRfcMeas1GapOffsetCfg
- 0x100b3a02 0x64 _zPHY_ecsrs_MulmRfOpenNo
- 0x100b3a66 0x49 _zPHY_ecsrs_MulmConfigSynState
- 0x100b3aaf 0x56 _zPHY_ecsrs_MulmEnableRF
- 0x100b3b05 0x45 _zPHY_emc_MulmCsrRfStartDeal
- 0x100b3b4a 0x62 _zPHY_emc_MulmCsrRfEndDeal
- 0x100b3bac 0x20 _zPHY_emc_DealRFCloseEvent
- 0x100b3bcc 0x2d _zPHY_ecsrc_CtrlMulmDbAging
- 0x100b3bf9 0xf _zPHY_ecsrc_CtrlSetMulmSlaveSearchMeasAgeInfor
- 0x100b3c08 0x97 _zPHY_ecsrc_CtrlMulmRefreshDataBase
- 0x100b3c9f 0x50 _zPHY_ecsrs_MulmTpuAdjCheckTime
- 0x100b3cef 0x2f _zPHY_ecsrs_MulmIcpPssBoundryAdj
- 0x100b3d1e 0x1a _zPHY_ecsrs_MulmPssTpuCnf
- 0x100b3d38 0x46 _zPHY_ecsrs_MulmIsPssWorkTime
- 0x100b3d7e 0xa0 _zPHY_ecsrs_MulmGetPssHwStartTime
- 0x100b3e1e 0x53 _zPHY_ecsrs_MulmPssCfg
- 0x100b3e71 0xb _zPHY_ecsrs_MulmPssConfig
- 0x100b3e7c 0x16 _zPHY_ecsrs_MulmPssGapCoverTime
- 0x100b3e92 0x68 _zPHY_ecsrc_MulmGetValidCellFrameBoundry7510
- 0x100b3efa 0x3f _zPHY_ecsrc_MulmTpuAdjPro
- 0x100b3f39 0x27 _zPHY_ecsrc_MulmBoundryAdj
- 0x100b3f60 0x7f _zPHY_ecsrs_MulmCheckTpuAdj
- 0x100b3fdf 0x28 _zPHY_ecsrs_MulmStartTpuAdj
- 0x100b4007 0xf3 _zPHY_ecsrc_MulmIratSearchStartSchedule7510
- 0x100b40fa 0x56 _zPHY_emc_MulmSlaveMeasureReportProtect
- 0x100b4150 0x190 _zPHY_emc_MulmSlaveMeasureFlow
- 0x100b42e0 0x7 _zPHY_ecsrs_MulmIratFSPssGapPositionCheck
- 0x100b42e7 0x17 _zPHY_ecsrs_MulmIratCheckGapTime
- 0x100b42fe 0x3d _zPHY_ecsrs_MulmIratPssTimeCheck
- 0x100b433b 0x4b _zPHY_ecsrs_MulmIratSssGapPositionCheck
- 0x100b4386 0x39 _zPHY_ecsrs_MulmAgcStable
- 0x100b43bf 0x15 _L1e_mulm_CfoAccNum
- 0x100b43d4 0x87 _zPHY_ecsrs_MulmCfoConfig
- 0x100b445b 0x1e _zPHY_ecsrs_MulmSssCfg
- 0x100b4479 0x8b _zPHY_ecsrs_MulmIsTddSssWorkTime
- 0x100b4504 0x18 _zPHY_ecsrs_MulmStartICSPSubFrameInt
- 0x100b451c 0x13 _zPHY_ecsrs_MulmStartSynSearchSubFrameInt
- 0x100b452f 0x40 _zPHY_ecsrs_MulmGapCoverTime7510
- 0x100b456f 0x136 _zPHY_ecsrs_MulmIsFddSssWorkTime
- 0x100b46a5 0x1d _zPHY_ecsrs_MulmGetMeasBaseTime
- 0x100b46c2 0x154 _zPHY_ecsrs_MulmCfoCheckTime
- 0x100b4816 0xa9 _zPHY_ecsrs_MulmIsValidTime
- 0x100b48bf 0xfd _zPHY_ecsrs_MulmCheckOpenTime
- 0x100b49bc 0xb3 _zPHY_ecsrm_MulmBuffCheckOpenTimePeriod
- 0x100b4a6f 0x5a _zPHY_ecsrs_MulmGapCoverCheck
- 0x100b4ac9 0x47 _zPHY_ecsrs_MulmGapCoverBufferCheck
- 0x100b4b10 0x14 _zPHY_ecsrs_MulmIsShortGap
- 0x100b4b24 0x16 _zPHY_ecsrs_MulmGetFreqIndex
- 0x100b4b3a 0x2e _zPHY_ecsrc_MulmIratClearPreFilter
- 0x100b4b68 0x26 _zPHY_ecsrs_AbsModSub
- 0x100b4b8e 0xc _zPHY_ecsrs_MulmCsBefore
- 0x100b4b9a 0x26 _zPHY_ecsrs_MulmCsNeedCs
- 0x100b4bc0 0xc _zPHY_ecsrs_MulmCsNeedAgc
- 0x100b4bcc 0x37 _zPHY_ecsrs_MulmCsBeforeAgc
- 0x100b4c03 0xb _zPHY_ecsrs_MulmCsIsOnAgc
- 0x100b4c0e 0x1c _zPHY_ecsrs_MulmCsAgcProc
- 0x100b4c2a 0x8 _zPHY_ecsrs_MulmCsAgcProcEnd
- 0x100b4c32 0xb _zPHY_ecsrs_MulmCsNeedPss
- 0x100b4c3d 0x2d _zPHY_ecsrs_MulmCsBeforePss
- 0x100b4c6a 0x18 _zPHY_ecsrs_MulmCsIsOnPss
- 0x100b4c82 0x41 _zPHY_ecsrs_MulmCsPssProc
- 0x100b4cc3 0x43 _zPHY_ecsrs_MulmCsPssProcEnd
- 0x100b4d06 0x14 _zPHY_ecsrs_MulmCsNeedTpuAdj1
- 0x100b4d1a 0xc _zPHY_ecsrs_MulmCsNeedTpuAdj
- 0x100b4d26 0xc _zPHY_ecsrs_MulmCsTpuAdjProc
- 0x100b4d32 0x1a _zPHY_ecsrs_MulmCsTpuAdjProc2
- 0x100b4d4c 0xe _zPHY_ecsrs_MulmCsTpuCheck
- 0x100b4d5a 0xc _zPHY_ecsrs_MulmCsNeedCfo
- 0x100b4d66 0x15 _zPHY_ecsrs_MulmCsBeforeCfo
- 0x100b4d7b 0x25 _zPHY_ecsrs_MulmCsBeforeCfoOnce
- 0x100b4da0 0x20 _zPHY_ecsrs_MulmCsIsOnCfo
- 0x100b4dc0 0x1d _zPHY_ecsrs_MulmCsNeedMoreCfo
- 0x100b4ddd 0x30 _zPHY_ecsrs_MulmCsCfoProc
- 0x100b4e0d 0x4a _zPHY_ecsrs_MulmCsCfoOnceProcEnd
- 0x100b4e57 0x8 _zPHY_ecsrs_MulmCsCfoProcEnd
- 0x100b4e5f 0x31 _zPHY_ecsrs_MulmLteCordicConfig
- 0x100b4e90 0x12 _zPHY_ecsrs_MulmGetLteCordicValue
- 0x100b4ea2 0xc _zPHY_ecsr_MulmCordicAdjust
- 0x100b4eae 0x5a _zPHY_ecsr_MulmToLteCfo
- 0x100b4f08 0x8 _zPHY_ecsr_MulmReadCordicValue
- 0x100b4f10 0x8 _zPHY_ecsr_MulmWriteCordicValue
- 0x100b4f18 0xc _zPHY_ecsrs_MulmCsNeedSss
- 0x100b4f24 0x28 _zPHY_ecsrs_MulmCsBeforeSss
- 0x100b4f4c 0x29 _zPHY_ecsrs_MulmCsIsOnSss
- 0x100b4f75 0x18 _zPHY_ecsrs_MulmIsSssWorkTime
- 0x100b4f8d 0x47 _zPHY_ecsrs_MulmCsSssProc
- 0x100b4fd4 0x50 _zPHY_ecsrs_MulmCsSssProcEnd
- 0x100b5024 0x75 _zPHY_ecsrs_MulmCsProEnd
- 0x100b5099 0x8 _zPHY_ecsrc_MulmSetRfState
- 0x100b50a1 0x25 _zPHY_ecsrc_MulmSchedCheck
- 0x100b50c6 0x15 _zPHY_ecsrs_MulmCheckReadTime
- 0x100b50db 0x66 _zPHY_ecsrs_MulmIsSssSchedSubFrm
- 0x100b5141 0xa _zPHY_ecsrs_Wait
- .text 0x100b514b 0xf1a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
- 0x100b514b 0x1a _zPHY_ecsrc_InitCellSearchProc
- 0x100b5165 0x1c _zPHY_ecsrc_IdleCellSearchProc
- 0x100b5181 0x4d _zPHY_ecsrc_SetCellSearchCnf
- 0x100b51ce 0x7c _zPHY_ecsrc_InitAppointedCS
- 0x100b524a 0x16 _zPHY_ecsrc_InitNotAppointedCS
- 0x100b5260 0x46 _zPHY_ecsrc_CtrlSssUpdateProcess
- 0x100b52a6 0x42 _zPHY_ecsrc_ReSearchOrReportCell
- 0x100b52e8 0x37 _zPHY_ecsrc_SetInitMeasTime
- 0x100b531f 0x6b _zPHY_ecsrc_CtrlICPTimeEvent
- 0x100b538a 0x3f _zPHY_ecsrc_CtrlICPTpuAdjust
- 0x100b53c9 0xaf _zPHY_ecsrc_CtrlICPMeasTimeEvent
- 0x100b5478 0x3c _zPHY_ecsrc_SortCellSearchCnf
- 0x100b54b4 0x4a _zPHY_ecsrc_SetReportCellList
- 0x100b54fe 0x87 _zPHY_ecsrc_CtrlICPReportResult
- 0x100b5585 0xc2 _zPHY_ecsrc_CtrlIcpBchHandle
- 0x100b5647 0x4f _zPHY_ecsrc_CtrlBchDecodeEvent
- 0x100b5696 0x48 _zPHY_ecsrc_CtrlIcpReportNoCell
- 0x100b56de 0x62 _zPHY_ecsrc_CtrlIcpTimeEndEvent
- 0x100b5740 0x29 _zPHY_ecsrc_CfgSynTable
- 0x100b5769 0x36 _zPHY_ecsrc_ReConstructRxPara
- 0x100b579f 0x2d _zPHY_ecsrc_ConfirmRxPara
- 0x100b57cc 0x35 _zPHY_ecsrc_PlmnBackupSrvCell
- 0x100b5801 0x86 _zPHY_ecsrc_PlmnResumeDlRfcEnableEvent
- 0x100b5887 0xcc _zPHY_ecsrc_PlmnPhyResultReport
- 0x100b5953 0x54 _zPHY_ecsrc_FreqScanResultReportHandle
- 0x100b59a7 0x43 _zPHY_ecsrc_PlmnResumeSrvCellTPU
- 0x100b59ea 0x3b _zPHY_ecsrc_PlmnCurTime2PiTimeDistance
- 0x100b5a25 0x10 _zPHY_ecsrc_PlmnHasEnoughTime
- 0x100b5a35 0x30 _zPHY_ecsrc_PlmnProcessPeriodicalTpuIntIn
- 0x100b5a65 0x24 _zPHY_ecsrc_PlmnResumeSrvCellNew
- 0x100b5a89 0x31 _zPHY_ecsrc_PlmnSearchResultHandleNew
- 0x100b5aba 0x37 _zPHY_ecsrc_PlmnFreqScanReqPro
- 0x100b5af1 0x15 _zPHY_ecsrc_PlmnCellSearchReqPro
- 0x100b5b06 0x72 _zPHY_ecsrc_PlmnPeriodTpuInPro
- 0x100b5b78 0x33 _L1e_csrc_CalcProTime
- 0x100b5bab 0x1d _zPHY_ecsrc_PlmnGetPhaseMinTime
- 0x100b5bc8 0xa2 _zPHY_ecsrc_PlmnBackupAfc
- 0x100b5c6a 0x1c _zPHY_ecsrc_PlmnResumeAgcAFc
- 0x100b5c86 0xf _zPHY_ecsrc_PlmnPhasePro
- 0x100b5c95 0x4a _zPHY_ecsrc_SearchPhaseCheck
- 0x100b5cdf 0xa _zPHY_ecsrc_PlmnReadPhase
- 0x100b5ce9 0xf _zPHY_ecsrc_PlmnPhaseShift
- 0x100b5cf8 0x3c _zPHY_ecsrc_PlmnPhaseContinue
- 0x100b5d34 0x28 _zPHY_ecsrc_SearchDone
- 0x100b5d5c 0x38 _zPHY_ecsrc_SendCellSearchReq
- 0x100b5d94 0x9 _zPHY_ecsrc_RestartCellSearch
- 0x100b5d9d 0xd4 _zPHY_ecsrc_CtrlAbortICPProcess
- 0x100b5e71 0x35 _zPHY_ecsrc_BchCellInfoBak
- 0x100b5ea6 0x134 _l1e_SchedCsrcGetOverlapInfo
- 0x100b5fda 0x53 _zPHY_ecsrc_ProWriteBch2CsrDb
- 0x100b602d 0x38 _zPHY_ecsrc_ProBackBchInfo
- .text 0x100b6065 0x379 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
- 0x100b6065 0x35 _CheckThread
- 0x100b609a 0x6b _NextStep
- 0x100b6105 0x33 _RunProc
- 0x100b6138 0x12 _RunFun0
- 0x100b614a 0x14 _RunFun0P1
- 0x100b615e 0xc _RunFun1
- 0x100b616a 0x15 _RunOpt
- 0x100b617f 0x4c _RunWhile
- 0x100b61cb 0x27 _RunEnd
- 0x100b61f2 0x1c _RunDo
- 0x100b620e 0x43 _RunWhile1
- 0x100b6251 0x15 _RunLoop0
- 0x100b6266 0x15 _RunLoop1
- 0x100b627b 0x25 _RunReturnIf
- 0x100b62a0 0x8b _DispatchStep
- 0x100b632b 0x26 _RunSync
- 0x100b6351 0x4c _EventHandlerOnce
- 0x100b639d 0x16 _EventHandler
- 0x100b63b3 0x2b _StartProc
- .text 0x100b63de 0x1ff T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
- 0x100b63de 0xc _L1e_SchedMbmsInit
- 0x100b63ea 0x48 _L1e_SchedMbmsProcMsg
- 0x100b6432 0x20 _L1e_SchedMbmsGenMbsfnSfBmp
- 0x100b6452 0xe3 _L1e_SchedMbmsGenAllocSfBmp
- 0x100b6535 0xd _L1e_SchedMbmsGetNextTimeInfo
- 0x100b6542 0x31 _L1e_SchedMbmsProcMchRecv
- 0x100b6573 0xb _L1e_SchedMbmsGetMbsfnInd
- 0x100b657e 0xb _L1e_SchedMbmsSetMbsfnFlag
- 0x100b6589 0xb _L1e_SchedMbmsSetMbmsFlag
- 0x100b6594 0xd _L1e_SchedMbmsGetMbsfnFlag
- 0x100b65a1 0xf _L1e_SchedMbmsGetMbmsFlag
- 0x100b65b0 0x2 _L1e_SchedMBmsGetMbsfnAllocNum
- 0x100b65b2 0xd _L1e_SchedMbmsGetAreaIndex
- 0x100b65bf 0xd _L1e_SchedMbmsGetNonMbsfnLen
- 0x100b65cc 0x11 _L1e_SchedMBmsGetConfigNum
- .text 0x100b65dd 0x141c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
- 0x100b65dd 0x44 _zPHY_DrxPreSyncStartCtrl
- 0x100b6621 0x1f1 _zPHY_emc_ProDrxSchedFlow
- 0x100b6812 0x97 _zPHY_emc_DrxInactivityTimerCtrl
- 0x100b68a9 0x73 _zPHY_emc_DrxOnDurationTimerCtrl
- 0x100b691c 0x128 _zPHY_emc_DrxRttTimerAndDlHarqRetranTimerCtrl
- 0x100b6a44 0xf9 _zPHY_emc_DrxUlHarqCtrl
- 0x100b6b3d 0x31 _zPHY_emc_ProDrxTpuEventSchedFlow
- 0x100b6b6e 0x88 _zPHY_emc_DrxCalcOndurationTimerStartTime
- 0x100b6bf6 0x64 _zPHY_emc_ProDrxCallBackFunction
- 0x100b6c5a 0x62 _zPHY_emc_RegOndurStartEvent
- 0x100b6cbc 0x9e _zPHY_emc_RegShortDrxCycleEvent
- 0x100b6d5a 0x64 _zPHY_emc_CurSubFrDRXStateCtrl
- 0x100b6dbe 0x1f _zPHY_emc_DRXCompare2Time
- 0x100b6ddd 0x65 _zPHY_emc_OnDurationPre2SubFrm
- 0x100b6e42 0x41 _zPHY_emc_InactivityPre2SubFrm
- 0x100b6e83 0x9b _zPHY_emc_DlHarqPre2SubFrm
- 0x100b6f1e 0x89 _zPHY_emc_UlHarqPhichPre2SubFrm
- 0x100b6fa7 0x63 _zPHY_emc_Next2SubFrameDrxStateCtrl
- 0x100b700a 0x93 _zPHY_emc_ProDrxInitial
- 0x100b709d 0xb _zPHY_emc_ChePwrCtrlFlg
- 0x100b70a8 0x90 _Ltel1_GetConnNearestGap
- 0x100b7138 0x28d _zPHY_emc_DrxPresyncCalc
- 0x100b73c5 0x4e _zPHY_emc_DrxStateCtrl
- 0x100b7413 0xaf _zPHY_emc_DrxCsi_OpenRXCtrl
- 0x100b74c2 0xa1 _zPHY_emc_DRXProcLpCtrl
- 0x100b7563 0x15a _zPHY_emc_DrxSpsLpCtrl
- 0x100b76bd 0x23 _zPHY_emc_GetDrxCloseRfState
- 0x100b76e0 0x162 _zPHY_emc_DRXCalOpenRFTime
- 0x100b7842 0x84 _zPHY_emc_DRXSleepJudge
- 0x100b78c6 0x75 _zPHY_emc_DrxParallelSleepCtrl
- 0x100b793b 0x9d _zPHY_emc_DrxParallelFlowLog
- 0x100b79d8 0x21 _zPHY_emc_DrxParallelFlowCtrl
- .text 0x100b79f9 0x3f8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
- 0x100b79f9 0x7 _zPHY_emc_ProRadioLink_GetFIUpdateInd
- 0x100b7a00 0x7 _zPHY_emc_ProRadioLink_SetFIUpdateInd
- 0x100b7a07 0x4e _zPHY_emc_ProRadioLink_ParaGetInDrx
- 0x100b7a55 0x1e _zPHY_emc_ProRadioLink_THInit
- 0x100b7a73 0x28 _zPHY_emc_ProRadioLink_THFilterInFI
- 0x100b7a9b 0x60 _zPHY_emc_ProRadioLink_GetFinalTH
- 0x100b7afb 0x52 _zPHY_emc_ProRadioLink_DrxFilter
- 0x100b7b4d 0xa2 _zPHY_emc_ProRadioLink_DrxFlow
- 0x100b7bef 0x60 _zPHY_emc_ProRadioLink_NoDrxFilter
- 0x100b7c4f 0x45 _zPHY_emc_ProRadioLink_StateSwitch
- 0x100b7c94 0xb7 _zPHY_emc_ProRadioLink_MainPro
- 0x100b7d4b 0xa6 _zPHY_emc_ProRadioLinkFlow
- .text 0x100b7df1 0x2db3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
- 0x100b7df1 0x40 _zPHY_amt_Lte_PrintMsgLog
- 0x100b7e31 0x4c _zPHY_AMT_Rfc_WriteRfFrontReg
- 0x100b7e7d 0x66 _zPHY_AMT_erfc_SetCurrentBandAntGPIO
- 0x100b7ee3 0xc1 _zPHY_AMT_erfc_SetCurrentBandPaModeGPIO
- 0x100b7fa4 0x17 _zPHY_AMT_RFC_110_RxOn
- 0x100b7fbb 0x16 _zPHY_AMT_RFC_110_RxOff
- 0x100b7fd1 0x17 _zPHY_AMT_RFC_110_TxOn
- 0x100b7fe8 0x16 _zPHY_AMT_RFC_110_TxOff
- 0x100b7ffe 0x16 _zPHY_AMT_RFC_120_RxOn
- 0x100b8014 0x16 _zPHY_AMT_RFC_120_RxOff
- 0x100b802a 0x16 _zPHY_AMT_RFC_120_TxOn
- 0x100b8040 0x16 _zPHY_AMT_RFC_120_TxOff
- 0x100b8056 0x17 _zPHY_AMT_RFC_RXENABLE_On
- 0x100b806d 0x16 _zPHY_AMT_RFC_RXENABLE_Off
- 0x100b8083 0x17 _zPHY_AMT_RFC_TXENABLE_On
- 0x100b809a 0x16 _zPHY_AMT_RFC_TXENABLE_Off
- 0x100b80b0 0xf _zPHY_AMT_RFC_110_AfcSet
- 0x100b80bf 0x1 _zPHY_AMT_RFC_110_Xo_AfcSet
- 0x100b80c0 0x22 _zPHY_AMT_RFC_120_DCIQSet
- 0x100b80e2 0x42 _zPHY_AMT_RFC_110_TempDacGet
- 0x100b8124 0x42 _zPHY_AMT_RFC_110_Xo_TempDacGet
- 0x100b8166 0x1d _zPHY_AMT_RFC_110_BandWidthModeGet
- 0x100b8183 0xa1 _zPHY_AMT_RFC_110_TxFreqSet
- 0x100b8224 0x35 _zPHY_AMT_RFC_110_RegTxCfg
- 0x100b8259 0x24 _zPHY_AMT_RFC_120_RegTxCfg
- 0x100b827d 0x36 _zPHY_AMT_RFC_110_RegRxCfg
- 0x100b82b3 0x30 _zPHY_AMT_RFC_120_RegRxCfg
- 0x100b82e3 0x28 _zPHY_AMT_RFC_ZTERF_TxApcSet
- 0x100b830b 0x33 _zPHY_AMT_RFC_ZTERF_Tx2Idle
- 0x100b833e 0x33 _zPHY_AMT_RFC_ZTERF_Rx2Idle
- 0x100b8371 0x70 _zPHY_AMT_RFC_ZTERF_ToTx
- 0x100b83e1 0x70 _zPHY_AMT_RFC_ZTERF_ToRx
- 0x100b8451 0x13 _zPHY_AMT_RFC_ZTERF_ToIdle
- 0x100b8464 0xd _zPHY_amt_Lte_GetCarrierMode
- 0x100b8471 0x1f _zPHY_amt_Lte_SetCarrierMode
- 0x100b8490 0xd8 _zPHY_amt_Lte_ChangeMode
- 0x100b8568 0x15 _zPHY_amt_Lte_TxParaUpdate
- 0x100b857d 0xc2 _zPHY_amt_Lte_ServCellFreqUpdate
- 0x100b863f 0x134 _zPHY_amt_Lte_CellSyncProc
- 0x100b8773 0xd1 _zPHY_amt_Lte_MprDeterm
- 0x100b8844 0xa8 _zPHY_amt_Lte_RfcTxDataBaseSet
- 0x100b88ec 0x48 _zPHY_amt_Lte_FDTTransTxVgaCtrl
- 0x100b8934 0x226 _zPHY_amt_Lte_FDT_PAVGAVOL_Update
- 0x100b8b5a 0x1f _zPHY_amt_Lte_FDTTxOffsetSet
- 0x100b8b79 0x12e _zPHY_amt_Lte_FDTRfcDataBaseSet
- 0x100b8ca7 0x1c _zPHY_amt_Lte_FDTRfcDataBaseClear
- 0x100b8cc3 0xe _zPHY_amt_Lte_FDTGetAgcGain
- 0x100b8cd1 0x7c _zPHY_amt_Lte_FDTSaveAgcGain
- 0x100b8d4d 0xf6 _zPHY_amt_Lte_FDTControl
- 0x100b8e43 0x2 _zPHY_amt_Lte_FDTGetAGC
- 0x100b8e45 0xb1 _zPHY_amt_Lte_FDTStart
- 0x100b8ef6 0x12 _zPHY_amt_Lte_FDTCellSyncProc
- 0x100b8f08 0x20 _zPHY_amt_Lte_NSTCellSyncProc
- 0x100b8f28 0x37 _zPHY_amt_Lte_NSTCellSyncSuccessRsp
- 0x100b8f5f 0x43 _zPHY_amt_Lte_NSTStartBler
- 0x100b8fa2 0xed _zPHY_amt_Lte_NSTGetBler
- 0x100b908f 0x32 _zPHY_amt_Lte_NSTStart
- 0x100b90c1 0x22 _zPHY_amt_Lte_NSTCirCfoStop
- 0x100b90e3 0x39 _zPHY_amt_Lte_NSTChangeFreq
- 0x100b911c 0x15b _zPHY_amt_Lte_NSTControl
- 0x100b9277 0x13 _zPHY_amt_Lte_FSTCellSyncProc
- 0x100b928a 0x89 _zPHY_amt_Lte_FSTStart
- 0x100b9313 0xc9 _zPHY_amt_Lte_FSTRfcDataBaseSet
- 0x100b93dc 0xda _zPHY_amt_Lte_FSTPowerUpdate
- 0x100b94b6 0xc0 _zPHY_amt_Lte_FSTSaveBlerAndRsrp
- 0x100b9576 0xf6 _zPHY_amt_Lte_FSTControl
- 0x100b966c 0x29 _zPHY_amt_Lte_Control
- 0x100b9695 0x294 _zPHY_amt_Lte_Tx_Init_Power
- 0x100b9929 0x1a4 _zPHY_amt_Lte_Tx_Init_RFC
- 0x100b9acd 0x7a _zPHY_amt_Lte_Tx_Init_MC
- 0x100b9b47 0x7a _zPHY_amt_Lte_Tx_Init_MC_Power
- 0x100b9bc1 0x6e _zPHY_amt_Lte_Close_Rfc
- 0x100b9c2f 0x51 _zPHY_amt_Lte_Tx_Close_MC
- 0x100b9c80 0x3c _zPHY_amt_Lte_TxFreq_RFC
- 0x100b9cbc 0x1d _zPHY_amt_Lte_TxPaMode_RFC
- 0x100b9cd9 0x4c _zPHY_amt_Lte_TxAPC_RFC
- 0x100b9d25 0x3a _zPHY_amt_Lte_AFC_RFC
- 0x100b9d5f 0x38 _zPHY_amt_Lte_XO_AFC_RFC
- 0x100b9d97 0x152 _zPHY_amt_Lte_Rx_Init_RFC
- 0x100b9ee9 0x1a _zPHY_amt_Lte_SetSyncTimer
- 0x100b9f03 0x4f _zPHY_amt_Lte_Cell_Search
- 0x100b9f52 0xa3 _zPHY_amt_Lte_CommMsg_Stub
- 0x100b9ff5 0x3d _zPHY_amt_Lte_CommMsg_Send
- 0x100ba032 0x19f _zPHY_amt_Lte_DediMsg_Stub
- 0x100ba1d1 0x33 _zPHY_amt_Lte_DediMsg_Send
- 0x100ba204 0x26b _zPHY_amt_Lte_Sync_Process
- 0x100ba46f 0x73 _zPHY_amt_Lte_Rx_Init_MC
- 0x100ba4e2 0x70 _zPHY_amt_Lte_Rx_Close_MC
- 0x100ba552 0x1b _zPHY_amt_Lte_RxFreq_RFC
- 0x100ba56d 0x2 _zPHY_amt_Lte_RxLNAMode_RFC
- 0x100ba56f 0x2 _zPHY_amt_Lte_RxVGA_RFC
- 0x100ba571 0x43 _zPHY_amt_Lte_Get_Rsrp
- 0x100ba5b4 0xe _zPHY_amt_Lte_Get_TempDAC
- 0x100ba5c2 0xe _zPHY_amt_Lte_Get_Xo_TempDAC
- 0x100ba5d0 0xe _zPHY_amt_Lte_Set_AfcData
- 0x100ba5de 0x25 _zPHY_amt_Lte_Tx_DcOffset
- 0x100ba603 0xbc _zPHY_amt_Lte_CellSearchResult
- 0x100ba6bf 0x4e _zPHY_amt_Lte_CalcServCellAntAMT
- 0x100ba70d 0x49 _zPHY_amt_Lte_UpCellSearchResult
- 0x100ba756 0xf5 _zPHY_amt_Lte_RxAlways_Init
- 0x100ba84b 0xa _zPHY_amt_Lte_RxAlways_Close
- 0x100ba855 0xe _zPHY_amt_Lte_RxAlwaysOpen_GetAgc
- 0x100ba863 0x76 _zPHY_amt_Lte_RxAlwaysOpen
- 0x100ba8d9 0x2 _zPHY_amt_Lte_RxCwControl
- 0x100ba8db 0x2c9 _zPHY_amtTool_ThreadEntry
- .text 0x100baba4 0x1b39 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
- 0x100baba4 0x4a _zPHY_erapc_InitialProc
- 0x100babee 0x33 _zPHY_erapc_RaParamReset
- 0x100bac21 0xa4 _zPHY_erapc_BiProc
- 0x100bacc5 0x106 _zPHY_erapc_RaResourceSelect
- 0x100badcb 0x164 _zPHY_erapc_RaResourceSelectFDD
- 0x100baf2f 0x12d _zPHY_erapc_RaResourceSelectTDD
- 0x100bb05c 0x48 _zPHY_erapc_PreambleGroupSelect
- 0x100bb0a4 0x4f _zPHY_erapc_PreambleSelect
- 0x100bb0f3 0x1d0 _zPHY_erapc_PreamCycShiftCalc
- 0x100bb2c3 0x12b _zPHY_erapc_KValueCalc
- 0x100bb3ee 0xb8 _zPHY_erapc_PreambleTransPower
- 0x100bb4a6 0x6f _zPHY_erapc_PcmaxCalc
- 0x100bb515 0x12a _zPHY_erapc_RarMacPduDecode
- 0x100bb63f 0x9c _zPHY_erapc_TpuEventDelete
- 0x100bb6db 0x42 _zPHY_erapc_RntiDelete
- 0x100bb71d 0x4b _zPHY_erapc_SetRapcState
- 0x100bb768 0x43 _zPHY_erapc_PreamFormatDetermFDD
- 0x100bb7ab 0x3e _zPHY_erapc_PreamFormatDetermTDD
- 0x100bb7e9 0xff _zPHY_erapc_ResrConfigDetermFDD
- 0x100bb8e8 0x1e1 _zPHY_erapc_ResrConfigDetermTDD
- 0x100bbac9 0x8f _zPHY_erapc_NextAvailSFDetermTDD
- 0x100bbb58 0x67 _zPHY_erapc_NPrbRaCalcTDD
- 0x100bbbbf 0x21 _zPHY_erapc_RandomNumGenerate
- 0x100bbbe0 0xdd _zPHY_erapc_RaRntiCalc
- 0x100bbcbd 0x8f _zPHY_erapc_SendRaCnfMsg
- 0x100bbd4c 0x152 _zPHY_erapc_ConfigSAD
- 0x100bbe9e 0x235 _zPHY_erapc_PreamTransPro
- 0x100bc0d3 0x7a _zPHY_erapc_RaRetransProc
- 0x100bc14d 0x150 _zPHY_erapc_RarDetectedProc
- 0x100bc29d 0x7b _zPHY_erapc_CRntiMsg4Proc
- 0x100bc318 0x79 _zPHY_erapc_CcchSduMsg4Proc
- 0x100bc391 0x55 _zPHY_erapc_AbortRaProc
- 0x100bc3e6 0x63 _zPHY_erapc_ContenStopProc
- 0x100bc449 0x3d _zPHY_erapc_GetRapcTpuEventFlag
- 0x100bc486 0x37 _zPHY_erapc_SetRapcTpuEventFlag
- 0x100bc4bd 0xae _zPHY_erapc_Format4PrachNumCalc
- 0x100bc56b 0xda _zPHY_erapc_GapConflictIndicate
- 0x100bc645 0x94 _zPHY_erapc_Format4PrachNumCalc_ForUla
- 0x100bc6d9 0x4 _zPHY_erapc_PrachAntennaSelect
- .text 0x100bc6dd 0x5eb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
- 0x100bc6dd 0x283 _zPHY_emc_ProHandover2Module
- 0x100bc960 0x35d _zPHY_emc_ProHandoverFlow
- 0x100bccbd 0xb _zPHY_emc_InHandoverProc
- .text 0x100bccc8 0xc86 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
- 0x100bccc8 0x1f9 _zPHY_emc_ProPagingFlow
- 0x100bcec1 0xf8 _zPHY_L1e_DcxoDelayProc
- 0x100bcfb9 0x8 _zPHY_L1e_GetPreSyncValidInd
- 0x100bcfc1 0x8 _zPHY_L1e_SetPreSyncValidInd
- 0x100bcfc9 0x7 _zPHY_L1e_GetPreSyncAccNum
- 0x100bcfd0 0x39 _zPHY_emc_RegPageCallEvent
- 0x100bd009 0x198 _zPHY_emc_CalPagingParam
- 0x100bd1a1 0x103 _zPHY_emc_ProPagingCallBackFunction
- 0x100bd2a4 0x31 _zPHY_emc_NxtSubFrmIsPage
- 0x100bd2d5 0x16 _zPHY_emc_DrxPoLpCtrl
- 0x100bd2eb 0x53 _L1e_Page_ReUpdatePoEvt
- 0x100bd33e 0xd5 _L1e_SchedGetPreSyncSchdInfo
- 0x100bd413 0x33 _L1e_SchedPreSyncGetIdleWorkTimer
- 0x100bd446 0x8 _L1e_SchedReturnPreSyncWorkTime
- 0x100bd44e 0x29 _L1e_SchedPreSyncGetAgcWorkTimer
- 0x100bd477 0x1b _L1e_SchedPreSyncSetState
- 0x100bd492 0x7 _L1e_SchedPreSyncGetState
- 0x100bd499 0xc _L1e_SchedPreSyncSetWorkCnt
- 0x100bd4a5 0x12 _L1e_SchedPreSyncIsWorkSn
- 0x100bd4b7 0x12 _L1e_SchedPreSyncIsWorkInd
- 0x100bd4c9 0x17 _L1e_SchedPreSyncGetRfOpenInd
- 0x100bd4e0 0x29 _L1e_SchedPreSyncGetAgcWorkInd
- 0x100bd509 0x24 _L1e_SchedPreSyncGetFssWorkInd
- 0x100bd52d 0x2d _L1e_SchedPreSyncGetCfoWorkInd
- 0x100bd55a 0x8 _L1e_SchedPreSyncGetFssWorkCnt
- 0x100bd562 0x8 _L1e_SchedPreSyncGetRfcWorkCnt
- 0x100bd56a 0x8 _L1e_SchedPreSyncSetCfgSfnInd
- 0x100bd572 0x8 _L1e_SchedPreSyncGetCfgSfnInd
- 0x100bd57a 0x8 _L1e_SchedPreSyncGetSfnBmp
- 0x100bd582 0xa _L1e_SchedPreSyncGetPoMarkSn
- 0x100bd58c 0x2e _L1e_SchedPreSyncGetConnWorkTimer
- 0x100bd5ba 0x75 _L1e_SchedPreSyncUpdateStep
- 0x100bd62f 0x8 _L1e_SchedPreSyncSetStep
- 0x100bd637 0x8 _L1e_SchedPreSyncGetStep
- 0x100bd63f 0x66 _L1e_DbgPreSyncCtrlInfo
- 0x100bd6a5 0x7f _L1e_SchedPreSyncCtrl
- 0x100bd724 0x132 _zPHY_emc_tRxCirPreSyncStart
- 0x100bd856 0xa1 _zPHY_emc_RfcRxColseOperationCheck
- 0x100bd8f7 0x57 _zPHY_emc_ProLpcSleepSchd
- .text 0x100bd94e 0x670 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_meas.o)
- 0x100bd94e 0x71 _zPHY_ecscMeas_LogMeasConfigReq
- 0x100bd9bf 0x35 _zPHY_ecscMeas_LogMeasBitMask
- 0x100bd9f4 0x71 _zPHY_ecscMeas_LogMeasAgeThrold
- 0x100bda65 0x5e _zPHY_ecscMeas_LogServCellResult
- 0x100bdac3 0x3f _zPHY_ecscMeas_LogPccMeasResult
- 0x100bdb02 0x78 _zPHY_ecscMeas_LogInterCellInfo
- 0x100bdb7a 0x47 _zPHY_ecsrc_LogInterMeasInd
- 0x100bdbc1 0x23 _zPHY_ecscMeas_LogConnInterReport
- 0x100bdbe4 0x4f _zPHY_ecscMeas_LogSccIntraMeasFilter
- 0x100bdc33 0x1a _zPHY_ecscMeas_LogSccIntraMeasFilter2
- 0x100bdc4d 0x2e _zPHY_ecscMeas_LogIntraFilter2
- 0x100bdc7b 0x19 _zPHY_ecscMeas_LogInterMeasFilter
- 0x100bdc94 0x1f _zPHY_ecscMeas_LogIntraRSSI
- 0x100bdcb3 0x16 _zPHY_ecscMeas_LogUpdateInterReportFail1
- 0x100bdcc9 0x47 _zPHY_ecscMeas_LogFilterInterReport3
- 0x100bdd10 0x33 _zPHY_ecscMeas_LogPCCIntraMeasCell
- 0x100bdd43 0x43 _zPHY_ecscMeas_LogPCCIntraMeasCell4
- 0x100bdd86 0x21 _zPHY_ecscMeas_LogSCCIntraMeasCell
- 0x100bdda7 0x85 _zPHY_ecscMeas_LogSCCIntraMeasCell2
- 0x100bde2c 0x76 _zPHY_ecscMeas_LogSCCIntraMeasCell4
- 0x100bdea2 0x41 _zPHY_ecscMeas_LogFilterIntraDebug
- 0x100bdee3 0x53 _zPHY_ecscMeas_LogFilterIntraDebug2
- 0x100bdf36 0x4f _zPHY_ecscMeas_LogFilterInterDebug
- 0x100bdf85 0x39 _zPHY_ecscMeas_LogCsrSnr
- .text 0x100bdfbe 0x6f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_dls.o)
- 0x100bdfbe 0x6f _L1e_LogDlDlsDciDetInfo
- .text 0x100be02d 0x9e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc.o)
- 0x100be02d 0x31 _zPHY_ecsc_LogMibReqCellInfo
- 0x100be05e 0x17 _zPHY_ecsc_LogEarfchTable
- 0x100be075 0x2f _zPHY_ecsc_LogTpuEventMark
- 0x100be0a4 0x59 _zPHY_ecsc_LogTimeOffsetPerfreq
- 0x100be0fd 0x25 _L1e_csrc_LogDrxRefreshGapCnt
- 0x100be122 0xa0 _L1e_csrc_LogCnnDrxSchedule
- 0x100be1c2 0x15 _zPHY_ecsc_LogRecv_REL_REQ
- 0x100be1d7 0x29 _zPHY_ecsc_LogRecv_StopInterSearchMeas
- 0x100be200 0x15 _zPHY_ecsc_LogReportMEASErr
- 0x100be215 0x48 _zPHY_ecsc_LogGAPTime
- 0x100be25d 0x2e _zPHY_ecsc_LogInterFreq
- 0x100be28b 0x2e _zPHY_ecsc_LogHandover
- 0x100be2b9 0x24 _zPHY_ecsc_LogRecv_MULM_IRAT_IDLE_PERIOD_REP_REQ
- 0x100be2dd 0x20 _zPHY_ecsc_LogRecv_FREQ_LIST_CONFIG_REQ
- 0x100be2fd 0x1d _zPHY_ecsc_LogRecv_IRAT_MEAS_CONFIG_REQ
- 0x100be31a 0x1d _zPHY_ecsc_LogRecv_IRAT_MEASURE_REPORT_INT
- 0x100be337 0x15 _zPHY_ecsc_LogAbortGap
- 0x100be34c 0x3f _zPHY_ecsc_LogREG_IRAT_GAP_CONFIG_DELAY_INT
- 0x100be38b 0x2e _zPHY_ecsc_LogRecv_IRAT_GAP_CONFIG_REQ
- 0x100be3b9 0x15 _zPHY_ecsc_LogTPUAdjusting
- 0x100be3ce 0x2e _zPHY_ecsc_LogRecv_IRAT_GAP_CONFIG_DELAY_INT
- 0x100be3fc 0x15 _zPHY_ecsc_LogRecv_RF_START_DEAL_PRE2SFINT
- 0x100be411 0x15 _zPHY_ecsc_LogRecv_RF_CLOSE_DEAL_PRE2SFINT
- 0x100be426 0x15 _zPHY_ecsc_LogRecv_RESET_REQ
- 0x100be43b 0x2a _zPHY_ecsc_LogRecv_CELL_SEARCH_REQ
- 0x100be465 0x15 _zPHY_ecsc_LogRecv_ABORT_CELL_SEARCH_REQ
- 0x100be47a 0x21 _zPHY_ecsc_LogRecv_COMMON_CONFIG_REQ
- 0x100be49b 0x15 _zPHY_ecsc_LogRecv_ABORT_MEAS_REQ
- 0x100be4b0 0x73 _zPHY_ecsc_LogRecv_PI_START_REQ
- 0x100be523 0x15 _zPHY_ecsc_LogRecv_ONE_FREQ_END_REQ
- 0x100be538 0x2e _zPHY_ecsc_LogRecv_IRAT_MEAS_GAP_CONFIG_REQ
- 0x100be566 0x1d _zPHY_ecsc_LogRecv_FREQ_SCAN_REQ
- 0x100be583 0x2b _zPHY_ecsc_LogPhyModeConfig
- 0x100be5ae 0x27 _zPHY_ecsc_LogReportGap
- 0x100be5d5 0x3c _L1e_CsrcDb_LogDelCell
- 0x100be611 0x18 _L1e_csrc_LogReTimeOffset
- 0x100be629 0x66 _zPHY_ecscDb_LogCellToDB
- 0x100be68f 0x3d _zPHY_ecscDb_LogRefreshDB
- 0x100be6cc 0x16 _zPHY_ecscDb_LogUpdateBoundary
- 0x100be6e2 0x1e _zPHY_ecsc_LogChangeMeasPeriodIdle
- 0x100be700 0x39 _zPHY_ecsc_Log_Earfcn_BandInfo
- 0x100be739 0x22 _zPHY_ecscMeas_LogSrvCellReslt
- 0x100be75b 0x1f _zPHY_ecsc_LogStandardOutput
- 0x100be77a 0x15 _zPHY_ecsc_LogMeasPeriodChgDelay
- 0x100be78f 0x1d _zPHY_ecsc_LogSibOrRapcConflict
- 0x100be7ac 0x1d _zPHY_ecsc_LogSubFreqOffset
- 0x100be7c9 0x16 _zPHY_ecsc_LogEarfcnError
- 0x100be7df 0x76 _L1e_csrc_LogShortDrxInfo
- 0x100be855 0x15 _L1e_csrc_LogTempComp
- 0x100be86a 0x15 _L1e_csrc_LogTempRead
- 0x100be87f 0x1f _L1e_csrc_LogGetFreqOffset
- 0x100be89e 0x1d _L1e_csrc_LogSetDisableAfcReloadFlag
- 0x100be8bb 0x25 _L1e_csrc_LogC0CaliUpDate
- 0x100be8e0 0x21 _L1e_csrc_LogC0CaliPeriod
- 0x100be901 0x22 _L1e_csrc_LogC0CaliEvalue
- 0x100be923 0x2f _L1e_csrc_LogC0Update
- 0x100be952 0x1e _L1e_csrc_LogC0Debug
- 0x100be970 0x27 _L1e_csrc_LogC0CalRsrp
- 0x100be997 0x1f _L1e_csrc_LogC0CalAfc
- 0x100be9b6 0x21 _L1e_csrc_LogC0UtcTimeExp
- 0x100be9d7 0x15 _L1e_csrc_LogC0CaliRestart
- 0x100be9ec 0x21 _L1e_csrc_LogNewUtcError
- .text 0x100bea0d 0x276 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm_normal.o)
- 0x100bea0d 0x4c _zPHY_ecsm_LogMeasHwInfo
- 0x100bea59 0x79 _zPHY_ecsmNormal_LogUpdateRes
- 0x100bead2 0x16 _zPHY_ecsrm_BuffLogSlaveMaxBdySub
- 0x100beae8 0x22 _zPHY_ecsrm_LogSetMeasAge
- 0x100beb0a 0x19 _zPHY_ecsrm_LogBuffFbRelatn
- 0x100beb23 0x17 _zPHY_ecsrm_LogMeasStartSubFrame
- 0x100beb3a 0x2b _zPHY_ecsrm_LogBuffCellPara
- 0x100beb65 0x3f _zPHY_ecsrm_LogBuffCommPara
- 0x100beba4 0x2d _zPHY_ecsrm_LogMeasResultRead
- 0x100bebd1 0x18 _zPHY_ecsrm_LogBuffMulmsubf
- 0x100bebe9 0x29 _zPHY_ecsrm_LogBuffSortCell
- 0x100bec12 0x27 _zPHY_ecsrm_LogBuffBdyCell
- 0x100bec39 0x27 _zPHY_ecsrm_LogBuffwait
- 0x100bec60 0x23 _zPHY_ecsrm_LogBuffMeasConfig
- .text 0x100bec83 0x378 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_cs.o)
- 0x100bec83 0x15 _zPHY_ecsccs_LogRSStart
- 0x100bec98 0x27 _zPHY_ecsccs_LogSearchReq
- 0x100becbf 0x41 _zPHY_ecsccs_LogCellInfo
- 0x100bed00 0x1a _zPHY_ecsc_LogRecv_PBCH
- 0x100bed1a 0x24 _zPHY_ecsccs_LogMeasStart
- 0x100bed3e 0x26 _zPHY_ecsccs_LogSendTPUAdjust
- 0x100bed64 0x30 _zPHY_ecsccs_LogCellRank
- 0x100bed94 0x1d _zPHY_ecsccs_LogNoAppointedCell
- 0x100bedb1 0x42 _zPHY_ecsccs_LogICPReportResultRIGHT
- 0x100bedf3 0x18 _zPHY_ecsccs_LogIcpBchCell
- 0x100bee0b 0x15 _zPHY_ecsccs_LogNoCell
- 0x100bee20 0x44 _zPHY_ecsccs_LogStartResumeSrv
- 0x100bee64 0x4b _zPHY_ecsccs_LogNewPlmnRS_ReportStatus
- 0x100beeaf 0x29 _zPHY_ecsccs_LogNewPlmnRS_SearchFinished
- 0x100beed8 0x1f _zPHY_ecsccs_LogNewPlmnRS_MeasFinished
- 0x100beef7 0x3c _zPHY_ecsccs_LogResumeServBCHBoundry
- 0x100bef33 0x26 _zPHY_ecsccs_LogCurTime2PiTime
- 0x100bef59 0x30 _zPHY_ecsccs_LogReg_PLMN_PERIODICAL_TPU_INT
- 0x100bef89 0x21 _zPHY_ecsccs_LogRecv_PLMN_SEARCH_TIME_EVENT
- 0x100befaa 0x51 _zPHY_ecsccs_LogWriteBch2CsrDb
- .text 0x100beffb 0x198 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_rx.o)
- 0x100beffb 0x29 _L1e_LogDlRxMbsfnCirInfo
- 0x100bf024 0x52 _L1e_LogRxMbmsCirAreaInfo
- 0x100bf076 0x9f _L1e_LogRxCirDataInfo
- 0x100bf115 0x42 _L1e_LogRxMbmsCirSearchInfo
- 0x100bf157 0x22 _L1e_LogRxBetaInfo
- 0x100bf179 0x1a _L1e_LogRxCfoCfgInfo
- .text 0x100bf193 0xb03 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_mulm.o)
- 0x100bf193 0x17 _zPHY_emulm_LogCsrSlaveStateChange
- 0x100bf1aa 0x17 _zPHY_emulm_LogCsrSlaveSYNStateChange
- 0x100bf1c1 0x20 _zPHY_emulm_LogCsrcGapStartOffset
- 0x100bf1e1 0x2c _zPHY_emulm_LogCsrcFreeTimeRep
- 0x100bf20d 0x17 _zPHY_emulm_LogCsrcSetModeReq
- 0x100bf224 0x17 _zPHY_emulm_LogCsrcMeasSche
- 0x100bf23b 0x26 _zPHY_emulm_LogCsrcMeasReportProct
- 0x100bf261 0x2f _zPHY_emulm_LogCsrcMeasReportInt
- 0x100bf290 0x16 _zPHY_emulm_LogMeasNoCell
- 0x100bf2a6 0x18 _zPHY_emulm_LogMeasCell
- 0x100bf2be 0x19 _zPHY_emulm_LogMeasNoCellReport
- 0x100bf2d7 0x73 _zPHY_emulm_LogMeasRight
- 0x100bf34a 0x16 _zPHY_emulm_LogASynSearch
- 0x100bf360 0x2a _zPHY_emulm_LogGapStartOffset
- 0x100bf38a 0x17 _zPHY_emulm_LogSubFrameOnOff
- 0x100bf3a1 0x2a _zPHY_emulm_LogGapEndOffset
- 0x100bf3cb 0x56 _zPHY_emulm_LogRegCsrIratGapStart
- 0x100bf421 0x94 _zPHY_emulm_LogRegCsrGapEnd
- 0x100bf4b5 0x56 _zPHY_emulm_LogRegCsrRfClose
- 0x100bf50b 0x17 _zPHY_emulm_LogBlackList
- 0x100bf522 0x1c _zPHY_emulm_LogRemainTime
- 0x100bf53e 0x20 _zPHY_emulm_LogSynInterSearchMeas
- 0x100bf55e 0x22 _zPHY_emulm_LogRegIratPlmnMeas
- 0x100bf580 0x22 _zPHY_emulm_LogRegSlaveAbortGap
- 0x100bf5a2 0x1d _zPHY_emulm_LogIratAbortGap
- 0x100bf5bf 0x1d _zPHY_emulm_LogIratMeasDone
- 0x100bf5dc 0x1e _zPHY_emulm_LogGapPosition
- 0x100bf5fa 0x4d _zPHY_emulm_LogGapTime
- 0x100bf647 0x4d _zPHY_emulm_LogGapTime1
- 0x100bf694 0x4d _zPHY_emulm_LogGapTime2
- 0x100bf6e1 0x17 _zPHY_emulm_LogPbchInGap
- 0x100bf6f8 0x28 _zPHY_emulm_LogEnRfcEventTable
- 0x100bf720 0x54 _zPHY_emulm_Log6MSRfcEventTableInGap
- 0x100bf774 0x39 _zPHY_emulm_LogrRfStartDeal
- 0x100bf7ad 0x39 _zPHY_emulm_LogrRfEndDeal
- 0x100bf7e6 0x36 _zPHY_emulm_LogRefreshDataBase1
- 0x100bf81c 0x18 _zPHY_emulm_LogtpuAdjust
- 0x100bf834 0x18 _zPHY_emulm_LogtpuCantAdjust
- 0x100bf84c 0x29 _zPHY_emulm_LogPssAdjust
- 0x100bf875 0x15 _zPHY_emulm_LogRecvSlaveAbortGap
- 0x100bf88a 0x15 _zPHY_emulm_LogRecvCsrAbortGap
- 0x100bf89f 0x15 _zPHY_emulm_LogRecvCsrTpuIratGap
- 0x100bf8b4 0x15 _zPHY_emulm_LogRecvCsrTpuIratGapStart
- 0x100bf8c9 0x65 _zPHY_emulm_LogSlaveMeasureFlow
- 0x100bf92e 0x15 _zPHY_emulm_LogRecvCsrTpuIratPlmnMeas
- 0x100bf943 0x15 _zPHY_emulm_LogRecvCsrTpuUpdateCounter
- 0x100bf958 0x15 _zPHY_emulm_LogCsrcRecvGapEndOffsetCfg
- 0x100bf96d 0x38 _zPHY_emulm_LogCsrcGatValidCellFbInfo
- 0x100bf9a5 0x21 _zPHY_emulm_LogCsrcTimeDelayIntEvent
- 0x100bf9c6 0x2c _zPHY_emulm_LogCsrcAfterAdjTpu
- 0x100bf9f2 0x31 _L1e_Mulm_LogNeedSearchAndMeas
- 0x100bfa23 0x19 _zPHY_emulm_LogCsrcStartEarfcnInfo
- 0x100bfa3c 0x2f _zPHY_emulm_LogCsrcEndEarfcnInfo
- 0x100bfa6b 0x67 _zPHY_emulm_LogCsrcGapAndSssInfo
- 0x100bfad2 0x6a _zPHY_emulm_LogCsrcHbTimeInfo
- 0x100bfb3c 0x2c _zPHY_emulm_LogCsrcSssBufferAndGap
- 0x100bfb68 0x21 _zPHY_emulm_LogCsrcAgcStart
- 0x100bfb89 0x39 _zPHY_emulm_LogCsrcSlaveSssProcessInfo
- 0x100bfbc2 0x43 _zPHY_emulm_LogBuffCheckOpenTimePeriod
- 0x100bfc05 0x21 _zPHY_emulm_LogGapCoverBuffCheck
- 0x100bfc26 0x1a _zPHY_emulm_LogMeasFilter
- 0x100bfc40 0x16 _zPHY_emulm_LogUpdateReportFail
- 0x100bfc56 0x26 _zPHY_emulm_LogSetFilterFact
- 0x100bfc7c 0x1a _zPHY_emulm_LogGetFilterFact
- .text 0x100bfc96 0x120 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_cmn_mbms.o)
- 0x100bfc96 0x91 _L1e_logCmnMbmsMbsfnSubfListInfo
- 0x100bfd27 0x8f _L1e_LogCmnMbmsMbsfnAllocInfo
- .text 0x100bfdb6 0x239 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm.o)
- 0x100bfdb6 0x30 _zPHY_ecsm_LogBlackCell
- 0x100bfde6 0xba _zPHY_ecsm_LogRfcOpenTime
- 0x100bfea0 0x4d _zPHY_ecsm_LogRfcOpenTimeFddIdle
- 0x100bfeed 0x54 _zPHY_ecsm_LogTDDRfcEventTab
- 0x100bff41 0x14 _zPHY_ecsm_LogRecv_RESET_REQ
- 0x100bff55 0x32 _zPHY_ecsm_LogMeasStart
- 0x100bff87 0x14 _zPHY_ecsm_Logrec_MEASRESET
- 0x100bff9b 0x16 _zPHY_ecsm_LogRecv_UnknownMsg
- 0x100bffb1 0x1e _zPHY_ecsm_Buff_LogRfcOpenTime
- 0x100bffcf 0x20 _zPHY_ecsm_LogRfcEventTablength
- .text 0x100bffef 0x3c8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_func.o)
- 0x100bffef 0xc _zPHY_GetUINT32BitsField
- 0x100bfffb 0x27 _zPHY_GetUINT64BitsField
- 0x100c0022 0x1f _zPHY_GetUINT16DivCeilValue
- 0x100c0041 0x22 _zPHY_GetUINT32DivCeilValue
- 0x100c0063 0x28 _zPHY_GetSINT16DivFloorValue
- 0x100c008b 0x2e _zPHY_GetSINT32DivFloorValue
- 0x100c00b9 0x16 _zPHY_BinarySearch
- 0x100c00cf 0x132 _zPHY_Pow2
- 0x100c0201 0x5b _zPHY_Fixpoint2Float
- 0x100c025c 0x88 _zPHY_Float2Fixpoint
- 0x100c02e4 0x6c _zPHY_DivRet2Fixpoint7510
- 0x100c0350 0x57 _zPHY_DivRet2Fixpoint
- 0x100c03a7 0x10 _zPHY_LteaDelay
- .text 0x100c03b7 0x60 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
- 0x100c03b7 0x57 _zPHY_setRxMaskFlag
- 0x100c040e 0x9 _zPHY_getRxMaskFlag
- .text 0x100c0417 0x95 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
- 0x100c0417 0x37 _L1l_CmnAssert
- 0x100c044e 0x5a _zPHY_RecvUnknownMsg
- 0x100c04a8 0x4 _zPHY_create_handler
- .text 0x100c04ac 0x28c5 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_srs.o)
- 0x100c04ac 0x2f _zPHY_eula_PucchSrsRelease
- 0x100c04db 0x6d _zPHY_eula_SetSrsScale
- 0x100c0548 0x58 _zPHY_eula_LtxParas_QDivNRsZcSrs
- 0x100c05a0 0x31f _zPHY_eula_UpdataSrsBGParas_Cell
- 0x100c08bf 0xd0 _zPHY_eula_UpdataSrsBGParas_APSfOffset
- 0x100c098f 0x19d _zPHY_eula_UpdataSrsBGParas_APTiming
- 0x100c0b2c 0x159 _zPHY_eula_UpdataSrsBGParas_APParaCalc_PTS
- 0x100c0c85 0x29b _zPHY_eula_UpdataSrsBGParas_APParaCalc
- 0x100c0f20 0x3d _zPHY_eula_UpdataSrsBGParas_APParaAssign
- 0x100c0f5d 0x62 _zPHY_eula_UpdataSrsBGParas_AP
- 0x100c0fbf 0x2f6 _zPHY_eula_UpdataSrsBGParas_PTiming
- 0x100c12b5 0x159 _zPHY_eula_UpdataSrsBGParas_PNonHopParaCalc_PTS
- 0x100c140e 0x219 _zPHY_eula_UpdataSrsBGParas_PNonHopParaCalc
- 0x100c1627 0x118 _zPHY_eula_UpdataSrsBGParas_PHopParaCalc_PTS
- 0x100c173f 0x27d _zPHY_eula_UpdataSrsBGParas_PHopParaCalc
- 0x100c19bc 0x6d _zPHY_eula_UpdataSrsBGParas_P
- 0x100c1a29 0xb2 _zPHY_eula_UpdataSrsBGParas
- 0x100c1adb 0xe4 _zPHY_eula_CommSrsProc
- 0x100c1bbf 0x22e _zPHY_eula_ScheApSrs
- 0x100c1ded 0x27 _zPHY_eula_WipeSrsInRarBasedPusch
- 0x100c1e14 0x80 _zPHY_eula_DetermineSrsCellSpecStateInPusch
- 0x100c1e94 0xbe _zPHY_eula_ProcConflictOfSrsAndPucchPusch_OneCell
- 0x100c1f52 0x50 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell
- 0x100c1fa2 0x4d _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschScell
- 0x100c1fef 0x86 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_PuschScell
- 0x100c2075 0x120 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_Pucch
- 0x100c2195 0x136 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_Pucch_PuschScell
- 0x100c22cb 0x12e _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_Pucch_PuschScell
- 0x100c23f9 0x2 _zPHY_eula_ProcConflictOfSrsAndPucchPusch
- 0x100c23fb 0x5e _zPHY_eula_ScheSrsInPusch_AntMapping
- 0x100c2459 0x7d _zPHY_eula_ScheSrsInPusch
- 0x100c24d6 0xb1 _zPHY_eula_ProcConflictOfSrsAndPucch_OneCell
- 0x100c2587 0x2 _zPHY_eula_ProcConflictOfSrsAndPucch
- 0x100c2589 0x1d _zPHY_eula_ProcConflictOfSrsAndDrx
- 0x100c25a6 0x4b _zPHY_eula_ScheSrsInNonPusch
- 0x100c25f1 0x4e _zPHY_eula_ProcSrsInDurationMode0
- 0x100c263f 0x4c _zPHY_eula_GetPtsState
- 0x100c268b 0xbe _zPHY_eula_CalcApSrsParas
- 0x100c2749 0xbe _zPHY_eula_CalcPNonHopSrsParas
- 0x100c2807 0x389 _zPHY_eula_CalcPHopSrsParas
- 0x100c2b90 0x46 _zPHY_eula_CalcSrsParas
- 0x100c2bd6 0x70 _zPHY_eula_InitSrsDB
- 0x100c2c46 0x4e _zPHY_eula_SrsSrcRelease
- 0x100c2c94 0x18 _zPHY_eula_ClearApSrsSche
- 0x100c2cac 0xbc _zPHY_eula_CalcnSrs
- 0x100c2d68 0x9 _zPHY_eula_SrsAntennaSelect
- .text 0x100c2d71 0x516 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
- 0x100c2d71 0x53 _zPHY_edla_GetPhichGrpNum
- 0x100c2dc4 0xb _zPHY_edla_GetPhichRegNum
- 0x100c2dcf 0x10b _zPHY_edla_GetNextSubFrmPhichInfo
- 0x100c2eda 0x100 _zPHY_edla_UpdateIphichInfo
- 0x100c2fda 0x10 _zPHY_edla_GetPhichInfo
- 0x100c2fea 0xc9 _zPHY_edla_GetPerPhichSeq
- 0x100c30b3 0x95 _zPHY_edla_GetPerTBPhichSeq
- 0x100c3148 0x11 _zPHY_edla_GetPhichSeq
- 0x100c3159 0x23 _zPHY_edla_GetHichSubFreq
- 0x100c317c 0xbb _zPHY_edla_PhichProc
- 0x100c3237 0x45 _zPHY_edla_UpdatePhichInfo
- 0x100c327c 0xb _zPHY_edla_HiValidJudgment
- .text 0x100c3287 0x1540 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
- 0x100c3287 0x5d _zPHY_edfe_SupCommonCalAGC
- 0x100c32e4 0x72 _zPHY_edfe_SupFastAGC
- 0x100c3356 0xd9 _zPHY_edfe_SupNotSyncAGC
- 0x100c342f 0x295 _zPHY_edfe_SupNotSyncAGCAnt0And1
- 0x100c36c4 0x18 _zPHY_edfe_GetAgcReloadVal
- 0x100c36dc 0x11 _zPHY_edfe_ConfigAgcReloadVal
- 0x100c36ed 0x16 _zPHY_edfe_ACP405AgcGainConfig
- 0x100c3703 0xac _zPHY_edfe_SupAGCLostLockMethod
- 0x100c37af 0x3f _zPHY_edfe_InitAgcPara
- 0x100c37ee 0x1a _zPHY_edfe_ResetAgcCoverJudgePara
- 0x100c3808 0x24 _zPHY_edfe_InitAgcDagcGain
- 0x100c382c 0x155 _zPHY_edfe_JudgeAgcCoverOpt
- 0x100c3981 0x67 _zPHY_edfe_CalcAGCForBandChange
- 0x100c39e8 0xb8 _zPHY_edfe_GetNextAGCInitGain
- 0x100c3aa0 0x9b _zPHY_edfe_CalcAGCNewMethodAnt
- 0x100c3b3b 0x9d _zPHY_edfe_CalcAGCGainNewMethod
- 0x100c3bd8 0x139 _zPHY_edfe_SupHandleAGCOpt
- 0x100c3d11 0x51 _zPHY_edfe_FindOldestPosInAgcGainDB
- 0x100c3d62 0x9 _zPHY_edfe_SupResetAGCLoopOpt
- 0x100c3d6b 0xb7 _zPHY_edfe_NotSyncToSyncSetAgc
- 0x100c3e22 0x3d _zPHY_edfe_SyncToNotSyncSetAgc
- 0x100c3e5f 0x10b _zPHY_edfe_UpdateSCCAGC
- 0x100c3f6a 0x12 _zPHY_edfe_CompAgcDBTimeInfo
- 0x100c3f7c 0xc7 _zPHY_edfe_IratHandoverAfcManage
- 0x100c4043 0x71 _zPHY_edfe_SupSaveSlaveAfcCtrl
- 0x100c40b4 0xfd _zPHY_edfe_IratHandoverCordicManage
- 0x100c41b1 0x8e _zPHY_edfe_IratCordicManage
- 0x100c423f 0x6e _zPHY_edfe_SupSaveSlaveCordicCtrl
- 0x100c42ad 0x77 _zPHY_edfe_FSNewAgcIntHandle
- 0x100c4324 0x72 _zPHY_edfe_InitSubFramePwrDB
- 0x100c4396 0x263 _zPHY_edfe_SupSemiStaticAgcNew
- 0x100c45f9 0x26 _zPHY_edfe_MbsfnAgcDbInit
- 0x100c461f 0xc _zPHY_edfe_MbsfnAgcParaConfig
- 0x100c462b 0x9f _zPHY_edfe_SupCalMbsfnRegionAgc
- 0x100c46ca 0xb6 _zPHY_edfe_SupHandleMbsfnAGC
- 0x100c4780 0x2f _zPHY_edfe_NewMbsfnAGCGainInit
- 0x100c47af 0x1 _zPHY_edfe_MbsfnAgcCoverJudge
- 0x100c47b0 0x17 _zPHY_edfe_MbsfnAgcGainConfig
- .text 0x100c47c7 0x251 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
- 0x100c47c7 0x1ae _zPHY_eulpc_SrsPowCalc
- 0x100c4975 0xa3 _zPHY_eulpc_SrsPowCtrl
- .text 0x100c4a18 0x1175 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
- 0x100c4a18 0x1 _zPHY_euls_L_Entry
- 0x100c4a19 0x34c _zPHY_euls_Entry
- 0x100c4d65 0x2cc _zPHY_euls_TPU_INT1_RARGrantProcess
- 0x100c5031 0x2fa _zPHY_euls_TPU_INT1_DCIProcess
- 0x100c532b 0x435 _zPHY_euls_TPU_INT1_Step1_process
- 0x100c5760 0x191 _zPHY_euls_TPU_INT1_Step2_process
- 0x100c58f1 0x8b _zPHY_euls_GetDediCfgParas
- 0x100c597c 0x7f _zPHY_euls_GetSCellCfgParas
- 0x100c59fb 0x80 _zPHY_euls_GetCommCfgParas
- 0x100c5a7b 0x10e _zPHY_euls_GetHandoverCfgParas
- 0x100c5b89 0x4 _zPHY_euls_PuschAntennaSelect
- .text 0x100c5b8d 0x224c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
- 0x100c5b8d 0x2c _L1e_FS_SwReset
- 0x100c5bb9 0x16 _L1e_FS_Init
- 0x100c5bcf 0x32 _L1e_FS_FreqScanEnRfcNotSyncTable
- 0x100c5c01 0xb3 _L1e_FS_HandleFreqscanAddSearchResult
- 0x100c5cb4 0x9c _L1e_FS_CalcSssAgcGainCompen
- 0x100c5d50 0xec _L1e_FS_FreqScanAddSearchResultSort
- 0x100c5e3c 0x30 _L1e_FS_SetFSResult
- 0x100c5e6c 0x110 _L1e_FS_FindFSEarfcnToReport
- 0x100c5f7c 0x34 _L1e_FS_FindEarfcnForSearch
- 0x100c5fb0 0x36 _L1e_FS_SendFsCnf
- 0x100c5fe6 0x8f _L1e_FS_BufForSearch
- 0x100c6075 0x86 _L1e_Fs_CreateList_Band38_Bak
- 0x100c60fb 0x6c _L1e_Fs_CreateListBak
- 0x100c6167 0x6a _L1e_Fs_IsFreqPointValid
- 0x100c61d1 0x36 _L1e_Fs_MaxPeakSetZero
- 0x100c6207 0x2a _L1e_Fs_GetMaxValue
- 0x100c6231 0x28 _L1e_Fs_GetMinValue
- 0x100c6259 0x33 _L1e_Fs_SetProfileInfo
- 0x100c628c 0x34 _L1e_Fs_DelList
- 0x100c62c0 0x6 _L1e_FS_ClearPssResultList
- 0x100c62c6 0x6 _L1e_FS_ClearMeanPowerResultList
- 0x100c62cc 0xe _L1e_FS_SetRedoInfo
- 0x100c62da 0xf4 _L1e_FS_GetAllGainProfileInfo
- 0x100c63ce 0x63 _L1e_FS_GetAllProfileInfo
- 0x100c6431 0xcf _L1e_Fs_GetAllValidFreqPoint
- 0x100c6500 0x33 _L1e_FS_SetBandInfo
- 0x100c6533 0xf _L1e_FS_SetSpecialBandInfo
- 0x100c6542 0x5c _L1e_FS_SetOverLapFreqBand
- 0x100c659e 0x1cb _L1e_FS_GenFreqBand
- 0x100c6769 0x1e _L1e_FS_CfgRfcNotSyncTable
- 0x100c6787 0x51 _L1e_FS_ReqMsgHandle
- 0x100c67d8 0x13 _L1e_FS_SetFreqPoint
- 0x100c67eb 0x74 _L1e_FS_InsertPssResult
- 0x100c685f 0xb3 _L1e_FS_SetIniCsrInfo
- 0x100c6912 0xb0 _L1e_FS_SetFsRslt
- 0x100c69c2 0x8b _L1e_FS_ResultSort
- 0x100c6a4d 0x1b _L1e_FS_PlmnPeriodTpuInPro
- 0x100c6a68 0xca _L1e_FS_SetDisctRslt
- 0x100c6b32 0x21 _L1e_FS_SeekToHalfFram
- 0x100c6b53 0xce _L1e_FS_DoPss
- 0x100c6c21 0x109 _L1e_FS_PssNext100KFreqPointNoPreCFO
- 0x100c6d2a 0x61 _L1e_FS_PssNext100KFreqPointPreCFO
- 0x100c6d8b 0x2f _L1e_FS_PssNext100KFreqPoint
- 0x100c6dba 0x35 _L1e_FS_PssNextAgcGain
- 0x100c6def 0x1b _L1e_FS_PssNextProfile
- 0x100c6e0a 0x79 _L1e_FS_InitFreqOffset
- 0x100c6e83 0x41 _L1e_FS_PssNextFreqOffset
- 0x100c6ec4 0x3d _L1e_FS_PreFreqOffset
- 0x100c6f01 0x12d _L1e_FS_Pss100KResult
- 0x100c702e 0x27 _L1e_FS_DiscreteFreqOffsetLoop
- 0x100c7055 0x77 _L1e_FS_PssDisctResult
- 0x100c70cc 0x1b _L1e_FS_PssProfileLoopStart
- 0x100c70e7 0x54 _L1e_FS_NextBand
- 0x100c713b 0x1b _L1e_FS_Pss500KFreqPointLoopStart
- 0x100c7156 0x31 _L1e_FS_PssNext500KFreqPoint
- 0x100c7187 0x11 _L1e_FS_GetFsMode
- 0x100c7198 0x56 _L1e_FS_SetFsTempResult
- 0x100c71ee 0xa4 _L1e_FS_FreqScanCellSearch
- 0x100c7292 0x4a _L1e_FS_PssOneFreqPointStart
- 0x100c72dc 0x2b _L1e_FS_PssAgcGainLoopStart
- 0x100c7307 0x4e _L1e_FS_Pss100KFreqPointLoopStart
- 0x100c7355 0xc _L1e_FS_PssNeedOffset
- 0x100c7361 0xd _L1e_FS_PssNeedDo100K
- 0x100c736e 0xe _L1e_FS_BandLoopStart
- 0x100c737c 0x2b _L1e_FS_PssSkipPiTime
- 0x100c73a7 0x1e _L1e_FS_PssSeekToSlaveGap
- 0x100c73c5 0x23 _L1e_FS_SeekToWorkTime
- 0x100c73e8 0x24 _L1e_FS_MpFreqPointLoopStart
- 0x100c740c 0x7b _L1e_FS_SegmentInfoSort
- 0x100c7487 0x93 _L1e_FS_SetSegmentInfo
- 0x100c751a 0xd3 _L1e_FS_SetSegmentInfoEnd
- 0x100c75ed 0xb4 _L1e_FS_FreqSegmentAlorigthm
- 0x100c76a1 0x62 _L1e_FS_FreqSegment
- 0x100c7703 0x2f _L1e_FS_MpNextFreqPoint
- 0x100c7732 0x24 _L1e_FS_MpOneFreqPointStart
- 0x100c7756 0x40 _L1e_FS_MeanPowerCal
- 0x100c7796 0xc _L1e_FS_MpMethod
- 0x100c77a2 0x11 _L1e_FS_PssMethod
- 0x100c77b3 0x14 _L1e_FS_PLMN
- 0x100c77c7 0xb _L1e_FS_SetState
- 0x100c77d2 0x8 _L1e_FS_GetState
- 0x100c77da 0x13 _L1e_FS_MpStart
- 0x100c77ed 0x15 _L1e_FS_SetCnfInfo
- 0x100c7802 0x68 _L1e_FS_OverlapSegment
- 0x100c786a 0x89 _L1e_FS_Report2PsResult
- 0x100c78f3 0x1b _l1e_FS_MPEnvelopeSort
- 0x100c790e 0x22 _L1e_FS_MpEnvelope
- 0x100c7930 0xa _L1e_FS_PssNeedReDo500K
- 0x100c793a 0xc _L1e_FS_Redo500KStart
- 0x100c7946 0xf _L1e_FS_PssReDo500KNextProfile
- 0x100c7955 0x1c _L1e_FS_PssReDo500KFpLoopStart
- 0x100c7971 0x43 _L1e_Fs_ReDoGetAllValidFreqPoint
- 0x100c79b4 0x24 _L1e_FS_PssReDoNext500KFreqPoint
- 0x100c79d8 0xa _L1e_FS_PssNeedAgc
- 0x100c79e2 0x9 _L1e_FS_AgcLoopStart
- 0x100c79eb 0x45 _L1e_FS_AgcNextFreqPoint
- 0x100c7a30 0x21 _L1e_FS_BeforeAgc
- 0x100c7a51 0x16 _L1e_FS_AddAgcWaitTime
- 0x100c7a67 0xc5 _L1e_FS_AgcProc
- 0x100c7b2c 0x17 _L1e_FS_PssNeedReDo100K
- 0x100c7b43 0x17 _L1e_FS_IsSerialMode
- 0x100c7b5a 0x35 _L1e_FS_IsDiscreteMode
- 0x100c7b8f 0x2b _L1e_FS_DiscretePssStart
- 0x100c7bba 0x12 _L1e_FS_DiscretePssSnrBackup
- 0x100c7bcc 0xc _L1e_FS_DiscretePssSnrClear
- 0x100c7bd8 0x31 _L1e_FS_CheckSearchMode
- 0x100c7c09 0x1b6 _L1e_FS_CfgRfAndGetMp
- 0x100c7dbf 0x1a _L1e_FS_MpSeekWorkTime
- .text 0x100c7dd9 0x345c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
- 0x100c7dd9 0x119 _zPHY_euls_UlGrantReception
- 0x100c7ef2 0x13d _zPHY_euls_HARQEntity
- 0x100c802f 0x333 _zPHY_euls_HARQProcess
- 0x100c8362 0x57 _zPHY_euls_ProInitial
- 0x100c83b9 0x31 _zPHY_euls_InitUlHarqIDInHarqDB
- 0x100c83ea 0x141 _zPHY_euls_UlHarqProcessCtrl
- 0x100c852b 0x364 _zPHY_euls_DecodeDci4
- 0x100c888f 0x3bf _zPHY_euls_DecodeDci0
- 0x100c8c4e 0x104 _zPHY_euls_DecodeDci
- 0x100c8d52 0x4f _zPHY_euls_DecodePucchTPC
- 0x100c8da1 0x8f _zPHY_euls_GetMsg3SendSubFrmNo
- 0x100c8e30 0x99 _zPHY_euls_DecodeRARGrant
- 0x100c8ec9 0xaf _zPHY_euls_ReportUlGrantParas
- 0x100c8f78 0xa8 _zPHY_euls_ReportUlGrantToPS
- 0x100c9020 0xab _zPHY_euls_CalcLUtrPara
- 0x100c90cb 0x9c _zPHY_euls_CalcLTxPara
- 0x100c9167 0x129 _zPHY_euls_PuschPrmFHType1
- 0x100c9290 0x1df _zPHY_euls_PuschPrmFHType2
- 0x100c946f 0x10 _zPHY_euls_CalcX2Cinit
- 0x100c947f 0x62 _zPHY_euls_CalcNPuschSymb
- 0x100c94e1 0x148 _zPHY_euls_DecodeModuleCodeSchem
- 0x100c9629 0x25 _zPHY_euls_Nchoosek
- 0x100c964e 0x1b5 _zPHY_euls_DecodeRIV_Ratype1
- 0x100c9803 0x75 _zPHY_euls_DecodeRIV
- 0x100c9878 0x44 _zPHY_euls_GetRbAssignBitWidInDci4
- 0x100c98bc 0x43 _zPHY_euls_GetRbAssignBitWidInDci0
- 0x100c98ff 0xc9 _zPHY_euls_GetPuschPosByPdcchOrPhichPos
- 0x100c99c8 0x59 _zPHY_euls_AddMsg4DetectStartEvent
- 0x100c9a21 0x5a _zPHY_euls_AddMsg4DetectStopEvent
- 0x100c9a7b 0x1f _zPHY_euls_AddMsg4DetectWinEvents
- 0x100c9a9a 0x2d _zPHY_euls_ModifyMsg4DetectWinEvents
- 0x100c9ac7 0xde _zPHY_euls_AddMsg3LtxDealEvent
- 0x100c9ba5 0x49 _zPHY_euls_AddCqiRarSchdEvents
- 0x100c9bee 0x32 _zPHY_euls_InitSPSMode
- 0x100c9c20 0x2b _zPHY_euls_SetupSPSMode
- 0x100c9c4b 0x7a _zPHY_euls_SetupSPSMode_DealComnPara
- 0x100c9cc5 0x37 _zPHY_euls_SetupSPSMode_CalNextRecurPara
- 0x100c9cfc 0x41 _zPHY_euls_JudgeAndDealUlSpsInterval_TDD
- 0x100c9d3d 0x2e _zPHY_euls_JudgeAndDealUlSpsInterval_FDD
- 0x100c9d6b 0x53 _zPHY_euls_ProSPSMode
- 0x100c9dbe 0x53 _zPHY_euls_ProSPSMode_GetUlSfUponCfgGrantSf
- 0x100c9e11 0x44 _zPHY_euls_ProSPSMode_CalNextRecurPara
- 0x100c9e55 0x32 _zPHY_euls_ReleaseSPSMode
- 0x100c9e87 0x37 _zPHY_euls_ProcessSPSImplicitRelease
- 0x100c9ebe 0x11 _zPHY_euls_GetDCI0InfoFromConfiguredGrant
- 0x100c9ecf 0x11 _zPHY_euls_LastSubframe_SFN
- 0x100c9ee0 0xd _zPHY_euls_LastSubframe_Subframe
- 0x100c9eed 0xc _zPHY_euls_JudgeIfBitsIsAll1s_ForSPSRelease
- 0x100c9ef9 0x4b _zPHY_euls_TATimerStop
- 0x100c9f44 0xe _zPHY_euls_MACReset
- 0x100c9f52 0xa1 _zPHY_euls_Release
- 0x100c9ff3 0x1e _zPHY_euls_ProcDci0PhichSelec
- 0x100ca011 0xcd _zPHY_euls_ProcDci0PhichSelec_Assign
- 0x100ca0de 0x46 _zPHY_euls_ProcDci0PhichSelec_Selec
- 0x100ca124 0x34 _zPHY_euls_DecodeUlIndexDci0
- 0x100ca158 0x33 _zPHY_euls_DecodeUlIndexDci4
- 0x100ca18b 0x152 _zPHY_euls_AssignDCI0PHICH
- 0x100ca2dd 0x5e _zPHY_euls_AssignDCI0_Schedule
- 0x100ca33b 0x26 _zPHY_euls_AssignPHICH_Schedule
- 0x100ca361 0x5a _zPHY_euls_SelecDCI0PHICH
- 0x100ca3bb 0x21 _zPHY_euls_ReleaseDCI0PHICHSelecDB
- 0x100ca3dc 0x67 _zPHY_euls_UpdataTTIBundlingHarqID
- 0x100ca443 0xa1 _zPHY_euls_DealBundlingGrant
- 0x100ca4e4 0x5a _zPHY_euls_ProcRealPHICH
- 0x100ca53e 0x59 _zPHY_euls_ProcVirtualPHICH
- 0x100ca597 0x7b _zPHY_euls_InitTTIBundlingHarqID
- 0x100ca612 0x16 _zPHY_euls_InitTTIBundlingMode
- 0x100ca628 0xc _zPHY_euls_ReleaseTTIBundlingMode
- 0x100ca634 0x6c _zPHY_euls_GetBundlingIDAndHarqID_InULA
- 0x100ca6a0 0x75 _zPHY_euls_UpdataHarqID
- 0x100ca715 0x8 _zPHY_euls_AddAbsSubframe
- 0x100ca71d 0x66 _zPHY_euls_SetDrxFlag
- 0x100ca783 0xcd _zPHY_euls_Dci0SelecAndCsiReport_Proc
- 0x100ca850 0x3d3 _zPHY_euls_CalcDciCsiReqFlag
- 0x100cac23 0xf7 _zPHY_euls_CalLutrAndLtx
- 0x100cad1a 0x16 _zPHY_euls_ScheduleTxChannelType
- 0x100cad30 0x7d _zPHY_euls_SchedulePuschAndPucch
- 0x100cadad 0x16f _zPHY_euls_DeterminePuschTransType
- 0x100caf1c 0x37 _zPHY_euls_GetPuschHarqAckInfo
- 0x100caf53 0x12d _zPHY_euls_DeterminePucchFmt
- 0x100cb080 0x26 _zPHY_euls_GetSysTimeInfo
- 0x100cb0a6 0x75 _zPHY_euls_TM2_ChanExchange
- 0x100cb11b 0x66 _zPHY_euls_PuschPowerControl_Process
- 0x100cb181 0x50 _zPHY_euls_NoPuschPowerControl_Process
- 0x100cb1d1 0x2a _zPHY_euls_GaoTong_Statistics_Process
- 0x100cb1fb 0x1 _zPHY_euls_AmtTest_DciStubProcess
- 0x100cb1fc 0x39 _zPHY_euls_GetPhichSubFrmNo
- .text 0x100cb235 0xa6d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
- 0x100cb235 0x5 _zPHY_ecsrs_GetIdleDrxInterPssWorkTime
- 0x100cb23a 0x165 _zPHY_ecsrs_GetPssStartTime
- 0x100cb39f 0x63 _zPHY_ecsrs_AdjustPssStartTime
- 0x100cb402 0x14e _zPHY_ecsrs_SetPssFirstStartInfo
- 0x100cb550 0xca _zPHY_ecsrs_SetPssNotFirstStartInfo
- 0x100cb61a 0x9a _zPHY_ecsrs_GetPssStartInfo
- 0x100cb6b4 0x4f _zPHY_ecsrs_GetPssReadFlag
- 0x100cb703 0x23 _zPHY_ecsrs_ClearPeakList
- 0x100cb726 0x1a _zPHY_ecsrs_GetPssData
- 0x100cb740 0x1c _zPHY_ecsrs_BackupPssFinger
- 0x100cb75c 0xb _zPHY_ecsrs_ClearPssFinger
- 0x100cb767 0xd _zPHY_ecsrs_ClearInnerPeakList
- 0x100cb774 0x5e _zPHY_ecsrs_AdjustPeakTime
- 0x100cb7d2 0x19 _zPHY_ecsrs_FindFreq
- 0x100cb7eb 0x3d _zPHY_ecsrs_BackupPeakList
- 0x100cb828 0xa8 _zPHY_ecsrs_RecoverPeakList
- 0x100cb8d0 0x215 _zPHY_ecsrs_PssResultReadNew
- 0x100cbae5 0x63 _zPHY_ecsrs_CalBoundary
- 0x100cbb48 0x2b _zPHY_ecsrs_CalRedoCfoBoundary
- 0x100cbb73 0x46 _zPHY_ecsrs_PssAdjustPro
- 0x100cbbb9 0x28 _zPHY_ecsrs_PssTpuAdjust
- 0x100cbbe1 0x13 _zPHY_ecsrs_SearchMaxFinger
- 0x100cbbf4 0xa0 _zPHY_ecsrs_FilterFinger
- 0x100cbc94 0xe _zPHY_ecsrs_FingerIsValid
- .text 0x100cbca2 0xc54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pusch.o)
- 0x100cbca2 0x69 _zPHY_eula_PuschAckProcess
- 0x100cbd0b 0x177 _zPHY_eula_PuschCsiProcess
- 0x100cbe82 0xc2 _zPHY_eula_SetPuschScale
- 0x100cbf44 0x1ed _zPHY_eula_PuschAckEncodedLenCalc
- 0x100cc131 0x2b9 _zPHY_eula_TDD_PuschAckParasCalc
- 0x100cc3ea 0x57 _zPHY_eula_TDD_PuschAckParasCalc_UlDl0
- 0x100cc441 0x86 _zPHY_eula_LtxParas_acNcsPuschDmrs
- 0x100cc4c7 0xc7 _zPHY_eula_LtxParas_acUVPuschDmrs
- 0x100cc58e 0x290 _zPHY_eula_PuschCqiRiEncodedLenCalc
- 0x100cc81e 0x24 _zPHY_eula_FDD_PuschAckParasCalc
- 0x100cc842 0x8e _zPHY_eula_LtxParas_adwNcsDiv6PuschDmrs
- 0x100cc8d0 0x26 _zPHY_eula_HarqPuschMsg3Stub
- .text 0x100cc8f6 0x547 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
- 0x100cc8f6 0x80 _zPHY_eulpc_PuschPowParasCalc
- 0x100cc976 0x119 _zPHY_eulpc_UlsRelativePuscchPowCtrlProc
- 0x100cca8f 0x190 _zPHY_eulpc_PuschPowCalcProc
- 0x100ccc1f 0xa9 _zPHY_eulpc_NoPuschPowCalc
- 0x100cccc8 0xb3 _zPHY_eulpc_DeltaTFCalc
- 0x100ccd7b 0x89 _zPHY_eulpc_Log10yLinear
- 0x100cce04 0x39 _zPHY_eulpc_PuschGetCsiInfo
- .text 0x100cce3d 0x540 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
- 0x100cce3d 0x6d _zPHY_edfe_Q8log2
- 0x100cceaa 0x21 _zPHY_edfe_Logarithm
- 0x100ccecb 0x34 _zPHY_edfe_SupCalLog
- 0x100cceff 0x8 _zPHY_edfe_SetCsrmDAGCGain
- 0x100ccf07 0x76 _zPHY_edfe_CalcRxDAGCGain
- 0x100ccf7d 0xa2 _zPHY_edfe_HandleRxDAGCGain
- 0x100cd01f 0x57 _zPHY_edfe_FixedRXDagcGain
- 0x100cd076 0x105 _zPHY_edfe_CalcCsrsDAGCGain
- 0x100cd17b 0x26 _zPHY_edfe_JudgeRxDagcCover
- 0x100cd1a1 0x6d _zPHY_edfe_JudgeCsrsDagcCover
- 0x100cd20e 0xa8 _zPHY_edfe_HandleCsrsDagcInt
- 0x100cd2b6 0x39 _zPHY_edfe_ConfigDagcCalcPara
- 0x100cd2ef 0x8e _zPHY_edfe_SetInterCsrsDAGCGain
- .text 0x100cd37d 0x777 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
- 0x100cd37d 0x26 _zAsn1_GetU16Bits
- 0x100cd3a3 0x39 _zAsn1_SetU16Bits
- 0x100cd3dc 0x18 _zEasn1p_perGetConVal
- 0x100cd3f4 0xc _zEasn1p_perGetDivbVal
- 0x100cd400 0xa _zEasn1p_perGetIntVal
- 0x100cd40a 0x13 _zEasn1p_perGetBitNum
- 0x100cd41d 0x1a _zEasn1p_perGetRange
- 0x100cd437 0x67 _zEasn1p_DcGetBitsVal32_Dec
- 0x100cd49e 0x2 _zEasn1p_DcGetBitsVal32
- 0x100cd4a0 0x13 _zEasn1p_MovePtr_Dec
- 0x100cd4b3 0x1d _zEasn1p_EcSetBitStr_Dec
- 0x100cd4d0 0xa2 _zEasn1p_DcGetBitsStr_Dec
- 0x100cd572 0x2 _zEasn1p_DcGetBitsStr
- 0x100cd574 0x1a _zEasn1p_ChkCodeLen_Dec
- 0x100cd58e 0x91 _zEasn1p_per_dcOctStr
- 0x100cd61f 0xe5 _zEasn1p_per_dcLen
- 0x100cd704 0x2f _zEasn1p_per_DcExt
- 0x100cd733 0x2f _zEasn1p_per_dcIndefiniteLenWholeNum
- 0x100cd762 0x2e _zEasn1p_per_dcConWholeNum
- 0x100cd790 0x8f _zEasn1p_per_dcSequenceOf
- 0x100cd81f 0x2 _zEasn1p_MovePtr
- 0x100cd821 0x24 _zEasn1p_per_dcPreamble
- 0x100cd845 0x29 _zEasn1p_per_dcPreamble_Sequence
- 0x100cd86e 0x47 _zEasn1p_per_dcSmallWholeNum
- 0x100cd8b5 0x46 _zEasn1p_per_dcSkipAllExtData
- 0x100cd8fb 0xb7 _zEasn1p_per_dcInt
- 0x100cd9b2 0x66 _zEasn1p_per_dcChoiceOf
- 0x100cda18 0x4a _zEasn1p_per_dcSkipOneExtData
- 0x100cda62 0x92 _zEasn1p_per_dcBitStr
- .text 0x100cdaf4 0x391 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
- 0x100cdaf4 0x55 _zPHY_ecsrs_GetCfoStartTime
- 0x100cdb49 0x54 _zPHY_ecsrs_SetCfoStartInfoSymMap
- 0x100cdb9d 0xa1 _zPHY_ecsrs_GetCfoStartInfo
- 0x100cdc3e 0x1e _zPHY_ecsrs_CalPowerNcpEcp
- 0x100cdc5c 0x46 _zPHY_ecsrs_CfoCalcPower
- 0x100cdca2 0x5e _zPHY_ecsrs_CfoCalcPowerNcpEcp
- 0x100cdd00 0x5e _zPHY_ecsrs_Codic_atan_FixPoint
- 0x100cdd5e 0x76 _zPHY_ecsrs_CsCfoResultMerge
- 0x100cddd4 0xb1 _zPHY_ecsrs_CfoResultRead
- .text 0x100cde85 0x189 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
- 0x100cde85 0x186 _zPHY_edla_CalcPcfichRegFilePara
- 0x100ce00b 0x3 _zPHY_edla_PcfichProc
- .text 0x100ce00e 0x1107 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
- 0x100ce00e 0xb7 _zPHY_ecsrs_SssStartFingerSort
- 0x100ce0c5 0xff _zPHY_ecsrs_SssFingerReorder
- 0x100ce1c4 0x49 _zPHY_ecsrs_AdjustSssFddProc
- 0x100ce20d 0x7c _zPHY_ecsrs_GetSssStartFinger
- 0x100ce289 0x37 _zPHY_ecsrs_GetNearValidTime
- 0x100ce2c0 0x33 _zPHY_ecsrs_CalSssBufferTime
- 0x100ce2f3 0x170 _zPHY_ecsrs_GetSssStartTime
- 0x100ce463 0x92 _zPHY_ecsrs_GetRfcEnableInfo
- 0x100ce4f5 0x3e _zPHY_ecsrs_GetSssStartFg
- 0x100ce533 0x50 _zPHY_ecsrs_InitSssStartInfo
- 0x100ce583 0x8f _zPHY_ecsrs_SetSssFddStartInfoAllProc
- 0x100ce612 0xb7 _zPHY_ecsrs_SetSssTddStartInfoAllProc
- 0x100ce6c9 0x251 _zPHY_ecsrs_SetSssFirstStartInfo
- 0x100ce91a 0xd9 _zPHY_ecsrs_SetSssComStartInfo
- 0x100ce9f3 0x4d _zPHY_ecsrs_GetSssStartInfo
- 0x100cea40 0x9b _zPHY_ecsrs_GetSssReadFlag
- 0x100ceadb 0xe2 _zPHY_ecsrs_GetThresholdAndFilterCell
- 0x100cebbd 0x2ae _zPHY_ecsrs_SssResultReadNew
- 0x100cee6b 0x1a7 _zPHY_ecsrs_SssResultReadAppointCell
- 0x100cf012 0x28 _zPHY_ecsrs_RecodCfoInfo
- 0x100cf03a 0x3e _zPHY_ecsrs_CheckCfoValid
- 0x100cf078 0x77 _zPHY_ecsrs_SearchForSssHwReset
- 0x100cf0ef 0x26 _zPHY_ecsrs_SetSssHwCfgTime
- .text 0x100cf115 0x172d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
- 0x100cf115 0x5 _zPHY_ecsrs_Init
- 0x100cf11a 0x17 _zPHY_ecsrs_Reset
- 0x100cf131 0x1 _zPHY_ecsrs_DebugModeInitPara
- 0x100cf132 0x24 _zPHY_ecsrs_InitCommonInfor
- 0x100cf156 0x1b _zPHY_ecsrs_DeleteAllSubFrameInt
- 0x100cf171 0x8 _zPHY_ecsrs_ResetSynInforTable
- 0x100cf179 0x30 _zPHY_ecsrs_GetIntraEarfcnInfo
- 0x100cf1a9 0x1e _zPHY_ecsrs_GetInterEarfcnInfo
- 0x100cf1c7 0x1c4 _zPHY_ecsrs_GetCommonInfor
- 0x100cf38b 0x34 _zPHY_ecsrs_CsRfcConfig
- 0x100cf3bf 0x1a _zPHY_ecsrs_BeforeInitSearch
- 0x100cf3d9 0x15 _zPHY_ecsrs_TimeRelation
- 0x100cf3ee 0x88 _zPHY_ecsrs_InterFreqChange
- 0x100cf476 0x62 _zPHY_ecsrs_GetHwConfigMode
- 0x100cf4d8 0x112 _zPHY_ecsrs_GetReadAndConfigIndex
- 0x100cf5ea 0x1e _zPHY_ecsrs_SetSyncRelation
- 0x100cf608 0x25 _zPHY_ecsrs_TFConfirmSearchMode
- 0x100cf62d 0x31 _zPHY_ecsrs_SetFilterRange
- 0x100cf65e 0xd _zPHY_ecsrs_OpenSubFrameInt
- 0x100cf66b 0xd _zPHY_ecsrs_DelSubFrameInt
- 0x100cf678 0x8 _zPHY_ecsrs_UpdateInnOffset
- 0x100cf680 0x2b _zPHY_ecsrs_ReadSearchResult
- 0x100cf6ab 0x3d _zPHY_ecsrs_GetSubTime
- 0x100cf6e8 0x31 _L1e_csrs_InitGloPara
- 0x100cf719 0x8 _zPHY_ecsrs_OnReset
- 0x100cf721 0x3 _zPHY_ecsrs_OnSearchMeasReset
- 0x100cf724 0x49 _zPHY_ecsrs_OnSearchFreqScan
- 0x100cf76d 0x81 _zPHY_ecsrs_OnSearchMeasStart
- 0x100cf7ee 0x1f _zPHY_ecsrs_OnPssUpdateCounterCnf
- 0x100cf80d 0x70 _zPHY_ecsrs_OnTimeDelayInt
- 0x100cf87d 0xd _zPHY_ecsrs_OnNotSynSubFrameInt
- 0x100cf88a 0x57 _zPHY_ecsrs_InitFreqOffset
- 0x100cf8e1 0xa6 _L1e_csrs_GetFreqOffset
- 0x100cf987 0x6e _L1e_csrs_SetFtErrorList
- 0x100cf9f5 0x65 _L1e_csrs_SetFreqOffsetAge
- 0x100cfa5a 0x11 _L1e_csrs_GetMaxAgeIndex
- 0x100cfa6b 0x2f _L1e_csrs_NormalTemp
- 0x100cfa9a 0x89 _zPHY_ecsrs_ModifyRfCfgInfo
- 0x100cfb23 0x7 _zPHY_ecsrs_setMode
- 0x100cfb2a 0xa _zPHY_ecsrs_IsIntraMode
- 0x100cfb34 0x86 _zEcsrs_PreEvent
- 0x100cfbba 0x9e _L1e_csrs_SfProc
- 0x100cfc58 0x2c _L1e_FS_SfProc
- 0x100cfc84 0x2e _zEcsrs_OnEvent
- 0x100cfcb2 0xb _zPHY_ecsrs_IsInitCs
- 0x100cfcbd 0x3c _zPHY_ecsrs_CsNeedReCfo
- 0x100cfcf9 0x16 _zPHY_ecsrs_CsNeedReSss
- 0x100cfd0f 0x67 _zPHY_ecsrs_IsRfOpen
- 0x100cfd76 0x14c _zPHY_csr_RfcConfig
- 0x100cfec2 0x1e _zPHY_ecsrs_IsOptSearch
- 0x100cfee0 0x1a _zPHY_ecsrs_CfoAccNum
- 0x100cfefa 0x1a _zPHY_ecsrs_GetConfigRfFlag
- 0x100cff14 0x3d _zPHY_ecsrs_GetScheduleFlag
- 0x100cff51 0x9 _zPHY_ecsrs_CsBeforeAgc
- 0x100cff5a 0x17 _zPHY_ecsrs_CsNeedAgc
- 0x100cff71 0x6b _zPHY_ecsrs_CsNeedPss
- 0x100cffdc 0x2 _zPHY_ecsrs_CsNeedCfo
- 0x100cffde 0x82 _zPHY_ecsrs_CsNeedSss
- 0x100d0060 0x16 _zPHY_ecsrs_CsNeedTempComp
- 0x100d0076 0x26 _zPHY_ecsrs_CsIsOnAgc
- 0x100d009c 0x37 _zPHY_ecsrs_CsAgcProc
- 0x100d00d3 0x1 _zPHY_ecsrs_CsAgcProcEnd
- 0x100d00d4 0xd _zPHY_ecsrs_CsNeedPssAgain
- 0x100d00e1 0x17 _zPHY_ecsrs_CsBeforePss
- 0x100d00f8 0x1a _zPHY_ecsrs_CsIsOnPss
- 0x100d0112 0x91 _zPHY_ecsrs_CsGetPssRfCfgInfo
- 0x100d01a3 0x50 _zPHY_ecsrs_SniffInterFreqChange
- 0x100d01f3 0x13b _zPHY_ecsrs_CsPssProc
- 0x100d032e 0xda _zPHY_ecsrs_CsPssProcEnd
- 0x100d0408 0x2a _zPHY_ecsrs_CsNeedMoreCfo
- 0x100d0432 0x23 _zPHY_ecsrs_CsBeforeCfo
- 0x100d0455 0x12 _zPHY_ecsrs_CsCfoTpuAdjPro
- 0x100d0467 0x14 _zPHY_ecsrs_CsIsOnCfo
- 0x100d047b 0x6f _zPHY_ecsrs_CsCfoProc
- 0x100d04ea 0x60 _zPHY_ecsrs_CsCfoProcEnd
- 0x100d054a 0x13 _zPHY_ecsrs_CsBeforeSss
- 0x100d055d 0x1a _zPHY_ecsrs_CsIsOnSss
- 0x100d0577 0x8d _zPHY_ecsrs_CsGetSssRfCfgInfo
- 0x100d0604 0x12d _zPHY_ecsrs_CsSssProc
- 0x100d0731 0x1d _zPHY_ecsrs_InitSearchCnf
- 0x100d074e 0x56 _zPHY_ecsrs_CsSssProcEnd
- 0x100d07a4 0x18 _zPHY_ecsrs_CsNeedCs
- 0x100d07bc 0x1a _zPHY_ecsrs_CsBeforeCs
- 0x100d07d6 0xb _zPHY_ecsrs_WaitSubFrameInt
- 0x100d07e1 0x1c _zPHY_ecsrs_SSSearctT
- 0x100d07fd 0x3d _zPHY_ecsrs_CheckSssCount
- 0x100d083a 0x8 _zPHY_ecsrs_SetSssHwRestartCnt
- .text 0x100d0842 0x3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_ti.o)
- .text 0x100d087e 0x458 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
- 0x100d087e 0x13 _zPHY_ecsrs_HwIntHandle
- 0x100d0891 0x49 _zPHY_ecsrs_HwReset
- 0x100d08da 0x33 _zPHY_ecsrs_AllHwReset
- 0x100d090d 0x15 _zPHY_ecsr_HwSssTdCommonReset
- 0x100d0922 0xa3 _zPHY_ecsrs_ConfigIcFiFoHw
- 0x100d09c5 0x8a _zPHY_ecsrs_ConfigIcHw
- 0x100d0a4f 0x4f _zPHY_ecsrs_ConfigPssHw
- 0x100d0a9e 0x36 _zPHY_ecsrs_ConfigCfoHw
- 0x100d0ad4 0x47 _zPHY_ecsrs_ConfigSssHw
- 0x100d0b1b 0xc _zPHY_ecsrs_CfgTopClkGating
- 0x100d0b27 0x14 _zPHY_ecsrs_CfgTopReg
- 0x100d0b3b 0x27 _zPHY_ecsrs_SssCfgPschLocalSeq
- 0x100d0b62 0x31 _zPHY_ecsrs_AgcBalanceCfgRegs
- 0x100d0b93 0xc _zPHY_ecsrs_AgcBalanceDisable
- 0x100d0b9f 0x23 _zPHY_ecsrc_SwClkGateCtrl
- 0x100d0bc2 0x49 _zPHY_ecsr_ConvertFinger
- 0x100d0c0b 0x1f _zPHY_ecsr_GetHwPssFinger
- 0x100d0c2a 0x8 _zPHY_ecsr_GetHwPssFreqInd
- 0x100d0c32 0xd _zPHY_ecsr_GetHwPssDoneMark
- 0x100d0c3f 0xd _zPHY_ecsr_GetHwPssNumHalfFrame
- 0x100d0c4c 0x3 _zPHY_ecsr_GetHwPssPeakValid
- 0x100d0c4f 0x8 _zPHY_ecsr_GetHwPssMaxPower
- 0x100d0c57 0xa _zPHY_ecsr_GetHwCfoOutput
- 0x100d0c61 0x10 _zPHY_ecsr_GetHwSssPeakList
- 0x100d0c71 0xa _zPHY_ecsr_GetHwSssComResult
- 0x100d0c7b 0xb _zPHY_ecsr_GetHwSssProcCount
- 0x100d0c86 0xb _zPHY_ecsr_GetHwSssProcStatus
- 0x100d0c91 0xd _zPHY_ecsr_GetHwSssProcEnable
- 0x100d0c9e 0x8 _zPHY_ecsr_GetHwSssProcRdWrState
- 0x100d0ca6 0x8 _zPHY_ecsr_GetHwIcWorkState
- 0x100d0cae 0x8 _zPHY_ecsr_GetHwTopClkGating
- 0x100d0cb6 0x8 _zPHY_ecsr_GetHwPssClkGatingBypass
- 0x100d0cbe 0x8 _zPHY_ecsr_GetHwIcClkGatingBypass
- 0x100d0cc6 0x8 _zPHY_ecsr_GetHwSssClkGatingEn
- 0x100d0cce 0x8 _zPHY_ecsr_GetHwSssWorkStatus
- .text 0x100d0cd6 0x571 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_fs.o)
- 0x100d0cd6 0x2f _L1e_FS_LogAddSearchResult
- 0x100d0d05 0x25 _L1e_FS_LogAddSearchResultFail
- 0x100d0d2a 0x14 _L1e_FS_LogGainCompenError
- 0x100d0d3e 0x17 _L1e_FS_LogMinAgcGainError
- 0x100d0d55 0x17 _L1e_FS_LogDeleteEarfcn
- 0x100d0d6c 0x2d _L1e_FS_LogSssResult
- 0x100d0d99 0x17 _L1e_FS_LogFsResultNum
- 0x100d0db0 0x1e _L1e_FS_LogDeleteFreqPoint
- 0x100d0dce 0x5c _L1e_FS_LogBandInfo
- 0x100d0e2a 0x40 _L1e_FS_LogProfileInfo
- 0x100d0e6a 0x38 _L1e_FS_LogInsertPSSResult
- 0x100d0ea2 0x54 _L1e_FS_LogAddSearchwEarfcn
- 0x100d0ef6 0x21 _L1e_FS_LogPlmnReturnSrvCell
- 0x100d0f17 0x95 _L1e_FS_LogPSSFinger
- 0x100d0fac 0x14 _L1e_FS_LogPSSNoValidEarfcn
- 0x100d0fc0 0x22 _L1e_FS_LogResultNULL
- 0x100d0fe2 0x1d _L1e_FS_LogChangeAgc
- 0x100d0fff 0x1a _L1e_FS_LogAllAgcFail
- 0x100d1019 0x14 _L1e_FS_LogReqMsgError
- 0x100d102d 0x41 _L1e_FS_LogSegmeantInfo
- 0x100d106e 0x31 _L1e_FS_LogSssAgcGain
- 0x100d109f 0x26 _L1e_FS_LogMpInfo
- 0x100d10c5 0x5b _L1e_FS_LogProGainInfo
- 0x100d1120 0x1d _L1e_FS_LogAGCInfo
- 0x100d113d 0x4a _L1e_FS_LogProRedo100KInfo
- 0x100d1187 0x1d _L1e_FS_StartAGC
- 0x100d11a4 0x2a _L1e_FS_AGCInfo
- 0x100d11ce 0x27 _L1e_FS_TestInfo
- 0x100d11f5 0x1e _L1e_FS_LogBackup100KResult
- 0x100d1213 0x17 _L1e_FS_LogFreqOffsetIndex
- 0x100d122a 0x1d _zPHY_ecsc_LogPss100KResult
- .text 0x100d1247 0x10f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrs.o)
- 0x100d1247 0x35 _zPHY_ecsrc_LogSlaveSearchMode
- 0x100d127c 0x34 _zPHY_ecsrc_LogRecvUpdateCounterCnf
- 0x100d12b0 0x64 _zPHY_ecsrc_LogPssTpuAdjust3
- 0x100d1314 0x26 _zPHY_ecsrc_LogModifyRfCfgInfo
- 0x100d133a 0x85 _zPHY_ecsrc_LogIsRfOpen
- 0x100d13bf 0x4f _zPHY_ecsrs_LogCommonInfor
- 0x100d140e 0x36 _zPHY_ecsrs_LogInterFreqChange
- 0x100d1444 0x2e _zPHY_ecsrs_LogGetHwConfigMode
- 0x100d1472 0x34 _zPHY_ecsrs_LogGetReadAndConfigIndex
- 0x100d14a6 0x18 _zPHY_ecsrs_LogTFConfirmSearchMode
- 0x100d14be 0x19 _zPHY_ecsrs_LogGetSubTime
- 0x100d14d7 0x16 _zPHY_ecsrs_LogSubFrameOnOff
- 0x100d14ed 0xba _zPHY_ecsrs_LogCsPssPro
- 0x100d15a7 0x48 _zPHY_ecsrs_LogGetPssStartTime
- 0x100d15ef 0x14 _zPHY_ecsrs_LogCsCfoProcEnd
- 0x100d1603 0x9a _zPHY_ecsrs_LogCsSssPro
- 0x100d169d 0x3e _zPHY_ecsrpss_LogAdjustPssStartTime
- 0x100d16db 0x1c _zPHY_ecsrpss_LogUrfcnFreqIdx
- 0x100d16f7 0x57 _zPHY_ecsrpss_LogSearchResult
- 0x100d174e 0x5f _zPHY_ecsrpss_LogPssDb
- 0x100d17ad 0x1b _zPHY_ecsrpss_LogSendRfcOffset
- 0x100d17c8 0x2a _zPHY_ecsrpss_LogCalRedoCfoBoundary
- 0x100d17f2 0x2a _zPHY_ecsrpss_LogFilterFinger
- 0x100d181c 0x4d _zPHY_ecsrSss_LogStartFinger
- 0x100d1869 0x3c _zPHY_ecsrSss_LogStartTime
- 0x100d18a5 0x4f _zPHY_ecsrSss_LogStartFingerAll
- 0x100d18f4 0x4a _zPHY_ecsrSss_LogSLAVE_HWStart
- 0x100d193e 0x22 _zPHY_ecsrSss_LogGetRfcEnableInfo
- 0x100d1960 0x27 _zPHY_ecsrSss_LogReadFlagInfor
- 0x100d1987 0xc5 _zPHY_ecsrSss_LogThreshold
- 0x100d1a4c 0x5d _zPHY_ecsrSss_LogResultInfo
- 0x100d1aa9 0x65 _zPHY_ecsrSss_LogSssFingerReorder
- 0x100d1b0e 0x18 _zPHY_ecsrSss_LogAdjustSssFddProc
- 0x100d1b26 0x2e _zPHY_ecsrSss_LogSssState
- 0x100d1b54 0x62 _zPHY_ecsrSss_LogStartFingerAfterSort
- 0x100d1bb6 0x14 _zPHY_ecsrSss_LogGetSssStartInfo
- 0x100d1bca 0x27 _zPHY_ecsrCfo_LogFreqOffset
- 0x100d1bf1 0x6a _zPHY_ecsrCfo_LogSLAVE_HWStart
- 0x100d1c5b 0x28 _zPHY_ecsrCfo_LogCfoResultMerge
- 0x100d1c83 0x41 _zPHY_ecsrIc_LogCellFlag
- 0x100d1cc4 0x7e _zPHY_ecsrIc_LogCoverInfo
- 0x100d1d42 0x60 _zPHY_ecsrIc_LogCellInfo
- 0x100d1da2 0xa9 _zPHY_ecsrs_LogCfgIcFifo
- 0x100d1e4b 0x191 _zPHY_ecsrs_LogCfgIc
- 0x100d1fdc 0x136 _zPHY_ecsrs_LogCfgPssHw
- 0x100d2112 0x5f _zPHY_ecsrs_LogCfgCfoHw
- 0x100d2171 0x138 _zPHY_ecsrs_LogCfgSssHw
- 0x100d22a9 0x20 _zPHY_ecsrSss_LogCheckCfoValid
- 0x100d22c9 0x2d _L1e_csrs_LogSetFtErrorList
- 0x100d22f6 0x25 _L1e_csrs_LogSetFreqOffsetAge
- 0x100d231b 0x1e _L1e_csrs_LogGetFreqOffset
- .text 0x100d2339 0x4e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_list.o)
- 0x100d2339 0x1c _zPHY_ecsrs_ListInsert
- 0x100d2355 0x5 _zPHY_ecsrs_ListAdd
- 0x100d235a 0x1a _zPHY_ecsrs_ListDelete
- 0x100d2374 0x3 _zPHY_ecsrs_ListFirst
- 0x100d2377 0x3 _zPHY_ecsrs_ListLast
- 0x100d237a 0x2 _zPHY_ecsrs_ListNext
- 0x100d237c 0x3 _zPHY_ecsrs_ListPrev
- 0x100d237f 0x8 _zPHY_ecsrs_IsListEmpty
- .text 0x100d2387 0x9c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(crepool.o)
- 0x100d2387 0x9c _s_create_pool
- .text 0x100d2423 0x20 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cresem.o)
- 0x100d2423 0x20 _create_sem
- .text 0x100d2443 0x9 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(current.o)
- 0x100d2443 0x9 _current_process
- .text 0x100d244c 0x50 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(delay.o)
- 0x100d244c 0x50 _delay
- .text 0x100d249c 0x63 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(free.o)
- 0x100d249c 0x63 _free_buf
- .text 0x100d24ff 0x49 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(get_pri.o)
- 0x100d24ff 0x49 _get_pri
- .text 0x100d2548 0x8 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(getticks.o)
- 0x100d2548 0x8 _get_ticks
- .text 0x100d2550 0x4c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(killsem.o)
- 0x100d2550 0x4c _kill_sem
- .text 0x100d259c 0x7c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(receive.o)
- 0x100d259e 0x7a _receive
- .text 0x100d2618 0xc7 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(s_allnil.o)
- 0x100d261a 0xc5 _s_alloc_nil
- .text 0x100d26df 0x16 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sender.o)
- 0x100d26df 0x16 _sender
- .text 0x100d26f5 0x116 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(set_pri.o)
- 0x100d26f5 0x77 _set_pri
- 0x100d276c 0x9f _set_ot_pri
- .text 0x100d280b 0x31 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(signsem.o)
- 0x100d280b 0x31 _signal_sem
- .text 0x100d283c 0x65 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(start.o)
- 0x100d283c 0x65 _start
- .text 0x100d28a1 0x1c5 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o)
- 0x100d28a1 0xa _zcos_sysd_init
- 0x100d28ab 0x5b _odo_kill_proc
- 0x100d2906 0x39 _odo_hunt_kill_proc
- 0x100d293f 0x7b _odo_new_process
- 0x100d29ba 0x34 _odo_hunt_request_local
- 0x100d29ee 0x55 _ose_sysd_handle_signal
- 0x100d2a43 0x23 _zcos_sysd
- .text 0x100d2a66 0x83 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(timer.o)
- 0x100d2a66 0x83 _tick
- .text 0x100d2ae9 0x4c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(waitsem.o)
- 0x100d2ae9 0x4c _wait_sem
- .text 0x100d2b35 0xfa T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o)
- 0x100d2b35 0x36 _odo_hunt_find_name
- 0x100d2b6b 0xc4 _hunt
- .text 0x100d2c2f 0x43 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(restore.o)
- 0x100d2c2f 0x43 _restore
- .text 0x100d2c72 0x98 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send_w_s.o)
- 0x100d2c72 0x98 _send_w_s
- .text 0x100d2d0a 0x5b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_efuse.o)
- 0x100d2d0a 0x5b _zDrvEfuse_IsSpe
- .text 0x100d2d65 0x4f C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(32.o)
- 0x100d2d65 0xf ___modhi3
- 0x100d2d74 0x19 ___umodhi3
- 0x100d2d8d 0x11 ___divhi3
- 0x100d2d9e 0x16 ___udivhi3
- .text 0x100d2db4 0xd C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(adddf3_v2.o)
- 0x100d2db4 0xd ___adddf3_v2
- .text 0x100d2dc1 0x29 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(div.o)
- 0x100d2dc9 0x21 ___divqi3
- .text 0x100d2dea 0x29 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(divzi3_v2.o)
- 0x100d2dea 0x29 ___divzi3_v2
- *fill* 0x100d2e13 0x80000001 00
- .text 0x100d2e14 0x19e C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_Add.o)
- 0x100d2e14 0x19e ___addsf3
- .text 0x100d2fb2 0x2a C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_compare_IEEE.o)
- 0x100d2fb2 0x0 ___gehf2
- 0x100d2fb2 0x0 ___nehf2
- 0x100d2fb2 0x0 ___eqhf2
- 0x100d2fb2 0x0 ___lthf2
- 0x100d2fb2 0x0 ___gthf2
- 0x100d2fb2 0x2a ___lehf2
- .text 0x100d2fdc 0x2a C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_convert.o)
- 0x100d2fdc 0x1e ___floatunshihf2
- 0x100d2ffa 0xc ___floathihf2
- .text 0x100d3006 0x18 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_convertqi.o)
- 0x100d3006 0xb ___floatqihf2
- 0x100d3011 0xd ___floatunsqihf2
- .text 0x100d301e 0x112 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_Div.o)
- 0x100d301e 0x112 ___divsf3
- .text 0x100d3130 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_ftou.o)
- 0x100d3130 0x17 ___ieee754_ftou
- .text 0x100d3147 0xe1 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_Mul.o)
- 0x100d3147 0x0 ___ieee754_mul
- 0x100d3147 0xe1 ___mulsf3
- .text 0x100d3228 0x6b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_pnan.o)
- 0x100d3228 0x6b ___ieee754_propagate_nan
- *fill* 0x100d3293 0x80000001 00
- .text 0x100d3294 0x1ab C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ie_Sub.o)
- 0x100d3294 0x1ab ___subsf3
- .text 0x100d343f 0xf C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcmp.o)
- 0x100d343f 0xf _memcmp
- .text 0x100d344e 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcpy16.o)
- 0x100d344f 0x11 ___memcpy16
- .text 0x100d3460 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcpy.o)
- 0x100d3465 0x10 _memcpy
- .text 0x100d3475 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memset.o)
- 0x100d3476 0x14 _memset
- .text 0x100d348a 0x21 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(mod.o)
- 0x100d348a 0x21 ___modqi3
- .text 0x100d34ab 0x27 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(modzi3_v2.o)
- 0x100d34ab 0x27 ___modzi3_v2
- .text 0x100d34d2 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(sprintf.o)
- 0x100d34d2 0x15 _sprintf
- .text 0x100d34e7 0xf C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strchr.o)
- 0x100d34e7 0xf _strchr
- *fill* 0x100d34f6 0x80000002 00
- .text 0x100d34f8 0x7 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strcmp.o)
- 0x100d34f8 0x7 _strcmp
- .text 0x100d34ff 0x6 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strcpy.o)
- 0x100d34ff 0x6 _strcpy
- .text 0x100d3505 0xe C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strlen.o)
- 0x100d3505 0xe _strlen
- .text 0x100d3513 0xd C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(subdf3_v2.o)
- 0x100d3513 0xd _(short, bool __restrict, double, float, _v2)
- .text 0x100d3520 0x7 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(udiv.o)
- 0x100d3520 0x7 ___udivqi3
- .text 0x100d3527 0x21 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(udivzi3_v2.o)
- 0x100d3527 0x21 ___udivzi3_v2
- .text 0x100d3548 0x8 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(umod.o)
- 0x100d3548 0x8 ___umodqi3
- .text 0x100d3550 0x1d C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(umodzi3_v2.o)
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+ 0x10009c50 0x5e _L1_DevRxFpachRel
+ 0x10009cae 0x48 _L1_DevRtxIntraCellCfg
+ 0x10009cf6 0x34 _L1_DevRtxHandleRxInt
+ 0x10009d2a 0xe1 _L1_DevRtxHandleFpachInt
+ 0x10009e0b 0x153 _L1_DevRtxHandleMcheInt
+ 0x10009f5e 0x135 _L1_DevRtxHandleJdcoreInt
+ 0x1000a093 0xd9 _L1_DevRtxHandlePichData
+ 0x1000a16c 0x56 _L1_DevRtxCalcPi
+ 0x1000a1c2 0x2c _L1_DevRtxHandleHwacdInt
+ 0x1000a1ee 0xa1 _L1_DevRtxHandleEhichInt
+ 0x1000a28f 0x121 _L1_DevRtxHandleTfciInt
+ 0x1000a3b0 0x3b _L1_DevRtxHandleTtiInt
+ 0x1000a3eb 0xc _L1_DevRtxCalcMinCode
+ 0x1000a3f7 0x25 _L1_DevRtxCalWinNo
+ 0x1000a41c 0xae _L1_DevRtxCalcDstData
+ 0x1000a4ca 0x55 _L1_DevRtxSelectMcheData
+ 0x1000a51f 0x2a7 _L1_DevRtxCalcSir
+ 0x1000a7c6 0x51 _L1_DevRtxCalcRscp
+ 0x1000a817 0x1c _L1_DevRtxCalcActiveCodeNum
+ 0x1000a833 0x2d _L1_DevRtxCalcAcd
+ 0x1000a860 0x3a _L1_DevRtxMcheShift
+ 0x1000a89a 0x3f _L1_DevRtxCalcWinPower
+ 0x1000a8d9 0xd9 _L1_DevRtxCalcDataFoe
+ 0x1000a9b2 0x15 _L1_DevRtxGetLowTwoCode
+ 0x1000a9c7 0x64 _L1_DevRtxRxBchDataReport
+ 0x1000aa2b 0x198 _L1_DevRtxHandleTrchOut
+ 0x1000abc3 0x14 _L1_DevRtxRxCalcCrcOkTbNum
+ 0x1000abd7 0x7b _L1_DevRtxRxDlTrchDataReport
+ 0x1000ac52 0x84 _L1_DevRtxCmpPchUeId
+ 0x1000acd6 0x3c9 _L1_DevRtxHandleCctrchOut
+ 0x1000b09f 0x4a _L1_DevCalcHsdschPhyInfo
+ 0x1000b0e9 0x31 _L1_RtxCalcCommonWinNo
+ 0x1000b11a 0xf _L1_RtxCalcCodeNum
+ 0x1000b129 0xe _L1_DevRtxCalcLastCode
+ 0x1000b137 0x10 _L1_RtxCalcMinRm
+ 0x1000b147 0x58 _L1_DevRxGetTpcSs
+ 0x1000b19f 0x1a _L1_DevRtxJudgeChannel
+ 0x1000b1b9 0x43 _L1_DevRtxSetSirForMeas
+ 0x1000b1fc 0x58 _L1_DevRtxSetSirForDs
+ 0x1000b254 0x12c _L1_DevRtxSetSirForPc
+ 0x1000b380 0x21 _L1_RxRefreshDchPara
+ 0x1000b3a1 0x34 _L1_DevRtxSirGet
+ 0x1000b3d5 0xb8 _L1_DevRtxHsDschCfg
+ 0x1000b48d 0xd _L1_DevRxMoveCctrchPara
+ 0x1000b49a 0x45 _L1_DevRxSelectMaxSir
+ 0x1000b4df 0x2b _L1_DevRxGetCctrchCellInfo
+ 0x1000b50a 0xbe _L1_DevRtxDchDtxChkNullFrm
+ 0x1000b5c8 0xdc _L1_DevRtxDchDtxChkSBFrm
+ 0x1000b6a4 0x33 _L1_DevRtxDchDtxStateUpdate
+ 0x1000b6d7 0x73 _L1_DevRtxDchDtxCalcSBBit
+ 0x1000b74a 0x18 _L1_DevRtxDchDtxSBBitErrCnt
+ 0x1000b762 0x45 _L1_DevRtxDchDtxIsDtxNullFrm
+ 0x1000b7a7 0xa _L1_DevRtxRxSfn2Ssfn
+ .text 0x1000b7b1 0x11a8 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rtx.o)
+ 0x1000b7b1 0xf _L1_DevRtxReset
+ 0x1000b7c0 0xf _L1_DevRtxInit
+ 0x1000b7cf 0x62 _L1_DevRtxBchConfigReq
+ 0x1000b831 0x39 _L1_DevRtxPichConfigReq
+ 0x1000b86a 0x39 _L1_DevRtxPchConfigReq
+ 0x1000b8a3 0x2b _L1_DevRtxUppchConfigReq
+ 0x1000b8ce 0x50 _L1_DevRtxFpachConfigReq
+ 0x1000b91e 0x39 _L1_DevRtxFachConfigReq
+ 0x1000b957 0x33 _L1_DevRtxUldchConfigReq
+ 0x1000b98a 0x44 _L1_DevRtxDldchConfigReq
+ 0x1000b9ce 0x21 _L1_DevRtxUlResetReq
+ 0x1000b9ef 0x21 _L1_DevRtxDlResetReq
+ 0x1000ba10 0x2a _L1_DevRtxBchInfoInd
+ 0x1000ba3a 0x26 _L1_DevRtxPichInd
+ 0x1000ba60 0x26 _L1_DevRtxFpachDetectInd
+ 0x1000ba86 0x21 _L1_DevRtxRachFinishInd
+ 0x1000baa7 0x3b _L1_DevRtxUppchPcCfg
+ 0x1000bae2 0x3a _L1_DevRtxFpachPcCnf
+ 0x1000bb1c 0x3b _L1_DevRtxPrachPcCfg
+ 0x1000bb57 0x21 _L1_DevRtxRachAbort
+ 0x1000bb78 0x24 _L1_DevRtxFachAbort
+ 0x1000bb9c 0x1e9 _L1_DevRtxHardIntInd
+ 0x1000bd85 0x7c _L1_DevRtxEagchRcvReq
+ 0x1000be01 0x70 _L1_DevRtxHsscchRcvReq
+ 0x1000be71 0x50 _L1_DevRtxHssichSendReq
+ 0x1000bec1 0x63 _L1_DevRtxEhichRcvReq
+ 0x1000bf24 0x63 _L1_DevRtxHsDschRcvReq
+ 0x1000bf87 0x29 _L1_DevRtxDchSyncStartReq
+ 0x1000bfb0 0x21 _L1_DevRtxDchSyncStopReq
+ 0x1000bfd1 0x21 _L1_DevRtxPcTxEnReq
+ 0x1000bff2 0x21 _L1_DevRtxPcTxDisEnReq
+ 0x1000c013 0x45 _L1_DevRtxDsInit
+ 0x1000c058 0x54 _L1_DevRtxDsSaveSIR
+ 0x1000c0ac 0x84 _L1_DevRtxDsSaveCRC
+ 0x1000c130 0xa9 _L1_DevRtxDsStep1Handle
+ 0x1000c1d9 0x48 _L1_DevRtxDsStep2SbSirCalc
+ 0x1000c221 0x37 _L1_DevRtxDsStep2SirCalc
+ 0x1000c258 0x57 _L1_DevRtxDsStep2TdmSirCalc
+ 0x1000c2af 0x29 _L1_DevRtxDsStep2CrcCalc
+ 0x1000c2d8 0x136 _L1_DevRtxDsStep2Handle
+ 0x1000c40e 0xaf _L1_DevRtxDsStartWorking
+ 0x1000c4bd 0xa9 _L1_DevRtxDsHandle
+ 0x1000c566 0xb7 _L1_DevRtxCmnRecMsgProc
+ 0x1000c61d 0x5b _L1_DevRtxRxPcchBitRead
+ 0x1000c678 0x3e _L1_DevRtxRxImsiGsm
+ 0x1000c6b6 0x2f _L1_DevRtxRxTmsiGsm
+ 0x1000c6e5 0x2f _L1_DevRtxRxPTmsiGsm
+ 0x1000c714 0xf _L1_DevRtxRxImsiDs41
+ 0x1000c723 0xf _L1_DevRtxRxTmsiDs41
+ 0x1000c732 0x3d _L1_DevRtxRxPagRecCnId
+ 0x1000c76f 0x44 _L1_DevRtxRxPagRecUtranId
+ 0x1000c7b3 0x4e _L1_DevRtxRxPagRec2UtranSingUeId
+ 0x1000c801 0x28 _L1_DevRtxRxPagRec2UtranGrpId
+ 0x1000c829 0x28 _L1_DevRtxRxPagingRecList
+ 0x1000c851 0x28 _L1_DevRtxRxPagingRec2ListR5
+ 0x1000c879 0x12 _L1_DevRtxRxPagingV590ExtIE
+ 0x1000c88b 0x10 _L1_DevRtxRxPagingV860ExtIE
+ 0x1000c89b 0x47 _L1_DevRtxRxPagingType1
+ 0x1000c8e2 0x19 _L1_DevRtxRxPcchMsgType
+ 0x1000c8fb 0x17 _L1_DevRtxRxDecodePcch
+ 0x1000c912 0x47 _L1_RtxTask
+ .text 0x1000c959 0x2154 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hsdpa.o)
+ 0x1000c959 0x2c _L1_DevHsdpaCalc2ndRmEini
+ 0x1000c985 0x33 _L1_DevHsdpaCalcCodeBlockPara
+ 0x1000c9b8 0x1e _L1_DevHsdpaCalc1stRmPara
+ 0x1000c9d6 0xfa _L1_DevHsdpaCalcRmPara
+ 0x1000cad0 0xea _L1_DevHsdpaCalcHdtrPara
+ 0x1000cbba 0x4d _L1_DevHsdpaCalcCqiDelta
+ 0x1000cc07 0x7a _L1_DevHsdpaSetHarqInfo
+ 0x1000cc81 0x6a _L1_DevHsdpaSetHssichSendInf
+ 0x1000cceb 0x38 _L1_DevHsdpaSetHssichAckInf
+ 0x1000cd23 0x3b _L1_DevHsdpaSetHssichCqiInf
+ 0x1000cd5e 0x30 _L1_DevHsdpaClrHssichSendInf
+ 0x1000cd8e 0x44 _L1_DevHsdpaGetHssichSendInf
+ 0x1000cdd2 0x70 _L1_DevHsdpaSearchHssichSendInf
+ 0x1000ce42 0x23 _L1_DevHsdpaHssichSendInfReset
+ 0x1000ce65 0x22 _L1_DevHsdpaHssichSendInfInit
+ 0x1000ce87 0x66 _L1_DevHsdpaReset
+ 0x1000ceed 0x27 _L1_DevHsdpaNvInit
+ 0x1000cf14 0x5a _L1_DevHsdpaParaInit
+ 0x1000cf6e 0x37 _L1_DevHsdpaInit
+ 0x1000cfa5 0x19 _L1_DevHsdpaSetHdtrCallback
+ 0x1000cfbe 0xa _L1_DevHsdpaSetGdtrCallback
+ 0x1000cfc8 0x1f1 _L1_DevHsdpaConfigProc
+ 0x1000d1b9 0x29 _L1_DevHsdpaReleaseProc
+ 0x1000d1e2 0x22 _L1_DevHsdpaIntraCellIndProc
+ 0x1000d204 0xf _L1_DevHsdpaHarqNewDataPrint
+ 0x1000d213 0xe2 _L1_DevHsdpaGetHsdschResInfo
+ 0x1000d2f5 0x1e _L1_DevHsdpaDelta2Change2One
+ 0x1000d313 0x1c _L1_DevHsdpaDelta2Change2Two
+ 0x1000d32f 0xda _L1_DevHsdpaCalDelta2
+ 0x1000d409 0x8c _L1_DevHsdpaHsscchIndProc
+ 0x1000d495 0x11 _L1_DevHsdpaDschDataCheck
+ 0x1000d4a6 0x6c _L1_DevHsdpaHdtrTtiIntPrint
+ 0x1000d512 0x160 _L1_DevHsdpaHdtrTtiIntProc
+ 0x1000d672 0x43 _L1_DevHsdpaCalcCqiSnr
+ 0x1000d6b5 0x2b _L1_DevHsdpaCalcCqiRefPoint
+ 0x1000d6e0 0xe _L1_DevHsdpaCalCqiTbs
+ 0x1000d6ee 0x17 _L1_DevHsdpaCalCqiRtbs
+ 0x1000d705 0x2 _L1_DevHsdpaFixRmf
+ 0x1000d707 0x136 _L1_DevHsdpaHdtrCqiIntProc
+ 0x1000d83d 0x28 _L1_DevHsdpaCfgHdtr
+ 0x1000d865 0x65 _L1_DevHsdpaCfgHdtrTpuIntProc
+ 0x1000d8ca 0xd _L1_DevHsdpaDmaIntProc
+ 0x1000d8d7 0x33 _L1_DevHsdpaConfigReq
+ 0x1000d90a 0x21 _L1_DevHsdpaRelReq
+ 0x1000d92b 0x2d _L1_DevHsdpaHsscchInd
+ 0x1000d958 0x26 _L1_DevHsdpaHdtrIntInd
+ 0x1000d97e 0x45 _L1_DevHsdpaIntraCellInd
+ 0x1000d9c3 0x30 _L1_DevHsdpaScchTypeAnalyze
+ 0x1000d9f3 0x19 _L1_DevHsdpaScchMissRecord
+ 0x1000da0c 0xcc _L1_DevHsdpaScchType1Filter
+ 0x1000dad8 0x11f _L1_DevHsdpaScchType1Proc
+ 0x1000dbf7 0xec _L1_DevHsdpaDschRecCfg
+ 0x1000dce3 0x27 _L1_DevHsdpaHsdschRcvReq
+ 0x1000dd0a 0x33 _L1_DevHsdpaPchConfigReq
+ 0x1000dd3d 0x21 _L1_DevHsdpaPchRelReq
+ 0x1000dd5e 0x33 _L1_DevHsdpaFachConfigReq
+ 0x1000dd91 0x21 _L1_DevHsdpaFachRelReq
+ 0x1000ddb2 0x21 _L1_DevHsdpaFachCellReselReq
+ 0x1000ddd3 0x29 _L1_DevHsdpaFachHrntiUpdateInd
+ 0x1000ddfc 0x21 _L1_DevHsdpaUlSyncOrderReq
+ 0x1000de1d 0x27 _L1_DevHsdpaSpsPatternInd
+ 0x1000de44 0x21 _L1_DevHsdpaSpsRelOrderReq
+ 0x1000de65 0x21 _L1_DevHsdpaDrxActOrderReq
+ 0x1000de86 0x21 _L1_DevHsdpaDrxDeactOrderReq
+ 0x1000dea7 0x21 _L1_DevHsdpaPchDschRcvInd
+ 0x1000dec8 0x26 _L1_DevHsdpaTs0ReschedInd
+ 0x1000deee 0x21 _L1_DevHsdpaFachScchDrxActiveInd
+ 0x1000df0f 0x21 _L1_DevHsdpaShareChInSyncInd
+ 0x1000df30 0x21 _L1_DevHsdpaShareChOutSyncInd
+ 0x1000df51 0x11 _L1_DevHsdpaSearchNextHssich
+ 0x1000df62 0xd7 _L1_DevHsdpaPchConfigProc
+ 0x1000e039 0x14 _L1_DevHsdpaPchRelProc
+ 0x1000e04d 0xab _L1_DevHsdpaFachConfigProc
+ 0x1000e0f8 0x14 _L1_DevHsdpaFachRelProc
+ 0x1000e10c 0xcc _L1_DevHsdpaDschRcvReqProc
+ 0x1000e1d8 0x2a _L1_DevHsdpaHsdschResInd
+ 0x1000e202 0x3f _L1_DevHsdpaDschResIndProc
+ 0x1000e241 0x19 _L1_DevHsdpaCellReSelProc
+ 0x1000e25a 0x35 _L1_DevHsdpaFachHrntiUpd
+ 0x1000e28f 0x4d _L1_DevHsdpaPchGetDschResInfo
+ 0x1000e2dc 0x5e _L1_DevHsdpaSpsGetDschResInfo
+ 0x1000e33a 0x69 _L1_DevHsdpaScch3GetDschResInfo
+ 0x1000e3a3 0x7e _L1_DevHsdpaScchOrderProc
+ 0x1000e421 0x52 _L1_DevHsdpaScchType2Filter
+ 0x1000e473 0x91 _L1_DevHsdpaScchType2Proc
+ 0x1000e504 0x48 _L1_DevHsdpaScchType3Filter
+ 0x1000e54c 0xd7 _L1_DevHsdpaScchType3Proc
+ 0x1000e623 0x24 _L1_DevHsdpaPchScchTypeAnalyze
+ 0x1000e647 0x31 _L1_DevHsdpaFachScchTypeAnalyze
+ 0x1000e678 0x51 _L1_DevHsdpaDchScchTypeAnalyze
+ 0x1000e6c9 0x2d _L1_DevHsdpaResCheck
+ 0x1000e6f6 0x1d _L1_DevHsdpaGetTs0ResState
+ 0x1000e713 0x17 _L1_DevHsdpaClrResState
+ 0x1000e72a 0x4f _L1_DevHsdpaScchType2SaveSpsInfo
+ 0x1000e779 0xbb _L1_DevHsdpaSetHarqInfoWithSps
+ 0x1000e834 0x1a _L1_DevHsdpaIsNeedSendSich
+ 0x1000e84e 0x4 _L1_DevHsdpaDschUsedTs0
+ 0x1000e852 0x55 _L1_DevHsdpaSpsSearchHarqId
+ 0x1000e8a7 0xe _L1_DevHsdpaCcsAnalyse
+ 0x1000e8b5 0x24 _L1_DevHsdpaModSub
+ 0x1000e8d9 0x1d _L1_DevHsdpaHarqHistoryInfoUpd
+ 0x1000e8f6 0x2c _L1_DevHsdpaCalcModuleType
+ 0x1000e922 0x2e _L1_DevHsdpaTs0ReschedProc
+ 0x1000e950 0x40 _L1_DevHsdpaSyncParaCfg
+ 0x1000e990 0x43 _L1_DevHsdpaInSyncCheck
+ 0x1000e9d3 0x3e _L1_DevHsdpaOutSyncCheck
+ 0x1000ea11 0x9c _L1_DevHsdpaEverySubfrmProc
+ .text 0x1000eaad 0x3ce T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls.o)
+ 0x1000eaad 0x26 _L1_DevDlsSendnitMsg
+ 0x1000ead3 0x24 _L1_DevDlsSendCnf
+ 0x1000eaf7 0x21 _L1_DevDlsReset
+ 0x1000eb18 0x15 _L1_DevDlsInit
+ 0x1000eb2d 0x15 _L1_DevDlsCsrReset
+ 0x1000eb42 0x23 _L1_DevDlsCsrInt
+ 0x1000eb65 0xa5 _L1_DevDlsTpuInt
+ 0x1000ec0a 0x80 _L1_DevDlsTimingSetReqHandle
+ 0x1000ec8a 0x1f1 _L1_DlsTask
+ .text 0x1000ee7b 0x986 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_hsupa.o)
+ 0x1000ee7b 0x36 _L1_DevPcHsupaStart
+ 0x1000eeb1 0xb _L1_DevPcHsupaStop
+ 0x1000eebc 0x17 _L1_DevPcHsupaResetDb
+ 0x1000eed3 0x50 _L1_DevPcEagchOuterCfg
+ 0x1000ef23 0x16 _L1_DevPcNonSchEpuchTpcCfg
+ 0x1000ef39 0x52 _L1_DevPcEagchInnerCfg
+ 0x1000ef8b 0xb5 _L1_DevPcEpuchCfg
+ 0x1000f040 0x4c _L1_DevPcHsupaCloseLoopPro
+ 0x1000f08c 0x31 _L1_DevPcHsupaGetRxInfo
+ 0x1000f0bd 0x65 _L1_DevPcGetEagchFromDb
+ 0x1000f122 0x5a _L1_DevPcHsupaGetEagch
+ 0x1000f17c 0x6c _L1_DevPcHsupaGetEhich
+ 0x1000f1e8 0x5e _L1_DevPcEagchOuterPro
+ 0x1000f246 0x44 _L1_DevPcEagchInnerPro
+ 0x1000f28a 0x84 _L1_DevPcEpuchTpcSsMerge
+ 0x1000f30e 0xc3 _L1_DevPcEpuchCloseLoopPro
+ 0x1000f3d1 0x1ea _L1_DevPcEpuchPro
+ 0x1000f5bb 0x91 _L1_DevPcErucchPro
+ 0x1000f64c 0x74 _L1_DevPcErucchPwr
+ 0x1000f6c0 0xf _L1_DevPcEhichTpcSsCmdToBit
+ 0x1000f6cf 0x15 _L1_DevPcGetRefBetaE
+ 0x1000f6e4 0x2b _L1_DevPcCalcUph
+ 0x1000f70f 0x30 _L1_DevPcSaveUph
+ 0x1000f73f 0x50 _L1_DevPcSetUph
+ 0x1000f78f 0x36 _L1_DevPcLinearAverage
+ 0x1000f7c5 0x2b _L1_DevPcGetSpreadingGain
+ 0x1000f7f0 0x11 _L1_DevPcSetEpuchPwr
+ .text 0x1000f801 0x216 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_comm_int.o)
+ 0x1000f801 0x2d _L1_DevDrvAllIntClear
+ 0x1000f82e 0x3b _L1_DevDrvRestoreAllInt
+ 0x1000f869 0x4e _CSR_JD_DTR_ISR
+ 0x1000f8b7 0xac _RFC_AFC_DST_ISR
+ 0x1000f963 0xc _L1T_RFC_AFC_DST_L1W_CSR_DTR_PSR_ISR
+ 0x1000f96f 0x17 _ICP_PS2TD_UPA_ISR
+ 0x1000f986 0x58 _ICP_PS2TD_WAKEUP_ISR
+ 0x1000f9de 0x28 _L1_TD_LPM_T3_ISR
+ 0x1000fa06 0x11 _DMA_ISR_0
+ .text 0x1000fa17 0x6fd T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc.o)
+ 0x1000fa17 0x28 _L1_DevPcReset
+ 0x1000fa3f 0x3d _L1_DevPcInit
+ 0x1000fa7c 0x15 _L1_DevPcErrorHandle
+ 0x1000fa91 0x99 _L1_DevPcSetRfcPwr
+ 0x1000fb2a 0x18 _L1_DevPcGetDlTpcCmd
+ 0x1000fb42 0xf _L1_DevPcDlTpc2Symbol
+ 0x1000fb51 0x4a _L1_DevPcDlpcLimit
+ 0x1000fb9b 0x17 _L1_DevPcAdjTpcSsCmd
+ 0x1000fbb2 0x14 _L1_DevPcUlOpenLoopPwr
+ 0x1000fbc6 0x7 _L1_DevPcUlCloseLoopPwr
+ 0x1000fbcd 0xb _L1_DevPcPathLossUpdate
+ 0x1000fbd8 0x121 _L1_DevPcTxReq
+ 0x1000fcf9 0xc _L1_DevPcSendOnOffToRtx
+ 0x1000fd05 0x1d _L1_DevPcErucchReq
+ 0x1000fd22 0x40 _L1_DevPcFpachCnf
+ 0x1000fd62 0x24 _L1_DevPcUlDpchReq
+ 0x1000fd86 0x1f _L1_DevPcDlDpchReq
+ 0x1000fda5 0x25 _L1_DevPcHsdpaTypeReq
+ 0x1000fdca 0x25 _L1_DevPcHsupaTypeReq
+ 0x1000fdef 0xd2 _L1_DevPcDchHspaGapPro
+ 0x1000fec1 0xc6 _L1_PcTask
+ 0x1000ff87 0x36 _L1_DevPcUlDpchCfgReq
+ 0x1000ffbd 0x43 _L1_DevPcDlDpchCfgReq
+ 0x10010000 0x7 _L1_DevPcSetTadv
+ 0x10010007 0x19 _L1_DevPcGetTadv
+ 0x10010020 0x2c _L1_DevPcTadvUpdate
+ 0x1001004c 0x3c _L1_DevPcHsupaErucchCfg
+ 0x10010088 0x35 _L1_DevPcHsdpaCfg
+ 0x100100bd 0x35 _L1_DevPcHsupaCfg
+ 0x100100f2 0x22 _L1_DevPcRtxTxReq
+ .text 0x10010114 0x4f0 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_eng.o)
+ 0x10010114 0xa7 _L1_EngTask
+ 0x100101bb 0x36 _L1_DevEngPaConfig
+ 0x100101f1 0x3c _L1_DevEngLogNVParaCfg
+ 0x1001022d 0x21 _L1_DevEngLogFilter
+ 0x1001024e 0xcb _L1_DevEngDisplay
+ 0x10010319 0x6d _L1_DevEngTrace
+ 0x10010386 0x100 _L1_DevEngWriteDataToBuffer
+ 0x10010486 0x4e _L1_DevEngDataDump
+ 0x100104d4 0x64 _L1_DevEngDmacMem2Uart
+ 0x10010538 0x19 _L1_DevEngCopyMem2Dpram
+ 0x10010551 0x2e _L1_DevEngErrorHandler
+ 0x1001057f 0x84 _L1_DevEngDmaIntProc
+ 0x10010603 0x1 _L1_DevLogFilter
+ .text 0x10010604 0x848 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_tpu.o)
+ 0x10010604 0x71 _L1_DevTpuReset
+ 0x10010675 0xe _L1_DevTpuSetAdvTime
+ 0x10010683 0xc _L1_DevTpuSetNetTime
+ 0x1001068f 0x5 _L1_DevTpuSetQuaterNetTime
+ 0x10010694 0x7 _L1_DevTpuGetQuaterNetTime
+ 0x1001069b 0xe _L1_DevTpuSubFrmSlide
+ 0x100106a9 0xe _L1_DevTpuSfnSet
+ 0x100106b7 0x2d _L1_DevTpuSetDoff
+ 0x100106e4 0x7 _L1_DevTpuGetDoff
+ 0x100106eb 0x20 _L1_DevTpuSfn2Cfn
+ 0x1001070b 0x40 _L1_DevTpuCfn2Sfn
+ 0x1001074b 0x3a _L1_DevTpuGetRealTime
+ 0x10010785 0x59 _L1_DevTpuGetSSFN
+ 0x100107de 0x57 _L1_DevTpuGetNetTime
+ 0x10010835 0x41 _L1_DevTpuGetAllTime
+ 0x10010876 0x42 _L1_DevTpuAddFixedEvent
+ 0x100108b8 0x4f _L1_DevTpuDelFixedEvent
+ 0x10010907 0x92 _L1_DevTpuAddVarChipEvent
+ 0x10010999 0x8a _L1_DevTpuDelVarChipEvent
+ 0x10010a23 0x40 _L1_DevTpuNtToRt
+ 0x10010a63 0x37 _L1_DevTpuCalNT2RTOffset
+ 0x10010a9a 0x15 _L1_DevTpuSleepFrmHeadSave
+ 0x10010aaf 0x3e _L1_DevTpuNtToRtCnt
+ 0x10010aed 0x9a _L1_DevTpuSleepWaite32KClkEdge
+ 0x10010b87 0x51 _L1_DevTpuSleepSetNtChipZero
+ 0x10010bd8 0x8 _L1_DevTpuSetSSFN
+ 0x10010be0 0x70 _L1_DevTpuSleepFrmHeadRestore
+ 0x10010c50 0x7 _L1_DevTpuSfn2Ssfn
+ 0x10010c57 0xa _L1_DevTpuCfn2Ssfn
+ 0x10010c61 0x34 _L1_DevTpuSSfnCfnUpdate
+ 0x10010c95 0xc _L1_DevTpuGapSSfnUpdate
+ 0x10010ca1 0x25 _L1_DevTpuRtSSfnUpdate
+ 0x10010cc6 0xa1 _L1_DevTpuNTEventProc
+ 0x10010d67 0x6a _L1_DevTpuRTEventProc
+ 0x10010dd1 0x11 _L1_DevTpuTaskIdTransForm
+ 0x10010de2 0x6a _TPU_ISR
+ .text 0x10010e4c 0x897 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(L1_dev_rfc_db.o)
+ 0x10010e4c 0xd _L1_DevRfcAgcDbInit
+ 0x10010e59 0x1f _L1_DevRfcAgcDbFreqPosInAgcInfo
+ 0x10010e78 0x4e _L1_DevRfcAgcDbFindOldestFreqPos
+ 0x10010ec6 0x4d _L1_DevRfcAgcDbFindFreqPos
+ 0x10010f13 0x6b _L1_DevRfcAgcDbLockCheck
+ 0x10010f7e 0x39 _L1_DevRfcAgcDbGetAgcGain
+ 0x10010fb7 0x3d _L1_DevRfcEstimDschAgc
+ 0x10010ff4 0x23 _L1_DevRfcAgcDbReliableCheck
+ 0x10011017 0x75 _L1_DevRfcAgcDbGetRssi
+ 0x1001108c 0x29 _L1_DevRfcAgcDbHspaTs0AgcSet
+ 0x100110b5 0x34 _L1_DevRfcAgcDbRdbCalcRssi
+ 0x100110e9 0x28 _L1_DevRfcAgcGetRdbRssi
+ 0x10011111 0x46 _L1_DevRfcAgcDbSet
+ 0x10011157 0x37 _L1_DevRfcAgcDbLockInfoCalc
+ 0x1001118e 0x92 _L1_DevRfcAgcDbHspaTs0AgcCalc
+ 0x10011220 0x55 _L1_DevRfcTargetAgcInfoGet
+ 0x10011275 0x98 _L1_DevRfcAgcDbAgcCalc
+ 0x1001130d 0x95 _L1_DevRfcAgcDbGetDwDelta
+ 0x100113a2 0xaa _L1_DevRfcAgcDbSetCtrlInfo
+ 0x1001144c 0x3b _L1_L1_DevRfcAgcPreFirstSlotGet
+ 0x10011487 0x4b _L1_DevRfcAgcPerGet
+ 0x100114d2 0x3e _L1_DevRfcAgcDbSaveRdbInfo
+ 0x10011510 0xc _L1_DevRfcCtrlDbInit
+ 0x1001151c 0x76 _L1_DevRfcCtrlDbFndMatchPatn
+ 0x10011592 0x62 _L1_DevRfcCtrlDbOperCodeGen
+ 0x100115f4 0x14 _L1_DevRfcCtrlDbGetLogFreq
+ 0x10011608 0x77 _L1_DevRfcCtrlDbRfcOpenMsgProc
+ 0x1001167f 0x22 _L1_DevRfcCtrlDbGetPatternInfo
+ 0x100116a1 0x42 _L1_DevRfcCtrlDbWakeUpMsgProc
+ .text 0x100116e3 0x561 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_meas.o)
+ 0x100116e3 0x40 _L1_DevMeasInit
+ 0x10011723 0x3a _L1_DevMeasReset
+ 0x1001175d 0x3e _L1_DevMeasStartRscpMeas
+ 0x1001179b 0x32 _L1_DevMeasStartIscpMeas
+ 0x100117cd 0x16f _L1_DevMeasRscpIntProc
+ 0x1001193c 0xbd _L1_DevMeasIscpIntProc
+ 0x100119f9 0x13 _L1_DevMeasIntProc
+ 0x10011a0c 0x33 _L1_DevMeasRscpMeasCnf
+ 0x10011a3f 0x32 _L1_DevMeasIscpMeasCnf
+ 0x10011a71 0x1e _L1_DevMEASRscpGrouped
+ 0x10011a8f 0x13 _L1_DevMEASIscpGrouped
+ 0x10011aa2 0x81 _L1_DevMeasTpuHandle
+ 0x10011b23 0x40 _L1_DevMeasIntInd
+ 0x10011b63 0xe1 _L1_MeasTask
+ .text 0x10011c44 0x1e12 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hsupa.o)
+ 0x10011c44 0x1a _L1_DevHsupaCalcUpperLimit
+ 0x10011c5e 0x1e _L1_DevHsupaCalcMod
+ 0x10011c7c 0x4b _L1_DevHsupaCalcMidambleUeId
+ 0x10011cc7 0x35 _L1_DevHsupaCalcCodeBlockPara
+ 0x10011cfc 0xf6 _L1_DevHsupaCalcRmPara
+ 0x10011df2 0xb4 _L1_DevHsupaCalcEutrPara
+ 0x10011ea6 0x108 _L1_DevHsupaCalcEtxPara
+ 0x10011fae 0x99 _L1_DevHsupaCalcEhichRcvPara
+ 0x10012047 0x3a _L1_DevHsupaSetEhichRcvInf
+ 0x10012081 0x27 _L1_DevHsupaClrEhichRcvInf
+ 0x100120a8 0x3a _L1_DevHsupaGetEhichRcvInf
+ 0x100120e2 0x42 _L1_DevHsupaSearchEhichRcvInf
+ 0x10012124 0xb _L1_DevHsupaEhichRcvInfReset
+ 0x1001212f 0xd _L1_DevHsupaEhichRcvInfInit
+ 0x1001213c 0x22 _L1_DevHsupaSetEpuchDataReady
+ 0x1001215e 0x22 _L1_DevHsupaClrEpuchDataReady
+ 0x10012180 0x5a _L1_DevHsupaSearchEpuchSendInf
+ 0x100121da 0xa _L1_DevHsupaEpuchDataReadyReset
+ 0x100121e4 0xa _L1_DevHsupaEpuchDataReadyInit
+ 0x100121ee 0x4f _L1_DevHsupaParaInit
+ 0x1001223d 0x6e _L1_DevHsupaReset
+ 0x100122ab 0x19 _L1_DevHsupaInit
+ 0x100122c4 0x189 _L1_DevHsupaSendDataProc
+ 0x1001244d 0x24 _L1_DevHsupaCalcNonSchEhichResId
+ 0x10012471 0x113 _L1_DevHsupaRcvEhichProc
+ 0x10012584 0x96 _L1_DevHsupaSetSchInfo
+ 0x1001261a 0x8b _L1_DevHsupaSetNonSchInfo
+ 0x100126a5 0x2b _L1_DevHsupaSetSpsInfo
+ 0x100126d0 0x34 _L1_DevHsupaSetSpsInitGrant
+ 0x10012704 0x90 _L1_DevHsupaSetSpsGrantInfo
+ 0x10012794 0x3e _L1_DevHsupaSpsEagchAnalyze
+ 0x100127d2 0x9e _L1_DevHsupaEagchType2RdiProc
+ 0x10012870 0x89 _L1_DevHsupaEagchType2NoRdiProc
+ 0x100128f9 0x27 _L1_DevHsupaSendSpsPatternInd
+ 0x10012920 0xa7 _L1_DevHsupaEagchType2RrpiProc
+ 0x100129c7 0x21 _L1_DevHsupaSendSpsRelOrder
+ 0x100129e8 0x3b _L1_DevHsupaEagchOrderProc
+ 0x10012a23 0x136 _L1_DevHsupaConfigProc
+ 0x10012b59 0x1f _L1_DevHsupaReleaseProc
+ 0x10012b78 0x2a _L1_DevHsupaByteSwitch
+ 0x10012ba2 0x3 _L1_DevHsupaClrDpramBufFlag
+ 0x10012ba5 0x3f _L1_DevHsupaEpuchDataPrint
+ 0x10012be4 0x53 _L1_DevHsupaMbxIntErucchDataProc
+ 0x10012c37 0x1a1 _L1_DevHsupaMbxIntEdchDataProc
+ 0x10012dd8 0x80 _L1_DevHsupaMbxIntProc
+ 0x10012e58 0x48 _L1_DevHsupaDmaIntProc
+ 0x10012ea0 0xf _L1_DevHsupaEutrIntProc
+ 0x10012eaf 0x66 _L1_DevHsupaEagchIsInvalid
+ 0x10012f15 0x5f _L1_DevHsupaEagchAnalyze
+ 0x10012f74 0xca _L1_DevHsupaEagchType1Proc
+ 0x1001303e 0xd4 _L1_DevHsupaEagchIndProc
+ 0x10013112 0xe9 _L1_DevHsupaEhichIndProc
+ 0x100131fb 0x32 _L1_DevHsupaRdiTti
+ 0x1001322d 0x13 _L1_DevHsupaGetSichDpchErucchTs
+ 0x10013240 0x6d _L1_DevHsupaSetSchGrantInfo
+ 0x100132ad 0x1f _L1_DevHsupaSetNonSchGrantInfo
+ 0x100132cc 0x33 _L1_DevHsupaSetHarqInfo
+ 0x100132ff 0x151 _L1_DevHsupaReportToPs
+ 0x10013450 0x16 _L1_DevHsupaReportToPsCallBack
+ 0x10013466 0x26 _L1_DevHsupaSendErucchCnf
+ 0x1001348c 0x3e _L1_DevHsupaFachSelCommonErnti
+ 0x100134ca 0xe _L1_DevHsupaFachErucchAffixErnti
+ 0x100134d8 0x26 _L1_DevHsupaSendCommonErntiInd
+ 0x100134fe 0x142 _L1_DevHsupaErucchSendProc
+ 0x10013640 0x19 _L1_DevHsupaActivateErucch
+ 0x10013659 0x1b _L1_DevHsupaAbortErucch
+ 0x10013674 0x22 _L1_DevHsupaIntraCellIndProc
+ 0x10013696 0x20 _L1_DevHsupaCalcTxOffset
+ 0x100136b6 0x54 _L1_DevHsupaGenPNSeq
+ 0x1001370a 0x2f _L1_DevHsupaConfigReq
+ 0x10013739 0x21 _L1_DevHsupaRelReq
+ 0x1001375a 0x21 _L1_DevHsupaErucchReq
+ 0x1001377b 0x21 _L1_DevHsupaErucchAbortReq
+ 0x1001379c 0x6c _L1_DevHsupaErucchSendReq
+ 0x10013808 0x2d _L1_DevHsupaEagchInd
+ 0x10013835 0x27 _L1_DevHsupaEhichInd
+ 0x1001385c 0x2c _L1_DevHsupaMbxIntInd
+ 0x10013888 0x21 _L1_DevHsupaEutrIntInd
+ 0x100138a9 0x45 _L1_DevHsupaIntraCellInd
+ 0x100138ee 0xb7 _L1_DevHsupaFachConfigProc
+ 0x100139a5 0x14 _L1_DevHsupaFachReleaseProc
+ 0x100139b9 0x31 _L1_DevHsupaFachConfigReq
+ 0x100139ea 0x21 _L1_DevHsupaFachRelReq
+ 0x10013a0b 0x10 _L1_DevHsupaEagchMissCntDebug
+ 0x10013a1b 0x3b _L1_DevHsupaGetNack
+ .text 0x10013a56 0xaa4 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_sleep.o)
+ 0x10013a56 0x28 _L1t_SetTdsLpcMacroValue
+ 0x10013a7e 0x8 _L1_DevSleepSetCfunFlg
+ 0x10013a86 0x7f _L1t_DevSleepNoLpc
+ 0x10013b05 0x7 _L1t_DevLpcSetDwFinger
+ 0x10013b0c 0x7 _L1t_DevLpcGetDwFinger
+ 0x10013b13 0x45 _L1t_DevLpcPwrCtrl
+ 0x10013b58 0x1c _L1t_DevLpcDvfs
+ 0x10013b74 0xec _L1t_DevLpcPwrFreqCtrl
+ 0x10013c60 0x3b _L1t_DevLpcIcpSendForPsm
+ 0x10013c9b 0x1b _L1t_DevLpcSendIcpInOneSfn
+ 0x10013cb6 0xf _L1t_DevLpcGetL1sRecPSMsgPerm
+ 0x10013cc5 0x46 _L1t_DevLpcWakeupRfResUpdate
+ 0x10013d0b 0x1e _L1t_DevLpcWakeDpramSfnUpdate
+ 0x10013d29 0x8 _L1t_DevLpcSetAbleToCfgPsLpm
+ 0x10013d31 0x8 _L1t_DevLpcGetAbleToCfgPsLpm
+ 0x10013d39 0xa _L1t_DevLpcGetWakeUpType
+ 0x10013d43 0x8 _L1t_DevLpcSetPiResultFlg
+ 0x10013d4b 0x8 _L1t_DevLpcGetPiResultFlg
+ 0x10013d53 0xe _L1t_DevLpcSetPreIcpFlg
+ 0x10013d61 0x8 _L1t_DevLpcGetPreIcpFlg
+ 0x10013d69 0x8 _L1t_DevLpcDrxLongFlg
+ 0x10013d71 0x16 _L1t_DevLpcRemoveSchedAgc
+ 0x10013d87 0x1 _L1t_DevLpcWakeNotAgcPro
+ 0x10013d88 0x8 _L1t_DevLpcSetQuickWakeFlg
+ 0x10013d90 0x2 _L1t_DevLpcGetQuickWakeFlg
+ 0x10013d92 0x8 _L1t_DevLpcSetMcsValidFlg
+ 0x10013d9a 0x8 _L1t_DevLpcGetMcsValidFlg
+ 0x10013da2 0x8 _L1t_DevLpcSetPichRcvPos
+ 0x10013daa 0x2 _L1t_DevLpcCheckRfQuickOpen
+ 0x10013dac 0x69 _L1t_DevLpcSendWakeRfMsg
+ 0x10013e15 0x1 _L1t_DevLpcWakeUpOpenRf
+ 0x10013e16 0x8 _L1t_DevLpcSetPorcState
+ 0x10013e1e 0x8 _L1t_DevLpcGetPorcState
+ 0x10013e26 0x7 _L1t_DevLpcSetGapInfo
+ 0x10013e2d 0x74 _L1t_DevLpcGetTdsSleepLen
+ 0x10013ea1 0x10 _L1t_DevLpcWakeupClrModemInt
+ 0x10013eb1 0x42 _L1t_DevLpcRestoreSFN
+ 0x10013ef3 0x55 _L1t_DevLpcWakeupTpuCheck
+ 0x10013f48 0x3 _L1t_DevLpcMasterWakeAhead
+ 0x10013f4b 0x73 _L1t_DevLpcCalcWakeTimeFcCc
+ 0x10013fbe 0x1 _L1t_DevLpcWdtdipPrwCtrl
+ 0x10013fbf 0x8 _L1t_GetNtSsfn
+ 0x10013fc7 0xa _L1t_DevLpcWorkSfnCnt
+ 0x10013fd1 0x7e _L1t_DevLpcInit
+ 0x1001404f 0x7d _L1t_DevLpcCfgSocWkupInt
+ 0x100140cc 0x14 _L1t_DevLpcDisSocWkupInt
+ 0x100140e0 0x17 _L1t_DevLpcSetWakeupFlag
+ 0x100140f7 0x1e3 _L1t_ModemLpcSleep
+ 0x100142da 0x220 _L1t_ModemLpcWakeup
+ .text 0x100144fa 0xb52 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_afc.o)
+ 0x100144fa 0x42 _L1_DevDlsAfcGlobInit
+ 0x1001453c 0x11 _L1_DevDlsAfcMaStart
+ 0x1001454d 0x5e _L1_DevDlsAfcProc
+ 0x100145ab 0x34 _L1_DevDlsAfcFoeAdjStatSel
+ 0x100145df 0x1b _L1_DevDlsAfcSlotIntProc
+ 0x100145fa 0xaa _L1_DevDlsAfcDataFoeProc
+ 0x100146a4 0x54 _L1_DevDlsAfcFoeCalProc
+ 0x100146f8 0x38 _L1_DevAfcNormalToAfc
+ 0x10014730 0x22 _L1_DevAfcToNormal
+ 0x10014752 0x10b _L1_DevAfcCalcPhaseErr
+ 0x1001485d 0x5c _L1_DevAfcDiv
+ 0x100148b9 0x7c _L1_DevAfcAdd
+ 0x10014935 0x1c _L1_DevAfcMultip
+ 0x10014951 0xd _L1_DevAfcCompABS
+ 0x1001495e 0x2d _L1_DevDlsAfcFactorSel
+ 0x1001498b 0xc8 _L1_DevDlsAfcReport
+ 0x10014a53 0x74 _L1_DevAfcLockCheck
+ 0x10014ac7 0x2a _L1_DevAfcLockReport
+ 0x10014af1 0x2b _L1_DevAfcSendFreqMsgToL1s
+ 0x10014b1c 0x3b _L1_DevAfcFreqAdjReport
+ 0x10014b57 0x73 _L1_DevAfcCellInfoSet
+ 0x10014bca 0x28 _L1_DevDlsAfcReset
+ 0x10014bf2 0x3e _L1_DevDlsAfcInit
+ 0x10014c30 0x9 _L1_DevAfcStartCal
+ 0x10014c39 0x9 _L1_DevAfcActive
+ 0x10014c42 0x18 _L1_DevAfcFingerCfg
+ 0x10014c5a 0x38 _L1_DevAfcMAStart
+ 0x10014c92 0x5f _L1_DevAfcMAFingerIQCal
+ 0x10014cf1 0x35 _L1_DevAfcMAFoeConfig
+ 0x10014d26 0x4a _L1_DevAfcMADel
+ 0x10014d70 0x14 _L1_DevAfcRdbReset
+ 0x10014d84 0x50 _L1_DevAfcRdbMaFoeCal
+ 0x10014dd4 0x21 _L1_DevAfcMADataStore
+ 0x10014df5 0x48 _L1_DevAfcReadMid
+ 0x10014e3d 0xf _L1_DevAfcFormatCheck
+ 0x10014e4c 0x43 _L1_DevDlsMaFoeReq
+ 0x10014e8f 0x42 _L1_DevDlsDataFoeReq
+ 0x10014ed1 0x6 _L1_DevAfcSgnData
+ 0x10014ed7 0x121 _L1_DevAfcCalcIqData
+ 0x10014ff8 0x33 _L1_DevDlsDataAdjFoeReq
+ 0x1001502b 0x21 _L1_DevDLSAFCIntInd
+ .text 0x1001504c 0xa2b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_db.o)
+ 0x1001504c 0xb7 _L1_DevDbInit
+ 0x10015103 0x23 _L1_DevDbCalcTrchCfgMaxTti
+ 0x10015126 0x3f _L1_DevDbGetTrchCfgMaxTti
+ 0x10015165 0x25 _L1_DevDbCalcTrchCfgMinTti
+ 0x1001518a 0x3f _L1_DevDbGetTrchCfgMinTti
+ 0x100151c9 0x40 _L1_DevDbSetCctrchQualitytData
+ 0x10015209 0xb _L1_DevDbClearCctrchQualitytData
+ 0x10015214 0x34 _L1_DevDbGetCctrchQualitytData
+ 0x10015248 0x35 _L1_DevDbSetEhichTpcSsInfo
+ 0x1001527d 0xbf _L1_DevDbSetRxInfo
+ 0x1001533c 0x28 _L1_DevDbGetRxInfo
+ 0x10015364 0x2e _L1_DevDbSetSbInfo
+ 0x10015392 0x2e _L1_DevDbGetSbInfo
+ 0x100153c0 0x2b _L1_DevDbSetFpachData
+ 0x100153eb 0x2b _L1_DevDbGetFpachData
+ 0x10015416 0x48 _L1_DevDbSetDchCrcInfo
+ 0x1001545e 0x2d _L1_DevDbGetDchCrcInfo
+ 0x1001548b 0x8 _L1_DevDbSetTxPcEn
+ 0x10015493 0x8 _L1_DevDbSetTxPcDisEn
+ 0x1001549b 0x7 _L1_DevDbGetTxPcEn
+ 0x100154a2 0x85 _L1_DevDbSetTxInfo
+ 0x10015527 0x2c _L1_DevDbGetTxInfo
+ 0x10015553 0x3e _L1_DevDbSetHsscchInfo
+ 0x10015591 0x34 _L1_DevDbGetHsscchInfo
+ 0x100155c5 0x3e _L1_DevDbSetEagchInfo
+ 0x10015603 0x2a _L1_DevDbGetEagchInfo
+ 0x1001562d 0x3a _L1_DevDbSetMcheData
+ 0x10015667 0x19 _L1_DevDbGetMcheDataAddr
+ 0x10015680 0x1f _L1_DevDbSetDagcResult
+ 0x1001569f 0x21 _L1_DevDbGetDagcResult
+ 0x100156c0 0x63 _L1_DevDbSetJdoutData
+ 0x10015723 0x3b _L1_DevDbGetJdoutData
+ 0x1001575e 0x1a _L1_DevDbGetJdoutAddr
+ 0x10015778 0x40 _L1_DevDbGetOneChanJdoutData
+ 0x100157b8 0x2b _L1_DevDbSetTpcSsData
+ 0x100157e3 0x2a _L1_DevDbGetTpcSsData
+ 0x1001580d 0x2b _L1_DevDbSetCodePwrData
+ 0x10015838 0x2a _L1_DevDbGetCodePwrData
+ 0x10015862 0x36 _L1_DevDbResetRxIntData
+ 0x10015898 0x18 _L1_DevDbResetTxInfo
+ 0x100158b0 0x1f _L1_DevDbResetRxCrcInfo
+ 0x100158cf 0x14 _L1_DevDbResetHsscchInfo
+ 0x100158e3 0x14 _L1_DevDbResetEagchInfo
+ 0x100158f7 0xc _L1_DevDbResetInfoForPc
+ 0x10015903 0x7 _L1_DevDbSetUlDataFlag
+ 0x1001590a 0x7 _L1_DevDbGetUlDataFlag
+ 0x10015911 0x17 _L1_DevDbResetUlDpchInfo
+ 0x10015928 0x1f _L1_DevDbResetDlDpchInfo
+ 0x10015947 0x28 _L1_DevDbResetDpchInfo
+ 0x1001596f 0x25 _L1_DevDbResetHsdpaInfo
+ 0x10015994 0x23 _L1_DevDbResetHsupaInfo
+ 0x100159b7 0xb _L1_DevDbReadRtxSirValue
+ 0x100159c2 0xc _L1_DevDbSaveRtxSirValue
+ 0x100159ce 0xc _L1_DevDbSetRtx2RfcSirFlag
+ 0x100159da 0xb _L1_DevDbGetRtx2RfcSirFlag
+ 0x100159e5 0x6 _L1_DevDbGetPageParaAddr
+ 0x100159eb 0x6 _L1_DevDbGetFachParaAddr
+ 0x100159f1 0x7 _L1_DevDbSetMeasRscp
+ 0x100159f8 0x7 _L1_DevDbGetMeasRscp
+ 0x100159ff 0x4b _L1_DevDbSetUlData
+ 0x10015a4a 0x7 _L1_DevDbSetDlDataOk
+ 0x10015a51 0x7 _L1_DevDbGetDlDataOk
+ 0x10015a58 0x7 _L1_DevDbGetUlMinTti
+ 0x10015a5f 0x6 _L1_DevDbGetUlDataAddr
+ 0x10015a65 0x9 _L1_DevDbSetSirThresIndex
+ 0x10015a6e 0x9 _L1_DevDbGetSirThresIndex
+ .text 0x10015a77 0x3c2 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_tadv.o)
+ 0x10015a77 0x10 _L1_DevPcGetTpuOffset
+ 0x10015a87 0xd7 _L1_DevPcTadvAdjProtect
+ 0x10015b5e 0x23 _L1_DevPcCctrchSsCmd
+ 0x10015b81 0x43 _L1_DevPcUlTadvPriStrategyCalc
+ 0x10015bc4 0xa _L1_DevPcUlTimingSsCmd
+ 0x10015bce 0x28 _L1_DevPcUlTimingFollowTpu
+ 0x10015bf6 0x48 _L1_DevPcUlGetTadvInit
+ 0x10015c3e 0x40 _L1_DevPcUlGetErucchTadv
+ 0x10015c7e 0x3a _L1_DevPcUlSetTadvPara
+ 0x10015cb8 0xe _L1_DevPcGetUlTadvCmd
+ 0x10015cc6 0xa4 _L1_DevPcUlAdjustTadv
+ 0x10015d6a 0x4c _L1_DevPcUlRecfgSwitchTadv
+ 0x10015db6 0x83 _L1_DevPcUlTimingPro
+ .text 0x10015e39 0x654 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_ulpwr.o)
+ 0x10015e39 0x71 _L1_DevPcUlPwrPro
+ 0x10015eaa 0x70 _L1_DevPcUlMultiChanPwrPro
+ 0x10015f1a 0x24b _L1_DevPcUlPwrGetParam
+ 0x10016165 0x95 _L1_DevPcUlTriChanPwrPro
+ 0x100161fa 0x14 _L1_DevPcUlPwrGetPwrLimit
+ 0x1001620e 0x30 _L1_DevPcPwrSetDpchScale
+ 0x1001623e 0x16 _L1_DevPcPwrSetHssichScale
+ 0x10016254 0x16 _L1_DevPcPwrSetErucchScale
+ 0x1001626a 0x31 _L1_DevPcPwrSetEpuchScale
+ 0x1001629b 0x70 _L1_DevPcUlPwrSetScale
+ 0x1001630b 0xd6 _L1_DevPcUlPwrCalcPwrScale
+ 0x100163e1 0x1e _L1_DevPcDb2Linear
+ 0x100163ff 0x19 _L1_DevPcLinear2Db
+ 0x10016418 0x75 _L1_DevPcUlPwrCalcSqrt
+ .text 0x1001648d 0x29f T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_dst.o)
+ 0x1001648d 0xad _L1_DrvDstInitial
+ 0x1001653a 0x90 _L1_DrvDstInitial2
+ 0x100165ca 0xa _L1_DrvDstRdAfcMaxPath
+ 0x100165d4 0x35 _L1_DrvDstWrAfcCellInfo
+ 0x10016609 0x52 _L1_DrvDstCfgCoarCellInfo
+ 0x1001665b 0x24 _L1_DrvDstCoarStart
+ 0x1001667f 0x2b _L1_DrvDstCfgInterf
+ 0x100166aa 0x4f _L1_DrvDstStartDwPtsSync
+ 0x100166f9 0x2a _L1_DrvDstStartMcheSync
+ 0x10016723 0x9 _L1_DrvDSTReadMaxPath
+ .text 0x1001672c 0x26b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_sleep.o)
+ 0x1001672c 0xe _L1t_DrvLpcSetSleepFlag
+ 0x1001673a 0xe _L1t_DrvLpcSetCampOnFlg
+ 0x10016748 0x10 _L1t_DrvLpcNotPageSetLpmIntTime
+ 0x10016758 0x10 _L1t_DrvLpcPageSetLpmIntTime
+ 0x10016768 0x7 _L1t_DrvLpcLpm10MIntSet
+ 0x1001676f 0x7 _L1t_DrvLpcLpm32kIntSet
+ 0x10016776 0xf _L1t_DrvLpcSocWkTimeCfg
+ 0x10016785 0xf _L1t_DrvLpcModemWkTimeCfg
+ 0x10016794 0x10 _L1t_DrvLpcSocWakeUpIntCtrl
+ 0x100167a4 0x11 _L1t_DrvLpcModemWakeUpIntCtrl
+ 0x100167b5 0xca _L1t_DrvLpcCfgModemWkupInt
+ 0x1001687f 0x8 _L1t_DrvLpcPsLpm8xClkEnCtr
+ 0x10016887 0x17 _L1t_DrvLpcCloseClk
+ 0x1001689e 0x16 _L1t_DrvLpcOpenClk
+ 0x100168b4 0xc _L1t_DrvLpcAfcAgcIntOpen
+ 0x100168c0 0xe _L1t_DrvLpcDstAfcAgcIntCls
+ 0x100168ce 0x1c _L1t_DrvLpcTdsModemIntCtrl
+ 0x100168ea 0x10 _L1t_DrvLpcGetLpmNT
+ 0x100168fa 0xe _L1t_DrvLpcGetLpmRT
+ 0x10016908 0x32 _L1t_DrvLpcModemSave
+ 0x1001693a 0x4d _L1t_DrvLpcModemStdDrxRestore
+ 0x10016987 0xf _L1t_DrvLpcModemDpaRestore
+ 0x10016996 0x1 _L1t_DrvLpcClrTopRfTpuReg
+ .text 0x10016997 0x344 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_csr.o)
+ 0x10016997 0x1b _L1_DrvCsrStop
+ 0x100169b2 0x20 _L1_DrvCsrRdbReset
+ 0x100169d2 0x1b _L1_DrvCsrSetSample
+ 0x100169ed 0x10 _L1_DrvCsrSetTimeBase
+ 0x100169fd 0x9 _L1_DrvCsrGetTimeBase
+ 0x10016a06 0xe _L1_DrvCsrSyncidCutMode
+ 0x10016a14 0xf _L1_DrvCsrMidIdCutMode
+ 0x10016a23 0x22 _L1_DrvCsrEngParaCfg
+ 0x10016a45 0x16 _L1_DrvCsrEngPosParaCfg
+ 0x10016a5b 0x19 _L1_DrvCsrSyncParaCfg
+ 0x10016a74 0xe _L1_DrvCsrSyncCorrModeCfg
+ 0x10016a82 0xc _L1_DrvCsrSyncMaskCfg
+ 0x10016a8e 0x27 _L1_DrvCsrSyncM1StateRdRst
+ 0x10016ab5 0xa _L1_DrvCsrStartEng
+ 0x10016abf 0xa _L1_DrvCsrStartSyncDl
+ 0x10016ac9 0x10 _L1_DrvCsrMidIterate
+ 0x10016ad9 0xf _L1_DrvCsrMidSyncNum
+ 0x10016ae8 0x101 _L1_DrvCsrSetMidInput
+ 0x10016be9 0xa _L1_DrvCSRStartMid
+ 0x10016bf3 0x11 _L1_DrvCSROpenIntMask
+ 0x10016c04 0x1f _L1_DrvCsrGetDpramEngPeak
+ 0x10016c23 0x80 _L1_DrvCSRGetSyncM1Power
+ 0x10016ca3 0x9 _L1_DrvCsrGetEngIterate
+ 0x10016cac 0x9 _L1_DrvCsrGetSyncIterate
+ 0x10016cb5 0x9 _L1_DrvCsrGetSyncMode
+ 0x10016cbe 0x9 _L1_DrvCsrGetSampRat
+ 0x10016cc7 0x14 _L1_DrvCsrGetDpramMidPeak
+ .text 0x10016cdb 0x968 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rfc.o)
+ 0x10016cdb 0x11 _L1_DrvTxRRC
+ 0x10016cec 0x11 _L1_DrvRxRRC
+ 0x10016cfd 0x7 _L1_DrvRfcRamEnCtrl
+ 0x10016d04 0x9 _L1_DrvRfcGetWorkingRamIndex
+ 0x10016d0d 0x7 _L1_DrvRfcSetRAMStartTime
+ 0x10016d14 0x9 _L1_DrvRfcGetWorkStatus
+ 0x10016d1d 0x23 _L1_DrvRfcSetIntTime
+ 0x10016d40 0x9 _L1_DrvRfcGetIntType
+ 0x10016d49 0x12 _L1_DrvRfcInterEnCtrl
+ 0x10016d5b 0x79 _L1_DrvRfcNotchCordicCfg
+ 0x10016dd4 0x9 _L1_DrvRfcGetEstimatePwr
+ 0x10016ddd 0x65 _L1_DrvRfcGetMaxPower
+ 0x10016e42 0x27 _L1_DrvRfcRtxRegInit
+ 0x10016e69 0x20 _L1_DrvRfcMipiRffeWrite
+ 0x10016e89 0x20 _L1_DrvRfcMipiRffeDoubleWrite
+ 0x10016ea9 0x14 _L1_DrvRfcGpioWrite
+ 0x10016ebd 0x30 _L1_DrvRfcSpiWrite
+ 0x10016eed 0x2f _L1_DrvRfcAbbSpiWrite
+ 0x10016f1c 0x61 _L1_DrvRfcDirectRamSwitch
+ 0x10016f7d 0x3b _L1_DrvRfcRamEventWrt
+ 0x10016fb8 0x1b _L1_DrvRfcEventDataWrt
+ 0x10016fd3 0x1e _L1_DrvRfcSwPaWrite
+ 0x10016ff1 0x1f _L1_DrvRfcGetTxSwData
+ 0x10017010 0x1f _L1_DrvRfcGetRxSwData
+ 0x1001702f 0x21 _L1_DrvRfcGetSwIdleData
+ 0x10017050 0x2d _L1_DrvRfcGetPaCtrlData
+ 0x1001707d 0x1f _L1_DrvRfcGetPaIdleCtrlData
+ 0x1001709c 0x33 _L1_DrvRfcEventOffsetWrt
+ 0x100170cf 0xa7 _L1_DrvRfcEventRamInitSet
+ 0x10017176 0x6b _L1_DrvRfcUnavailEvntInit
+ 0x100171e1 0x9 _L1_DrvRfcSyncModeSwitchEnable
+ 0x100171ea 0xf _L1_DrvRfcNormalRamInit
+ 0x100171f9 0xb _L1_DrvRfcUnSyncRamDisable
+ 0x10017204 0x41 _L1_DrvRfcEventEnable
+ 0x10017245 0x25 _L1_DrvRfcEventDisable
+ 0x1001726a 0x32 _L1_DrvRfcSlotEventDisable
+ 0x1001729c 0x70 _L1_DrvRfcModeSwitch
+ 0x1001730c 0x53 _L1_DrvRfcTs0EventOffsetAdj
+ 0x1001735f 0xb _L1_DrvRfcSlotUpCheck
+ 0x1001736a 0x63 _L1_DrvRfcTxEventOffsetAdjust
+ 0x100173cd 0x7 _L1_DrvRfcTs6Ts0FreqDiff
+ 0x100173d4 0x80 _L1_DrvRfcReset
+ 0x10017454 0x80 _L1_DrvRfcInit
+ 0x100174d4 0x40 _L1_DrvRfcGetAfcCtrlWord
+ 0x10017514 0x42 _L1_DrvRfcCheckDACTable
+ 0x10017556 0x2 _L1_DrvRfcApcTmpCmp
+ 0x10017558 0x2d _L1_DrvRfcFreqCmpSearchNvIdx
+ 0x10017585 0x3c _L1_DrvRfcApcFreCmp
+ 0x100175c1 0x2c _L1_DrvRfcAgcFreCmp
+ 0x100175ed 0x56 _L1_DrvRfcRestore
+ .text 0x10017643 0x253 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_tpu.o)
+ 0x10017643 0x13 _L1_DrvTpuReset
+ 0x10017656 0x31 _L1_DrvTpuInit
+ 0x10017687 0x10 _L1_DrvTpuMaskIntEnableCfg
+ 0x10017697 0x8 _L1_DrvTpuMaskIntDisableCfg
+ 0x1001769f 0x1c _L1_DrvTpuSoftResetCfg
+ 0x100176bb 0xe _L1_DrvTpuNTIntEnable
+ 0x100176c9 0xf _L1_DrvTpuNTIntDisable
+ 0x100176d8 0xe _L1_DrvTpuRTIntEnable
+ 0x100176e6 0xf _L1_DrvTpuRTIntDisable
+ 0x100176f5 0x84 _L1_DrvTpuNTSyncQuaterChipCfg
+ 0x10017779 0x22 _L1_DrvTpuNTSyncSubFrmCfg
+ 0x1001779b 0x14 _L1_DrvTpuNTSyncSubFrmSlipCfg
+ 0x100177af 0x10 _L1_DrvTpuLatchTimeCfg
+ 0x100177bf 0x23 _L1_DrvTpuRdNTTiming
+ 0x100177e2 0x13 _L1_DrvTpuRdRTTiming
+ 0x100177f5 0x1a _L1_DrvTpuNTIntParaCfg
+ 0x1001780f 0x1a _L1_DrvTpuRTIntParaCfg
+ 0x10017829 0x35 _L1_DrvTpuSaveReg
+ 0x1001785e 0x38 _L1_DrvTpuRestorReg
+ .text 0x10017896 0x6f9 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_tx.o)
+ 0x10017896 0xc _L1_DrvTxLogTwo
+ 0x100178a2 0x2e _L1_DrvTxReset
+ 0x100178d0 0x2b _L1_DrvTxUppchConfig
+ 0x100178fb 0xd _L1_DrvTxUppchStop
+ 0x10017908 0x28 _L1_DrvTxHssichStop
+ 0x10017930 0x1c _L1_DrvTxPrachEnable
+ 0x1001794c 0x1d _L1_DrvTxDpchEnable
+ 0x10017969 0x14 _L1_DrvTxClose
+ 0x1001797d 0x104 _L1_DrvTxPrachConfig
+ 0x10017a81 0x81 _L1_DrvTxClearTsPara
+ 0x10017b02 0xd9 _L1_DrvTxDpchConfig
+ 0x10017bdb 0xe9 _L1_DrvTxDpchCh1Cfg
+ 0x10017cc4 0xd3 _L1_DrvTxDpchCh2Cfg
+ 0x10017d97 0x77 _L1_DrvTxHssichConfig
+ 0x10017e0e 0x11 _L1_DrvTxUpTimingCfg
+ 0x10017e1f 0x10 _L1_DrvTxUpDataScale
+ 0x10017e2f 0x1c _L1_DrvTxOffsetCfg
+ 0x10017e4b 0x6c _L1_DrvTxTxTpcBitCfg
+ 0x10017eb7 0x27 _L1_DrvTxTsChScale
+ 0x10017ede 0x1a _L1_DrvTxHssichTsChScale
+ 0x10017ef8 0x9 _L1_DrvTxHssichTpcBitCfg
+ 0x10017f01 0x36 _L1_DrvTxRegClear
+ 0x10017f37 0x22 _L1_DrvTxSoftModeCfg
+ 0x10017f59 0x1b _L1_DrvTxSoftModeClear
+ 0x10017f74 0x1b _L1_DrvTxSoftCh1BitsCfg
+ .text 0x10017f8f 0x240 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_meas.o)
+ 0x10017f8f 0x28 _L1_DrvMeasInit
+ 0x10017fb7 0x5 _L1_DrvMeasStop
+ 0x10017fbc 0x56 _L1_DrvMeasStart
+ 0x10018012 0x4c _L1_DrvMeasRscpIntProc
+ 0x1001805e 0x12e _L1_DrvMeasIscpIntProc
+ 0x1001818c 0x5 _L1_DrvMeasGetBs
+ 0x10018191 0x8 _L1_DrvMeasGetBitshiftrm
+ 0x10018199 0x36 _Meas_Arith_CountQ8Db
+ .text 0x100181cf 0x3d1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_hsupa.o)
+ 0x100181cf 0xa _L1_DrvHsupaEutrEnable
+ 0x100181d9 0xa _L1_DrvHsupaEutrDisable
+ 0x100181e3 0x124 _L1_DrvHsupaEutrConfig
+ 0x10018307 0xe _L1_DrvHsupaEtxEnable
+ 0x10018315 0xa _L1_DrvHsupaEtxDisable
+ 0x1001831f 0xfd _L1_DrvHsupaEtxConfig
+ 0x1001841c 0x37 _L1_DrvHsupaEpuchScaleConfig
+ 0x10018453 0xa _L1_DrvHsupaErucchEnable
+ 0x1001845d 0x12 _L1_DrvHsupaErucchDisable
+ 0x1001846f 0x99 _L1_DrvHsupaErucchConfig
+ 0x10018508 0x18 _L1_DrvHsupaErucchScaleConfig
+ 0x10018520 0xe _L1_DrvHsupaTpcConfig
+ 0x1001852e 0x1f _L1_DrvHsupaTxOffsetConfig
+ 0x1001854d 0xc _L1_DrvHsupaRegClear
+ 0x10018559 0xa _L1_DrvHsupaEnableInt
+ 0x10018563 0xa _L1_DrvHsupaMaskInt
+ 0x1001856d 0x17 _L1_DrvHsupaGetHarqRamOffset
+ 0x10018584 0x1c _L1_DrvHsupaGetHarqRamAddr
+ .text 0x100185a0 0x298 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_dpram.o)
+ 0x100185a0 0x21 _L1_DrvDpramStructInit
+ 0x100185c1 0x38 _L1_DrvDpramInit
+ 0x100185f9 0x29 _L1_DrvDpramIsEmpty
+ 0x10018622 0x43 _L1_DrvDpramReadMsg
+ 0x10018665 0x1 _L1_DrvDpramUpdateMsgPos
+ 0x10018666 0x1 _L1_DrvDpramQueMemRead
+ 0x10018667 0x1a _L1_DrvICPSend
+ 0x10018681 0x36 _L1_DrvDpramWriteMsg
+ 0x100186b7 0x2e _L1_DrvDpramGetRdDataPtr
+ 0x100186e5 0x27 _L1_DrvDpramUpdateRdDataPos
+ 0x1001870c 0x3e _L1_DrvDpramGetWrDataPtr
+ 0x1001874a 0x3d _L1_DrvDpramUpdateWrDataPos
+ 0x10018787 0x24 _L1_DpramTxReadClearData
+ 0x100187ab 0x27 _L1_DrvDpramSleepCheck
+ 0x100187d2 0xa _L1_DrvDpramCheckA2DMsg
+ 0x100187dc 0xa _L1_DrvDpramCheckD2AMsg
+ 0x100187e6 0x2 _L1_DrvDpramReadL1tQueueFlag
+ 0x100187e8 0x8 _L1_DrvDpramWriteSfnDpramFlg
+ 0x100187f0 0x7 _L1_DrvDpramReadIcpIntState
+ 0x100187f7 0x7 _L1_DrvDpramClrIcpIntState
+ 0x100187fe 0xa _L1_DrvDpramMaskIcpInt
+ 0x10018808 0x9 _L1_DrvDpramDemaskIcpInt
+ 0x10018811 0x11 _L1S_DrvDpramWriteTiming
+ 0x10018822 0x7 _L1_DrvDpramWriteUph
+ 0x10018829 0x7 _L1_DrvDpramWriteSnpl
+ 0x10018830 0x8 _L1_DrvDpramAbnomalRst
+ .text 0x10018838 0xace T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rx.o)
+ 0x10018838 0x4d _L1_DrvRxReset
+ 0x10018885 0x167 _L1_DrvRxInit
+ 0x100189ec 0x12 _L1_DrvRxAmmse
+ 0x100189fe 0xb _L1_DrvRxReadAmmse
+ 0x10018a09 0xb _L1_DrvRxGetDenoiseFactor
+ 0x10018a14 0x2a _L1_DrvRxSetDenoiseFactor
+ 0x10018a3e 0x1fd _L1_DrvRxSlotParaCfg
+ 0x10018c3b 0x73 _L1_DrvRxSlotParaRel
+ 0x10018cae 0x61 _L1_DrvRxIntraCellSlotCfg
+ 0x10018d0f 0x22 _L1_DrvRxReadMcheIntInd
+ 0x10018d31 0x8 _L1_DrvRxReadMcheDataAddr
+ 0x10018d39 0xa _L1_DrvRxReadDagcResultAddr
+ 0x10018d43 0x3f _L1_DrvRxReadJdcoreIntInd
+ 0x10018d82 0xa _L1_DrvRxReadJdoutDataAddr
+ 0x10018d8c 0xa _L1_DrvRxReadTpcSsDataAddr
+ 0x10018d96 0xa _L1_DrvRxReadCodePwrDataAddr
+ 0x10018da0 0x21 _L1_DrvRxReadHichIntInd
+ 0x10018dc1 0x3f _L1_DrvRtxReadRxIntResult
+ 0x10018e00 0x4a _L1_DrvRtxReadJdOut
+ 0x10018e4a 0x26 _L1_DrvRxForcedCfg
+ 0x10018e70 0xb7 _L1_DrvRxCctrchReCfg
+ 0x10018f27 0x68 _L1_DrvRxCctrchParaCfg
+ 0x10018f8f 0x21 _L1_DrvRxReadEHichRegInfo
+ 0x10018fb0 0x18 _L1_DrvRxReadMcheWinPower
+ 0x10018fc8 0x1d _L1_DrvRxReadCctrchSBValue
+ 0x10018fe5 0x30 _L1_DrvRxReadHwacdIntInd
+ 0x10019015 0x59 _L1_DrvRxConfigFcCodeReg
+ 0x1001906e 0x50 _L1_DrvRxHspaCodeCfg
+ 0x100190be 0x21 _L1_DrvRxSetDtxFactor
+ 0x100190df 0x19 _L1_DrvRxRecfgRscpGf
+ 0x100190f8 0x2a _L1_DrvRx2MeasRscpResult
+ 0x10019122 0x22 _L1_DrvRx2MeasRscpInit
+ 0x10019144 0xd _L1_DrvRx2MeasRscpStop
+ 0x10019151 0x32 _L1_DrvRx2MeasRscpCfg
+ 0x10019183 0x9 _L1_DrvRx2MeasJdCellIdAddr
+ 0x1001918c 0x9 _L1_DrvRx2MeasJdResultAddr
+ 0x10019195 0x2 _L1_DrvRx2MeasGetBs
+ 0x10019197 0x36 _L1_DrvRxSetDagcPara
+ 0x100191cd 0x57 _L1_DrvRxReadJdCctrchCfg
+ 0x10019224 0x71 _L1_DrvRxSaveReg
+ 0x10019295 0x71 _L1_DrvRxRestorReg
+ .text 0x10019306 0x9b1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_dtr.o)
+ 0x10019306 0x36 _L1_DrvDtrReset
+ 0x1001933c 0xae _L1_DrvDtrInit
+ 0x100193ea 0xd _L1_DrvDtrRegSet1Update
+ 0x100193f7 0x83 _L1_DrvDtrBchCfg
+ 0x1001947a 0x23 _L1_DrvDtrBchRel
+ 0x1001949d 0x4e _L1_DrvDtrFachPchS1Cfg
+ 0x100194eb 0x25 _L1_DrvDtrFachPchRel
+ 0x10019510 0x67 _L1_DrvDtrFpachCfg
+ 0x10019577 0x1e _L1_DrvDtrFpachRel
+ 0x10019595 0x165 _L1_DrvDtrFachPchS2Cfg
+ 0x100196fa 0x90 _L1_DrvDtrDlDchS1Cfg
+ 0x1001978a 0xd _L1_DrvDtrTurboCfg
+ 0x10019797 0x22 _L1_DrvDtrTurboReset
+ 0x100197b9 0x25 _L1_DrvDtrDchS1Rel
+ 0x100197de 0x1dd _L1_DrvDtrDchS2Cfg
+ 0x100199bb 0x52 _L1_DrvDtrS2Rel
+ 0x10019a0d 0x90 _L1_DrvDtrHsscchCfg
+ 0x10019a9d 0x44 _L1_DrvDtrHsscchRel
+ 0x10019ae1 0x88 _L1_DrvDtrEagchCfg
+ 0x10019b69 0x44 _L1_DrvDtrEagchRel
+ 0x10019bad 0xd _L1_DrvDtrTfUpdate
+ 0x10019bba 0x1c _L1_DrvDtrReadTfciIntInd
+ 0x10019bd6 0x24 _L1_DrvDtrReadTtiIntInd
+ 0x10019bfa 0x37 _L1_DrvDtrReadTrchData
+ 0x10019c31 0x14 _L1_DrvDtrReadTrchOutState2
+ 0x10019c45 0xe _L1_DrvDtrGetCrcMode
+ 0x10019c53 0x11 _L1_DrvDtrGetTtiType
+ 0x10019c64 0x21 _L1_DrvDtrCfgMaxTti
+ 0x10019c85 0x20 _L1_DrvDtrSetDoffMode
+ 0x10019ca5 0x12 _L1_DrvDtrClearDoffMode
+ .text 0x10019cb7 0x1402 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rfc_zx220a1.o)
+ 0x10019cb7 0x2e _L1_DrvRfcApcTableSel
+ 0x10019ce5 0x1a2 _L1_DrvRfcAbbCsfHpfCfg
+ 0x10019e87 0x1 _L1_DrvRfcNvInit
+ 0x10019e88 0x29 _L1_DrvRfcCalcFracFreq
+ 0x10019eb1 0x5 _L1_DrvRfcCalcIntFreq
+ 0x10019eb6 0x39 _L1_DrvRfcGetFreqData
+ 0x10019eef 0xcc _L1_DrvRfcRfTxOpenForever
+ 0x10019fbb 0xb1 _L1_DrvRfcRfRxOpenForever
+ 0x1001a06c 0xa _L1_DrvRfcDeviceInit
+ 0x1001a076 0x31 _L1_DrvRfcPaIdleSet
+ 0x1001a0a7 0x2a _L1_DrvRfcDmSwCfg
+ 0x1001a0d1 0xda _L1_DrvRfcFreqSet
+ 0x1001a1ab 0x11 _L1_DrvRfcInitAfcSet
+ 0x1001a1bc 0x2c _L1_DrvRfcAfcCtrl
+ 0x1001a1e8 0x7a _L1_DrvRfcApcSet
+ 0x1001a262 0x4f _L1_DrvRfcSwPaIdleNvGet
+ 0x1001a2b1 0x65 _L1_DrvRfcPaSet
+ 0x1001a316 0xa0 _L1_DrvRfcFindApcTable
+ 0x1001a3b6 0x1b _L1_DrvRfcApcGainCheck
+ 0x1001a3d1 0x21 _L1_DrvRfcApcFreCmpIdxGet
+ 0x1001a3f2 0x21 _L1_DrvRfcAgcFreCmpIdxGet
+ 0x1001a413 0x29 _L1_DrvRfcApcCtrl
+ 0x1001a43c 0x4e _L1_DrvRfcAgcNvTableCheck
+ 0x1001a48a 0x18 _L1_DrvRfcAgcGainCheck
+ 0x1001a4a2 0xb2 _L1_DrvRfcCfgAgc
+ 0x1001a554 0x19 _L1_DrvRfcIdleToRxUnSyncEnable
+ 0x1001a56d 0x1b _L1_DrvRfcRxToRxUnSyncEnable
+ 0x1001a588 0x12 _L1_DrvRfcQKUnSyncEnable
+ 0x1001a59a 0xbb _L1_DrvRfcNormalUnSynRamInit
+ 0x1001a655 0xef _L1_DrvRfcNormalSynRamInit
+ 0x1001a744 0x13 _L1_DrvRfcRdbRamEnable
+ 0x1001a757 0x6d _L1_DrvRfcRdbUnSynRamInit
+ 0x1001a7c4 0x2 _L1_DrvRfcRdbRamInit
+ 0x1001a7c6 0x88 _L1_DrvRfcIdleToTx
+ 0x1001a84e 0x59 _L1_DrvRfcTxToIdle
+ 0x1001a8a7 0x8c _L1_DrvRfcIdleToRx
+ 0x1001a933 0x49 _L1_DrvRfcRxToIdle
+ 0x1001a97c 0x54 _L1_DrvRfcTxToTx
+ 0x1001a9d0 0x6f _L1_DrvRfcRxToRx
+ 0x1001aa3f 0x1 _L1_DrvRfcRxToTx
+ 0x1001aa40 0x8a _L1_DrvRfcT3R4
+ 0x1001aaca 0x60 _L1_DrvRfcSlotEventCtrl
+ 0x1001ab2a 0x32 _L1_DrvRfcRfBandData
+ 0x1001ab5c 0x63 _L1_DrvRfcRfCloseRx
+ 0x1001abbf 0x88 _L1_DrvRfcRfCloseTx
+ 0x1001ac47 0x3b _L1_DrvRfcTxSlotTadvAdj
+ 0x1001ac82 0xdf _L1_DrvRfcMainRegRdBack
+ 0x1001ad61 0x1 _L1_DrvRfcAllRegRdBack
+ 0x1001ad62 0x19 _L1_DrvRfcSpiReadData
+ 0x1001ad7b 0x3c _L1_DrvRfcReadTmpEventSet
+ 0x1001adb7 0x1 _L1_DrvRfcReadRegEventSet
+ 0x1001adb8 0x99 _L1_DrvRfcRdbEventCfg
+ 0x1001ae51 0x25 _L1_DrvRfcRegRead
+ 0x1001ae76 0x81 _L1_DrvRfcAmtTxInit
+ 0x1001aef7 0x49 _L1_DrvRfcRfIdle
+ 0x1001af40 0x32 _L1_DrvRfcAmtAfcCtrl
+ 0x1001af72 0x46 _L1_DrvRfcAfcCfg
+ 0x1001afb8 0xa _L1_DrvRfcTmpRbCfg
+ 0x1001afc2 0x42 _L1_DrvRfcApcCfg
+ 0x1001b004 0x41 _L1_DrvRfcApcDcocCfg
+ 0x1001b045 0x13 _L1_DrvRfcGetApcCtrlWord
+ 0x1001b058 0x2b _L1_DrvRfcAgcDataGet
+ 0x1001b083 0x36 _L1_DrvRfcFdtApcSet
+ .text 0x1001b0b9 0x114 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rdb.o)
+ 0x1001b0b9 0x20 _L1_DrvRdbReset
+ 0x1001b0d9 0x52 _L1_StartRdbNoneTimingWrite
+ 0x1001b12b 0x3b _L1_RdbReadCsr
+ 0x1001b166 0x22 _L1_RdbStop
+ 0x1001b188 0x1e _L1_RdbStopRead
+ 0x1001b1a6 0x12 _L1_DrvRdbInterEnCtrl
+ 0x1001b1b8 0x15 _L1_DrvRdbZspView
+ .text 0x1001b1cd 0x14c T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_top.o)
+ 0x1001b1cd 0x20 _L1td_DrvMcuIntMask
+ 0x1001b1ed 0x20 _L1td_DrvMcuIntUnmask
+ 0x1001b20d 0x9 _L1td_DrvMcuIntIreqClr
+ 0x1001b216 0x47 _L1td_DrvTopIntMask
+ 0x1001b25d 0x3d _L1td_DrvTopIntMaskRestore
+ 0x1001b29a 0x13 _L1td_DrvTopIntClr
+ 0x1001b2ad 0x44 _L1td_DrvTopSaveReg
+ 0x1001b2f1 0x28 _L1td_DrvTopRestorReg
+ .text 0x1001b319 0xe4 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_afc.o)
+ 0x1001b319 0x3e _L1_DrvAfcReset
+ 0x1001b357 0x1c _L1_DrvAfcCellIqReadResult
+ 0x1001b373 0x5d _L1_DrvAfcCellFigParaCfg
+ 0x1001b3d0 0x11 _L1_DrvAfcSetHwParaCfg
+ 0x1001b3e1 0xe _L1_DrvAfcInterStart
+ 0x1001b3ef 0xe _L1_DrvAfcInterStop
+ .text 0x1001b3fd 0x41c T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_hsdpa.o)
+ 0x1001b3fd 0xa _L1_DrvHsdpaOpenHdtrInt
+ 0x1001b407 0x2c _L1_DrvHsdpaHdtrTurboOpen
+ 0x1001b433 0x16 _L1_DrvHsdpaHdtrTurboClose
+ 0x1001b449 0x1c _L1_DrvHsdpaHdtrTurboReset
+ 0x1001b465 0xa _L1_DrvHsdpaMaskHdtrInt
+ 0x1001b46f 0x20 _L1_DrvHsdpaHdtrReset
+ 0x1001b48f 0x86 _L1_DrvHsdpaHdtrFrmSlotConfig
+ 0x1001b515 0xa _L1_DrvHsdpaHdtrFrmSlotClear
+ 0x1001b51f 0x44 _L1_DrvHsdpaHdtrHarqAddrConfig
+ 0x1001b563 0x1a0 _L1_DrvHsdpaHdtrDecodeConfig
+ 0x1001b703 0x25 _L1_DrvHsdpaHdtrGetCrcResult
+ 0x1001b728 0x47 _L1_DrvHsdpaHdtrGetCqiInfo
+ 0x1001b76f 0xaa _L1_DrvHsdpaRegRead
+ .text 0x1001b819 0x1264 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_main.o)
+ 0x1001b819 0x2b _L1_SEND_RST_REQ
+ 0x1001b844 0x2b _L1_SEND_INIT_REQ
+ 0x1001b86f 0x44 _L1_SEND_LOG_FILTER_REQ
+ 0x1001b8b3 0x42 _L1_SEND_LOG_CHANNEL_REQ
+ 0x1001b8f5 0x57 _L1_SEND_LOG_TDPHY_DEBUG_REQ
+ 0x1001b94c 0x14e _L1S_Reset
+ 0x1001ba9a 0x12c _L1S_Init
+ 0x1001bbc6 0xa3 _L1S_TD_Release
+ 0x1001bc69 0x2c _L1sAmtRxRel
+ 0x1001bc95 0x106 _L1S_PSCommonMsgCtrl
+ 0x1001bd9b 0x247 _L1_PsToPhyMsgEngDisplay
+ 0x1001bfe2 0x1ed _L1_PhyToPsMsgEngDisplay
+ 0x1001c1cf 0xef _L1S_ReadPSMsg
+ 0x1001c2be 0x1b _L1S_InnerCmd
+ 0x1001c2d9 0x1f _L1S_ProcSend2PS
+ 0x1001c2f8 0x1e _L1S_ProcAftSchedHandler
+ 0x1001c316 0x1e0 _L1S_RfDevCtrl
+ 0x1001c4f6 0x5c _L1S_DlsDevCtrl
+ 0x1001c552 0x11 _L1S_CommonDevCtrl
+ 0x1001c563 0x76 _L1S_ReadPsData
+ 0x1001c5d9 0x75 _L1S_AmtNstReadPsData
+ 0x1001c64e 0xe3 _L1S_SubFrameInt
+ 0x1001c731 0x104 _L1S_DevResultProc
+ 0x1001c835 0x248 _L1_SchedMainTask
+ .text 0x1001ca7d 0x68a T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_sync.o)
+ 0x1001ca7d 0x73 _L1_SerCellTimeFrmMeas
+ 0x1001caf0 0x19 _L1_SetOtdOriCellInfo
+ 0x1001cb09 0xd0 _L1_GetCellTimingInfo
+ 0x1001cbd9 0xad _L1_GetCellAfcValue
+ 0x1001cc86 0x8a _L1_SetCellTimingInfo
+ 0x1001cd10 0x45 _L1_SetSysAfcValue
+ 0x1001cd55 0x13 _L1_ResetSysSynDb
+ 0x1001cd68 0x22 _L1_ClearUNconfInfo
+ 0x1001cd8a 0x161 _L1_UpdateSysSyncState
+ 0x1001ceeb 0x14a _L1_UpdateSysSyncInfo
+ 0x1001d035 0x64 _L1_GetCellUnSyncPeriod
+ 0x1001d099 0x7 _L1_GetSysSyncState
+ 0x1001d0a0 0x7 _L1_GetUnConfSysSyncState
+ 0x1001d0a7 0x58 _L1_GetCellOtdValue
+ 0x1001d0ff 0x8 _L1_SetSysUnconfsyncState
+ .text 0x1001d107 0x2b69 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_meas_db.o)
+ 0x1001d107 0x1e _L1_SchedMeasProcAllCellCmp
+ 0x1001d125 0x16 _L1_SchedMeasProcDbFreqSearch
+ 0x1001d13b 0x19 _L1_SchedMeasProcSchedFreqSearch
+ 0x1001d154 0x1d _L1_SchedMeasProcResetSync
+ 0x1001d171 0x9a _L1_SchedMeasProcIntraDetCell
+ 0x1001d20b 0x25 _L1_SchedMeasProcUpdateDeteDb
+ 0x1001d230 0x12f _L1_SchedMeasGetDchIntraCell
+ 0x1001d35f 0xd _L1_SchedMeasDbReset
+ 0x1001d36c 0x18 _L1_SchedMeasProcSetHighPriReq
+ 0x1001d384 0x49 _L1_SchedMeasProcGetHighPriReq
+ 0x1001d3cd 0xe _L1_SchedMeasProcSetHighTime
+ 0x1001d3db 0x33 _L1_SchedMeasProcRscpLinerFilter
+ 0x1001d40e 0x9c _L1_SchedMeasProcSetHighResult
+ 0x1001d4aa 0x1c _L1_SchedMeasProcGetHighResult
+ 0x1001d4c6 0x56 _L1_SchedMeasProcIntraIscpNeed
+ 0x1001d51c 0x3f _L1_SchedMeasProcInterIscpNeed
+ 0x1001d55b 0x98 _L1_SchedMeasProcDelDbListByFreq
+ 0x1001d5f3 0x1c4 _L1_SchedMeasProcSaveDbIntraFreq
+ 0x1001d7b7 0x47 _L1_SchedMeasProcClrResultByFreq
+ 0x1001d7fe 0x5b _L1_SchedMeasProcDelDbLsLeftFreq
+ 0x1001d859 0xda _L1_SchedMeasProcUpdateDbSerCell
+ 0x1001d933 0x189 _L1_SchedMeasProcUpdateIntraDbLs
+ 0x1001dabc 0x8f _L1_SchedMeasProcDbAddSCell
+ 0x1001db4b 0x24 _L1_SchedMeasProcIsScell
+ 0x1001db6f 0x24 _L1_SchedMeasProcIsIntraCell
+ 0x1001db93 0x3a _L1_SchedMeasProcSaveScellInfo
+ 0x1001dbcd 0x68 _L1_SchedMeasProcAddSaveSerCell
+ 0x1001dc35 0x134 _L1_SchedMeasProcUpdateDbInterLs
+ 0x1001dd69 0x49 _L1_SchedMeasProcQuerySynlIdInfo
+ 0x1001ddb2 0x16f _L1_SchedMeasProcSetBlindInfo
+ 0x1001df21 0x6b _L1_SchedMeasProcClrBlindInfo
+ 0x1001df8c 0x34 _L1_SchedMeasProcUpdateSchedList
+ 0x1001dfc0 0xff _L1_SchedMeasProSaveWorkFreqCell
+ 0x1001e0bf 0x81 _L1_SchedMeasProSavePriFreqCell
+ 0x1001e140 0x17 _L1_SchedMeasProcSaveDbIntraCell
+ 0x1001e157 0xd6 _L1_SchedMeasProcSaveInterCell
+ 0x1001e22d 0x26 _L1_SchedMeasProcSaveDbInterCell
+ 0x1001e253 0x64 _L1_SchedMeasProcLoadTempBufInfo
+ 0x1001e2b7 0x4f _L1_SchedMeasSetIntraSchedTime
+ 0x1001e306 0xa0 _L1_SchedMeasProcSetSchedTime
+ 0x1001e3a6 0x22 _L1_SchedMeasProcGetSchedTime
+ 0x1001e3c8 0xe5 _L1_SchedMeasProcSetDetectCell
+ 0x1001e4ad 0x4c _L1_SchedMeasProcUpdateDetCell
+ 0x1001e4f9 0x70 _L1_SchedMeasProcDelSameCell
+ 0x1001e569 0x228 _L1_SchedMeasProcGetCurrentCell
+ 0x1001e791 0x201 _L1_SchedMeasProcSetCurFreqInfo
+ 0x1001e992 0x59 _L1_SchedMeasProcCellSort
+ 0x1001e9eb 0xce _L1_SchedMeasProcCalcSnPl
+ 0x1001eab9 0x72 _L1_SchedMeasProcSaveRssiResult
+ 0x1001eb2b 0xa1 _L1_SchedMeasProcSaveOtdResult
+ 0x1001ebcc 0x98 _L1_SchedMeasProcUpdateSync
+ 0x1001ec64 0xe6 _L1_SchedMeasProcSaveDetcResult
+ 0x1001ed4a 0xa9 _L1_SchedMeasProcSaveIscpResult
+ 0x1001edf3 0x2a _L1_SchedMeasRscpNewFilter
+ 0x1001ee1d 0x52 _L1_SchedMeasProcRscpFilter
+ 0x1001ee6f 0x10a _L1_SchedMeasSetMaxEnvCell
+ 0x1001ef79 0x25 _L1_SchedMeasSlaveGetCsFlag
+ 0x1001ef9e 0x338 _L1_SchedMeasProcSaveRscpResult
+ 0x1001f2d6 0x45 _L1_SchedMeasProcGetScellResult
+ 0x1001f31b 0x1e _L1_SchedMeasProcGetDetectCell
+ 0x1001f339 0x8e _L1_SchedMeasProcCalIntraResult
+ 0x1001f3c7 0x6c _L1_SchedMeasProcGetIntraResult
+ 0x1001f433 0xb5 _L1_SchedMeasProcCalInterResult
+ 0x1001f4e8 0xd8 _L1_SchedMeasProcGetInterResult
+ 0x1001f5c0 0x61 _L1_SchedMeasProcGetBlindResult
+ 0x1001f621 0x24 _L1_SchedMeasProcFoundCond
+ 0x1001f645 0xa0 _L1_SchedGetCellRscpMeasResult
+ 0x1001f6e5 0x26 _L1_SchedSetCellMeasList
+ 0x1001f70b 0x13f _L1_SchedGetCellMeasExcptDch
+ 0x1001f84a 0x29 _L1_SchedGetCellMeasList
+ 0x1001f873 0x4b _L1_SchedMeasSetCellAfc
+ 0x1001f8be 0x44 _L1_SchedMeasQueryCellInMidDb
+ 0x1001f902 0x31 _L1_SchedMeasGetCellAfc
+ 0x1001f933 0x3b _L1_SchedMeasSetCellTiming
+ 0x1001f96e 0x24 _L1_SchedMeasProcIsSyncOrMid
+ 0x1001f992 0xa1 _L1_SchedMeasGetCellTiming
+ 0x1001fa33 0x83 _L1_SchedMeasProcSchedCond
+ 0x1001fab6 0x5d _L1_SchedMeasProcCurFreqEnd
+ 0x1001fb13 0xb _L1_SchedMeasClearPageScellRscp
+ 0x1001fb1e 0x2b _L1_SchedMeasSavePageScellRscp
+ 0x1001fb49 0x43 _L1_SchedMeasJudgePageScellRscp
+ 0x1001fb8c 0x18 _L1_SchedMeasDbInitMaxRscp
+ 0x1001fba4 0x6e _L1_SchedMeasDbUpdateMaxRscp
+ 0x1001fc12 0x5e _L1_SchedMeasDbRptCheckMaxRscp
+ .text 0x1001fc70 0x4d6 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_fsm.o)
+ 0x1001fc70 0x9 _L1S_ClearShadowRes
+ 0x1001fc79 0x2c _L1S_RegisterProcedure
+ 0x1001fca5 0x42 _L1S_SetIcsStateProcs
+ 0x1001fce7 0x4b _L1S_SetIdleStateProcs
+ 0x1001fd32 0x4c _L1S_SetPageStateProcs
+ 0x1001fd7e 0x52 _L1S_SetFachStateProcs
+ 0x1001fdd0 0x4a _L1S_SetDchStateProcs
+ 0x1001fe1a 0x3b _L1S_SetAmtStateRxProcs
+ 0x1001fe55 0x18 _L1S_SetAmtStateTxProcs
+ 0x1001fe6d 0x3b _L1S_SetTdSlaveModeProcs
+ 0x1001fea8 0x14 _L1S_SetCloseStateProcs
+ 0x1001febc 0x3c _L1S_NotifyFSM
+ 0x1001fef8 0xb7 _L1S_L1TdMasteStateCtrl
+ 0x1001ffaf 0xc2 _L1S_ModeCtrl
+ 0x10020071 0x3b _L1S_L1StateCtrl
+ 0x100200ac 0x60 _L1S_SetProc
+ 0x1002010c 0x3a _L1S_GetPriId
+ .text 0x10020146 0x114 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_db.o)
+ 0x10020146 0x7 _Set_bch_rel_flag
+ 0x1002014d 0x7 _Get_bch_rel_flag
+ 0x10020154 0x8 _L1S_DevResultClear
+ 0x1002015c 0x24 _L1S_ReadDevResult
+ 0x10020180 0x2e _L1S_ReadDevMultiResult
+ 0x100201ae 0x41 _L1S_WriteDevResult
+ 0x100201ef 0x16 _L1S_ClrMeasDevResult
+ 0x10020205 0x29 _L1_SchedDbInit
+ 0x1002022e 0x23 _L1_ReadPsMsgFromDb
+ 0x10020251 0x6 _L1_GetPsMsgAddress
+ 0x10020257 0x3 _L1_GetPsMsgMaxLen
+ .text 0x1002025a 0x3210 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_meas.o)
+ 0x1002025a 0x23 _L1_SchedMeasProcActive
+ 0x1002027d 0x3e _L1_SchedMeasProcDeactive
+ 0x100202bb 0x1e _L1_SchedMeasProcIsInterFreq
+ 0x100202d9 0x2e _L1_SchedMeasProcHighSchedReq
+ 0x10020307 0x1f _L1_SchedMeasProcHighJudge
+ 0x10020326 0x8e _L1_SchedMeasProcHighSched
+ 0x100203b4 0x3d _L1_SchedMeasProcMeasGroup
+ 0x100203f1 0x223 _L1_SchedMeasPeriodUpdate
+ 0x10020614 0x1c _L1_SchedMeasProcIsNewState
+ 0x10020630 0x19 _L1_SchedMeasProcIsUeMeasCond
+ 0x10020649 0x54 _L1_SchedMeasProcFirstPriFreq
+ 0x1002069d 0x137 _L1_SchedMeasProcGetFreqToMeas
+ 0x100207d4 0x49 _L1_SchedMeasProcIsBlindFreq
+ 0x1002081d 0xa0 _L1_SchedMeasProcDstDwptsTrace
+ 0x100208bd 0xc2 _L1_SchedMeasProcUpdateSysSync
+ 0x1002097f 0x172 _L1_SchedMeasProcGsmIdle
+ 0x10020af1 0xd _L1_SchedMeasProcSyncState
+ 0x10020afe 0xc1 _L1_SchedMeasProcIsMeasCond
+ 0x10020bbf 0x1a _L1_SchedMeasProcIsBlindResult
+ 0x10020bd9 0x3b _L1_SchedMeasJudgeSlavePeriod
+ 0x10020c14 0x11a _L1_SchedMeasProcRscpSched
+ 0x10020d2e 0x6f _L1_SchedMeasProcOtdSched
+ 0x10020d9d 0x19 _L1_SchedMeasProcRssiSched
+ 0x10020db6 0xba _L1_SchedMeasProcTs0IscpSched
+ 0x10020e70 0x47 _L1_SchedMeasProcGetRssiFreq
+ 0x10020eb7 0x41 _L1_SchedMeasProcDelSchedFreqLs
+ 0x10020ef8 0x18 _L1_SchedMeasProcSavSchedIntraFreq
+ 0x10020f10 0x2b _L1_SchedMeasProcDelSchedLsFreq
+ 0x10020f3b 0x41 _L1_SchedMeasProcAddSchedIntraLs
+ 0x10020f7c 0x74 _L1_SchedMeasProcAddSchedInterLs
+ 0x10020ff0 0x11 _L1_SchedMeasProcExistPriFreq
+ 0x10021001 0xe0 _L1_SchedMeasProcIntraFreqReq
+ 0x100210e1 0x4d _L1_SchedMeasSlaveShortGapDel
+ 0x1002112e 0xe0 _L1_SchedMeasProcInterFreqReq
+ 0x1002120e 0x33 _L1_SchedMeasInterReqChange
+ 0x10021241 0xa _L1_SchedMeasProcQualMeasReq
+ 0x1002124b 0xa _L1_SchedMeasProcUeInternalReq
+ 0x10021255 0x92 _L1_SchedMeasProcMeasRelReq
+ 0x100212e7 0xb8 _L1_SchedMeasProcGetUeIntResult
+ 0x1002139f 0x67 _L1_SchedMeasProcGetQualResult
+ 0x10021406 0x2f _L1_SchedMeasProcRptScellInd
+ 0x10021435 0x50 _L1_SchedMeasProcRptDetCellInd
+ 0x10021485 0x30 _L1_SchedMeasProcRptIntraCellInd
+ 0x100214b5 0x32 _L1_SchedMeasProcRptInterCellInd
+ 0x100214e7 0x70 _L1_SchedMeasProcRptBlindFreqInd
+ 0x10021557 0x32 _L1_SchedMeasProcRptQualityInd
+ 0x10021589 0x2b _L1_SchedMeasProcRptInternalInd
+ 0x100215b4 0x3d _L1_SchedMeasProcResetExceptDb
+ 0x100215f1 0x54 _L1_SchedMeasProcInit
+ 0x10021645 0x2e _L1_SchedMeasProcReset
+ 0x10021673 0x101 _L1_SchedMeasProcPSCmd
+ 0x10021774 0x23 _L1_SchedMeasProcL1Cmd
+ 0x10021797 0x1b7 _L1_SchedMeasProcResAlloc
+ 0x1002194e 0x66 _L1_SchedMeasProcMidSchedReq
+ 0x100219b4 0x3e _L1_SchedMeasProcQuickSched
+ 0x100219f2 0x5d0 _L1_SchedMeasProcMidSched
+ 0x10021fc2 0xc0 _L1_SchedMeasSlaveCalRssi
+ 0x10022082 0x84 _L1_SchedMeasShortGapReqCS
+ 0x10022106 0x7b _L1_SchedMeasSlaveNoSignalHandler
+ 0x10022181 0xcd _L1_SchedMeasSlaveInSignal
+ 0x1002224e 0x95 _L1_SchedMeasSlaveDetctSignal
+ 0x100222e3 0x3d _L1_SchedMeasSlaveNoSignal
+ 0x10022320 0x53 _L1_SchedMeasSlaveUpdateMainCell
+ 0x10022373 0x10a _L1_SchedMeasSlaveShortGapHandel
+ 0x1002247d 0x1a7 _L1_SchedMeasProcSlaveReqCS
+ 0x10022624 0x1fd _L1_SchedMeasProcSlaveHandler
+ 0x10022821 0x172 _L1_SchedMeasProcSlaveSched
+ 0x10022993 0x18f _L1_SchedMeasProcSched
+ 0x10022b22 0x1cf _L1_SchedMeasProcCmdParse
+ 0x10022cf1 0x65 _L1_SchedMeasProcSaveMaxRscp
+ 0x10022d56 0xe0 _L1_SchedMeasProcReadResult
+ 0x10022e36 0x12b _L1_SchedMeasSetR9IntRptSign
+ 0x10022f61 0xec _L1_SchedMeasSetR9IntraRptSign
+ 0x1002304d 0x7f _L1_SchedMeasR9RptHandler
+ 0x100230cc 0x1bb _L1_SchedMeasSetR7RptSign
+ 0x10023287 0x66 _L1_SchedMeasProcSetRptSign
+ 0x100232ed 0x3f _L1_SchedMeasProcHandler
+ 0x1002332c 0x81 _L1_SchedMeasProcSend2PS
+ 0x100233ad 0x22 _L1_SchedMeasProcL1InnerRscpReq
+ 0x100233cf 0x9 _L1_SchedMeasProcL1InnerAbort
+ 0x100233d8 0x17 _L1_SchedMeasProcL1InnerInfoGet
+ 0x100233ef 0x8 _L1_SchedMeasGetInnerReq
+ 0x100233f7 0x8 _L1_SchedMeasProcSetSnplType
+ 0x100233ff 0x4b _L1_SchedMeasProcPageHandler
+ 0x1002344a 0x18 _L1_SchedMeasSetForbidMeas
+ 0x10023462 0x8 _L1_SchedMeasGetPageScellState
+ .text 0x1002346a 0x506 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_mcs.o)
+ 0x1002346a 0x23 _L1_SchedMcsProcInit
+ 0x1002348d 0x28 _L1_SchedMcsGetMainCellInfo
+ 0x100234b5 0xef _L1_SchedMcsMainCellUpdate
+ 0x100235a4 0x74 _L1_SchedMcsPSCmdHandler
+ 0x10023618 0x144 _L1_SchedMcsDlSyncProc
+ 0x1002375c 0x38 _L1_SchedMcsSleepSchedDlSync
+ 0x10023794 0x9b _L1_SchedMcsSchedHandler
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+ 0x1002d0c0 0x11 _L1_BitReverse
+ 0x1002d0d1 0xa _L1_GetNonZeroBitNum
+ 0x1002d0db 0x3 _L1_MathRxSlotId2Index
+ 0x1002d0de 0x7 _memset_16bit
+ .text 0x1002d0e5 0x18a T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_td_dbg.o)
+ 0x1002d0e5 0x47 _L1_AtDebugInfoRead
+ 0x1002d12c 0x13 _L1_AtDebugInfoWrite
+ 0x1002d13f 0x14 _L1_CmnAtDebugInfoHandler
+ 0x1002d153 0x1e _L1_AtDebugInfoHandler
+ 0x1002d171 0xfe _ose_assert
+ .text 0x1002d26f 0x1b12 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rtx_tx.o)
+ 0x1002d26f 0x5e _L1_DevRtxTxRecMsgProc
+ 0x1002d2cd 0xf _L1_DevRtxTxReset
+ 0x1002d2dc 0x1b _L1_DevRtxTxInit
+ 0x1002d2f7 0x2e _L1_DevRtxTxRevUlResetReq
+ 0x1002d325 0xce _L1_DevRtxTxRevUpCfgReq
+ 0x1002d3f3 0x5e _L1_DevRtxTxRevDchCfgReq
+ 0x1002d451 0x16 _L1_DevRtxTxGetMaxTti
+ 0x1002d467 0x98 _L1_DevRtxTxRevSichCfgReq
+ 0x1002d4ff 0x18 _L1_DevRtxTxRevAbortRaReq
+ 0x1002d517 0x35 _L1_DevRtxTxRevFpachTtiInt
+ 0x1002d54c 0x26 _L1_DevRtxTxTs1IntHandle
+ 0x1002d572 0xae _L1_DevRtxTxTs6IntHandle
+ 0x1002d620 0x71 _L1_DevRtxTxSavePcParaForUppch
+ 0x1002d691 0xa1 _L1_DevRtxTxSavePcParaForRach
+ 0x1002d732 0x81 _L1_DevRtxTxSaveRachCfgPara
+ 0x1002d7b3 0x7e _L1_DevRtxTxSaveDchCfgPara
+ 0x1002d831 0x7a _L1_DevRtxTxDataHandler
+ 0x1002d8ab 0x38 _L1_DevRtxTxCalcNi
+ 0x1002d8e3 0xb8 _L1_DevRtxTxCalcNiOfActiveTrch
+ 0x1002d99b 0x2b _L1_DevRtxTxRmInit
+ 0x1002d9c6 0x84 _L1_DevRtxTxRmGetNdata
+ 0x1002da4a 0xf _L1_DevRtxTxSavePhyPara
+ 0x1002da59 0x43 _L1_DevRtxTxSaveRachPhyPara
+ 0x1002da9c 0x10d _L1_DevRtxTxSaveDchPhyPara
+ 0x1002dba9 0x7 _L1_DevRtxTxRmDataCmp
+ 0x1002dbb0 0xea _L1_DevRtxTxRmCalcDeltaN
+ 0x1002dc9a 0x5f _L1_DevRtxTxRmSelAlgorithm
+ 0x1002dcf9 0x10c _L1_DevRtxTxUncodedCovRM
+ 0x1002de05 0x45 _L1_DevRtxTxTurboRm
+ 0x1002de4a 0xec _L1_DevRtxTxTurboRmFirst
+ 0x1002df36 0xf1 _L1_DevRtxTxTurboRmSecond
+ 0x1002e027 0x51 _L1_DevRtxTxCalcSArrayTurbo
+ 0x1002e078 0x4c _L1_DevRtxTxCalcSArrayUncodeCov
+ 0x1002e0c4 0x42 _L1_DevRtxTxRmCalcEpara
+ 0x1002e106 0x28 _L1_DevRtxTxRmGCD
+ 0x1002e12e 0x31 _L1_DevRtxTxRmGetSIndex
+ 0x1002e15f 0x43 _L1_DevRtxTxRmCalcZi
+ 0x1002e1a2 0x3b _L1_DevRtxTxMidShift
+ 0x1002e1dd 0x7b _L1_DevRtxTxRelRach
+ 0x1002e258 0x42 _L1_DevRtxTxRelDch
+ 0x1002e29a 0x113 _L1_DevRtxTxRachHandle
+ 0x1002e3ad 0xf6 _L1_DevRtxTxRachCfg
+ 0x1002e4a3 0x108 _L1_DevRtxTxDchIntHandle
+ 0x1002e5ab 0x74 _L1_DevRtxTxWithData
+ 0x1002e61f 0x28 _L1_DevRtxTxNonData
+ 0x1002e647 0x6f _L1_DevRtxTxSetDchparaForPc
+ 0x1002e6b6 0xf0 _L1_DevRtxTxDchDataSend
+ 0x1002e7a6 0x8f _L1_DevRtxTxDchSbSend
+ 0x1002e835 0x116 _L1_DevRtxTxDchCfg
+ 0x1002e94b 0x78 _L1_DevRtxTxHssichHandle
+ 0x1002e9c3 0x28 _L1_DevRtxTxFpachRel
+ 0x1002e9eb 0x70 _L1_DevRtxTxFpachAckHandle
+ 0x1002ea5b 0x13 _L1_DevRtxTxFpachNackHandle
+ 0x1002ea6e 0x2a _L1_DevRtxTxSsTpcHandle
+ 0x1002ea98 0x80 _L1_DevRtxTxPrachIntHandle
+ 0x1002eb18 0x43 _L1_DevRtxTxUppchIntHandle
+ 0x1002eb5b 0x92 _L1_DevRtxTxHssichIntHandle
+ 0x1002ebed 0xae _L1_DevRtxTxRmStaticSf
+ 0x1002ec9b 0xbf _L1_DevRtxTxRmDynamicSf
+ 0x1002ed5a 0x27 _L1_DevRtxTxGetErucchTti
+ .text 0x1002ed81 0x120e T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_dst.o)
+ 0x1002ed81 0x67 _L1_DevDlsDstMcsSetPara
+ 0x1002ede8 0x37 _L1_DevDlsDstReset
+ 0x1002ee1f 0x50 _L1_DevDlsRtxTimingTraceREQ
+ 0x1002ee6f 0xfc _L1_DrvDstChangeDataToBit8
+ 0x1002ef6b 0xad _L1_DevDstHandleMultiFinger
+ 0x1002f018 0x6 _L1_DevDstCalFingerWinStartPos
+ 0x1002f01e 0x53 _L1_DevL1_DevDstReadInterfDP
+ 0x1002f071 0x39 _L1_DevDstCalAvDP
+ 0x1002f0aa 0x3d _L1_DevDstCalMulFingerTh
+ 0x1002f0e7 0x56 _L1_DevDstSelectMultiFinger
+ 0x1002f13d 0x74 _L1_DevDstGetFingerCluster
+ 0x1002f1b1 0x99 _L1_DevDlsDstStartMcheSyncProc
+ 0x1002f24a 0x15a _L1_DevDlsDstMcheSyncIntProc
+ 0x1002f3a4 0x9e _L1_DevDlsDstStartDwPtsDlProc
+ 0x1002f442 0x82 _L1_DevDlsDstOtdMeasRpt
+ 0x1002f4c4 0x1c2 _L1_DevDlsDstDwPtsSirCal
+ 0x1002f686 0x10 _L1_DevDlsDstDwPtsMaxPathSrch
+ 0x1002f696 0xfe _L1_DevDlsDstDwPtsCellTimingEst
+ 0x1002f794 0x74 _L1_DevDlsDstDwPtsDlSyncIntProc
+ 0x1002f808 0xae _L1_DevDlsDstDbUpdate
+ 0x1002f8b6 0x22 _L1_DevDlsMcheReqDataProc
+ 0x1002f8d8 0x51 _L1_DevDlsDstDwptsProc
+ 0x1002f929 0x8c _L1_DevDlsDstMcheProc
+ 0x1002f9b5 0x39 _L1_DevDlsDstOtdProc
+ 0x1002f9ee 0x4f _L1_DevDlsDstMaFoeProc
+ 0x1002fa3d 0x23b _L1_DevDlsDstProc
+ 0x1002fc78 0xa6 _L1_DevDstOptSendTimingAdjToL1s
+ 0x1002fd1e 0x36 _L1_DevDstDwptsTraceReq
+ 0x1002fd54 0x33 _L1_DevDstSendToAFC
+ 0x1002fd87 0x58 _L1_DevDstIntInd
+ 0x1002fddf 0x70 _L1_DevDlsIsHeaderSfnEquToSave
+ 0x1002fe4f 0x20 _L1_DevDlsBaseTimeChange
+ 0x1002fe6f 0xf7 _L1_DevDlsDstAreaCondition
+ 0x1002ff66 0x29 _L1_DevDstTs0McheReq
+ .text 0x1002ff8f 0x118b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_csr.o)
+ 0x1002ff8f 0x29 _L1_DevDlsCsrInit
+ 0x1002ffb8 0x7 _L1_DevGetSlavePlmnFlg
+ 0x1002ffbf 0x7 _L1_DevSetSlavePlmnFlg
+ 0x1002ffc6 0x48 _L1_DevDlsStartDwPosSrchReq
+ 0x1003000e 0x80 _L1_DevDlsStartSyncIdSrchReq
+ 0x1003008e 0x80 _L1_DevDlsStartMidSrchReq
+ 0x1003010e 0x44 _L1_DevDlsCsrEngCfg
+ 0x10030152 0x5 _L1_DevCsrSetTimeBase
+ 0x10030157 0x5 _L1_DevCsrGetTimeBase
+ 0x1003015c 0x2d _L1_DevCsrReciprocal
+ 0x10030189 0xa _L1_DevCsrFindMaxEng
+ 0x10030193 0x8e _L1_DevDlsCsrEngIntProc
+ 0x10030221 0x45 _L1_DevCsrCalcP0m
+ 0x10030266 0x20 _L1_DevCsrCalcP1m
+ 0x10030286 0x7e _L1_DevCsrCalcP2m
+ 0x10030304 0x19 _L1_DevCsrCalcP3m
+ 0x1003031d 0xa0 _L1_DevCsrCalcRm
+ 0x100303bd 0x4f _L1_DevCsrIdentifyRm
+ 0x1003040c 0x3e _L1_DevCsrIsPeak
+ 0x1003044a 0x30 _L1_DevCsrCalcRmThresh
+ 0x1003047a 0x54 _L1_DevCsrSelectSortRm
+ 0x100304ce 0x4f _L1_DevCsrSelPosTable
+ 0x1003051d 0x84 _L1_DevCsrSelPosTableCombine
+ 0x100305a1 0x1f _L1_DevCsrIsSameEngPos
+ 0x100305c0 0x88 _L1_DevCsrSelectEngPos
+ 0x10030648 0xf8 _L1_DevCsrDoEngResult
+ 0x10030740 0x5b _L1_DevDlsCsrSyncidCfg
+ 0x1003079b 0x83 _L1_DevDlsCsrSyncIntProc
+ 0x1003081e 0x53 _L1_DevCsrSyncM1TblCombine
+ 0x10030871 0x56 _L1_DevCsrSyncM1TblCombineInsert
+ 0x100308c7 0x91 _L1_DevCsrSyncM1SelCandidate
+ 0x10030958 0x8e _L1_DevCsrSyncM1FiltrateTH
+ 0x100309e6 0x6a _L1_DevCsrSyncM1CalTH
+ 0x10030a50 0x111 _L1_DevCsrSyncM1Sel8Pos
+ 0x10030b61 0x3b _L1_DevCsrDoSync1Result
+ 0x10030b9c 0x96 _L1_DevDlsCsrMidCfg
+ 0x10030c32 0xd4 _L1_DevCsrSyncM1Sort8Pos
+ 0x10030d06 0x3f _L1_DevCsrMidSelSync
+ 0x10030d45 0x91 _L1_DevDlsCsrMidIntProc
+ 0x10030dd6 0x110 _L1_DevCsrMidSelCandidate
+ 0x10030ee6 0x64 _L1_DevCsrMidSelCandidateSort
+ 0x10030f4a 0x28 _L1_DevCsrNoiThFiltrate
+ 0x10030f72 0x4f _L1_DevCsrMidFiltrateTH
+ 0x10030fc1 0x4a _L1_DevCsrCalMidTH
+ 0x1003100b 0x5f _L1_DevCsrSetMidResult
+ 0x1003106a 0x60 _L1_DevCsrDoSearchResult
+ 0x100310ca 0x2a _L1_DevCsrDoSearchFailResult
+ 0x100310f4 0x26 _L1_DevCsrIntInd
+ .text 0x1003111a 0xd11 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_dpch.o)
+ 0x1003111a 0x2e _L1_DevPcUlDpchPwrCalc
+ 0x10031148 0x4e _L1_DevPcGetTxPower
+ 0x10031196 0x7e _L1_DevPcDlDpchTrchSequ
+ 0x10031214 0x96 _L1_DevPcDlDpchTpcSsCfg
+ 0x100312aa 0xa8 _L1_DevPcDlDpchOlpcInit
+ 0x10031352 0x47 _L1_DevPcDlDpchDlpcInit
+ 0x10031399 0x109 _L1_DevPcUlDpchInit
+ 0x100314a2 0xbb _L1_DevPcUlDpchCfg
+ 0x1003155d 0x89 _L1_DevPcDlDpchCfg
+ 0x100315e6 0x20 _L1_DevPcUlDpchRst
+ 0x10031606 0x5 _L1_DevPcDlDpchRst
+ 0x1003160b 0x17 _L1_DevPcDpchCfg
+ 0x10031622 0x8 _L1_DevPcDpchRst
+ 0x1003162a 0x39 _L1_DevPcDpchMapFunc
+ 0x10031663 0x27 _L1_DevPcDlDpchSyncPro
+ 0x1003168a 0x58 _L1_DevPcDlDpchDataOlpc
+ 0x100316e2 0x41 _L1_DevPcDlDpchOuterAdj
+ 0x10031723 0xb7 _L1_DevPcDlDpchOuterPro
+ 0x100317da 0x54 _L1_DevPcDlDpchGetDlTpc
+ 0x1003182e 0x4a _L1_DevPcDlDpchInnerPro
+ 0x10031878 0x30 _L1_DevPcDlDpchNonTrustUlCmd
+ 0x100318a8 0xe4 _L1_DevPcDlDpchGetSlotUlCmd
+ 0x1003198c 0x8b _L1_DevPcDlDpchGetUlCmd
+ 0x10031a17 0x3b _L1_DevPcUlDpchMapDlTpc
+ 0x10031a52 0x80 _L1_DevPcUlDpchSetDlTpc
+ 0x10031ad2 0x86 _L1_DevPcUlDpchMapUlTpc
+ 0x10031b58 0x50 _L1_DevPcUlDpchParseUlCmd
+ 0x10031ba8 0x99 _L1_DevPcUlDpchCloseLoopPwr
+ 0x10031c41 0x38 _L1_DevPcDlDpchCloseLoopPro
+ 0x10031c79 0x56 _L1_DevPcUlDpchCloseLoopPro
+ 0x10031ccf 0x59 _L1_DevPcDpchCloseLoopPro
+ 0x10031d28 0xf7 _L1_DevPcUlDpchPro
+ 0x10031e1f 0xc _L1_DevPcSetUlDpchPwr
+ .text 0x10031e2b 0x505 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_hsdpa.o)
+ 0x10031e2b 0xe _L1_DevPcHsdpaTpcSsMerge
+ 0x10031e39 0x64 _L1_DevPcDschTpcSsCalcMerge
+ 0x10031e9d 0xa _L1_DevPcTpcCmd2Symbol
+ 0x10031ea7 0x52 _L1_DevPcHssichInit
+ 0x10031ef9 0x47 _L1_DevPcHsscchClsInit
+ 0x10031f40 0x55 _L1_DevPcHsscchOuterInit
+ 0x10031f95 0x65 _L1_DevPcHsdpaInit
+ 0x10031ffa 0x5 _L1_DevPcHsdpaRst
+ 0x10031fff 0x5a _L1_DevPcHsscchClsPro
+ 0x10032059 0x5a _L1_DevPcHsscchOuterPro
+ 0x100320b3 0x71 _L1_DevPcGetHssichTpcSsCmd
+ 0x10032124 0x5e _L1_DevPcHssichCloseLoopPro
+ 0x10032182 0x2f _L1_DevPcHsdpaDownPro
+ 0x100321b1 0x90 _L1_DevPcHsdpaCloseLoopPro
+ 0x10032241 0xde _L1_DevPcHssichPro
+ 0x1003231f 0x11 _L1_DevPcSetHssichPwr
+ .text 0x10032330 0x2a1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_ra.o)
+ 0x10032330 0xb7 _L1_DevPcUppchPwr
+ 0x100323e7 0x3b _L1_DevPcUppchTiming
+ 0x10032422 0xa0 _L1_DevPcPrachPwr
+ 0x100324c2 0x6a _L1_DevPcUppchPro
+ 0x1003252c 0x59 _L1_DevPcPrachPro
+ 0x10032585 0x2b _L1_DevPcGetUppchPwr
+ 0x100325b0 0x21 _L1_DevPcGetPrachPwr
+ .text 0x100325d1 0x79b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_utr.o)
+ 0x100325d1 0x43 _L1_DrvUtrReset
+ 0x10032614 0xc _L1_DrvUtrInit
+ 0x10032620 0xf6 _L1_DrvUtrDchConfig
+ 0x10032716 0x60 _L1_DrvUtrRachConfig
+ 0x10032776 0xe _L1_DrvUtrEnable
+ 0x10032784 0x1c _L1_DrvUtrClose
+ 0x100327a0 0x8a _L1_DrvUtrTbAndCbConfig
+ 0x1003282a 0x124 _L1_DrvUtrRMConfig
+ 0x1003294e 0x7 _L1_DrvUtrGetRamAddr
+ 0x10032955 0x1b _L1_DrvUtrClearRmPara
+ 0x10032970 0xd _L1_DrvUtrRegClear
+ 0x1003297d 0xe _L1_DrvUtrGetCrcMode
+ 0x1003298b 0xe _L1_DrvUtrGetCodingType
+ 0x10032999 0xe _L1_DrvUtrGetRamData
+ 0x100329a7 0x9 _L1_DrvUtrGetInterlv1RamStateTd
+ 0x100329b0 0x11 _L1_DrvFdtUtrCfgCleanReg
+ 0x100329c1 0x3ab _L1_DrvFdtUtrCfgUlReg
+ .text 0x10032d6c 0xaad T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_rach.o)
+ 0x100331d1 0x48 _L1_SchedRachProcPSCmd
+ 0x10033219 0x55 _L1_SchedRachProcL1Cmd
+ 0x1003326e 0xcd _L1_SchedRachProcPreSchedHandler
+ 0x1003333b 0x5d _L1_SchedRachProcUpSendFailCmd
+ 0x10033398 0xb3 _L1_SchedRachProcIdleStCmd
+ 0x1003344b 0xad _L1_SchedRachProcIRecFpachStCmd
+ 0x100334f8 0x128 _L1_SchedRachProcIWaitFpachStCmd
+ 0x10033620 0xe _L1_SchedRachProcISendRachStCmd
+ 0x1003362e 0x4d _L1_SchedRachProcSched
+ 0x1003367b 0x5a _L1_SchedRachProcSend2PS
+ 0x100336d5 0xa8 _L1_SchedRachProcL1InnerReq
+ 0x1003377d 0x9 _L1_SchedRachProcL1InnerAbort
+ 0x10033786 0x10 _L1_SchedRachProcReset
+ 0x10033796 0x60 _L1_SchedRachProcInit
+ 0x100337f6 0xa _L1_SchedRachSetwUarFcn
+ 0x10033800 0x9 _L1_SchedRachSetFachRel
+ 0x10033809 0x8 _L1_SchedRachSetUppchflg
+ 0x10033811 0x8 _L1_SchedRachGetUppchflg
+ .text 0x10033819 0x92 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_common.o)
+ 0x10033819 0x4e _L1_SchedDchActiveSsfnCalc
+ 0x10033867 0x44 _L1_ShedCmnCalResWinInfo
+ .text 0x100338ab 0x145 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ 0x100338ab 0x54 _L1w_TaskPrioEng
+ 0x100338ff 0xf1 _L1w_ModemDrvInit
+ .text 0x100339f0 0x8e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ 0x100339f0 0x46 _L1w_AtNvInit
+ 0x10033a36 0x48 _L1w_NvDataInit
+ .text 0x10033a7e 0x13d5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o)
+ 0x10033a7e 0x2e _L1w_DevBchBchSchedReq
+ 0x10033aac 0x2c _L1w_DevBchAfcSupplyReq
+ 0x10033ad8 0x26 _L1w_DevBchAfcLockCnf
+ 0x10033afe 0x2e _L1w_DevBchIntInd
+ 0x10033b2c 0x3f _L1w_BchTask
+ 0x10033b6b 0x45 _L1w_DevBchTimeDecrease
+ 0x10033bb0 0xa _L1w_DevBchClearAfcInfo
+ 0x10033bba 0x1d _L1w_DevBchPiSymbol2Float
+ 0x10033bd7 0x53 _L1w_DevBchPiReset
+ 0x10033c2a 0x3e _L1w_DevBchReset
+ 0x10033c68 0x35 _L1w_DevBchInit
+ 0x10033c9d 0x1f _L1w_DevBchTpuIntHandle
+ 0x10033cbc 0x82 _L1w_DevBchPichSched
+ 0x10033d3e 0x222 _L1w_DevBchPichRxCfg
+ 0x10033f60 0x97 _L1w_DevBchBchSched
+ 0x10033ff7 0x1b4 _L1w_DevBchBchRxCfg
+ 0x100341ab 0xa8 _L1w_DevBchAfcSupply
+ 0x10034253 0xca _L1w_DevBchCpichRxCfg
+ 0x1003431d 0x23 _L1w_DevBchAfcLockHandle
+ 0x10034340 0x57 _L1w_DevBchPichIntHandle
+ 0x10034397 0xf8 _L1w_DevBchBchIntHandle
+ 0x1003448f 0x80 _L1w_DevBchCpichIntHandle
+ 0x1003450f 0x24 _L1w_DevBchTimeConflict
+ 0x10034533 0x56 _L1w_DevBchCalcFingerAdj
+ 0x10034589 0x32 _L1w_DevBchCalcFingerBound
+ 0x100345bb 0x6c _L1w_DevBchAddTpuEvent
+ 0x10034627 0x7e _L1w_DevBchBchAfcProc
+ 0x100346a5 0x54 _L1w_DevBchPichAfcProc
+ 0x100346f9 0x14d _L1w_DevBchAdjustFinger
+ 0x10034846 0x2d _L1w_DevBchCpichIntMask
+ 0x10034873 0x16 _L1w_DevBchClearAfcData
+ 0x10034889 0xf _L1w_DevBchReadSfnResult
+ 0x10034898 0x5c _L1w_DevBchFindBchRxCfgBuf
+ 0x100348f4 0x5c _L1w_DevBchRtCfgTimeValid
+ 0x10034950 0x49 _L1w_DevBchPichIntPostProc
+ 0x10034999 0x15 _L1w_DevBchCalcFingerDist
+ 0x100349ae 0xc7 _L1w_DevBchSigProc
+ 0x10034a75 0x3a _L1w_DevBchCalcChipDist
+ 0x10034aaf 0x25 _L1w_DevBchStopBchDecode
+ 0x10034ad4 0x7b _L1w_DevBchSetIQRotate
+ 0x10034b4f 0x26 _L1w_DevBchNCellAfcFeedback
+ 0x10034b75 0x60 _L1w_DevBchCaclRtSfnOffset
+ 0x10034bd5 0xcf _L1w_DevBchFingerManage
+ 0x10034ca4 0x42 _L1w_DevBchFingerUpdate
+ 0x10034ce6 0x21 _L1w_DevBchStopBchDecodeReq
+ 0x10034d07 0xe6 _L1w_DevBchPiaiAfcHandle
+ 0x10034ded 0x66 _L1w_DevBchFilterFinger
+ .text 0x10034e53 0x2301 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ 0x10034e53 0x41 _L1w_DevMeasInit
+ 0x10034e94 0x41 _L1w_DevMeasReset
+ 0x10034ed5 0xd _L1w_DevMeasJudgeBufStateFull
+ 0x10034ee2 0xe _L1w_DevMeasJudgeBufState
+ 0x10034ef0 0x2cc _L1w_DevMeasConfigHw
+ 0x100351bc 0x40 _L1w_DevMeasCpichMeasCnf
+ 0x100351fc 0x139 _L1w_DevMeasSideSupres
+ 0x10035335 0x94 _L1w_DevMeasPathDetct
+ 0x100353c9 0xd2 _L1w_DevMeasDeleteSttdDetctCell
+ 0x1003549b 0xc1 _L1w_DevMeasSttdDetct
+ 0x1003555c 0x4f _L1w_DevMeasCalcFingerPeakSum
+ 0x100355ab 0x5f _L1w_DevMeasCalcSearchWindowSum
+ 0x1003560a 0x29 _L1w_DevMeasSortFirstFinger
+ 0x10035633 0xd _L1w_DevMeasIsSearchWindowPath
+ 0x10035640 0x25 _L1w_DevMeasSelNewWindow
+ 0x10035665 0xa8 _L1w_DevMeasSelWinFinInfo
+ 0x1003570d 0xbe _L1w_DevMeasAdrWindowUpdate
+ 0x100357cb 0x104 _L1w_DevMeasTimeAdjust
+ 0x100358cf 0x5f _L1w_DevMeasLOG10Cal
+ 0x1003592e 0x146 _L1w_DevMeasCalRssi
+ 0x10035a74 0x17a _L1w_DevMeasSaveCnfCellInfo
+ 0x10035bee 0x35 _L1w_DevMeasEcIoClaib
+ 0x10035c23 0x104 _L1w_DevMeasGetRscpNew
+ 0x10035d27 0xc0 _L1w_DevMeasGetRscp
+ 0x10035de7 0x249 _L1w_DevMeasCalRscp1New
+ 0x10036030 0x2dd _L1w_DevMeasCalRscp1
+ 0x1003630d 0xed _L1w_DevMeasPreSyncFingerCmp
+ 0x100363fa 0xee _L1w_DevMeasAddPreSyncFingernew
+ 0x100364e8 0x14d _L1w_DevMeasAddPreSyncFinger
+ 0x10036635 0x2f _L1w_DevMeasSetPreSyncInfo
+ 0x10036664 0x4 _L1w_DevMeasPreSyncHandler
+ 0x10036668 0x134 _L1w_DevMeasRscpHandler
+ 0x1003679c 0x25 _L1w_DevMeasIntMissHandle
+ 0x100367c1 0xb2 _L1w_DevMeasGetTpuEvtTim
+ 0x10036873 0x50 _L1w_DevMeasSetAbnormalIntInfo
+ 0x100368c3 0x1b6 _L1w_DevMeasReqProc
+ 0x10036a79 0x216 _L1w_DevMeasIntProc
+ 0x10036c8f 0x62 _L1w_DevMeasTpuHandler
+ 0x10036cf1 0x48 _L1w_DevMeasIntInd
+ 0x10036d39 0x33 _L1w_DevMeasGetPreSyncInfo
+ 0x10036d6c 0xf _L1w_DevMeasCheckWorkSt
+ 0x10036d7b 0xe7 _L1w_DevMeasSetAgcStartTime
+ 0x10036e62 0x3e _L1w_DevMeasAgcTrans
+ 0x10036ea0 0x2d _L1w_DevMeasSetAgc
+ 0x10036ecd 0x18 _L1w_DevMeasOfflinedataStartTime
+ 0x10036ee5 0xc _L1w_DevMeasGetOfflinedataEndtTime
+ 0x10036ef1 0x2d _L1w_DevMeasOfflinedataSavedReq
+ 0x10036f1e 0xe7 _L1w_DevMeasCfgOfflineData
+ 0x10037005 0x15 _L1w_DevMeasSaveAgcValue
+ 0x1003701a 0x16 _L1w_DevMeasSaveAgcStartTime
+ 0x10037030 0x63 _L1w_DevMeasJugeIsSaveAgcInfo
+ 0x10037093 0xe _L1w_DevMeasClearOfflineDataInfo
+ 0x100370a1 0xb3 _L1w_MeasTask
+ .text 0x10037154 0x2bc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ 0x10037154 0x8 _L1w_DevHsdpaActiveFlgGet
+ 0x1003715c 0x8 _L1w_DevHsdpaActiveFlgSet
+ 0x10037164 0x8 _L1w_DevHsdpaHdtrUseTurboFlgGet
+ 0x1003716c 0x8 _L1w_DevHsdpaHdtrUseTurboFlgSet
+ 0x10037174 0x8 _L1w_DevHsdpaGetAgcDownFlg
+ 0x1003717c 0x7 _L1w_DevHspaFachSetEdchActive
+ 0x10037183 0x7 _L1w_DevHspaFachGetEdchActive
+ 0x1003718a 0x18 _L1w_DevHspaFachSubFrmInt
+ 0x100371a2 0x47 _L1w_DevHspaReset
+ 0x100371e9 0x3e _L1w_DevHspaInit
+ 0x10037227 0x18 _L1w_DevHspaCmnMsgProc
+ 0x1003723f 0x3c _L1w_DevHsupaFachMsgProc
+ 0x1003727b 0x4a _L1w_DevHsdpaFachMsgProc
+ 0x100372c5 0x5e _L1w_DevHsupaMsgProc
+ 0x10037323 0x83 _L1w_DevHsdpaMsgProc
+ 0x100373a6 0x6a _L1w_HspaTask
+ .text 0x10037410 0x951 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
+ 0x10037410 0x15 _L1w_DevRtxReset
+ 0x10037425 0xf _L1w_DevRtxInit
+ 0x10037434 0x44 _L1w_DevRtxInitCfgMsgHandle
+ 0x10037478 0x1 _L1w_DevRtxTxRfOperate
+ 0x10037479 0x95 _L1w_DevRtxRxCfgTpuIntHandle
+ 0x1003750e 0xce _L1w_DevRtxTpuIntUlRfHandle
+ 0x100375dc 0xfa _L1w_DevRtxTpuIntHandle
+ 0x100376d6 0x24 _L1w_DevRtxResetInd
+ 0x100376fa 0x24 _L1w_DevRtxInitInd
+ 0x1003771e 0x21 _L1w_DevRtxTxPrachAbortReq
+ 0x1003773f 0x1 _L1w_DevRtxTxDpcchOfHspaCfgReq
+ 0x10037740 0x48 _L1w_DevRtxUlRfCtrlSendReq
+ 0x10037788 0x2c _L1w_DevRtxRxFingerCfgReq
+ 0x100377b4 0x32 _L1w_DevRtxRxPchCfgReq
+ 0x100377e6 0x21 _L1w_DevRtxRxAichRelReq
+ 0x10037807 0x31 _L1w_DevRtxRxFachCfgReq
+ 0x10037838 0x21 _L1w_DevRtxRxFachRelReq
+ 0x10037859 0x2f _L1w_DevRtxRxDlCmCfgReq
+ 0x10037888 0x21 _L1w_DevRtxRxDlCmAbortReq
+ 0x100378a9 0x2d _L1w_DevRtxRxHsscchCfgReq
+ 0x100378d6 0x2f _L1w_DevRtxRxEagchCfgReq
+ 0x10037905 0x21 _L1w_DevRtxRxEagchRelReq
+ 0x10037926 0x35 _L1w_DevRtxRxDrxUpdateReq
+ 0x1003795b 0x2a _L1w_DevRtxRxPlusCpichCfgReq
+ 0x10037985 0x26 _L1w_DevRtxRxPlusCpichRelReq
+ 0x100379ab 0x2e _L1w_DevRtxRxRgHiCfgReq
+ 0x100379d9 0x21 _L1w_DevRtxRxRgHiRelReq
+ 0x100379fa 0x21 _L1w_DevRtxTxTimingAdjustInd
+ 0x10037a1b 0x19 _L1w_DevRtxRxTpcPilotIntInd
+ 0x10037a34 0x18 _L1w_DevRtxRxHwTpcPlIntInd
+ 0x10037a4c 0x2f _L1w_DevRtxRxHwPiAiIntInd
+ 0x10037a7b 0x9 _L1w_DevRtxRxHwRakeIntInd
+ 0x10037a84 0x1a _L1w_DevRtxRxHwDtrIntInd
+ 0x10037a9e 0x22 _L1w_DevRtxRxPichIntInd
+ 0x10037ac0 0x22 _L1w_DevRtxRxAichIntInd
+ 0x10037ae2 0x102 _L1w_DevRtxRxTpcIntInd
+ 0x10037be4 0x3e _L1w_DevRtxRxTpcIntReq
+ 0x10037c22 0x66 _L1w_DevRtxRxPilotIntInd
+ 0x10037c88 0x21 _L1w_DevRtxRxTfciIntInd
+ 0x10037ca9 0x22 _L1w_DevRtxRxTtiIntInd
+ 0x10037ccb 0x21 _L1w_DevRtxRxAgchFactorIntInd
+ 0x10037cec 0x1 _L1w_DevRtxErrHandle
+ 0x10037ced 0x6 _L1w_DevRtxInfoGet
+ 0x10037cf3 0x6e _L1w_RtxTask
+ .text 0x10037d61 0x152c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ 0x10037d61 0x49 _L1w_DevRfcAtSetDebug
+ 0x10037daa 0x5 _L1w_DevRfcGetAfcHz
+ 0x10037daf 0x1 _L1w_DevRfcRbdpRegCfg
+ 0x10037db0 0x6a _L1w_DevRfcReadMrtr
+ 0x10037e1a 0x2a _L1w_DevRfSleepInfo
+ 0x10037e44 0xc7 _L1w_DevRfcReset
+ 0x10037f0b 0x29 _L1w_DevRfcInit
+ 0x10037f34 0x8f _L1w_NvDataCheck
+ 0x10037fc3 0x24 _L1w_DevRfcResetCnf
+ 0x10037fe7 0x24 _L1w_DevRfcInitCnf
+ 0x1003800b 0x53 _L1w_DevRfcSchedOpenReq
+ 0x1003805e 0x23 _L1w_DevRestoreReq
+ 0x10038081 0x2e _L1w_DevRfcIntInd
+ 0x100380af 0x34 _L1w_DevRfcDpaInfoCtrl
+ 0x100380e3 0x30 _L1w_DevRfcAntExchange
+ 0x10038113 0x2c _L1w_DevRfcAntSel
+ 0x1003813f 0x5e _L1w_DevRfcDiversityCtrl
+ 0x1003819d 0x35 _L1w_DevRfcChgeInfoCtrlTx
+ 0x100381d2 0x82 _L1w_DevRfcNotchHandle
+ 0x10038254 0xfd _L1w_DevRfcChgeInfoCtrlRx
+ 0x10038351 0x21 _L1W_DevRfcWaitForRfClose
+ 0x10038372 0xa6 _L1W_DevRfcSoltCtrlRfClose
+ 0x10038418 0x71 _L1w_DevRfcSlotCtrl
+ 0x10038489 0xc6 _L1w_DevRfcFdtTrigCtrl
+ 0x1003854f 0x56 _L1w_DevRfcFdtGetAgc
+ 0x100385a5 0xbc _L1w_DevRfcFdtFreqCtrl
+ 0x10038661 0x67 _L1w_DevRfcFdtApcCwPaHighCtrl
+ 0x100386c8 0x6e _L1w_DevRfcFdtApcCwPaLowCtrl
+ 0x10038736 0x67 _L1w_DevRfcFdtStartCtrl
+ 0x1003879d 0x91 _L1w_DevRfcNstTRXOpenCtrl
+ 0x1003882e 0x42 _L1w_DevRfcNstTRXCloseCtrl
+ 0x10038870 0x6a _L1w_DevRfcNstTRXFreqChge
+ 0x100388da 0x52 _L1w_DevRfcAmtCtrl
+ 0x1003892c 0x46 _L1w_DevRfcAgcRefPowLogUpdate
+ 0x10038972 0x29 _L1w_DevRfcIntTimeLogUpdate
+ 0x1003899b 0x19 _L1w_DevRfcMrtrConfLogUpdate
+ 0x100389b4 0x91 _L1w_DevRfcAgcRxStateLogUpdate
+ 0x10038a45 0x8 _L1w_DevRfcTempDacToIram
+ 0x10038a4d 0x31 _L1w_DevRfcIntLogUpdate
+ 0x10038a7e 0x25 _L1w_DevRfcIntAgcDcCalc
+ 0x10038aa3 0x2f _L1w_DevRfcIntNotchCfg
+ 0x10038ad2 0x48 _L1w_DevRfc_RpiCfg
+ 0x10038b1a 0x18 _L1w_DevRfc_RpiSet
+ 0x10038b32 0x56 _L1w_DevRfc_RpiPwrCtrl
+ 0x10038b88 0x5e _L1w_DevRfcIntAgcDcSet
+ 0x10038be6 0x25 _L1w_DevRfcIntAfcSet
+ 0x10038c0b 0x63 _L1w_DevRfcRfRegReadCtrl
+ 0x10038c6e 0x2b _L1w_DevRfcSleepStatusSet
+ 0x10038c99 0x6b _L1w_DevRfcIntProc
+ 0x10038d04 0x45 _L1w_DevRfcSetTxBandMaxPwr
+ 0x10038d49 0x8f _L1w_DevRfcTxPowerSet
+ 0x10038dd8 0x3f _L1w_DevRfcAfcHz2PPM
+ 0x10038e17 0x4d _L1w_DevRfcPpm2Hz
+ 0x10038e64 0x50 _L1w_DevRfcAfcUpdate
+ 0x10038eb4 0x1c _L1w_DevRfcOpenCtrl
+ 0x10038ed0 0x33 _L1w_DevRfcReusedReSourceRestore
+ 0x10038f03 0x1 _L1w_DevRfcTxTestMode
+ 0x10038f04 0x389 _L1w_RfcTask
+ .text 0x1003928d 0x1c63 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ 0x1003928d 0x1f _L1w_DevPcDpchReset
+ 0x100392ac 0x1 _L1w_DevPcDpchInit
+ 0x100392ad 0x94 _L1w_DevPcDpcchPowerFilter
+ 0x10039341 0x38 _L1w_DevPcDeltaPilotPro
+ 0x10039379 0x28 _L1w_DevPcPowerItpPro
+ 0x100393a1 0x1c _L1w_DevPcGapTpcJudge
+ 0x100393bd 0x4b _L1w_DevPcCmPowerPro
+ 0x10039408 0x60 _L1w_DevPcDpcchPowerCalc
+ 0x10039468 0x40 _L1w_DevPcDeltaPilotPowerCalc
+ 0x100394a8 0x3c _L1w_DevPcDeltaResumeCalc
+ 0x100394e4 0x3c _L1w_DevPcRppPowerCalc
+ 0x10039520 0x59 _L1w_DevPcGetDeltaPilotCalcMode
+ 0x10039579 0x2a _L1w_DevPcSigmaLastCalc
+ 0x100395a3 0xe0 _L1w_DevPcAjCalc
+ 0x10039683 0x5d _L1w_DevPcFindNearBeltaC
+ 0x100396e0 0x6b _L1w_DevPcFindNearBeltaD
+ 0x1003974b 0x47 _L1w_DevPcAjToBelta
+ 0x10039792 0x11 _L1w_DevPcDpchCurTfciBeltaCD
+ 0x100397a3 0x1f5 _L1w_DevPcBeltaCBeltaDCalc
+ 0x10039998 0xf0 _L1w_DevPcBeltaCBeltaDUpdate
+ 0x10039a88 0xcc _L1w_DevPcSecCmBetalUpd
+ 0x10039b54 0x18 _L1w_DlIlpc_reset
+ 0x10039b6c 0x8 _L1w_Olpc_reset
+ 0x10039b74 0x10 _L1w_DevPcOlpcCntReset
+ 0x10039b84 0xf _L1w_DevPcTpcGenReset
+ 0x10039b93 0xc _L1w_DevPcWindupReset
+ 0x10039b9f 0x42 _L1w_DevPcDlSirCmAdjust
+ 0x10039be1 0x90 _L1w_DevPcDlSirTargetCalc
+ 0x10039c71 0xec _L1w_DevPcFdpchSirCal
+ 0x10039d5d 0x111 _L1w_DevPcDpchSirCal
+ 0x10039e6e 0x49 _L1w_DevPcDlWindUpMode
+ 0x10039eb7 0x3c _L1w_DevPcSirSfAdjust
+ 0x10039ef3 0x95 _L1w_DevPcTpcGenDpcMode1
+ 0x10039f88 0xd4 _L1w_DevPcDlTpcCmdGen
+ 0x1003a05c 0x26 _L1w_DevFdpchRscpCalc
+ 0x1003a082 0x37 _L1w_DevDpchParaECal
+ 0x1003a0b9 0x88 _L1w_DevDpchRscpCalc
+ 0x1003a141 0x9a _L1w_DevPcPilotIntInd
+ 0x1003a1db 0x75 _L1w_DevPcRlsSetStaticAndSirThJudge
+ 0x1003a250 0xb2 _L1w_DevPcSetTpcSoftBit
+ 0x1003a302 0xc5 _L1w_DevPcTpcCombine
+ 0x1003a3c7 0x14 _L1w_DevPcTpcSingleRlPca1Calc
+ 0x1003a3db 0x11 _L1w_DevPcTpcSingleRlPca2Calc
+ 0x1003a3ec 0x89 _L1w_DevPcTpcMultiRlsPca1Calc
+ 0x1003a475 0x51 _L1w_DevPcTpcMultiRlsPca2Calc
+ 0x1003a4c6 0x46 _L1w_DevPcTpcSingleRlCombine
+ 0x1003a50c 0x4d _L1w_DevPcTpcMultiRlCombine
+ 0x1003a559 0x7e _L1w_DevPcTpcMultiRlsCombine
+ 0x1003a5d7 0x18 _L1w_DevPcSirReset
+ 0x1003a5ef 0x5 _L1w_DevPcBetalSeqalCal
+ 0x1003a5f4 0x58 _L1w_DevPcCurSlotPowCalc
+ 0x1003a64c 0x1f _L1w_DevPcIsOverPwr
+ 0x1003a66b 0x2a _L1w_DevPcSerachTfci
+ 0x1003a695 0x31 _L1w_DevPcCurSlotOverPowProc
+ 0x1003a6c6 0x40 _L1w_DevPcMaxPowerUpdate
+ 0x1003a706 0xf _L1w_DevPcUlTfcOverEstCmp
+ 0x1003a715 0xe9 _L1w_DevPcUlTfcOverEstRlt
+ 0x1003a7fe 0x22 _L1w_DevPcUphFrmAvrCalc
+ 0x1003a820 0x5 _L1w_DevPcUphMapRep
+ 0x1003a825 0x32 _L1w_DevPcUphResult
+ 0x1003a857 0x8 _L1w_DevPcGetUphValue
+ 0x1003a85f 0xab _L1w_DevPcUphProc
+ 0x1003a90a 0x91 _L1w_DevPcCfgInfoUpd
+ 0x1003a99b 0x83 _L1w_DevPcDchInfoGet
+ 0x1003aa1e 0x1e _L1w_DevDchOlpcBlerTargetMapping
+ 0x1003aa3c 0x8f _L1w_DevPcDchOlpcThParamGet
+ 0x1003aacb 0x59 _L1w_DevPcEfachBeltacCal
+ 0x1003ab24 0x104 _L1w_DevPcDchStartReqHandle
+ 0x1003ac28 0x1a _L1w_DevPcUldpchTfciInfoHandle
+ 0x1003ac42 0x27 _L1w_DevPcFDpchOutLoopAdj
+ 0x1003ac69 0x55 _L1w_DevPcDpchOutLoopAdj
+ 0x1003acbe 0x69 _L1w_DevPcDlRefTrchSel
+ 0x1003ad27 0x68 _L1w_DevPcOlpcInit
+ 0x1003ad8f 0x3f _L1w_DevPcDtrBlerInfoHandle
+ 0x1003adce 0x14 _L1w_DevPcTpcBerCal
+ 0x1003ade2 0x27 _L1w_DevPcRlsTpcBerPro
+ 0x1003ae09 0x7e _L1w_DevPcMutlRlsTpcBerCal
+ 0x1003ae87 0x33 _L1w_DevPcTpcBerCtr
+ 0x1003aeba 0x36 _L1w_DevPcOlpcCtrl
+ .text 0x1003aef0 0x1bca T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ 0x1003aef0 0x64 _L1w_DevHsdpaStartPc
+ 0x1003af54 0x27 _L1w_DevHspdaHwReset
+ 0x1003af7b 0x1b _L1w_DevHsdpaHwInit
+ 0x1003af96 0xa3 _L1w_DevHsdpaReset
+ 0x1003b039 0x1 _L1w_DevHsdpaNvInit
+ 0x1003b03a 0x10d _L1w_DevHsdpaParaInit
+ 0x1003b147 0x187 _L1w_DevHsdpaRegTpuEvent
+ 0x1003b2ce 0x1ac _L1w_DevHsdpaCfgProc
+ 0x1003b47a 0x6e _L1w_DevHsdpaRelProc
+ 0x1003b4e8 0xc4 _L1w_DevHsdpaIcSymModProc
+ 0x1003b5ac 0xa1 _L1w_DevHsdpaAdrCirIntProc
+ 0x1003b64d 0xeb _L1w_DevHsdpaAdrCpichIntProc
+ 0x1003b738 0x30 _L1w_DevHsdpaHsscchPart1IntProc
+ 0x1003b768 0x4d _L1w_DevHsdpaHsscchPart2IntProc
+ 0x1003b7b5 0x30 _L1w_DevHsdpaHdtrIntProc
+ 0x1003b7e5 0x3a _L1w_DevHsdpaCfn2SfnTime
+ 0x1003b81f 0x37 _L1w_DevHsdpaOrderActProc
+ 0x1003b856 0x152 _L1w_DevHsdpaDchTpuProc
+ 0x1003b9a8 0x42f _L1w_DevHsdpaTpuTraceLog
+ 0x1003bdd7 0xfb _L1w_DevHsdpaIsJudgechangjing3
+ 0x1003bed2 0xe0 _L1w_DevHsdpaTpuProc
+ 0x1003bfb2 0xb4 _L1w_DevHsdpaCompareCellInfo
+ 0x1003c066 0x173 _L1w_DevHsdpaIsJudgePsrOver512
+ 0x1003c1d9 0x105 _L1w_DevHsdpaPsrOver512
+ 0x1003c2de 0x2a _L1w_DevHsdpaPsrFingerOldDaNew
+ 0x1003c308 0x2a _L1w_DevHsdpaPsrFingerNewXiaoOld
+ 0x1003c332 0xea _L1w_DevHsdpaPsrIschangjing3
+ 0x1003c41c 0x1d0 _L1w_DevHsdpaTxTpuProc
+ 0x1003c5ec 0x56 _L1w_DevHsdpaPsrUpdateProc
+ 0x1003c642 0x3f _L1w_DevHsdpaCmUpdateProc
+ 0x1003c681 0x4a _L1w_DevHsdpaCfgReq
+ 0x1003c6cb 0x29 _L1w_DevHsdpaRelReq
+ 0x1003c6f4 0x29 _L1w_DevHsdpaIcSymModIntInd
+ 0x1003c71d 0x29 _L1w_DevHsdpaAdrCirIntInd
+ 0x1003c746 0x29 _L1w_DevHsdpaAdrCpichIntInd
+ 0x1003c76f 0x29 _L1w_DevHsdpaHsscchPart1IntInd
+ 0x1003c798 0x29 _L1w_DevHsdpaHsscchPart2IntInd
+ 0x1003c7c1 0x29 _L1w_DevHsdpaHdtrIntInd
+ 0x1003c7ea 0x3b _L1w_DevDlsHsdpaPsrUpdateReq
+ 0x1003c825 0x35 _L1w_DevHsdpaCmUpdateReq
+ 0x1003c85a 0x3b _L1w_DevHsdpaHsscchOrdInd
+ 0x1003c895 0x4c _L1w_DevHsdpaFachCfgReq
+ 0x1003c8e1 0x26 _L1w_DevHsdpaFachRelReq
+ 0x1003c907 0x29 _L1w_DevHsdpaFachRcvReq
+ 0x1003c930 0x26 _L1w_DevHsdpaFachHrntiUpdateReq
+ 0x1003c956 0x21 _L1w_DevHsdpaFachDataInd
+ 0x1003c977 0x4b _L1w_DevHsdpaPchCfgReq
+ 0x1003c9c2 0x21 _L1w_DevHsdpaPchRelReq
+ 0x1003c9e3 0x26 _L1w_DevHsdpaRtxPiInd
+ 0x1003ca09 0x28 _L1w_DevHsdpaDmaIntInd
+ 0x1003ca31 0x39 _L1w_DevHsdpaDataDmaCpy
+ 0x1003ca6a 0x24 _L1w_DevHsdpaCurTime2SfnTime
+ 0x1003ca8e 0x2c _L1w_DevHsdpaGetCurSfnTime
+ .text 0x1003caba 0x16ff T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ 0x1003caba 0x20 _L1w_DevHsdpaLessIsAct
+ 0x1003cada 0xa5 _L1w_DevHsdpaLessParaInit
+ 0x1003cb7f 0x2f _L1w_DevHsdpaLessOrdIndProc
+ 0x1003cbae 0x33 _L1w_DevHsdpaLessTimeRcd
+ 0x1003cbe1 0x5f _L1w_DevHsdpaLessCfgTraceLog
+ 0x1003cc40 0xc _L1w_DevHsdpaLessCfgAllTb
+ 0x1003cc4c 0x23 _L1w_DevHsdpaLessFindIdleHarq
+ 0x1003cc6f 0x231 _L1w_DevHsdpaPart2Type2Proc
+ 0x1003cea0 0xc5 _L1w_DevHsdpaDchLessProc
+ 0x1003cf65 0x7e _L1w_DevHsdpaPart2LessProc
+ 0x1003cfe3 0x23 _L1w_DevHsdpaIsLessValid
+ 0x1003d006 0x18 _L1w_DevHsdpaLessFindHsdschTti
+ 0x1003d01e 0x1c9 _L1w_DevHsdpaDchLessHdtrIntProc
+ 0x1003d1e7 0x24 _L1w_DevHsdpaLessHdtrIntProc
+ 0x1003d20b 0x6b _L1w_DevHsdpaPchSaveAdrInitCfg
+ 0x1003d276 0x51 _L1w_DevHsdpaPchSaveHsscchInitCfg
+ 0x1003d2c7 0x7d _L1w_DevHsdpaPchRxInitRcvProc
+ 0x1003d344 0xae _L1w_DevHsdpaPchSaveLessPara
+ 0x1003d3f2 0x8e _L1w_DevHsdpaPchSaveAdrSubFrmCfg
+ 0x1003d480 0x42 _L1w_DevHsdpaPchSaveIcPsrCfg
+ 0x1003d4c2 0x9a _L1w_DevHsdpaPchRxSubFrmProc
+ 0x1003d55c 0x5f _L1w_DevHsdpaPchCfgProc
+ 0x1003d5bb 0x2d _L1w_DevHsdpaPchRelProc
+ 0x1003d5e8 0x18 _L1w_DevHsdpaPchTpuProc
+ 0x1003d600 0x62 _L1w_DevHsdpaPchSavePart1IntCfg
+ 0x1003d662 0x66 _L1w_DevHsdpaPchPart2Type1Proc
+ 0x1003d6c8 0x12d _L1w_DevHsdpaPchHdtrIntProc
+ 0x1003d7f5 0x92 _L1w_DevHsdpaPchLessProc
+ 0x1003d887 0x16d _L1w_DevHsdpaPchLessHdtrIntProc
+ 0x1003d9f4 0xa1 _L1w_DevHsdpaRtxPiIndProc
+ 0x1003da95 0x71 _L1w_DevHsdpaFachStartPc
+ 0x1003db06 0x4e _L1w_DevHsdpaFachSaveHsdpcchAckCfg
+ 0x1003db54 0x5c _L1w_DevHsdpaFachSaveHsdpcchCqiCfg
+ 0x1003dbb0 0x4d _L1w_DevHsdpaFachCqiSendCtrl
+ 0x1003dbfd 0x6e _L1w_DevHsdpaFachSaveAdrInitCfg
+ 0x1003dc6b 0x4a _L1w_DevHsdpaFachSaveHsscchInitCfg
+ 0x1003dcb5 0x52 _L1w_DevHsdpaFachRxInitRcvProc
+ 0x1003dd07 0x2e _L1w_DevHsdpaFachTxInitSendProc
+ 0x1003dd35 0x81 _L1w_DevHsdpaFachSaveAdrSubFrmCfg
+ 0x1003ddb6 0x83 _L1w_DevHsdpaFachRxSubFrmProc
+ 0x1003de39 0x56 _L1w_DevHsdpaFachTxSubFrmProc
+ 0x1003de8f 0x68 _L1w_DevHsdpaFachCfgProc
+ 0x1003def7 0x44 _L1w_DevHsdpaFachRelProc
+ 0x1003df3b 0x22 _L1w_DevHsdpaFachTpuProc
+ 0x1003df5d 0x2e _L1w_DevHsdpaFachSavePart1IntCfg
+ 0x1003df8b 0x131 _L1w_DevHsdpaFachHdtrIntProc
+ 0x1003e0bc 0x3c _L1w_DevHsdpaFachRcvProc
+ 0x1003e0f8 0x28 _L1w_DevHsdpaFachHrntiUpdateProc
+ 0x1003e120 0x79 _L1w_DevHsdpaFachEdchIndProc
+ 0x1003e199 0x20 _L1w_DevHsdpaFachSetHsdpcchFlg
+ .text 0x1003e1b9 0x1019 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o)
+ 0x1003e1b9 0x60 _L1w_DevRtxRxFingerCfg
+ 0x1003e219 0xe2 _L1w_DevRtxRxCpichCfg
+ 0x1003e2fb 0x4f _L1w_DevRtxRxPichCfg
+ 0x1003e34a 0x12 _L1w_DevRtxRxPichRel
+ 0x1003e35c 0x50 _L1w_DevRtxRxPchCfg
+ 0x1003e3ac 0x24 _L1w_DevRtxRxPchRel
+ 0x1003e3d0 0x2f _L1w_DevRtxRxAichRakeCfg
+ 0x1003e3ff 0x26 _L1w_DevRtxRxAichCfg
+ 0x1003e425 0x5 _L1w_DevRtxRxAichRel
+ 0x1003e42a 0x2e _L1w_DevRtxRxFachRakeCfg
+ 0x1003e458 0x46 _L1w_DevRtxRxFachCfg
+ 0x1003e49e 0x21 _L1w_DevRtxRxFachRel
+ 0x1003e4bf 0xa5 _L1w_DevRtxRxDlDpchRakeCfg
+ 0x1003e564 0x40 _L1w_DevRtxRxDlDpchCfg
+ 0x1003e5a4 0x26 _L1w_DrvDpramRxWriteClearData
+ 0x1003e5ca 0x39 _L1w_DevRtxRxDlDpchRel
+ 0x1003e603 0x16d _L1w_DevRtxRxDlCmSlotCfg
+ 0x1003e770 0xe5 _L1w_DevRtxRxDlCmSlotRel
+ 0x1003e855 0x63 _L1w_DevRtxRxDlCmCfgTpuIntHandle
+ 0x1003e8b8 0x1ff _L1w_DevRtxRxDlCmCfg
+ 0x1003eab7 0x6f _L1w_DevRtxRxFdpchRakeCfg
+ 0x1003eb26 0x3d _L1w_DevRtxRxFdpchCfg
+ 0x1003eb63 0x5 _L1w_DevRtxRxFdpchRel
+ 0x1003eb68 0x34 _L1w_DevRtxRxHsscchRakeCfg
+ 0x1003eb9c 0x39 _L1w_DevRtxRxHsscchCfg
+ 0x1003ebd5 0x5 _L1w_DevRtxRxHsscchRel
+ 0x1003ebda 0x38 _L1w_DevRtxRxEagchRakeCfg
+ 0x1003ec12 0x34 _L1w_DevRtxRxEagchCfg
+ 0x1003ec46 0xf _L1w_DevRtxRxEagchRel
+ 0x1003ec55 0xbc _L1w_DevRtxRxRgHiRakeCfg
+ 0x1003ed11 0x4b _L1w_DevRtxRxRgHiCfg
+ 0x1003ed5c 0x5 _L1w_DevRtxRxRgHiRel
+ 0x1003ed61 0x6b _L1w_DevRtxRxCctrchCfgHandle
+ 0x1003edcc 0x11b _L1w_DevRtxRxCfgHandle
+ 0x1003eee7 0x2f _L1w_DevRtxRxDlTpcPlCfg
+ 0x1003ef16 0x7e _L1w_DevRtxRxIntFingerCfg
+ 0x1003ef94 0x69 _L1w_DevRtxRxIntCfg
+ 0x1003effd 0x6e _L1w_DevRtxRxDpchSlotForm
+ 0x1003f06b 0x71 _L1w_DevRtxRxSccpchSlotForm
+ 0x1003f0dc 0x5a _L1w_DevRtxRxComparaSlotForm
+ 0x1003f136 0x34 _L1w_DevRtxRxCmASlotForm
+ 0x1003f16a 0x34 _L1w_DevRtxRxCmBSlotForm
+ 0x1003f19e 0x34 _L1w_DevRtxRxNormalSlotForm
+ .text 0x1003f1d2 0x92c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ 0x1003f1d2 0x13 _L1w_DevRtxTimeCmp
+ 0x1003f1e5 0x2d _L1w_DevRtxUlRfcReq
+ 0x1003f212 0x37 _L1w_DevRtxUlRfTblInit
+ 0x1003f249 0x2f _L1w_DevRtxUlRfGetNodeFromUnusedQ
+ 0x1003f278 0x17 _L1w_DevRtxUlRfPutNode2UnusedQ
+ 0x1003f28f 0x31 _L1w_DevRtxUlRfQueueInsert
+ 0x1003f2c0 0x41 _L1w_DevRtxUlRfQueueGet
+ 0x1003f301 0xf _L1w_DevRtxUlRfQueueSearch
+ 0x1003f310 0x67 _L1w_DevRtxUlRfStartSched
+ 0x1003f377 0x262 _L1w_DevRtxUlRfCtrlReq
+ 0x1003f5d9 0x1de _L1w_DevRtxUlRfSchedPick
+ 0x1003f7b7 0x81 _L1w_DevRtxUlRfSchedLink
+ 0x1003f838 0x12f _L1w_DevRtxUlRfSchedMerge
+ 0x1003f967 0x18a _L1w_DevRtxUlRfSched
+ 0x1003faf1 0xd _L1w_DevRtxUlRfStopSched
+ .text 0x1003fafe 0xf38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ 0x1003fafe 0x7 _L1w_DevTxGetDchState
+ 0x1003fb05 0x11 _L1w_DevTxGetRfCtrlPara
+ 0x1003fb16 0x15 _L1w_DevTxDchReset
+ 0x1003fb2b 0x39 _L1w_DevTxOpenRfc
+ 0x1003fb64 0x39 _L1w_DevTxCloseRfc
+ 0x1003fb9d 0x68 _L1w_DevTxCmRfcCfg
+ 0x1003fc05 0x50 _L1w_DevTxNormalSlotForm
+ 0x1003fc55 0x5e _L1w_DevTxCmSlotForm
+ 0x1003fcb3 0x1c _L1w_DevTxCalcCmPliot
+ 0x1003fccf 0x39 _L1w_DevTxGetUlMaxMinTti
+ 0x1003fd08 0x10e _L1w_DevTxGetDchParam
+ 0x1003fe16 0x75 _L1w_DevTxUlCmTfciAnalysis
+ 0x1003fe8b 0x29 _L1w_DevTxHsupaTransInd
+ 0x1003feb4 0x16b _L1w_DevTxDchToPcStart
+ 0x1004001f 0x26 _L1w_DevTxDchToPcStop
+ 0x10040045 0x64 _L1w_DevTxDchCmParaToPc
+ 0x100400a9 0x27 _L1w_DevTxDpcchPreambleToPc
+ 0x100400d0 0x2a _L1w_DevTxDpdchTfciToPc
+ 0x100400fa 0x177 _L1w_DevTxDataUpdate
+ 0x10040271 0x55 _L1w_DevTxGetUtrPara
+ 0x100402c6 0x115 _L1w_DevTxDchUtrCfg
+ 0x100403db 0x77 _L1w_DevTxDchCmProc
+ 0x10040452 0x154 _L1w_DevTxDchSendCfg
+ 0x100405a6 0xad _L1w_DevTxDchPreambleSendProc
+ 0x10040653 0x29 _L1w_DevTxDchPostVerifyFailProc
+ 0x1004067c 0x94 _L1w_DevTxDchPreambleIntHandle
+ 0x10040710 0xd9 _L1w_DevTxDpchSendCndCheck
+ 0x100407e9 0x59 _L1w_DevTxDpchIntHandle
+ 0x10040842 0x54 _L1w_DevTxDchTpuIntHandle
+ 0x10040896 0x65 _L1w_DevTxDchRelMsgHandle
+ 0x100408fb 0x8b _L1w_DevTxCmCfgMsgHandle
+ 0x10040986 0xb0 _L1w_DevTxDchCfgMsgHandle
+ .text 0x10040a36 0x6e4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ 0x10040a36 0xf _L1W_DevHsupaInitMacro
+ 0x10040a45 0xc _L1W_DevHsupaCalCBNum
+ 0x10040a51 0x21 _L1W_DevHsupaCalcCBLength
+ 0x10040a72 0xa _L1W_DevHsupaCalInterleavingRow
+ 0x10040a7c 0x3a _L1W_DevHsupaCalCodeBlockConf
+ 0x10040ab6 0x1c _L1w_DevHsupaCalMaxNej
+ 0x10040ad2 0x99 _L1W_DevHsupaCalSfOneEtfc
+ 0x10040b6b 0xfd _L1W_DevHsupaCalAllSFConf
+ 0x10040c68 0x12a _L1W_DevHsupaCalSFConf
+ 0x10040d92 0x94 _L1W_DevHsupaCalRmRv
+ 0x10040e26 0x9b _L1W_DevHsupaCalRmPara
+ 0x10040ec1 0x41 _L1W_DevHsupaCalChannelCodeConf
+ 0x10040f02 0x7a _L1W_DevHsupaCalInterleavingConf
+ 0x10040f7c 0x37 _L1W_DevHsupaReTransBitmapTtiTen
+ 0x10040fb3 0x6b _L1W_DevHsupaCalEtxBitmap
+ 0x1004101e 0x48 _L1W_DevHsupaCalEUTRConf
+ 0x10041066 0x6e _L1W_DevHsupaCalETXConf
+ 0x100410d4 0x46 _L1W_DevHsupaCalULConf
+ .text 0x1004111a 0x1358 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ 0x1004111a 0xb _L1w_DevRfcCtrlDbChgeInfoSet
+ 0x10041125 0xf _L1w_DevRfcCtrlDbChgeInfoInit
+ 0x10041134 0x2 _L1w_DevRfcCtrlDbSlotEndSet
+ 0x10041136 0x17 _L1w_DevRfcCtrlDbSlotInfoInit
+ 0x1004114d 0x61 _L1w_DevRfcCtrlDbInit
+ 0x100411ae 0x10 _L1w_DevRfcCtrlDbInitAll
+ 0x100411be 0x37 _L1w_DevRfcCtrlDbTimeContCheck
+ 0x100411f5 0x33 _L1w_DevRfcCtrlDbSlotChgeInfoWr
+ 0x10041228 0x16 _L1w_DevRfcCtrlDbGetDbInd
+ 0x1004123e 0x35 _L1w_DevRfcCtrlDbFrameChgeInfoWr
+ 0x10041273 0x2d _L1w_DevRfcCtrlDbGetSegLen
+ 0x100412a0 0x9f _L1w_DevRfcCtrlDbSlotEndUpdate
+ 0x1004133f 0x5c _L1w_DevRfcCtrlDbCtrlInfoUpdate
+ 0x1004139b 0x117 _L1w_DevRfcCtrlDbSchedUpdate
+ 0x100414b2 0x9c _L1w_DevRfcCtrlDbStPo2Chge
+ 0x1004154e 0x6d _L1w_DevRfcCtrlDbStPo1Chge
+ 0x100415bb 0x93 _L1w_DevRfcCtrlDbStPi2Chge
+ 0x1004164e 0x27 _L1w_DevRfcCtrlDbStPi1Chge
+ 0x10041675 0x63 _L1w_DevRfcCtrlDbStPi0Chge
+ 0x100416d8 0x49 _L1w_DevRfcCtrlDbStartInsert
+ 0x10041721 0xeb _L1w_DevRfcCtrlDbEndPo2Chge
+ 0x1004180c 0x5d _L1w_DevRfcCtrlDbEndPo1Chge
+ 0x10041869 0xf _L1w_DevRfcCtrlDbEndPo0Chge
+ 0x10041878 0x3f _L1w_DevRfcCtrlDbEndInsert
+ 0x100418b7 0xf9 _L1w_DevRfcCtrlDbDrvOpenUpdate
+ 0x100419b0 0xd _L1w_DevRfcCtrlDbGetAdr
+ 0x100419bd 0x4a _L1w_DevRfcCtrlDbChgeInfoHandle
+ 0x10041a07 0x10e _L1w_DevRfcCtrlDbGetSlotChgeInfo
+ 0x10041b15 0x39 _L1w_DevRfcAgcDbInit
+ 0x10041b4e 0x29 _L1w_DevRfcAfcDbInit
+ 0x10041b77 0x14 _L1w_DevRfcAgcDbFreqSearch
+ 0x10041b8b 0xe _L1w_DevRfcAgcDbSetFreqChgeFlag
+ 0x10041b99 0x21 _L1w_DevRfcAgcDbFindOldestPos
+ 0x10041bba 0x58 _L1w_DevRfcAgcDbFindFreqPos
+ 0x10041c12 0x21 _L1w_DevRfcAgcDbGetFreqInd
+ 0x10041c33 0x35 _L1w_DevRfcAgcDbFastAgcCond
+ 0x10041c68 0xd0 _L1w_DevRfcAgcDbAgcSet
+ 0x10041d38 0x3b _L1w_DevRfcAgcDbLockInfoUpdate
+ 0x10041d73 0x3a _L1w_DevRfcAgcCalcInfoUpdateCmn
+ 0x10041dad 0x2e _L1w_DevRfcAgcCalcInfoUpdateDpa
+ 0x10041ddb 0x58 _L1w_DevRfcAgcDbAgcStepCtrl
+ 0x10041e33 0x48 _L1w_DevRfcAgcDbAgcUpdate
+ 0x10041e7b 0x6e _L1w_DevRfcAgcDbAgcCalcSingleCh
+ 0x10041ee9 0x37 _L1w_DevRfcAgcDbAfterFastAgcSet
+ 0x10041f20 0x38 _L1w_DevRfcAgcDbFastAgcValUpdate
+ 0x10041f58 0x60 _L1w_DevRfcAgcDb2RMainChAdjCond
+ 0x10041fb8 0x6b _L1w_DevRfcAgcDb2RAgcHandle
+ 0x10042023 0x124 _L1w_DevRfcAgcDbAgcCalc
+ 0x10042147 0x1c _L1w_DevRfcAgcDbAgcEstEn
+ 0x10042163 0x3d _L1w_DevRfcAfcDbAfcSet
+ 0x100421a0 0x13 _L1w_DevRfcAfcDbGetAfcDbVal
+ 0x100421b3 0x1e _L1w_DevRfcSetRefFreq
+ 0x100421d1 0x43 _L1w_DevRfcAgcDbGetFreqAgcInfo
+ 0x10042214 0x62 _L1w_DevRfcAgcDbGetRssi
+ 0x10042276 0x9e _L1w_DevRfcAgcDbGetMeanpwr
+ 0x10042314 0x35 _L1w_DevRfcAgcDbAuxChInitSet
+ 0x10042349 0x42 _L1w_DevRfcAgcDbGetTableInd
+ 0x1004238b 0x7a _L1w_DevRfcAgcDbFdtAgcInit
+ 0x10042405 0x43 _L1w_DevRfcAgcDbNstAgcInit
+ 0x10042448 0x15 _L1w_DevRfcAgcDbTxChgeInfoWr
+ 0x1004245d 0x15 _L1w_DevRfcAgcDbRxChgeInfoWr
+ .text 0x10042472 0x2cb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
+ 0x10042472 0x26 _L1w_DevDlsSendIntMsg
+ 0x10042498 0x24 _L1w_DevDlsSendCnf
+ 0x100424bc 0xf _L1w_DevDlsReset
+ 0x100424cb 0xf _L1w_DevDlsInit
+ 0x100424da 0x263 _L1w_DlsTask
+ .text 0x1004273d 0x12a5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ 0x1004273d 0x89 _L1w_DevHsdpaSubFrmIsInCm
+ 0x100427c6 0x78 _L1w_DevHsdpaCalcTimingInfo
+ 0x1004283e 0x2d _L1w_DevHsdpaCalcAckNackPos
+ 0x1004286b 0x52 _L1w_DevHsdpaCalcTbSizeByTbs
+ 0x100428bd 0x23 _L1w_DevHsdpaCalcTbSizeByTbsIdx
+ 0x100428e0 0xd _L1w_DevHsdpaCalcRvB
+ 0x100428ed 0x3a _L1w_DevHsdpaCalcCodeBlockPara
+ 0x10042927 0x25 _L1w_DevHsdpaCalc1stRmPara
+ 0x1004294c 0x37 _L1w_DevHsdpaCalc2ndRmEini
+ 0x10042983 0xf9 _L1w_DevHsdpaCalcRmPara
+ 0x10042a7c 0x9f _L1w_DevHsdpaCalcVelcity
+ 0x10042b1b 0xd _L1w_DevHsdpaCalcSymPower
+ 0x10042b28 0x79 _L1w_DevHsdpaCalcFingerMaskStep1
+ 0x10042ba1 0xba _L1w_DevHsdpaCalcFingerMaskStep2
+ 0x10042c5b 0x45 _L1w_DevHsdpaCalcFingerMaskStep3
+ 0x10042ca0 0x5d _L1w_DevHsdpaCalcAntFingerMask
+ 0x10042cfd 0x11f _L1w_DevHsdpaFingerMaskBufUpdate
+ 0x10042e1c 0x8c _L1w_DevHsdpaCalcFingerMask
+ 0x10042ea8 0xb8 _L1w_DevHsdpaSnrLowRstJudge
+ 0x10042f60 0x1b0 _L1w_DevHsdpaCalcNoiseSinr
+ 0x10043110 0x47 _L1w_DevHsdpaCalcNoiseFactor
+ 0x10043157 0xc3 _L1w_DevHsdpaCalcCirPower
+ 0x1004321a 0xba _L1w_DevHsdpaCalcEqNoise
+ 0x100432d4 0x34 _L1w_DevHsdpaCalcNoise
+ 0x10043308 0x2d _L1w_DevHsdpaIsExceedFinWin
+ 0x10043335 0x6b _L1w_DevHsdpaPsrFingerFilter
+ 0x100433a0 0x56 _L1w_DevHsdpaCalcFrameHeadPos
+ 0x100433f6 0x87 _L1w_DevHsdpaCalcIntraCellSfnOffset
+ 0x1004347d 0xfc _L1w_DevHsdpaCalcFingerSort
+ 0x10043579 0x24 _L1w_DevHsdpaCalcJudgeResetFlg
+ 0x1004359d 0x27c _L1w_DevHsdpaCalcCellFingerSort
+ 0x10043819 0x1b _L1w_DevHsdpaCalcAntChe4xPos
+ 0x10043834 0xef _L1w_DevHsdpaCalcChe4xPos
+ 0x10043923 0xbf _L1w_DevHsdpaCalcAdrPsrInfo
+ .text 0x100439e2 0x3d4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o)
+ 0x100439e2 0x3f _L1w_DevDrvAllIntClear
+ 0x10043a21 0x54 _L1w_DevDrvRestoreAllInt
+ 0x10043a75 0x9e _L1W_TPU_RAKE_ISR
+ 0x10043b13 0x70 _L1W_RAKE_DFE_RFC_ISR
+ 0x10043b83 0xac _L1W_TPU_CSR_ADR_HSSCCH_ISR
+ 0x10043c2f 0x89 _L1W_CSR_DTR_PSR_ISR
+ 0x10043cb8 0x27 _L1w_DevCommGetTop19IntStatus
+ 0x10043cdf 0x26 _L1W_ICP_UPA_DATA_ISR
+ 0x10043d05 0x5c _L1W_ICP_SLEEP_WAKEUP_ISR
+ 0x10043d61 0x1c _L1W_EDCP_ISR
+ 0x10043d7d 0x39 _L1_W_LPM_T3_ISR
+ .text 0x10043db6 0x2265 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ 0x10043db6 0x8 _L1w_DevCsrSetStep1Clk
+ 0x10043dbe 0x8 _L1w_DevCsrGetStep1Clk
+ 0x10043dc6 0x6 _L1w_DevGetPeakThreshold
+ 0x10043dcc 0x1 _L1w_DevGetFsThreshold
+ 0x10043dcd 0x1e _L1w_DevCsrStep1Cmp
+ 0x10043deb 0xa _L1w_DevCsrF2W
+ 0x10043df5 0xf _L1w_DevCsrW2F
+ 0x10043e04 0x15 _L1w_DevCsrCompare
+ 0x10043e19 0x87 _L1w_DevCsrComputeWin
+ 0x10043ea0 0x2a _L1w_DevCsrInitReq
+ 0x10043eca 0x98 _L1w_DevCsrStep1Req
+ 0x10043f62 0x75 _L1w_DevCsrFsReq
+ 0x10043fd7 0x27 _L1w_DevCsrResetCnf
+ 0x10043ffe 0x27 _L1w_DevCsrInitCnf
+ 0x10044025 0x65 _L1w_DevCsrStep1Cnf
+ 0x1004408a 0x4f _L1w_DevCsrFsCnf
+ 0x100440d9 0x2d _L1w_DevCsrIntInd
+ 0x10044106 0x5d _L1w_DevCsrStep1CalConfigIndex4_1
+ 0x10044163 0x3d _L1w_DevCsrSaveDateMrtr
+ 0x100441a0 0x138 _L1w_DevCsrIcCfg
+ 0x100442d8 0xe _L1w_DevCsrSetFsAbort
+ 0x100442e6 0x1ac _L1w_DevCsrStep1Abort
+ 0x10044492 0x272 _L1w_DevCsrStep1Pro
+ 0x10044704 0xa _L1w_DevCsrClrFsSt
+ 0x1004470e 0x7d _L1w_DevCsrFsPro
+ 0x1004478b 0xbf _L1w_DevCsrPeakFilter
+ 0x1004484a 0xb8 _L1w_DevCsrPeakSearch
+ 0x10044902 0x95 _L1w_DevCsrFsReqCfg
+ 0x10044997 0x113 _L1w_DevCsrIcFilter
+ 0x10044aaa 0x1312 _L1w_DevCsrStep1Int
+ 0x10045dbc 0x125 _L1w_DevCsrFsInt
+ 0x10045ee1 0x1a _L1w_DevCsrStep1IsBusy
+ 0x10045efb 0x13 _L1w_DevCsrReset
+ 0x10045f0e 0x10 _L1w_DevCsrStFsSt
+ 0x10045f1e 0xfd _L1w_CsrTask
+ .text 0x1004601b 0x220d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ 0x1004601b 0x30 _L1w_DevPcWord64ToFloat
+ 0x1004604b 0x40 _L1w_DevPcFloatToWord
+ 0x1004608b 0x2e _L1w_PcLog2FindTable
+ 0x100460b9 0x80 _L1w_DevPcFloatSirAndBlerToWord32
+ 0x10046139 0x28 _L1w_DevPcDiv
+ 0x10046161 0x71 _L1w_DevPcLog10
+ 0x100461d2 0xe6 _L1w_DevPc10xPower10expOld
+ 0x100462b8 0x2c _L1w_DevPc10xPower10exp
+ 0x100462e4 0x65 _L1w_DevSirBlerPcDiv
+ 0x10046349 0x38 _L1w_DevPcFloatAdd
+ 0x10046381 0x3b _L1w_DevPcUlAlphaDiv
+ 0x100463bc 0x62 _L1w_DevPcPowerLimit
+ 0x1004641e 0x86 _L1w_DevPcSumBeltaIQmap
+ 0x100464a4 0x81 _L1w_DevPcCalcSquareBetaHs
+ 0x10046525 0x22 _L1w_DevPcP1P2LogCalc
+ 0x10046547 0x19 _L1w_DevPcP1P2Calc
+ 0x10046560 0xd _L1w_DevPcBetalRatioProc
+ 0x1004656d 0x9d _L1w_DevPcCodeRatioCalc
+ 0x1004660a 0x14 _L1w_DevPcGetTxpowerForMeas
+ 0x1004661e 0x99 _L1w_DevPcConfigTxReg
+ 0x100466b7 0x92 _L1w_DevPcTtiUpdDpaBeta
+ 0x10046749 0xe4 _L1w_DevPcTtiUpdEdchBeta
+ 0x1004682d 0x23 _L1w_DevPcNoDpdchPro
+ 0x10046850 0xb5 _L1w_DevPcTtiUpdDpchBeta
+ 0x10046905 0x35 _L1w_DevPcBetaEdAllSquareCalc
+ 0x1004693a 0xc _L1w_DevPcSumSquareCalc
+ 0x10046946 0x56 _L1w_DevPcSquareCalc
+ 0x1004699c 0x110 _L1w_DevPcIQMap
+ 0x10046aac 0x1b _L1w_DevPcRangeAdjust
+ 0x10046ac7 0x32 _L1w_DevPcCalcCm
+ 0x10046af9 0x146 _L1w_DevPcMprCalPro
+ 0x10046c3f 0x2f _L1w_DevPcMprAdjust
+ 0x10046c6e 0x39 _L1w_DevPcMprCalCtrl
+ 0x10046ca7 0x116 _L1w_DevPcCodeRatioAndTotalPowerCalc
+ 0x10046dbd 0x33 _L1w_DevPcPwrValadjust
+ 0x10046df0 0x94 _L1w_DevPcGainTorAdjust
+ 0x10046e84 0x89 _L1w_DevPcCalPvalue
+ 0x10046f0d 0x3f _L1w_DevPcGaintorHalf
+ 0x10046f4c 0x4b _L1w_DevPcMaxPwrSetProc
+ 0x10046f97 0x178 _L1w_DevPcTxAndRfSet
+ 0x1004710f 0x54 _L1w_DevPcTpuCallBack
+ 0x10047163 0x1d _L1w_DevPcRegFrmTpu
+ 0x10047180 0x88 _L1w_DevPcUlRegTpu
+ 0x10047208 0x1c _L1w_DevPcIsBeltaEdAllEquReduce
+ 0x10047224 0xff _L1w_DevPcSetLastBelta
+ 0x10047323 0x25 _L1w_DevPcPmaxReLimt
+ 0x10047348 0x7d _L1w_DevPcPmaxReCalc
+ 0x100473c5 0x2d _L1w_DevPcBeltaReCalcBeltaEdReducedMin
+ 0x100473f2 0x43 _L1w_DevPcBeltaReCalcEtfciBoost
+ 0x10047435 0x97 _L1w_DevPcBeltaReCalc
+ 0x100474cc 0x21 _L1w_DevPcMaxPowerLimit
+ 0x100474ed 0x14 _L1w_DevPcMinPowerLimit
+ 0x10047501 0xe0 _L1w_DevPcCMInfoUpdate
+ 0x100475e1 0x46 _L1w_DevPcFrmEventHandle
+ 0x10047627 0x51 _L1w_DevPcPreCalc
+ 0x10047678 0x63 _L1w_DevPcStopHandle
+ 0x100476db 0xdd _L1w_DevPc3SymbolIntHandle
+ 0x100477b8 0x4d _L1w_DevPcGaintorCalc
+ 0x10047805 0x46 _L1w_DevPcTpuTpcSlotHandle
+ 0x1004784b 0x1c _L1w_DevPcSlotModeGet
+ 0x10047867 0x15 _L1w_DevPcDlGapPatternJudge
+ 0x1004787c 0x9 _L1w_DevPcWriteCmBitMap
+ 0x10047885 0xa _L1w_DevPcIsUlCmFrm
+ 0x1004788f 0x15 _L1w_DevPcIsCmFrmOnlyGap
+ 0x100478a4 0x2d _L1w_DevPcIsCmFrm
+ 0x100478d1 0x7a _L1w_DevPcSlotModeSet
+ 0x1004794b 0x2d _L1w_DevPcUlCmInfoHandle
+ 0x10047978 0x24 _L1w_DevPcDlCmInfoHandle
+ 0x1004799c 0x48 _L1w_DevPcCmStopHandle
+ 0x100479e4 0x12 _L1w_DevPcCmStopReqHandle
+ 0x100479f6 0x32 _L1w_DevPcStopReqHandle
+ 0x10047a28 0x11c _L1w_DevPcWriteSubFrmIntInfo
+ 0x10047b44 0x74 _L1w_DevPcReset
+ 0x10047bb8 0xcb _L1w_DevPcInit
+ 0x10047c83 0x7b _L1w_DevPcOutSyncEng
+ 0x10047cfe 0xef _L1w_DevPcEngPrintf
+ 0x10047ded 0x63 _L1w_DevPcWriteDpramMsg
+ 0x10047e50 0x27 _L1w_DevPcResetCnf
+ 0x10047e77 0x27 _L1w_DevPcInitCnf
+ 0x10047e9e 0x2c _L1w_DevRtxPcPrachStartReq
+ 0x10047eca 0x28 _L1w_DevRtxPcPrachPreambleReq
+ 0x10047ef2 0x30 _L1w_DevRtxPcPrachMessageReq
+ 0x10047f22 0x39 _L1w_DevRtxPcDchStartReq
+ 0x10047f5b 0x2c _L1w_DevRtxPcUlDpchCmInfoReq
+ 0x10047f87 0x2c _L1w_DevRtxPcDlDpchCmInfoReq
+ 0x10047fb3 0x29 _L1w_DevRtxPcDpchCmStopReq
+ 0x10047fdc 0x2e _L1w_DevRtxPcBlerReq
+ 0x1004800a 0x2d _L1w_DevHsdpaPcStartReq
+ 0x10048037 0x28 _L1w_DevHsdpaPcTtiReq
+ 0x1004805f 0x21 _L1w_DevHsdpaPcStoptReq
+ 0x10048080 0x11 _L1w_DevDchPcSetPara
+ 0x10048091 0x2a _L1w_DevHsupaPcStartReq
+ 0x100480bb 0x2d _L1w_DevHsupaPcTtiReq
+ 0x100480e8 0x21 _L1w_DevHsupaPcStopReq
+ 0x10048109 0x11f _L1w_PcTask
+ .text 0x10048228 0x29a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ 0x10048228 0x1 _L1w_DevEngInitAddr
+ 0x10048229 0x19 _L1w_EngTaskInit
+ 0x10048242 0x7 _L1w_DevEngSetFlag
+ 0x10048249 0x12 _L1w_log_track_init
+ 0x1004825b 0x8e _L1w_DevEngDisplay
+ 0x100482e9 0x46 _L1w_EngTrace
+ 0x1004832f 0xaa _L1w_DevEngLogHeaderUpdate
+ 0x100483d9 0xc6 _L1w_DevEngWriteDataToBuffer
+ 0x1004849f 0x22 _L1w_DevEngCopyMem2Dpram
+ 0x100484c1 0x1 _L1w_DevEngUartTransmit
+ .text 0x100484c2 0xde T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o)
+ 0x100484c2 0x9 _L1w_DevTxFirstTpuIntSet
+ 0x100484cb 0xc _L1w_DevTxFirstTpuIntDelete
+ 0x100484d7 0x82 _L1w_DevRtxTxCfgMsgHandle
+ 0x10048559 0x16 _L1w_DevTxTpuIntHandle
+ 0x1004856f 0x15 _L1w_DevRtxTxReset
+ 0x10048584 0x1c _L1w_DevRtxTxInit
+ .text 0x100485a0 0x1cc0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ 0x100485a0 0x6b _L1w_DevRtxRxBlindAnalyse
+ 0x1004860b 0x77 _L1w_DevRtxRxTfcParaCalc
+ 0x10048682 0xd5 _L1w_DevRtxRxJudgeCsRam
+ 0x10048757 0x115 _L1w_DevRtxRxTrchParaCalc
+ 0x1004886c 0x33 _L1w_DevRtxRxDtrCtfcSort
+ 0x1004889f 0x81 _L1w_DevRtxRxSccpchDtrParam
+ 0x10048920 0x3b _L1w_DevRtxRxJudgeRrm
+ 0x1004895b 0x2f _L1w_DevRtxRxV3BlindTbs49Change
+ 0x1004898a 0x25 _L1w_DevRtxRxV3BlindTbsChange
+ 0x100489af 0xc4 _L1w_DevRtxRxV3BlindTfcPatch
+ 0x10048a73 0xd2 _L1w_DevRtxRxDpchDtrParam
+ 0x10048b45 0x11 _L1w_DevRtxRxTtiModeGet
+ 0x10048b56 0xe _L1w_DevRtxRxCrcModeGet
+ 0x10048b64 0x16 _L1w_DevRtxRxCodingGet
+ 0x10048b7a 0x89 _L1w_DevRtxRxTrchInfoCfg
+ 0x10048c03 0x51 _L1w_DevRtxRxDpchDtrCmCfg
+ 0x10048c54 0x74 _L1w_DevRtxRxDlDpchDtrCfg
+ 0x10048cc8 0x6d _L1w_DevRtxRxDlSccpchDtrCfg
+ 0x10048d35 0x36 _L1w_DevRtxRxAgchDtrCfg
+ 0x10048d6b 0x83 _L1w_DevRtxRxAgchCmDtrCfg
+ 0x10048dee 0x45 _L1w_DevRtxRxCfgABUpdate
+ 0x10048e33 0x34 _L1w_DevRtxRxDeilBaseSort
+ 0x10048e67 0x9f _L1w_DevRtxRxTfciS2Cfg
+ 0x10048f06 0xb1 _L1w_DevRtxRxTfcAnalyse
+ 0x10048fb7 0x58 _L1w_DevRtxRxBlindGuidCfg
+ 0x1004900f 0x37 _L1w_DevRtxRxPn9BerCheckStart
+ 0x10049046 0xa1 _L1w_DevRtxRxPn9Get244Bit
+ 0x100490e7 0x42 _L1w_DevRtxRxPn9BerRltReport
+ 0x10049129 0xc5 _L1w_DevRtxRxPn9DataCheck
+ 0x100491ee 0x81 _L1w_DevRtxRxAllBlindHandle
+ 0x1004926f 0xda _L1w_DevRtxRxBlindDtrCfg
+ 0x10049349 0x17a _L1w_DevRtxRxBlindCrcHandle
+ 0x100494c3 0xc3 _L1w_DevRtxRxBlindDataHandle
+ 0x10049586 0x21 _L1w_DevRtxRxBlindStateCheck
+ 0x100495a7 0xeb _L1w_DevRtxRxBlindTfcAnalyse
+ 0x10049692 0x3a _L1w_DevRtxRxTfcDataCmpHandle
+ 0x100496cc 0x38 _L1w_DevRtxRxTfciFWHT
+ 0x10049704 0x126 _L1w_DevRtxRxTfciCoding
+ 0x1004982a 0x1f1 _L1w_DevRtxRxTfciIntHandle
+ 0x10049a1b 0x18 _L1w_DevRtxRxGetGsmVal
+ 0x10049a33 0x76 _L1w_DevRtxRxCmpPchUeId
+ 0x10049aa9 0x55 _L1w_DevRtxRxPchUeIdHandle
+ 0x10049afe 0x114 _L1w_DevRtxRxTtiBlindHandle
+ 0x10049c12 0xab _L1w_DevRtxRxTrchCrcStatic
+ 0x10049cbd 0xbd _L1w_DevRtxRxTtiCrcStatic
+ 0x10049d7a 0xb _L1w_DevRtxRxTtiCrcStatForAfc
+ 0x10049d85 0x63 _L1w_DevRtxRxTtiTrchInfoHandle
+ 0x10049de8 0x8d _L1w_DevRtxRxTtiBdTrchInfoHandle
+ 0x10049e75 0x64 _L1w_DevRtxRxNoBdTtiHandle
+ 0x10049ed9 0x54 _L1w_DevRtxRxBlindTtiHandle
+ 0x10049f2d 0x49 _L1w_DevRtxRxPchTtiHandle
+ 0x10049f76 0x68 _L1w_DevRtxRxTtiIntAfterHandle
+ 0x10049fde 0x25e _L1w_DevRtxRxTtiIntHandle
+ 0x1004a23c 0x24 _L1w_DevRtxRxDtrRel
+ .text 0x1004a260 0x5db T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_cqi.o)
+ 0x1004a260 0x8b _L1w_DevHsdpaCqiCalcPos
+ 0x1004a2eb 0x1b1 _L1w_DevHsdpaCalcCqiSnr
+ 0x1004a49c 0x6b _L1w_DevHsdpaSnrLimitAdj
+ 0x1004a507 0xbf _L1w_DevHsdpaCqiSnrAdj
+ 0x1004a5c6 0x68 _L1w_DevHsdpaCalcSnrVal
+ 0x1004a62e 0x20d _L1w_DevHsdpaSnrMapToCqiVal
+ .text 0x1004a83b 0x2f5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_pcch.o)
+ 0x1004a83b 0x5b _L1w_DevRtxRxPcchBitRead
+ 0x1004a896 0x3e _L1w_DevRtxRxImsiGsm
+ 0x1004a8d4 0x2f _L1w_DevRtxRxTmsiGsm
+ 0x1004a903 0x2f _L1w_DevRtxRxPTmsiGsm
+ 0x1004a932 0xf _L1w_DevRtxRxImsiDs41
+ 0x1004a941 0xf _L1w_DevRtxRxTmsiDs41
+ 0x1004a950 0x3d _L1w_DevRtxRxPagRecCnId
+ 0x1004a98d 0x44 _L1w_DevRtxRxPagRecUtranId
+ 0x1004a9d1 0x4e _L1w_DevRtxRxPagRec2UtranSingUeId
+ 0x1004aa1f 0x28 _L1w_DevRtxRxPagRec2UtranGrpId
+ 0x1004aa47 0x28 _L1w_DevRtxRxPagingRecList
+ 0x1004aa6f 0x28 _L1w_DevRtxRxPagingRec2ListR5
+ 0x1004aa97 0x12 _L1w_DevRtxRxPagingV590ExtIE
+ 0x1004aaa9 0x10 _L1w_DevRtxRxPagingV860ExtIE
+ 0x1004aab9 0x47 _L1w_DevRtxRxPagingType1
+ 0x1004ab00 0x19 _L1w_DevRtxRxPcchMsgType
+ 0x1004ab19 0x17 _L1w_DevRtxRxDecodePcch
+ .text 0x1004ab30 0x18da T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ 0x1004ab30 0x22 _L1w_HspaCalcMod
+ 0x1004ab52 0xb _L1w_DevHsupaEdchReadyInit
+ 0x1004ab5d 0x11 _L1w_DevHsupaInitUlDataInfo
+ 0x1004ab6e 0x18 _L1w_DevHsupaUlReset
+ 0x1004ab86 0x5c _L1w_DevHsupaParaInit
+ 0x1004abe2 0x45 _L1w_DevHsupaInit
+ 0x1004ac27 0x15 _L1w_DevHsupaHwRel
+ 0x1004ac3c 0x8f _L1w_DevHsupaReset
+ 0x1004accb 0x5f _L1w_DevHsupaGetDlChanInfo
+ 0x1004ad2a 0x34 _L1w_DevHsupaCalcDisEagchEdch
+ 0x1004ad5e 0x10 _L1w_DevHsupaCalcDisEhichEdch
+ 0x1004ad6e 0x21 _L1w_DevHsupaCalcDisErgchEdch
+ 0x1004ad8f 0x1a _L1w_DevHsupaCalcInitNo
+ 0x1004ada9 0x3a _L1w_DevHsupaCalcInitSwNo
+ 0x1004ade3 0x64 _L1w_DevHsupaCalcIscpSlotId
+ 0x1004ae47 0x9a _L1w_DevHsupaCalcDlChanInitNo
+ 0x1004aee1 0x5e _L1w_DevHsupaConfigReq
+ 0x1004af3f 0x2b _L1w_DevHsupaCpEdpdchInfo
+ 0x1004af6a 0x3d _L1w_DevHsupaCpErntiInfo
+ 0x1004afa7 0x65 _L1w_DevHsupaCpRxEagchCfg
+ 0x1004b00c 0x42 _L1w_DevHsupaRtxEagchCfg
+ 0x1004b04e 0x8 _L1w_DevHsupaGetErgchFrameType
+ 0x1004b056 0x7e _L1w_DevHsupaCpRxRgHiCfg
+ 0x1004b0d4 0x77 _L1w_DevHsupaRtxRgHiCfg
+ 0x1004b14b 0x23 _L1w_DevHsupaRtxCfg
+ 0x1004b16e 0xca _L1w_DevHsupaCpDlRcvInfo
+ 0x1004b238 0x20 _L1w_DevHsupaCfgTxInit
+ 0x1004b258 0x22 _L1w_DevHsupaEagchInt2Ps
+ 0x1004b27a 0x97 _L1w_DevHsupaCalAgRgHiIntNo
+ 0x1004b311 0x4f _L1w_DevHsupaNorm2TpuBase
+ 0x1004b360 0x79 _L1w_DevHsupaFachNt2CfnTime
+ 0x1004b3d9 0x84 _L1w_DevHsupaSaveTpuTime
+ 0x1004b45d 0x2d _L1w_DevHsupaCalcSwTtiCntIntOff
+ 0x1004b48a 0x73 _L1w_DevHsupaGetCfnTime
+ 0x1004b4fd 0x25 _L1w_DevHsupaCalcSwTtiCntIntOn
+ 0x1004b522 0x114 _L1w_DevHsupaEagchIntProc
+ 0x1004b636 0x18 _L1w_DevHsupaEagchIntInd
+ 0x1004b64e 0x4c _L1w_DevHuspaSaveAG
+ 0x1004b69a 0x12 _L1w_DevHuspaUpaTransFlgToMac
+ 0x1004b6ac 0x1c _L1w_DevHuspaGrantHarqToMac
+ 0x1004b6c8 0xb9 _L1w_DevHsupaReportPsStatistic
+ 0x1004b781 0x65 _L1w_DevHsupaStdlogThroughput
+ 0x1004b7e6 0x82 _L1w_DevHsupaStdlogPacketInfo
+ 0x1004b868 0x40 _L1w_DevHsupaReportToMac
+ 0x1004b8a8 0x71 _L1w_DevHsupaRptHarqFlag
+ 0x1004b919 0x5b _L1w_DevHsupaDchIsMacTrans
+ 0x1004b974 0x14 _L1w_DevHsupaFachIsMacTrans
+ 0x1004b988 0x22 _L1w_DevHsupaIsMacTrans
+ 0x1004b9aa 0x37 _L1w_DevHsupaPcCfg
+ 0x1004b9e1 0x1 _L1w_DevHsupaAgRgHiIndCallBack
+ 0x1004b9e2 0x3a _L1w_DevHsupaAddTpu
+ 0x1004ba1c 0x9 _L1w_DevHsupaGetPhyMinSfMaxChan
+ 0x1004ba25 0x9e _L1w_DevHsupaDisplayCfgInfo
+ 0x1004bac3 0x6a _L1w_DevHsupaSaveStdlogPacket
+ 0x1004bb2d 0x35 _L1w_DevHsupaCfgToPsrInd
+ 0x1004bb62 0x125 _L1w_DevHsupaConfigProc
+ 0x1004bc87 0x2c _L1w_DevHsupaIcpIntInd
+ 0x1004bcb3 0x2c _L1w_DevHsupaEdcpIntInd
+ 0x1004bcdf 0x59 _L1w_DevHsupaIcpIntProc
+ 0x1004bd38 0xea _L1w_DevHsupaEdcpIntProc
+ 0x1004be22 0x26 _L1w_DevHsupaCfgPcTti
+ 0x1004be48 0x2c _L1w_DevHsupaEtxIntInd
+ 0x1004be74 0x2d _L1w_DevHsupaCalcNtx1Info
+ 0x1004bea1 0x23 _L1w_DevHsupaCmInfoClr
+ 0x1004bec4 0xf1 _L1w_DevHsupaEtxIntProc
+ 0x1004bfb5 0x21 _L1w_DevHsupaRelReq
+ 0x1004bfd6 0xf _L1w_DevHsupaRtxRelReq
+ 0x1004bfe5 0x4e _L1w_DevHsupaReleaseProc
+ 0x1004c033 0xc _L1w_DevHsupaIfHarqIdValid
+ 0x1004c03f 0x66 _L1w_DevHsupaTestCurFrameNum
+ 0x1004c0a5 0x37 _L1w_DevHsupaCalcEdchCfn
+ 0x1004c0dc 0x2a _L1w_DevHsupaGetCurFrameNum
+ 0x1004c106 0x2d _L1w_DevHsupaCalcNextTtiFrameNum
+ 0x1004c133 0x2b _L1w_DevHsupaCmPatternUpdateReq
+ 0x1004c15e 0x5c _L1w_DevHsupaCalcDlCm
+ 0x1004c1ba 0x69 _L1w_DevHsupaCmPatternUpdateProc
+ 0x1004c223 0x31 _L1w_DevHsupaCalChLen
+ 0x1004c254 0x7 _L1w_DevHsupaSetHsdschCfg
+ 0x1004c25b 0x77 _L1w_DevHsupaActive
+ 0x1004c2d2 0xf1 _L1w_DevHsupaTpuProc
+ 0x1004c3c3 0x3b _L1w_DevHsupaTransIndProc
+ 0x1004c3fe 0xc _L1w_DevHsupaIsDchActive
+ .text 0x1004c40a 0x18b3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
+ 0x1004c40a 0xb _L1w_DevRtxRxIntDataInit
+ 0x1004c415 0x13 _L1w_DevRtxRxIntReset
+ 0x1004c428 0x12 _L1w_DevRtxRxFix2Sword32
+ 0x1004c43a 0x13 _L1w_DevRtxRxFix2Sword16
+ 0x1004c44d 0x6e _L1w_DevRtxRxRcvFingerSlotwt
+ 0x1004c4bb 0x38 _L1w_DevRtxRxRcvFingerAfc
+ 0x1004c4f3 0x5b _L1w_DevRtxRxRcvFingerNoise
+ 0x1004c54e 0x27 _L1w_DevRtxRxCalcFingerIscp
+ 0x1004c575 0x9c _L1w_DevRtxRxRcvOffLInePiResult
+ 0x1004c611 0x88 _L1w_DevRtxRxRcvPiData
+ 0x1004c699 0xcc _L1w_DevRtxRxPichIntHandle
+ 0x1004c765 0x25 _L1w_DevRtxRxGetBuffIdx
+ 0x1004c78a 0xb2 _L1w_DevRtxRxRcvAiData
+ 0x1004c83c 0xdd _L1w_DevRtxRxCalcAiCpichPower
+ 0x1004c919 0x51 _L1w_DevRtxRxCalcAiCpichPrIIR
+ 0x1004c96a 0x10 _L1w_DevRtxRxGetAiDeltaPac
+ 0x1004c97a 0x31 _L1w_DevRtxRxCalcAiThreshold
+ 0x1004c9ab 0x24 _L1w_DevRtxRxCalcAiSignCorr
+ 0x1004c9cf 0x26 _L1w_DevRtxRxCalcAiVal
+ 0x1004c9f5 0x26 _L1w_DevRtxRxAiDataPreHandle
+ 0x1004ca1b 0x2e _L1w_DevRtxRxEAiResCfgMap
+ 0x1004ca49 0x4b _L1w_DevRtxRxNewCalcAiVal
+ 0x1004ca94 0x5e _L1w_DevRtxRxNewEAiCalc
+ 0x1004caf2 0x122 _L1w_DevRtxRxNewAichIntHandle
+ 0x1004cc14 0x2b _L1w_DevRtxRxCalcFbiFingerPr
+ 0x1004cc3f 0x34 _L1w_DevRtxRxCalcFbiRlPr
+ 0x1004cc73 0xed _L1w_DevRtxRxCalcFbiTotalPr
+ 0x1004cd60 0x23 _L1w_DevRtxRxCalcFbiValue
+ 0x1004cd83 0xc6 _L1w_DevRtxRxCalcFbi
+ 0x1004ce49 0x4a _L1w_DevRtxRxIntParaUpdate
+ 0x1004ce93 0x6 _L1w_DevRtxRxGetTpcIData
+ 0x1004ce99 0x5 _L1w_DevRtxRxGetTpcQData
+ 0x1004ce9e 0x6 _L1w_DevRtxRxGetTpcIExp
+ 0x1004cea4 0x5 _L1w_DevRtxRxGetTpcQExp
+ 0x1004cea9 0x58 _L1w_DevRtxRxDchTpcSirCalc
+ 0x1004cf01 0xcf _L1w_DevRtxRxDchTpcIntHandle
+ 0x1004cfd0 0x9 _L1w_DevRtxRxDchPilotIntHandle
+ 0x1004cfd9 0x6f _L1w_DevRtxRxFdpchTpcIntHandle
+ 0x1004d048 0x46 _L1w_DevRtxRxTpcIntHandle
+ 0x1004d08e 0x4c _L1w_DevRtxRxFactorCheck
+ 0x1004d0da 0x84 _L1w_DevRtxRxFactorDataGet
+ 0x1004d15e 0x44 _L1w_DevRtxRxFactorHandle
+ 0x1004d1a2 0x61 _L1w_DevRtxRxAgchFactorHandle
+ 0x1004d203 0x50 _L1w_DevRtxRxSccpchFactorCalc
+ 0x1004d253 0x13b _L1w_DevRtxRxPchFactorHandle
+ 0x1004d38e 0x109 _L1w_DevRtxRxFachFactorHandle
+ 0x1004d497 0x2f _L1w_DevRtxRxCalcIscp
+ 0x1004d4c6 0x1dd _L1w_DevRtxRxFingerDataHandle
+ 0x1004d6a3 0x8a _L1w_DevRtxRxNoiseDataCheck
+ 0x1004d72d 0x67 _L1w_DevRtxRxSetAfcInfo
+ 0x1004d794 0x119 _L1w_DevRtxRxCpich2ndFingerPrint
+ 0x1004d8ad 0xf3 _L1w_DevRtxRxCpichTpuIntPrint
+ 0x1004d9a0 0xea _L1w_DevRtxRxCpichTpuIntAllPrint
+ 0x1004da8a 0x5a _L1w_DevRtxRxCpichTpuIntIscpErrPrint
+ 0x1004dae4 0x45 _L1w_DevRtxRxCpichTpuIntUpaParaUpdate
+ 0x1004db29 0x167 _L1w_DevRtxRxCpichTpuIntHandle
+ 0x1004dc90 0x1 _L1w_DevRtxRxPilotIntHandle
+ 0x1004dc91 0x2c _L1w_DevRtxRxIntHandle
+ .text 0x1004dcbd 0x3556 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ 0x1004dcbd 0x5 _L1w_DevDlsPsrReset
+ 0x1004dcc2 0xb8 _L1w_DevDlsintialGlobalVariable
+ 0x1004dd7a 0x30 _L1w_DevDlsPsrIntialHardWare
+ 0x1004ddaa 0x8 _L1w_DevDlsPsrIntial
+ 0x1004ddb2 0xd _L1w_DevDlsSaveOldUlTiming
+ 0x1004ddbf 0x64 _L1w_DevDlsStop
+ 0x1004de23 0x3a _L1w_DevPsrIntEventProc
+ 0x1004de5d 0x35 _L1w_DevPsrSendTimingInfoToL1s
+ 0x1004de92 0x3d _L1w_DevPsrAddTpuFixedEvent
+ 0x1004decf 0x27 _L1w_DevPsrDchStopReq
+ 0x1004def6 0x39 _L1w_DevPsrMeasStartReq
+ 0x1004df2f 0x12d _L1w_DevPsrDchJudgeNcellSave
+ 0x1004e05c 0x177 _L1w_DevPsrSetRlNcellFlag
+ 0x1004e1d3 0x36 _L1w_DevPsrEfachStartReq
+ 0x1004e209 0x32 _L1w_DevPsrEfachFdpchOffsetReq
+ 0x1004e23b 0x22 _L1w_DevPsrEfachStopReq
+ 0x1004e25d 0x25 _L1w_DevPsrFmoStopReq
+ 0x1004e282 0x3b _L1w_DevDlsPsrHsdpaReq
+ 0x1004e2bd 0x32 _L1w_DevPsrDchUpaExistReq
+ 0x1004e2ef 0x6c _L1w_DevPsrEfachUlDpcchFBConfig
+ 0x1004e35b 0x54 _L1w_DevPsrUlDpcchFBConfig
+ 0x1004e3af 0x1 _L1w_DevPsrCommParaCfg
+ 0x1004e3b0 0x3c _L1w_DevPsrSaveCmInfo
+ 0x1004e3ec 0x21 _L1w_DevPsrTransDpchCm2Cpich
+ 0x1004e40d 0xa8 _L1w_DevPsrRtxFirstFingerConfigS
+ 0x1004e4b5 0x196 _L1w_DevPsrSelectMasterRl
+ 0x1004e64b 0x6c _L1w_DevPsrSaveLastTimingTrace
+ 0x1004e6b7 0x110 _L1w_DevPsrDchSelectUpaCell
+ 0x1004e7c7 0x160 _L1w_DevPsrDchConfigHardware
+ 0x1004e927 0xf8 _L1w_DevPsrDchReqConfig
+ 0x1004ea1f 0xfa _L1w_DevPsrHardWorkTimeConfig
+ 0x1004eb19 0x53 _L1w_DevPsrRlPosAndCodeConfig
+ 0x1004eb6c 0xc8 _L1w_DevPsrFachReqConfig
+ 0x1004ec34 0x29 _L1w_DevDlsCalcHandOverNtAdjPos
+ 0x1004ec5d 0x2f _L1w_DevDlsCalcAdjPos
+ 0x1004ec8c 0x1d9 _L1w_DevDlsCalcRegConfigTimingAndReport
+ 0x1004ee65 0x15a _L1w_DevDlsCalcRlTimingAndReport
+ 0x1004efbf 0x58 _L1w_DevDlsPsrUpdateULInfo
+ 0x1004f017 0x125 _L1w_DevDlsFachTimingMaintain
+ 0x1004f13c 0x1c _L1w_DevDlsTimingMaintain
+ 0x1004f158 0x34 _L1w_DevDlsDchJudgeAdustSpeed
+ 0x1004f18c 0x42 _L1w_DevDlsDchTimingMaintain
+ 0x1004f1ce 0x48 _L1w_DevDlsPsrSelectDpaId
+ 0x1004f216 0x63 _L1w_DevDlsPsrChangeDpaIdCell
+ 0x1004f279 0xc8 _L1w_DevDlsPsrGetAntNumAndJudgeConfig
+ 0x1004f341 0xa _L1w_DevDlsPsrClearCopyFingernfo
+ 0x1004f34b 0x3a _L1w_DevDlsPsrDpaIsChangjing1
+ 0x1004f385 0x11a _L1w_DevDlsPsrJudgeFingerOver512
+ 0x1004f49f 0x2df _L1w_DevDlsPsrWholeHandleS
+ 0x1004f77e 0x24 _L1w_DevPsrTpuIntHandle
+ 0x1004f7a2 0x4a _L1w_DevPsrRlCpichTimingAdujst
+ 0x1004f7ec 0x5b _L1w_DevPsrSoftHandOverTimingAdj
+ 0x1004f847 0x5a _L1w_DevPsrIsCmCfgBug
+ 0x1004f8a1 0x66 _L1w_DevPsrCmHandle
+ 0x1004f907 0x50 _L1w_DevPsrCalcRlsTxRxTimeDiff
+ 0x1004f957 0x9a _L1w_DevPsrTimingAdj
+ 0x1004f9f1 0x182 _L1w_DevPsrUpdateRlPos
+ 0x1004fb73 0x53 _L1w_DevPsrFmoHandle
+ 0x1004fbc6 0x170 _L1w_DevPsrRdPeakInfoS
+ 0x1004fd36 0xaf _L1w_DevDlsPsrSidelobeSurp
+ 0x1004fde5 0x10 _L1w_DevDlsPsrFingerSidelobeSurp
+ 0x1004fdf5 0xb2 _L1w_DevDlsPsrCorasePathDetect
+ 0x1004fea7 0x3d _L1w_DevDlsPsrFindStrongFiger
+ 0x1004fee4 0x46 _L1w_DevDlsPsrUpdateFigerTable
+ 0x1004ff2a 0x152 _L1w_DevDlsPsrStrongFigerPathDetect
+ 0x1005007c 0x149 _L1w_DevDlsPsrPathDect
+ 0x100501c5 0x3b _L1w_DevPsrRssiNormal
+ 0x10050200 0x99 _L1w_DevDlsPsrUpdateFingerPos
+ 0x10050299 0x12 _L1w_DevDlsPsrCalcMrtrDiff
+ 0x100502ab 0x23 _L1w_DevDlsPsrCalcMrtrAver
+ 0x100502ce 0x31 _L1w_DevDlsPsrSortMinRange
+ 0x100502ff 0x31 _L1w_DevDlsPsrSortMinRange1
+ 0x10050330 0x70 _L1w_DevDlsPsrSynProtect
+ 0x100503a0 0x24 _L1w_DevPsrBackWardProtect
+ 0x100503c4 0x26 _L1w_DevPsrForwardProtect
+ 0x100503ea 0x19b _L1w_DevDlsPsrFingerPeakUpdate
+ 0x10050585 0x18 _L1w_DevPsrSortMinValue
+ 0x1005059d 0x18 _L1w_DevDlsPsrSortMaxValue
+ 0x100505b5 0x14c _L1w_DevPsrCandidatefingerUpdate
+ 0x10050701 0xb3 _L1w_DevDlsPsrFingerPeakSelect
+ 0x100507b4 0x72 _L1w_DevDlsPsrCalcDpchTiming
+ 0x10050826 0x2f _L1w_DevPsrFinPeakNormal
+ 0x10050855 0x38 _L1w_DevPsrAntFinPeakNormal
+ 0x1005088d 0x3b _L1w_DevDlsPsrSelectValidFinger
+ 0x100508c8 0x98 _L1w_DevDlsPsrCalcDpchBaseTiming
+ 0x10050960 0x47 _L1w_DevDlsPsrSortRtxFinger
+ 0x100509a7 0xb _L1w_DevPsrGetDchStartPsrFlag
+ 0x100509b2 0x150 _L1w_DevDlsPsrSelectRtxFinger
+ 0x10050b02 0x93 _L1w_DevDlsPsrSelectNcellFinger
+ 0x10050b95 0xc8 _L1w_DevDlsPsrSortDpaFirst
+ 0x10050c5d 0xf6 _L1w_DevDlsPsrNewFingerMapping
+ 0x10050d53 0xd4 _L1w_DevDlsPsrAdrWindowUpdateS
+ 0x10050e27 0xc _L1w_DevDlsPsrSendAdrFingerInfoS
+ 0x10050e33 0xd0 _L1w_DevPsrSelSeaWindowFinInfoS
+ 0x10050f03 0x47 _L1w_DevPsrSelNewSearchWindowS
+ 0x10050f4a 0x21 _L1w_DevPsrIsSearchWindowPath
+ 0x10050f6b 0x28 _L1w_DevPsrCalcSearchWindowSum
+ 0x10050f93 0x15 _L1w_DevDlsPsrCalcFingerPeakSum
+ 0x10050fa8 0x38 _L1w_DevPsrSortFirstFinger
+ 0x10050fe0 0x23 _L1w_DevDlscalcPosOff
+ 0x10051003 0x1e3 _L1w_DevDlsChangedMasterRlTiming
+ 0x100511e6 0x13 _L1w_DevDlsPsrFingerCmp
+ 0x100511f9 0x12 _L1w_DevDlsPsrFingerLessThan
+ 0x1005120b 0x8 _TestZero
+ .text 0x10051213 0x5c1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_plus.o)
+ 0x10051213 0x8 _L1w_DevHsupaFachFdpchOffset
+ 0x1005121b 0xb _L1w_DevHsupaIsEfachActive
+ 0x10051226 0x35 _L1w_DevHsupaRtxEdchResInd
+ 0x1005125b 0x16 _L1w_DevHsupaFachToPsrInd
+ 0x10051271 0x52 _L1w_DevHsupaFachConfigReq
+ 0x100512c3 0x3c _L1w_DevHsupaFachCpErntiInfo
+ 0x100512ff 0xa5 _L1w_DevHsupaFachConfigProc
+ 0x100513a4 0x21 _L1w_DevHsupaFachRelReq
+ 0x100513c5 0x46 _L1w_DevHsupaFachRelProc
+ 0x1005140b 0x26 _L1w_DevHsupaErntiUpdateReq
+ 0x10051431 0x24 _L1w_DevHsupaErntiUpdateProc
+ 0x10051455 0x21 _L1w_DevHsupaFachNoDataReq
+ 0x10051476 0x7e _L1w_DevHsupaFachNoDataProc
+ 0x100514f4 0x96 _L1w_DevHsupaFachGetRgHiChanInfo
+ 0x1005158a 0x4a _L1w_DevHsupaFachCfn2NetTime
+ 0x100515d4 0x9b _L1w_DevHsupaFachAddTpu2ms
+ 0x1005166f 0x6b _L1w_DevHsupaFachAddTpu10ms
+ 0x100516da 0x22 _L1w_DevHsupaFachAddTpu
+ 0x100516fc 0xe _L1w_DevHsupaFachIsMacInitTrans
+ 0x1005170a 0x1d _L1w_DevHsupaFachAddTpuSubInt
+ 0x10051727 0x88 _L1w_DevHsupaFachEdchResProc
+ 0x100517af 0x25 _L1w_DevHsupaFachReset
+ .text 0x100517d4 0x1833 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x100517d4 0x21 _L1w_SetWmodeLpcMacroValue
+ 0x100517f5 0x8 _L1w_DevSleepSetCfunFlg
+ 0x100517fd 0x13 _L1w_PosCmp
+ 0x10051810 0x1c _L1w_DevLpcDvfs
+ 0x1005182c 0x2b _L1W_DevSleepLpmInspectInit
+ 0x10051857 0x87 _L1w_DevUeTurnOn3sNoLpc
+ 0x100518de 0xe _l1w_DevLpcSetAdjLpmFrmIntFlg
+ 0x100518ec 0xe _l1w_DevLpcGetAdjLpmFrmIntFlg
+ 0x100518fa 0xf _L1w_DevLpcSetSleepSubSt
+ 0x10051909 0x10 _L1w_DevLpcGetSleepFlg
+ 0x10051919 0x85 _L1w_DevLpcDpaRecover
+ 0x1005199e 0x1f _L1w_DevLpcDrxRecover
+ 0x100519bd 0x93 _L1w_DevLpcClkDevCtrl
+ 0x10051a50 0x3d _l1w_DevLpcClkInit
+ 0x10051a8d 0xa4 _L1w_DevLpcPwrDevCtrl
+ 0x10051b31 0x2d _l1w_DevLpcPwrInit
+ 0x10051b5e 0x7d _L1w_DevSleepNoLpc
+ 0x10051bdb 0xa2 _L1w_DevLpcLpmIntCheck
+ 0x10051c7d 0x124 _L1w_DevLpcSendIcp
+ 0x10051da1 0x10 _L1w_DevLpcGetWakeUpType
+ 0x10051db1 0x2f _L1w_LpcRegionJudge
+ 0x10051de0 0x4a _L1w_DevLpcSerIdleLen
+ 0x10051e2a 0x6 _L1w_LpcGetLpcDbAddress
+ 0x10051e30 0x23 _L1w_LpcCalcLen
+ 0x10051e53 0x46 _L1w_LpcPosMove
+ 0x10051e99 0xb5 _L1w_DevLpcCalPreSyncInfo
+ 0x10051f4e 0x43 _L1w_DevLpcIsPiPchOffsetLen
+ 0x10051f91 0x1ac _L1w_SchedGapGetSleepEnLen
+ 0x1005213d 0x77 _L1w_DevLpcCalSleepInfo
+ 0x100521b4 0x7b _L1W_DevLpcGetWSleepLen
+ 0x1005222f 0x92 _L1w_DevLpcUpdateWakeFlg
+ 0x100522c1 0x14e _L1w_DevLpcSyncWkUpOpenRf
+ 0x1005240f 0xa _L1w_DevSleepGetPiEndPos
+ 0x10052419 0x7d _L1W_LPNoSleepAPeriod
+ 0x10052496 0x8f _L1W_DevLpcPwrPrintInfo
+ 0x10052525 0x18 _L1w_DevSleepCloseIsAbleSleep
+ 0x1005253d 0x2a9 _L1W_DevSleepLpmInspect
+ 0x100527e6 0x4f _L1w_DevLpcWakeTimeCheck
+ 0x10052835 0x9 _L1W_LPNoSleepEndSsfnInit
+ 0x1005283e 0x5e _L1W_LPDataInit
+ 0x1005289c 0x71 _L1W_LPInit
+ 0x1005290d 0x37 _L1W_LpcCfgSocWkupInt
+ 0x10052944 0x1b _L1W_LpcDisSocWkupInt
+ 0x1005295f 0x16 _L1W_WakeupIsr
+ 0x10052975 0x8 _L1W_GetNtSsfn
+ 0x1005297d 0x4 _L1w_DevSleepPreSyncPiOffset
+ 0x10052981 0xd _L1W_DevSleepQueryAllowbit
+ 0x1005298e 0x335 _L1W_ModemLpcSleep
+ 0x10052cc3 0x344 _L1W_ModemLpcWakeup
+ .text 0x10053007 0x1519 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ 0x10053007 0x39 _L1w_DevDlsAfcReset
+ 0x10053040 0x19 _L1w_DevDlsAfcInit
+ 0x10053059 0x56 _L1w_DevAfcBchCorrCalEachSlot
+ 0x100530af 0x23 _L1w_DevAfcNormalToAfc
+ 0x100530d2 0x20 _L1w_DevAfcToNormal
+ 0x100530f2 0xf _L1w_DevAfcFormatCheck
+ 0x10053101 0x6 _L1w_DevAfcSubFunc1ForAdd
+ 0x10053107 0x27 _L1w_DevAfcSubFunc2ForAdd
+ 0x1005312e 0x75 _L1w_DevAfcAdd
+ 0x100531a3 0x60 _L1w_DevAfcDiv
+ 0x10053203 0x24 _L1w_DevAfcMultip
+ 0x10053227 0xf _L1w_DevAfcCompABS
+ 0x10053236 0xfe _L1w_DevAfcCalcPhaseErr
+ 0x10053334 0x36 _L1w_DevAfcCalcFreqcenErr
+ 0x1005336a 0x1c _L1w_DevAfcLockCheck
+ 0x10053386 0xa6 _L1w_DevAfcBchFoePostProc
+ 0x1005342c 0x44 _L1w_DevDlsAfcResultValid
+ 0x10053470 0x31 _L1w_DevAfcFoeAdjResultLim
+ 0x100534a1 0x42 _L1w_DevAfcFoeResultLimit
+ 0x100534e3 0x1c _L1w_DevAfcIQFilterProc
+ 0x100534ff 0x72 _L1w_DevAfcForBchProc
+ 0x10053571 0x26 _L1w_DevAfcStateTransfer
+ 0x10053597 0x64 _L1w_DevAfcRxFoePostProc
+ 0x100535fb 0x13 _L1w_DevAfcCalcFingerPower
+ 0x1005360e 0xab _L1w_DevAfcFingerFoeAdp
+ 0x100536b9 0x7b _L1w_DevAfcFingerSortByPeak
+ 0x10053734 0x27b _L1w_DevAfcForRxProc
+ 0x100539af 0x27 _L1w_DevAfcSendFreqMsgToL1s
+ 0x100539d6 0x29 _L1w_DevAfcBchReq
+ 0x100539ff 0x2c _L1w_DevAfcRxReq
+ 0x10053a2b 0x26 _L1w_DevAfcRxCrcFlagReq
+ 0x10053a51 0x28 _L1w_DevAfcStateChangeReq
+ 0x10053a79 0x97 _L1w_DevAfcRxDataAccu
+ 0x10053b10 0xa _L1w_DevAfcVcoTimeSet
+ 0x10053b1a 0xb5 _L1w_DevAfcCalcParam
+ 0x10053bcf 0xd _L1w_DevAfcIsInStableSt
+ 0x10053bdc 0x11 _L1w_DevAfcRxCrcFlagProc
+ 0x10053bed 0x37 _L1w_DevAfcLockHandle
+ 0x10053c24 0x4d _L1w_DevAfcNeedAdj
+ 0x10053c71 0x72 _L1w_DevAfcSaveStableVco
+ 0x10053ce3 0x21 _L1w_DevAfcMasteStChange
+ 0x10053d04 0x11 _L1w_DevAfcGetRxCrc
+ 0x10053d15 0x31 _L1w_DevAfcGetAfcCellEcIo
+ 0x10053d46 0x43 _L1w_DevAfcRxDataReqProc
+ 0x10053d89 0x52 _L1w_DevAfcGetNCellAfcPt
+ 0x10053ddb 0xa _L1w_DevAfcGetSystemAfc
+ 0x10053de5 0xb _L1w_DevAfcGetNCellAbsAfc
+ 0x10053df0 0x1b _L1w_DevAfcGetNCellRelativeAfc
+ 0x10053e0b 0x58 _L1w_DevAfcUpdateNCellAfc
+ 0x10053e63 0x8 _L1w_DevAfcSetWorkCellInfo
+ 0x10053e6b 0xa _L1w_DevAfcGetWorkCellInfo
+ 0x10053e75 0x50 _L1w_DevAfcIsSystemAfc
+ 0x10053ec5 0xa2 _L1w_DevAfcNcellAfcPostProc
+ 0x10053f67 0x3 _L1w_DevAfcSetNCellAbsAfc
+ 0x10053f6a 0xa5 _L1w_DevAfcRlsAloneProc
+ 0x1005400f 0x131 _L1w_DevAfcCalcRlOwnFoe
+ 0x10054140 0xf _L1w_DevAfcClearNcellAfc
+ 0x1005414f 0x1e _L1w_DevAfcCalcFilterPara
+ 0x1005416d 0x66 _L1w_DevAfcDpaIqRotateProc
+ 0x100541d3 0x1d _L1w_DevAfcNcellAdjLimit
+ 0x100541f0 0xc _L1w_DevAfcNormDiffValue
+ 0x100541fc 0x11 _L1w_DevAfcSaveDpaInfo
+ 0x1005420d 0x38 _L1w_DevAfcSetDpaIqRotate
+ 0x10054245 0x4f _L1w_DevAfcCalcSlotWeight
+ 0x10054294 0x15 _L1w_DevAfcInitNcellData
+ 0x100542a9 0x2e _L1w_DevAfcNcellUpByEcIo
+ 0x100542d7 0x1f _L1w_DevAfcRestartReq
+ 0x100542f6 0x22 _L1w_DevAfcRestartLockCheck
+ 0x10054318 0x29 _L1w_DevAfcWriteBackVco
+ 0x10054341 0x4f _L1w_DevAfcSaveWMode
+ 0x10054390 0xa7 _L1w_DevAfcSlaveAfcMangement
+ 0x10054437 0x15 _L1w_DevAfcLimitSlaveVco
+ 0x1005444c 0x15 _L1w_CleanSlaveAfcIRAMBuf
+ 0x10054461 0x32 _L1w_WriteMasterAfcInfo
+ 0x10054493 0x20 _L1w_ReadMasterAfcInfo
+ 0x100544b3 0x6d _L1w_DevChangeAndUpdateAfc
+ .text 0x10054520 0xf2e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ 0x10054520 0x129 _L1w_DevTpuRt1SampleCompst
+ 0x10054649 0x77 _L1w_DevTpuReset
+ 0x100546c0 0x10 _L1w_DevTpuTaskIdTransForm
+ 0x100546d0 0x5e _L1w_DevTpuAddFixedEvent
+ 0x1005472e 0x1a _L1w_DevTpuAddFixedCycleEvent
+ 0x10054748 0x15 _L1w_DevTpuDelFixedCycleEvent
+ 0x1005475d 0x21 _L1w_DevTpuUpdateVarNtEvent
+ 0x1005477e 0x20 _L1w_DevTpuUpdateVarRtEvent
+ 0x1005479e 0xfd _L1w_DevTpuAddVarNtEvent
+ 0x1005489b 0xdf _L1w_DevTpuAddVarRtEvent
+ 0x1005497a 0x46 _L1w_DevTpuDelFixedEvent
+ 0x100549c0 0x62 _L1w_DevTpuDelVarNtEvent
+ 0x10054a22 0x3e _L1w_DevTpuDelVarRtEvent
+ 0x10054a60 0x65 _L1w_DevTpuGetRealTime
+ 0x10054ac5 0x8e _L1w_DevTpuGetRtForWakeUp
+ 0x10054b53 0x50 _L1w_DevTpuGetNetTime
+ 0x10054ba3 0xa4 _L1w_DevTpuGetAllTime
+ 0x10054c47 0x80 _L1w_DevTpuNtFixedEventProc
+ 0x10054cc7 0xdd _L1w_DevTpuNtVarEventProc
+ 0x10054da4 0xf6 _L1w_DevTpuRtEventProc
+ 0x10054e9a 0x59 _L1w_DevTpuMacroAdjust
+ 0x10054ef3 0x56 _L1w_DevTpuMicroAdjust
+ 0x10054f49 0x1a _L1w_DevTpuMicroAdjustForSleep
+ 0x10054f63 0x56 _L1w_DevTpuMicroAdjSetPreSyncFlag
+ 0x10054fb9 0x5 _L1w_DevTpuAdjEventProc
+ 0x10054fbe 0xb _L1w_DevTpuSetDoff
+ 0x10054fc9 0x7 _L1w_DevTpuGetDoff
+ 0x10054fd0 0xa _L1w_DevTpuSfn2Cfn
+ 0x10054fda 0x25 _L1w_DevTpuCfn2Sfn
+ 0x10054fff 0x1b _L1w_DevTpuGetNtSSFN
+ 0x1005501a 0x1c _L1w_DevTpuGetRtSSFN
+ 0x10055036 0x17 _L1w_DevTpuGetSSFN
+ 0x1005504d 0xe _L1w_DevTpuGetCurCFN
+ 0x1005505b 0x7 _L1w_DevTpuSfn2Ssfn
+ 0x10055062 0x7 _L1w_DevTpuCfn2Ssfn
+ 0x10055069 0x27 _L1w_DevTpuRt2Nt
+ 0x10055090 0x69 _L1w_DevTpuAddCnt
+ 0x100550f9 0x34 _L1w_DevTpuCalNt2RtOffset
+ 0x1005512d 0x2c _L1w_DevTpuMicroSsfnJumpPatch
+ 0x10055159 0x7a _L1w_DevTpuCheckMicroSsfnJump
+ 0x100551d3 0x21 _L1w_DevTpuMicroSsfnJumpPro
+ 0x100551f4 0x77 _L1w_DevTpuCheckMicroSsfnBack
+ 0x1005526b 0x1f _L1w_DevTpuMicroSsfnBackPro
+ 0x1005528a 0x32 _L1w_DevTpuNtSSfnCfnUpdate
+ 0x100552bc 0x14 _L1w_DevTpuRtSSfnUpdate
+ 0x100552d0 0x32 _L1w_DevTpuCalcNtUpdateTime
+ 0x10055302 0x31 _L1w_DevTpuCalcRtUpdateTime
+ 0x10055333 0x1e _L1w_DevTpuBase2Norm
+ 0x10055351 0x43 _L1w_DevTpuNorm2Base
+ 0x10055394 0x17 _L1w_DevTpuCalRt2NtOffset
+ 0x100553ab 0x27 _L1w_DevTpuNt2Rt
+ 0x100553d2 0x7c _L1w_DevTpuSubCnt
+ .text 0x1005544e 0x9a4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ 0x1005544e 0x6 _L1w_DevDbAfcAddrGet
+ 0x10055454 0x6 _L1w_DevDbIscpAddrGet
+ 0x1005545a 0x6f _L1w_DevDbRtxUpaRlIscpReport
+ 0x100554c9 0xa _L1w_DevDbRtxPcRlIscpReport
+ 0x100554d3 0x7 _L1w_DevDbSetHsdpaInd
+ 0x100554da 0xb _L1w_DevDbReSetHsdpaInd
+ 0x100554e5 0x3d _L1w_DevDbUpdateHsdpaInd
+ 0x10055522 0x6 _L1w_DevDbGetHsdpaInd
+ 0x10055528 0x26 _L1w_DevDbRtxRxSirSet
+ 0x1005554e 0x26 _L1w_DevDbRtxRxSirGet
+ 0x10055574 0x2d _L1w_DevDbBchWriteAfcData
+ 0x100555a1 0x34 _L1w_DevAfcReadDataFromBch
+ 0x100555d5 0x3a9 _L1w_DevDlsAfcReadDataFromRx
+ 0x1005597e 0x43 _L1w_DevDbGetInitXValue
+ 0x100559c1 0x42 _L1w_DevDbGetInitYValue
+ 0x10055a03 0x1e _L1w_DevDbGetInitValue
+ 0x10055a21 0x45 _L1w_DevDbCodingPara
+ 0x10055a66 0x43 _L1w_DevDbTrchTtiMap
+ 0x10055aa9 0x28 _L1w_DevDbTrchMaxMinTti
+ 0x10055ad1 0x7 _L1w_DevDbTrchMaxTtiGet
+ 0x10055ad8 0x8 _L1w_DevDbTrchMinTtiGet
+ 0x10055ae0 0x6 _L1w_DevDbGetPichCfg
+ 0x10055ae6 0x6 _L1w_DevDbGetPchCfg
+ 0x10055aec 0x6 _L1w_DevDbGetFachCfg
+ 0x10055af2 0x6 _L1w_DevDbGetDldpchCfg
+ 0x10055af8 0x6 _L1w_DevDbGetFdpchCfg
+ 0x10055afe 0x32 _L1w_DevDbGetSchCodeGrp
+ 0x10055b30 0x3a _L1w_DevDbSaveCirData
+ 0x10055b6a 0xb _L1w_DevDbClearCirData
+ 0x10055b75 0x6 _L1w_DevDbGetCirDataAddr
+ 0x10055b7b 0x6 _L1w_DevDbGetFingerMaskBufAddr
+ 0x10055b81 0x1b _L1w_DevDbRtxReportToMac
+ 0x10055b9c 0x21 _L1w_DevDbHspaReportToMac
+ 0x10055bbd 0x1d _L1w_DevDbSetHsdpaToMacInfo
+ 0x10055bda 0x21 _L1w_DevDbSetHsupaToMacInfo
+ 0x10055bfb 0xb _L1w_DevDbClrHspaToMacInfo
+ 0x10055c06 0x1 _L1w_DevDbPcReportToMac
+ 0x10055c07 0x9 _L1w_SchedResIsBand8Freq
+ 0x10055c10 0x15 _L1w_DevDbGetAiSignSeries
+ 0x10055c25 0x27 _L1w_DevDbPiValHandle
+ 0x10055c4c 0x26 _L1w_DevDbCalcPiVal
+ 0x10055c72 0x1c _L1w_DevRtxRxPiAiFloatAdd
+ 0x10055c8e 0x6 _L1w_DevDbGetHspaPlusFachPsCmd
+ 0x10055c94 0x12 _L1w_DevDbPsSubFrmInt
+ 0x10055ca6 0x24 _L1w_DevDbSubFrmInt
+ 0x10055cca 0xe _L1w_DevDbSetHarqFlag
+ 0x10055cd8 0xc _L1w_DevDbInitHsdpaAntSwitchInfo
+ 0x10055ce4 0x7 _L1w_DevDbSetHsdpaAntSwitchFlg
+ 0x10055ceb 0x7 _L1w_DevDbGetHsdpaAntSwitchFlg
+ 0x10055cf2 0x8 _L1w_DevDbSetHsdpaAntNum
+ 0x10055cfa 0x8 _L1w_DevDbGetHsdpaAntNum
+ 0x10055d02 0x1a _L1w_DevDbHsdpaJudge2Rto1R
+ 0x10055d1c 0x1c _L1w_DevDbHsdpaJudge1Rto2R
+ 0x10055d38 0x9 _L1w_DevDbAddHsscchCnt
+ 0x10055d41 0x17 _L1w_DevDbHsscchSchedCnt
+ 0x10055d58 0x9 _L1w_DevDbAddHsscchCorrectCnt
+ 0x10055d61 0xa _L1w_DevDbAddHsscchErrorCnt
+ 0x10055d6b 0x9 _L1w_DevDbClearHsscchErrorCnt
+ 0x10055d74 0xa _L1w_DevDbAddSnrHighCnt
+ 0x10055d7e 0x9 _L1w_DevDbClearSnrHighCnt
+ 0x10055d87 0xa _L1w_DevDbAddSnrLowCnt
+ 0x10055d91 0x9 _L1w_DevDbClearSnrLowCnt
+ 0x10055d9a 0xd _L1w_DevDbSet1R2RState
+ 0x10055da7 0xc _L1w_DevDbSetLas1R2RState
+ 0x10055db3 0x11 _L1w_DevDbIs1RTo2R
+ 0x10055dc4 0x7 _L1w_DevDbGet1R2RState
+ 0x10055dcb 0xb _L1w_DevDbGet1R2RAntNum
+ 0x10055dd6 0x7 _L1w_DevSetSystemAntNum
+ 0x10055ddd 0x7 _L1w_DevGetSystemAntNum
+ 0x10055de4 0x7 _L1w_DevDbSetTxPower
+ 0x10055deb 0x7 _L1w_DevDbGetTxPower
+ .text 0x10055df2 0x1833 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ 0x10055df2 0xf _L1w_DevRtxRxInit
+ 0x10055e01 0x29 _L1w_DevRtxRxReset
+ 0x10055e2a 0x87 _L1w_DevRtxRxAddTpuEvent
+ 0x10055eb1 0x36 _L1w_DevRtxRxDelTpuEvent
+ 0x10055ee7 0x1c _L1w_DevRtxRxDelFactorTpuInt
+ 0x10055f03 0x80 _L1w_DevRtxRxSwapFinger
+ 0x10055f83 0x10f _L1w_DevRtxRxFingerSort
+ 0x10056092 0x72 _L1w_DevRtxRxFingerSelect
+ 0x10056104 0x75 _L1w_DevRtxRxFingerMsgHandle
+ 0x10056179 0x27 _L1w_DevRtxOfflinePichRelHanlde
+ 0x100561a0 0x38 _L1w_DevRtxSetPchCfgState
+ 0x100561d8 0x65 _L1w_DevRtxRxPchCfgReqHandle
+ 0x1005623d 0x5f _L1w_DevRtxRxCompareConfigTime
+ 0x1005629c 0x1a1 _L1w_DevRtxRxOffLinePichCfg
+ 0x1005643d 0xcd _L1w_DevRtxRxPichCfgMsgHandle
+ 0x1005650a 0x3e _L1w_DevRtxRxPichRelMsgHandle
+ 0x10056548 0x187 _L1w_DevRtxRxPchCfgMsgHandle
+ 0x100566cf 0x26 _L1w_DevRtxRxPchRelMsgHandle
+ 0x100566f5 0x157 _L1w_DevRtxRxAichCfgMsgHandle
+ 0x1005684c 0x38 _L1w_DevRtxRxAichRelMsgHandle
+ 0x10056884 0x123 _L1w_DevRtxRxFachCfgMsgHandle
+ 0x100569a7 0x38 _L1w_DevRtxRxFachRelMsgHandle
+ 0x100569df 0x219 _L1w_DevRtxRxDlDpchCfgMsgHandle
+ 0x10056bf8 0x36 _L1w_DevRtxRxDlDpchRelMsgHandle
+ 0x10056c2e 0x119 _L1w_DevRtxRxFdpchCfgMsgHandle
+ 0x10056d47 0x87 _L1w_DevRtxRxPlusCpCfgMsgHandle
+ 0x10056dce 0x38 _L1w_DevRtxRxFdpchRelMsgHandle
+ 0x10056e06 0x3 _L1w_DevRtxRxPlusFachTpuHandle
+ 0x10056e09 0x1cc _L1w_DevRtxRxPlusFachCfg
+ 0x10056fd5 0x15b _L1w_DevRtxRxCmCfgMsgHandle
+ 0x10057130 0x26 _L1w_DevRtxRxCmAbortMsgHandle
+ 0x10057156 0x5a _L1w_DevRtxRxHsscchCfgMsgHandle
+ 0x100571b0 0x51 _L1w_DevRtxRxEagchCfgMsgHandle
+ 0x10057201 0x9 _L1w_DevRtxRxEagchRelMsgHandle
+ 0x1005720a 0x63 _L1w_DevRtxRxRgHiCfgMsgHandle
+ 0x1005726d 0x9 _L1w_DevRtxRxRgHiRelMsgHandle
+ 0x10057276 0x45 _L1w_DevRtxRxDrxMsgHandle
+ 0x100572bb 0x12e _L1w_DevRtxRxMsgHandle
+ 0x100573e9 0x6 _L1w_DevRtxRxTrchInfoGet
+ 0x100573ef 0x16 _L1w_DevRtxRxTurboUse
+ 0x10057405 0xed _L1w_DevRtxRxDlStatEng
+ 0x100574f2 0x6 _L1w_DevRtxRxDpchPhyInfoGet
+ 0x100574f8 0x6 _L1w_DevRtxRxIntCfgParaGet
+ 0x100574fe 0xf _L1w_DevRtxRxDrxSlotCheck
+ 0x1005750d 0x28 _L1w_DevRtxRxCmSlotCheck
+ 0x10057535 0x8c _L1w_DevRtxRxCpCmSlotCheck
+ 0x100575c1 0x19 _L1w_DevRtxRxGetSlotId
+ 0x100575da 0xa _L1w_DevRtxRxDrxSlotClr
+ 0x100575e4 0x6 _L1w_DevRtxRxTpcInfoGet
+ 0x100575ea 0x6 _L1w_DevRtxRxSccpchPhyInfoGet
+ 0x100575f0 0x6 _L1w_DevRtxRxAgchPhyInfoGet
+ 0x100575f6 0x6 _L1w_DevRtxRxCfgInfoGet
+ 0x100575fc 0xd _L1w_DevRtxRxCfgRlCntGet
+ 0x10057609 0x1c _L1w_DevRtxRxRlPrimSrcGet
+ .text 0x10057625 0x516 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_ds.o)
+ 0x10057625 0xd _L1w_DevRtxRxDsReset
+ 0x10057632 0x25 _L1w_DevRtxDsMsgHandle
+ 0x10057657 0x72 _L1w_DevRtxDsStageHandle
+ 0x100576c9 0x84 _L1w_DevRtxDsStart
+ 0x1005774d 0x9 _L1w_DevRtxDsStop
+ 0x10057756 0x3d _L1w_DevRtxDsCrcCalc
+ 0x10057793 0x62 _L1w_DevRtxDsStep1Handle
+ 0x100577f5 0x7c _L1w_DevRtxDsQosStep1
+ 0x10057871 0x41 _L1w_DevRtxDsStep2Handle
+ 0x100578b2 0xcc _L1w_DevRtxDsQosStep2
+ 0x1005797e 0x2a _L1w_DevRtxRxDsPostInd
+ 0x100579a8 0x3d _L1w_DevRtxDsInsyncInd
+ 0x100579e5 0x41 _L1w_DevRtxDsOutsyncInd
+ 0x10057a26 0x19 _L1w_DevRtxRxDsIsCrcExist
+ 0x10057a3f 0x1f _L1w_DevRtxRxDsIsCrcOk
+ 0x10057a5e 0x16 _L1w_DevRtxRxDsCurTtiParaClr
+ 0x10057a74 0x16 _L1w_DevRtxRxDsLast20CrcFalse
+ 0x10057a8a 0xb _L1w_DevRtxRxDsIsPostOk
+ 0x10057a95 0x14 _L1w_DevRtxRxDsIsN312Ok
+ 0x10057aa9 0x31 _L1w_DevRtxRxDsSetTpcData
+ 0x10057ada 0x1d _L1w_DevRtxRxDsGetSyncSt
+ 0x10057af7 0x44 _L1w_DevRtxRxDsUlSendState
+ .text 0x10057b3b 0x37c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ 0x10057b3b 0xe _L1w_DrvRfcSingedDataMaxLimit
+ 0x10057b49 0xc _L1w_DrvRfcUnSingedDataMaxLimit
+ 0x10057b55 0x26 _L1w_DrvRfcS16ToFastFloat
+ 0x10057b7b 0x3e _L1w_DrvRfcS16FastFloatDiv
+ 0x10057bb9 0xd _L1w_DrvRfcFastFloatToS16
+ 0x10057bc6 0x3e _L1w_DrvRfcAgcgain2ManExp
+ 0x10057c04 0x71 _L1w_DrvRfcDcCalcSingleCh
+ 0x10057c75 0x29 _L1w_DrvRfcDcCalc
+ 0x10057c9e 0x37 _L1w_DrvRfcDcSet
+ 0x10057cd5 0x1c _L1w_DevRfcDcEstEn
+ 0x10057cf1 0xac _L1w_DrvRfcIQCalcSingleCh
+ 0x10057d9d 0x2e _L1w_DrvRfcIQSet
+ 0x10057dcb 0x11 _L1w_DrvRfcIQCalc
+ 0x10057ddc 0x4f _L1w_DrvRfcDagcCalc
+ 0x10057e2b 0x8c _L1w_DrvRfcDagcSet
+ .text 0x10057eb7 0x421 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o)
+ 0x10057eb7 0xa _L1w_DrvPIAIClkGateEnable
+ 0x10057ec1 0xa _L1w_DrvPIAIClkGateDisable
+ 0x10057ecb 0x10 _L1w_DrvPIAISttdCfg
+ 0x10057edb 0xc _L1w_DrvAiOnLineEn
+ 0x10057ee7 0xa _L1w_DrvAIonLineDisable
+ 0x10057ef1 0xc _L1w_DrvPIAfcoffLineEnable
+ 0x10057efd 0x12 _L1w_DrvPIAfcoffLineDisable
+ 0x10057f0f 0xf _L1w_DrvPiAfcIntModeCfg
+ 0x10057f1e 0xe _L1w_DrvGetPiAiEnPara
+ 0x10057f2c 0x9 _L1w_DrvGetPiAiIntMode
+ 0x10057f35 0xe _L1w_DrvGetConfigState
+ 0x10057f43 0xf _L1w_DrvPiAIFirOrderCfg
+ 0x10057f52 0x21 _L1w_DrvPiSysmbolLenCfg
+ 0x10057f73 0x9 _L1w_DrvAlphaCfg
+ 0x10057f7c 0xa _L1w_DrvAfcCompensateEnable
+ 0x10057f86 0xa _L1w_DrvAfcCompensateDisable
+ 0x10057f90 0x14 _L1w_DrvAfcRotateParaCfg
+ 0x10057fa4 0xd _L1w_DrvPiAiFingerParaCfg
+ 0x10057fb1 0x16 _L1w_DrvPiOffsetCfg
+ 0x10057fc7 0x23 _L1w_DrvPiAiOvsfCfg
+ 0x10057fea 0xf _L1w_DrvAfcBestFingerIndexCfg
+ 0x10057ff9 0x16 _L1w_DrvAiSeqIndexCfg
+ 0x1005800f 0xa _L1w_DrvPiAiCfgOver
+ 0x10058019 0x15 _L1w_DrvReadCpichPower
+ 0x1005802e 0xd _L1w_DrvReadAiResult
+ 0x1005803b 0x3b _L1w_DrvReadConfigTime
+ 0x10058076 0x3e _L1w_DrvSetConfigTime
+ 0x100580b4 0x1f _L1w_DrvPiAiReadCpichRam
+ 0x100580d3 0xa _L1w_DrvPiAiReadAiSymbolRam
+ 0x100580dd 0x1b _L1w_DrvPiAiReadSymbolRam
+ 0x100580f8 0xa _L1w_DrvEAiReadAmRam
+ 0x10058102 0x18 _L1w_DrvAiReadAmRam
+ 0x1005811a 0xff _L1w_DrvPiAiAichCfg
+ 0x10058219 0x12 _L1w_DrvPiAiAichRel
+ 0x1005822b 0x82 _L1w_DrvOffPichCfg
+ 0x100582ad 0x2b _L1w_DrvOffPichRel
+ .text 0x100582d8 0x2b7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_sleep.o)
+ 0x100582d8 0x9 _L1w_DrvSleepLpmCtrPwrOn
+ 0x100582e1 0x1c _L1w_DrvLpcModemIntCtrl
+ 0x100582fd 0x3d _L1w_DrvLpcLpmConfPosCal
+ 0x1005833a 0x38 _L1W_DrvLpcCfgSocWkupInt
+ 0x10058372 0x15 _L1W_DrvLpcCfgModemWkupInt
+ 0x10058387 0xe _L1w_DrvLpcModemWakeUpIntCtrl
+ 0x10058395 0xe _L1w_DrvLpcSocWakeUpIntCtrl
+ 0x100583a3 0x17 _L1w_DrvLpcLpmSoftReset
+ 0x100583ba 0x1a _L1w_DrvLpcClearInt
+ 0x100583d4 0xe _L1w_DrvLpcLpmSfIntCtrl
+ 0x100583e2 0x9 _L1w_DrvLpcIsLpmSfIntEn
+ 0x100583eb 0x8c _L1w_DrvLpcSetLpmFrmInt
+ 0x10058477 0x2b _L1w_DrvLpcSetLpmAdjustFactor
+ 0x100584a2 0x87 _L1w_DrvLpcLpmIntPwrCtrl
+ 0x10058529 0x1f _L1w_DrvLpcGetWNtTimeFromLpm
+ 0x10058548 0x2a _L1w_DrvLpcIcpSendForPsm
+ 0x10058572 0xe _L1w_DrvLpcSetCampOnFlg
+ 0x10058580 0x8 _L1w_DrvLpcSetSleepFlag
+ 0x10058588 0x7 _L1w_DrvLpcGetSleepFlag
+ .text 0x1005858f 0x39d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o)
+ 0x1005858f 0x1c _L1_DrvCsrInit
+ 0x100585ab 0x30 _L1_DrvCsrReset
+ 0x100585db 0x1c _L1w_DevCsrStep1Reset
+ 0x100585f7 0x5f _L1w_DrvCsrTopCfg
+ 0x10058656 0x82 _L1w_DrvCsrSlotSyncCfg
+ 0x100586d8 0x4b _L1w_DrvCsrIcCfg
+ 0x10058723 0x1 _L1w_DrvCsrFrameSyncCfg2A
+ 0x10058724 0x1 _L1w_DrvCsrFrameSyncCfg2B
+ 0x10058725 0x1 _L1w_DrvCsrScrambleSrchCfg
+ 0x10058726 0x66 _L1w_DrvCsrFullscanKscCfg
+ 0x1005878c 0x44 _L1w_DrvCsrFullscanUnKscCfg
+ 0x100587d0 0x83 _L1w_DrvCsrFullscanCfg
+ 0x10058853 0x94 _L1w_DrvCsrReadSlotSync
+ 0x100588e7 0x1 _L1w_DrvCsrStep1ReadMaxPos
+ 0x100588e8 0x1 _L1w_DrvCsrReadFrameSync2A
+ 0x100588e9 0x1 _L1w_DrvCsrReadFrameSync2B
+ 0x100588ea 0x1d _L1w_DrvCsrCmpFloat
+ 0x10058907 0x1 _L1w_DrvCsrReadScrambleCode
+ 0x10058908 0x24 _L1w_DrvCsrReadFs
+ .text 0x1005892c 0x306 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ 0x1005892c 0x9 _L1w_DrvSetTop01GdtrHdtrBitSet
+ 0x10058935 0xa _L1w_DrvSetTop01GdtrHdtrBitclr
+ 0x1005893f 0x9 _L1w_DrvSetTopEDmaIntBypassBitSet
+ 0x10058948 0xa _L1w_DrvSetTopEDmaIntBypassBitclr
+ 0x10058952 0x1c _L1w_DrvResetTopViterbi
+ 0x1005896e 0x6 _L1w_DrvGetTop0OSoftResetRegAddr
+ 0x10058974 0x9 _L1w_DrvTop00SoftResetBitSet
+ 0x1005897d 0xa _L1w_DrvTop00SoftResetBitClr
+ 0x10058987 0x9 _L1w_DrvTop10TpuRakeIntMaskBitSet
+ 0x10058990 0xa _L1w_DrvTop10TpuRakeIntMaskBitClr
+ 0x1005899a 0x9 _L1w_DrvTop11RakeDfeRfcIntMaskBitSet
+ 0x100589a3 0xa _L1w_DrvTop11RakeDfeRfcIntMaskBitClr
+ 0x100589ad 0x9 _L1w_DrvTop12TpuCsrAdrHsscchIntMaskBitSet
+ 0x100589b6 0xa _L1w_DrvTop12TpuCsrAdrHsscchIntMaskBitClr
+ 0x100589c0 0x9 _L1w_DrvTop13CsrDtrPsrIntMaskBitSet
+ 0x100589c9 0xa _L1w_DrvTop13CsrDtrPsrIntMaskBitClr
+ 0x100589d3 0x9 _L1w_DrvTop14TpuRakeIntStateMaskBitSet
+ 0x100589dc 0xa _L1w_DrvTop14TpuRakeIntStateMaskBitClr
+ 0x100589e6 0x9 _L1w_DrvTop15RakeDfeRfcIntStateMaskBitSet
+ 0x100589ef 0xa _L1w_DrvTop15RakeDfeRfcIntStateMaskBitClr
+ 0x100589f9 0x9 _L1w_DrvTop16TpuCsrAdrHsscchIntStateMaskBitSet
+ 0x10058a02 0xa _L1w_DrvTop16TpuCsrAdrHsscchIntStateMaskBitClr
+ 0x10058a0c 0x9 _L1w_DrvTop17CsrDtrPsrIntStateMaskBitSet
+ 0x10058a15 0xa _L1w_DrvTop17CsrDtrPsrIntStateMaskBitClr
+ 0x10058a1f 0xe _L1w_DrvTopCsrDtrPsrIntOpen
+ 0x10058a2d 0xe _L1w_DrvTopCsrDtrPsrIntClose
+ 0x10058a3b 0x8 _L1w_DrvTopGetTop10High16b
+ 0x10058a43 0x7 _L1w_DrvTopGetTop10Low16b
+ 0x10058a4a 0x8 _L1w_DrvTopGetTop14High16b
+ 0x10058a52 0x7 _L1w_DrvTopGetTop14Low16b
+ 0x10058a59 0x7 _L1w_DrvTopGetTop11Low16b
+ 0x10058a60 0x7 _L1w_DrvTopGetTop15Low16b
+ 0x10058a67 0x9 _L1w_DrvTopLpcOpenGateClk
+ 0x10058a70 0xa _L1w_DrvTopLpcCloseGateClk
+ 0x10058a7a 0xb _L1w_DrvTopClkIsOpen
+ 0x10058a85 0x13 _L1W_DrvTopLpcRegSave
+ 0x10058a98 0x23 _L1W_DrvTopLpcRegRestore
+ 0x10058abb 0x26 _L1w_DrvMcuIntMask
+ 0x10058ae1 0x26 _L1w_DrvMcuIntUnmask
+ 0x10058b07 0xa _L1w_DrvMcuIntIreqClr
+ 0x10058b11 0x5f _L1w_DrvTopIntMask
+ 0x10058b70 0x4f _L1w_DrvTopIntMaskRestore
+ 0x10058bbf 0x1a _L1w_DrvTopIntClr
+ 0x10058bd9 0x59 _L1w_DrvTopIntEng
+ .text 0x10058c32 0x20d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ 0x10058c32 0x25 _L1w_DrvTpuSoftResetCfg
+ 0x10058c57 0x39 _L1w_DrvTpuReset
+ 0x10058c90 0x28 _L1w_DrvTpuInit
+ 0x10058cb8 0x39 _L1w_DrvTpuNTIntEnable
+ 0x10058cf1 0x3a _L1w_DrvTpuNTIntDisable
+ 0x10058d2b 0x14 _L1w_DrvTpuRTIntEnable
+ 0x10058d3f 0x15 _L1w_DrvTpuRTIntDisable
+ 0x10058d54 0x11 _L1w_DrvTpuLatchTimeCfg
+ 0x10058d65 0x8 _L1w_DrvTpuRdNTTiming
+ 0x10058d6d 0x8 _L1w_DrvTpuRdRTTiming
+ 0x10058d75 0x11 _L1w_DrvTpuNTIntParaCfg
+ 0x10058d86 0x11 _L1w_DrvTpuRTIntParaCfg
+ 0x10058d97 0xa _L1w_DrvTpuMacroIntDisble
+ 0x10058da1 0x7 _L1w_DrvTpuMicroAdjParaCfg
+ 0x10058da8 0x8 _L1w_DrvTpuGetNT2RtOffset
+ 0x10058db0 0x8 _L1w_DrvTpuGetNTssfn
+ 0x10058db8 0x8 _L1w_DrvTpuGetRTssfn
+ 0x10058dc0 0x32 _L1w_DrvTpuMacroAdjParaCfg
+ 0x10058df2 0x28 _L1W_DrvTpuLpcRegRestore
+ 0x10058e1a 0x25 _L1W_DrvTpuLpcRegSave
+ .text 0x10058e3f 0x431 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o)
+ 0x10058e3f 0x26 _L1w_DrvTxReset
+ 0x10058e65 0xb _L1w_DrvTxClear
+ 0x10058e70 0x16 _L1w_DrvTxDpxchEnCfg
+ 0x10058e86 0x10 _L1w_DrvTxRamLpEnCfg
+ 0x10058e96 0x10 _L1w_DrvTxScramFixRotateEnCfg
+ 0x10058ea6 0x10 _L1w_DrvTxModeTypeCfg
+ 0x10058eb6 0x10 _L1w_DrvTxGateClkDisableCfg
+ 0x10058ec6 0x2b _L1w_DrvTxDpxchOffsetCfg
+ 0x10058ef1 0x31 _L1w_DrvTxPreamblePhchCfg
+ 0x10058f22 0xa _L1w_DrvTxPreamblePhchDisable
+ 0x10058f2c 0x2d _L1w_DrvTxPrachPhchCfg
+ 0x10058f59 0xa _L1w_DrvTxPrachPhchEnable
+ 0x10058f63 0xa _L1w_DrvTxPrachPhchDisable
+ 0x10058f6d 0x10 _L1w_DrvTxSampleTxRegTimeCfg
+ 0x10058f7d 0x10 _L1w_DrvTxDpcchFbiCfg
+ 0x10058f8d 0x16 _L1w_DrvTxDpcchTpcCfg
+ 0x10058fa3 0x43 _L1w_DrvTxDpxchPhchCfg
+ 0x10058fe6 0x30 _L1w_DrvTxPrachSpreaderCfg
+ 0x10059016 0x22 _L1w_DrvTxScramblerCfg
+ 0x10059038 0x2a _L1w_DrvTxDpxchOrPrachPwrCfg
+ 0x10059062 0x18 _L1w_DrvTxHsDpcchPwrCfg
+ 0x1005907a 0x18 _L1w_DrvTxEdpcchPwrCfg
+ 0x10059092 0x49 _L1w_DrvTxEdpdchPwrCfg
+ 0x100590db 0xc _L1w_DrvTxPreamblePwrCfg
+ 0x100590e7 0x111 _L1_DrvTxRfcTest
+ 0x100591f8 0x13 _L1w_DrvGetTxDpxchOffset
+ 0x1005920b 0x39 _L1w_DrvTxCordicAdjustCfg
+ 0x10059244 0x9 _L1w_DrvTxCordicDisable
+ 0x1005924d 0x23 _L1w_DrvTxCordicEnable
+ .text 0x10059270 0x381 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ 0x10059270 0x27 _L1w_DrvMeasReset
+ 0x10059297 0x57 _L1w_DrvMeasCfgCellCode
+ 0x100592ee 0x19 _L1w_DrvMeasParaOverCfg
+ 0x10059307 0x6e _L1w_DrvMeasCfgSpsrStartTime
+ 0x10059375 0x8 _L1w_DrvMeasCfgClkGating
+ 0x1005937d 0x60 _L1w_DrvMeasReadResult
+ 0x100593dd 0x1a _L1w_DrvMeasReadAgc
+ 0x100593f7 0xa _L1w_DrvMeasReadSpsrIntSeqNum
+ 0x10059401 0x5f _L1w_DrvMeasCompareConfigTime
+ 0x10059460 0x14 _L1w_DrvMeasReadSpsrstatus
+ 0x10059474 0x8 _L1w_DrvMeasOffLineRamparaCfg
+ 0x1005947c 0x8 _L1w_DrvMeasOffLineRamMrtrCfg
+ 0x10059484 0x9 _L1w_DrvMeasMeasBufUpdateCfg
+ 0x1005948d 0x8 _L1w_DrvMeasWorkModeCfg
+ 0x10059495 0x8 _L1w_DrvMeasOnLineStartSpsrCfg
+ 0x1005949d 0xe _L1w_DrvMeasOnLineGetSpsrCfg
+ 0x100594ab 0x10 _L1w_DrvMeasOnLineAgc0paraCfg
+ 0x100594bb 0x10 _L1w_DrvMeasOnLineAgc1paraCfg
+ 0x100594cb 0x35 _L1w_DrvMeasOnLineAgc0StartMrtrCfg
+ 0x10059500 0x35 _L1w_DrvMeasOnLineAgc1StartMrtrCfg
+ 0x10059535 0x4f _L1w_DrvMeasFrameBoundaryCfg
+ 0x10059584 0x2d _L1w_DrvMeasSpsrParaCfg
+ 0x100595b1 0x1c _L1w_DrvMeasCellSttdModeCfg
+ 0x100595cd 0xa _L1w_DrvMeasClkGatingCfg
+ 0x100595d7 0x9 _L1w_DrvMeasSoftPatternCfg
+ 0x100595e0 0x9 _L1w_DrvMeasPatternModeCfg
+ 0x100595e9 0x8 _L1w_DrvMeasCfgOfflineSpsrStartTime
+ .text 0x100595f1 0x55d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o)
+ 0x100595f1 0x22 _L1w_DrvHsupaEutrEnable
+ 0x10059613 0xa _L1w_DrvHsupaEutrDisable
+ 0x1005961d 0xe _L1w_DrvHsupaEutrSoftRst
+ 0x1005962b 0x13 _L1w_DrvHsupaEutrHarqRamMode
+ 0x1005963e 0x10 _L1w_DrvHsupaEutrHarqId
+ 0x1005964e 0xb _L1w_DrvHsupaEutrTtiTwoFlg
+ 0x10059659 0xb _L1w_DrvHsupaEutrTbSize
+ 0x10059664 0x47 _L1w_DrvHsupaEutrCodeSize
+ 0x100596ab 0x3e _L1w_DrvHsupaEutrPhchPara
+ 0x100596e9 0x2d _L1w_DrvHsupaEutrRmSysPara
+ 0x10059716 0x2d _L1w_DrvHsupaEutrRmP1Para
+ 0x10059743 0x2d _L1w_DrvHsupaEutrRmP2Para
+ 0x10059770 0x55 _L1w_DrvHsupaEutrInterPara
+ 0x100597c5 0x60 _L1w_DrvHsupaEutrConfig
+ 0x10059825 0xb _L1w_DrvHsupaEutrReadHarqStatus
+ 0x10059830 0x23 _L1w_DrvHsupaEtxEnable
+ 0x10059853 0x12 _L1w_DrvHsupaEtxDisable
+ 0x10059865 0x19 _L1w_DrvHsupaEtxCfgTti
+ 0x1005987e 0x2a _L1w_DrvHsupaCfgEtxInt
+ 0x100598a8 0x12 _L1w_DrvHsupaTopEtxIntEnable
+ 0x100598ba 0xb _L1w_DrvHsupaEtxDisInt
+ 0x100598c5 0x1b _L1w_DrvHsupaTopMaskEtxInt
+ 0x100598e0 0x31 _L1w_DrvHsupaRakeReadRgHi
+ 0x10059911 0xa _L1w_DrvHsupaCalLogTwo
+ 0x1005991b 0x42 _L1w_DrvHsupaEtxInterPara
+ 0x1005995d 0x34 _L1w_DrvHsupaEtxChCfgReg2
+ 0x10059991 0x54 _L1w_DrvHsupaEtxEdpxchPara
+ 0x100599e5 0x25 _L1w_DrvHsupaEtxSpreadReg
+ 0x10059a0a 0x29 _L1w_DrvHsupaEtxConf
+ 0x10059a33 0xb _L1w_DrvHsupaEtxReadTtiCnt
+ 0x10059a3e 0x20 _L1w_DrvHsupaTopGetIntState
+ 0x10059a5e 0x1 _L1w_DrvHsupaTopMaskEutrInt
+ 0x10059a5f 0xf _L1w_DrvHsupaTopMaskRgHiState
+ 0x10059a6e 0xf _L1w_DrvHsupaTopMaskRgHiInt
+ 0x10059a7d 0x17 _L1w_DevHsupaTopMaskAgInt
+ 0x10059a94 0x2 _L1w_DrvHsupaTopMaskRgchHichInt
+ 0x10059a96 0x23 _L1w_DrvHsupaMaskInt
+ 0x10059ab9 0x2d _L1w_DrvHsupaTopEagchRst
+ 0x10059ae6 0x7 _L1w_DrvHsupaRdAgIntStateMask
+ 0x10059aed 0x7 _L1w_DrvHsupaWtAgIntStateMask
+ 0x10059af4 0x7 _L1w_DrvHsupaRdAgIntEnable
+ 0x10059afb 0x7 _L1w_DrvHsupaWtAgIntEnable
+ 0x10059b02 0x7 _L1w_DrvHsupaRdRgHiIntStateMask
+ 0x10059b09 0x7 _L1w_DrvHsupaWtRgHiIntStateMask
+ 0x10059b10 0x7 _L1w_DrvHsupaRdRgHiIntEnable
+ 0x10059b17 0x7 _L1w_DrvHsupaWtRgHiIntEnable
+ 0x10059b1e 0x17 _L1w_DrvHsupaEnableAgInt
+ 0x10059b35 0x13 _L1w_DrvHsupaPcEtxEdpdchDisable
+ 0x10059b48 0x6 _L1w_DrvEutrGetRamAddr
+ .text 0x10059b4e 0x506 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ 0x10059b4e 0x1 _L1w_DrvDpramEngDisplay
+ 0x10059b4f 0x4a _L1w_DrvDpramStructInit
+ 0x10059b99 0x25 _L1w_DrvDpramIsEmpty
+ 0x10059bbe 0x42 _L1w_DrvDpramReadMsg
+ 0x10059c00 0x1 _L1w_DrvDpramUpdateMsgPos
+ 0x10059c01 0x5 _L1w_DrvDpramQueMemRead
+ 0x10059c06 0x37 _L1w_DrvDpramWriteMsg
+ 0x10059c3d 0x23 _L1w_DrvDpramGetRdDataPtr
+ 0x10059c60 0x1f _L1w_DrvDpramUpdateRdDataPos
+ 0x10059c7f 0x24 _L1w_DrvDpramTxReadClearData
+ 0x10059ca3 0x31 _L1w_DrvDpramGetWrDataPtr
+ 0x10059cd4 0x8 _L1w_DrvDpramGetWrCnt
+ 0x10059cdc 0x2c _L1w_DrvDpramUpdateWrDataPos
+ 0x10059d08 0x1a _L1w_DrvICPSendForPsSched
+ 0x10059d22 0xa _L1w_DrvDpramIsD2AEmpty
+ 0x10059d2c 0xa _L1w_DrvDpramSleepCheck
+ 0x10059d36 0x8 _L1w_DrvDpramWriteSfnDpramFlg
+ 0x10059d3e 0x7 _L1w_DrvDpramWriteDoff2Dpram
+ 0x10059d45 0x7 _L1w_DrvDpramReadEdcpIntState
+ 0x10059d4c 0xa _L1w_DrvDpramClrEdcpIntState
+ 0x10059d56 0x7 _L1w_DrvDpramClrIcpIntState
+ 0x10059d5d 0xa _L1w_DrvDpramMaskIcpInt
+ 0x10059d67 0x9 _L1w_DrvDpramDemaskIcpInt
+ 0x10059d70 0x49 _L1w_DrvDpramPrintLog
+ 0x10059db9 0x104 _L1w_DrvDpramUpdateTpu
+ 0x10059ebd 0x26 _L1w_DrvDpramWriteGrantHarq
+ 0x10059ee3 0x26 _L1w_DrvDpramWriteUlPower
+ 0x10059f09 0x41 _L1w_DrvDpramGetEutrCtrlInfo
+ 0x10059f4a 0xa _L1w_DrvDpramSetRachDchTransFlg
+ 0x10059f54 0xa _L1w_DrvDpramGetRachDchTransFlg
+ 0x10059f5e 0x20 _L1w_DrvDpramSetUpaTransInfo
+ 0x10059f7e 0x1f _L1w_DrvDpramGetGrantMonitorReq
+ 0x10059f9d 0xe _L1w_DrvDpramHsupaSetActiveInfos
+ 0x10059fab 0xa _L1w_DrvDpramSetCmPattern
+ 0x10059fb5 0x9 _L1w_DrvDpramSetUph
+ 0x10059fbe 0x2f _L1w_DrvDpramWriteEtfcRestrictInfo
+ 0x10059fed 0x3e _L1w_DrvDpramWriteCmNtrInfo
+ 0x1005a02b 0x29 _L1w_DrvDpramGetEdchHarqId
+ .text 0x1005a054 0x1984 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ 0x1005a054 0x81 _L1w_DrvRxTpcPlCombTimeInit
+ 0x1005a0d5 0x83 _L1w_DrvRxInit
+ 0x1005a158 0x50 _L1w_DrvRxReset
+ 0x1005a1a8 0x2c _L1w_DrvRxSoftReset
+ 0x1005a1d4 0x35 _L1w_DrvRxCalcExp2
+ 0x1005a209 0xe _L1w_DrvRxFingerCfg
+ 0x1005a217 0x2c _L1w_DrvRxSetTfciIntTime
+ 0x1005a243 0x8 _L1w_DrvRxGetTfciIntTime
+ 0x1005a24b 0x191 _L1w_DrvRxCpichCfg
+ 0x1005a3dc 0x16 _L1w_DrvRxCpichRel
+ 0x1005a3f2 0x109 _L1w_DrvRxPichCfg
+ 0x1005a4fb 0x3a _L1w_DrvRxPichRel
+ 0x1005a535 0x123 _L1w_DrvRxAichCfg
+ 0x1005a658 0x3a _L1w_DrvRxAichRel
+ 0x1005a692 0x11d _L1w_DrvRxPchCfg
+ 0x1005a7af 0x11 _L1w_DrvRxPchRel
+ 0x1005a7c0 0x126 _L1w_DrvRxFachCfg
+ 0x1005a8e6 0x3b _L1w_DrvRxFachRel
+ 0x1005a921 0x10e _L1w_DrvRxDlDpchCodeCfg
+ 0x1005aa2f 0x33 _L1w_DrvRxDlTpcPilotCfg
+ 0x1005aa62 0x29 _L1w_DrvRxFdpchTpcCfg
+ 0x1005aa8b 0xa4 _L1w_DrvRxDlDpchCfg
+ 0x1005ab2f 0x6f _L1w_DrvRxDlDpchRel
+ 0x1005ab9e 0x31 _L1w_DrvRxDlFbiCfg
+ 0x1005abcf 0x15b _L1w_DrvRxFdpchCfg
+ 0x1005ad2a 0x3b _L1w_DrvRxFdpchRel
+ 0x1005ad65 0x16a _L1w_DrvRxHsscchCfg
+ 0x1005aecf 0x65 _L1w_DrvRxHsscchRel
+ 0x1005af34 0x103 _L1w_DrvRxEagchCfg
+ 0x1005b037 0x40 _L1w_DrvRxEagchRel
+ 0x1005b077 0x333 _L1w_DrvRxRgHiCfg
+ 0x1005b3aa 0x3c _L1w_DrvRxRgHiRel
+ 0x1005b3e6 0x15 _L1w_DrvRxEdchTtiCfg
+ 0x1005b3fb 0x5b _L1w_DrvRxRgHichPostCmCfg
+ 0x1005b456 0x10 _L1w_DrvRxDpchFactorCfg
+ 0x1005b466 0xf _L1w_DrvRxAgchFactorCfg
+ 0x1005b475 0x77 _L1w_DrvRxDlCmCfnCfg
+ 0x1005b4ec 0x8c _L1w_DrvRxDlCmSymbCfg
+ 0x1005b578 0x64 _L1w_DrvRxDlCmPostCfg
+ 0x1005b5dc 0x1f _L1w_DrvRxDlCmSymbRel
+ 0x1005b5fb 0x16 _L1w_DrvRxDlCmPostRel
+ 0x1005b611 0x24 _L1w_DrvRxRakeCpChangRel
+ 0x1005b635 0x8e _L1w_DrvRxRakeChipCfg
+ 0x1005b6c3 0x119 _L1w_DrvRxRakeSymbCfg
+ 0x1005b7dc 0x4a _L1w_DrvRxRakePostCfg
+ 0x1005b826 0x18 _L1w_DrvRxRakeCfg
+ 0x1005b83e 0xc _L1w_DrvRxSymbCpichStRead
+ 0x1005b84a 0xc _L1w_DrvRxSymbPilotStRead
+ 0x1005b856 0x9 _L1w_DrvRxCombPiAiIntRead
+ 0x1005b85f 0x9 _L1w_DrvRxCombPilotIntRead
+ 0x1005b868 0x9 _L1w_DrvRxCombTpcIntRead
+ 0x1005b871 0x15 _L1w_DrvRxCombTpcPlStIntRead
+ 0x1005b886 0x8 _L1w_DrvRxCombFdpchIntRead
+ 0x1005b88e 0xa _L1w_DrvRxCombDpchFactorDataRead
+ 0x1005b898 0xa _L1w_DrvRxCombAgchFactorDataRead
+ 0x1005b8a2 0x27 _L1w_DrvRxRamPiAiRead
+ 0x1005b8c9 0xa _L1w_DrvRxRamDpchPilotRead
+ 0x1005b8d3 0xa _L1w_DrvRxRamDpchTpcRead
+ 0x1005b8dd 0x43 _L1w_DrvRxRamFdpchTpcRead
+ 0x1005b920 0x15 _L1w_DrvRxRamSlotwtRead
+ 0x1005b935 0x15 _L1w_DrvRxRamNoiseRead
+ 0x1005b94a 0x1f _L1w_DrvRxRamRawCpichRead
+ 0x1005b969 0x15 _L1w_DrvRxRamAfcRead
+ 0x1005b97e 0x1c _L1w_DrvRxRamRawPilotRead
+ 0x1005b99a 0x1f _L1w_DrvRxRgchIntInfoRead
+ 0x1005b9b9 0x1f _L1w_DrvRxHichIntInfoRead
+ .text 0x1005b9d8 0xa62 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dtr.o)
+ 0x1005b9d8 0x11 _L1w_DrvDtrBitReverse
+ 0x1005b9e9 0xa _L1w_DrvDtrTurboInit
+ 0x1005b9f3 0x1d _L1w_DrvDtrTurboReset
+ 0x1005ba10 0x11 _L1w_DrvDtrSetCsServiceFlg
+ 0x1005ba21 0x3b _L1w_DrvDtrReset
+ 0x1005ba5c 0x5e _L1w_DrvDtrInit
+ 0x1005baba 0x3e _L1w_DrvDtrTrchCmCfg
+ 0x1005baf8 0x4c _L1w_DrvDtrTrchSlotFormCfg
+ 0x1005bb44 0x171 _L1w_DrvDtrTrchTfciS1Cfg
+ 0x1005bcb5 0x24 _L1w_DrvDtrTrchTfciS1Clear
+ 0x1005bcd9 0xb _L1w_DrvDtrTrchCfnSet
+ 0x1005bce4 0xa _L1w_DrvDtrTrchCfnGet
+ 0x1005bcee 0xf _L1w_DrvDtrTrchRegRel
+ 0x1005bcfd 0xa _L1w_DrvDtrTrchTfciS2Update
+ 0x1005bd07 0xa _L1w_DrvDtrTrchDemultiplexUpdate
+ 0x1005bd11 0x9f _L1w_DrvDtrS1CfgPrint
+ 0x1005bdb0 0x1d7 _L1w_DrvDtrS2CfgPrint
+ 0x1005bf87 0xb0 _L1w_DrvDtrTrchTfciS2Cfg
+ 0x1005c037 0xb _L1w_DrvDtrTrchTfciS2Clear
+ 0x1005c042 0x42 _L1w_DrvDtrTrchBlindS1Cfg
+ 0x1005c084 0xa5 _L1w_DrvDtrTrchBlindGuidCfg
+ 0x1005c129 0xc _L1w_DrvDtrTrchBlindGuidUpdate
+ 0x1005c135 0xa _L1w_DrvDtrTrchTfciRead
+ 0x1005c13f 0x2d _L1w_DrvDtrTrchTfciDataReadV3
+ 0x1005c16c 0x30 _L1w_DrvDtrTrchBlindRead
+ 0x1005c19c 0x6 _L1w_DrvDtrTrchBlindDataAddrGet
+ 0x1005c1a2 0x24 _L1w_DrvDtrTrchDecodeInfoRead
+ 0x1005c1c6 0x6 _L1w_DrvDtrTrchDecodeAddrGet
+ 0x1005c1cc 0x1bb _L1w_DrvDtrTrchDecodeDataRead
+ 0x1005c387 0x61 _L1w_DrvDtrEagchCfg
+ 0x1005c3e8 0xe _L1w_DrvDtrEagchCmCfg
+ 0x1005c3f6 0x9 _L1w_DrvDtrEagchRel
+ 0x1005c3ff 0x3b _L1w_DrvDtrAgchIntDataRead
+ .text 0x1005c43a 0x572 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_bch.o)
+ 0x1005c43a 0x2d _L1w_DrvBchInit
+ 0x1005c467 0xe _L1w_DrvBchReset
+ 0x1005c475 0x2d _L1w_DrvBchRecover
+ 0x1005c4a2 0xd _L1w_DrvBchSetFingerAdjust
+ 0x1005c4af 0xe _L1w_DrvBchGeViterbiOut
+ 0x1005c4bd 0x56 _L1w_DrvBchGePichSymbol
+ 0x1005c513 0xa _L1w_DrvBchGeCrcResult
+ 0x1005c51d 0x2b _L1w_DrvBchGeCpichOut
+ 0x1005c548 0xf8 _L1w_DrvBchBchRxCfg
+ 0x1005c640 0xcd _L1w_DrvBchPichRxCfg
+ 0x1005c70d 0x9b _L1w_DrvBchCpichRxCfg
+ 0x1005c7a8 0xc _L1w_DrvBchSetFingerEn
+ 0x1005c7b4 0xc _L1w_DrvBchSetRuntime
+ 0x1005c7c0 0xe _L1w_DrvBchGetFingerPos
+ 0x1005c7ce 0x10 _L1w_DrvBchSetS5TestMode
+ 0x1005c7de 0xa _L1w_DrvBchSetTxdMode
+ 0x1005c7e8 0x7 _L1w_DrvBchSetBchPichSel
+ 0x1005c7ef 0x7 _L1w_DrvBchSetTtiSync
+ 0x1005c7f6 0x7 _L1w_DrvBchSetWindowTh
+ 0x1005c7fd 0x7 _L1w_DrvBchSetPichOvsfk
+ 0x1005c804 0xc _L1w_DrvBchSetContexSel
+ 0x1005c810 0xd _L1w_DrvBchSetFingerPos
+ 0x1005c81d 0x19 _L1w_DrvBchSetScramCode
+ 0x1005c836 0x16 _L1w_DrvBchSetStartMode
+ 0x1005c84c 0xc _L1w_DrvBchSetPiAfcNum
+ 0x1005c858 0x31 _L1w_DrvBchSetPiPos
+ 0x1005c889 0xe _L1w_DrvBchGetFingerSt
+ 0x1005c897 0xd _L1w_DrvBchHasInvalidSymbol
+ 0x1005c8a4 0xe _L1w_DrvBchGetBufIndex
+ 0x1005c8b2 0xe _L1w_DrvBchGetSlotIndex
+ 0x1005c8c0 0xe _L1w_DrvBchGetBurstPattern
+ 0x1005c8ce 0xa _L1w_DrvBchGeTotalSt
+ 0x1005c8d8 0x16 _L1w_DrvBchIsHwBusy
+ 0x1005c8ee 0x13 _L1w_DrvBchSetIQSel
+ 0x1005c901 0x12 _L1w_DrvBchSetRotatePara
+ 0x1005c913 0x21 _L1w_DrvBchSetRotateEn
+ 0x1005c934 0xf _L1w_DrvBchSetRotateGateCtrl
+ 0x1005c943 0xb _L1w_DrvBchIsIqRotateEn
+ 0x1005c94e 0x36 _L1w_DrvBchStopIqRotate
+ 0x1005c984 0x12 _L1w_DrvBchSetFingerAnt
+ 0x1005c996 0x16 _L1w_DrvBchSetAdjFingerInfo
+ .text 0x1005c9ac 0x2f1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_utr.o)
+ 0x1005c9ac 0xc _L1w_DrvUtrLogTwo
+ 0x1005c9b8 0x31 _L1w_DrvUtrReset
+ 0x1005c9e9 0x1c _L1w_DrvUtrRamSoftReset
+ 0x1005ca05 0x3 _L1w_DrvUtrInit
+ 0x1005ca08 0xac _L1w_DrvUtrDchConfig
+ 0x1005cab4 0x32 _L1w_DrvUtrRachConfig
+ 0x1005cae6 0xa _L1w_DrvUtrEnable
+ 0x1005caf0 0xe _L1w_DrvUtrClose
+ 0x1005cafe 0x8 _L1w_DrvUtrGetRamAddr
+ 0x1005cb06 0x5f _L1w_DrvUtrTbAndCbConfig
+ 0x1005cb65 0xac _L1w_DrvUtrRMConfig
+ 0x1005cc11 0x2d _L1w_DrvUtrGetCrcMode
+ 0x1005cc3e 0x20 _L1w_DrvUtrGetCodingType
+ 0x1005cc5e 0x1a _L1w_DrvUtrClearRmPara
+ 0x1005cc78 0xc _L1w_DrvUtrRegClear
+ 0x1005cc84 0x11 _L1w_DrvUtrGetRamData
+ 0x1005cc95 0x8 _L1_DrvUtrGetInterlv1RamState
+ .text 0x1005cc9d 0x1dda T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o)
+ 0x1005cc9d 0x5e _L1w_DrvRfcApcTableSel
+ 0x1005ccfb 0x1d2 _L1w_DrvRfcAbbCsfHpfCfg
+ 0x1005cecd 0x5 _L1w_DrvRfcCalcIntFreq
+ 0x1005ced2 0x29 _L1w_DrvRfcCalcFracFreq
+ 0x1005cefb 0x51 _L1w_DrvRfcGetFreqData
+ 0x1005cf4c 0x19 _L1w_DrvRfcGetBandData
+ 0x1005cf65 0x9d _L1w_DrvRfcFreqSetTx
+ 0x1005d002 0x12a _L1w_DrvRfcFreqSetRx
+ 0x1005d12c 0x84 _L1w_DrvRfcGetBandNvIndex
+ 0x1005d1b0 0x79 _L1w_DrvRfcAuxRxCtrlSet
+ 0x1005d229 0x1c _L1w_DrvRfcAuxRxIdleSet
+ 0x1005d245 0x20 _L1w_DrvRfcRegReadBackSet
+ 0x1005d265 0x1 _L1w_DrvRfcChSel
+ 0x1005d266 0x1 _L1w_DrvRfcTransceiverInit
+ 0x1005d267 0x2e _L1w_DrvRfcAgcSet
+ 0x1005d295 0x2f _L1w_DrvRfcApcTableFreqSel
+ 0x1005d2c4 0xbc _L1w_DrvRfcApcSet
+ 0x1005d380 0x2d _L1w_DrvRfcFreqCompGetNvIdx
+ 0x1005d3ad 0x7c _L1w_DrvRfcApcFreqComp
+ 0x1005d429 0x38 _L1w_DrvRfcApcTmpComp
+ 0x1005d461 0x100 _L1w_DrvRfcApcCalibTableCheck
+ 0x1005d561 0x4f _L1w_DrvRfcApcDefaultTableCheck
+ 0x1005d5b0 0x77 _L1w_DrvRfcAgcFreqComp
+ 0x1005d627 0x71 _L1w_DrvRfcAgcCalibTableCheck
+ 0x1005d698 0x46 _L1w_DrvRfcAgcDefaultTableCheck
+ 0x1005d6de 0x2a _L1w_DrvRfcRxNotchEn
+ 0x1005d708 0x2a _L1w_DrvRfcRxNotchDisEn
+ 0x1005d732 0x2b _L1w_DrvRfcAntExChangeSelEn
+ 0x1005d75d 0x2b _L1w_DrvRfcAntOriginSelEn
+ 0x1005d788 0x2a _L1w_DrvRfcRxStartDivEn
+ 0x1005d7b2 0x2b _L1w_DrvRfcRxStopDivEn
+ 0x1005d7dd 0x2a _L1w_DrvRfcAuxRxSwCtrlEn
+ 0x1005d807 0x2b _L1w_DrvRfcAuxRxSwIdleEn
+ 0x1005d832 0x38 _L1w_DrvRfcIdleToTxEn
+ 0x1005d86a 0x36 _L1w_DrvRfcTxToRxTxEn
+ 0x1005d8a0 0x3a _L1w_DrvRfcTxToIdleEn
+ 0x1005d8da 0x36 _L1w_DrvRfcRxTxToTxEn
+ 0x1005d910 0x36 _L1w_DrvRfcIdleToRxEn
+ 0x1005d946 0x38 _L1w_DrvRfcRxToRxTxEn
+ 0x1005d97e 0x2b _L1w_DrvRfcSwAllIdleEn
+ 0x1005d9a9 0x40 _L1w_DrvRfcRxToIdleEn
+ 0x1005d9e9 0x2d _L1w_DrvRfcRxTxToRxEn
+ 0x1005da16 0x37 _L1w_DrvRfcRxFreqChangeEn
+ 0x1005da4d 0x38 _L1w_DrvRfcTxFreqChangeEn
+ 0x1005da85 0x32 _L1w_DrvRfcIdleToTxHandle
+ 0x1005dab7 0x48 _L1w_DrvRfcTxToIdleHandle
+ 0x1005daff 0x45 _L1w_DrvRfcIdleToRxHandle
+ 0x1005db44 0x55 _L1w_DrvRfcRxToIdleHandle
+ 0x1005db99 0x53 _L1w_DrvRfcRxFreqChangeHandle
+ 0x1005dbec 0xd _L1w_DrvRfcTxFreqChangeHandle
+ 0x1005dbf9 0x41 _L1w_DrvRfcSlotCtrlDiv
+ 0x1005dc3a 0x2a _L1w_DrvRfcSlotCtrlAntSel
+ 0x1005dc64 0x29 _L1w_DrvRfcAgcEstEn
+ 0x1005dc8d 0x29 _L1w_DrvRfcAgcSetEn
+ 0x1005dcb6 0x35 _L1w_DrvRfcApcEn
+ 0x1005dceb 0x3c _L1w_DrvRfcAfcSetEn
+ 0x1005dd27 0x29 _L1w_DrvRfcDcEstEn
+ 0x1005dd50 0x29 _L1w_DrvRfcDcSetEn
+ 0x1005dd79 0x29 _L1w_DrvRfcRegReadBackEn
+ 0x1005dda2 0x29 _L1w_DrvRfcStartAuxAdcEn
+ 0x1005ddcb 0x29 _L1w_DrvRfcStopAuxAdcEn
+ 0x1005ddf4 0x1c _L1w_DrvRfcDcxoAuxAdcStart
+ 0x1005de10 0x1d _L1w_DrvRfcDcxoAuxAdcStop
+ 0x1005de2d 0x1f _L1w_DrvRfcAuxAdcCtrlEn
+ 0x1005de4c 0x41 _L1w_DrvRfcAbbCsfWriteEn
+ 0x1005de8d 0x33 _L1w_DrvRfcCtrlRamTxInit
+ 0x1005dec0 0x33 _L1w_DrvRfcCtrlRamRx0Init
+ 0x1005def3 0x204 _L1w_DrvRfcCtrlRamSwitchNvInit
+ 0x1005e0f7 0xea _L1w_DrvRfcCtrlRamPaNvInit
+ 0x1005e1e1 0x8 _L1w_DrvRfcCtrlRamNvEventInit
+ 0x1005e1e9 0x38 _L1w_DrvRfcFastAgcCwTableInit
+ 0x1005e221 0x4c _L1w_DrvRfcFastAgcRamInit
+ 0x1005e26d 0xda _L1w_DrvRfcOpenTx
+ 0x1005e347 0xf7 _L1w_DrvRfcOpenRx
+ 0x1005e43e 0xa _L1w_DrvRfcDiversityCtrl
+ 0x1005e448 0x12 _L1w_DrvRfcAfcCw2Hz
+ 0x1005e45a 0x6a _L1w_DrvRfcRfRegRead
+ 0x1005e4c4 0xce _L1w_DrvRfcAllRegReadBack
+ 0x1005e592 0x54 _L1w_DrvRfcGetDCXOTmp
+ 0x1005e5e6 0x3b _L1w_DrvRfcReadTmp
+ 0x1005e621 0x15 _L1w_DrvRfcAptWrite
+ 0x1005e636 0x21 _L1w_DrvRfcDcocWrite
+ 0x1005e657 0x18 _L1w_DrvRfcAgcWrite
+ 0x1005e66f 0x8d _L1w_DrvRfcCloseTx
+ 0x1005e6fc 0x6d _L1w_DrvRfcCloseRx
+ 0x1005e769 0x7e _L1w_DrvRfcDirFreqSetTx
+ 0x1005e7e7 0x7c _L1w_DrvRfcDirFreqSetRx
+ 0x1005e863 0x32 _L1w_DrvRfcPowerApcSet
+ 0x1005e895 0x43 _L1w_DrvRfcIndexApcSet
+ 0x1005e8d8 0x177 _L1w_DrvRfcFdtTxApcSet
+ 0x1005ea4f 0x22 _L1w_DrvRfcHdtGetTxApcTable
+ 0x1005ea71 0x6 _L1w_DrvRfcHdtGetRxAgcTable
+ .text 0x1005ea77 0xb8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_psr.o)
+ 0x1005ea77 0x8 _L1w_DrvPsrStartPosCfg
+ 0x1005ea7f 0xb _L1w_DrvPsrRlMrtrPosMrtrConfig
+ 0x1005ea8a 0xb _L1w_DrvPsrSrcAndChanCodeCfg
+ 0x1005ea95 0x8 _L1w_DrvPsrClkGatePassCfg
+ 0x1005ea9d 0x9 _L1w_DrvPsrPilotPatternCfg
+ 0x1005eaa6 0x8 _L1w_DrvPsrCmModeCfg
+ 0x1005eaae 0x9 _L1w_DrvPsrRlPosStartCfgOver
+ 0x1005eab7 0x9 _L1w_DrvPsrSuspendCfg
+ 0x1005eac0 0x12 _L1w_DrvPsrTopMaskIntCfg
+ 0x1005ead2 0x1c _L1w_DrvPsrResetCfg
+ 0x1005eaee 0x8 _L1w_DrvPsrPeriodCfg
+ 0x1005eaf6 0x8 _L1w_DrvPsrDoubleAntOpencfg
+ 0x1005eafe 0x8 _L1w_DrvPsrStartWinPosCfg
+ 0x1005eb06 0x8 _L1w_DrvPsrRlOpenCloseCfg
+ 0x1005eb0e 0x8 _L1w_DrvPsrMasterRlCfg
+ 0x1005eb16 0x8 _L1w_DrvPsrSttdCfg
+ 0x1005eb1e 0x8 _L1w_DrvPsrIntInfoCfg
+ 0x1005eb26 0x9 _L1w_DrvPsrCmOverCfg
+ .text 0x1005eb2f 0xaff T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ 0x1005eb2f 0x3c _L1w_DrvRfcGetFreqOffset
+ 0x1005eb6b 0x17 _L1w_DrvRfcNextSlotGet
+ 0x1005eb82 0x16 _L1w_DrvRfcPreSlotGet
+ 0x1005eb98 0x20 _L1w_DrvRfcFindSlot
+ 0x1005ebb8 0x8 _L1w_DrvRfcGetTxFirDlyNum
+ 0x1005ebc0 0x31 _L1w_DrvRfcSpiWrite
+ 0x1005ebf1 0x31 _L1w_DrvRfcAbbSpiWrite
+ 0x1005ec22 0x12 _L1w_DrvRfcGpioWrite
+ 0x1005ec34 0x14 _L1w_DrvRfcRffeWrite
+ 0x1005ec48 0x38 _L1w_DrvRfcFindBandNumFromTable
+ 0x1005ec80 0x41 _L1w_DrvRfcGetFreqBand
+ 0x1005ecc1 0x22 _L1w_DrvRfcRxDfeIntfCfg
+ 0x1005ece3 0x2f _L1w_DrvRfcPaModeSel
+ 0x1005ed12 0x25 _L1w_DrvRfcGetPaCtrlData
+ 0x1005ed37 0x1a _L1w_DrvRfcGetPaIdleData
+ 0x1005ed51 0x2a _L1w_DrvRfcGetApcCtrlWord
+ 0x1005ed7b 0xa3 _L1w_DrvRfcGetTxPowerCtrlWord
+ 0x1005ee1e 0x14 _L1w_DrvRfcPaCtrl
+ 0x1005ee32 0x25 _L1w_DrvRfcGetAgcCtrlWord
+ 0x1005ee57 0x27 _L1w_DrvRfcGetAfcDacCtrlWord
+ 0x1005ee7e 0x2c _L1w_DrvRfcDCXOGetTempDegree
+ 0x1005eeaa 0xb _L1w_DrvRfcAfcSet
+ 0x1005eeb5 0x1a _L1w_DrvRfcGetTxSwData
+ 0x1005eecf 0x29 _L1w_DrvRfcGetRxSwData
+ 0x1005eef8 0x1a _L1w_DrvRfcGetTxSwIdleData
+ 0x1005ef12 0x29 _L1w_DrvRfcGetRxSwIdleData
+ 0x1005ef3b 0x1a _L1w_DrvRfcGetSwAllIdleData
+ 0x1005ef55 0x27 _L1w_DrvRfcSwitchPaCwWr
+ 0x1005ef7c 0x37 _L1w_DrvRfcSwitchCtrl
+ 0x1005efb3 0x55 _L1w_DrvRfcSwPaIdleNvGet
+ 0x1005f008 0x12 _L1w_DrvRfcGetCfgMrtr
+ 0x1005f01a 0x54 _L1w_DrvRfcTuEventMrtrWr
+ 0x1005f06e 0x21 _L1w_DrvRfcTuEventCtrlDataWr
+ 0x1005f08f 0x54 _L1w_DrvRfcTuEventEn
+ 0x1005f0e3 0x27 _L1w_DrvRfcCtrlRamFmtDataWr
+ 0x1005f10a 0x28 _L1w_DrvRfcCtrlRamFmtInfoWr
+ 0x1005f132 0x20 _L1w_DrvRfcCtrlRamDataTypeWr
+ 0x1005f152 0x40 _L1w_DrvRfcCtrlRamEn
+ 0x1005f192 0xe _L1w_DrvRfcAgcRamDataWr
+ 0x1005f1a0 0x1c _L1w_DrvRfcFastAgcEn
+ 0x1005f1bc 0x1a _L1w_DrvRfcFastAgcDisEn
+ 0x1005f1d6 0x15 _L1w_DrvRfcIntCfg
+ 0x1005f1eb 0x15 _L1w_DrvRfcSpiFormatCfg
+ 0x1005f200 0x9 _L1w_DrvRfcRffeFormatCfg
+ 0x1005f209 0x2 _L1w_DrvRfcRbdpCfg
+ 0x1005f20b 0x1c _L1w_DrvRfcDagcCfg
+ 0x1005f227 0x13 _L1w_DrvRfcDcCfg
+ 0x1005f23a 0xd _L1w_DrvRfcFcCordicCfg
+ 0x1005f247 0x1a _L1w_DrvRfcNotchCordicCfg
+ 0x1005f261 0x21 _L1w_DrvRfcReadNotchCordicAVal
+ 0x1005f282 0xb8 _L1w_DrvRfcNotchRegCfg
+ 0x1005f33a 0x52 _L1w_DrvRfcFastAgcCfg
+ 0x1005f38c 0x4f _L1w_DrvRfcCtrlRamEventInit
+ 0x1005f3db 0x84 _L1w_DrvRfcAbbCsfCtrlRamInit
+ 0x1005f45f 0x21 _L1w_DrvRfcEventTableInit
+ 0x1005f480 0x41 _L1w_DrvRfcReset
+ 0x1005f4c1 0x8f _L1w_DrvRfcGsmIntNotchCalc
+ 0x1005f550 0x73 _L1w_DrvRfcInit
+ 0x1005f5c3 0x9 _L1w_DrvRfcDfeTxInit
+ 0x1005f5cc 0x30 _L1w_DrvRfcTxTone
+ 0x1005f5fc 0x28 _L1w_DrvRfcAfcCwSet
+ 0x1005f624 0x1 _L1w_DrvRfcAfcCwGet
+ 0x1005f625 0x9 _L1w_DrvRfcRestore
+ .text 0x1005f62e 0x1594 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ 0x1005f62e 0x38 _L1w_DrvHsdpaIcReset
+ 0x1005f666 0x2f _L1w_DrvHsdpaIcTpuCfgOver
+ 0x1005f695 0x30 _L1w_DrvHsdpaIcTxTpuCfgOver
+ 0x1005f6c5 0x28 _L1w_DrvHsdpaIcInit
+ 0x1005f6ed 0x12 _L1w_DrvHsdpaIcIntOpen
+ 0x1005f6ff 0x12 _L1w_DrvHsdpaIcIntMask
+ 0x1005f711 0x17 _L1w_DrvHsdpaIcEnable
+ 0x1005f728 0x18 _L1w_DrvHsdpaIcStaticCfg
+ 0x1005f740 0x273 _L1w_DrvHsdpaIcTpuAntPsrCfg
+ 0x1005f9b3 0x1d8 _L1w_DrvHsdpaIcTxTpuAntPsrCfg
+ 0x1005fb8b 0xa9 _L1w_DrvHsdpaIcTpuSubFrmCfg
+ 0x1005fc34 0x97 _L1w_DrvHsdpaIcTxTpuSubFrmCfg
+ 0x1005fccb 0x69 _L1w_DrvHsdpaIcModeEnableCfg
+ 0x1005fd34 0x5b _L1w_DrvHsdpaIcLambdaCfg
+ 0x1005fd8f 0x5b _L1w_DrvHsdpaIcSymModulusRead
+ 0x1005fdea 0x34 _L1w_DrvHsdpaAdrReset
+ 0x1005fe1e 0x18 _L1w_DrvHsdpaAdrInit
+ 0x1005fe36 0x12 _L1w_DrvHsdpaAdrIntOpen
+ 0x1005fe48 0x12 _L1w_DrvHsdpaAdrIntMask
+ 0x1005fe5a 0xd6 _L1w_DrvHsdpaAdrStaticCfg
+ 0x1005ff30 0x83 _L1w_DrvHsdpaAdrInitRcvCfg
+ 0x1005ffb3 0x4b _L1w_DrvHsdpaAdrFcCfg
+ 0x1005fffe 0x10 _L1w_DrvHsdpaAdrEnableCfg
+ 0x1006000e 0x172 _L1w_DrvHsdpaAdrSubFrmCfg
+ 0x10060180 0x10 _L1w_DrvHsdpaAdrHsscchCfg
+ 0x10060190 0x2e _L1w_DrvHsdpaAdrHsdschCfg
+ 0x100601be 0xa _L1w_DrvHsdpaAdrDisable
+ 0x100601c8 0x2d _L1w_DrvHsdpaAdrCltd1Cfg
+ 0x100601f5 0x74 _L1w_DrvHsdpaAdrCirIntRead
+ 0x10060269 0x11 _L1w_DrvHsdpaAdrGetCirDataAddr
+ 0x1006027a 0x20 _L1w_DrvHsdpaAdrCpichIntRead
+ 0x1006029a 0x2e _L1w_DrvHsdpaHsscchReset
+ 0x100602c8 0x21 _L1w_DrvHsdpaHsscchInit
+ 0x100602e9 0x12 _L1w_DrvHsdpaHsscchIntOpen
+ 0x100602fb 0x12 _L1w_DrvHsdpaHsscchIntMask
+ 0x1006030d 0x11 _L1w_DrvHsdpaHsscchStaticCfg
+ 0x1006031e 0x65 _L1w_DrvHsdpaHsscchInitRcvCfg
+ 0x10060383 0x2d _L1w_DrvHsdpaHsscchPart1Cfg
+ 0x100603b0 0x3b _L1w_DrvHsdpaHsscchPart2Cfg
+ 0x100603eb 0x1b _L1w_DrvHsdpaHsscchDisable
+ 0x10060406 0xeb _L1w_DrvHsdpaHsscchPart1IntRead
+ 0x100604f1 0x31 _L1w_DrvHsdpaHsscchPart2IntRead
+ 0x10060522 0x30 _L1w_DrvHsdpaHdtrReset
+ 0x10060552 0x1a _L1w_DrvHdtrTurboReset
+ 0x1006056c 0x1b _L1w_DrvHdtrLessTurboReset
+ 0x10060587 0x2e _L1w_DrvHsdpaHdtrInit
+ 0x100605b5 0x12 _L1w_DrvHsdpaHdtrIntOpen
+ 0x100605c7 0x12 _L1w_DrvHsdpaHdtrIntMask
+ 0x100605d9 0x25 _L1w_DrvHsdpaHdtrStaticCfg
+ 0x100605fe 0xa _L1w_DrvHsdpaHdtrInitRcvCfg
+ 0x10060608 0x3b _L1w_DrvHsdpaHdtrDemoduleCfg
+ 0x10060643 0x183 _L1w_DrvHsdpaHdtrDecodeCfg
+ 0x100607c6 0x83 _L1w_DrvHsdpaHdtrHwCfg
+ 0x10060849 0xa _L1w_DrvHsdpaHdtrGetCurCfgSubFrm
+ 0x10060853 0x76 _L1w_DrvHsdpaHdtrIntRead
+ 0x100608c9 0x6 _L1w_DrvHsdpaHdtrGetRamDataAddr
+ 0x100608cf 0x3b _L1w_DrvHsdpaHsdpcchInitSendCfg
+ 0x1006090a 0x39 _L1w_DrvHsdpaHsdpcchAckNackCfg
+ 0x10060943 0x3c _L1w_DrvHsdpaHsdpcchCqiPciCfg
+ 0x1006097f 0x10 _L1w_DrvHsdpaHsdpcchCqiPciCfgEn
+ 0x1006098f 0x10 _L1w_DrvHsdpaHsdpcchDisable
+ 0x1006099f 0x19 _L1w_DrvHsdpaLessStaticCfg
+ 0x100609b8 0x20a _L1w_DrvHsdpaLessCfgAllTb
+ .text 0x10060bc2 0x2951 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ 0x10060bc2 0x2f _L1W_SEND_RST_REQ
+ 0x10060bf1 0x2f _L1W_SEND_INIT_REQ
+ 0x10060c20 0x1d _L1W_RegTpuTS0IntEvent
+ 0x10060c3d 0xc _L1W_ResetTpu
+ 0x10060c49 0x18d _L1W_Reset
+ 0x10060dd6 0x125 _L1W_Init
+ 0x10060efb 0x35 _L1w_SchedMeasRelease
+ 0x10060f30 0x120 _L1W_W_Release
+ 0x10061050 0x1c _L1W_SetSecSchedId
+ 0x1006106c 0x8 _L1W_CampOnSetFlag
+ 0x10061074 0x75 _L1W_CampOnOrReconfig
+ 0x100610e9 0xad _L1W_DchIn1R2RCtrl
+ 0x10061196 0x1e _L1W_Only1RCtrl
+ 0x100611b4 0xa9 _L1W_Sch1R2RAntCtrl
+ 0x1006125d 0xd8 _L1w_TpuAdjScByDchCfgScene
+ 0x10061335 0xa8 _L1W_DlDpchReconfig
+ 0x100613dd 0x1c _L1W_DchRelTpuAdj
+ 0x100613f9 0x6e _L1w_AmtFsmProc
+ 0x10061467 0x89 _L1w_AmtNSTSetUlDpchParm
+ 0x100614f0 0x72 _L1w_AmtNSTSetDlDpchParm
+ 0x10061562 0x5b _L1W_WRelDelayHandle
+ 0x100615bd 0x4af _L1W_PSCommonMsgCtrl
+ 0x10061a6c 0x5 _L1w_HsupaSubIntCallBack
+ 0x10061a71 0x111 _L1W_ReadPSMsg
+ 0x10061b82 0x1d _L1W_RegTpuSubFrmIntEvent
+ 0x10061b9f 0x42 _L1W_SubFrmSchedStateCtrl
+ 0x10061be1 0x1b _L1W_InnerCmd
+ 0x10061bfc 0x55 _L1W_ActiveProcHandler
+ 0x10061c51 0x1f _L1W_ProcSend2PS
+ 0x10061c70 0x34 _L1W_ProcAftSchedHandler
+ 0x10061ca4 0x26f _L1W_RfDevCtrl
+ 0x10061f13 0xa3 _L1W_DlsDevCtrl
+ 0x10061fb6 0x64 _L1W_SlaveSetRFStartEnd
+ 0x1006201a 0x9e _L1W_CommonDevCtrl
+ 0x100620b8 0x1ce _L1W_BeforeTpuAdjHandler
+ 0x10062286 0x19f _L1W_StateChanging
+ 0x10062425 0x8d _L1W_NorSubFrmIntHandle
+ 0x100624b2 0x150 _L1W_FrameInt
+ 0x10062602 0x29 _L1w_SchedResBaseOffUpdate
+ 0x1006262b 0x1a1 _L1W_PichIntHandle
+ 0x100627cc 0xe3 _L1W_PreSyncSleepSched
+ 0x100628af 0x583 _L1W_DevIntHandle
+ 0x10062e32 0x1bd _L1W_DevMeasResultHnd
+ 0x10062fef 0x18d _L1W_DevResultProc
+ 0x1006317c 0x1c2 _L1w_MainTs0Log
+ 0x1006333e 0x12 _L1w_MainSetCloseLog
+ 0x10063350 0x3a _L1w_SchedAntSet
+ 0x1006338a 0x189 _L1w_SchedMainTask
+ .text 0x10063513 0x7c7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_rach.o)
+ 0x10063513 0x36 _L1w_SchedRachProcInit
+ 0x10063549 0x14 _L1w_SchedRachProcReset
+ 0x1006355d 0x9c _L1w_SchedRachProcRanSelSig
+ 0x100635f9 0x52 _L1w_SchedRachFindAvailableAS
+ 0x1006364b 0xab _L1w_SchedRachNeedDeleteRtFrameEndAichSlot
+ 0x100636f6 0x170 _L1w_SchedRachProcRanSelAS
+ 0x10063866 0x49 _L1w_SchedRachProcActive
+ 0x100638af 0x2f _L1w_SchedRachProcDeactive
+ 0x100638de 0xce _L1w_SchedRachConfigRtx
+ 0x100639ac 0xb9 _L1w_SchedRachProcPSCmd
+ 0x10063a65 0x33 _L1w_SchedRachProcL1Cmd
+ 0x10063a98 0x2e _L1w_SchedRachProcPreSched
+ 0x10063ac6 0x4d _L1w_SchedRachProcCfgHandle
+ 0x10063b13 0x27 _L1w_SchedRachAiResultHandle
+ 0x10063b3a 0xea _L1w_SchedRachProcSched
+ 0x10063c24 0x28 _L1w_SchedRachProcSend2PS
+ 0x10063c4c 0x36 _L1w_SchedRachProcL1InnerReq
+ 0x10063c82 0x9 _L1w_SchedRachProcL1InnerAbort
+ 0x10063c8b 0x8 _L1w_SchedRachProcDevFachEnable
+ 0x10063c93 0x1b _L1W_SchedRachProcConfigCheck
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+ 0x1007636d 0xb _L1w_SchedHspaEraInd
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+ .text 0x1007661b 0x341 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fmo.o)
+ 0x1007661b 0x8 _L1w_SchedFmoProcActive
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+ .text 0x10077b2c 0x539 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_tx.o)
+ 0x10077b2c 0x21 _L1w_DevHsupaSetEdpdchReadyTrue
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+ 0x10077d3e 0x24 _L1w_DevHsupaIsNextTtiReady
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+ 0x10077e9c 0x33 _L1w_DevHsupaTxProc
+ 0x10077ecf 0x24 _L1w_DevHsupaSetEhichRcvInf
+ 0x10077ef3 0x20 _L1w_DevHsupaClrEhichRcvInf
+ 0x10077f13 0xa _L1w_DevHsupaSearchEhichRcvInf
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+ 0x10077f34 0xe6 _L1w_DevHsupaIcpIntEdchDataProc
+ 0x1007801a 0x4b _L1w_DevHsupaCpPcTtiInfo
+ .text 0x10078065 0x2a8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_hspa.o)
+ 0x10078065 0x25 _L1w_DevPcHspaReset
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+ 0x10078242 0x69 _L1w_DevPcHsupaStartReqHandle
+ 0x100782ab 0x62 _L1w_DevPcHsupaTtiInfoHandle
+ .text 0x1007830d 0xede T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ 0x1007830d 0x26 _L1w_DevTxRachIndToL1s
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+ 0x10078a25 0xd8 _L1w_DevTxPrachPowerCtrl
+ 0x10078afd 0xc8 _L1w_DevTxPrachCfg
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+ 0x10078d4d 0x5e _L1w_DevTxRaIntHandle
+ 0x10078dab 0x1a _L1w_DevTxPrachClose
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+ 0x10079144 0xa7 _L1w_DevTxPiAiAichIntHandle
+ .text 0x100791eb 0xfa4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ 0x100791eb 0xb _L1w_DevRtxRmReset
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+ 0x10079728 0xa3 _L1w_DevRmCalcUlUncodeRm
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+ 0x10079a38 0xbd _L1w_DevRmCalcDlRmTfcNMax
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+ 0x10079b8c 0x67 _L1w_DevRmCalcDlRmNiMax
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+ 0x1007a0ff 0x25 _L1w_DevRmCalcUlCmRes
+ 0x1007a124 0x6b _L1w_DevRmCalcTfcRes
+ .text 0x1007a18f 0x3fc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_tx.o)
+ 0x1007a18f 0x23 _L1w_DevHsdpaSendPcTtiInfo
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+ 0x1007a374 0x4b _L1w_DevHsdpaSnrCalcCtrl
+ 0x1007a3bf 0x81 _L1w_DevHsdpaCqiSendCtrl
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+ 0x1007a47c 0x4a _L1w_DevHsdpaSaveHsdpcchAckCfg
+ 0x1007a4c6 0x49 _L1w_DevHsdpaSaveHsdpcchCqiCfg
+ 0x1007a50f 0x2a _L1w_DevHsdpaTxInitSendProc
+ 0x1007a539 0x52 _L1w_DevHsdpaTxSubFrmProc
+ .text 0x1007a58b 0x1a89 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ 0x1007a58b 0x9a _L1w_DevHsdpaInitHarqInfo
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+ 0x1007a6bc 0x5f _L1w_DevHsdpaSaveDecodeCfg
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+ 0x1007a89c 0xea _L1w_DevHsdpaTpuCalcCfgPara
+ 0x1007a986 0x153 _L1w_DevHsdpaTxTpuSaveIcPsrCfg
+ 0x1007aad9 0xdc _L1w_DevHsdpaTxTpuCalcCfgPara
+ 0x1007abb5 0x92 _L1w_DevHsdpaTpuSaveScrCodePara
+ 0x1007ac47 0x93 _L1w_DevHsdpaTxTpuSaveScrCodePara
+ 0x1007acda 0x151 _L1w_DevHsdpaSaveAdrIcSubFrmPara
+ 0x1007ae2b 0x6e _L1w_DevHsdpaSaveAdrInitRcvCfg
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+ 0x1007aee0 0xa5 _L1w_DevHsdpaSaveAdrSubFrmCfg
+ 0x1007af85 0x15 _L1w_DevHsdpaIsPart1Valid
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+ 0x1007b0a3 0x96 _L1w_DevHsdpaDchSavePart1IntCfg
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+ 0x1007b3eb 0x97 _L1w_DevHsdpaHsscchTypeAnalyse
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+ 0x1007b6ad 0x2d _L1w_DevHsdpaHdtrCfg
+ 0x1007b6da 0x3e _L1w_DevHsdpaCalcShiftFactor
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+ 0x1007b88b 0x119 _L1w_DevHsdpaPart2IntTraceLog
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+ 0x1007bb01 0x3c _L1w_DevHsdpaRxParaInit
+ 0x1007bb3d 0x5d _L1w_DevHsdpaRxInitRcvProc
+ 0x1007bb9a 0x5f _L1w_DevHsdpaRxIcRstFirstCfg
+ 0x1007bbf9 0xb9 _L1w_DevHsdpaRxSubFrmProc
+ 0x1007bcb2 0xd3 _L1w_DevHsdpaRxPart1IntProc
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+ 0x1007bf15 0xcc _L1w_DevHsdpaRxHdtrIntProc
+ 0x1007bfe1 0x33 _L1w_DevHsdpaRxThDataUpdate
+ .text 0x1007c014 0x297 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ 0x1007c014 0x1c _L1w_DevPcRachReset
+ 0x1007c030 0x1c _L1w_DevPcRachInit
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+ 0x1007c0e7 0x7 _L1w_DevPcPrachPreamblePowerEngGet
+ 0x1007c0ee 0x7b _L1w_DevPcPrachPreamblePowerCtrl
+ 0x1007c169 0xf6 _L1w_DevPcPrachMessagePowerCtrl
+ 0x1007c25f 0x34 _L1w_DevPcPrachStartReqHandle
+ 0x1007c293 0x6 _L1w_DevPcPrachPreambleReqHandle
+ 0x1007c299 0x12 _L1w_DevPcPrachMessageReqHandle
+ .text 0x1007c2ab 0xeba T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ 0x1007c2ab 0x3a _L1w_HsupaCalcLowLim
+ 0x1007c2e5 0x48 _L1w_HsupaFlt2Fix
+ 0x1007c32d 0x21 _L1w_DevHsupaCalcHiFrameOffset
+ 0x1007c34e 0xf _L1w_DevHsupaCalcRgFrameOffset
+ 0x1007c35d 0x46 _L1w_DevHsupaCalcRgHiFrmOffset
+ 0x1007c3a3 0x1f _L1w_DevHsupaIsTtiCntValid
+ 0x1007c3c2 0x14 _L1w_DevHsupaCalcTtiCntMod
+ 0x1007c3d6 0x26 _L1w_DevHsupaIsDlChanFrontByTx
+ 0x1007c3fc 0x3e _L1w_DevHsupaReadRgHi
+ 0x1007c43a 0x20 _L1w_DevHsupaLookUpTtiCm
+ 0x1007c45a 0x15a _L1w_DevHsupaIsRgHiCm
+ 0x1007c5b4 0x15c _L1w_DevHsupaReadAllRgHiInfo
+ 0x1007c710 0x2 _L1w_DevHsupaReadHarqGrant
+ 0x1007c712 0x91 _L1w_DevHsupaHiCombine
+ 0x1007c7a3 0x90 _L1w_DevHsupaRgCombine
+ 0x1007c833 0xaf _L1w_DevHsupaIscpSlotCombine
+ 0x1007c8e2 0x87 _L1w_DevHsupaHiDecisonParam
+ 0x1007c969 0x46 _L1w_DevHsupaNackConfirm
+ 0x1007c9af 0xa5 _L1w_DevHsupaSingleHiDecision
+ 0x1007ca54 0xb2 _L1w_DevHsupaSingleRgDecision
+ 0x1007cb06 0x14 _L1w_DevHsupaMulHiNsrlsDecision
+ 0x1007cb1a 0x73 _L1w_DevHsupaMulRgNsrlsDecision
+ 0x1007cb8d 0x30 _L1w_DevHsupaTtiCnt2HarqId
+ 0x1007cbbd 0x84 _L1w_DevHsupaNsrlsHiCombDecis
+ 0x1007cc41 0x47 _L1w_DevHsupaSrlsHICombDecis
+ 0x1007cc88 0x4d _L1w_DevHsupaSrlsRGCombDecis
+ 0x1007ccd5 0x75 _L1w_DevHsupaGetRlIscp
+ 0x1007cd4a 0xee _L1w_DevHsupaReadAllIscpInfo
+ 0x1007ce38 0x39 _L1w_DevHsupaSingleHiCombDec
+ 0x1007ce71 0x61 _L1w_DevHsupaHiCombAndDecision
+ 0x1007ced2 0x3d _L1w_DevHsupaSingleRgCombDecis
+ 0x1007cf0f 0x75 _L1w_DevHsupaNsrlsRGDecision
+ 0x1007cf84 0x51 _L1w_DevHsupaRgIndProc
+ 0x1007cfd5 0x91 _L1w_DevHsupaCalcDisDlChanEdch
+ 0x1007d066 0xff _L1w_DevHsupaSetHarqInfo
+ .text 0x1007d165 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dma.o)
+ 0x1007d165 0x1 _L1w_DrvDmaReset
+ 0x1007d166 0x1 _L1w_DrvDmaInit
+ 0x1007d167 0x1 _L1w_DrvDmaSingleMemcpy
+ 0x1007d168 0x1 _L1W_DMA_ISR
+ .text 0x1007d169 0x165 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_epch.o)
+ 0x1007d169 0xd5 _L1w_SchedHsdpaPchCfgPSCmd
+ 0x1007d23e 0x43 _L1w_SchedHsdpaPchRelPSCmd
+ 0x1007d281 0x14 _L1w_SchedHsdpaPchPreSched
+ 0x1007d295 0x1 _L1w_SchedHsdpaPchSched
+ 0x1007d296 0x38 _L1w_SchedHsdpaPchSend2PS
+ .text 0x1007d2ce 0x127 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x1007d2ce 0x86 _zPHY_ModemOsProcessInit
+ 0x1007d354 0x38 _zPHY_HwInit
+ 0x1007d38c 0x1 _zPHY_FpgaPlatTopInit
+ 0x1007d38d 0x5 _zPHY_ChipTopRegInit
+ 0x1007d392 0x63 _zPHY_LteaInit
+ .text 0x1007d3f5 0x153 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ 0x1007d3f5 0xe _zPHY_NVInit_PreInit
+ 0x1007d403 0xce _zPHY_NVInit
+ 0x1007d4d1 0x8 _L1e_CmnNvGetUeCategory
+ 0x1007d4d9 0x8 _L1e_CmnNvGetDlMimoCapability
+ 0x1007d4e1 0xa _L1e_CmnNvGetRxAntNum
+ 0x1007d4eb 0xf _L1e_CmnNvGetRxRsrpInterval
+ 0x1007d4fa 0xf _L1e_CmnNvGetRxAntThreshold
+ 0x1007d509 0xa _L1e_CmnNvGetRxN1Timer
+ 0x1007d513 0xa _L1e_CmnNvGetRxN2Timer
+ 0x1007d51d 0x8 _L1e_CmnNvGetLteTempDetectEn
+ 0x1007d525 0x8 _L1e_CmnNvGetLteTxPwrBackoffEn
+ 0x1007d52d 0x8 _L1e_CmnNvGetLteRxRateLimitEn
+ 0x1007d535 0x9 _L1e_CmnNvGetLteCqiThdParam
+ 0x1007d53e 0xa _L1e_CmnNvGetLteRxTiAlgoCtrl
+ .text 0x1007d548 0xd86 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ 0x1007d548 0x1 _zPHY_ErrorHandle
+ 0x1007d549 0x14 _zPHY_GetErrorName
+ 0x1007d55d 0x102 _zPHY_etmtlog_ThreadEntry
+ 0x1007d65f 0x5c _zPHY_VersionInfo
+ 0x1007d6bb 0x41 _L1e_CmnLogUpdateAbsSfn
+ 0x1007d6fc 0xc6 _L1e_CmnLogClearVariableVal
+ 0x1007d7c2 0x1c8 _L1e_CmnLogDlTbCrcAndThroughPut
+ 0x1007d98a 0x3b _L1e_CmnLogStatDlFlowByCc
+ 0x1007d9c5 0x11 _L1e_CmnLogStatDlThroughPut
+ 0x1007d9d6 0x45 _L1e_CmnLogDlDdtrCfgTimes
+ 0x1007da1b 0x45 _L1e_CmnLogDlDdtrIntTimes
+ 0x1007da60 0x86 _L1e_CmnLogStatDlRntiApplyCnt
+ 0x1007dae6 0x52 _L1e_CmnLogStatPcfichChannel
+ 0x1007db38 0x15c _L1e_CmnLogStatPhichChannel
+ 0x1007dc94 0x2a9 _L1e_CmnLogStatPdcchChannel
+ 0x1007df3d 0xa _L1e_CmnLogStatDlCtrlChMonitor
+ 0x1007df47 0x9e _L1e_CmnLogStatDciDecodeInfo
+ 0x1007dfe5 0x42 _L1e_CmnLogGetRxTxBitmap
+ 0x1007e027 0x94 _L1e_CmnLogGetCalcSinrValByCc
+ 0x1007e0bb 0x3 _L1e_CmnLogGetCalcSinrVal
+ 0x1007e0be 0x24 _L1e_CmnLogStatUlFlowByCc
+ 0x1007e0e2 0x37 _L1e_CmnLogStatUlThroughPut
+ 0x1007e119 0x1d _zPHY_GetUlQmMcs
+ 0x1007e136 0x2f _zPHY_GetDlQmMcs
+ 0x1007e165 0xa _zPHY_GetDlSinr
+ 0x1007e16f 0x1d _zPHY_GetUlHarqNack
+ 0x1007e18c 0x22 _zPHY_GetDlHarqNack
+ 0x1007e1ae 0xf _zPHY_GetDlThrougput
+ 0x1007e1bd 0xf _zPHY_GetUlThrougput
+ 0x1007e1cc 0x1a _zPHY_UlResidualBlerCount
+ 0x1007e1e6 0xd _zPHY_AtGetPowerHeadroom
+ 0x1007e1f3 0x9 _zPHY_AtGetPcmax
+ 0x1007e1fc 0x26 _zPHY_AtGetRsrpDbm
+ 0x1007e222 0x2a _zPHY_AtGetRssiDbm
+ 0x1007e24c 0x42 _zPHY_AtGetResidualBlerByCc
+ 0x1007e28e 0x26 _zPHY_AtGetResidualBler
+ 0x1007e2b4 0x1a _zPHY_AtClearVariableVal
+ .text 0x1007e2ce 0xbb9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x1007e2ce 0x117 _zPHY_Tpu_ExtraCheck
+ 0x1007e3e5 0x2a _L1L_TpuAdjCnfMsg
+ 0x1007e40f 0x293 _L1L_TpuCpModeSwitchProc
+ 0x1007e6a2 0x40 _L1L_TpuDevFixedIntRegister
+ 0x1007e6e2 0x3d _L1L_TpuDevTimerUnRegister
+ 0x1007e71f 0x63 _L1L_TpuMicroAdj
+ 0x1007e782 0x7 _L1L_TpuDevMsgDelayMsgTimerRegister
+ 0x1007e789 0x6 _L1L_TpuDevMsgDelayCBTimerRegister
+ 0x1007e78f 0x15 _L1L_TpuDevRelativeMsgTimerRegister
+ 0x1007e7a4 0x13 _L1L_TpuDevRelativeCBTimerRegister
+ 0x1007e7b7 0x36 _L1L_TpuDevMrtrTimeTypeMsgTimerRegister
+ 0x1007e7ed 0x35 _L1L_TpuDevMrtrTimeTypeCBTimerRegister
+ 0x1007e822 0x20 _L1L_TpuSuperSlotGet
+ 0x1007e842 0x21 _L1L_TpuMrtrFormat
+ 0x1007e863 0x1c _L1L_TpuLocalMrtr2FreeMrtr
+ 0x1007e87f 0x1c _L1L_TpuFreeMrtr2LocalMrtr
+ 0x1007e89b 0xb4 _L1L_TpuProUpdateLocalMRTR
+ 0x1007e94f 0xa _L1L_TpuTimeSub
+ 0x1007e959 0x13 _L1L_TpuTimeAdd
+ 0x1007e96c 0x4d _L1L_TpuTs2Time
+ 0x1007e9b9 0x17 _L1L_TpuTime2Ts
+ 0x1007e9d0 0x34 _L1L_TpuMrtrAdd
+ 0x1007ea04 0x40 _L1L_TpuMrtrSub
+ 0x1007ea44 0x443 _zPHY_LTE_TPU_ThreadEntry
+ .text 0x1007ee87 0x677 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ 0x1007ee87 0x40 _zPHY_ecsi_HNoDMA
+ 0x1007eec7 0x1 _zPHY_ecsi_PCellCSI_En
+ 0x1007eec8 0x1 _zPHY_ecsi_SCellCSI_En
+ 0x1007eec9 0x49 _zPHY_ecsi_Init
+ 0x1007ef12 0x2c _zPHY_ecsi_PCellCommParmUpdate
+ 0x1007ef3e 0x9b _zPHY_ecsi_PCellDediParmUpdate
+ 0x1007efd9 0xb7 _zPHY_ecsi_PCellHOParmUpdate
+ 0x1007f090 0xd3 _zPHY_ecsi_MsgResponse
+ 0x1007f163 0x2d _zPHY_ecsi_ctrl_GetNodeTXAttennaNum
+ 0x1007f190 0x8c _zPHY_ecsi_CbResSetGet
+ 0x1007f21c 0x2c _zPHY_ecsi_PerCqiParaGet
+ 0x1007f248 0x23 _zPHY_ecsi_CqiRowAParaCalc
+ 0x1007f26b 0x5c _zPHY_ecsi_PcellCsiRepParaDediGet
+ 0x1007f2c7 0x3f _zPHY_ecsi_ScellCsiRepParaDediGet
+ 0x1007f306 0x12 _zPHY_ecsi_CsiRsParaGet
+ 0x1007f318 0x28 _zPHY_ecsi_CSITimeUpdate
+ 0x1007f340 0xac _zPHY_ecsi_FlowPrint
+ 0x1007f3ec 0x1 _zPHY_ecsi2dl_CHECfg
+ 0x1007f3ed 0xab _zPHY_ecsi_Start
+ 0x1007f498 0x66 _zPHY_ecsi_CSIAThreadEntry
+ .text 0x1007f4fe 0x104d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ 0x1007f4fe 0x26 _L1e_DevDlsGetTbCrc
+ 0x1007f524 0x16 _L1e_DevDlsGetTbCbCrc
+ 0x1007f53a 0x9c _L1e_DevDlsSetDlHarqFlag
+ 0x1007f5d6 0x43 _L1e_DevDlsGetDdtrWorkSf
+ 0x1007f619 0x89 _zPHY_edls_ProCwCrcGeneration
+ 0x1007f6a2 0xfa _zPHY_edls_ProTddCwCrcFeedback
+ 0x1007f79c 0x56 _zPHY_edls_ProFddCwCrcFeedback
+ 0x1007f7f2 0x115 _zPHY_edls_ProHarqFeedbackInfo
+ 0x1007f907 0x11e _zPHY_edls_ProDdtrHbitInt
+ 0x1007fa25 0xb3 _zPHY_edls_ProDdtrIntDtch
+ 0x1007fad8 0xa2 _zPHY_edls_ProDdtrIntSibPch
+ 0x1007fb7a 0x64 _L1e_DbgDlsDecPchInfo
+ 0x1007fbde 0x2d _L1e_DevDlsPageMatch
+ 0x1007fc0b 0x5e _L1e_DevDlsPchMessagePro
+ 0x1007fc69 0x5b _L1e_DevDlsPchReportInd
+ 0x1007fcc4 0x56 _zPHY_edls_ProPchDataProc
+ 0x1007fd1a 0x48 _zPHY_edls_ProSibDataProc
+ 0x1007fd62 0x5b _zPHY_edls_ProPchStatAndPrint
+ 0x1007fdbd 0x53 _zPHY_edls_ProSibStatAndPrint
+ 0x1007fe10 0x75 _zEumacdl_CrExist
+ 0x1007fe85 0x285 _L1e_DevDlsCfgMacPduCtrlInfo
+ 0x1008010a 0x32 _L1e_DevDlsReportMacPdu
+ 0x1008013c 0x1dc _zPHY_edls_ProDschIntThread
+ 0x10080318 0x5c _zPHY_edls_ProMsg2RaRntiMacPdu
+ 0x10080374 0x36 _zPHY_edls_PDschIsr
+ 0x100803aa 0x7f _L1e_DbgDlsAckNakRptInfo
+ 0x10080429 0x122 _L1e_DbgDlsDecStatInfo
+ .text 0x1008054b 0x6f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x1008054b 0x51 _zPHY_edls_ProPdcchIntThread
+ 0x1008059c 0x44 _zPHY_edls_ProMsg4CRntiPdcch
+ 0x100805e0 0x6a _zPHY_edls_DciIsr
+ 0x1008064a 0xc _zPHY_edls_ProSetVoLteTime
+ 0x10080656 0x23 _zLtePsPhy_RemoteMalloc
+ 0x10080679 0x35 _zPHY_edls_ProStoreSpsInfo
+ 0x100806ae 0x17 _L1e_DevDlsRstRxRbBmpReg
+ 0x100806c5 0x42 _L1e_DevDlsRefSenCntPro
+ 0x10080707 0x72 _L1e_DevDlsRefSenPro
+ 0x10080779 0xf _L1e_DevDlsBfInd
+ 0x10080788 0x39 _zPHY_edls_DdtrHwIdleState
+ 0x100807c1 0x25 _L1x_DevDlsInOutJudge
+ 0x100807e6 0x4e _L1e_DbgDlsCommDecInfo
+ 0x10080834 0xce _L1e_DbgDlsDciInfo
+ 0x10080902 0x51 _L1e_DbgDlsDecErr
+ 0x10080953 0x1 _L1e_DbgDlsValidRptInfo
+ 0x10080954 0x58 _zPHY_edls_ProDbgSpsDciDetInfo
+ 0x100809ac 0x291 _zPHY_edls_DbgHarqDdrClose
+ .text 0x10080c3d 0x2d38 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x10080c3d 0x3a _zPHY_erfc_ProSetRamSFNumForLargeAdj
+ 0x10080c77 0x46 _zPHY_erfc_ProGetMeas0RamNum
+ 0x10080cbd 0x37 _zPHY_erfc_ProGetTxRamNum
+ 0x10080cf4 0x34 _zPHY_erfc_ProGetNextSubFrameOffset
+ 0x10080d28 0x96 _zPHY_erfc_SupLteTxEnableCtrl
+ 0x10080dbe 0xc _zPHY_erfc_ProSpecSubfrmCheck
+ 0x10080dca 0x23 _zPHY_erfc_ProTxSendCtrl
+ 0x10080ded 0x25 _zPHY_erfc_SupDFESubframeStartCtl
+ 0x10080e12 0x311 _zPHY_erfc_ProRamCtrl
+ 0x10081123 0x1 _zPHY_erfc_ProPrintProcess
+ 0x10081124 0x27 _zPHY_erfc_ProNotchProCtrl
+ 0x1008114b 0x10 _zPHY_erfc_ProGetFreqBandNum
+ 0x1008115b 0x238 _zPHY_erfc_TDDProRFABB_RxToRx
+ 0x10081393 0xe1 _zPHY_erfc_TDDProRFABB_RxToIdle
+ 0x10081474 0x4c _zPHY_erfc_TDDProRFABB_RxToTx
+ 0x100814c0 0x31 _zPHY_erfc_TDDProRFABB_IdleToTx
+ 0x100814f1 0x2ee _zPHY_erfc_TDDProRFABB_IdleToRx
+ 0x100817df 0x1 _zPHY_erfc_TDDProRFABB_IdleToIdle
+ 0x100817e0 0x30 _zPHY_erfc_TDDProRFABB_TxToIdle
+ 0x10081810 0x108 _zPHY_erfc_TDDProRFABB_TxToRx
+ 0x10081918 0x1 _zPHY_erfc_TDDProRFABB_TxToTx
+ 0x10081919 0x58 _zPHY_erfc_ATSetAndReadRfReg
+ 0x10081971 0x534 _zPHY_erfc_ProRFABBCtrl
+ 0x10081ea5 0xa07 _zPHY_erfc_ProRFABBCtrl_FDD
+ 0x100828ac 0x5b _zPHY_erfc_Pro_IFTempNeedFix
+ 0x10082907 0x343 _zPHY_erfc_ProRFCWork
+ 0x10082c4a 0x58 _zPHY_erfc_ProRxOffsetAutoCtrl
+ 0x10082ca2 0x10 _zPHY_erfc_ProTAOffsetAutoCtrl
+ 0x10082cb2 0x3b8 _zPHY_erfc_ProTxAndRxOffsetCtrl
+ 0x1008306a 0xe _zPHY_erfc_ProRFSDInit
+ 0x10083078 0xa _zPHY_erfc_ProRFCSA_CSRConfig
+ 0x10083082 0xe _zPHY_erfc_ProRFCSA_RXConfig
+ 0x10083090 0xa _zPHY_erfc_ProRFCSA_TXConfig
+ 0x1008309a 0x95 _zPHY_erfc_ProRFSDAndRFCSAInit
+ 0x1008312f 0x4b _zPHY_erfc_RpiCfg
+ 0x1008317a 0x1d _zPHY_erfc_RpiSet
+ 0x10083197 0x5d _zPHY_erfc_RpiPwrCtrl
+ 0x100831f4 0x72 _zPHY_erfc_ProRFCSAInit
+ 0x10083266 0x68 _zPHY_erfc_ProRFCInit
+ 0x100832ce 0x54 _zPHY_erfc_ProRFCInitPointer
+ 0x10083322 0x18d _zPHY_erfc_ProRfsdCheck_FDD
+ 0x100834af 0x3f _zPHY_erfc_CheckNextSccRfcToIdle
+ 0x100834ee 0x17 _zPHY_erfc_ProGetRFCCurrentState
+ 0x10083505 0x1e2 _zPHY_erfc_ThreadEntry
+ 0x100836e7 0x16 _zPHY_erfc_GetRfcMeasStatus
+ 0x100836fd 0x19 _zPHY_erfc_TjpAlgorithm
+ 0x10083716 0x3d _zPHY_erfc_CalcMeasSubfNum
+ 0x10083753 0x3f _zPHY_erfc_CalcSyncSubfNum
+ 0x10083792 0x1a _zPHY_erfc_IntraFrameTimeComp
+ 0x100837ac 0x1 _zPHY_erfc_ProCleanHWTable
+ 0x100837ad 0x47 _zPHY_erfc_LTXTxTaConfig
+ 0x100837f4 0x36 _zPHY_erfc_ProCopyTxPccParaToScc
+ 0x1008382a 0x1 _zPHY_erfc_RXTX_PathTest
+ 0x1008382b 0x27 _zPHY_erfc_MainSlave_InterSwitch
+ 0x10083852 0x5b _zPHY_erfc_GetTxTabAdjust
+ 0x100838ad 0xa _zPHY_erfc_GetFixDlDelay
+ 0x100838b7 0xd _L1l_DevRfcRxOffsetGet
+ 0x100838c4 0xd _L1l_DevRfcTaTimingGet
+ 0x100838d1 0x9 _L1l_DevRfcRatModeSet
+ 0x100838da 0xc _L1l_DevRfcTmpReadEn
+ 0x100838e6 0x81 _L1l_DevRfcTmpReadCtrl
+ 0x10083967 0x7 _L1l_DevRfcSetOffsetFlag
+ 0x1008396e 0x7 _L1l_DevRfcGetOffsetFlag
+ .text 0x10083975 0x2c1d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x10083975 0xf _zPHY_eCSI_Calc_MultiPmiAddr_Init
+ 0x10083984 0x8 _OSMemCopy16
+ 0x1008398c 0x6 _OSMemCopy32
+ 0x10083992 0x23 _IsTM9_PMIRIEn_CSIRS_2_4
+ 0x100839b5 0x16 _IsTM8_PMIRIEn
+ 0x100839cb 0x1a _zPHY_eCSI_Calc_Sort
+ 0x100839e5 0x27 _zPHY_eCSI_Calc_MaxM
+ 0x10083a0c 0x16 _zPHY_eCSI_Calc_CapMaxVal
+ 0x10083a22 0x20 _zPHY_eCSI_Calc_GetSubbandIdx
+ 0x10083a42 0x6c _zPHY_eCSI_Calc_eesm
+ 0x10083aae 0x59 _zPHY_eRLM_Calc_eesm
+ 0x10083b07 0x161 _zPHY_eCSI_Calc_LookupCqiTable
+ 0x10083c68 0x47 _zPHY_eCSI_Calc_WideTotalCapCalc
+ 0x10083caf 0x33 _zPHY_eCSI_Calc_WideTotalCapCalc_PerRI
+ 0x10083ce2 0x8e _zPHY_eCSI_Calc_WideHigh2UESubCap
+ 0x10083d70 0x10c _zPHY_eCSI_Calc_BPMI
+ 0x10083e7c 0x3e _zPHY_eCSI_Calc_SPMI
+ 0x10083eba 0x185 _zPHY_eCSI_Calc_RI_TM3
+ 0x1008403f 0x127 _zPHY_eCSI_Calc_WPMI_TM4_LastRI
+ 0x10084166 0x2d0 _zPHY_eCSI_Calc_RI_WPMI_TM4
+ 0x10084436 0xe5 _zPHY_eCSI_Adjust_RI_PMI
+ 0x1008451b 0x2e4 _zPHY_eCSI_Calc_RI_PMI
+ 0x100847ff 0xd6 _zPHY_eCSI_Calc_WbCQICalc
+ 0x100848d5 0x98 _zPHY_eCSI_Calc_NoPmiGetMsbIdx
+ 0x1008496d 0x82 _zPHY_eCSI_Calc_MsbCqiCalc
+ 0x100849ef 0xc1 _zPHY_eCSI_Calc_SbCqiCalc
+ 0x10084ab0 0x16 _zPHY_eCSI_Calc_Curr_SBSize_Get
+ 0x10084ac6 0xcf _zPHY_eCSI_Calc_BpCqiCalc
+ 0x10084b95 0x6d _zPHY_eCSI_Calc_AperSbCqiUpDown
+ 0x10084c02 0xb7 _zPHY_eCSI_Calc_AperCQI
+ 0x10084cb9 0x9e _zPHY_eCSI_Calc_PerCQI
+ 0x10084d57 0x33 _zPHY_eCSI_Calc_Radio_Monitor
+ 0x10084d8a 0x19 _zPHY_eCSI_Calc_BitReversal
+ 0x10084da3 0xf _zPHY_eCSI_Calc_GetPmiBitNum
+ 0x10084db2 0x13 _zPHY_eCSI_Calc_GetMSubbandDifferentCqiValue
+ 0x10084dc5 0xf _zPHY_eCSI_Calc_GetSubbandDifferentCqiValue
+ 0x10084dd4 0x30 _zPHY_eCSI_CalcMSubbandPosition
+ 0x10084e04 0x18 _zPHY_eCSI_FindDiffCQI
+ 0x10084e1c 0x297 _zPHY_eCSI_PER_BagPack
+ 0x100850b3 0x5ea _zPHY_eCSI_APER_BagPack
+ 0x1008569d 0x29 _zPHY_eCSI_PER_PmiBitLen_Estimate
+ 0x100856c6 0x52 _zPHY_eCSI_APER_PmiBitLen_Estimate
+ 0x10085718 0x1d _zPHY_ecqi_GetLookTableSNR
+ 0x10085735 0x70 _zPHY_ecsi_Calc_Pow10_inDiv10
+ 0x100857a5 0x3e _zPHY_ecsi_Calc_Get_InvRow_feedA
+ 0x100857e3 0x49 _zPHY_ecqi_Calc_Get_InvRowB_lin
+ 0x1008582c 0x243 _zPHY_ecqi_Calc_CSIRltPrint
+ 0x10085a6f 0x8e _zPHY_eCSI_Calc_ParaInitInDedi
+ 0x10085afd 0x211 _zPHY_ecqi_SnrConv
+ 0x10085d0e 0x1 _zPHY_ecqi_CQISnrPrint
+ 0x10085d0f 0x1 _zPHY_ecqi_RlmSnrPrint
+ 0x10085d10 0x1 _zPHY_ecqi_RiCapPrint
+ 0x10085d11 0x60 _zPHY_ecqi_CQIFilter
+ 0x10085d71 0x88 _zPHY_ecqi_Sqrt
+ 0x10085df9 0x126 _zPHY_ecsi_Calc_EstiFormatTransform
+ 0x10085f1f 0x11 _zPHY_ecsi_Calc_LTE_RICapFollowHw0
+ 0x10085f30 0x12 _zPHY_ecsi_Calc_LTE_RICapFollowHw1
+ 0x10085f42 0x16 _zPHY_ecsi_Calc_LTE_RICapFollowHw2
+ 0x10085f58 0x1c _zPHY_ecsi_Calc_LTE_RICapFollowHw4
+ 0x10085f74 0x149 _zPHY_ecsi_Calc_LTE_RICloseLoop
+ 0x100860bd 0x18b _zPHY_ecsi_Calc_LTE_RIOpenLoop
+ 0x10086248 0x90 _zPHY_ecsi_Calc_LTE_2Tx2Rx2LWbPMI
+ 0x100862d8 0xb1 _zPHY_ecsi_Calc_LTE_PeriodWBPmi
+ 0x10086389 0x79 _zPHY_ecsi_Calc_LTE_GetCQICalcFunc
+ 0x10086402 0xab _zPHY_ecsi_Calc_LTE_GetCQISNR
+ 0x100864ad 0x16 _zPHY_ecsi_Calc_LTE_PerCQISNRCalc
+ 0x100864c3 0x94 _zPHY_ecsi_Calc_LTE_AperCQISNRCalc
+ 0x10086557 0x3b _zPHY_ecsi_Calc_LTE_RLMSNRCalc
+ .text 0x10086592 0x1592 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ 0x10086592 0x1b _zPHY_Dl_HwReset
+ 0x100865ad 0x2a0 _zPHY_epbch_ThreadEntry
+ 0x1008684d 0x9a _L1e_Bch_UpdateRxRegs
+ 0x100868e7 0xa _L1e_Bch_ResetProc
+ 0x100868f1 0x19 _L1e_Bch_ClkPowerCtrl
+ 0x1008690a 0x2e _L1e_Bch_JudgeSlavePbch
+ 0x10086938 0x6 _L1e_Bch_GetMaxAntCnt
+ 0x1008693e 0x1b _L1e_Bch_BwValid
+ 0x10086959 0x10 _L1e_Bch_AntValid
+ 0x10086969 0x7 _L1e_Bch_FrmTyeValid
+ 0x10086970 0x7 _L1e_Bch_SpecPatValid
+ 0x10086977 0x8e _L1e_Bch_UpdateDb
+ 0x10086a05 0x72 _L1e_Bch_CellSync
+ 0x10086a77 0x2b _L1e_Bch_UpRxCtrlOps
+ 0x10086aa2 0x8 _L1e_Bch_ClrSyncOps
+ 0x10086aaa 0x7 _L1e_Bch_QuerySyncOps
+ 0x10086ab1 0x45 _L1e_Bch_PreDecProc
+ 0x10086af6 0x3f _L1e_Bch_UpRxState
+ 0x10086b35 0x2d _L1e_Bch_InitAllGVar
+ 0x10086b62 0x2a _L1e_Bch_AddSpecTpuEvt
+ 0x10086b8c 0x2d _L1e_Bch_DelAllTpuEvt
+ 0x10086bb9 0x1d _L1e_Bch_DelSpecTpuEvt
+ 0x10086bd6 0x1a _L1e_Bch_QueryTpuEvt
+ 0x10086bf0 0x31 _L1e_Bch_CalStartAddr
+ 0x10086c21 0x1b _L1e_Bch_GetTpuOffset
+ 0x10086c3c 0x43 _L1e_Bch_CalBodryDis
+ 0x10086c7f 0x1c _L1e_Bch_RegRxNewFrmEvt
+ 0x10086c9b 0x1 _L1e_Bch_SaveRfcSyncTable
+ 0x10086c9c 0x5e _L1e_Bch_UpRfcCfg
+ 0x10086cfa 0x39 _L1e_Bch_RegTpuAdjEvt
+ 0x10086d33 0x86 _L1e_Bch_InitBchRegFile
+ 0x10086db9 0x72 _L1e_Bch_GenRxRsScrm
+ 0x10086e2b 0xc9 _L1e_Bch_InitRxRegFile
+ 0x10086ef4 0x6e _L1e_Bch_GetSfnOffset
+ 0x10086f62 0x5d _L1e_Bch_StopMibProc
+ 0x10086fbf 0x64 _L1e_Bch_Decode
+ 0x10087023 0x89 _L1e_Bch_RltReport
+ 0x100870ac 0x11 _L1e_Bch_StartMib
+ 0x100870bd 0xe _L1e_Bch_GetMibIntCnt
+ 0x100870cb 0x2b _L1e_Bch_ModifyParaForBldDetect
+ 0x100870f6 0x2a _L1e_Bch_StartAnr
+ 0x10087120 0x45 _L1e_Bch_AnrDecPorc
+ 0x10087165 0xa7 _L1e_Bch_FrmIntCheck
+ 0x1008720c 0xc _L1e_Bch_FristBchFrm
+ 0x10087218 0xe2 _L1e_Bch_NewFrmDecPorc
+ 0x100872fa 0x1a _L1e_Bch_EnableSF0RxRcv
+ 0x10087314 0x9a _L1e_Bch_AdjTpuTime
+ 0x100873ae 0x18 _L1e_Bch_GetMibResult
+ 0x100873c6 0x14 _L1e_Bch_CalcInitFrm
+ 0x100873da 0x1c _L1e_Bch_MibInfoCheck
+ 0x100873f6 0x3a _L1e_Bch_HandleCrcResult
+ 0x10087430 0x18 _L1e_Bch_NxtBranchCtrl
+ 0x10087448 0xf0 _L1e_Bch_StartNxtDecode
+ 0x10087538 0x66 _L1e_Bch_DecideNxtDecode
+ 0x1008759e 0x5c _L1e_Bch_IntHandle
+ 0x100875fa 0x49 _L1e_Bch_SaveDlapara
+ 0x10087643 0x47 _L1e_Bch_ResumeDlapara
+ 0x1008768a 0x53 _L1e_Bch_GetNCellRsNullInd
+ 0x100876dd 0x2e _L1e_Bch_GetNCellRsNullValid
+ 0x1008770b 0x17 _L1e_Bch_WriteIntraMeasResult
+ 0x10087722 0x90 _L1e_Bch_GetIntraMeasResult
+ 0x100877b2 0x6f _L1e_Bch_SortIntraMeasResult
+ 0x10087821 0x8 _L1e_Bch_GetMibProc
+ 0x10087829 0x6d _L1e_Bch_Performance
+ 0x10087896 0x17 _L1e_Bch_ErrorMoniter
+ 0x100878ad 0xc4 _L1e_Bch_RxRsrpMoniter
+ 0x10087971 0x38 _L1e_Bch_MibReqMonitor
+ 0x100879a9 0x59 _L1e_Bch_RfcTpuMonitor
+ 0x10087a02 0x67 _L1e_Bch_IntRptMonitor
+ 0x10087a69 0x6c _L1e_Bch_CrcRltMonitor
+ 0x10087ad5 0x32 _L1e_Bch_RxParaMonitor
+ 0x10087b07 0x1d _L1e_Bch_SerPbchRead
+ .text 0x10087b24 0x9e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x10087b24 0x7b _zPHY_edls_DlHarqReport
+ 0x10087b9f 0x35 _zPHY_edls_ProDlHarqInit
+ 0x10087bd4 0x6d _zPHY_edls_ProGvInit
+ 0x10087c41 0x8c _zPHY_edls_ProCommDlschParaInit
+ 0x10087ccd 0x42 _zPHY_edls_ProSwInit
+ 0x10087d0f 0xc _zPHY_edls_ProMcReleaseMsg
+ 0x10087d1b 0x4c _zPHY_edls_ProMsg4AckFeedback
+ 0x10087d67 0xc _zPHY_edls_ProMcResetMsg
+ 0x10087d73 0x23 _zPHY_edls_ProMcMacResetMsg
+ 0x10087d96 0x27 _zPHY_edls_CheckHarqGroupNum
+ 0x10087dbd 0x116 _zPHY_edls_ThreadEntry
+ 0x10087ed3 0x4a _zPHY_edls_ProCommDlschParaCal
+ 0x10087f1d 0x1 _L1e_DevDlsDdtrAxiReset
+ 0x10087f1e 0x1 _L1e_DevDlsProcAxiReset
+ 0x10087f1f 0xbe _L1e_DevDlsUeRacpParamInit
+ 0x10087fdd 0x4b _L1e_DevDlsDecoderInit
+ 0x10088028 0x3e _L1e_DevDlsHarqHwInit
+ 0x10088066 0x6c _L1e_DevDlsDdtrHwInit
+ 0x100880d2 0x17 _L1e_DevDlsRxTMIndCfg
+ 0x100880e9 0x1f _L1e_DevDlsSpsParamCfg
+ 0x10088108 0x45 _L1e_DevDlsCsiRsParamCfg
+ 0x1008814d 0x6d _L1e_DevDlsProcCommonMsg
+ 0x100881ba 0x5e _L1e_DevDlsProcDedicatedMsg
+ 0x10088218 0xa5 _L1e_DevDlsProcHandoverMsg
+ 0x100882bd 0x8 _zPHY_edls_ProSetSpsMode
+ 0x100882c5 0x8 _zPHY_edls_ProGetSpsMode
+ 0x100882cd 0xe _L1e_DevDlsSetTimeInfo
+ 0x100882db 0xd _L1e_DevDlsSetCellParam1
+ 0x100882e8 0xd _L1e_DevDlsSetCellparam2
+ 0x100882f5 0xd _L1e_DevDlsSetRntiInfo
+ 0x10088302 0xf _L1e_DevDlsGetTimeInfo
+ 0x10088311 0x1a _L1e_DevDlsGetCellParam1
+ 0x1008832b 0x1a _L1e_DevDlsGetCellParam2
+ 0x10088345 0x1a _L1e_DevDlsGetRntiInfo
+ 0x1008835f 0x19 _L1e_DevDlsSetDciF1aPld
+ 0x10088378 0x10 _L1e_DevDlsSetDciF1cPld
+ 0x10088388 0x10 _L1e_DevDlsSetDciFxxPld
+ 0x10088398 0xe _L1e_DevDlsSetDciCifSize
+ 0x100883a6 0xe _L1e_DevDlsSetDciRaHeaderSize
+ 0x100883b4 0x10 _L1e_DevDlsSetDciRbaSize
+ 0x100883c4 0xe _L1e_DevDlsSetDciHarqIdSize
+ 0x100883d2 0xe _L1e_DevDlsSetDciDaiSize
+ 0x100883e0 0xe _L1e_DevDlsSetDciTpmiSize
+ 0x100883ee 0xe _L1e_DevDlsSetDciScidSize
+ 0x100883fc 0xe _L1e_DevDlsSetDciSrsReqSize
+ 0x1008840a 0x1a _L1e_DevDlsGetDciF1aPld
+ 0x10088424 0x10 _L1e_DevDlsGetDciF1cPld
+ 0x10088434 0x10 _L1e_DevDlsGetDciFxxPld
+ 0x10088444 0xd _L1e_DevDlsGetDciCifSize
+ 0x10088451 0xd _L1e_DevDlsGetDciRaHeaderSize
+ 0x1008845e 0x11 _L1e_DevDlsGetDciRbaSize
+ 0x1008846f 0xd _L1e_DevDlsGetDciHarqIdSize
+ 0x1008847c 0xd _L1e_DevDlsGetDciDaiSize
+ 0x10088489 0xd _L1e_DevDlsGetDciTpmiSize
+ 0x10088496 0xd _L1e_DevDlsGetDciScidSize
+ 0x100884a3 0xd _L1e_DevDlsGetDciSrsReqSize
+ 0x100884b0 0x8 _L1e_DevDlsDdtrUpdateCntCbInit
+ 0x100884b8 0xc _L1e_DevDlsDdtrUpdateCntInc
+ 0x100884c4 0xc _L1e_DevDlsDdtrUpdateCntClr
+ 0x100884d0 0x9 _L1e_DevDlsGetDdtrCcUpdateCnt
+ 0x100884d9 0x7 _L1e_DevDlsGetDdtrUpdateCnt
+ 0x100884e0 0x7 _L1e_DevDlsSetMsg4RaConflictCnt
+ 0x100884e7 0x7 _L1e_DevDlsGetMsg4RaConflictCnt
+ 0x100884ee 0x9 _L1e_DevDlsMsg4RaConflictCntDec
+ 0x100884f7 0x8 _L1e_DevDlsMsg4RaConflictCntClr
+ 0x100884ff 0x8 _L1e_DevDlsGetTransMode
+ .text 0x10088507 0xbf2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ 0x10088507 0x69 _zPHY_ecsi_ctrl_Init
+ 0x10088570 0x80 _zPHY_ecsi_StaticBandParaUpdata
+ 0x100885f0 0x28 _zPHY_ecsi_ctrl_PeriodParaUpdate
+ 0x10088618 0x7a _zPHY_ecsi_ctrl_AperiodParaUpdate
+ 0x10088692 0x7d _zPHY_ecsi_ctrl_AperRepJudge
+ 0x1008870f 0x3f _zPHY_ecsi_ctrl_GetSubbandIdx
+ 0x1008874e 0x51 _zPHY_ecsi_ctrl_CqiPmiConfigIndexCalcTDD
+ 0x1008879f 0x57 _zPHY_ecsi_ctrl_CqiPmiConfigIndexCalcFDD
+ 0x100887f6 0x32 _zPHY_ecsi_ctrl_RiConfigIndexCalc
+ 0x10088828 0x6b _zPHY_ecsi_ctrl_GetPeriodPara
+ 0x10088893 0x14a _zPHY_ecsi_ctrl_GetPeriodRepType
+ 0x100889dd 0xcb _zPHY_ecsi_ctrl_LastRIInit
+ 0x10088aa8 0x4a _zPHY_ecsi_ctrl_GetMaxLayerNum
+ 0x10088af2 0x71 _zPHY_ecsi_ctrl_SecondCfg
+ 0x10088b63 0x8 _zPHY_ecsi_ctrl_SentCqiRlmProMsg
+ 0x10088b6b 0xc _zPHY_ecsi_ctrl_RlmProEn
+ 0x10088b77 0x87 _zPHY_ecsi_ctrl_FirIntPrint
+ 0x10088bfe 0xa9 _zPHY_ecsi_ctrl_FdBkFirst_IntIsr
+ 0x10088ca7 0x1e _zPHY_ecsi_ctrl_FdBkSecond_IntIsr
+ 0x10088cc5 0x1b _zPHY_ecsi_ctrl_FdBk_IntIsr
+ 0x10088ce0 0x5c _zPHY_ecsi_ctrl_First_GetEnStep1
+ 0x10088d3c 0x69 _zPHY_ecsi_ctrl_FdBkFirCfgAper
+ 0x10088da5 0xbd _zPHY_ecsi_ctrl_FdBkFirCfgPer
+ 0x10088e62 0xcd _zPHY_ecsi_ctrl_First_FdBkCfg
+ 0x10088f2f 0x3a _zPHY_ecsi_ctrl_ULGetCSI_Callback
+ 0x10088f69 0x71 _zPHY_ecsi_Ctrl_CqiRlmCalc
+ 0x10088fda 0x2f _zPHY_ecsi_ctrl_PreBagPack
+ 0x10089009 0x33 _zPHY_ecsi_ctrl_FindPreDlSfn
+ 0x1008903c 0xbd _zPHY_ecsi_ctrl_DrxRfZspCtrl
+ .text 0x100890f9 0x1aac T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ 0x100890f9 0x7 _L1e_DevRxGetAveSinr
+ 0x10089100 0x1d _zPHY_erxp_convert_RbNum_to_BWIdx
+ 0x1008911d 0x7 _L1e_DevRxCirSetIdleAccessReqInd
+ 0x10089124 0x7 _L1e_DevRxCirGetIdleAccessReqInd
+ 0x1008912b 0x1b2 _zPHY_erxph_ThreadEntry
+ 0x100892dd 0x173 _L1e_DevRxPowerPrepare
+ 0x10089450 0x55 _L1e_DevRxGetSnrFilterFactor
+ 0x100894a5 0xa0 _zPHY_erxp_PowerFilterInit
+ 0x10089545 0x97 _zPHY_erxp_ProPowerFilter
+ 0x100895dc 0x149 _zPHY_erxp_ProSnrMake
+ 0x10089725 0x64 _zPHY_erxp_ProSnrDB
+ 0x10089789 0x54 _zPHY_erxp_ProLog2
+ 0x100897dd 0x19e _L1e_DevRxProcPwrNbnb
+ 0x1008997b 0x8a _L1e_DevRxCalcRsrpPwr
+ 0x10089a05 0x36 _L1e_DevRxProcSnrPwrFilter
+ 0x10089a3b 0x50 _L1e_DevRxCalcLinearSnr
+ 0x10089a8b 0x3e _L1e_DevRxCalcLinearSinr
+ 0x10089ac9 0x5c _L1e_DevRxConvertSnrDbValue
+ 0x10089b25 0x88 _L1e_DevRxCalcAveSnr
+ 0x10089bad 0xa _L1e_DevRxGetAveSnr
+ 0x10089bb7 0xa _L1e_DevRxGetNeiAveSnr
+ 0x10089bc1 0x14 _L1e_DevRxCalSign
+ 0x10089bd5 0xa6 _L1e_DevRxCalcMod
+ 0x10089c7b 0x6e _L1e_DevRxDbgMsgRxCrsPwr
+ 0x10089ce9 0x91 _L1e_DevRxDbgMsgRxDrsPwr
+ 0x10089d7a 0x56 _L1e_DevRxDbgMsgRxSnrInfo
+ 0x10089dd0 0x81 _L1e_DevRxDbgMsgSyncInfo
+ 0x10089e51 0x48 _L1e_LogDevRxMbsfnCsiInfo
+ 0x10089e99 0x54 _L1e_DevRxDbgMsgRxHResult
+ 0x10089eed 0x54 _L1e_DevRxDbgMsgRxPrbN0
+ 0x10089f41 0x17 _L1e_DevRxExpInfo
+ 0x10089f58 0x1c _L1e_DevRxRssiRead
+ 0x10089f74 0x2b _L1e_DevRxRspRead
+ 0x10089f9f 0x25 _L1e_DevRxRsrpRead
+ 0x10089fc4 0x43 _L1e_DevRxN0Read
+ 0x1008a007 0x15 _L1e_DevRxMrsN0Read
+ 0x1008a01c 0x7a _L1e_DevRxGetRxLogInfo
+ 0x1008a096 0x20 _L1e_DevRxGetDfeAgcGain
+ 0x1008a0b6 0x14 _L1e_DevRxGetRxAntNum
+ 0x1008a0ca 0x7 _L1e_DevRxSetSingleAntInd
+ 0x1008a0d1 0x7 _L1e_DevRxGetSingleAntInd
+ 0x1008a0d8 0x9 _L1e_DevRxSetNbNbSinrCalInd
+ 0x1008a0e1 0x9 _L1e_DevRxGetNbNbSinrCalInd
+ 0x1008a0ea 0x9 _L1e_DevRxSetDrsAccNum
+ 0x1008a0f3 0x9 _L1e_DevRxGetDrsAccNum
+ 0x1008a0fc 0x9 _L1e_DevRxSetBfDagcFlag
+ 0x1008a105 0x9 _L1e_DevRxGetBfDagcFlag
+ 0x1008a10e 0x5f _L1e_DevRxProcBfDagcFlag
+ 0x1008a16d 0x7 _L1e_DevRxPrintCtrlCfg
+ 0x1008a174 0x7 _L1e_DevRxPrintCtrlGet
+ 0x1008a17b 0x9 _L1e_DevRxPrintCtrlCnt
+ 0x1008a184 0x22c _L1e_DevRxCalcCsi
+ 0x1008a3b0 0x11c _L1e_DevRxCsiLog
+ 0x1008a4cc 0xe _L1e_DevRxSetAntChangeInd
+ 0x1008a4da 0xd _L1e_DevRxGetAntChangeInd
+ 0x1008a4e7 0xb4 _zPHY_erxp_RX_DFE_UERS
+ 0x1008a59b 0x10 _zPHY_erxp_RX_SNR
+ 0x1008a5ab 0xe _L1e_DevRxSetCfoWorkInd
+ 0x1008a5b9 0xd _L1e_DevRxGetCfoWorkInd
+ 0x1008a5c6 0x1f _L1e_DevRxSetSinrInd
+ 0x1008a5e5 0x10 _L1e_DevRxGetSinrInd
+ 0x1008a5f5 0x2b _L1e_DevRxGetLowSinrInd
+ 0x1008a620 0x11 _L1e_DevReadSnr
+ 0x1008a631 0x8 _L1e_DevRxClearFilterInd
+ 0x1008a639 0x42 _L1e_DevGetNeiBorCellMaxSnr
+ 0x1008a67b 0x7 _L1e_DevRxGetCellComponState
+ 0x1008a682 0x7 _L1e_DevRxSetCellComponState
+ 0x1008a689 0x7 _L1e_DevRxSetAdaptAntProcInd
+ 0x1008a690 0x7 _L1e_DevRxGetAdaptAntProcInd
+ 0x1008a697 0xaa _L1e_DevRxAdaptAntProc
+ 0x1008a741 0x44 _L1e_DevRxAdaptAntResult
+ 0x1008a785 0x3a _L1e_DevRxAdaptAntUpdate
+ 0x1008a7bf 0x36 _L1e_DevRxAdaptSinrAcc
+ 0x1008a7f5 0x101 _L1e_DevRxAdaptCalSinr
+ 0x1008a8f6 0x34 _L1e_DevRxAdaptAgcGainAcc
+ 0x1008a92a 0x10 _L1e_DevRxAdaptGetAveResult
+ 0x1008a93a 0x8 _L1e_DevRxAdaptGetRsrpRange
+ 0x1008a942 0x58 _L1e_DevRxAdaptSetRsrpInterval
+ 0x1008a99a 0x13 _L1e_DevRxClrAdaptAntInfo
+ 0x1008a9ad 0xa _L1e_DevRxAdaptBetaUpdate
+ 0x1008a9b7 0x26 _L1e_DevRxAdaptJudge
+ 0x1008a9dd 0xa _L1e_DevRxIncN1Timer
+ 0x1008a9e7 0x8 _L1e_DevRxGetN1Timer
+ 0x1008a9ef 0x9 _L1e_DevRxClrN1Timer
+ 0x1008a9f8 0x8 _L1e_DevRxSetN1StartInd
+ 0x1008aa00 0x8 _L1e_DevRxGetN1StartInd
+ 0x1008aa08 0xa _L1e_DevRxIncN2Timer
+ 0x1008aa12 0x9 _L1e_DevRxClrN2Timer
+ 0x1008aa1b 0x8 _L1e_DevRxGetN2Timer
+ 0x1008aa23 0x8 _L1e_DevRxSetN2StartInd
+ 0x1008aa2b 0x8 _L1e_DevRxGetN2StartInd
+ 0x1008aa33 0x8 _L1e_DevRxSetAdaptStartInd
+ 0x1008aa3b 0xa _L1e_DevRxGetDLTimer
+ 0x1008aa45 0x8 _L1e_DevRxGetAdaptStartInd
+ 0x1008aa4d 0x8 _L1e_DevRxGetAdaptResult
+ 0x1008aa55 0x8 _L1e_DevRxSetAdaptResult
+ 0x1008aa5d 0x8 _L1e_DevRxSetAdaptChangeInd
+ 0x1008aa65 0x8 _L1e_DevRxGetAdaptChangeInd
+ 0x1008aa6d 0x64 _L1e_DevRxDbgAdptAntInfo
+ 0x1008aad1 0x6f _L1e_DevRxDbgAdptchangeInfo
+ 0x1008ab40 0x65 _L1e_DevRxAntInfoGetForTool
+ .text 0x1008aba5 0x1d43 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x1008aba5 0x69 _zPHY_LteaSysInfoPrint
+ 0x1008ac0e 0x1d _L1L_elpc_Dvfs
+ 0x1008ac2b 0x107 _zPHY_elpc_LtePhyTaskStateInfo
+ 0x1008ad32 0x9 _zPHY_elpc_SetCfunFlg
+ 0x1008ad3b 0x42 _zPHY_elpc_SetLteCamonFlag
+ 0x1008ad7d 0x22 _zPHY_elpc_SetLteConnectFlag
+ 0x1008ad9f 0x28 _zPHY_elpc_SetIratGapReportFlag
+ 0x1008adc7 0x19 _L11_DrvLpcModemIntCtrl
+ 0x1008ade0 0xe _zPHY_elpc_SetlLtePhySleepFlag
+ 0x1008adee 0x1f _zPHY_elpc_LteIdleTaskStateCtrl
+ 0x1008ae0d 0x264 _zPHY_elpc_UpdateLteSubFrameNum
+ 0x1008b071 0x24 _L1L_UpdateAwakeTimer
+ 0x1008b095 0x1e _L1L_SetAwakeTimer
+ 0x1008b0b3 0xc _L1L_IsAwakeTimerEnable
+ 0x1008b0bf 0x38 _zPHY_elpc_ProKeepAwakeTimer
+ 0x1008b0f7 0x87 _zPHY_elpc_ProSleepTimer
+ 0x1008b17e 0x33 _L1_TdSleepInfoPrint
+ 0x1008b1b1 0x18 _zPHY_eLpc_GetLpm32KCALIPara
+ 0x1008b1c9 0x339 _L1_CpuPhySleepInfo
+ 0x1008b502 0x34 _L1L_PrintPwrCtrlInfo
+ 0x1008b536 0x29 _L1L_PrintModemClkCtrlInfo
+ 0x1008b55f 0x8e _zPHY_elpc_LpmCalibrationLog
+ 0x1008b5ed 0x50 _zPHY_elpc_GetLpmCaliIdx
+ 0x1008b63d 0x7e _zPHY_elpc_LpmCalibrationProc
+ 0x1008b6bb 0x11 _zPHY_elpc_LpmCalibrationParaUpdate
+ 0x1008b6cc 0x40 _zPHY_eLpc_RecordTpuMrtrForCaliTest
+ 0x1008b70c 0xf _zPHY_elpc_IsRfStateIdle
+ 0x1008b71b 0x1 _zPHY_elpc_RficSccSleepCtrl
+ 0x1008b71c 0x63 _zPHY_eLpc_Lpm32KCALIInfor
+ 0x1008b77f 0xf1 _zPHY_eLpc_PintCpuAxiFreq
+ 0x1008b870 0x17 _zPHY_eLpc_PrintIcpResult
+ 0x1008b887 0x19b _zPHY_eLpc_ChipCfgInfor
+ 0x1008ba22 0x8e _zPHY_eLpc_TimeSysInfo
+ 0x1008bab0 0x4b4 _zPHY_elpc_CaliTempCompensate
+ 0x1008bf64 0xb _L1L_eLpc_AsynMsgProc
+ 0x1008bf6f 0x2c1 _L1L_elpc_WakeupMsgFlow
+ 0x1008c230 0x23a _L1L_elpc_LpmWakeupFlow
+ 0x1008c46a 0x94 _L1L_LPInit
+ 0x1008c4fe 0x2 _zPHY_elpc_Init
+ 0x1008c500 0x6d _L1L_LpcCfgSocWkupInt
+ 0x1008c56d 0x14 _L1L_LpcDisSocWkupInt
+ 0x1008c581 0x15 _L1L_WakeupIsr
+ 0x1008c596 0x2b4 _L1L_ModemLpcSleep
+ 0x1008c84a 0x9e _L1L_ModemLpcWakeup
+ .text 0x1008c8e8 0xfab T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x1008c8ea 0x3d _zPHY_erfc_DrvCheckNVBandWithRFBand
+ 0x1008c927 0x3b _zPHY_erfc_FindNVBandWithRFBand
+ 0x1008c962 0x3e _zPHY_erfc_DrvCheckTpCompNV
+ 0x1008c9a0 0x2a _zPHY_erfc_SupBinarySearchNv
+ 0x1008c9ca 0xad _zPHY_erfc_SupSampleRateSet
+ 0x1008ca77 0x85 _zPHY_erfc_SupNVBandIndexInit
+ 0x1008cafc 0x1b _zPHY_erfc_SupGlobalVarInit
+ 0x1008cb17 0x18e _zPHY_erfc_InitTableByDma
+ 0x1008cca5 0x1 _zPHY_erfc_SupIntTxTable
+ 0x1008cca6 0x129 _zPHY_erfc_SupIntRFC
+ 0x1008cdcf 0x1e _zPHY_erfc_SupBinarySearchAdc
+ 0x1008cded 0x39 _zPHY_erfc_SupCalcDiffpower
+ 0x1008ce26 0x38 _zPHY_erfc_SupCalcDiffpower7510ACP
+ 0x1008ce5e 0x36 _zPHY_erfc_SupEventRxoffsetEn
+ 0x1008ce94 0x1c _zPHY_erfc_SupTxSymbSend
+ 0x1008ceb0 0xa _zPHY_erfc_SupTxFclkCtrl
+ 0x1008ceba 0x2e _zPHY_erfc_SupDFEFrontEsti
+ 0x1008cee8 0x11 _zPHY_erfc_SupDFEpath0RxControl
+ 0x1008cef9 0x1a _zPHY_erfc_SupDFERxDAGC0estiControl
+ 0x1008cf13 0x27 _zPHY_erfc_SupDFERxRemovCpControl
+ 0x1008cf3a 0x11 _zPHY_erfc_SupDFEpath1Meas0Control
+ 0x1008cf4b 0x1f5 _zPHY_erfc_SupDFEMeas0RemovCpControl
+ 0x1008d140 0x66 _zPHY_erfc_SupDFEMeas0eICICControl
+ 0x1008d1a6 0x21 _zPHY_erfc_SupDFEpath2CellSearchControl
+ 0x1008d1c7 0x2b _zPHY_erfc_SupDFECellSearchDAGC2estiControl
+ 0x1008d1f2 0x1 _zPHY_erfc_SupDFEMeas0DAGC1estiControl
+ 0x1008d1f3 0x3a _zPHY_erfc_SupDFESubframeStart
+ 0x1008d22d 0x14 _zPHY_erfc_SupDFEFrameStart
+ 0x1008d241 0x1 _zPHY_erfc_SupSetTDDFDD
+ 0x1008d242 0x24 _zPHY_erfc_SupEnterLowPower
+ 0x1008d266 0x296 _zPHY_erfc_SupLeaveLowPower
+ 0x1008d4fc 0x1 _zPHY_erfc_SupRfGPIOOpen
+ 0x1008d4fd 0x41 _zPHY_erfc_SupRfRxOpen
+ 0x1008d53e 0x1 _zPHY_erfc_SupRfGPIOClose
+ 0x1008d53f 0x1 _zPHY_erfc_SupRfRxClose
+ 0x1008d540 0x23 _zPHY_erfc_SupRfEnterLightSleep
+ 0x1008d563 0x26 _zPHY_erfc_SupRfEnterDeepSleep
+ 0x1008d589 0x22 _zPHY_erfc_SupRfLeaveLightSleep
+ 0x1008d5ab 0x23 _zPHY_erfc_SupRfLeaveDeepSleep
+ 0x1008d5ce 0x2c _zPHY_erfc_SupRfLeaveSleep
+ 0x1008d5fa 0x24 _zPHY_erfc_SupRfWakeUpRxOpen
+ 0x1008d61e 0x1e _zPHY_erfc_SupRfRxCloseSleep
+ 0x1008d63c 0x4d _zPHY_erfc_SupGetUserNVBandIndex
+ 0x1008d689 0x3a _zPHY_erfc_SupGetCaliNVBandIndex
+ 0x1008d6c3 0x6f _zPHY_erfc_SupNotchEn
+ 0x1008d732 0xa _zPHY_erfc_SupWriteTempCompDacToIram
+ 0x1008d73c 0x157 _zPHY_erfc_SupGetRBESF
+ .text 0x1008d893 0x5f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ 0x1008d893 0x12 _zPHY_ecsrm_ProReset
+ 0x1008d8a5 0x17 _zPHY_ecsrm_InitialGlobalVar
+ 0x1008d8bc 0x55 _zPHY_ecsrm_IsBlackCell
+ 0x1008d911 0x88 _zPHY_ecsrm_BuffGetEveryRfcOpenTime
+ 0x1008d999 0xe3 _zPHY_ecsrm_GetRfcOpenTime
+ 0x1008da7c 0xba _zPHY_ecsrm_GetRfcOpenTimeFddIdle
+ 0x1008db36 0x8 _zPHY_ecsrm_SetDdMode
+ 0x1008db3e 0x94 _zPHY_ecsrm_CfgRfcData
+ 0x1008dbd2 0x2 _zPHY_ecsrm_OnReset
+ 0x1008dbd4 0x4a _zPHY_ecsrm_OnSearchMeasStart
+ 0x1008dc1e 0x12 _zPHY_ecsrm_OnSearchMeasReset
+ 0x1008dc30 0x21 _zEcsm_PreEvent
+ 0x1008dc51 0x38 _L1e_csrm_SfProc
+ 0x1008dc89 0x1fe _zPHY_ecsrm_WriteRfcEventTabNew
+ .text 0x1008de87 0x1eef T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ 0x1008de87 0x3d _zPHY_ecsrm_AveMeasResult
+ 0x1008dec4 0x18 _zPHY_ecsrm_AveValLog
+ 0x1008dedc 0x8 _zPHY_ecsrm_CalSint16ResVal
+ 0x1008dee4 0x2 _zPHY_ecsrm_PointToInt
+ 0x1008dee6 0x21 _zPHY_ecsrm_CalApproValLog
+ 0x1008df07 0x8 _zPHY_ecsrm_ClearMeasResult
+ 0x1008df0f 0xd _zPHY_ecsrm_InitialMeasCommPara
+ 0x1008df1c 0x9 _zPHY_ecsrm_RegistPeriodSfInt
+ 0x1008df25 0xc _L1e_csrm_ClearCurCellInfo
+ 0x1008df31 0xfa _zPHY_ecsrm_JudgeMeasState
+ 0x1008e02b 0x1f _zPHY_escrm_GetFbRelatn
+ 0x1008e04a 0x2b _zPHY_ecsrm_GetRsNumLogIndex
+ 0x1008e075 0x34 _zPHY_ecsrm_CalModVal
+ 0x1008e0a9 0x59 _zPHY_ecsrm_Q8log2
+ 0x1008e102 0x3c _zPHY_ecsrm_Logarithm
+ 0x1008e13e 0x3b _zPHY_ecsrm_GetAntAgcCsrm
+ 0x1008e179 0x17 _zPHY_ecsrm_CfgDfeBandCsr
+ 0x1008e190 0x3b _zPHY_ecsrm_GetAntAgcRx
+ 0x1008e1cb 0x119 _zPHY_ecsrm_ReadRsrpNvInfo
+ 0x1008e2e4 0x19 _zPHY_ecsrm_CalLog
+ 0x1008e2fd 0x25 _zPHY_ecsrm_ReadCaliNvPoint
+ 0x1008e322 0x26 _zPHY_ecsrm_WriteMeasResult
+ 0x1008e348 0xa4 _zPHY_ecsrm_CalRsrpOffset
+ 0x1008e3ec 0x1ee _zPHY_ecsrm_CalRsrpRssi
+ 0x1008e5da 0xe3 _zPHY_ecsrm_CalRsrpForRx
+ 0x1008e6bd 0x18 _zPHY_ecsrm_ReadRealOffet
+ 0x1008e6d5 0xf1 _zPHY_ecsrm_CalSinr
+ 0x1008e7c6 0x9 _zPHY_ecrsm_DelAllTpuInt
+ 0x1008e7cf 0x2e _zPHY_ecsrm_Buffer_TDDMode
+ 0x1008e7fd 0x36 _zPHY_ecsrm_Idle_Buffer_FddMode
+ 0x1008e833 0x29 _zPHY_ecsrm_Idle_FddMode
+ 0x1008e85c 0x2c _zPHY_ecsrm_Idle_FddScheInAny
+ 0x1008e888 0x31 _zPHY_ecsrm_Idle_FddReadInAny
+ 0x1008e8b9 0x26 _zPHY_ecsrm_ClearMeasCellInfo
+ 0x1008e8df 0x40 _zPHY_ecsrm_ClearBuffInfo
+ 0x1008e91f 0x34 _zPHY_ecsrm_half_FrameBoundrySub
+ 0x1008e953 0x25 _zPHY_ecsrm_BuffSlaveHFS
+ 0x1008e978 0x44 _zPHY_ecsrm_BuffSlaveMaxBdySub
+ 0x1008e9bc 0x13 _zPHY_ecsrm_GetCurrCellId
+ 0x1008e9cf 0x97 _zPHY_ecsrm_UpdateResIntoDbNew
+ 0x1008ea66 0x2e _zPHY_ecsrm_ClearMeasResultNew
+ 0x1008ea94 0x5d _zPHY_ecsrm_UpdateMeasResultNew
+ 0x1008eaf1 0x2a _zPHY_ecsrm_Half_Frame_Bdy_Sub
+ 0x1008eb1b 0x25 _zPHY_ecsrm_GetBuffSlaveOpenSfNum
+ 0x1008eb40 0x3d _zPHY_ecsrm_GetBuffMeasSfNum
+ 0x1008eb7d 0x2c _zPHY_ecsrm_GetMeasSfNum
+ 0x1008eba9 0x10a _zPHY_ecsrm_CalRsrpNew
+ 0x1008ecb3 0x29 _zPHY_ecsrm_GetNextSchTime
+ 0x1008ecdc 0x1c _zPHY_ecsrm_ClearMeasSch
+ 0x1008ecf8 0x6a _zPHY_ecsrm_DiscardMeas
+ 0x1008ed62 0x81 _GetMeasInfo
+ 0x1008ede3 0x50 _SetMeasAgeInfo
+ 0x1008ee33 0xbf _zPHY_ecsrm_MeasGetCell
+ 0x1008eef2 0x10e _zPHY_ecsrm_GetCsrmRegParaNew
+ 0x1008f000 0x69 _zPHY_ecsrm_GetDFEBuffFbRelatn
+ 0x1008f069 0xc8 _zPHY_ecsrm_GetDFEBuffRegPara
+ 0x1008f131 0xb7 _zPHY_ecsrm_GetDFECellMeasPara_FDD
+ 0x1008f1e8 0xf7 _zPHY_ecsrm_GetDFECellMeasPara_TDD
+ 0x1008f2df 0x97 _zPHY_ecsrm_HandleCsrHWNormalNew
+ 0x1008f376 0x12 _zPHY_ecsrm_Need_Wait_Cnditon
+ 0x1008f388 0x9d _zPHY_ecsrm_Wait_MeasPeriodProc
+ 0x1008f425 0x9a _zPHY_ecsrm_HandleMeasResultNormalNew
+ 0x1008f4bf 0x123 _zPHY_ecsrm_MeasSeekToWorkTime
+ 0x1008f5e2 0xb _zPHY_ecsrm_OnMeasStart
+ 0x1008f5ed 0x4a _zPHY_ecsrm_MulmGapCheck
+ 0x1008f637 0x162 _zPHY_ecsrm_MeasConfigHw
+ 0x1008f799 0xc0 _zPHY_ecsrm_MeasReadResult
+ 0x1008f859 0x23 _zPHY_ecsrm_BufferScene
+ 0x1008f87c 0x32 _zPHY_ecsrm_CsrFingerSort
+ 0x1008f8ae 0x4 _zPHY_ecsrc_RemoveMrtrFrame
+ 0x1008f8b2 0x58 _zPHY_ecsrm_half_FrameBoundryCenter
+ 0x1008f90a 0x4e _zPHY_ecsrm_GetBdyMeasCell
+ 0x1008f958 0x215 _zPHY_ecsrm_GetMeasmodeAndCell
+ 0x1008fb6d 0x25 _zPHY_ecsrm_GetMeasCellEarfcn
+ 0x1008fb92 0xd3 _eL1_CalCellCfgCont
+ 0x1008fc65 0x2c _zPHY_ecsrm_GetSF0SF5
+ 0x1008fc91 0x2d _zPHY_ecsrm_BeforeBufferMeas
+ 0x1008fcbe 0x95 _zPHY_ecsrm_MeasNextCell
+ 0x1008fd53 0x7 _zPHY_ecsrm_SetCaIndex
+ 0x1008fd5a 0x10 _zPHY_ecsrm_MeasNeedPrimary
+ 0x1008fd6a 0xc _l1e_csrm_GetMeasFalg
+ .text 0x1008fd76 0x31e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ 0x1008fd76 0x1c1 _zPHY_UL_CSI_CombThreadEntry
+ 0x1008ff37 0x15d _zPHY_DLA_ULSL_CombThreadEntry
+ .text 0x10090094 0x1861 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x10090094 0x27 _L1e_DevRxFssSetModIdx
+ 0x100900bb 0xcd _zPHY_eMBMS_CirSearchWinPos_Calc
+ 0x10090188 0x27 _L1e_DevRxDoubleAntCheckOnlyOneValid
+ 0x100901af 0x3d _L1e_DevCirPreSyncAcc
+ 0x100901ec 0x5e _L1e_DevCirPreSyncProtect
+ 0x1009024a 0x43 _zPHY_erxp_CirProc
+ 0x1009028d 0x25 _zPHY_erxp_CirAdjBorderOfSubframe
+ 0x100902b2 0x9 _zPHY_eCir_PccPdsch_DmaCallback
+ 0x100902bb 0x9 _zPHY_eCir_SccPdsch_DmaCallback
+ 0x100902c4 0x9 _zPHY_eCir_PccEicic_DmaCallback
+ 0x100902cd 0x8 _L1e_DevRxSetMbsfnCirIntInt
+ 0x100902d5 0x1a _L1e_DevRxMbmsCirIntProc
+ 0x100902ef 0x44 _L1e_DevRxFssMainAntFlagSet
+ 0x10090333 0xd _L1e_DevRxFssMainAntFlagGet
+ 0x10090340 0xe _L1e_DevRxRefSenDecodeCnt
+ 0x1009034e 0xd _L1e_DevRxRefSenDecodeCntGet
+ 0x1009035b 0xd _L1e_DevRxRefSenDecodeCntClr
+ 0x10090368 0xe _L1e_DevRxRefSenCnt
+ 0x10090376 0xd _L1e_DevRxRefSenCntGet
+ 0x10090383 0xd _L1e_DevRxRefSenCntClr
+ 0x10090390 0xe _L1e_DevRxRefSenIndCfg
+ 0x1009039e 0xd _L1e_DevRxRefSenIndGet
+ 0x100903ab 0x16 _L1e_devRxMrsFIUpdateIndSet
+ 0x100903c1 0x16 _L1e_devRxMrsBetaUpdateIndSet
+ 0x100903d7 0x18 _L1e_devRxMrsFIUpdateIndGet
+ 0x100903ef 0x18 _L1e_devRxMrsBetaUpdateIndGet
+ 0x10090407 0x23 _L1e_devRxMrsFIDataAddrGet
+ 0x1009042a 0x19 _L1e_devRxMrsBetaGet
+ 0x10090443 0x93e _zPHY_eMBMS_CirInitFftSeq
+ 0x10090d81 0xa8 _zPHY_ecir_SW_DynFiRegUdate
+ 0x10090e29 0x135 _zPhy_eMBMS_cir_nomarlize_fir_coeff
+ 0x10090f5e 0x16a _zPHY_ecir_Apply_Triangle_Window
+ 0x100910c8 0xcb _zPhy_ecir_CalcBeta_R01
+ 0x10091193 0x95 _zPHY_erxp_BchNormalCirCtrl
+ 0x10091228 0x23 _zPHY_erxp_CirCfgForBch
+ 0x1009124b 0x577 _L1e_DevRxCirCtrlCfg
+ 0x100917c2 0x63 _L1e_DevRxSetRxOffsetAdjTiMode
+ 0x10091825 0x7 _zPHY_ecir_CellChangeSet
+ 0x1009182c 0xc9 _zPHY_ecir_CellChangeGet
+ *fill* 0x100918f5 0x80000003 00
+ .text 0x100918f8 0x203 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
+ 0x100918f8 0xc4 _zPHY_ecir_Fft256
+ 0x100919bc 0xb _zPhy_ecir_continuous_add
+ 0x100919c7 0x17 _zPhy_ecir_search_max_value
+ 0x100919de 0xa _zPhy_ecir_acquire_fir_coeff
+ 0x100919e8 0x35 _zPhy_eMBMS_cir_midify_nosieEff
+ 0x10091a1d 0x2d _zPhy_ecir_generet_fir_coeff
+ 0x10091a4a 0x37 _zPhy_ecir_midify_nosieEff
+ 0x10091a81 0x7a _Asm_CIR_FIRCoeffNorm
+ .text 0x10091afb 0x55a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ 0x10091afb 0x9 _L1e_DevRxSetRsrpIntInd
+ 0x10091b04 0x9 _L1e_DevRxGetRsrpIntInd
+ 0x10091b0d 0x1f _L1e_DevRxSetServingCellInd
+ 0x10091b2c 0x10b _zPHY_erxp_Cfo_Isr
+ 0x10091c37 0x44 _L1e_DevCFOPreSyncAcc
+ 0x10091c7b 0x4e _L1e_DevCfoFilterCoeffAdapt
+ 0x10091cc9 0x1e _L1e_DevCfoCfgTempRead
+ 0x10091ce7 0x59 _L1e_DevSetCfoCoeffK
+ 0x10091d40 0xfb _L1e_DevGetCfoCoeffK
+ 0x10091e3b 0xa _L1e_DevRxRsrpFilterFlagInit
+ 0x10091e45 0x3f _L1e_DevRxGetRsrpFilterCoeff
+ 0x10091e84 0x116 _zPHY_erxp_CalRsrpFilter
+ 0x10091f9a 0x92 _zPHY_erxp_RsrpFilter
+ 0x1009202c 0xd _L1e_DevRxGetFastCfoConvergenceCnt
+ 0x10092039 0xe _L1e_DevRxSetFastCfoConvergenceCnt
+ 0x10092047 0xe _L1e_DevRxDecreaseFastCfoCnt
+ .text 0x10092055 0x200d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x10092055 0x249 _zPHY_edfe_SupInitDFE
+ 0x1009229e 0x24 _zPHY_edfe_WriteSnrTh
+ 0x100922c2 0x71 _zPHY_edfe_DCOffsetCal
+ 0x10092333 0xea _zPHY_edfe_SupNormalHandleDCOffset
+ 0x1009241d 0xa9 _zPHY_edfe_IQImbaCal
+ 0x100924c6 0x77 _zPHY_edfe_SupHandleIQImba
+ 0x1009253d 0x51 _zPHY_edfe_NormalNotSyncAgcIntHandle
+ 0x1009258e 0x8 _zPHY_edfe_SupInt0Handle
+ 0x10092596 0x14 _zPHY_edfe_SupInt1Handle
+ 0x100925aa 0x15 _zPHY_edfe_SupInt2Handle
+ 0x100925bf 0x39 _zPHY_edfe_ProDfeInt
+ 0x100925f8 0x27 _zPHY_edfe_ConfigRXBandwidth
+ 0x1009261f 0x22 _zPHY_edfe_ConfigCSRMBandwidth
+ 0x10092641 0x7d _zPHY_edfe_CompesateCFO
+ 0x100926be 0x72 _zPHY_edfe_CalMeasTotalAGCGain
+ 0x10092730 0x4c _zPHY_edfe_TotalAGCCsrm
+ 0x1009277c 0x4c _zPHY_edfe_TotalAGCRx
+ 0x100927c8 0x2e _zPHY_edfe_SupResetDfeForRelease
+ 0x100927f6 0xe _zPHY_edfe_RegsTpuIntForDfe
+ 0x10092804 0x91 _zPHY_edfe_RegsTpuIntForDfeCtrl
+ 0x10092895 0x1ab _zPHY_edfe_SupDfeIntCheckCtrl
+ 0x10092a40 0xb4 _zPHY_edfe_PlmnSaveServCellAgcAndDagc
+ 0x10092af4 0x26 _zPHY_edfe_PlmnResumeServCellAgcAndDagc
+ 0x10092b1a 0x76 _zPHY_edfe_PlmnBackUpAgcPara
+ 0x10092b90 0x20 _zPHY_edfe_PlmnResumeAgcAndAfc
+ 0x10092bb0 0xa _zPHY_edfe_ClearPlmnAgcPara
+ 0x10092bba 0x1ed _zPHY_edfe_SupNotSyncAGCInitCtrl
+ 0x10092da7 0x17e _zPHY_edfe_TMTPrintForFreqScan
+ 0x10092f25 0x8d _zPHY_edfe_ConfigAgcWorkState
+ 0x10092fb2 0x1b5 _zPHY_edfe_ConfigAgcCalcPara
+ 0x10093167 0xf6 _zPHY_edfe_SupInitAgcDagcGainDB
+ 0x1009325d 0x5c _zPHY_edfe_SupHandleRxDagcInt
+ 0x100932b9 0x1b0 _zPHY_edfe_SupHandleAgcInt
+ 0x10093469 0x43 _zPHY_edfe_StateChangeSetAgcGain
+ 0x100934ac 0x12a _zPHY_edfe_GetTotalAGCGainOpt
+ 0x100935d6 0x67 _zPHY_edfe_SupCsrcDagcLoseDataCtrl
+ 0x1009363d 0xbe _zPHY_edfe_PhySlaveDfeIntCtrlOpt
+ 0x100936fb 0x2c _zPHY_edfe_TotalSubFramePwr
+ 0x10093727 0x21 _zPHY_edfe_CSRSetFSNewState
+ 0x10093748 0x48 _zPHY_edfe_CSRSetAGCGain
+ 0x10093790 0xfa _zPHY_edfe_SupFSNewSetRF
+ 0x1009388a 0x2d _zPHY_edfe_SupNotSyncAgcIntHandle
+ 0x100938b7 0x72 _zPHY_edfe_FSDCOffsetCal
+ 0x10093929 0x17 _zPHY_edfe_FSDCOffsetClear
+ 0x10093940 0x86 _zPHY_edfe_SupFSHandleDCOffset
+ 0x100939c6 0x12 _zPHY_edfe_SupHandleDCOffset
+ 0x100939d8 0xa9 _zPHY_edfe_SupSingAntNVControl
+ 0x10093a81 0x9 _zPHY_edfe_ConfigSingAnt
+ 0x10093a8a 0x86 _zPHY_edfe_SupCalAGCGainBalance
+ 0x10093b10 0xfa _L1l_DevDfeNotchDbInit
+ 0x10093c0a 0x3 _L1l_DevRfcNotchDbReset
+ 0x10093c0d 0x14 _L1l_DevDfeNotchAgcGainSave
+ 0x10093c21 0x4c _L11_DevDfeNotchBwAndSampRateGet
+ 0x10093c6d 0x186 _L1l_DevDfeNotchStartJudge
+ 0x10093df3 0xd3 _L1l_DevDfeNotchEvtGet
+ 0x10093ec6 0xb7 _L1l_DevDfeNotchRegSet
+ 0x10093f7d 0xc7 _L1l_DevDfeNotchProc
+ 0x10094044 0xb _L1l_DevRfcSemiStaticAgcConvCheck
+ 0x1009404f 0x13 _L1l_DevRfcAgcValGet
+ .text 0x10094062 0x1f9a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ 0x10094062 0xfc _zPHY_eula_Entry
+ 0x1009415e 0xf9 _zPHY_eula_TpuInt1MsgPro
+ 0x10094257 0x9e _zPHY_eula_TpuInt2MsgPro
+ 0x100942f5 0x58e _zPHY_eula_TPU_INT1_process
+ 0x10094883 0x360 _zPHY_eula_TPU_INT2_process
+ 0x10094be3 0x98 _zPHY_eula_ResetDB
+ 0x10094c7b 0x17 _zPHY_eula_ResetReqPro
+ 0x10094c92 0x2d4 _zPHY_eula_HandoverReqPro
+ 0x10094f66 0x160 _zPHY_eula_Release
+ 0x100950c6 0xd7 _zPHY_eula_MACReset
+ 0x1009519d 0x12d _zPHY_eula_ComCfgReqPro
+ 0x100952ca 0x16d _zPHY_eula_CommRelatedParasCalc
+ 0x10095437 0x156 _zPHY_eula_DediCfgReqPro
+ 0x1009558d 0x51 _zPHY_eula_GetScellInfo
+ 0x100955de 0xca _zPHY_eula_DediRelatedParasCalc
+ 0x100956a8 0x169 _zPHY_eula_PSGenAllWithCellID
+ 0x10095811 0x5c _zPHY_eula_FuncHopCalculation
+ 0x1009586d 0x5c _zPHY_eula_FuncHopCalculation_Scell
+ 0x100958c9 0x35 _zPHY_eula_UlBandSampleCoeffCfg
+ 0x100958fe 0x46 _zPHY_eula_SetSampleAndFFT
+ 0x10095944 0x15 _zPHY_eula_GetSysTimeInfo
+ 0x10095959 0x13 _zPHY_eula_GetChannelType
+ 0x1009596c 0x29 _zPHY_eula_GetHarqProcessId
+ 0x10095995 0xe _zPHY_eula_CheckPuschInGap
+ 0x100959a3 0x52 _zPHY_eula_HarqNewTransNoData
+ 0x100959f5 0xb0 _zPHY_eula_UL_Conflict_GAP
+ 0x10095aa5 0x6b _zPHY_eula_HarqSendDataCopy
+ 0x10095b10 0x18 _zPHY_eula_TXInt_Pulse_Isr
+ 0x10095b28 0x13 _zPHY_eula_Isr
+ 0x10095b3b 0x91 _zPHY_eula_lpcHwRestoreBackupCtrl
+ 0x10095bcc 0x2e6 _zPHY_eula_AMTCalcPara
+ 0x10095eb2 0x106 _zPHY_amt_Lte_Tx_Create_CommonMsg
+ 0x10095fb8 0x44 _zPHY_PrintLocalMrtr
+ .text 0x10095ffc 0x121f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ 0x10095ffc 0x1a7 _zPHY_edla_Entry
+ 0x100961a3 0x3e _L1e_Dla_UpBchNormalPara
+ 0x100961e1 0x1f7 _zPHY_edla_CdtrCfgProc
+ 0x100963d8 0x1a2 _zPHY_edla_GetSiRnti
+ 0x1009657a 0x6a _zPHY_edla_QueryDb
+ 0x100965e4 0x1e _zPHY_edla_ProCalYk
+ 0x10096602 0x1a9 _zPHY_edla_GetRntiInfo
+ 0x100967ab 0xa8 _zPHY_edla_GetCellInfo
+ 0x10096853 0x20 _zPHY_edla_GetVcInfo
+ 0x10096873 0x1a _zPHY_edla_ErrorTmGuard
+ 0x1009688d 0x2c _zPHY_edla_SetDefaultTM
+ 0x100968b9 0x2e _zPHY_edla_GetTimingInfo
+ 0x100968e7 0x31 _L1e_DevDlaGetPhichMi
+ 0x10096918 0x1b _zPHY_edla_CommRegParaProc
+ 0x10096933 0xbe _zPHY_edla_CdtrCfgCaApply
+ 0x100969f1 0x24 _zPHY_edla_CdtrCfgApply
+ 0x10096a15 0xf7 _zPHY_edla_InfoCaPrepare
+ 0x10096b0c 0x9 _zPHY_edla_InfoPrepare
+ 0x10096b15 0x4a _zPHY_edla_IndInfoCaSet
+ 0x10096b5f 0x9 _zPHY_edla_IndInfoSet
+ 0x10096b68 0x46 _zPHY_edla_ResetDcb
+ 0x10096bae 0x3e _zPHY_edla_Init
+ 0x10096bec 0x1e _zPHY_edla_HwInit
+ 0x10096c0a 0x1c _zPHY_edla_CacheCtrlReset
+ 0x10096c26 0x3b _zPHY_edla_SaveWorkCachePara
+ 0x10096c61 0x1a _zPHY_edla_UpdateRBGSize
+ 0x10096c7b 0x3d _zPHY_edla_UpdateNGap1
+ 0x10096cb8 0x15 _zPHY_edla_UpdateNrbStep
+ 0x10096ccd 0x8 _zPHY_edla_ResetCommonInfo
+ 0x10096cd5 0xfc _zPHY_edla_UpdateCommonInfo
+ 0x10096dd1 0x55 _zPHY_edla_ProCommReqMsg
+ 0x10096e26 0x60 _zPHY_edla_ProDediReqMsg
+ 0x10096e86 0x56 _zPHY_edla_ProHoReqMsg
+ 0x10096edc 0x24 _zPHY_edla_HoReqEx
+ 0x10096f00 0xd _zPHY_edla_LteAmtUpdateEarfcnInfo
+ 0x10096f0d 0xb _L1e_DevRxInitLpConvergeCb
+ 0x10096f18 0xf _L1e_DevRxSetLpConvergeInd
+ 0x10096f27 0x10 _L1e_DevRxGetLpConvergeInd
+ 0x10096f37 0x10 _L1e_DevRxSetWorkTimer
+ 0x10096f47 0x10 _L1e_DevRxGetWorkTimer
+ 0x10096f57 0x13 _L1e_DevRxIncWorkTimer
+ 0x10096f6a 0x27 _zPHY_edla_DebugPrint
+ 0x10096f91 0x43 _zPHY_edla_ProDbgMsgRecvCommMsg
+ 0x10096fd4 0x43 _zPHY_edla_ProDbgMsgRecvHOMsg
+ 0x10097017 0x43 _zPHY_edla_ProDbgMsgRstRelMacRstMsg
+ 0x1009705a 0x52 _zPHY_edla_ProDbgStateSwitchPrint
+ 0x100970ac 0x3a _zPHY_edla_ProDbgMsgFuncRetErr
+ 0x100970e6 0x77 _zPHY_edla_ProDlCtrlChStatInfoMonitor
+ 0x1009715d 0x25 _zPHY_edla_ProDlCtrlChDecodeMonitor
+ 0x10097182 0x1 _zPHY_edla_ProDlCtrlChConfigMonitor
+ 0x10097183 0x4e _zPHY_edla_PlmnReflashDlaConfig
+ 0x100971d1 0x1a _L1e_DevRxLpcHwRecover
+ 0x100971eb 0x17 _L1e_DevDlaSetDlWorkIndBmp
+ 0x10097202 0xc _L1e_DevDlaGetDlWorkIndBmp
+ 0x1009720e 0xd _L1e_DevDlaGetDlBandWidth
+ .text 0x1009721b 0x2ed3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
+ 0x1009721b 0x1cd _zPHY_eula_ProInitial
+ 0x100973e8 0x68 _zPHY_eula_RegistLutrSymb
+ 0x10097450 0x130 _zPHY_eula_UlDataSendCtrlInfoProcess
+ 0x10097580 0x26a _zPHY_eula_LtxParas_ACKMultiplexing
+ 0x100977ea 0xec _zPHY_eula_LutrLtxParas_RIMultiplexing
+ 0x100978d6 0xb _zPHY_eula_CalcInterMatrixColNumber
+ 0x100978e1 0x93 _zPHY_eula_CalcRMOutputParas
+ 0x10097974 0x8 _zPHY_eula_CalcRMOutputParasForPuschWithoutData
+ 0x1009797c 0xd0 _zPHY_eula_SchdPhichRecInSad
+ 0x10097a4c 0x65 _zPHY_eula_DeterMineHWChanType
+ 0x10097ab1 0x194 _zPHY_eula_LTXParasCalc
+ 0x10097c45 0x2c _zPHY_eula_LtxParas_wNRsZcDmrs
+ 0x10097c71 0x21 _zPHY_eula_LargestPrimeNumber
+ 0x10097c92 0x28 _zPHY_eula_LtxParas_DmrsOCC
+ 0x10097cba 0x71 _zPHY_eula_LtxParas_adwQDivNRsZcDmrs
+ 0x10097d2b 0x28 _zPHY_eula_LtxParas_awNcscell
+ 0x10097d53 0x16 _zPHY_eula_LtxParas_acUPucch
+ 0x10097d69 0x113 _zPHY_eula_LtxParas_PucchFormat1Spec
+ 0x10097e7c 0x232 _zPHY_eula_LtxParas_PucchFormat3Spec
+ 0x100980ae 0x13 _zPHY_eula_LtxParas_dwX2Cinit
+ 0x100980c1 0x3e _zPHY_eula_LtxParas_awNcs2
+ 0x100980ff 0x9e _zPHY_eula_LtxParas_ResMappingPucch
+ 0x1009819d 0x14 _zPHY_eula_711712ClosePsmStub
+ 0x100981b1 0x46c _zPHY_eula_RfcConfigure
+ 0x1009861d 0xe7 _zPHY_eula_LutrRegConfigure
+ 0x10098704 0x3da _zPHY_eula_LtxConfigure
+ 0x10098ade 0x63 _zPHY_eula_LTXTxTaConfig
+ 0x10098b41 0x50 _zPHY_eula_LTXTimingFirstFlag
+ 0x10098b91 0x53 _zPHY_eula_LTXTimingLastFlag
+ 0x10098be4 0x17 _zPHY_eula_ResetSrInfo
+ 0x10098bfb 0x100 _zPHY_eula_SetPuchFilterCoeff1
+ 0x10098cfb 0x66 _zPHY_eula_SetPrachFilterCoeff2
+ 0x10098d61 0x34 _zPHY_eula_SetPucchScale
+ 0x10098d95 0xf _zPHY_eula_GetCsiInfo
+ 0x10098da4 0x2 _zPHY_eula_FDDGetHarqAckInfo
+ 0x10098da6 0x25 _zPHY_euls_GetPucchHarqAckInfo
+ 0x10098dcb 0x83 _zPHY_eula_GetPucchHarqAckLen
+ 0x10098e4e 0xf7 _zPHY_eula_PucchUciProcess
+ 0x10098f45 0x2bc _zPHY_eula_TDD_PucchAckProcess
+ 0x10099201 0x1a _zPHY_eula_FDD_PucchAckProcess
+ 0x1009921b 0x70 _zPHY_eula_PucchCSI
+ 0x1009928b 0x271 _zPHY_eula_PucchAckParasCalc
+ 0x100994fc 0x34 _zPHY_eula_PucchN1pucchCalc
+ 0x10099530 0xaa _zPHY_eula_FDD_PucchAckParasCalc
+ 0x100995da 0x25 _zPHY_eula_PSGeneration
+ 0x100995ff 0x7a _zPHY_eula_SrProcess
+ 0x10099679 0x566 _zPHY_eula_LtxStub
+ 0x10099bdf 0x213 _zPHY_eula_LutrStub
+ 0x10099df2 0x15a _zPHY_eula_UlTwoAntenHWChanTypeDeterm
+ 0x10099f4c 0xc _zPHY_eula_TATimerStop
+ 0x10099f58 0x25 _zPHY_eula_PucchTwoAntenActivedDetermine
+ 0x10099f7d 0x12f _zPHY_eula_NextAckParasProcess
+ 0x1009a0ac 0x3b _zPHY_eula_GetTQCfgFlg
+ 0x1009a0e7 0x7 _zPHY_eula_PucchAntennaSelect
+ .text 0x1009a0ee 0x38e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x1009a0ee 0x2d _zPHY_eintc_IntDispatchProcess_ICP
+ 0x1009a11b 0x47 _zPHY_eintc_EnableInt
+ 0x1009a162 0x50 _zPHY_eintc_ClearInt
+ 0x1009a1b2 0x1c _L1l_DrvTopIntClr
+ 0x1009a1ce 0x46 _zPHY_eintc_InthInit
+ 0x1009a214 0x1a _L1_LTE_LPM_T1_ISR
+ 0x1009a22e 0x1 _zPHY_eintc_NullIsr
+ 0x1009a22f 0xd _zPHY_DMA_CallBack_M
+ 0x1009a23c 0xd _zPHY_DMA_CallBack_S
+ 0x1009a249 0xd _zPHY_DMA_CallBack_CSILte
+ 0x1009a256 0xd _L1e_DevCmnIntPbchIntProc
+ 0x1009a263 0x36 _L1e_DevCmnIntCfoIntProc
+ 0x1009a299 0x1c _L1e_DevCmnIntCrsCirIntProc
+ 0x1009a2b5 0x31 _L1e_DevCmnIntCdtrIntProc
+ 0x1009a2e6 0x24 _L1e_DevCmnIntDdtrIntProc
+ 0x1009a30a 0x39 _L1e_CmnCheCqiInt
+ 0x1009a343 0xe _L1e_CmnTpuSubFrameInt
+ 0x1009a351 0x7 _L1e_CmnTpuAdjInt
+ 0x1009a358 0xb _L1e_CmnTxPulseInt
+ 0x1009a363 0x2d _L1e_CmnPdcchIntPcc
+ 0x1009a390 0x3d _L1e_CmnDfeInt
+ 0x1009a3cd 0x2f _L1e_CmnDfeDcInt
+ 0x1009a3fc 0x2c _L1e_CmnPdcchPccInt
+ 0x1009a428 0xd _L1e_CmnCsrDebugInt
+ 0x1009a435 0xd _L1e_CmnPbchInt
+ 0x1009a442 0xf _L1e_CmnPdschPccCirInt
+ 0x1009a451 0x1e _L1e_CmnDdtrPccInt
+ 0x1009a46f 0xd _L1e_CmnPbchIcInt
+ .text 0x1009a47c 0x1419 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
+ 0x1009a47c 0x1e9 _zPHY_eulpc_GetConfigParas
+ 0x1009a665 0x46 _zPHY_eulpc_InitialProc
+ 0x1009a6ab 0x3a _zPHY_eulpc_DeltaTcEUtraBandNoDeterm
+ 0x1009a6e5 0x278 _zPHY_eulpc_SingleCarrierMprDeterm
+ 0x1009a95d 0x4e9 _zPHY_eulpc_NoCaAMprDeterm
+ 0x1009ae46 0x82 _zPHY_eulpc_PcmaxCalc
+ 0x1009aec8 0x132 _zPHY_eulpc_PucchTpcProc
+ 0x1009affa 0x104 _zPHY_eulpc_PuschTpcProc
+ 0x1009b0fe 0x44 _zPHY_eulpc_RarTpcProc
+ 0x1009b142 0x6d _zPHY_eulpc_PowCtrlConfigParasCalc
+ 0x1009b1af 0x96 _zPHY_eulpc_TpcCommandsProc
+ 0x1009b245 0x110 _zPHY_eulpc_CloseLoopPowCtrlProc
+ 0x1009b355 0xb2 _zPHY_eulpc_Type1PhrCalc
+ 0x1009b407 0x27 _zPHY_eulpc_PhrCalcProc
+ 0x1009b42e 0xb7 _zPHY_eulpc_Sqrt
+ 0x1009b4e5 0x10d _zPHY_eulpc_PowScaleValCalc
+ 0x1009b5f2 0x37 _zPHY_eulpc_LinearValToPowDB
+ 0x1009b629 0x142 _zPHY_eulpc_UlaRelativeProc
+ 0x1009b76b 0x29 _zPHY_eulpc_UlPowerStub
+ 0x1009b794 0x1c _zPHY_eulpc_ReSetParameters
+ 0x1009b7b0 0xba _zPHY_eulpc_TempMaxPowerBackoff
+ 0x1009b86a 0x2b _zPHY_eulpc_GetLatestPower
+ .text 0x1009b895 0x134 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x1009b895 0x9 _L1l_DevEngInitAddr
+ 0x1009b89e 0x12 _L1l_log_track_init
+ 0x1009b8b0 0x46 _L1l_DevEngTrace
+ 0x1009b8f6 0xd1 _L1l_DevEngWriteDataToBuffer
+ 0x1009b9c7 0x1 _L1l_DevEngUartTransmit
+ 0x1009b9c8 0x1 _L1l_DevEngSwapHook
+ .text 0x1009b9c9 0x35a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o)
+ 0x1009b9c9 0x38 _zEasn1p_DcT_zEurrc_OctString
+ 0x1009ba01 0x46 _zEasn1p_DcT_zEurrc_S_TMSI
+ 0x1009ba47 0x5b _zEasn1p_DcT_zEurrc_IMSI
+ 0x1009baa2 0x42 _zEasn1p_DcT_zEurrc_PagingUE_Identity
+ 0x1009bae4 0x56 _zEasn1p_DcT_zEurrc_PagingRecord
+ 0x1009bb3a 0x4a _zEasn1p_DcT_zEurrc_PagingRecordList
+ 0x1009bb84 0x4e _zEasn1p_DcT_zEurrc_Paging_v920_IEs
+ 0x1009bbd2 0x49 _zEasn1p_DcT_zEurrc_Paging_v890_IEs
+ 0x1009bc1b 0x8f _zEasn1p_DcT_zEurrc_Paging
+ 0x1009bcaa 0x36 _zEasn1p_DcT_zEurrc_PCCH_MessageType_c1
+ 0x1009bce0 0x3a _zEasn1p_DcT_zEurrc_PCCH_MessageType
+ 0x1009bd1a 0x9 _zEasn1p_DcT_zEurrc_PCCH_Message
+ .text 0x1009bd23 0xe7e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
+ 0x1009bd23 0x27 _L1e_DevDlaCalcTotRegNum
+ 0x1009bd4a 0x75 _L1e_DevDlaCalcSearchSpace
+ 0x1009bdbf 0xdd _L1e_DevDlaProcPdcchSearchSpace
+ 0x1009be9c 0x11c _zPHY_edla_PdcchBldRntiEnRegProc
+ 0x1009bfb8 0x6f _zPHY_edla_PdcchBldPayLoadRegProc
+ 0x1009c027 0x82 _zPHY_edla_PdcchBlindDetectCaProc
+ 0x1009c0a9 0xd _zPHY_edla_PdcchBlindDetectProc
+ 0x1009c0b6 0x20 _zPHY_edla_GetBandWidthIdx
+ 0x1009c0d6 0x1c _zPHY_edla_GetAmbitiousBits
+ 0x1009c0f2 0x8c _zPHY_edla_PreDciInfo
+ 0x1009c17e 0x20d _zPHY_edla_GetDciSize
+ 0x1009c38b 0x809 _zPHY_edla_PdcchDemappingCaProc
+ 0x1009cb94 0xd _zPHY_edla_PdcchDemappingProc
+ .text 0x1009cba1 0x9b9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x1009cba1 0xa0 _zPHY_erfc_SupACP405ToRx
+ 0x1009cc41 0x6f _zPHY_erfc_SupACP405ToIdle
+ 0x1009ccb0 0x7f _zPHY_erfc_SupACP405ToTx
+ 0x1009cd2f 0x82 _zPHY_erfc_SupACP405ToRxTx
+ 0x1009cdb1 0x1 _zPHY_erfc_SupACP405McroWriteAGC
+ 0x1009cdb2 0x1c _zPHY_erfc_SupGetRealWorkFreq
+ 0x1009cdce 0x46 _zPHY_erfc_ATAptPointAdjust
+ 0x1009ce14 0x22 _zPHY_erfc_TxPowerAdjust
+ 0x1009ce36 0xb7 _zPHY_erfc_SupGetPATuRegInfo
+ 0x1009ceed 0x87 _zPHY_erfc_ProTxTempCompensate
+ 0x1009cf74 0x1d3 _zPHY_erfc_SupAPCControl
+ 0x1009d147 0x6f _zPHY_erfc_SupClosePA
+ 0x1009d1b6 0x1 _zPHY_erfc_SupAptReload
+ 0x1009d1b7 0x109 _L1l_DevRfcAfcFreqOffsetSet
+ 0x1009d2c0 0xd8 _zPHY_erfc_SupAfcEventSet
+ 0x1009d398 0x43 _zPHY_erfc_SupFreqOffseToDacValue
+ 0x1009d3db 0x52 _zPHY_erfc_SupDacValueToFreqOffset
+ 0x1009d42d 0x36 _zPHY_erfc_SupBandNumToVcxoBitPerHz
+ 0x1009d463 0x55 _zPHY_erfc_SupAfcVxcoInitWord
+ 0x1009d4b8 0x24 _L1l_DevRfcAfcFreqOffsetGet
+ 0x1009d4dc 0x2e _zPHY_erfc_DCXOCordicCfg
+ 0x1009d50a 0x50 _zPHY_erfc_DCXOAfcParaGet
+ .text 0x1009d55a 0x45e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ 0x1009d55a 0x20 _zPHY_edls_AdaJudgePdschTrans
+ 0x1009d57a 0x7a _zPHY_edls_AdaDecodePdcchOrder
+ 0x1009d5f4 0x89 _zPHY_edls_AdaDecodeDciF1C
+ 0x1009d67d 0x71 _zPHY_edls_AdaCalSiRntiNdiRv
+ 0x1009d6ee 0x72 _zPHY_edls_AdaCalSibDecodeParas
+ 0x1009d760 0x5e _zPHY_edls_AdaRbDmpType0Bw25Rb
+ 0x1009d7be 0x56 _zPHY_edls_AdaRbDmpType0Bw15Rb
+ 0x1009d814 0x46 _zPHY_edls_AdaRbDmpType0Bw6Rb
+ 0x1009d85a 0x26 _L1e_DevDlsGetMLSMTbs
+ 0x1009d880 0x1f _L1e_DevDlsTbsBinarySearch
+ 0x1009d89f 0x25 _L1e_DevDlsCalcRmCtrlParam
+ 0x1009d8c4 0xe9 _zPHY_edls_AdaCalRarDecodeParas
+ 0x1009d9ad 0xb _L1e_DevDlsCalcRmBbClk
+ .text 0x1009d9b8 0xf0b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ 0x1009d9b8 0x7 _L1e_DevRxGetPrevRxStatus
+ 0x1009d9bf 0x7 _L1e_DevRxGetCurrRxStatus
+ 0x1009d9c6 0xc _L1e_DevRxSwitchPrevStatus
+ 0x1009d9d2 0x9 _L1e_DevRxSetCurrRxStatus
+ 0x1009d9db 0xa6 _zPHY_edla_PageSubFrmJudge
+ 0x1009da81 0x17 _zPHY_edla_RxVshiftConfig
+ 0x1009da98 0xde _L1e_DevRxSfTypeCfg
+ 0x1009db76 0x18 _L1e_DevRxRsN0FactorCtrl
+ 0x1009db8e 0x17c _L1e_DevRxCRsN0ModeCtrl
+ 0x1009dd0a 0x7e _L1e_DevRxProcRsCinit
+ 0x1009dd88 0x5d _zPHY_edla_RxBandTxRxPortConfig
+ 0x1009dde5 0x113 _zPHY_edla_RxPhichMatrixConfig
+ 0x1009def8 0xf _zPHY_edla_RxCtrlChannelMimoModeConfig
+ 0x1009df07 0x6 _zPHY_edla_RxCalIndicatorConfig
+ 0x1009df0d 0x44 _zPHY_edla_RxCarrierInfoConfig
+ 0x1009df51 0x85 _zPHY_edla_CheProc
+ 0x1009dfd6 0xb _zPHY_edla_RxRbDemappingProc
+ 0x1009dfe1 0x25c _zPHY_edla_RbDemappingSubProc
+ 0x1009e23d 0x20 _zPHY_edla_WriteRxRbDemapRegFile
+ 0x1009e25d 0x2b _L1e_DevRxNormalN0ModCfg
+ 0x1009e288 0x25 _L1e_DevRxNCellRsNullCfg
+ 0x1009e2ad 0x9 _L1e_DevRxSetCirTiCtlFlg
+ 0x1009e2b6 0x9 _L1e_DevRxGetCirTiCtlFlg
+ 0x1009e2bf 0x70 _L1e_DevRxSinrLowInd
+ 0x1009e32f 0x53 _L1e_DevNSIOT_8242_Ind
+ 0x1009e382 0x41 _L1e_DevRxSinrTiCloseInd
+ 0x1009e3c3 0x7 _L1e_DevRxCrsIIRIndSet
+ 0x1009e3ca 0x7 _L1e_DevRxCrsIIRIndGet
+ 0x1009e3d1 0x8f _L1e_DevRxCrsIIRCfg
+ 0x1009e460 0x5d _L1e_DevRxSnrModeTiAdptProc
+ 0x1009e4bd 0x1c _L1e_DevRxSetTiAlgoMode
+ 0x1009e4d9 0x9 _L1e_DevRxGetNCellRsNullEnInd
+ 0x1009e4e2 0x9 _L1e_DevRxSetNCellRsNullEnInd
+ 0x1009e4eb 0x59 _L1e_DevRxTempPro
+ 0x1009e544 0x25b _zPHY_edla_RxRegCfgApply
+ 0x1009e79f 0x30 _L1e_DrvRxAgcCalandConfig
+ 0x1009e7cf 0xf4 _L1e_DbgRxCtrlInfo
+ .text 0x1009e8c3 0x25e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pucch.o)
+ 0x1009e8c5 0x217 _zPHY_eulpc_PucchPowCtrl
+ 0x1009eadc 0x45 _zPHY_eulpc_HNcqiNharqNsrCalc
+ .text 0x1009eb21 0x287 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_ddtr.o)
+ 0x1009eb21 0x8 _L1e_DrvDdtrResetCfg
+ 0x1009eb29 0x8 _L1e_DrvDdtrResetGet
+ 0x1009eb31 0x7 _L1e_DrvDtrScaleResetCfg
+ 0x1009eb38 0x8 _L1e_DrvDtrScaleEnCfg
+ 0x1009eb40 0xb _L1e_DrvDtrScaleDtchEnCfg
+ 0x1009eb4b 0x19 _L1e_DrvDtrScaleReset
+ 0x1009eb64 0x8 _L1e_DrvDdtrModeCfg
+ 0x1009eb6c 0x8 _L1e_DrvDdtrTurboLpCtrlRegCfg
+ 0x1009eb74 0x8 _L1e_DrvDdtrSubfNumCfg
+ 0x1009eb7c 0x8 _L1e_DrvDdtrHarqCtrlCfg
+ 0x1009eb84 0x8 _L1e_DrvDdtrHarqIramCtrlCfg
+ 0x1009eb8c 0xb _L1e_DrvDdtrHarqPriorityCfg
+ 0x1009eb97 0x8 _L1e_DrvDdtrHarqBurstCtrlCfg
+ 0x1009eb9f 0x8 _L1e_DrvDdtrIntTimerCfg
+ 0x1009eba7 0x8 _L1e_DrvDdtrLpCtrlCfg
+ 0x1009ebaf 0x8 _L1e_DrvDdtrUpdateCfg
+ 0x1009ebb7 0xd _L1e_DrvDdtrTbCrcRead
+ 0x1009ebc4 0x9 _L1e_DrvDdtrSibPchCrcRead
+ 0x1009ebcd 0x9 _L1e_DrvDdtrSubfNumRead
+ 0x1009ebd6 0x9 _L1e_DrvDdtrIdleStateRead
+ 0x1009ebdf 0x9 _L1e_DrvDdtrErrorIndRead
+ 0x1009ebe8 0x1 _L1e_DrvDdtrTurboLpCtrlCfg
+ 0x1009ebe9 0xb _L1e_DrvDdtrPdschEnCfg
+ 0x1009ebf4 0xb _L1e_DrvDdtrPdschEnRead
+ 0x1009ebff 0xb _L1e_DrvDdtrSwapFlagCfg
+ 0x1009ec0a 0xb _L1e_DrvDdtrSwapFlagGet
+ 0x1009ec15 0xe _L1e_DrvDdtrCwCinitCfg
+ 0x1009ec23 0xb _L1e_DrvDdtrTurboCtrlCfg
+ 0x1009ec2e 0xb _L1e_DrvDdtrPchBchTurboCtrlCfg
+ 0x1009ec39 0x5d _L1e_DrvDdtrTbParamCfg
+ 0x1009ec96 0x8 _L1e_DrvDdtrPchCinitCfg
+ 0x1009ec9e 0x11 _L1e_DrvDdtrPchParamCfg
+ 0x1009ecaf 0x8 _L1e_DrvDdtrSibCinitCfg
+ 0x1009ecb7 0x11 _L1e_DrvDdtrSibParamCfg
+ 0x1009ecc8 0x1d _L1e_DrvDdtrTurboReset
+ 0x1009ece5 0x9 _L1e_DrvDdtrGetAxiInfo
+ 0x1009ecee 0x39 _L1e_DrvDdtrPatchCfg
+ 0x1009ed27 0x8 _L1e_DrvDdtrDbgGetDdtrMode
+ 0x1009ed2f 0x8 _L1e_DrvDdtrDbgGetTopErrInd
+ 0x1009ed37 0x8 _L1e_DrvDdtrDbgGetAxiInfo
+ 0x1009ed3f 0x8 _L1e_DrvDdtrDbgGetIdleState
+ 0x1009ed47 0x8 _L1e_DrvDdtrDbgGetSubfNum
+ 0x1009ed4f 0xb _L1e_DrvDdtrDbgGetTurboCtrl
+ 0x1009ed5a 0xb _L1e_DrvDdtrDbgGetTbCbCrc
+ 0x1009ed65 0xa _L1e_DrvDdtrGetDbgMontor1
+ 0x1009ed6f 0xa _L1e_DrvDdtrGetDbgMontor2
+ 0x1009ed79 0xf _L1e_DrvDdtrDbgSelCfg
+ 0x1009ed88 0x8 _L1e_DrvDdtrDbgSelCfgread
+ 0x1009ed90 0x8 _L1e_DrvDdtrDbgSelCfgread0
+ 0x1009ed98 0x8 _L1e_DrvDdtrDbgSelCfgread1
+ 0x1009eda0 0x8 _L1e_DrvDdtrDbgSelCfgread2
+ .text 0x1009eda8 0x454 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x1009eda8 0x1c _zPHY_DrvTopIntAbleBitSet
+ 0x1009edc4 0x1f _zPHY_DrvTopIntMaskBitSet
+ 0x1009ede3 0xc _zPHY_DrvTopIntMaskRegWR
+ 0x1009edef 0xc _zPHY_DrvTopIntMaskRegRD
+ 0x1009edfb 0xc _zPHY_DrvGetTopIntStaus
+ 0x1009ee07 0xc _zPHY_DrvGetTopIntVec
+ 0x1009ee13 0xc _zPHY_DrvTopIntClear
+ 0x1009ee1f 0x1f _zPHY_DrvTopIntEnable
+ 0x1009ee3e 0x5a _zPHY_eintc_IntRegPrint
+ 0x1009ee98 0x2c _zPHY_DrvTopIntReg_Print
+ 0x1009eec4 0x1 _zPHY_DrvModemTopClkGate
+ 0x1009eec5 0x1 _zPHY_DrvModemTopClkSel
+ 0x1009eec6 0x11 _zPHY_LteModemTopClkCfg
+ 0x1009eed7 0x1b _zPHY_ResetModemHw
+ 0x1009eef2 0x33 _zPHY_LteaModemTopCfgBackup
+ 0x1009ef25 0x4a _zPHY_LteaModemTopCfgRecover
+ 0x1009ef6f 0x9 _zPHY_DrvTop_Reg_Set
+ 0x1009ef78 0x9 _zPHY_DrvTop_IntReg_Set
+ 0x1009ef81 0x9 _zPHY_DrvTop_IntReg_Get
+ 0x1009ef8a 0x28 _L1l_DrvMcuIntMask
+ 0x1009efb2 0x28 _L1l_DrvMcuIntUnmask
+ 0x1009efda 0xa _L1l_DrvMcuIntIreqClr
+ 0x1009efe4 0x3a _L1l_DrvTopIntMask
+ 0x1009f01e 0x39 _L1l_DrvTopIntRestore
+ 0x1009f057 0x48 _L1l_DrvTopIntEng
+ 0x1009f09f 0x1 _zPHY_DrvTOP_DFE_ClkPrintf
+ 0x1009f0a0 0x1 _zPHY_DrvTOP_CSR_ClkPrintf
+ 0x1009f0a1 0x7 _zPHY_DrvTOP_GetHarkRamSel
+ 0x1009f0a8 0x7 _zPHY_DrvTOP_GetTDHarkRamSel
+ 0x1009f0af 0x1 _zPHY_DrvTOP_Ddtr_ClkAndLpramPrintf
+ 0x1009f0b0 0x37 _zPHY_DrvLteaPwrClkCtrl
+ 0x1009f0e7 0x6 _zPHY_DrvPhyLteModemSel
+ 0x1009f0ed 0x7 _zPHY_DrvRmHarqRamLteModeClkSelCfg
+ 0x1009f0f4 0x5 _zPHY_DrvTurboModeSel
+ 0x1009f0f9 0x58 _zPHY_DrvLteTpuClkSet
+ 0x1009f151 0xe _zPHY_DrvLteTpuClkInit
+ 0x1009f15f 0x19 _zPHY_DrvChipTopRegInit
+ 0x1009f178 0x8 _zPHY_DrvTopCLKRegPOWGAT
+ 0x1009f180 0x9 _zPHY_DrvTopCLKReg2m1SCfg
+ 0x1009f189 0x9 _zPHY_DrvTopCLKRegRfcCfg
+ 0x1009f192 0xb _zPHY_DrvTop_RFInitReg_Set
+ 0x1009f19d 0x5f _zPHY_DMA_Cfg
+ .text 0x1009f1fc 0x2b6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ 0x1009f1fc 0x58 _L1L_TpuDrvReset
+ 0x1009f254 0x33 _L1L_TpuDrvSuspend
+ 0x1009f287 0x3f _L1L_TpuDrvResume
+ 0x1009f2c6 0x7 _L1L_TpuDrvCpModeGet
+ 0x1009f2cd 0x46 _L1L_TpuDrvCpModeSet
+ 0x1009f313 0x1c _L1L_TpuDrvLocalMrtrGet
+ 0x1009f32f 0x1c _L1L_TpuDrvMrtrGet
+ 0x1009f34b 0xe _L1L_TpuDrvMrtrOffsetGet
+ 0x1009f359 0x47 _L1L_TpuDrvTpuRegister
+ 0x1009f3a0 0x1b _L1L_TpuDrvMicroAdj
+ 0x1009f3bb 0x6 _L1L_TpuDrvMacroAdj
+ 0x1009f3c1 0x20 _L1L_TpuDrvHwBackup
+ 0x1009f3e1 0xb _L1L_TPUDrvCPModeGet
+ 0x1009f3ec 0xb _L1L_TPUDrvCPModeSet
+ 0x1009f3f7 0xa _L1L_TPUDrvMrtrOffGet
+ 0x1009f401 0x8 _L1L_TPUDrvMrtrOffSet
+ 0x1009f409 0x8 _L1L_TPUDrvAdjTimeSet
+ 0x1009f411 0xc _L1L_TPUDrvCPMrtrOffStore
+ 0x1009f41d 0xa _L1L_TPUDrvMRTRTransfer
+ 0x1009f427 0x8 _L1L_TPUDrvLocalMrtrGet
+ 0x1009f42f 0x8 _L1L_TPUDrvMrtrGet
+ 0x1009f437 0xb _L1L_TPUDrvHWResetCfg
+ 0x1009f442 0xf _L1L_TpuDrvRAMCtrl
+ 0x1009f451 0x8 _L1L_TPUDrvInttoArmIndexGet
+ 0x1009f459 0x9 _L1L_TpuDrvIntECTRamSel
+ 0x1009f462 0x50 _L1L_TPUDrvIntECTInit
+ .text 0x1009f4b2 0x242 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ 0x1009f4b2 0xea _zPHY_emc_DlDataReport
+ 0x1009f59c 0x27 _zPHY_emc_RdUlDataSendCtrlInfo
+ 0x1009f5c3 0x20 _zPHY_emc_wrUlReportBlerInfo
+ 0x1009f5e3 0x53 _zPHY_emc_WrUlSchedInfo
+ 0x1009f636 0x25 _zPHY_emc_InitRpMsgCh
+ 0x1009f65b 0x8 _zPHY_emc_MaskRpMsgCh
+ 0x1009f663 0x8 _zPHY_emc_UnMaskRpMsgCh
+ 0x1009f66b 0x9 _L1e_DrvGetIramTempCtrlBit
+ 0x1009f674 0x12 _L1e_DrvGetLteTempCtrlLimitInd
+ 0x1009f686 0xa _L1e_DrvGetDlSibPduCrcBaseAddr
+ 0x1009f690 0xb _L1e_DrvGetDlSibPduDataBaseAddr
+ 0x1009f69b 0xa _L1e_DrvGetDlPchPduCrcBaseAddr
+ 0x1009f6a5 0xb _L1e_DrvGetDlPchPduDataBaseAddr
+ 0x1009f6b0 0xa _L1e_DrvGetDlRarPduCrcBaseAddr
+ 0x1009f6ba 0xb _L1e_DrvGetDlRarPduDataBaseAddr
+ 0x1009f6c5 0x17 _L1e_DrvGetDlMacPduHarqBaseAddr
+ 0x1009f6dc 0xb _L1e_DrvGetDlMacPduCrcBaseAddr
+ 0x1009f6e7 0xd _L1e_DrvSetIslandAddr
+ .text 0x1009f6f4 0x57c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ 0x1009f6f4 0x7 _zPHY_elpc_DrvDelay
+ 0x1009f6fb 0x85 _L1l_DrvLpcGetSleepLen
+ 0x1009f780 0x32 _L1l_DrvLpcGetRemainCaliTime
+ 0x1009f7b2 0x8c _zPHY_elpc_LpmTimerCtrl
+ 0x1009f83e 0x26 _L1_LTE_GetLpmTimerIsEn
+ 0x1009f864 0x4 _L1L_DrvLpcSocWakeUpIntCtrl
+ 0x1009f868 0x1d _L1L_DrvLpcModemWakeUpIntCtrl
+ 0x1009f885 0x1b _L1L_DrvLpcCfgSocWkupInt
+ 0x1009f8a0 0x23 _L1L_DrvLpcCfgModemWkupInt
+ 0x1009f8c3 0x16 _L1l_DrvLpcGetLpmNT
+ 0x1009f8d9 0x4b _L1l_DrvLpcWaitLpmMrtrChange
+ 0x1009f924 0x19 _zPHY_elpc_DrvLpmCaliCfg
+ 0x1009f93d 0x10 _zPHY_elpc_DrvPdLteaCsrBackup
+ 0x1009f94d 0x6 _zPHY_elpc_DrvPdLteaTxBackup
+ 0x1009f953 0x1e _zPHY_elpc_DrvPdLteaCsrRecover
+ 0x1009f971 0x6 _zPHY_elpc_DrvPdLteaTxRecover
+ 0x1009f977 0x11 _zPHY_elpc_DrvPdLteaRfcDfeBackup
+ 0x1009f988 0x16 _zPHY_elpc_DrvPdLteaRfcDfeRecover
+ 0x1009f99e 0x5 _zPHY_elpc_DrvPdLteaRxRecover
+ 0x1009f9a3 0xf _zPHY_elpc_DrvPdLteaMimoCdtrRecover
+ 0x1009f9b2 0x5 _zPHY_elpc_DrvPdLteaDdtrHarqRecover
+ 0x1009f9b7 0x19 _zPHY_elpc_DrvPdLteaStdbyCtrl
+ 0x1009f9d0 0x47 _zPHY_elpc_DrvPdHwIsBusy
+ 0x1009fa17 0x1a _zPHY_elpc_DrvLteaPwrScenarioCtrlLog
+ 0x1009fa31 0x37 _zPHY_elpc_DrvLteaPwrHwBackup
+ 0x1009fa68 0x12e _zPHY_elpc_DrvLteaPwrScenarioCtrl
+ 0x1009fb96 0xc1 _zPHY_elpc_DrvLteaPwrCtrl
+ 0x1009fc57 0x19 _zPHY_eLpc_DrvClearLteaModemInt
+ .text 0x1009fc70 0x802 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
+ 0x1009fc70 0x24 _zPHY_eltx_SoftReset
+ 0x1009fc94 0x10 _zPHY_eltx_GetHWVersion
+ 0x1009fca4 0x10 _zPHY_eltx_GetStatus
+ 0x1009fcb4 0x42 _zPHY_eltx_Clk_En
+ 0x1009fcf6 0xa _zPHY_eltx_SetCPType
+ 0x1009fd00 0x12 _zPHY_eltx_SetChannelType
+ 0x1009fd12 0x27 _zPHY_eltx_SetSysBandwidth
+ 0x1009fd39 0xc _zPHY_eltx_SetTxTa
+ 0x1009fd45 0x9 _zPHY_eltx_SetPortSel
+ 0x1009fd4e 0x14 _zPHY_eltx_SetFirstSfFlag
+ 0x1009fd62 0xf _zPHY_eltx_SetConsecutiveSFLast
+ 0x1009fd71 0x1e _zPHY_eltx_SetFirstLastMode
+ 0x1009fd8f 0xa _zPHY_eltx_SetSendMode
+ 0x1009fd99 0xe _zPHY_eltx_SetAbbSampleRate
+ 0x1009fda7 0x14 _zPHY_eltx_SetInterMatrixInfo
+ 0x1009fdbb 0xc _zPHY_eltx_SetPuschScreamblePara
+ 0x1009fdc7 0xe _zPHY_eltx_SetPuschModulationMode
+ 0x1009fdd5 0xc _zPHY_eltx_SetPuschDFTPointNumber
+ 0x1009fde1 0x9 _zPHY_eltx_SetPrecodingCodeBook
+ 0x1009fdea 0x19 _zPHY_eltx_SetAckRiInfo
+ 0x1009fe03 0x4c _zPHY_eltx_SetRiMultiplexingInfo
+ 0x1009fe4f 0x77 _zPHY_eltx_SetAckMultiplexingInfo
+ 0x1009fec6 0xc _zPHY_eltx_SetPucchScreambleCint
+ 0x1009fed2 0x24 _zPHY_eltx_SetPucchHarqAckinfo
+ 0x1009fef6 0x1c _zPHY_eltx_SetPucchCqiInfo
+ 0x1009ff12 0xe _zPHY_eltx_SetPucchFmt
+ 0x1009ff20 0x20 _zPHY_eltx_SetPucchCommonReg
+ 0x1009ff40 0x20 _zPHY_eltx_SetPucchZCParas
+ 0x1009ff60 0x7f _zPHY_eltx_SetPucchNcsParas
+ 0x1009ffdf 0x72 _zPHY_eltx_SetPuschDmrsParas
+ 0x100a0051 0x68 _zPHY_eltx_SetSrsParas
+ 0x100a00b9 0x3c _zPHY_eltx_SetPrachParas
+ 0x100a00f5 0x3e _zPHY_eltx_SetScale
+ 0x100a0133 0x2b _zPHY_eltx_SetPuschReMappingParas
+ 0x100a015e 0x1c _zPHY_eltx_SetPucchReMappingParas
+ 0x100a017a 0x4b _zPHY_eltx_TxCalibrationPreIQOrDC
+ 0x100a01c5 0x4b _zPHY_eltx_SetTxCalibrationParas
+ 0x100a0210 0x19 _zPHY_eltx_SetFilter1Coeff
+ 0x100a0229 0x19 _zPHY_eltx_SetFilter2Coeff
+ 0x100a0242 0x19 _zPHY_eltx_SetFilter3Coeff
+ 0x100a025b 0xc _zPHY_eltx_SetByPass
+ 0x100a0267 0x9 _zPHY_eltx_SetFiFO
+ 0x100a0270 0xb _zPHY_eltx_SetAntPhaseClkDelay
+ 0x100a027b 0xc _zPHY_eltx_SetAntFrameDlyNum
+ 0x100a0287 0x2 _zPHY_eltx_SetPucchFormat3Paras
+ 0x100a0289 0xe _zPHY_eltx_Enable
+ 0x100a0297 0x9 _zPHY_eltx_SetDebugMode
+ 0x100a02a0 0x9 _zPHY_eltx_SetDebugBusSel
+ 0x100a02a9 0x9 _zPHY_eula_SetTXIntPulse
+ 0x100a02b2 0xa _zPHY_eltx_SetLTXIntSymbol
+ 0x100a02bc 0x30 _zPHY_eltx_SetPRS1Paras
+ 0x100a02ec 0x31 _zPHY_eltx_GetPRS1Result
+ 0x100a031d 0x30 _zPHY_eltx_SetPRS2Paras
+ 0x100a034d 0x2f _zPHY_eltx_GetPRS2Result
+ 0x100a037c 0x62 _zPHY_eula_TxRFCDBB_Interface
+ 0x100a03de 0x9 _zPHY_eula_SetTxDmaConfig
+ 0x100a03e7 0xb _zPHY_eula_SetLtxFreqCompBypass
+ 0x100a03f2 0xb _zPHY_eula_SetLtxFreqCompTheta
+ 0x100a03fd 0xb _zPHY_eula_SetLtxFreqCompTheta0
+ 0x100a0408 0x48 _zPHY_eula_TxFreqCompValGet
+ 0x100a0450 0x11 _zPHY_eula_TxCordicInit
+ 0x100a0461 0x11 _zPHY_eula_TxCordicCfg
+ .text 0x100a0472 0x165 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
+ 0x100a0472 0x19 _zPHY_ecsrm_MeasHwReset
+ 0x100a048b 0x77 _zPHY_ecsrm_MeasHwConfig
+ 0x100a0502 0x79 _zPHY_ecsrm_MeasResultRead
+ 0x100a057b 0x45 _zPHY_ecsrm_GetMeasDoneFlag
+ 0x100a05c0 0xb _zPHY_ecsrm_GetRspCnt
+ 0x100a05cb 0xc _zPHY_ecsrm_ClearMeasDoneFlag
+ .text 0x100a05d7 0x8de T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ 0x100a05d7 0x1b _L1e_DrvRxResetHW
+ 0x100a05f2 0xd1 _L1e_DrvRxCcRegInit
+ 0x100a06c3 0x92 _L1e_DrvRxPccRegInit
+ 0x100a0755 0x30 _L1e_DrvRxWriteRamCosWinCoeff
+ 0x100a0785 0x10 _L1e_DrvRxTransformFirCoeff
+ 0x100a0795 0x1c _L1e_DrvRxInitMrsFirCoeff
+ 0x100a07b1 0x61 _L1e_DrvRxWriteRamFICoeff
+ 0x100a0812 0x14 _zPHY_Drv_Rx_HwInit
+ 0x100a0826 0x18 _L1e_DrvRxWritePcfichPosRegFile
+ 0x100a083e 0x19 _zPHY_Drv_Rx_WritePhichPosRegFile
+ 0x100a0857 0x1 _zPHY_Drv_Rx_ClkPrintf
+ 0x100a0858 0x8 _L1e_DrvRxGateCtrlRead
+ 0x100a0860 0x8 _L1e_DrvRxClkSwitch0Cfg
+ 0x100a0868 0x8 _L1e_DrvRxClkSwitch0Read
+ 0x100a0870 0x8 _L1e_DrvRxPort5PatchCfg
+ 0x100a0878 0x8 _L1e_DrvRxPccCsiCheTimeRead
+ 0x100a0880 0x8 _L1e_DrvRxPbchCtrlCfg
+ 0x100a0888 0x8 _L1e_DrvRxPbchCtrlRead
+ 0x100a0890 0x8 _L1e_DrvRxCarrierInfoCfg
+ 0x100a0898 0x8 _L1e_DrvRxCarrierInfoRead
+ 0x100a08a0 0xb _L1e_DrvRxRxModeCfg
+ 0x100a08ab 0xb _L1e_DrvRxRxModeRead
+ 0x100a08b6 0xb _L1e_DrvRxRatModeCfg
+ 0x100a08c1 0xb _L1e_DrvRxCpModeCfg
+ 0x100a08cc 0xb _L1e_DrvRxCpModeRead
+ 0x100a08d7 0xb _L1e_DrvRxVshiftCfg
+ 0x100a08e2 0xb _L1e_DrvRxVshiftRead
+ 0x100a08ed 0xe _L1e_DrvRxPcfichRegPosCfg
+ 0x100a08fb 0xe _L1e_DrvRxPhichRegPosCfg
+ 0x100a0909 0x18 _L1e_DrvRxCellInfoCfg
+ 0x100a0921 0xb _L1e_DrvRxCellInfoRead
+ 0x100a092c 0xe _L1e_DrvRxSfnTypeCfg
+ 0x100a093a 0xe _L1e_DrvRxSfnTypeRead
+ 0x100a0948 0x13 _L1e_DrvRxTmIndCfg
+ 0x100a095b 0xb _L1e_DrvRxMbsfnCfiCfg
+ 0x100a0966 0xb _L1e_DrvRxMbsfnTm9IndCfg
+ 0x100a0971 0xb _L1e_DrvRxCirAccCtrlCfg
+ 0x100a097c 0xb _L1e_DrvRxCirAccCtrlRead
+ 0x100a0987 0xb _L1e_DrvRxMrsCirAccCtrlCfg
+ 0x100a0992 0xb _L1e_DrvRxMrsCirAccCtrlRead
+ 0x100a099d 0xb _L1e_DrvRxN0FgtFactorlCfg
+ 0x100a09a8 0x8 _L1e_DrvRxN0FgtFactorRead
+ 0x100a09b0 0xb _L1e_DrvRxN0ModeCfg
+ 0x100a09bb 0xb _L1e_DrvRxN0ModeRead
+ 0x100a09c6 0xb _L1e_DrvRxSwN0ValCfg
+ 0x100a09d1 0xb _L1e_DrvRxSwN0ValRead
+ 0x100a09dc 0xb _L1e_DrvRxMbsfnN0FgtCfg
+ 0x100a09e7 0xb _L1e_DrvRxMbsfnN0FgtRead
+ 0x100a09f2 0xb _L1e_DrvRxEicicModeCfg
+ 0x100a09fd 0xb _L1e_DrvRxEicicModeRead
+ 0x100a0a08 0xb _L1e_DrvRxBniCtrlCfg
+ 0x100a0a13 0x1 _L1e_DrvRxNbnbCtrlCfg
+ 0x100a0a14 0x2 _L1e_DrvRxNbnbCtrlRead
+ 0x100a0a16 0xb _L1e_DrvRxCchModuModeCfg
+ 0x100a0a21 0xb _L1e_DrvRxCchModuModeRead
+ 0x100a0a2c 0xb _L1e_DrvRxCchPcVolCfg
+ 0x100a0a37 0xb _L1e_DrvRxCchPcPowCfg
+ 0x100a0a42 0xb _L1e_DrvRxCsiRsCfg
+ 0x100a0a4d 0xb _L1e_DrvRxHijRptModeCfg
+ 0x100a0a58 0xb _L1e_DrvRxTiCrsRptModeCfg
+ 0x100a0a63 0xb _L1e_DrvRxTiCrsRptModeRead
+ 0x100a0a6e 0xb _L1e_DrvRxPhichMatrixCfg
+ 0x100a0a79 0xb _L1e_DrvRxCchWorkModeCfg
+ 0x100a0a84 0xb _L1e_DrvRxTiModeCfg
+ 0x100a0a8f 0xb _L1e_DrvRxTiModeRead
+ 0x100a0a9a 0x10 _L1e_DrvRxAgcBalanceCfg
+ 0x100a0aaa 0xe _L1e_DrvRxAgcBalanceRead
+ 0x100a0ab8 0xb _L1e_DrvRxZpCsiBmpCfg
+ 0x100a0ac3 0xe _L1e_DrvRxZpCsiPosCfg
+ 0x100a0ad1 0xe _L1e_DrvRxCrsCinitCfg
+ 0x100a0adf 0xe _L1e_DrvRxCrsCinitRead
+ 0x100a0aed 0xe _L1e_DrvRxCsiRsCinitCfg
+ 0x100a0afb 0xb _L1e_DrvRxRsParamCfg
+ 0x100a0b06 0xe _L1e_DrvRxIcCrsCinitCfg
+ 0x100a0b14 0xb _L1e_DrvRxIcRsParamCfg
+ 0x100a0b1f 0x26 _L1e_DrvRxN0BetaCfg
+ 0x100a0b45 0x27 _L1e_DrvRxN0BetaRead
+ 0x100a0b6c 0xb _L1e_DrvRxSwFirUpdateCfg
+ 0x100a0b77 0x8 _L1e_DrvRxFixFirUpdateCfg
+ 0x100a0b7f 0xb _L1e_DrvRxDrsGenStateCfg
+ 0x100a0b8a 0xb _L1e_DrvRxDrsCinitCfg
+ 0x100a0b95 0xb _L1e_DrvRxDrsParamCfg
+ 0x100a0ba0 0xb _L1e_DrvRxRbBmpValidCfg
+ 0x100a0bab 0x13 _L1e_DrvRxRbBmpCfg
+ 0x100a0bbe 0xb _L1e_DrvRxPrbBundlingBmpCfg
+ 0x100a0bc9 0xb _L1e_DrvRxCsiRsDelCtrlCfg
+ 0x100a0bd4 0xb _L1e_DrvRxCsiRsDelCtrlRead
+ 0x100a0bdf 0xb _L1e_DrvRxPdschModuModeCfg
+ 0x100a0bea 0xb _L1e_DrvRxPdschModuModeRead
+ 0x100a0bf5 0xb _L1e_DrvRxPdschMimoModeCfg
+ 0x100a0c00 0xb _L1e_DrvRxPdschMimoModeRead
+ 0x100a0c0b 0xb _L1e_DrvRxPdschRbMaskCfg
+ 0x100a0c16 0xb _L1e_DrvRxPdschTpmiCfg
+ 0x100a0c21 0x10 _L1e_DrvRxDchPcVolCfg
+ 0x100a0c31 0x10 _L1e_DrvRxDchPcPowCfg
+ 0x100a0c41 0xb _L1e_DrvRxPcEnCfg
+ 0x100a0c4c 0xb _L1e_DrvRxPort7IndCfg
+ 0x100a0c57 0xb _L1e_DrvRxMimoAlgoCfg
+ 0x100a0c62 0xb _L1e_DrvRxBfAlgoCfg
+ 0x100a0c6d 0xb _L1e_DrvRxPdschValidCfg
+ 0x100a0c78 0x13 _L1e_DrvRxCrsRssiRead
+ 0x100a0c8b 0x13 _L1e_DrvRxCrsRspRead
+ 0x100a0c9e 0x16 _L1e_DrvRxCrsRsrpRead
+ 0x100a0cb4 0xb _L1e_DrvRxCfoPhaseRead
+ 0x100a0cbf 0x13 _L1e_DrvRxMbsfnRssiRead
+ 0x100a0cd2 0x13 _L1e_DrvRxMbsfnRspRead
+ 0x100a0ce5 0x13 _L1e_DrvRxMbsfnRsrpRead
+ 0x100a0cf8 0x1c _L1e_DrvRxN0Read
+ 0x100a0d14 0x1e _L1e_DrvRxCirPeakPosRead
+ 0x100a0d32 0x22 _L1e_DrvRxDrsRsrpRead
+ 0x100a0d54 0x24 _L1e_DrvRxDrsRspRead
+ 0x100a0d78 0xb _L1e_DrvRxDrsAccNumRead
+ 0x100a0d83 0xc _L1e_DrvRxGetGenStateInd
+ 0x100a0d8f 0x6 _L1e_DrvRx_CqiHRx0
+ 0x100a0d95 0x6 _L1e_DrvRx_CqiNo0
+ 0x100a0d9b 0x6 _L1e_DrvRx_R
+ 0x100a0da1 0xd _L1e_DrvRxTpmiRamCfg
+ 0x100a0dae 0xd _L1e_DrvRxFirFixRamCfg
+ 0x100a0dbb 0x6 _L1e_DrvRxFirFixRamRec
+ 0x100a0dc1 0x16 _L1e_DrvRxFirDynRamCfg
+ 0x100a0dd7 0x1 _L1e_DrvRxFftBitmapRamCfg
+ 0x100a0dd8 0x1 _L1e_DrvRxTiAptRamRead
+ 0x100a0dd9 0x28 _L1e_DrvRxCirRamDataRead
+ 0x100a0e01 0xb4 _L1e_DrvRxDbgLogRxCheReg
+ .text 0x100a0eb5 0x209 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
+ 0x100a0eb5 0x1d _zPHY_elutr_SoftReset
+ 0x100a0ed2 0x12 _zPHY_elutr_GetHWVersion
+ 0x100a0ee4 0x1f _zPHY_elutr_HarqRam_Harness
+ 0x100a0f03 0x2b _zPHY_elutr_HarqRam_NoHarness
+ 0x100a0f2e 0x3a _zPHY_elutr_Clk_En
+ 0x100a0f68 0xe _zPHY_elutr_Enable
+ 0x100a0f76 0x9 _zPHY_elutr_GetHWStatus
+ 0x100a0f7f 0x13 _zPHY_elutr_CommonReg
+ 0x100a0f92 0xc _zPHY_elutr_Modulation
+ 0x100a0f9e 0xc _zPHY_elutr_SetTBLength
+ 0x100a0faa 0x24 _zPHY_elutr_SetTBSegParas
+ 0x100a0fce 0x1a _zPHY_elutr_SetTurboParas
+ 0x100a0fe8 0x25 _zPHY_elutr_SetRateMatchParas
+ 0x100a100d 0xc _zPHY_elutr_SetInterMatrixColNumber
+ 0x100a1019 0x24 _zPHY_elutr_SetPuschAckParas
+ 0x100a103d 0xe _zPHY_elutr_SetPuschAckUpdate
+ 0x100a104b 0x15 _zPHY_elutr_SetPuschRiParas
+ 0x100a1060 0xe _zPHY_elutr_SetPuschRiUpdate
+ 0x100a106e 0x25 _zPHY_elutr_SetPuschCqiParas
+ 0x100a1093 0xc _zPHY_elutr_SetPuschSubCarrierNumber
+ 0x100a109f 0x1f _zPHY_elutr_SetRiMultiplexingInfo
+ .text 0x100a10be 0x22a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
+ 0x100a10be 0x1b _L1e_DrvRxMimoReset
+ 0x100a10d9 0x19 _L1e_DrvPbchCdtrViterbiReset
+ 0x100a10f2 0x1b _L1e_DrvPbchHWReset
+ 0x100a110d 0x2 _L1e_DrvPbchInit
+ 0x100a110f 0x6a _L1e_DrvPbchConfigPbchReg
+ 0x100a1179 0xde _L1e_DrvPbchConfigRxReg
+ 0x100a1257 0x22 _L1e_DrvPbchGenRxSubFrmHead
+ 0x100a1279 0x23 _L1e_DrvPbchScGeneration
+ 0x100a129c 0x8 _L1e_DrvPbchCdtrViterbiClkRead
+ 0x100a12a4 0x8 _L1e_DrvPbchResultRead
+ 0x100a12ac 0x8 _L1e_DrvPbchAntSfnRead
+ 0x100a12b4 0x8 _L1e_DrvPbchStateRead
+ 0x100a12bc 0x9 _L1e_DrvPbchCdtrViterbiCtrl
+ 0x100a12c5 0x9 _L1e_DrvPbchCdtrVtbRamLpCtrl
+ 0x100a12ce 0x8 _L1e_DrvPbchLpcCfg
+ 0x100a12d6 0x9 _L1e_DrvCdtrlkEn
+ 0x100a12df 0x9 _L1e_DrvPbchClkEn
+ .text 0x100a12e8 0x36f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
+ 0x100a12e8 0x7 _L1e_DrvMimoCaRstCfg
+ 0x100a12ef 0xb _L1e_DrvMimoIrcModeCfg
+ 0x100a12fa 0xb _L1e_DrvMimoIrcModeRead
+ 0x100a1305 0x8 _L1e_DrvMimoUpdateCfg
+ 0x100a130d 0x8 _L1e_DrvMimoUpdateRead
+ 0x100a1315 0x8 _L1e_DrvCdtrResetCfg
+ 0x100a131d 0x1b _L1e_DrvCdtrHwReset
+ 0x100a1338 0x19 _L1e_DrvMimoReset
+ 0x100a1351 0x43 _L1e_DrvCdtrHwInit
+ 0x100a1394 0x8 _L1e_DrvCdtrTopClkSelCfg
+ 0x100a139c 0x26 _L1e_DrvCdtrTopRegCfg
+ 0x100a13c2 0x9 _L1e_DrvCdtrLpcCtrl
+ 0x100a13cb 0x1b _L1e_DrvCdtrPcfichRegCfg
+ 0x100a13e6 0x3b _L1e_DrvCdtrPhichRegCfg
+ 0x100a1421 0x93 _L1e_DrvCdtrPdcchBldRegCfg
+ 0x100a14b4 0x54 _L1e_DrvCdtrPdcchDmpRegCfg
+ 0x100a1508 0xb _L1e_DrvCdtrPhichNumCfg
+ 0x100a1513 0xb _L1e_DrvCdtrCchEnableCfg
+ 0x100a151e 0xc _L1e_DrvCdtrRntiEnRead
+ 0x100a152a 0xc _L1e_DrvCdtrCfiValueRead
+ 0x100a1536 0xc _L1e_DrvCdtrHiNumRead
+ 0x100a1542 0xf _L1e_DrvCdtrHiValueRead
+ 0x100a1551 0xc _L1e_DrvCdtrDciPld1Read
+ 0x100a155d 0xc _L1e_DrvCdtrDciPld2Read
+ 0x100a1569 0x1d _L1e_DrvCdtrDciRead
+ 0x100a1586 0x17 _L1e_DrvCdtrDciInfoRead
+ 0x100a159d 0xc _L1e_DrvCdtrDciValidRead
+ 0x100a15a9 0xc _L1e_DrvCdtrUePortRead
+ 0x100a15b5 0x8 _L1e_DrvCdtrDbgGetIntType
+ 0x100a15bd 0xb _L1e_DrvCdtrDbgGetDlDciInfo
+ 0x100a15c8 0x11 _L1e_DrvCdtrDbgGetDlDciFlag
+ 0x100a15d9 0x11 _L1e_DrvCdtrDbgGetSiDciFlag
+ 0x100a15ea 0x11 _L1e_DrvCdtrDbgGetPmDciFlag
+ 0x100a15fb 0x11 _L1e_DrvCdtrDbgGetRaDciFlag
+ 0x100a160c 0x4b _L1e_DrvCdtrPdcchBmpRamCfg
+ .text 0x100a1657 0x7f8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x100a1657 0x38 _zPHY_erfc_DrvGetSubFrameAddr
+ 0x100a168f 0xd1 _zPHY_erfc_DrvRealwokEventEn
+ 0x100a1760 0x62 _zPHY_erfc_DrvInitAllEventEnArray
+ 0x100a17c2 0x186 _zPHY_erfc_DrvWriteAllEventEnArrayToHwReg
+ 0x100a1948 0x1 _zPHY_erfc_DrvWriteAllEventEnArrayToHwReg_Slave
+ 0x100a1949 0x87 _zPHY_erfc_DrvAFCEventEn
+ 0x100a19d0 0x10 _zPHY_erfc_DrvSpiWrite
+ 0x100a19e0 0x59 _zPHY_erfc_DrvSetAgcSpiReg
+ 0x100a1a39 0xa _zPHY_erfc_DrvRbdp_RxIQInvert
+ 0x100a1a43 0xa _zPHY_erfc_DrvRbdp_TxIQInvert
+ 0x100a1a4d 0x1 _zPHY_erfc_DrvRbdpModeCfg
+ 0x100a1a4e 0x1 _zPHY_erfc_DrvTopRBDPGPIOConfig
+ 0x100a1a4f 0x1 _zPHY_erfc_DrvTopSSCConfig
+ 0x100a1a50 0xa _zPHY_erfc_DrvMasterModeTopGPIOConfig
+ 0x100a1a5a 0x1 _zPHY_erfc_DrvEventRamLeaveLP
+ 0x100a1a5b 0x50 _zPHY_erfc_DrvRfcRegInit
+ 0x100a1aab 0x1 _zPHY_erfc_DrvRfcRegInit_Slave
+ 0x100a1aac 0x91 _zPHY_erfc_DrvRFEventRamInit
+ 0x100a1b3d 0x1b _zPHY_erfc_DrvSoftwareReset
+ 0x100a1b58 0x18 _zPHY_erfc_DrvResetHw
+ 0x100a1b70 0xe _zPHY_erfc_DrvWriteCmdEvent
+ 0x100a1b7e 0xe _zPHY_erfc_DrvDBBEventSet
+ 0x100a1b8c 0x6 _zPHY_erfc_GetDfeSampleRateAddr
+ 0x100a1b92 0x2c _zPHY_erfc_GetRfcShadowEventTableAddr
+ 0x100a1bbe 0x33 _zPHY_erfc_GetRfcEventTableAddr
+ 0x100a1bf1 0x33 _zPHY_erfc_GetRfcBackupDDREventTableAddr
+ 0x100a1c24 0x30 _zPHY_erfc_DrvGetRamState
+ 0x100a1c54 0x85 _zPHY_erfc_DrvEvtTabStart
+ 0x100a1cd9 0x12 _zPHY_erfc_DrvGPIOEventSet
+ 0x100a1ceb 0xb _zPHY_erfc_DrvOpenfilter0
+ 0x100a1cf6 0xb _zPHY_erfc_DrvClosefilter0
+ 0x100a1d01 0xb _zPHY_erfc_DrvOpenfilter1
+ 0x100a1d0c 0xb _zPHY_erfc_DrvClosefilter1
+ 0x100a1d17 0xe _zPHY_erfc_DrvOpenfilter2
+ 0x100a1d25 0xb _zPHY_erfc_DrvClosefilter2
+ 0x100a1d30 0x10 _zPHY_erfc_DrvDfeRXBandWidthEn
+ 0x100a1d40 0x10 _zPHY_erfc_DrvDfeMeas0BandWidthEn
+ 0x100a1d50 0xb _zPHY_erfc_DrvGetfilter2State
+ 0x100a1d5b 0x7 _zPHY_erfc_DrvGetfilterState
+ 0x100a1d62 0x7 _zPHY_erfc_DrvGetSpiReadData
+ 0x100a1d69 0x7 _zPHY_erfc_DrvGetMipiReadData
+ 0x100a1d70 0x9 _zPHY_erfc_DrvSetRxRemovCpOffset
+ 0x100a1d79 0x54 _zPHY_erfc_DrvEvtSetTableOffset
+ 0x100a1dcd 0x9 _zPHY_erfc_DrvEnTxCalibration
+ 0x100a1dd6 0x1 _zPHY_erfc_DrvSlaveModeTopGPIOConfig
+ 0x100a1dd7 0xb _zPHY_erfc_DrvRfcRXBandWidthEn
+ 0x100a1de2 0xb _zPHY_erfc_DrvRfcMeas0BandWidthEn
+ 0x100a1ded 0x1a _zPHY_erfc_DrvInitTuRamTxEnReg
+ 0x100a1e07 0x25 _zPHY_erfc_DrvInitTuRamTxTable
+ 0x100a1e2c 0x23 _zPHY_erfc_DrvInitTuRegTxTable
+ .text 0x100a1e4f 0x1ad1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ 0x100a1e4f 0xcb _sin_wave_test_dfe
+ 0x100a1f1a 0x5a _zPHY_erfc_DrvRfcRffeWrite
+ 0x100a1f74 0x7a _zPHY_erfc_MIPI_Config
+ 0x100a1fee 0x1 _zPHY_erfc_DrvRfcRffeSwitchInit
+ 0x100a1fef 0x9f _zPHY_erfc_DrvDFESetAcp405Gain
+ 0x100a208e 0x25 _zPHY_erfc_DrvSpiCtrlWordPreDef
+ 0x100a20b3 0x4b _zPHY_erfc_DrvPaAndAntOpenForRX
+ 0x100a20fe 0x7b _zPHY_erfc_DrvPaAndAntOpenForTX
+ 0x100a2179 0x8e _zPHY_erfc_Idle2TDRX
+ 0x100a2207 0x82 _zPHY_erfc_Idle2TDTX
+ 0x100a2289 0x2f _zPHY_erfc_TxDbbSingleTone
+ 0x100a22b8 0xc _zPHY_erfc_TransToRX
+ 0x100a22c4 0xe _zPHY_erfc_TransToTX
+ 0x100a22d2 0x1 _zPHY_erfc_DrvACP405GpioTest
+ 0x100a22d3 0xc _zPHY_erfc_DrvACP405Spi32BitWrReg
+ 0x100a22df 0x11 _zPHY_erfc_ZTERfSPIWrite
+ 0x100a22f0 0x20 _zPHY_erfc_ZTERfSPIRead
+ 0x100a2310 0x1f _zPHY_erfc_ZTERfMIPIRead
+ 0x100a232f 0x1f _zPHY_erfc_ZTEAbbSPIRead
+ 0x100a234e 0xa _zPHY_erfc_DrvZTE110RegSet
+ 0x100a2358 0x49 _zPHY_erfc_DrvZTE110RxBandAndWidthConf
+ 0x100a23a1 0x10 _zPHY_erfc_DrvZTE120TxDACEn
+ 0x100a23b1 0x10 _zPHY_erfc_DrvZTE120TxDTXModeEn
+ 0x100a23c1 0xf _zPHY_erfc_DrvZTE120TxDACClk
+ 0x100a23d0 0x33 _zPHY_erfc_DrvCalcFracFreq
+ 0x100a2403 0x72 _zPHY_erfc_ZTE110_RxRegConfig
+ 0x100a2475 0x65 _zPHY_erfc_ZTE110_TxRegConfig
+ 0x100a24da 0x3a _zPHY_erfc_ZTE120_RxRegConfig
+ 0x100a2514 0x36 _zPHY_erfc_ZTE120_TxRegConfig
+ 0x100a254a 0x8c _zPHY_erfc_GetOpenRxRamNum
+ 0x100a25d6 0x1c5 _zPHY_erfc_EventOpenRx
+ 0x100a279b 0x89 _zPHY_erfc_EventOpenRxAntenna
+ 0x100a2824 0x18c _zPHY_erfc_EventOpenTx
+ 0x100a29b0 0x65 _zPHY_erfc_EventOpenTxAntenna
+ 0x100a2a15 0x92 _zPHY_erfc_GetOpenRxAntennaIndex
+ 0x100a2aa7 0xe9 _zPHY_erfc_GetOpenRxIndex
+ 0x100a2b90 0x30 _zPHY_erfc_GetOpenTxIndex
+ 0x100a2bc0 0x35 _zPHY_erfc_GetOpenTxAntennaIndex
+ 0x100a2bf5 0x26 _zPHY_erfc_GetOpenTxRamNum
+ 0x100a2c1b 0xdc _zPHY_erfc_GetOpenRxLineIndex
+ 0x100a2cf7 0x70 _zPHY_erfc_GetOpenRxLineData
+ 0x100a2d67 0x55 _zPHY_erfc_GetNorTxOpenIndex
+ 0x100a2dbc 0x57 _zPHY_erfc_GetOpenTxLineIndex
+ 0x100a2e13 0x6d _zPHY_erfc_GetOpenTxLineData
+ 0x100a2e80 0xb6 _zPHY_erfc_EventTableOpenRx
+ 0x100a2f36 0xae _zPHY_erfc_TxTableOpenTx
+ 0x100a2fe4 0xd8 _zPHY_erfc_GetCloseAntennaIndex
+ 0x100a30bc 0xdf _zPHY_erfc_GetRfToIdleIndex
+ 0x100a319b 0x75 _zPHY_erfc_GetRfToIdleData
+ 0x100a3210 0x97 _zPHY_erfc_EventAntennaToIdle
+ 0x100a32a7 0xb9 _zPHY_erfc_EventRfToIdle
+ 0x100a3360 0x2d _zPHY_erfc_GetCloseRfRamNum
+ 0x100a338d 0x54 _zPHY_erfc_EventTableToIdle
+ 0x100a33e1 0x111 _zPHY_erfc_GetPAIndex
+ 0x100a34f2 0x7d _zPHY_erfc_AmtRfFrontSet
+ 0x100a356f 0x2f _zPHY_erfc_RfAntenna_set
+ 0x100a359e 0x6b _zPHY_erfc_RfPAFrontSet
+ 0x100a3609 0x25 _zPHY_erfc_ATSetAptFixVoltage
+ 0x100a362e 0xe8 _zPHY_erfc_GetRfVGACtrlWord
+ 0x100a3716 0x14 _zPHY_erfc_LittleTabWritePATrigEna
+ 0x100a372a 0x14 _zPHY_erfc_LittleTabWritePATrigLoad
+ 0x100a373e 0x14 _zPHY_erfc_LittleTabWritePATrigDisa
+ 0x100a3752 0x13e _zPHY_erfc_LittleTabWritePaAndVga
+ 0x100a3890 0x49 _zPHY_erfc_SupCheckPAMode
+ 0x100a38d9 0x1 _zPHY_erfc_RxSinToneTest
+ 0x100a38da 0x1 _zPHY_erfc_TxSinToneTest
+ 0x100a38db 0x1 _zPHY_erfc_DrvRfNvInit
+ 0x100a38dc 0x44 _zPHY_erfc_GetRfDCOC_CalVaue
+ .text 0x100a3920 0x204 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ 0x100a3920 0x21 _zPHY_erfc_DrvRfcTxSampleRateSet
+ 0x100a3941 0x34 _zPHY_erfc_DrvRfcDfeSampleRateSet
+ 0x100a3975 0x4c _zPHY_erfc_DrvInitMainSyncTable
+ 0x100a39c1 0xa5 _zPHY_erfc_DrvInitMeasTable0
+ 0x100a3a66 0x45 _zPHY_erfc_DrvInitTxSendTable
+ 0x100a3aab 0x42 _zPHY_erfc_DrvEventTableBoundaryInit
+ 0x100a3aed 0xc _zPHY_erfc_IRAM_Set
+ 0x100a3af9 0x1a _zPHY_erfc_IRAM_Get
+ 0x100a3b13 0x10 _zPHY_erfc_DrvDBBDely
+ 0x100a3b23 0x1 _zPHY_erfc_DrvRfTopIntfInit
+ .text 0x100a3b24 0xb70 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x100a3b24 0x4a _zPHY_edfe_DrvInitInt
+ 0x100a3b6e 0x53 _zPHY_edfe_DrvResetHw
+ 0x100a3bc1 0x3b _zPHY_edfe_DrvConfigRXBandwidth
+ 0x100a3bfc 0x3b _zPHY_edfe_DrvConfigCSRMBandwidth
+ 0x100a3c37 0x1f _zPHY_edfe_DrvGetDCOffsetEsti
+ 0x100a3c56 0x2c _zPHY_edfe_DrvConfigDCOffset
+ 0x100a3c82 0x1f _zPHY_edfe_DrvGetIQEstiSum
+ 0x100a3ca1 0x1f _zPHY_edfe_DrvGetIQEstiCPSum
+ 0x100a3cc0 0x30 _zPHY_edfe_DrvConfigIQImbal
+ 0x100a3cf0 0x6a _zPHY_edfe_DrvConfigAGCPara
+ 0x100a3d5a 0x14 _zPHY_edfe_DrvGetAGCMeanPower
+ 0x100a3d6e 0x12 _zPHY_edfe_DrvGetAGCLFOutVal
+ 0x100a3d80 0xa _zPHY_edfe_DrvGetAGCHWGainValue
+ 0x100a3d8a 0xa _zPHY_edfe_DrvCompesateCFO
+ 0x100a3d94 0x27 _zPHY_edfe_DrvDcIqParaInit
+ 0x100a3dbb 0x8a _zPHY_edfe_DrvConfigFIRCoeff
+ 0x100a3e45 0x50 _zPHY_edfe_DrvConfigDAGCPara
+ 0x100a3e95 0x31 _zPHY_edfe_DrvGetDAGCMeanPower
+ 0x100a3ec6 0x12 _zPHY_edfe_DrvGetMbsfnDAGCMeanPower
+ 0x100a3ed8 0x52 _zPHY_edfe_DrvConfigDAGCSWGainValue
+ 0x100a3f2a 0x3b _zPHY_edfe_DrvConfigMbsfnRxDAGCSWGainValue
+ 0x100a3f65 0x1 _zPHY_edfe_DrvAGCGainConvertTableInit
+ 0x100a3f66 0x7e _zPHY_edfe_DrvInitDFE
+ 0x100a3fe4 0x72 _zPHY_edfe_DrvDcIqCfoDagcApplyEn
+ 0x100a4056 0xd0 _zPHY_edfe_DrvRxCPModeConfig
+ 0x100a4126 0x1 _zPHY_edfe_DrvCsrmCPModeConfig
+ 0x100a4127 0x29 _zPHY_edfe_DrvAgcExtModeConfig
+ 0x100a4150 0x22 _zPHY_edfe_DrvDfeAbbSamplingRateConfig
+ 0x100a4172 0x1a _zPHY_edfe_DrvMbsfnTwoAgcDagcEn
+ 0x100a418c 0xb _zPHY_edfe_DrvMbsfnTimingOffset
+ 0x100a4197 0x14 _zPHY_edfe_DrvTxCaliConfig
+ 0x100a41ab 0x1e _zPHY_edfe_DrvMeasBufferModeComnParaConfig
+ 0x100a41c9 0x15 _zPHY_edfe_DrvMeasBufferModeCellParaConfig
+ 0x100a41de 0x9 _zPHY_edfe_DrvMeasBufferModeRamReadEn
+ 0x100a41e7 0x29 _zPHY_edfe_DrvMeasMode
+ 0x100a4210 0x15 _zPHY_edfe_DrvMeasClock
+ 0x100a4225 0xe _zPHY_edfe_DrvMeasClockClose
+ 0x100a4233 0x15 _zPHY_edfe_DrvMeasReset
+ 0x100a4248 0x14 _zPHY_edfe_DrvGetMbsfnAGCMeanPower
+ 0x100a425c 0x29 _zPHY_edfe_DrvConfigMbsfnAGCSWGainValue
+ 0x100a4285 0x14 _zPHY_edfe_DrvLpcSaveRegForCsr
+ 0x100a4299 0x2a _zPHY_edfe_DrvLpcSaveRegForRxCommon
+ 0x100a42c3 0xe8 _zPHY_edfe_DrvLpcResumeRxCommon
+ 0x100a43ab 0x3 _zPHY_edfe_DrvLpcResumePower1Public
+ 0x100a43ae 0x68 _zPHY_edfe_DrvLpcResumeCsr
+ 0x100a4416 0x20 _zPHY_edfe_DrvLpcResumePower0Public
+ 0x100a4436 0x12 _zPHY_edfe_DrvAgcLenStepConfig
+ 0x100a4448 0xb _zPHY_edfe_DrvDagc2LenStepConfig
+ 0x100a4453 0x13 _zPHY_edfe_DrvAntModeConfig
+ 0x100a4466 0x26 _zPHY_edfe_DrvAgcIntStateConfig
+ 0x100a448c 0x8 _zPHY_edfe_DrvConfigAgcCalControl
+ 0x100a4494 0x18 _zPHY_edfe_DrvGetEverySampMeanPower
+ 0x100a44ac 0x1 _zPHY_edfe_DrvRfcDfeInterfaceSet
+ 0x100a44ad 0x1 _zPHY_edfe_DrvPrsMeasModeComnParaConfig
+ 0x100a44ae 0x1 _zPHY_edfe_DrvCsrInputSelect
+ 0x100a44af 0x2 _zPHY_edfe_DrvGetCsrInputSelState
+ 0x100a44b1 0x54 _zPHY_edfe_DrvResetPwr0
+ 0x100a4505 0xa _zPHY_edfe_DrvDfeIntfSel
+ 0x100a450f 0x16 _zPHY_edfe_DrvCPAddLenConfig
+ 0x100a4525 0x30 _zPHY_edfe_DrvCsrDDrCatchDataEn
+ 0x100a4555 0xd _zPHY_edfe_DrvCsrDDrCatchDataStop
+ 0x100a4562 0x1f _zPHY_edfe_DrvPwr0RestCsrSyncHw
+ 0x100a4581 0x3c _L1l_DrvDfeCalcNotchParaA
+ 0x100a45bd 0x8 _L1l_DrvDfeNotchSetBypass
+ 0x100a45c5 0xa _L1l_DrvDfeNotchSetA_First
+ 0x100a45cf 0xa _L1l_DrvDfeNotchSetA_Second
+ 0x100a45d9 0xa _L1l_DrvDfeNotchSetA_Third
+ 0x100a45e3 0xc _L1l_DrvDfeNotchSetT_A
+ 0x100a45ef 0xc _L1l_DrvDfeNotchSetT_B
+ 0x100a45fb 0xe _L1l_DrvDfeNotchSetK_A
+ 0x100a4609 0xe _L1l_DrvDfeNotchSetK_B
+ 0x100a4617 0xf _zPHY_edfe_DrvEnableDcInt
+ 0x100a4626 0x5 _zPHY_edfe_ClkPrintf
+ 0x100a462b 0x69 _zPHY_edfe_LteBuffRegPrint
+ .text 0x100a4694 0x879 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ 0x100a4694 0x2a _zEcsr_CurrentGapTime
+ 0x100a46be 0x1d _zEcsr_CurrentGapSuperTime
+ 0x100a46db 0x3c _zEcsr_GetGapStateEx
+ 0x100a4717 0x13 _zEcsr_GetLteGapState
+ 0x100a472a 0x9 _zEcsr_GetGapState
+ 0x100a4733 0x16 _zEcsr_GetIratGapState
+ 0x100a4749 0x23 _zEcsr_GapCnt
+ 0x100a476c 0x48 _zEcsr_GetLastGapTime
+ 0x100a47b4 0x42 _zEcsr_GetGapStartTime
+ 0x100a47f6 0x4b _zEcsr_GetNeartGapTime
+ 0x100a4841 0x76 _zEcsr_GetTimeBeforeIratGap
+ 0x100a48b7 0x42 _zEcsr_GetTimeBeforeGapEx
+ 0x100a48f9 0x8 _zEcsr_GetTimeBeforeGap
+ 0x100a4901 0x12 _zEcsr_GetTimeBeforeLteGap
+ 0x100a4913 0x19 _zEcsr_Compare
+ 0x100a492c 0xb _zEcsr_GapTimeCompare
+ 0x100a4937 0x7 _zEcsr_TimeCompare
+ 0x100a493e 0x40 _zEcsr_BeforeGapHalfFrame
+ 0x100a497e 0x40 _zEcsr_AfterGapHalfFrame
+ 0x100a49be 0x33 _zEcsr_GetGapOffsetEx
+ 0x100a49f1 0x8 _zEcsr_GetGapOffset
+ 0x100a49f9 0x60 _zEcsr_GetGapType
+ 0x100a4a59 0x32 _zEcsr_IsValidGapTime
+ 0x100a4a8b 0x61 _zEcsr_GetGapDistance
+ 0x100a4aec 0x89 _zEcsr_GapType
+ 0x100a4b75 0x13 _zEcsr_GetLteGapOffset
+ 0x100a4b88 0x14 _zEcsr_IsAroundGap
+ 0x100a4b9c 0x14 _zEcsr_IsAroundLteGap
+ 0x100a4bb0 0x54 _zEcsr_CurrentGapType
+ 0x100a4c04 0x3d _zEcsr_CurrentGapStartTime
+ 0x100a4c41 0x10 _zEcsr_CurrentGapFrame
+ 0x100a4c51 0x18 _zEcsr_NextGapFrame
+ 0x100a4c69 0xd _zEcsr_GapSubFrame
+ 0x100a4c76 0xe _zEcsr_LteGapGapAvai
+ 0x100a4c84 0xc _zEcsr_CurrentGapStartMrtr
+ 0x100a4c90 0x19 _zEcsr_CurrentMrtrUpper
+ 0x100a4ca9 0x2a _zEcsr_NextHalfFrame
+ 0x100a4cd3 0x2d _zEcsr_TimeToMrtr
+ 0x100a4d00 0x12 _zEcsr_MrtrToTime
+ 0x100a4d12 0xb _zEcsr_TimeToTs
+ 0x100a4d1d 0x57 _zEcsr_TimeOnGapConfig
+ 0x100a4d74 0x1a _zEcsr_TimeInit
+ 0x100a4d8e 0x7 _zPHY_ecsrc_CtrltTime2Ts
+ 0x100a4d95 0x1f _zPHY_ecsrc_TimeAdd
+ 0x100a4db4 0x25 _zPHY_ecsrc_TimeSub
+ 0x100a4dd9 0x16 _zPHY_ecsrc_MrtrAddTs
+ 0x100a4def 0x19 _zPHY_ecsrc_MrtrAddSlot
+ 0x100a4e08 0x1c _zPHY_ecsrc_MrtrSubTs
+ 0x100a4e24 0x1f _zPHY_ecsrc_MrtrSubSlot
+ 0x100a4e43 0x2b _zPHY_ecsrc_MrtrAddSignTs
+ 0x100a4e6e 0x24 _zPHY_ecsrc_GetCurTime
+ 0x100a4e92 0x18 _zPHY_ecsrc_Mrtr2LocalMrtr
+ 0x100a4eaa 0x18 _zPHY_ecsrc_LocalMrtr2Mrtr
+ 0x100a4ec2 0x4 _zPHY_ecsrc_RemoveMrtrTs
+ 0x100a4ec6 0x23 _zPHY_ecsrc_MakeMrtr
+ 0x100a4ee9 0x24 _zPHY_ecsrc_TsToLocalTs
+ .text 0x100a4f0d 0x571 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc.o)
+ 0x100a4f0d 0x571 _zPHY_erapc_ThreadEntry
+ .text 0x100a547e 0x12ff T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ 0x100a547e 0xcf _zPHY_ecsrc_InitMeasOnIdle
+ 0x100a554d 0x31 _zPHY_ecsrc_ConfigRfcOffset
+ 0x100a557e 0x96 _zPHY_ecsrc_CtrlCampOnProcess
+ 0x100a5614 0x9a _zPHY_ecsrc_CtrlMeasConfigProcess
+ 0x100a56ae 0x141 _zPHY_ecsrc_CtrlMeasSetProcess
+ 0x100a57ef 0x37 _zPHY_ecsrc_SetMeasAge
+ 0x100a5826 0x7c _L1e_csrc_IdleSetAgeThrold
+ 0x100a58a2 0x147 _L1e_csrc_ConnectSetAgeThrold
+ 0x100a59e9 0x46 _zPHY_ecsrc_CtrlSetSearchMeasAgeThrold
+ 0x100a5a2f 0x73 _zPHY_ecsrc_ReadRxMeas
+ 0x100a5aa2 0x47 _zPHY_ecsrc_ReadServCellRxMeas
+ 0x100a5ae9 0x23 _zPHY_ecsrc_GetCellMeasReslut
+ 0x100a5b0c 0x96 _zPHY_ecsrc_CtrlWriteServingCellResult
+ 0x100a5ba2 0x3d _zPHY_ecsrc_SetMeasResultValue
+ 0x100a5bdf 0x3c _zPHY_ecsrc_WriteNeibMeasResult
+ 0x100a5c1b 0x10 _zPHY_ecsrc_CtrlWritePccMeasResult
+ 0x100a5c2b 0x14d _zPHY_ecsrc_CtrlMeasFilterReq
+ 0x100a5d78 0x13 _zPHY_ecsrc_ConnAcquireIntraMeas
+ 0x100a5d8b 0x70 _zPHY_ecsrc_AcquireInterMeas
+ 0x100a5dfb 0x16 _zPHY_ecsrc_AcquireServMeas
+ 0x100a5e11 0xd _zPHY_ecsrc_ReportMeasReslutIntra
+ 0x100a5e1e 0x50 _zPHY_ecsrc_ReportMeasReslutInter
+ 0x100a5e6e 0x2b _zPHY_ecsrc_UpdateRsrpKByFlagCounter
+ 0x100a5e99 0x38 _zPHY_ecsrc_AdaptFilterFactor
+ 0x100a5ed1 0xb5 _zPHY_ecsrc_FreqFilter
+ 0x100a5f86 0x33 _zPHY_ecsrc_FilterNoResult
+ 0x100a5fb9 0x30 _zPHY_ecsrc_DelInvalidCell
+ 0x100a5fe9 0x9b _zPHY_ecsrc_InterMeasFilter
+ 0x100a6084 0x72 _zPHY_ecsrc_IntraMeasFilter
+ 0x100a60f6 0x69 _zPHY_ecsrc_FilterMeasRank
+ 0x100a615f 0x42 _zPHY_ecsrc_ReportMeasRank
+ 0x100a61a1 0x34 _zPHY_ecsrc_UpdateFreqReport
+ 0x100a61d5 0x7a _zPHY_ecsrc_UpdateIntraReport
+ 0x100a624f 0x9 _zPHY_ecsrc_GetFilterIntraMeasRsrp
+ 0x100a6258 0x70 _zPHY_ecsrc_UpdateInterReport
+ 0x100a62c8 0x12 _zPHY_ecsrc_ClearNeibCellRsrp
+ 0x100a62da 0x1c _zPHY_ecsrc_ClearIntraFilter
+ 0x100a62f6 0x23 _L1e_csrc_SetIdleFilterFactor
+ 0x100a6319 0x2e _zPHY_ecsrc_SetFilterFactor
+ 0x100a6347 0x62 _zPHY_ecsrc_FilterMeasCfg
+ 0x100a63a9 0x4 _zPHY_ecsrc_FilterComnCfg
+ 0x100a63ad 0xc _zPHY_ecsrc_InitInterFilter
+ 0x100a63b9 0x36 _zPHY_ecsrc_InitInterFilterFreq
+ 0x100a63ef 0x60 _zPHY_ecsrc_InitIntraFilter
+ 0x100a644f 0x47 _zPHY_ecsrc_InterMeasIndPrint
+ 0x100a6496 0x49 _zPHY_ecsrc_CtrlIntraMeasInfoPrint
+ 0x100a64df 0x37 _zPHY_ecsrc_IntraFilterDebugInfo
+ 0x100a6516 0x4a _zPHY_ecsrc_InterFilterDebugInfo
+ 0x100a6560 0x12 _zPHY_ecsrc_CaSwitch
+ 0x100a6572 0x78 _zPHY_ecsrc_ProPhy2PsMsgSINRandRSSI
+ 0x100a65ea 0x54 _zPHY_ecsrc_WriteRssiToSearchCnf
+ 0x100a663e 0x25 _zPHY_ecsrc_AcquireIntraMeas
+ 0x100a6663 0x20 _zPHY_ecsrc_SrvCellResltDeal
+ 0x100a6683 0x45 _zPHY_ecsrc_ClearAfcInfo
+ 0x100a66c8 0x6a _L1e_DevCsrNCellRsNullInd
+ 0x100a6732 0x10 _L1e_DevCsrGetMeasResult
+ 0x100a6742 0x3b _zPHY_ecsrc_CtrlIdleSetInterFilterFact
+ .text 0x100a677d 0x21b2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ 0x100a677d 0x8 _L1e_Sir_RxMeasMask
+ 0x100a6785 0x8 _L1e_Sir_QuryRxMeasMask
+ 0x100a678d 0x27f _L1e_Sir_MainCtrlFlow
+ 0x100a6a0c 0x33 _L1e_Sir_DbReset
+ 0x100a6a3f 0x31 _L1e_Sir_LpcAndTurboCtrl
+ 0x100a6a70 0x30 _L1e_Sir_AddTpuEvt
+ 0x100a6aa0 0x28 _L1e_Sir_DelAllTpuEvt
+ 0x100a6ac8 0x26 _L1e_Sir_QueryTpuEvt
+ 0x100a6aee 0x33 _L1e_Sir_DelTpuEvt
+ 0x100a6b21 0x4a _L1e_Sir_RegDelayEvt
+ 0x100a6b6b 0x21 _L1e_Sir_PreProc
+ 0x100a6b8c 0x8 _L1e_Sir_MainState
+ 0x100a6b94 0x8 _L1e_Sir_StepState
+ 0x100a6b9c 0x8 _L1e_Sir_SyncState
+ 0x100a6ba4 0x19 _L1e_Sir_CommInSiProc
+ 0x100a6bbd 0x34 _L1e_Sir_SetState
+ 0x100a6bf1 0x98 _L1e_Sir_UpSib1Para
+ 0x100a6c89 0x75 _L1e_Sir_UpSiPara
+ 0x100a6cfe 0x15 _L1e_Sir_UpSerPara
+ 0x100a6d13 0x2d _L1e_Sir_UpDecPara
+ 0x100a6d40 0x8 _L1e_Sir_UpDecState
+ 0x100a6d48 0xd _L1e_Sir_QurySerSir
+ 0x100a6d55 0xc _L1e_Sir_QurySib1State
+ 0x100a6d61 0xd _L1e_Sir_QurySiState
+ 0x100a6d6e 0x1a _L1e_Sir_QueryRptEn
+ 0x100a6d88 0x14 _L1e_Sir_CtrlDecOps
+ 0x100a6d9c 0x23 _L1e_Sir_UpSibWin
+ 0x100a6dbf 0x56 _L1e_Sir_StopSibProc
+ 0x100a6e15 0x4e _L1e_Sir_UpSchedPara
+ 0x100a6e63 0x96 _L1e_Sir_StartSib1
+ 0x100a6ef9 0x71 _L1e_Sir_BchSync
+ 0x100a6f6a 0x5c _L1e_Sir_RestartBch
+ 0x100a6fc6 0xcc _L1e_Sir_StartSi
+ 0x100a7092 0xb7 _L1e_Sir_AbortSi
+ 0x100a7149 0x64 _L1e_Sir_SchedSib1
+ 0x100a71ad 0xd4 _L1e_Sir_SchedSi
+ 0x100a7281 0xcb _L1e_Sir_ProcDecSucc
+ 0x100a734c 0xd0 _L1e_Sir_BackSerCell
+ 0x100a741c 0x2c _L1e_Sir_DataReport
+ 0x100a7448 0x92 _L1e_Sir_SndMibReq
+ 0x100a74da 0x39 _L1e_Sir_SndMibCnf
+ 0x100a7513 0x19 _L1e_Sir_SndBchFail
+ 0x100a752c 0x7d _L1e_Sir_QueryMib
+ 0x100a75a9 0x2e _L1e_Sir_ProBchHandle
+ 0x100a75d7 0x43 _L1e_Sir_QueryCell
+ 0x100a761a 0x15 _L1e_Sir_CtrlAgcState
+ 0x100a762f 0x40 _L1e_Sir_UpRfcCfg
+ 0x100a766f 0x7 _L1e_Sir_CalBoundryTs
+ 0x100a7676 0x81 _L1e_Sir_DelyTpuAdjust
+ 0x100a76f7 0x60 _L1e_Sir_TpuMacroAdjust
+ 0x100a7757 0x2 _L1e_Sir_SndTpuAdjust
+ 0x100a7759 0x8f _L1e_Sir_StartWinEvtCB
+ 0x100a77e8 0x60 _L1e_Sir_EndWinEvtCB
+ 0x100a7848 0x32 _L1e_Sir_RegWindowEvt
+ 0x100a787a 0x9e _L1e_Sir_CalNearRxRcv
+ 0x100a7918 0x5a _L1e_Sir_CheckRxRcv
+ 0x100a7972 0x39 _L1e_Sir_CellSync
+ 0x100a79ab 0x3d _L1e_Sir_CheckPaging
+ 0x100a79e8 0x7d _L1e_Sir_CheckGapPos
+ 0x100a7a65 0x5e _L1e_Sir_SerCellBackProc
+ 0x100a7ac3 0x7 _L1e_Sir_SetAbortSiProcState
+ 0x100a7aca 0x7 _L1e_Sir_GetAbortSiProcState
+ 0x100a7ad1 0x7 _L1e_Sir_SetSiDelayProcState
+ 0x100a7ad8 0x7 _L1e_Sir_GetSiDelayProcState
+ 0x100a7adf 0x7 _L1e_Sir_SetTimingNeibState
+ 0x100a7ae6 0x7 _L1e_Sir_GetTimingNeibState
+ 0x100a7aed 0x10 _L1e_Sir_GetMibReadStateInSib
+ 0x100a7afd 0x13 _L1e_Sir_GetSibState
+ 0x100a7b10 0x68 _L1e_Sir_GetNextSiWinTime
+ 0x100a7b78 0x1a _L1e_Sir_GetNeiBorSiState
+ 0x100a7b92 0x1e _L1e_Sir_GetNeiBorSibState
+ 0x100a7bb0 0x2d _L1e_Sir_GetNeiBorSib1ReportState
+ 0x100a7bdd 0x1c _L1e_Sir_GetSerSibState
+ 0x100a7bf9 0x12 _L1e_Sir_GetNeiBorSiBackState
+ 0x100a7c0b 0xd _L1e_Sir_CleanSiPreSyncState
+ 0x100a7c18 0x8 _L1e_Sir_GetSiSubFrmPat
+ 0x100a7c20 0xb9 _L1e_Sir_PreSyncProc
+ 0x100a7cd9 0x80 _L1e_Sir_PreSyncSched
+ 0x100a7d59 0x7 _L1e_Sir_SetSiSyncState
+ 0x100a7d60 0x7 _L1e_Sir_GetSiSyncState
+ 0x100a7d67 0x7 _L1e_Sir_SetSiSyncSchedState
+ 0x100a7d6e 0x7 _L1e_Sir_GetSiSyncSchedState
+ 0x100a7d75 0x28 _L1e_Sir_SiWakeUpProc
+ 0x100a7d9d 0x12 _L1e_Sir_GetBandWidth
+ 0x100a7daf 0xc5 _L1e_Sir_StartAnr
+ 0x100a7e74 0x8 _L1e_Anr_QueryEn
+ 0x100a7e7c 0x8 _L1e_Anr_GetState
+ 0x100a7e84 0x8 _L1e_Anr_ProcIndGet
+ 0x100a7e8c 0x1f _L1e_Anr_SetState
+ 0x100a7eab 0x2fd _L1e_Anr_SubFrmProc
+ 0x100a81a8 0x1c _L1e_Anr_BchProc
+ 0x100a81c4 0x6 _L1e_Anr_BchBackSerRx
+ 0x100a81ca 0x19 _L1e_Anr_AbortSi
+ 0x100a81e3 0x2f _L1e_Anr_Reset
+ 0x100a8212 0x11 _L1e_Anr_ProcDecSucc
+ 0x100a8223 0x7e _L1e_Anr_NeibLocalMrtr
+ 0x100a82a1 0xc1 _L1e_Anr_SwitchRF
+ 0x100a8362 0x1a _L1e_Anr_GetAutoGapState
+ 0x100a837c 0x49 _L1e_Anr_TpuMacroAdjust
+ 0x100a83c5 0xe _L1e_Anr_EnableRxRcv
+ 0x100a83d3 0x6e _L1e_Anr_CalNeibTime
+ 0x100a8441 0x2 _L1e_Anr_BchAbortProc
+ 0x100a8443 0xd _L1e_Anr_SibAbortProc
+ 0x100a8450 0x2c _L1e_Sir_Sib1MsgMonitor
+ 0x100a847c 0x59 _L1e_Sir_SiMsgMonitor
+ 0x100a84d5 0x29 _L1e_Sir_SibReportMonitor
+ 0x100a84fe 0x2c _L1e_Sir_StateMonitor
+ 0x100a852a 0x2f _L1e_Sir_ErrMonitor
+ 0x100a8559 0x5c _L1e_Sir_RfcMonitor
+ 0x100a85b5 0x93 _L1e_Sir_CellMonitor
+ 0x100a8648 0x38 _L1e_Sir_SibParaMonitor
+ 0x100a8680 0x43 _L1e_Sir_MibCnfMonitor
+ 0x100a86c3 0x2c _L1e_Sir_RxRcvCtrlMonitor
+ 0x100a86ef 0x5b _L1e_Sir_SchedParaMonitor
+ 0x100a874a 0x6e _L1e_Sir_StartWinMonitor
+ 0x100a87b8 0x6e _L1e_Sir_EndWinMonitor
+ 0x100a8826 0x24 _L1e_Sir_AnrStateMonitor
+ 0x100a884a 0x51 _L1e_Anr_StartMonitor
+ 0x100a889b 0x34 _L1e_Sir_AnrRfcMonitor
+ 0x100a88cf 0x32 _L1e_Anr_GapPrintf
+ 0x100a8901 0x2e _L1e_Anr_ErrProcMonitor
+ .text 0x100a892f 0x3f87 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x100a892f 0x27 _zPHY_emc_DvfsPatch
+ 0x100a8956 0x12 _zPHY_emc_PsMsgIdFindIndex
+ 0x100a8968 0x12 _zPHY_emc_PhyMsgIdFindIndex
+ 0x100a897a 0x12 _zPHY_emc_FindSynMsgIndex
+ 0x100a898c 0x12 _zPHY_emc_FindEmpLoc
+ 0x100a899e 0xf _zPHY_emc_FindAllSyncMsg
+ 0x100a89ad 0x26 _zPHY_emc_ClearSyncMsg
+ 0x100a89d3 0x131 _zPHY_emc_ReadSyncMsg
+ 0x100a8b04 0x55 _zPHY_emc_StubRecvSyncMsg
+ 0x100a8b59 0x1a _zPHY_emc_GetPs2PhyCF
+ 0x100a8b73 0x3a _zPHY_emc_LteAmtUpdateServeCellEarfch
+ 0x100a8bad 0x8 _l1e_SchedMcIdlePiCnt
+ 0x100a8bb5 0x17b _zPHY_emc_ProInitial
+ 0x100a8d30 0x11 _memcpy_Ps2PhySram
+ 0x100a8d41 0x35 _zPHY_emc_ProPs2PhyMsgLog
+ 0x100a8d76 0x5a _zPHY_emc_ProPhy2PsMsgLog
+ 0x100a8dd0 0x670 _zPHY_emc_ProSyncMsgSend
+ 0x100a9440 0x27e _zPHY_emc_ProDedicatedMsg
+ 0x100a96be 0x1a1 _zPHY_emc_ProPs2PhySyncMsg
+ 0x100a985f 0x41 _zPHY_emc_ProAbortAccessMsg
+ 0x100a98a0 0x1ad _zPHY_emc_ProAccessMsg
+ 0x100a9a4d 0x5 _zPHY_emc_ProTaCmdMsg
+ 0x100a9a52 0x12 _zPHY_emc_ProTaTimeStopMsg
+ 0x100a9a64 0x24c _zPHY_emc_ProPs2PhyMsgRouter
+ 0x100a9cb0 0x2c _zPHY_emc_WakeUpPS
+ 0x100a9cdc 0x1c _zPHY_emc_SendIcpToPS
+ 0x100a9cf8 0xd5 _zPHY_emc_ProPhy2PsMsgRouter
+ 0x100a9dcd 0x275 _zPHY_emc_ProReleaseFlow
+ 0x100aa042 0x1a8 _zPHY_emc_ProTimingCtrlFlow
+ 0x100aa1ea 0x1fd _zPHY_emc_ProTASchedFlow
+ 0x100aa3e7 0x46 _zPHY_emc_ProMacResetFlow
+ 0x100aa42d 0x57 _zPHY_emc_ProSubfrmTypeConfig
+ 0x100aa484 0x20d _zPHY_emc_ProResetFlow
+ 0x100aa691 0x207 _zPHY_emc_ProSetModeFlow
+ 0x100aa898 0x2b _zPHY_emc_ProShowLtePhyStateInfo
+ 0x100aa8c3 0x58 _zPHY_emc_ProShowLtePhySIDInfo
+ 0x100aa91b 0x11b _zPHY_emc_ProAfcConfig
+ 0x100aaa36 0x14 _zPHY_emc_UpdateIniFreq
+ 0x100aaa4a 0x12 _zPHY_emc_ReadIniFreq
+ 0x100aaa5c 0x53 _zPHY_emc_StartGapDelayPro
+ 0x100aaaaf 0x63 _zPHY_emc_GetRfTpuRegTime
+ 0x100aab12 0x25 _zPHY_emc_RegEvent
+ 0x100aab37 0x13 _zPHY_emc_DelEvent
+ 0x100aab4a 0x40 _zPHY_emc_RfDeal
+ 0x100aab8a 0xb _zPHY_emc_ResetProOn
+ 0x100aab95 0xb _zPHY_emc_RelProOn
+ 0x100aaba0 0x15 _zPHY_emc_InitScellInfo
+ 0x100aabb5 0x1 _zPHY_emc_ModifyScellExistFlag
+ 0x100aabb6 0x1 _zPHY_emc_ModifyScellActiveFlag
+ 0x100aabb7 0x1d _zPHY_emc_InitScellDefaultPara
+ 0x100aabd4 0x21 _zPHY_emc_ScellRatModeSet
+ 0x100aabf5 0x10 _zPHY_emc_FindFreeSCarrier
+ 0x100aac05 0x10 _zPHY_emc_AddSCarrier
+ 0x100aac15 0x29 _zPHY_emc_ReleaseSCarrier
+ 0x100aac3e 0x41 _zPHY_emc_ModifyScellInfo
+ 0x100aac7f 0x2 _zPHY_emc_ActiveScell
+ 0x100aac81 0x2 _zPHY_emc_DeactiveScell
+ 0x100aac83 0x2 _zPHY_emc_AutoDeactiveScell
+ 0x100aac85 0x2 _zPHY_emc_UpdateDeactInfo
+ 0x100aac87 0xa _zPHY_emc_IsAnyScellExist
+ 0x100aac91 0xa _zPHY_emc_IsAnyScellActive
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+ 0x100ab1aa 0x3d _zPHY_emc_ScellRFParaPrint
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+ 0x100ab431 0xd _L1e_SchedMc_GetCalcTimeState
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+ 0x100ab7cb 0x1a _L1e_SchedMc_CfgRfcRxClose
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+ 0x100ab969 0x9f _zPHY_emc_RdPs2PhyAsyncMsg
+ 0x100aba08 0x63 _zPHY_emc_CalTpuMrtrAdjType
+ 0x100aba6b 0x48 _zPHY_emc_RefreshPagePara
+ 0x100abab3 0x1b _zPHY_SendMsg
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+ 0x100abaea 0x62 _L1e_SchedMcGetCellInfo
+ 0x100abb4c 0xd _L1e_SchedMc_AbortSi
+ 0x100abb59 0xd _L1e_SchedMc_AbortSearch
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+ 0x100abb9d 0xd _L1e_SchedMc_StoreFreqScan
+ 0x100abbaa 0xd _L1e_SchedMc_StoreRapc
+ 0x100abbb7 0x3b _L1e_SchedMc_SndDelaySearch
+ 0x100abbf2 0x3b _L1e_SchedMc_SendDelayFreqScan
+ 0x100abc2d 0x1a _L1e_SchedMc_SndDelaySib
+ 0x100abc47 0x1a _L1e_SchedMc_SndDelaySi
+ 0x100abc61 0x10 _L1e_SchedMc_SndDelayRapc
+ 0x100abc71 0x1e _L1e_SchedMc_ReadTpuOffset
+ 0x100abc8f 0x10 _zPHY_emc_ATSetDrxCtrl
+ 0x100abc9f 0x83 _zPHY_emc_ATSetAndReadRlm
+ 0x100abd22 0x65 _zPHY_emc_ATSetAndReadCsi
+ 0x100abd87 0xc5 _zPHY_emc_ATSetAndReadUlpc
+ 0x100abe4c 0x72 _zPHY_emc_ATSetAntenna
+ 0x100abebe 0x56 _zPHY_emc_ATSetAndReadUeCategory
+ 0x100abf14 0x21 _zPHY_emc_ATCheckSinr
+ 0x100abf35 0x20 _zPHY_emc_ATCheckTmMode
+ 0x100abf55 0x4f _zPHY_emc_ATCheckMcsQmod
+ 0x100abfa4 0x6e _zPHY_emc_ATCheckHarqNack
+ 0x100ac012 0x32 _zPHY_emc_ATCheckThrougput
+ 0x100ac044 0x1f _zPHY_emc_ATCheckRssi
+ 0x100ac063 0x32 _zPHY_emc_ATCheckSinrRsrp
+ 0x100ac095 0x2a _zPHY_emc_ATCheckResidualBler
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+ 0x100ac187 0x3d _zPHY_emc_ExtraCheck
+ 0x100ac1c4 0x6f2 _zPHY_emc_ThreadEntry
+ .text 0x100ac8b6 0x4e8f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ 0x100ac8b6 0x16 _zPHY_ecsrc_LteAmtUpdateServeCellEarfch
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+ 0x100af8d0 0x21 _zPHY_ecsrc_OnCtrlSearchFreqScanCnf
+ 0x100af8f1 0x1c _zPHY_ecsrc_OnHandoverReq
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+ 0x100af96f 0x47 _zPHY_ecsrc_RunningCheck
+ 0x100af9b6 0x8d _zPHY_ecsrc_OnArfcnListInfo
+ 0x100afa43 0x47 _zPHY_amt_Lte_Set_EarfcnInfo
+ 0x100afa8a 0xf _L1e_csrc_HandoverSuccPro
+ 0x100afa99 0x1b _zPHY_ecsrc_StartProc
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+ 0x100afc13 0x15 _zPHY_ecsrc_InitProc
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+ 0x100afd49 0x5b _zPHY_ecsrc_Ctrl
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+ 0x100afdea 0xc8 _zEcsrc_PreEvent
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+ 0x100b0030 0x1e _zPHY_ecsrc_ReadSpeedSearctT
+ 0x100b004e 0x1d _zPHY_ecsrc_ReadCfoUpdateT
+ 0x100b006b 0x2a _zPHY_ecsrc_GetDestTime
+ 0x100b0095 0x1c _zPHY_ecsrc_CalDestTimeOffset
+ 0x100b00b1 0x19 _zPHY_ecsrc_GetNonHighPrioFreqNum
+ 0x100b00ca 0x19 _zPHY_ecsrc_GetHighPrioFreqNum
+ 0x100b00e3 0x13 _zPHY_ecsrc_GetReportNum
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+ 0x100b019a 0x22 _zPHY_ecsrc_IsNonHighPrioWorkDrx
+ 0x100b01bc 0xaa _zPHY_ecsrc_NeedWork
+ 0x100b0266 0x54 _zPHY_ecsrc_CalcInitDrxNum
+ 0x100b02ba 0x7f _zPHY_ecsrc_CalcWorkDrxNum
+ 0x100b0339 0x22 _zPHY_ecsrc_NeedInterSearch
+ 0x100b035b 0x9 _zPHY_ecsrc_NeedInterMeas
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+ 0x100b03b6 0x3f _zPHY_ecsrc_FreqIndexAcc
+ 0x100b03f5 0x37 _zPHY_ecsrc_IsLastFreqInDrx
+ 0x100b042c 0x72 _L1e_csrc_SRCellRank
+ 0x100b049e 0x9a _L1e_csrc_SaveSRCellInfo
+ 0x100b0538 0x52 _L1e_csrc_SetSRCellInfo
+ 0x100b058a 0x121 _L1e_csrc_GetMobileCxtFlag
+ 0x100b06ab 0x47 _zPHY_ecsrc_CtrlIdleIntraMeasEndEventNew
+ 0x100b06f2 0x37 _zPHY_ecsrc_GetReportDrxNum
+ 0x100b0729 0x2 _zPHY_ecsrc_EverTrue
+ 0x100b072b 0x10 _zPHY_ecsrc_StartDelayTimer
+ 0x100b073b 0x9 _zPHY_ecsrc_WaitEvent
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+ 0x100b0761 0x1f _zPHY_ecsrc_SchedStop
+ 0x100b0780 0x8 _zPHY_ecsrc_SchedStart
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+ 0x100b079d 0xbc _zPHY_ecsrc_OnStartPi
+ 0x100b0859 0x63 _zPHY_ecsrc_OnEndPi
+ 0x100b08bc 0x9b _zPHY_ecsrc_ReportOneFreq
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+ 0x100b09d3 0x2f _zPHY_ecsrc_ReportInra
+ 0x100b0a02 0x57 _zPHY_ecsrc_DoReportIner
+ 0x100b0a59 0x11 _zPHY_ecsrc_ReportInter
+ 0x100b0a6a 0x12 _zPHY_ecsrc_OneFreqModeWork
+ 0x100b0a7c 0x1a _zPHY_ecsrc_OneFreqIntraWork
+ 0x100b0a96 0x27 _zPHY_ecsrc_IntraSearchInLowSnr
+ 0x100b0abd 0x33 _zPHY_ecsrc_FixedStrongSearch
+ 0x100b0af0 0x8 _zPHY_ecsrc_GetFixedStrongSearchFlag
+ 0x100b0af8 0x30 _zPHY_ecsrc_NeedSearchInLowSnr
+ 0x100b0b28 0x25 _zPHY_ecsrc_NeedSearchInRA
+ 0x100b0b4d 0x14 _zPHY_ecsrc_OneFreqInterWork
+ 0x100b0b61 0x11 _zPHY_ecsrc_GerFreqNumPerDrx
+ 0x100b0b72 0x3c _zPHY_ecsrc_NextInterFreqInDrx
+ 0x100b0bae 0x23 _zPHY_ecsrc_IntraWorkInDrx
+ 0x100b0bd1 0x20 _zPHY_ecsrc_InterFinishInDrx
+ 0x100b0bf1 0x35 _zPHY_ecsrc_RecordInterDoneInDrx
+ 0x100b0c26 0x65 _zPHY_ecsrc_InterSchedInitPerDrx
+ 0x100b0c8b 0x9b _zPHY_ecsrc_GetIntraSearchTime
+ 0x100b0d26 0x2e _zPHY_ecsrc_GetInterSearchTime
+ 0x100b0d54 0x7f _zPHY_ecsrc_GetIntraMeasTime
+ 0x100b0dd3 0xa1 _zPHY_ecsrc_GetInterMeasTime
+ 0x100b0e74 0x4d _zPHY_ecsrc_GetIntraWorkTime
+ 0x100b0ec1 0x15 _zPHY_ecsrc_GetInterWorkTime
+ 0x100b0ed6 0x69 _zEcsr_GetWorkTimeInCurDrx
+ 0x100b0f3f 0x71 _zPHY_ecsrc_ChangeMeasMode
+ 0x100b0fb0 0x36 _zPHY_ecsrc_IntraMeasStart
+ 0x100b0fe6 0x3 _zPHY_ecsrc_InterMeasStart
+ 0x100b0fe9 0x15 _zPHY_ecsrc_IntraSearchStart
+ 0x100b0ffe 0xd _zPHY_ecsrc_SetIntraWorkTime
+ 0x100b100b 0x1e _zPHY_ecsrc_SetInterWorkTime
+ 0x100b1029 0x12 _zPHY_ecsrc_ServCellStart
+ 0x100b103b 0x26 _zPHY_ecsrc_SearchInMeasConfig
+ 0x100b1061 0x21 _zPHY_ecsrc_ReadIndexInSchedContext
+ 0x100b1082 0x21 _zPHY_ecsrc_IntraFreqStart
+ 0x100b10a3 0x11c _zPHY_ecsrc_InterFreqStart
+ 0x100b11bf 0xb4 _zPHY_ecsrc_OneFreqStart
+ 0x100b1273 0x26 _zPHY_ecsrc_NeedSchedInter
+ 0x100b1299 0x1 _zPHY_ecsrc_BeforeInter
+ 0x100b129a 0x15 _zPHY_ecsrc_BeforeOneFreq
+ 0x100b12af 0x24 _zPHY_ecsrc_NeedInitial
+ 0x100b12d3 0x49 _zPHY_ecsrc_ChangeMeasPeriodIdle
+ 0x100b131c 0x32 _zPHY_ecsrc_ReportNoInactiveTime
+ 0x100b134e 0x7 _zPHY_ecsrc_NeedAdjustBndFrmCfo
+ 0x100b1355 0x5e _zPHY_ecsrc_AdjustBndFrmCfo
+ 0x100b13b3 0x15 _zPHY_ecsrc_SetShortDrxState
+ 0x100b13c8 0x12 _zPHY_ecsrc_CfgRfcRxOffset
+ 0x100b13da 0x2b _zPHY_ecsrc_AdjustSrvTpu
+ 0x100b1405 0x7 _zPHY_ecsrc_BackupCFOFreqOffset
+ 0x100b140c 0x8 _l1e_csrc_GetDrxCnt
+ 0x100b1414 0x3b _zPHY_ecsrc_DrxReStartSearchMeas
+ 0x100b144f 0x2a _zPHY_ecsrc_ReadPrio
+ 0x100b1479 0x85 _zPHY_ecsrc_WakeupPs
+ 0x100b14fe 0x8 _L1e_csrc_GetCurCtx
+ 0x100b1506 0x8 _L1e_csrc_GetMeasBit
+ 0x100b150e 0x94 _L1e_csrc_TempRead
+ 0x100b15a2 0xd0 _L1e_ecsrc_UpdateBackBchBnd
+ 0x100b1672 0xa _L1e_csrc_AtZepcgSetLowPower
+ 0x100b167c 0x20 _L1e_csrc_AtZepcgSetPhyCfg
+ 0x100b169c 0x6b _L1e_csrc_GetFreqOffset
+ 0x100b1707 0x29 _L1e_csrc_SetDisableAfcReloadFlag
+ 0x100b1730 0x15 _L1e_csrc_SetScanFailNum
+ .text 0x100b1745 0x212 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_fsm.o)
+ 0x100b1745 0x212 _zPHY_emc_ProPhyStateCtrl
+ .text 0x100b1957 0xb29 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_db.o)
+ 0x100b1957 0x7 _zPHY_ecsrc_SatAdd
+ 0x100b195e 0x9 _zPHY_ecsrc_SatSub
+ 0x100b1967 0x18 _zPHY_ecsrc_CellDatabaseReset
+ 0x100b197f 0x2b _zPHY_ecsrc_GetCellInfo
+ 0x100b19aa 0x48 _zPHY_ecsrc_GetAddCell
+ 0x100b19f2 0x61 _zPHY_ecsrc_DeleteCell
+ 0x100b1a53 0x4d _zPHY_ecsrc_DeleteOldCell
+ 0x100b1aa0 0x69 _zPHY_ecsrc_DeleteAllCell
+ 0x100b1b09 0x4d _zPHY_ecsrc_DeleteNoCfgCell
+ 0x100b1b56 0x1a _L1e_Csrc_IsServcell
+ 0x100b1b70 0x13 _L1e_Csrc_IsServcellEarfcn
+ 0x100b1b83 0x42 _zPHY_ecsrc_FindCell
+ 0x100b1bc5 0x29 _zPHY_ecsrc_ClearOtherCell
+ 0x100b1bee 0x12 _zPHY_ecsrc_FindServCell
+ 0x100b1c00 0x4e _zPHY_ecsrc_CtrlICPWriteMeasPriority
+ 0x100b1c4e 0x9e _zPHY_ecsrc_SearchAddCellToDatabase
+ 0x100b1cec 0x8d _zPHY_ecsrc_CtrlRefreshDataBase
+ 0x100b1d79 0x54 _zPHY_ecsrc_CtrlUpdateBoundary
+ 0x100b1dcd 0x49 _zPHY_ecsrc_AdjustCellAge
+ 0x100b1e16 0x3a _zPHY_ecsrc_CtrlGetStrongestCell
+ 0x100b1e50 0xc _zPHY_ecsrc_ScellDatabaseReset
+ 0x100b1e5c 0x44 _zPHY_ecsrc_CtrlCellDatabaseAging
+ 0x100b1ea0 0x2a _zPHY_ecsrc_ClearSearchNewCellFlag
+ 0x100b1eca 0x2e _zPHY_ecsrc_ClearAppointCellFlag
+ 0x100b1ef8 0x23 _zPHY_ecsrc_ClearValidCellFlag
+ 0x100b1f1b 0x22 _zEcsrc_FindFreq
+ 0x100b1f3d 0x13 _zEcsrc_IsIcp
+ 0x100b1f50 0x40 _zEcsrc_GetMeasBand
+ 0x100b1f90 0x19 _zEcsrc_GetMeasTimes
+ 0x100b1fa9 0x2c _zPHY_ecsrc_ClearFreqInfo
+ 0x100b1fd5 0x34 _zPHY_ecsrc_ClearNoCfgFreqInfo
+ 0x100b2009 0x1f _zPHY_ecsrc_FindFreqInfo
+ 0x100b2028 0x60 _zPHY_ecsrc_ExChangeFreqInfo
+ 0x100b2088 0x9e _zPHY_ecsrc_SaveFreqInfo
+ 0x100b2126 0x4d _zPHY_ecsrc_ReadRsrpCaliInfo
+ 0x100b2173 0x4a _zPHY_ecsrc_UpdateTimeOffset
+ 0x100b21bd 0x41 _zPHY_ecsrc_RecoverTimeOffset
+ 0x100b21fe 0x48 _zPHY_ecsrc_ChangeTimeOffset
+ 0x100b2246 0x23 _zPHY_ecsrc_ReadTimeOffset
+ 0x100b2269 0x1e _zPHY_ecsrc_GetCellNum
+ 0x100b2287 0xb _L1e_Csrc_UpdateServCell
+ 0x100b2292 0x10 _L1e_Csrc_ServCellChange
+ 0x100b22a2 0xc _L1e_Csrc_ChangeNeiConfigFlag
+ 0x100b22ae 0x7e _zPHY_ecsrc_DealSrvBndFrmCfo
+ 0x100b232c 0x25 _L1e_csrc_SetMeasState
+ 0x100b2351 0x87 _zPHY_ecsrc_GetMeasCell
+ 0x100b23d8 0x4b _zPHY_ecsrc_GetMeasCellNum
+ 0x100b2423 0x12 _zPHY_ecsrc_GetFddBufferMode
+ 0x100b2435 0x1e _zPHY_ecsrc_GetIndexInFreqMeasMode
+ 0x100b2453 0x11 _zPHY_ecsrc_GetMeasAge
+ 0x100b2464 0x1c _zPHY_ecsrc_GetFreqOffset
+ .text 0x100b2480 0x2bfc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ 0x100b2480 0xb _zPHY_ecsrc_CtrlShiftSlaveFunState
+ 0x100b248b 0x14 _zPHY_ecsrc_CtrlShiftSlaveSynState
+ 0x100b249f 0xa _zPHY_ecsrc_MulmSetRfWorkSet
+ 0x100b24a9 0x65 _zPHY_ecsrc_MulmCfgRFCModem7510
+ 0x100b250e 0x5f _zPHY_ecsrc_MulmRegRFStartClose
+ 0x100b256d 0xf7 _zPHY_ecsrc_MulmIratIdlePeriodRepProcess7510
+ 0x100b2664 0x44 _zEcsr_UpdateSiReadState
+ 0x100b26a8 0x35 _zPHY_ecsrc_MulmCtrlSetMode
+ 0x100b26dd 0xa3 _zPHY_ecsrc_MulmSlaveReset
+ 0x100b2780 0x14 _zPHY_ecsrc_MulmFreqListConfigProcess
+ 0x100b2794 0x60 _L1e_Mulm_ReadSearchT
+ 0x100b27f4 0x58 _L1e_Mulm_NeedSearch
+ 0x100b284c 0x34 _L1e_Mulm_NeedMeas
+ 0x100b2880 0x47 _zPHY_ecsrc_MulmIratMeasScheduleProcess
+ 0x100b28c7 0x3c _zPHY_ecsrc_MulmIratAddMeasReport
+ 0x100b2903 0x77 _zPHY_ecsrc_MulmMeasReset
+ 0x100b297a 0xe5 _zPHY_ecsrc_MulmIratMeasConfigProcess
+ 0x100b2a5f 0x72 _zPHY_ecsrc_MulmReportFreqMeasResult
+ 0x100b2ad1 0x5d _zPHY_ecsrc_MulmIratMeasResultHandle
+ 0x100b2b2e 0x9 _zPHY_ecsrc_MulmIratResetMeasCnt
+ 0x100b2b37 0x8d _zPHY_ecsrc_MulmIratMeasReportIntHandle
+ 0x100b2bc4 0xaf _zPHY_ecsrc_MulmIratMeasFilter
+ 0x100b2c73 0x88 _zPHY_ecsrc_MulmIratFreqFilter
+ 0x100b2cfb 0x72 _zPHY_ecsrc_MulmIratUpdateMeasInd
+ 0x100b2d6d 0x34 _zPHY_ecsrc_MulmIratUpdateFreqReport
+ 0x100b2da1 0x40 _zPHY_ecsrc_MulmIratSetFilterFact
+ 0x100b2de1 0x2a _zPHY_ecsrc_MulmIratReadPrio
+ 0x100b2e0b 0x55 _zPHY_ecsrc_MulmIratSearchMeasureStartSchedule
+ 0x100b2e60 0x17 _zPHY_ecsrc_MulmSlaveCfgRfcMeas1Offset7510
+ 0x100b2e77 0x37 _zPHY_ecsrc_MulmSlaveGapStartOffsetCfg7510
+ 0x100b2eae 0x43 _zPHY_ecsrc_MulmSlaveGapEndOffsetCfg7510
+ 0x100b2ef1 0x36 _zPHY_ecsrc_MulmRegTpuSingleEvent
+ 0x100b2f27 0x63 _zPHY_ecsrc_MulmGetGapType
+ 0x100b2f8a 0x28 _zPHY_ecsrc_MulmRegTpuEvent
+ 0x100b2fb2 0xed _zPHY_ecsrc_MulmIratGapSchedFlow
+ 0x100b309f 0x62 _zPHY_ecsrc_ReRegistGapConfigDelag
+ 0x100b3101 0x62 _zPHY_ecsrc_MulmIratGapSchedFlowProtect
+ 0x100b3163 0x56 _zPHY_ecsrc_MulmBlackCellFilter
+ 0x100b31b9 0x60 _zPHY_ecsrs_MulmRemainTimeInGap
+ 0x100b3219 0x2d _zPHY_ecsrs_MulmProtectTimeBeforeGap
+ 0x100b3246 0x1a _zPHY_ecsrc_MulmCalMeasTime
+ 0x100b3260 0x5b _zPHY_ecsrc_MulmCalSearchTime
+ 0x100b32bb 0x104 _zPHY_ecsrc_MulmTpuCnf
+ 0x100b33bf 0x13 _zPHY_ecsrc_MulmCsr2TpuUpdateCounterCnfHandle
+ 0x100b33d2 0x4a _zPHY_ecsrc_MulmSlavePlmnSearchStart
+ 0x100b341c 0x2a _zPHY_ecsrc_MulmSlavePlmnSearchFinHandle
+ 0x100b3446 0x42 _zPHY_ecsrc_MulmSlavePlmnMeasureTimerIntHandle
+ 0x100b3488 0x2e _zPHY_ecsrc_MulmSlavePlmnAbortCellSearchHandle
+ 0x100b34b6 0x45 _zPHY_ecsrs_MulmPlmnSib1InGap
+ 0x100b34fb 0x45 _zPHY_ecsrc_MulmRegNotSynSubFrameInt
+ 0x100b3540 0x2c _zPHY_ecsrc_MulmRegCsrmSfInt
+ 0x100b356c 0xaa _zPHY_ecsrc_MulmIratGapStartTpuIntHandle
+ 0x100b3616 0x20 _zPHY_ecsrc_MulmUnRegistSearchMeasInt
+ 0x100b3636 0x42 _zPHY_ecsrc_MulmIratGapEndTpuIntHandle
+ 0x100b3678 0x50 _zPHY_ecsrc_MulmSlaveAbortGapProtectTimerEnable
+ 0x100b36c8 0x48 _zPHY_ecsrc_MulmIratMeasDoneHandle
+ 0x100b3710 0x6e _zPHY_ecsrc_MulmIratAbortGapHandle
+ 0x100b377e 0x68 _zPHY_ecsrc_MulmIratAbortGapProtectTimerHandle
+ 0x100b37e6 0x97 _zPHY_ecsrs_MulmIratGapPositionCheck
+ 0x100b387d 0x27 _zPHY_ecsrs_MulmGapCoverTime
+ 0x100b38a4 0x42 _zPHY_ecsrm_MulmPbchStartCheck
+ 0x100b38e6 0x27 _zPHY_ecsrs_MulmEnableRfcEventTable
+ 0x100b390d 0x26 _zPHY_ecsrs_Mulm6MSRfcMeas1GapOffsetCfg
+ 0x100b3933 0x64 _zPHY_ecsrs_MulmRfOpenNo
+ 0x100b3997 0x49 _zPHY_ecsrs_MulmConfigSynState
+ 0x100b39e0 0x56 _zPHY_ecsrs_MulmEnableRF
+ 0x100b3a36 0x45 _zPHY_emc_MulmCsrRfStartDeal
+ 0x100b3a7b 0x62 _zPHY_emc_MulmCsrRfEndDeal
+ 0x100b3add 0x20 _zPHY_emc_DealRFCloseEvent
+ 0x100b3afd 0x2d _zPHY_ecsrc_CtrlMulmDbAging
+ 0x100b3b2a 0xf _zPHY_ecsrc_CtrlSetMulmSlaveSearchMeasAgeInfor
+ 0x100b3b39 0x97 _zPHY_ecsrc_CtrlMulmRefreshDataBase
+ 0x100b3bd0 0x50 _zPHY_ecsrs_MulmTpuAdjCheckTime
+ 0x100b3c20 0x2f _zPHY_ecsrs_MulmIcpPssBoundryAdj
+ 0x100b3c4f 0x1a _zPHY_ecsrs_MulmPssTpuCnf
+ 0x100b3c69 0x46 _zPHY_ecsrs_MulmIsPssWorkTime
+ 0x100b3caf 0xa0 _zPHY_ecsrs_MulmGetPssHwStartTime
+ 0x100b3d4f 0x53 _zPHY_ecsrs_MulmPssCfg
+ 0x100b3da2 0xb _zPHY_ecsrs_MulmPssConfig
+ 0x100b3dad 0x16 _zPHY_ecsrs_MulmPssGapCoverTime
+ 0x100b3dc3 0x68 _zPHY_ecsrc_MulmGetValidCellFrameBoundry7510
+ 0x100b3e2b 0x3f _zPHY_ecsrc_MulmTpuAdjPro
+ 0x100b3e6a 0x27 _zPHY_ecsrc_MulmBoundryAdj
+ 0x100b3e91 0x7f _zPHY_ecsrs_MulmCheckTpuAdj
+ 0x100b3f10 0x28 _zPHY_ecsrs_MulmStartTpuAdj
+ 0x100b3f38 0xf3 _zPHY_ecsrc_MulmIratSearchStartSchedule7510
+ 0x100b402b 0x56 _zPHY_emc_MulmSlaveMeasureReportProtect
+ 0x100b4081 0x190 _zPHY_emc_MulmSlaveMeasureFlow
+ 0x100b4211 0x7 _zPHY_ecsrs_MulmIratFSPssGapPositionCheck
+ 0x100b4218 0x17 _zPHY_ecsrs_MulmIratCheckGapTime
+ 0x100b422f 0x3d _zPHY_ecsrs_MulmIratPssTimeCheck
+ 0x100b426c 0x4b _zPHY_ecsrs_MulmIratSssGapPositionCheck
+ 0x100b42b7 0x39 _zPHY_ecsrs_MulmAgcStable
+ 0x100b42f0 0x15 _L1e_mulm_CfoAccNum
+ 0x100b4305 0x87 _zPHY_ecsrs_MulmCfoConfig
+ 0x100b438c 0x1e _zPHY_ecsrs_MulmSssCfg
+ 0x100b43aa 0x8b _zPHY_ecsrs_MulmIsTddSssWorkTime
+ 0x100b4435 0x18 _zPHY_ecsrs_MulmStartICSPSubFrameInt
+ 0x100b444d 0x13 _zPHY_ecsrs_MulmStartSynSearchSubFrameInt
+ 0x100b4460 0x40 _zPHY_ecsrs_MulmGapCoverTime7510
+ 0x100b44a0 0x136 _zPHY_ecsrs_MulmIsFddSssWorkTime
+ 0x100b45d6 0x1d _zPHY_ecsrs_MulmGetMeasBaseTime
+ 0x100b45f3 0x154 _zPHY_ecsrs_MulmCfoCheckTime
+ 0x100b4747 0xa9 _zPHY_ecsrs_MulmIsValidTime
+ 0x100b47f0 0xfd _zPHY_ecsrs_MulmCheckOpenTime
+ 0x100b48ed 0xb3 _zPHY_ecsrm_MulmBuffCheckOpenTimePeriod
+ 0x100b49a0 0x5a _zPHY_ecsrs_MulmGapCoverCheck
+ 0x100b49fa 0x47 _zPHY_ecsrs_MulmGapCoverBufferCheck
+ 0x100b4a41 0x14 _zPHY_ecsrs_MulmIsShortGap
+ 0x100b4a55 0x16 _zPHY_ecsrs_MulmGetFreqIndex
+ 0x100b4a6b 0x2e _zPHY_ecsrc_MulmIratClearPreFilter
+ 0x100b4a99 0x26 _zPHY_ecsrs_AbsModSub
+ 0x100b4abf 0xc _zPHY_ecsrs_MulmCsBefore
+ 0x100b4acb 0x26 _zPHY_ecsrs_MulmCsNeedCs
+ 0x100b4af1 0xc _zPHY_ecsrs_MulmCsNeedAgc
+ 0x100b4afd 0x37 _zPHY_ecsrs_MulmCsBeforeAgc
+ 0x100b4b34 0xb _zPHY_ecsrs_MulmCsIsOnAgc
+ 0x100b4b3f 0x1c _zPHY_ecsrs_MulmCsAgcProc
+ 0x100b4b5b 0x8 _zPHY_ecsrs_MulmCsAgcProcEnd
+ 0x100b4b63 0xb _zPHY_ecsrs_MulmCsNeedPss
+ 0x100b4b6e 0x2d _zPHY_ecsrs_MulmCsBeforePss
+ 0x100b4b9b 0x18 _zPHY_ecsrs_MulmCsIsOnPss
+ 0x100b4bb3 0x41 _zPHY_ecsrs_MulmCsPssProc
+ 0x100b4bf4 0x43 _zPHY_ecsrs_MulmCsPssProcEnd
+ 0x100b4c37 0x14 _zPHY_ecsrs_MulmCsNeedTpuAdj1
+ 0x100b4c4b 0xc _zPHY_ecsrs_MulmCsNeedTpuAdj
+ 0x100b4c57 0xc _zPHY_ecsrs_MulmCsTpuAdjProc
+ 0x100b4c63 0x1a _zPHY_ecsrs_MulmCsTpuAdjProc2
+ 0x100b4c7d 0xe _zPHY_ecsrs_MulmCsTpuCheck
+ 0x100b4c8b 0xc _zPHY_ecsrs_MulmCsNeedCfo
+ 0x100b4c97 0x15 _zPHY_ecsrs_MulmCsBeforeCfo
+ 0x100b4cac 0x25 _zPHY_ecsrs_MulmCsBeforeCfoOnce
+ 0x100b4cd1 0x20 _zPHY_ecsrs_MulmCsIsOnCfo
+ 0x100b4cf1 0x1d _zPHY_ecsrs_MulmCsNeedMoreCfo
+ 0x100b4d0e 0x30 _zPHY_ecsrs_MulmCsCfoProc
+ 0x100b4d3e 0x4a _zPHY_ecsrs_MulmCsCfoOnceProcEnd
+ 0x100b4d88 0x8 _zPHY_ecsrs_MulmCsCfoProcEnd
+ 0x100b4d90 0x31 _zPHY_ecsrs_MulmLteCordicConfig
+ 0x100b4dc1 0x12 _zPHY_ecsrs_MulmGetLteCordicValue
+ 0x100b4dd3 0xc _zPHY_ecsr_MulmCordicAdjust
+ 0x100b4ddf 0x5a _zPHY_ecsr_MulmToLteCfo
+ 0x100b4e39 0x8 _zPHY_ecsr_MulmReadCordicValue
+ 0x100b4e41 0x8 _zPHY_ecsr_MulmWriteCordicValue
+ 0x100b4e49 0xc _zPHY_ecsrs_MulmCsNeedSss
+ 0x100b4e55 0x28 _zPHY_ecsrs_MulmCsBeforeSss
+ 0x100b4e7d 0x29 _zPHY_ecsrs_MulmCsIsOnSss
+ 0x100b4ea6 0x18 _zPHY_ecsrs_MulmIsSssWorkTime
+ 0x100b4ebe 0x47 _zPHY_ecsrs_MulmCsSssProc
+ 0x100b4f05 0x50 _zPHY_ecsrs_MulmCsSssProcEnd
+ 0x100b4f55 0x75 _zPHY_ecsrs_MulmCsProEnd
+ 0x100b4fca 0x8 _zPHY_ecsrc_MulmSetRfState
+ 0x100b4fd2 0x25 _zPHY_ecsrc_MulmSchedCheck
+ 0x100b4ff7 0x15 _zPHY_ecsrs_MulmCheckReadTime
+ 0x100b500c 0x66 _zPHY_ecsrs_MulmIsSssSchedSubFrm
+ 0x100b5072 0xa _zPHY_ecsrs_Wait
+ .text 0x100b507c 0xf3b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ 0x100b507c 0x1a _zPHY_ecsrc_InitCellSearchProc
+ 0x100b5096 0x1c _zPHY_ecsrc_IdleCellSearchProc
+ 0x100b50b2 0x4d _zPHY_ecsrc_SetCellSearchCnf
+ 0x100b50ff 0x7c _zPHY_ecsrc_InitAppointedCS
+ 0x100b517b 0x16 _zPHY_ecsrc_InitNotAppointedCS
+ 0x100b5191 0x46 _zPHY_ecsrc_CtrlSssUpdateProcess
+ 0x100b51d7 0x42 _zPHY_ecsrc_ReSearchOrReportCell
+ 0x100b5219 0x37 _zPHY_ecsrc_SetInitMeasTime
+ 0x100b5250 0x6b _zPHY_ecsrc_CtrlICPTimeEvent
+ 0x100b52bb 0x3f _zPHY_ecsrc_CtrlICPTpuAdjust
+ 0x100b52fa 0xaf _zPHY_ecsrc_CtrlICPMeasTimeEvent
+ 0x100b53a9 0x3c _zPHY_ecsrc_SortCellSearchCnf
+ 0x100b53e5 0x4a _zPHY_ecsrc_SetReportCellList
+ 0x100b542f 0x87 _zPHY_ecsrc_CtrlICPReportResult
+ 0x100b54b6 0xc2 _zPHY_ecsrc_CtrlIcpBchHandle
+ 0x100b5578 0x4f _zPHY_ecsrc_CtrlBchDecodeEvent
+ 0x100b55c7 0x48 _zPHY_ecsrc_CtrlIcpReportNoCell
+ 0x100b560f 0x62 _zPHY_ecsrc_CtrlIcpTimeEndEvent
+ 0x100b5671 0x29 _zPHY_ecsrc_CfgSynTable
+ 0x100b569a 0x36 _zPHY_ecsrc_ReConstructRxPara
+ 0x100b56d0 0x2d _zPHY_ecsrc_ConfirmRxPara
+ 0x100b56fd 0x35 _zPHY_ecsrc_PlmnBackupSrvCell
+ 0x100b5732 0x86 _zPHY_ecsrc_PlmnResumeDlRfcEnableEvent
+ 0x100b57b8 0xcc _zPHY_ecsrc_PlmnPhyResultReport
+ 0x100b5884 0x54 _zPHY_ecsrc_FreqScanResultReportHandle
+ 0x100b58d8 0x43 _zPHY_ecsrc_PlmnResumeSrvCellTPU
+ 0x100b591b 0x3b _zPHY_ecsrc_PlmnCurTime2PiTimeDistance
+ 0x100b5956 0x10 _zPHY_ecsrc_PlmnHasEnoughTime
+ 0x100b5966 0x30 _zPHY_ecsrc_PlmnProcessPeriodicalTpuIntIn
+ 0x100b5996 0x24 _zPHY_ecsrc_PlmnResumeSrvCellNew
+ 0x100b59ba 0x31 _zPHY_ecsrc_PlmnSearchResultHandleNew
+ 0x100b59eb 0x37 _zPHY_ecsrc_PlmnFreqScanReqPro
+ 0x100b5a22 0x15 _zPHY_ecsrc_PlmnCellSearchReqPro
+ 0x100b5a37 0x72 _zPHY_ecsrc_PlmnPeriodTpuInPro
+ 0x100b5aa9 0x33 _L1e_csrc_CalcProTime
+ 0x100b5adc 0x1d _zPHY_ecsrc_PlmnGetPhaseMinTime
+ 0x100b5af9 0xa2 _zPHY_ecsrc_PlmnBackupAfc
+ 0x100b5b9b 0x1c _zPHY_ecsrc_PlmnResumeAgcAFc
+ 0x100b5bb7 0xf _zPHY_ecsrc_PlmnPhasePro
+ 0x100b5bc6 0x4a _zPHY_ecsrc_SearchPhaseCheck
+ 0x100b5c10 0xa _zPHY_ecsrc_PlmnReadPhase
+ 0x100b5c1a 0xf _zPHY_ecsrc_PlmnPhaseShift
+ 0x100b5c29 0x3c _zPHY_ecsrc_PlmnPhaseContinue
+ 0x100b5c65 0x28 _zPHY_ecsrc_SearchDone
+ 0x100b5c8d 0x38 _zPHY_ecsrc_SendCellSearchReq
+ 0x100b5cc5 0x9 _zPHY_ecsrc_RestartCellSearch
+ 0x100b5cce 0xd4 _zPHY_ecsrc_CtrlAbortICPProcess
+ 0x100b5da2 0x35 _zPHY_ecsrc_BchCellInfoBak
+ 0x100b5dd7 0x155 _l1e_SchedCsrcGetOverlapInfo
+ 0x100b5f2c 0x53 _zPHY_ecsrc_ProWriteBch2CsrDb
+ 0x100b5f7f 0x38 _zPHY_ecsrc_ProBackBchInfo
+ .text 0x100b5fb7 0x379 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
+ 0x100b5fb7 0x35 _CheckThread
+ 0x100b5fec 0x6b _NextStep
+ 0x100b6057 0x33 _RunProc
+ 0x100b608a 0x12 _RunFun0
+ 0x100b609c 0x14 _RunFun0P1
+ 0x100b60b0 0xc _RunFun1
+ 0x100b60bc 0x15 _RunOpt
+ 0x100b60d1 0x4c _RunWhile
+ 0x100b611d 0x27 _RunEnd
+ 0x100b6144 0x1c _RunDo
+ 0x100b6160 0x43 _RunWhile1
+ 0x100b61a3 0x15 _RunLoop0
+ 0x100b61b8 0x15 _RunLoop1
+ 0x100b61cd 0x25 _RunReturnIf
+ 0x100b61f2 0x8b _DispatchStep
+ 0x100b627d 0x26 _RunSync
+ 0x100b62a3 0x4c _EventHandlerOnce
+ 0x100b62ef 0x16 _EventHandler
+ 0x100b6305 0x2b _StartProc
+ .text 0x100b6330 0x1ff T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ 0x100b6330 0xc _L1e_SchedMbmsInit
+ 0x100b633c 0x48 _L1e_SchedMbmsProcMsg
+ 0x100b6384 0x20 _L1e_SchedMbmsGenMbsfnSfBmp
+ 0x100b63a4 0xe3 _L1e_SchedMbmsGenAllocSfBmp
+ 0x100b6487 0xd _L1e_SchedMbmsGetNextTimeInfo
+ 0x100b6494 0x31 _L1e_SchedMbmsProcMchRecv
+ 0x100b64c5 0xb _L1e_SchedMbmsGetMbsfnInd
+ 0x100b64d0 0xb _L1e_SchedMbmsSetMbsfnFlag
+ 0x100b64db 0xb _L1e_SchedMbmsSetMbmsFlag
+ 0x100b64e6 0xd _L1e_SchedMbmsGetMbsfnFlag
+ 0x100b64f3 0xf _L1e_SchedMbmsGetMbmsFlag
+ 0x100b6502 0x2 _L1e_SchedMBmsGetMbsfnAllocNum
+ 0x100b6504 0xd _L1e_SchedMbmsGetAreaIndex
+ 0x100b6511 0xd _L1e_SchedMbmsGetNonMbsfnLen
+ 0x100b651e 0x11 _L1e_SchedMBmsGetConfigNum
+ .text 0x100b652f 0x141c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ 0x100b652f 0x44 _zPHY_DrxPreSyncStartCtrl
+ 0x100b6573 0x1f1 _zPHY_emc_ProDrxSchedFlow
+ 0x100b6764 0x97 _zPHY_emc_DrxInactivityTimerCtrl
+ 0x100b67fb 0x73 _zPHY_emc_DrxOnDurationTimerCtrl
+ 0x100b686e 0x128 _zPHY_emc_DrxRttTimerAndDlHarqRetranTimerCtrl
+ 0x100b6996 0xf9 _zPHY_emc_DrxUlHarqCtrl
+ 0x100b6a8f 0x31 _zPHY_emc_ProDrxTpuEventSchedFlow
+ 0x100b6ac0 0x88 _zPHY_emc_DrxCalcOndurationTimerStartTime
+ 0x100b6b48 0x64 _zPHY_emc_ProDrxCallBackFunction
+ 0x100b6bac 0x62 _zPHY_emc_RegOndurStartEvent
+ 0x100b6c0e 0x9e _zPHY_emc_RegShortDrxCycleEvent
+ 0x100b6cac 0x64 _zPHY_emc_CurSubFrDRXStateCtrl
+ 0x100b6d10 0x1f _zPHY_emc_DRXCompare2Time
+ 0x100b6d2f 0x65 _zPHY_emc_OnDurationPre2SubFrm
+ 0x100b6d94 0x41 _zPHY_emc_InactivityPre2SubFrm
+ 0x100b6dd5 0x9b _zPHY_emc_DlHarqPre2SubFrm
+ 0x100b6e70 0x89 _zPHY_emc_UlHarqPhichPre2SubFrm
+ 0x100b6ef9 0x63 _zPHY_emc_Next2SubFrameDrxStateCtrl
+ 0x100b6f5c 0x93 _zPHY_emc_ProDrxInitial
+ 0x100b6fef 0xb _zPHY_emc_ChePwrCtrlFlg
+ 0x100b6ffa 0x90 _Ltel1_GetConnNearestGap
+ 0x100b708a 0x28d _zPHY_emc_DrxPresyncCalc
+ 0x100b7317 0x4e _zPHY_emc_DrxStateCtrl
+ 0x100b7365 0xaf _zPHY_emc_DrxCsi_OpenRXCtrl
+ 0x100b7414 0xa1 _zPHY_emc_DRXProcLpCtrl
+ 0x100b74b5 0x15a _zPHY_emc_DrxSpsLpCtrl
+ 0x100b760f 0x23 _zPHY_emc_GetDrxCloseRfState
+ 0x100b7632 0x162 _zPHY_emc_DRXCalOpenRFTime
+ 0x100b7794 0x84 _zPHY_emc_DRXSleepJudge
+ 0x100b7818 0x75 _zPHY_emc_DrxParallelSleepCtrl
+ 0x100b788d 0x9d _zPHY_emc_DrxParallelFlowLog
+ 0x100b792a 0x21 _zPHY_emc_DrxParallelFlowCtrl
+ .text 0x100b794b 0x3f8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ 0x100b794b 0x7 _zPHY_emc_ProRadioLink_GetFIUpdateInd
+ 0x100b7952 0x7 _zPHY_emc_ProRadioLink_SetFIUpdateInd
+ 0x100b7959 0x4e _zPHY_emc_ProRadioLink_ParaGetInDrx
+ 0x100b79a7 0x1e _zPHY_emc_ProRadioLink_THInit
+ 0x100b79c5 0x28 _zPHY_emc_ProRadioLink_THFilterInFI
+ 0x100b79ed 0x60 _zPHY_emc_ProRadioLink_GetFinalTH
+ 0x100b7a4d 0x52 _zPHY_emc_ProRadioLink_DrxFilter
+ 0x100b7a9f 0xa2 _zPHY_emc_ProRadioLink_DrxFlow
+ 0x100b7b41 0x60 _zPHY_emc_ProRadioLink_NoDrxFilter
+ 0x100b7ba1 0x45 _zPHY_emc_ProRadioLink_StateSwitch
+ 0x100b7be6 0xb7 _zPHY_emc_ProRadioLink_MainPro
+ 0x100b7c9d 0xa6 _zPHY_emc_ProRadioLinkFlow
+ .text 0x100b7d43 0x2db8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ 0x100b7d43 0x40 _zPHY_amt_Lte_PrintMsgLog
+ 0x100b7d83 0x4c _zPHY_AMT_Rfc_WriteRfFrontReg
+ 0x100b7dcf 0x66 _zPHY_AMT_erfc_SetCurrentBandAntGPIO
+ 0x100b7e35 0xc1 _zPHY_AMT_erfc_SetCurrentBandPaModeGPIO
+ 0x100b7ef6 0x17 _zPHY_AMT_RFC_110_RxOn
+ 0x100b7f0d 0x16 _zPHY_AMT_RFC_110_RxOff
+ 0x100b7f23 0x17 _zPHY_AMT_RFC_110_TxOn
+ 0x100b7f3a 0x16 _zPHY_AMT_RFC_110_TxOff
+ 0x100b7f50 0x16 _zPHY_AMT_RFC_120_RxOn
+ 0x100b7f66 0x16 _zPHY_AMT_RFC_120_RxOff
+ 0x100b7f7c 0x16 _zPHY_AMT_RFC_120_TxOn
+ 0x100b7f92 0x16 _zPHY_AMT_RFC_120_TxOff
+ 0x100b7fa8 0x17 _zPHY_AMT_RFC_RXENABLE_On
+ 0x100b7fbf 0x16 _zPHY_AMT_RFC_RXENABLE_Off
+ 0x100b7fd5 0x17 _zPHY_AMT_RFC_TXENABLE_On
+ 0x100b7fec 0x16 _zPHY_AMT_RFC_TXENABLE_Off
+ 0x100b8002 0xf _zPHY_AMT_RFC_110_AfcSet
+ 0x100b8011 0x1 _zPHY_AMT_RFC_110_Xo_AfcSet
+ 0x100b8012 0x22 _zPHY_AMT_RFC_120_DCIQSet
+ 0x100b8034 0x42 _zPHY_AMT_RFC_110_TempDacGet
+ 0x100b8076 0x42 _zPHY_AMT_RFC_110_Xo_TempDacGet
+ 0x100b80b8 0x1d _zPHY_AMT_RFC_110_BandWidthModeGet
+ 0x100b80d5 0xa1 _zPHY_AMT_RFC_110_TxFreqSet
+ 0x100b8176 0x35 _zPHY_AMT_RFC_110_RegTxCfg
+ 0x100b81ab 0x24 _zPHY_AMT_RFC_120_RegTxCfg
+ 0x100b81cf 0x36 _zPHY_AMT_RFC_110_RegRxCfg
+ 0x100b8205 0x30 _zPHY_AMT_RFC_120_RegRxCfg
+ 0x100b8235 0x28 _zPHY_AMT_RFC_ZTERF_TxApcSet
+ 0x100b825d 0x33 _zPHY_AMT_RFC_ZTERF_Tx2Idle
+ 0x100b8290 0x33 _zPHY_AMT_RFC_ZTERF_Rx2Idle
+ 0x100b82c3 0x70 _zPHY_AMT_RFC_ZTERF_ToTx
+ 0x100b8333 0x70 _zPHY_AMT_RFC_ZTERF_ToRx
+ 0x100b83a3 0x13 _zPHY_AMT_RFC_ZTERF_ToIdle
+ 0x100b83b6 0xd _zPHY_amt_Lte_GetCarrierMode
+ 0x100b83c3 0x1f _zPHY_amt_Lte_SetCarrierMode
+ 0x100b83e2 0xd8 _zPHY_amt_Lte_ChangeMode
+ 0x100b84ba 0x15 _zPHY_amt_Lte_TxParaUpdate
+ 0x100b84cf 0xc7 _zPHY_amt_Lte_ServCellFreqUpdate
+ 0x100b8596 0x134 _zPHY_amt_Lte_CellSyncProc
+ 0x100b86ca 0xd1 _zPHY_amt_Lte_MprDeterm
+ 0x100b879b 0xa8 _zPHY_amt_Lte_RfcTxDataBaseSet
+ 0x100b8843 0x48 _zPHY_amt_Lte_FDTTransTxVgaCtrl
+ 0x100b888b 0x226 _zPHY_amt_Lte_FDT_PAVGAVOL_Update
+ 0x100b8ab1 0x1f _zPHY_amt_Lte_FDTTxOffsetSet
+ 0x100b8ad0 0x12e _zPHY_amt_Lte_FDTRfcDataBaseSet
+ 0x100b8bfe 0x1c _zPHY_amt_Lte_FDTRfcDataBaseClear
+ 0x100b8c1a 0xe _zPHY_amt_Lte_FDTGetAgcGain
+ 0x100b8c28 0x7c _zPHY_amt_Lte_FDTSaveAgcGain
+ 0x100b8ca4 0xf6 _zPHY_amt_Lte_FDTControl
+ 0x100b8d9a 0x2 _zPHY_amt_Lte_FDTGetAGC
+ 0x100b8d9c 0xb1 _zPHY_amt_Lte_FDTStart
+ 0x100b8e4d 0x12 _zPHY_amt_Lte_FDTCellSyncProc
+ 0x100b8e5f 0x20 _zPHY_amt_Lte_NSTCellSyncProc
+ 0x100b8e7f 0x37 _zPHY_amt_Lte_NSTCellSyncSuccessRsp
+ 0x100b8eb6 0x43 _zPHY_amt_Lte_NSTStartBler
+ 0x100b8ef9 0xed _zPHY_amt_Lte_NSTGetBler
+ 0x100b8fe6 0x32 _zPHY_amt_Lte_NSTStart
+ 0x100b9018 0x22 _zPHY_amt_Lte_NSTCirCfoStop
+ 0x100b903a 0x39 _zPHY_amt_Lte_NSTChangeFreq
+ 0x100b9073 0x15b _zPHY_amt_Lte_NSTControl
+ 0x100b91ce 0x13 _zPHY_amt_Lte_FSTCellSyncProc
+ 0x100b91e1 0x89 _zPHY_amt_Lte_FSTStart
+ 0x100b926a 0xc9 _zPHY_amt_Lte_FSTRfcDataBaseSet
+ 0x100b9333 0xda _zPHY_amt_Lte_FSTPowerUpdate
+ 0x100b940d 0xc0 _zPHY_amt_Lte_FSTSaveBlerAndRsrp
+ 0x100b94cd 0xf6 _zPHY_amt_Lte_FSTControl
+ 0x100b95c3 0x29 _zPHY_amt_Lte_Control
+ 0x100b95ec 0x294 _zPHY_amt_Lte_Tx_Init_Power
+ 0x100b9880 0x1a4 _zPHY_amt_Lte_Tx_Init_RFC
+ 0x100b9a24 0x7a _zPHY_amt_Lte_Tx_Init_MC
+ 0x100b9a9e 0x7a _zPHY_amt_Lte_Tx_Init_MC_Power
+ 0x100b9b18 0x6e _zPHY_amt_Lte_Close_Rfc
+ 0x100b9b86 0x51 _zPHY_amt_Lte_Tx_Close_MC
+ 0x100b9bd7 0x3c _zPHY_amt_Lte_TxFreq_RFC
+ 0x100b9c13 0x1d _zPHY_amt_Lte_TxPaMode_RFC
+ 0x100b9c30 0x4c _zPHY_amt_Lte_TxAPC_RFC
+ 0x100b9c7c 0x3a _zPHY_amt_Lte_AFC_RFC
+ 0x100b9cb6 0x38 _zPHY_amt_Lte_XO_AFC_RFC
+ 0x100b9cee 0x152 _zPHY_amt_Lte_Rx_Init_RFC
+ 0x100b9e40 0x1a _zPHY_amt_Lte_SetSyncTimer
+ 0x100b9e5a 0x4f _zPHY_amt_Lte_Cell_Search
+ 0x100b9ea9 0xa3 _zPHY_amt_Lte_CommMsg_Stub
+ 0x100b9f4c 0x3d _zPHY_amt_Lte_CommMsg_Send
+ 0x100b9f89 0x19f _zPHY_amt_Lte_DediMsg_Stub
+ 0x100ba128 0x33 _zPHY_amt_Lte_DediMsg_Send
+ 0x100ba15b 0x26b _zPHY_amt_Lte_Sync_Process
+ 0x100ba3c6 0x73 _zPHY_amt_Lte_Rx_Init_MC
+ 0x100ba439 0x70 _zPHY_amt_Lte_Rx_Close_MC
+ 0x100ba4a9 0x1b _zPHY_amt_Lte_RxFreq_RFC
+ 0x100ba4c4 0x2 _zPHY_amt_Lte_RxLNAMode_RFC
+ 0x100ba4c6 0x2 _zPHY_amt_Lte_RxVGA_RFC
+ 0x100ba4c8 0x43 _zPHY_amt_Lte_Get_Rsrp
+ 0x100ba50b 0xe _zPHY_amt_Lte_Get_TempDAC
+ 0x100ba519 0xe _zPHY_amt_Lte_Get_Xo_TempDAC
+ 0x100ba527 0xe _zPHY_amt_Lte_Set_AfcData
+ 0x100ba535 0x25 _zPHY_amt_Lte_Tx_DcOffset
+ 0x100ba55a 0xbc _zPHY_amt_Lte_CellSearchResult
+ 0x100ba616 0x4e _zPHY_amt_Lte_CalcServCellAntAMT
+ 0x100ba664 0x49 _zPHY_amt_Lte_UpCellSearchResult
+ 0x100ba6ad 0xf5 _zPHY_amt_Lte_RxAlways_Init
+ 0x100ba7a2 0xa _zPHY_amt_Lte_RxAlways_Close
+ 0x100ba7ac 0xe _zPHY_amt_Lte_RxAlwaysOpen_GetAgc
+ 0x100ba7ba 0x76 _zPHY_amt_Lte_RxAlwaysOpen
+ 0x100ba830 0x2 _zPHY_amt_Lte_RxCwControl
+ 0x100ba832 0x2c9 _zPHY_amtTool_ThreadEntry
+ .text 0x100baafb 0x1b39 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
+ 0x100baafb 0x4a _zPHY_erapc_InitialProc
+ 0x100bab45 0x33 _zPHY_erapc_RaParamReset
+ 0x100bab78 0xa4 _zPHY_erapc_BiProc
+ 0x100bac1c 0x106 _zPHY_erapc_RaResourceSelect
+ 0x100bad22 0x164 _zPHY_erapc_RaResourceSelectFDD
+ 0x100bae86 0x12d _zPHY_erapc_RaResourceSelectTDD
+ 0x100bafb3 0x48 _zPHY_erapc_PreambleGroupSelect
+ 0x100baffb 0x4f _zPHY_erapc_PreambleSelect
+ 0x100bb04a 0x1d0 _zPHY_erapc_PreamCycShiftCalc
+ 0x100bb21a 0x12b _zPHY_erapc_KValueCalc
+ 0x100bb345 0xb8 _zPHY_erapc_PreambleTransPower
+ 0x100bb3fd 0x6f _zPHY_erapc_PcmaxCalc
+ 0x100bb46c 0x12a _zPHY_erapc_RarMacPduDecode
+ 0x100bb596 0x9c _zPHY_erapc_TpuEventDelete
+ 0x100bb632 0x42 _zPHY_erapc_RntiDelete
+ 0x100bb674 0x4b _zPHY_erapc_SetRapcState
+ 0x100bb6bf 0x43 _zPHY_erapc_PreamFormatDetermFDD
+ 0x100bb702 0x3e _zPHY_erapc_PreamFormatDetermTDD
+ 0x100bb740 0xff _zPHY_erapc_ResrConfigDetermFDD
+ 0x100bb83f 0x1e1 _zPHY_erapc_ResrConfigDetermTDD
+ 0x100bba20 0x8f _zPHY_erapc_NextAvailSFDetermTDD
+ 0x100bbaaf 0x67 _zPHY_erapc_NPrbRaCalcTDD
+ 0x100bbb16 0x21 _zPHY_erapc_RandomNumGenerate
+ 0x100bbb37 0xdd _zPHY_erapc_RaRntiCalc
+ 0x100bbc14 0x8f _zPHY_erapc_SendRaCnfMsg
+ 0x100bbca3 0x152 _zPHY_erapc_ConfigSAD
+ 0x100bbdf5 0x235 _zPHY_erapc_PreamTransPro
+ 0x100bc02a 0x7a _zPHY_erapc_RaRetransProc
+ 0x100bc0a4 0x150 _zPHY_erapc_RarDetectedProc
+ 0x100bc1f4 0x7b _zPHY_erapc_CRntiMsg4Proc
+ 0x100bc26f 0x79 _zPHY_erapc_CcchSduMsg4Proc
+ 0x100bc2e8 0x55 _zPHY_erapc_AbortRaProc
+ 0x100bc33d 0x63 _zPHY_erapc_ContenStopProc
+ 0x100bc3a0 0x3d _zPHY_erapc_GetRapcTpuEventFlag
+ 0x100bc3dd 0x37 _zPHY_erapc_SetRapcTpuEventFlag
+ 0x100bc414 0xae _zPHY_erapc_Format4PrachNumCalc
+ 0x100bc4c2 0xda _zPHY_erapc_GapConflictIndicate
+ 0x100bc59c 0x94 _zPHY_erapc_Format4PrachNumCalc_ForUla
+ 0x100bc630 0x4 _zPHY_erapc_PrachAntennaSelect
+ .text 0x100bc634 0x5eb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ 0x100bc634 0x283 _zPHY_emc_ProHandover2Module
+ 0x100bc8b7 0x35d _zPHY_emc_ProHandoverFlow
+ 0x100bcc14 0xb _zPHY_emc_InHandoverProc
+ .text 0x100bcc1f 0xc86 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ 0x100bcc1f 0x1f9 _zPHY_emc_ProPagingFlow
+ 0x100bce18 0xf8 _zPHY_L1e_DcxoDelayProc
+ 0x100bcf10 0x8 _zPHY_L1e_GetPreSyncValidInd
+ 0x100bcf18 0x8 _zPHY_L1e_SetPreSyncValidInd
+ 0x100bcf20 0x7 _zPHY_L1e_GetPreSyncAccNum
+ 0x100bcf27 0x39 _zPHY_emc_RegPageCallEvent
+ 0x100bcf60 0x198 _zPHY_emc_CalPagingParam
+ 0x100bd0f8 0x103 _zPHY_emc_ProPagingCallBackFunction
+ 0x100bd1fb 0x31 _zPHY_emc_NxtSubFrmIsPage
+ 0x100bd22c 0x16 _zPHY_emc_DrxPoLpCtrl
+ 0x100bd242 0x53 _L1e_Page_ReUpdatePoEvt
+ 0x100bd295 0xd5 _L1e_SchedGetPreSyncSchdInfo
+ 0x100bd36a 0x33 _L1e_SchedPreSyncGetIdleWorkTimer
+ 0x100bd39d 0x8 _L1e_SchedReturnPreSyncWorkTime
+ 0x100bd3a5 0x29 _L1e_SchedPreSyncGetAgcWorkTimer
+ 0x100bd3ce 0x1b _L1e_SchedPreSyncSetState
+ 0x100bd3e9 0x7 _L1e_SchedPreSyncGetState
+ 0x100bd3f0 0xc _L1e_SchedPreSyncSetWorkCnt
+ 0x100bd3fc 0x12 _L1e_SchedPreSyncIsWorkSn
+ 0x100bd40e 0x12 _L1e_SchedPreSyncIsWorkInd
+ 0x100bd420 0x17 _L1e_SchedPreSyncGetRfOpenInd
+ 0x100bd437 0x29 _L1e_SchedPreSyncGetAgcWorkInd
+ 0x100bd460 0x24 _L1e_SchedPreSyncGetFssWorkInd
+ 0x100bd484 0x2d _L1e_SchedPreSyncGetCfoWorkInd
+ 0x100bd4b1 0x8 _L1e_SchedPreSyncGetFssWorkCnt
+ 0x100bd4b9 0x8 _L1e_SchedPreSyncGetRfcWorkCnt
+ 0x100bd4c1 0x8 _L1e_SchedPreSyncSetCfgSfnInd
+ 0x100bd4c9 0x8 _L1e_SchedPreSyncGetCfgSfnInd
+ 0x100bd4d1 0x8 _L1e_SchedPreSyncGetSfnBmp
+ 0x100bd4d9 0xa _L1e_SchedPreSyncGetPoMarkSn
+ 0x100bd4e3 0x2e _L1e_SchedPreSyncGetConnWorkTimer
+ 0x100bd511 0x75 _L1e_SchedPreSyncUpdateStep
+ 0x100bd586 0x8 _L1e_SchedPreSyncSetStep
+ 0x100bd58e 0x8 _L1e_SchedPreSyncGetStep
+ 0x100bd596 0x66 _L1e_DbgPreSyncCtrlInfo
+ 0x100bd5fc 0x7f _L1e_SchedPreSyncCtrl
+ 0x100bd67b 0x132 _zPHY_emc_tRxCirPreSyncStart
+ 0x100bd7ad 0xa1 _zPHY_emc_RfcRxColseOperationCheck
+ 0x100bd84e 0x57 _zPHY_emc_ProLpcSleepSchd
+ .text 0x100bd8a5 0x670 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_meas.o)
+ 0x100bd8a5 0x71 _zPHY_ecscMeas_LogMeasConfigReq
+ 0x100bd916 0x35 _zPHY_ecscMeas_LogMeasBitMask
+ 0x100bd94b 0x71 _zPHY_ecscMeas_LogMeasAgeThrold
+ 0x100bd9bc 0x5e _zPHY_ecscMeas_LogServCellResult
+ 0x100bda1a 0x3f _zPHY_ecscMeas_LogPccMeasResult
+ 0x100bda59 0x78 _zPHY_ecscMeas_LogInterCellInfo
+ 0x100bdad1 0x47 _zPHY_ecsrc_LogInterMeasInd
+ 0x100bdb18 0x23 _zPHY_ecscMeas_LogConnInterReport
+ 0x100bdb3b 0x4f _zPHY_ecscMeas_LogSccIntraMeasFilter
+ 0x100bdb8a 0x1a _zPHY_ecscMeas_LogSccIntraMeasFilter2
+ 0x100bdba4 0x2e _zPHY_ecscMeas_LogIntraFilter2
+ 0x100bdbd2 0x19 _zPHY_ecscMeas_LogInterMeasFilter
+ 0x100bdbeb 0x1f _zPHY_ecscMeas_LogIntraRSSI
+ 0x100bdc0a 0x16 _zPHY_ecscMeas_LogUpdateInterReportFail1
+ 0x100bdc20 0x47 _zPHY_ecscMeas_LogFilterInterReport3
+ 0x100bdc67 0x33 _zPHY_ecscMeas_LogPCCIntraMeasCell
+ 0x100bdc9a 0x43 _zPHY_ecscMeas_LogPCCIntraMeasCell4
+ 0x100bdcdd 0x21 _zPHY_ecscMeas_LogSCCIntraMeasCell
+ 0x100bdcfe 0x85 _zPHY_ecscMeas_LogSCCIntraMeasCell2
+ 0x100bdd83 0x76 _zPHY_ecscMeas_LogSCCIntraMeasCell4
+ 0x100bddf9 0x41 _zPHY_ecscMeas_LogFilterIntraDebug
+ 0x100bde3a 0x53 _zPHY_ecscMeas_LogFilterIntraDebug2
+ 0x100bde8d 0x4f _zPHY_ecscMeas_LogFilterInterDebug
+ 0x100bdedc 0x39 _zPHY_ecscMeas_LogCsrSnr
+ .text 0x100bdf15 0x6f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_dls.o)
+ 0x100bdf15 0x6f _L1e_LogDlDlsDciDetInfo
+ .text 0x100bdf84 0x9e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc.o)
+ 0x100bdf84 0x31 _zPHY_ecsc_LogMibReqCellInfo
+ 0x100bdfb5 0x17 _zPHY_ecsc_LogEarfchTable
+ 0x100bdfcc 0x2f _zPHY_ecsc_LogTpuEventMark
+ 0x100bdffb 0x59 _zPHY_ecsc_LogTimeOffsetPerfreq
+ 0x100be054 0x25 _L1e_csrc_LogDrxRefreshGapCnt
+ 0x100be079 0xa0 _L1e_csrc_LogCnnDrxSchedule
+ 0x100be119 0x15 _zPHY_ecsc_LogRecv_REL_REQ
+ 0x100be12e 0x29 _zPHY_ecsc_LogRecv_StopInterSearchMeas
+ 0x100be157 0x15 _zPHY_ecsc_LogReportMEASErr
+ 0x100be16c 0x48 _zPHY_ecsc_LogGAPTime
+ 0x100be1b4 0x2e _zPHY_ecsc_LogInterFreq
+ 0x100be1e2 0x2e _zPHY_ecsc_LogHandover
+ 0x100be210 0x24 _zPHY_ecsc_LogRecv_MULM_IRAT_IDLE_PERIOD_REP_REQ
+ 0x100be234 0x20 _zPHY_ecsc_LogRecv_FREQ_LIST_CONFIG_REQ
+ 0x100be254 0x1d _zPHY_ecsc_LogRecv_IRAT_MEAS_CONFIG_REQ
+ 0x100be271 0x1d _zPHY_ecsc_LogRecv_IRAT_MEASURE_REPORT_INT
+ 0x100be28e 0x15 _zPHY_ecsc_LogAbortGap
+ 0x100be2a3 0x3f _zPHY_ecsc_LogREG_IRAT_GAP_CONFIG_DELAY_INT
+ 0x100be2e2 0x2e _zPHY_ecsc_LogRecv_IRAT_GAP_CONFIG_REQ
+ 0x100be310 0x15 _zPHY_ecsc_LogTPUAdjusting
+ 0x100be325 0x2e _zPHY_ecsc_LogRecv_IRAT_GAP_CONFIG_DELAY_INT
+ 0x100be353 0x15 _zPHY_ecsc_LogRecv_RF_START_DEAL_PRE2SFINT
+ 0x100be368 0x15 _zPHY_ecsc_LogRecv_RF_CLOSE_DEAL_PRE2SFINT
+ 0x100be37d 0x15 _zPHY_ecsc_LogRecv_RESET_REQ
+ 0x100be392 0x2a _zPHY_ecsc_LogRecv_CELL_SEARCH_REQ
+ 0x100be3bc 0x15 _zPHY_ecsc_LogRecv_ABORT_CELL_SEARCH_REQ
+ 0x100be3d1 0x21 _zPHY_ecsc_LogRecv_COMMON_CONFIG_REQ
+ 0x100be3f2 0x15 _zPHY_ecsc_LogRecv_ABORT_MEAS_REQ
+ 0x100be407 0x73 _zPHY_ecsc_LogRecv_PI_START_REQ
+ 0x100be47a 0x15 _zPHY_ecsc_LogRecv_ONE_FREQ_END_REQ
+ 0x100be48f 0x2e _zPHY_ecsc_LogRecv_IRAT_MEAS_GAP_CONFIG_REQ
+ 0x100be4bd 0x1d _zPHY_ecsc_LogRecv_FREQ_SCAN_REQ
+ 0x100be4da 0x2b _zPHY_ecsc_LogPhyModeConfig
+ 0x100be505 0x27 _zPHY_ecsc_LogReportGap
+ 0x100be52c 0x3c _L1e_CsrcDb_LogDelCell
+ 0x100be568 0x18 _L1e_csrc_LogReTimeOffset
+ 0x100be580 0x66 _zPHY_ecscDb_LogCellToDB
+ 0x100be5e6 0x3d _zPHY_ecscDb_LogRefreshDB
+ 0x100be623 0x16 _zPHY_ecscDb_LogUpdateBoundary
+ 0x100be639 0x1e _zPHY_ecsc_LogChangeMeasPeriodIdle
+ 0x100be657 0x39 _zPHY_ecsc_Log_Earfcn_BandInfo
+ 0x100be690 0x22 _zPHY_ecscMeas_LogSrvCellReslt
+ 0x100be6b2 0x1f _zPHY_ecsc_LogStandardOutput
+ 0x100be6d1 0x15 _zPHY_ecsc_LogMeasPeriodChgDelay
+ 0x100be6e6 0x1d _zPHY_ecsc_LogSibOrRapcConflict
+ 0x100be703 0x1d _zPHY_ecsc_LogSubFreqOffset
+ 0x100be720 0x16 _zPHY_ecsc_LogEarfcnError
+ 0x100be736 0x76 _L1e_csrc_LogShortDrxInfo
+ 0x100be7ac 0x15 _L1e_csrc_LogTempComp
+ 0x100be7c1 0x15 _L1e_csrc_LogTempRead
+ 0x100be7d6 0x1f _L1e_csrc_LogGetFreqOffset
+ 0x100be7f5 0x1d _L1e_csrc_LogSetDisableAfcReloadFlag
+ 0x100be812 0x25 _L1e_csrc_LogC0CaliUpDate
+ 0x100be837 0x21 _L1e_csrc_LogC0CaliPeriod
+ 0x100be858 0x22 _L1e_csrc_LogC0CaliEvalue
+ 0x100be87a 0x2f _L1e_csrc_LogC0Update
+ 0x100be8a9 0x1e _L1e_csrc_LogC0Debug
+ 0x100be8c7 0x27 _L1e_csrc_LogC0CalRsrp
+ 0x100be8ee 0x1f _L1e_csrc_LogC0CalAfc
+ 0x100be90d 0x21 _L1e_csrc_LogC0UtcTimeExp
+ 0x100be92e 0x15 _L1e_csrc_LogC0CaliRestart
+ 0x100be943 0x21 _L1e_csrc_LogNewUtcError
+ .text 0x100be964 0x276 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm_normal.o)
+ 0x100be964 0x4c _zPHY_ecsm_LogMeasHwInfo
+ 0x100be9b0 0x79 _zPHY_ecsmNormal_LogUpdateRes
+ 0x100bea29 0x16 _zPHY_ecsrm_BuffLogSlaveMaxBdySub
+ 0x100bea3f 0x22 _zPHY_ecsrm_LogSetMeasAge
+ 0x100bea61 0x19 _zPHY_ecsrm_LogBuffFbRelatn
+ 0x100bea7a 0x17 _zPHY_ecsrm_LogMeasStartSubFrame
+ 0x100bea91 0x2b _zPHY_ecsrm_LogBuffCellPara
+ 0x100beabc 0x3f _zPHY_ecsrm_LogBuffCommPara
+ 0x100beafb 0x2d _zPHY_ecsrm_LogMeasResultRead
+ 0x100beb28 0x18 _zPHY_ecsrm_LogBuffMulmsubf
+ 0x100beb40 0x29 _zPHY_ecsrm_LogBuffSortCell
+ 0x100beb69 0x27 _zPHY_ecsrm_LogBuffBdyCell
+ 0x100beb90 0x27 _zPHY_ecsrm_LogBuffwait
+ 0x100bebb7 0x23 _zPHY_ecsrm_LogBuffMeasConfig
+ .text 0x100bebda 0x378 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_cs.o)
+ 0x100bebda 0x15 _zPHY_ecsccs_LogRSStart
+ 0x100bebef 0x27 _zPHY_ecsccs_LogSearchReq
+ 0x100bec16 0x41 _zPHY_ecsccs_LogCellInfo
+ 0x100bec57 0x1a _zPHY_ecsc_LogRecv_PBCH
+ 0x100bec71 0x24 _zPHY_ecsccs_LogMeasStart
+ 0x100bec95 0x26 _zPHY_ecsccs_LogSendTPUAdjust
+ 0x100becbb 0x30 _zPHY_ecsccs_LogCellRank
+ 0x100beceb 0x1d _zPHY_ecsccs_LogNoAppointedCell
+ 0x100bed08 0x42 _zPHY_ecsccs_LogICPReportResultRIGHT
+ 0x100bed4a 0x18 _zPHY_ecsccs_LogIcpBchCell
+ 0x100bed62 0x15 _zPHY_ecsccs_LogNoCell
+ 0x100bed77 0x44 _zPHY_ecsccs_LogStartResumeSrv
+ 0x100bedbb 0x4b _zPHY_ecsccs_LogNewPlmnRS_ReportStatus
+ 0x100bee06 0x29 _zPHY_ecsccs_LogNewPlmnRS_SearchFinished
+ 0x100bee2f 0x1f _zPHY_ecsccs_LogNewPlmnRS_MeasFinished
+ 0x100bee4e 0x3c _zPHY_ecsccs_LogResumeServBCHBoundry
+ 0x100bee8a 0x26 _zPHY_ecsccs_LogCurTime2PiTime
+ 0x100beeb0 0x30 _zPHY_ecsccs_LogReg_PLMN_PERIODICAL_TPU_INT
+ 0x100beee0 0x21 _zPHY_ecsccs_LogRecv_PLMN_SEARCH_TIME_EVENT
+ 0x100bef01 0x51 _zPHY_ecsccs_LogWriteBch2CsrDb
+ .text 0x100bef52 0x198 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_rx.o)
+ 0x100bef52 0x29 _L1e_LogDlRxMbsfnCirInfo
+ 0x100bef7b 0x52 _L1e_LogRxMbmsCirAreaInfo
+ 0x100befcd 0x9f _L1e_LogRxCirDataInfo
+ 0x100bf06c 0x42 _L1e_LogRxMbmsCirSearchInfo
+ 0x100bf0ae 0x22 _L1e_LogRxBetaInfo
+ 0x100bf0d0 0x1a _L1e_LogRxCfoCfgInfo
+ .text 0x100bf0ea 0xb03 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_mulm.o)
+ 0x100bf0ea 0x17 _zPHY_emulm_LogCsrSlaveStateChange
+ 0x100bf101 0x17 _zPHY_emulm_LogCsrSlaveSYNStateChange
+ 0x100bf118 0x20 _zPHY_emulm_LogCsrcGapStartOffset
+ 0x100bf138 0x2c _zPHY_emulm_LogCsrcFreeTimeRep
+ 0x100bf164 0x17 _zPHY_emulm_LogCsrcSetModeReq
+ 0x100bf17b 0x17 _zPHY_emulm_LogCsrcMeasSche
+ 0x100bf192 0x26 _zPHY_emulm_LogCsrcMeasReportProct
+ 0x100bf1b8 0x2f _zPHY_emulm_LogCsrcMeasReportInt
+ 0x100bf1e7 0x16 _zPHY_emulm_LogMeasNoCell
+ 0x100bf1fd 0x18 _zPHY_emulm_LogMeasCell
+ 0x100bf215 0x19 _zPHY_emulm_LogMeasNoCellReport
+ 0x100bf22e 0x73 _zPHY_emulm_LogMeasRight
+ 0x100bf2a1 0x16 _zPHY_emulm_LogASynSearch
+ 0x100bf2b7 0x2a _zPHY_emulm_LogGapStartOffset
+ 0x100bf2e1 0x17 _zPHY_emulm_LogSubFrameOnOff
+ 0x100bf2f8 0x2a _zPHY_emulm_LogGapEndOffset
+ 0x100bf322 0x56 _zPHY_emulm_LogRegCsrIratGapStart
+ 0x100bf378 0x94 _zPHY_emulm_LogRegCsrGapEnd
+ 0x100bf40c 0x56 _zPHY_emulm_LogRegCsrRfClose
+ 0x100bf462 0x17 _zPHY_emulm_LogBlackList
+ 0x100bf479 0x1c _zPHY_emulm_LogRemainTime
+ 0x100bf495 0x20 _zPHY_emulm_LogSynInterSearchMeas
+ 0x100bf4b5 0x22 _zPHY_emulm_LogRegIratPlmnMeas
+ 0x100bf4d7 0x22 _zPHY_emulm_LogRegSlaveAbortGap
+ 0x100bf4f9 0x1d _zPHY_emulm_LogIratAbortGap
+ 0x100bf516 0x1d _zPHY_emulm_LogIratMeasDone
+ 0x100bf533 0x1e _zPHY_emulm_LogGapPosition
+ 0x100bf551 0x4d _zPHY_emulm_LogGapTime
+ 0x100bf59e 0x4d _zPHY_emulm_LogGapTime1
+ 0x100bf5eb 0x4d _zPHY_emulm_LogGapTime2
+ 0x100bf638 0x17 _zPHY_emulm_LogPbchInGap
+ 0x100bf64f 0x28 _zPHY_emulm_LogEnRfcEventTable
+ 0x100bf677 0x54 _zPHY_emulm_Log6MSRfcEventTableInGap
+ 0x100bf6cb 0x39 _zPHY_emulm_LogrRfStartDeal
+ 0x100bf704 0x39 _zPHY_emulm_LogrRfEndDeal
+ 0x100bf73d 0x36 _zPHY_emulm_LogRefreshDataBase1
+ 0x100bf773 0x18 _zPHY_emulm_LogtpuAdjust
+ 0x100bf78b 0x18 _zPHY_emulm_LogtpuCantAdjust
+ 0x100bf7a3 0x29 _zPHY_emulm_LogPssAdjust
+ 0x100bf7cc 0x15 _zPHY_emulm_LogRecvSlaveAbortGap
+ 0x100bf7e1 0x15 _zPHY_emulm_LogRecvCsrAbortGap
+ 0x100bf7f6 0x15 _zPHY_emulm_LogRecvCsrTpuIratGap
+ 0x100bf80b 0x15 _zPHY_emulm_LogRecvCsrTpuIratGapStart
+ 0x100bf820 0x65 _zPHY_emulm_LogSlaveMeasureFlow
+ 0x100bf885 0x15 _zPHY_emulm_LogRecvCsrTpuIratPlmnMeas
+ 0x100bf89a 0x15 _zPHY_emulm_LogRecvCsrTpuUpdateCounter
+ 0x100bf8af 0x15 _zPHY_emulm_LogCsrcRecvGapEndOffsetCfg
+ 0x100bf8c4 0x38 _zPHY_emulm_LogCsrcGatValidCellFbInfo
+ 0x100bf8fc 0x21 _zPHY_emulm_LogCsrcTimeDelayIntEvent
+ 0x100bf91d 0x2c _zPHY_emulm_LogCsrcAfterAdjTpu
+ 0x100bf949 0x31 _L1e_Mulm_LogNeedSearchAndMeas
+ 0x100bf97a 0x19 _zPHY_emulm_LogCsrcStartEarfcnInfo
+ 0x100bf993 0x2f _zPHY_emulm_LogCsrcEndEarfcnInfo
+ 0x100bf9c2 0x67 _zPHY_emulm_LogCsrcGapAndSssInfo
+ 0x100bfa29 0x6a _zPHY_emulm_LogCsrcHbTimeInfo
+ 0x100bfa93 0x2c _zPHY_emulm_LogCsrcSssBufferAndGap
+ 0x100bfabf 0x21 _zPHY_emulm_LogCsrcAgcStart
+ 0x100bfae0 0x39 _zPHY_emulm_LogCsrcSlaveSssProcessInfo
+ 0x100bfb19 0x43 _zPHY_emulm_LogBuffCheckOpenTimePeriod
+ 0x100bfb5c 0x21 _zPHY_emulm_LogGapCoverBuffCheck
+ 0x100bfb7d 0x1a _zPHY_emulm_LogMeasFilter
+ 0x100bfb97 0x16 _zPHY_emulm_LogUpdateReportFail
+ 0x100bfbad 0x26 _zPHY_emulm_LogSetFilterFact
+ 0x100bfbd3 0x1a _zPHY_emulm_LogGetFilterFact
+ .text 0x100bfbed 0x120 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_cmn_mbms.o)
+ 0x100bfbed 0x91 _L1e_logCmnMbmsMbsfnSubfListInfo
+ 0x100bfc7e 0x8f _L1e_LogCmnMbmsMbsfnAllocInfo
+ .text 0x100bfd0d 0x239 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm.o)
+ 0x100bfd0d 0x30 _zPHY_ecsm_LogBlackCell
+ 0x100bfd3d 0xba _zPHY_ecsm_LogRfcOpenTime
+ 0x100bfdf7 0x4d _zPHY_ecsm_LogRfcOpenTimeFddIdle
+ 0x100bfe44 0x54 _zPHY_ecsm_LogTDDRfcEventTab
+ 0x100bfe98 0x14 _zPHY_ecsm_LogRecv_RESET_REQ
+ 0x100bfeac 0x32 _zPHY_ecsm_LogMeasStart
+ 0x100bfede 0x14 _zPHY_ecsm_Logrec_MEASRESET
+ 0x100bfef2 0x16 _zPHY_ecsm_LogRecv_UnknownMsg
+ 0x100bff08 0x1e _zPHY_ecsm_Buff_LogRfcOpenTime
+ 0x100bff26 0x20 _zPHY_ecsm_LogRfcEventTablength
+ .text 0x100bff46 0x3c8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_func.o)
+ 0x100bff46 0xc _zPHY_GetUINT32BitsField
+ 0x100bff52 0x27 _zPHY_GetUINT64BitsField
+ 0x100bff79 0x1f _zPHY_GetUINT16DivCeilValue
+ 0x100bff98 0x22 _zPHY_GetUINT32DivCeilValue
+ 0x100bffba 0x28 _zPHY_GetSINT16DivFloorValue
+ 0x100bffe2 0x2e _zPHY_GetSINT32DivFloorValue
+ 0x100c0010 0x16 _zPHY_BinarySearch
+ 0x100c0026 0x132 _zPHY_Pow2
+ 0x100c0158 0x5b _zPHY_Fixpoint2Float
+ 0x100c01b3 0x88 _zPHY_Float2Fixpoint
+ 0x100c023b 0x6c _zPHY_DivRet2Fixpoint7510
+ 0x100c02a7 0x57 _zPHY_DivRet2Fixpoint
+ 0x100c02fe 0x10 _zPHY_LteaDelay
+ .text 0x100c030e 0x60 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x100c030e 0x57 _zPHY_setRxMaskFlag
+ 0x100c0365 0x9 _zPHY_getRxMaskFlag
+ .text 0x100c036e 0x95 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ 0x100c036e 0x37 _L1l_CmnAssert
+ 0x100c03a5 0x5a _zPHY_RecvUnknownMsg
+ 0x100c03ff 0x4 _zPHY_create_handler
+ .text 0x100c0403 0x28c5 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_srs.o)
+ 0x100c0403 0x2f _zPHY_eula_PucchSrsRelease
+ 0x100c0432 0x6d _zPHY_eula_SetSrsScale
+ 0x100c049f 0x58 _zPHY_eula_LtxParas_QDivNRsZcSrs
+ 0x100c04f7 0x31f _zPHY_eula_UpdataSrsBGParas_Cell
+ 0x100c0816 0xd0 _zPHY_eula_UpdataSrsBGParas_APSfOffset
+ 0x100c08e6 0x19d _zPHY_eula_UpdataSrsBGParas_APTiming
+ 0x100c0a83 0x159 _zPHY_eula_UpdataSrsBGParas_APParaCalc_PTS
+ 0x100c0bdc 0x29b _zPHY_eula_UpdataSrsBGParas_APParaCalc
+ 0x100c0e77 0x3d _zPHY_eula_UpdataSrsBGParas_APParaAssign
+ 0x100c0eb4 0x62 _zPHY_eula_UpdataSrsBGParas_AP
+ 0x100c0f16 0x2f6 _zPHY_eula_UpdataSrsBGParas_PTiming
+ 0x100c120c 0x159 _zPHY_eula_UpdataSrsBGParas_PNonHopParaCalc_PTS
+ 0x100c1365 0x219 _zPHY_eula_UpdataSrsBGParas_PNonHopParaCalc
+ 0x100c157e 0x118 _zPHY_eula_UpdataSrsBGParas_PHopParaCalc_PTS
+ 0x100c1696 0x27d _zPHY_eula_UpdataSrsBGParas_PHopParaCalc
+ 0x100c1913 0x6d _zPHY_eula_UpdataSrsBGParas_P
+ 0x100c1980 0xb2 _zPHY_eula_UpdataSrsBGParas
+ 0x100c1a32 0xe4 _zPHY_eula_CommSrsProc
+ 0x100c1b16 0x22e _zPHY_eula_ScheApSrs
+ 0x100c1d44 0x27 _zPHY_eula_WipeSrsInRarBasedPusch
+ 0x100c1d6b 0x80 _zPHY_eula_DetermineSrsCellSpecStateInPusch
+ 0x100c1deb 0xbe _zPHY_eula_ProcConflictOfSrsAndPucchPusch_OneCell
+ 0x100c1ea9 0x50 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell
+ 0x100c1ef9 0x4d _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschScell
+ 0x100c1f46 0x86 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_PuschScell
+ 0x100c1fcc 0x120 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_Pucch
+ 0x100c20ec 0x136 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_Pucch_PuschScell
+ 0x100c2222 0x12e _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_Pucch_PuschScell
+ 0x100c2350 0x2 _zPHY_eula_ProcConflictOfSrsAndPucchPusch
+ 0x100c2352 0x5e _zPHY_eula_ScheSrsInPusch_AntMapping
+ 0x100c23b0 0x7d _zPHY_eula_ScheSrsInPusch
+ 0x100c242d 0xb1 _zPHY_eula_ProcConflictOfSrsAndPucch_OneCell
+ 0x100c24de 0x2 _zPHY_eula_ProcConflictOfSrsAndPucch
+ 0x100c24e0 0x1d _zPHY_eula_ProcConflictOfSrsAndDrx
+ 0x100c24fd 0x4b _zPHY_eula_ScheSrsInNonPusch
+ 0x100c2548 0x4e _zPHY_eula_ProcSrsInDurationMode0
+ 0x100c2596 0x4c _zPHY_eula_GetPtsState
+ 0x100c25e2 0xbe _zPHY_eula_CalcApSrsParas
+ 0x100c26a0 0xbe _zPHY_eula_CalcPNonHopSrsParas
+ 0x100c275e 0x389 _zPHY_eula_CalcPHopSrsParas
+ 0x100c2ae7 0x46 _zPHY_eula_CalcSrsParas
+ 0x100c2b2d 0x70 _zPHY_eula_InitSrsDB
+ 0x100c2b9d 0x4e _zPHY_eula_SrsSrcRelease
+ 0x100c2beb 0x18 _zPHY_eula_ClearApSrsSche
+ 0x100c2c03 0xbc _zPHY_eula_CalcnSrs
+ 0x100c2cbf 0x9 _zPHY_eula_SrsAntennaSelect
+ .text 0x100c2cc8 0x516 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ 0x100c2cc8 0x53 _zPHY_edla_GetPhichGrpNum
+ 0x100c2d1b 0xb _zPHY_edla_GetPhichRegNum
+ 0x100c2d26 0x10b _zPHY_edla_GetNextSubFrmPhichInfo
+ 0x100c2e31 0x100 _zPHY_edla_UpdateIphichInfo
+ 0x100c2f31 0x10 _zPHY_edla_GetPhichInfo
+ 0x100c2f41 0xc9 _zPHY_edla_GetPerPhichSeq
+ 0x100c300a 0x95 _zPHY_edla_GetPerTBPhichSeq
+ 0x100c309f 0x11 _zPHY_edla_GetPhichSeq
+ 0x100c30b0 0x23 _zPHY_edla_GetHichSubFreq
+ 0x100c30d3 0xbb _zPHY_edla_PhichProc
+ 0x100c318e 0x45 _zPHY_edla_UpdatePhichInfo
+ 0x100c31d3 0xb _zPHY_edla_HiValidJudgment
+ .text 0x100c31de 0x1540 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ 0x100c31de 0x5d _zPHY_edfe_SupCommonCalAGC
+ 0x100c323b 0x72 _zPHY_edfe_SupFastAGC
+ 0x100c32ad 0xd9 _zPHY_edfe_SupNotSyncAGC
+ 0x100c3386 0x295 _zPHY_edfe_SupNotSyncAGCAnt0And1
+ 0x100c361b 0x18 _zPHY_edfe_GetAgcReloadVal
+ 0x100c3633 0x11 _zPHY_edfe_ConfigAgcReloadVal
+ 0x100c3644 0x16 _zPHY_edfe_ACP405AgcGainConfig
+ 0x100c365a 0xac _zPHY_edfe_SupAGCLostLockMethod
+ 0x100c3706 0x3f _zPHY_edfe_InitAgcPara
+ 0x100c3745 0x1a _zPHY_edfe_ResetAgcCoverJudgePara
+ 0x100c375f 0x24 _zPHY_edfe_InitAgcDagcGain
+ 0x100c3783 0x155 _zPHY_edfe_JudgeAgcCoverOpt
+ 0x100c38d8 0x67 _zPHY_edfe_CalcAGCForBandChange
+ 0x100c393f 0xb8 _zPHY_edfe_GetNextAGCInitGain
+ 0x100c39f7 0x9b _zPHY_edfe_CalcAGCNewMethodAnt
+ 0x100c3a92 0x9d _zPHY_edfe_CalcAGCGainNewMethod
+ 0x100c3b2f 0x139 _zPHY_edfe_SupHandleAGCOpt
+ 0x100c3c68 0x51 _zPHY_edfe_FindOldestPosInAgcGainDB
+ 0x100c3cb9 0x9 _zPHY_edfe_SupResetAGCLoopOpt
+ 0x100c3cc2 0xb7 _zPHY_edfe_NotSyncToSyncSetAgc
+ 0x100c3d79 0x3d _zPHY_edfe_SyncToNotSyncSetAgc
+ 0x100c3db6 0x10b _zPHY_edfe_UpdateSCCAGC
+ 0x100c3ec1 0x12 _zPHY_edfe_CompAgcDBTimeInfo
+ 0x100c3ed3 0xc7 _zPHY_edfe_IratHandoverAfcManage
+ 0x100c3f9a 0x71 _zPHY_edfe_SupSaveSlaveAfcCtrl
+ 0x100c400b 0xfd _zPHY_edfe_IratHandoverCordicManage
+ 0x100c4108 0x8e _zPHY_edfe_IratCordicManage
+ 0x100c4196 0x6e _zPHY_edfe_SupSaveSlaveCordicCtrl
+ 0x100c4204 0x77 _zPHY_edfe_FSNewAgcIntHandle
+ 0x100c427b 0x72 _zPHY_edfe_InitSubFramePwrDB
+ 0x100c42ed 0x263 _zPHY_edfe_SupSemiStaticAgcNew
+ 0x100c4550 0x26 _zPHY_edfe_MbsfnAgcDbInit
+ 0x100c4576 0xc _zPHY_edfe_MbsfnAgcParaConfig
+ 0x100c4582 0x9f _zPHY_edfe_SupCalMbsfnRegionAgc
+ 0x100c4621 0xb6 _zPHY_edfe_SupHandleMbsfnAGC
+ 0x100c46d7 0x2f _zPHY_edfe_NewMbsfnAGCGainInit
+ 0x100c4706 0x1 _zPHY_edfe_MbsfnAgcCoverJudge
+ 0x100c4707 0x17 _zPHY_edfe_MbsfnAgcGainConfig
+ .text 0x100c471e 0x251 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
+ 0x100c471e 0x1ae _zPHY_eulpc_SrsPowCalc
+ 0x100c48cc 0xa3 _zPHY_eulpc_SrsPowCtrl
+ .text 0x100c496f 0x1175 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
+ 0x100c496f 0x1 _zPHY_euls_L_Entry
+ 0x100c4970 0x34c _zPHY_euls_Entry
+ 0x100c4cbc 0x2cc _zPHY_euls_TPU_INT1_RARGrantProcess
+ 0x100c4f88 0x2fa _zPHY_euls_TPU_INT1_DCIProcess
+ 0x100c5282 0x435 _zPHY_euls_TPU_INT1_Step1_process
+ 0x100c56b7 0x191 _zPHY_euls_TPU_INT1_Step2_process
+ 0x100c5848 0x8b _zPHY_euls_GetDediCfgParas
+ 0x100c58d3 0x7f _zPHY_euls_GetSCellCfgParas
+ 0x100c5952 0x80 _zPHY_euls_GetCommCfgParas
+ 0x100c59d2 0x10e _zPHY_euls_GetHandoverCfgParas
+ 0x100c5ae0 0x4 _zPHY_euls_PuschAntennaSelect
+ .text 0x100c5ae4 0x224c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ 0x100c5ae4 0x2c _L1e_FS_SwReset
+ 0x100c5b10 0x16 _L1e_FS_Init
+ 0x100c5b26 0x32 _L1e_FS_FreqScanEnRfcNotSyncTable
+ 0x100c5b58 0xb3 _L1e_FS_HandleFreqscanAddSearchResult
+ 0x100c5c0b 0x9c _L1e_FS_CalcSssAgcGainCompen
+ 0x100c5ca7 0xec _L1e_FS_FreqScanAddSearchResultSort
+ 0x100c5d93 0x30 _L1e_FS_SetFSResult
+ 0x100c5dc3 0x110 _L1e_FS_FindFSEarfcnToReport
+ 0x100c5ed3 0x34 _L1e_FS_FindEarfcnForSearch
+ 0x100c5f07 0x36 _L1e_FS_SendFsCnf
+ 0x100c5f3d 0x8f _L1e_FS_BufForSearch
+ 0x100c5fcc 0x86 _L1e_Fs_CreateList_Band38_Bak
+ 0x100c6052 0x6c _L1e_Fs_CreateListBak
+ 0x100c60be 0x6a _L1e_Fs_IsFreqPointValid
+ 0x100c6128 0x36 _L1e_Fs_MaxPeakSetZero
+ 0x100c615e 0x2a _L1e_Fs_GetMaxValue
+ 0x100c6188 0x28 _L1e_Fs_GetMinValue
+ 0x100c61b0 0x33 _L1e_Fs_SetProfileInfo
+ 0x100c61e3 0x34 _L1e_Fs_DelList
+ 0x100c6217 0x6 _L1e_FS_ClearPssResultList
+ 0x100c621d 0x6 _L1e_FS_ClearMeanPowerResultList
+ 0x100c6223 0xe _L1e_FS_SetRedoInfo
+ 0x100c6231 0xf4 _L1e_FS_GetAllGainProfileInfo
+ 0x100c6325 0x63 _L1e_FS_GetAllProfileInfo
+ 0x100c6388 0xcf _L1e_Fs_GetAllValidFreqPoint
+ 0x100c6457 0x33 _L1e_FS_SetBandInfo
+ 0x100c648a 0xf _L1e_FS_SetSpecialBandInfo
+ 0x100c6499 0x5c _L1e_FS_SetOverLapFreqBand
+ 0x100c64f5 0x1cb _L1e_FS_GenFreqBand
+ 0x100c66c0 0x1e _L1e_FS_CfgRfcNotSyncTable
+ 0x100c66de 0x51 _L1e_FS_ReqMsgHandle
+ 0x100c672f 0x13 _L1e_FS_SetFreqPoint
+ 0x100c6742 0x74 _L1e_FS_InsertPssResult
+ 0x100c67b6 0xb3 _L1e_FS_SetIniCsrInfo
+ 0x100c6869 0xb0 _L1e_FS_SetFsRslt
+ 0x100c6919 0x8b _L1e_FS_ResultSort
+ 0x100c69a4 0x1b _L1e_FS_PlmnPeriodTpuInPro
+ 0x100c69bf 0xca _L1e_FS_SetDisctRslt
+ 0x100c6a89 0x21 _L1e_FS_SeekToHalfFram
+ 0x100c6aaa 0xce _L1e_FS_DoPss
+ 0x100c6b78 0x109 _L1e_FS_PssNext100KFreqPointNoPreCFO
+ 0x100c6c81 0x61 _L1e_FS_PssNext100KFreqPointPreCFO
+ 0x100c6ce2 0x2f _L1e_FS_PssNext100KFreqPoint
+ 0x100c6d11 0x35 _L1e_FS_PssNextAgcGain
+ 0x100c6d46 0x1b _L1e_FS_PssNextProfile
+ 0x100c6d61 0x79 _L1e_FS_InitFreqOffset
+ 0x100c6dda 0x41 _L1e_FS_PssNextFreqOffset
+ 0x100c6e1b 0x3d _L1e_FS_PreFreqOffset
+ 0x100c6e58 0x12d _L1e_FS_Pss100KResult
+ 0x100c6f85 0x27 _L1e_FS_DiscreteFreqOffsetLoop
+ 0x100c6fac 0x77 _L1e_FS_PssDisctResult
+ 0x100c7023 0x1b _L1e_FS_PssProfileLoopStart
+ 0x100c703e 0x54 _L1e_FS_NextBand
+ 0x100c7092 0x1b _L1e_FS_Pss500KFreqPointLoopStart
+ 0x100c70ad 0x31 _L1e_FS_PssNext500KFreqPoint
+ 0x100c70de 0x11 _L1e_FS_GetFsMode
+ 0x100c70ef 0x56 _L1e_FS_SetFsTempResult
+ 0x100c7145 0xa4 _L1e_FS_FreqScanCellSearch
+ 0x100c71e9 0x4a _L1e_FS_PssOneFreqPointStart
+ 0x100c7233 0x2b _L1e_FS_PssAgcGainLoopStart
+ 0x100c725e 0x4e _L1e_FS_Pss100KFreqPointLoopStart
+ 0x100c72ac 0xc _L1e_FS_PssNeedOffset
+ 0x100c72b8 0xd _L1e_FS_PssNeedDo100K
+ 0x100c72c5 0xe _L1e_FS_BandLoopStart
+ 0x100c72d3 0x2b _L1e_FS_PssSkipPiTime
+ 0x100c72fe 0x1e _L1e_FS_PssSeekToSlaveGap
+ 0x100c731c 0x23 _L1e_FS_SeekToWorkTime
+ 0x100c733f 0x24 _L1e_FS_MpFreqPointLoopStart
+ 0x100c7363 0x7b _L1e_FS_SegmentInfoSort
+ 0x100c73de 0x93 _L1e_FS_SetSegmentInfo
+ 0x100c7471 0xd3 _L1e_FS_SetSegmentInfoEnd
+ 0x100c7544 0xb4 _L1e_FS_FreqSegmentAlorigthm
+ 0x100c75f8 0x62 _L1e_FS_FreqSegment
+ 0x100c765a 0x2f _L1e_FS_MpNextFreqPoint
+ 0x100c7689 0x24 _L1e_FS_MpOneFreqPointStart
+ 0x100c76ad 0x40 _L1e_FS_MeanPowerCal
+ 0x100c76ed 0xc _L1e_FS_MpMethod
+ 0x100c76f9 0x11 _L1e_FS_PssMethod
+ 0x100c770a 0x14 _L1e_FS_PLMN
+ 0x100c771e 0xb _L1e_FS_SetState
+ 0x100c7729 0x8 _L1e_FS_GetState
+ 0x100c7731 0x13 _L1e_FS_MpStart
+ 0x100c7744 0x15 _L1e_FS_SetCnfInfo
+ 0x100c7759 0x68 _L1e_FS_OverlapSegment
+ 0x100c77c1 0x89 _L1e_FS_Report2PsResult
+ 0x100c784a 0x1b _l1e_FS_MPEnvelopeSort
+ 0x100c7865 0x22 _L1e_FS_MpEnvelope
+ 0x100c7887 0xa _L1e_FS_PssNeedReDo500K
+ 0x100c7891 0xc _L1e_FS_Redo500KStart
+ 0x100c789d 0xf _L1e_FS_PssReDo500KNextProfile
+ 0x100c78ac 0x1c _L1e_FS_PssReDo500KFpLoopStart
+ 0x100c78c8 0x43 _L1e_Fs_ReDoGetAllValidFreqPoint
+ 0x100c790b 0x24 _L1e_FS_PssReDoNext500KFreqPoint
+ 0x100c792f 0xa _L1e_FS_PssNeedAgc
+ 0x100c7939 0x9 _L1e_FS_AgcLoopStart
+ 0x100c7942 0x45 _L1e_FS_AgcNextFreqPoint
+ 0x100c7987 0x21 _L1e_FS_BeforeAgc
+ 0x100c79a8 0x16 _L1e_FS_AddAgcWaitTime
+ 0x100c79be 0xc5 _L1e_FS_AgcProc
+ 0x100c7a83 0x17 _L1e_FS_PssNeedReDo100K
+ 0x100c7a9a 0x17 _L1e_FS_IsSerialMode
+ 0x100c7ab1 0x35 _L1e_FS_IsDiscreteMode
+ 0x100c7ae6 0x2b _L1e_FS_DiscretePssStart
+ 0x100c7b11 0x12 _L1e_FS_DiscretePssSnrBackup
+ 0x100c7b23 0xc _L1e_FS_DiscretePssSnrClear
+ 0x100c7b2f 0x31 _L1e_FS_CheckSearchMode
+ 0x100c7b60 0x1b6 _L1e_FS_CfgRfAndGetMp
+ 0x100c7d16 0x1a _L1e_FS_MpSeekWorkTime
+ .text 0x100c7d30 0x345c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ 0x100c7d30 0x119 _zPHY_euls_UlGrantReception
+ 0x100c7e49 0x13d _zPHY_euls_HARQEntity
+ 0x100c7f86 0x333 _zPHY_euls_HARQProcess
+ 0x100c82b9 0x57 _zPHY_euls_ProInitial
+ 0x100c8310 0x31 _zPHY_euls_InitUlHarqIDInHarqDB
+ 0x100c8341 0x141 _zPHY_euls_UlHarqProcessCtrl
+ 0x100c8482 0x364 _zPHY_euls_DecodeDci4
+ 0x100c87e6 0x3bf _zPHY_euls_DecodeDci0
+ 0x100c8ba5 0x104 _zPHY_euls_DecodeDci
+ 0x100c8ca9 0x4f _zPHY_euls_DecodePucchTPC
+ 0x100c8cf8 0x8f _zPHY_euls_GetMsg3SendSubFrmNo
+ 0x100c8d87 0x99 _zPHY_euls_DecodeRARGrant
+ 0x100c8e20 0xaf _zPHY_euls_ReportUlGrantParas
+ 0x100c8ecf 0xa8 _zPHY_euls_ReportUlGrantToPS
+ 0x100c8f77 0xab _zPHY_euls_CalcLUtrPara
+ 0x100c9022 0x9c _zPHY_euls_CalcLTxPara
+ 0x100c90be 0x129 _zPHY_euls_PuschPrmFHType1
+ 0x100c91e7 0x1df _zPHY_euls_PuschPrmFHType2
+ 0x100c93c6 0x10 _zPHY_euls_CalcX2Cinit
+ 0x100c93d6 0x62 _zPHY_euls_CalcNPuschSymb
+ 0x100c9438 0x148 _zPHY_euls_DecodeModuleCodeSchem
+ 0x100c9580 0x25 _zPHY_euls_Nchoosek
+ 0x100c95a5 0x1b5 _zPHY_euls_DecodeRIV_Ratype1
+ 0x100c975a 0x75 _zPHY_euls_DecodeRIV
+ 0x100c97cf 0x44 _zPHY_euls_GetRbAssignBitWidInDci4
+ 0x100c9813 0x43 _zPHY_euls_GetRbAssignBitWidInDci0
+ 0x100c9856 0xc9 _zPHY_euls_GetPuschPosByPdcchOrPhichPos
+ 0x100c991f 0x59 _zPHY_euls_AddMsg4DetectStartEvent
+ 0x100c9978 0x5a _zPHY_euls_AddMsg4DetectStopEvent
+ 0x100c99d2 0x1f _zPHY_euls_AddMsg4DetectWinEvents
+ 0x100c99f1 0x2d _zPHY_euls_ModifyMsg4DetectWinEvents
+ 0x100c9a1e 0xde _zPHY_euls_AddMsg3LtxDealEvent
+ 0x100c9afc 0x49 _zPHY_euls_AddCqiRarSchdEvents
+ 0x100c9b45 0x32 _zPHY_euls_InitSPSMode
+ 0x100c9b77 0x2b _zPHY_euls_SetupSPSMode
+ 0x100c9ba2 0x7a _zPHY_euls_SetupSPSMode_DealComnPara
+ 0x100c9c1c 0x37 _zPHY_euls_SetupSPSMode_CalNextRecurPara
+ 0x100c9c53 0x41 _zPHY_euls_JudgeAndDealUlSpsInterval_TDD
+ 0x100c9c94 0x2e _zPHY_euls_JudgeAndDealUlSpsInterval_FDD
+ 0x100c9cc2 0x53 _zPHY_euls_ProSPSMode
+ 0x100c9d15 0x53 _zPHY_euls_ProSPSMode_GetUlSfUponCfgGrantSf
+ 0x100c9d68 0x44 _zPHY_euls_ProSPSMode_CalNextRecurPara
+ 0x100c9dac 0x32 _zPHY_euls_ReleaseSPSMode
+ 0x100c9dde 0x37 _zPHY_euls_ProcessSPSImplicitRelease
+ 0x100c9e15 0x11 _zPHY_euls_GetDCI0InfoFromConfiguredGrant
+ 0x100c9e26 0x11 _zPHY_euls_LastSubframe_SFN
+ 0x100c9e37 0xd _zPHY_euls_LastSubframe_Subframe
+ 0x100c9e44 0xc _zPHY_euls_JudgeIfBitsIsAll1s_ForSPSRelease
+ 0x100c9e50 0x4b _zPHY_euls_TATimerStop
+ 0x100c9e9b 0xe _zPHY_euls_MACReset
+ 0x100c9ea9 0xa1 _zPHY_euls_Release
+ 0x100c9f4a 0x1e _zPHY_euls_ProcDci0PhichSelec
+ 0x100c9f68 0xcd _zPHY_euls_ProcDci0PhichSelec_Assign
+ 0x100ca035 0x46 _zPHY_euls_ProcDci0PhichSelec_Selec
+ 0x100ca07b 0x34 _zPHY_euls_DecodeUlIndexDci0
+ 0x100ca0af 0x33 _zPHY_euls_DecodeUlIndexDci4
+ 0x100ca0e2 0x152 _zPHY_euls_AssignDCI0PHICH
+ 0x100ca234 0x5e _zPHY_euls_AssignDCI0_Schedule
+ 0x100ca292 0x26 _zPHY_euls_AssignPHICH_Schedule
+ 0x100ca2b8 0x5a _zPHY_euls_SelecDCI0PHICH
+ 0x100ca312 0x21 _zPHY_euls_ReleaseDCI0PHICHSelecDB
+ 0x100ca333 0x67 _zPHY_euls_UpdataTTIBundlingHarqID
+ 0x100ca39a 0xa1 _zPHY_euls_DealBundlingGrant
+ 0x100ca43b 0x5a _zPHY_euls_ProcRealPHICH
+ 0x100ca495 0x59 _zPHY_euls_ProcVirtualPHICH
+ 0x100ca4ee 0x7b _zPHY_euls_InitTTIBundlingHarqID
+ 0x100ca569 0x16 _zPHY_euls_InitTTIBundlingMode
+ 0x100ca57f 0xc _zPHY_euls_ReleaseTTIBundlingMode
+ 0x100ca58b 0x6c _zPHY_euls_GetBundlingIDAndHarqID_InULA
+ 0x100ca5f7 0x75 _zPHY_euls_UpdataHarqID
+ 0x100ca66c 0x8 _zPHY_euls_AddAbsSubframe
+ 0x100ca674 0x66 _zPHY_euls_SetDrxFlag
+ 0x100ca6da 0xcd _zPHY_euls_Dci0SelecAndCsiReport_Proc
+ 0x100ca7a7 0x3d3 _zPHY_euls_CalcDciCsiReqFlag
+ 0x100cab7a 0xf7 _zPHY_euls_CalLutrAndLtx
+ 0x100cac71 0x16 _zPHY_euls_ScheduleTxChannelType
+ 0x100cac87 0x7d _zPHY_euls_SchedulePuschAndPucch
+ 0x100cad04 0x16f _zPHY_euls_DeterminePuschTransType
+ 0x100cae73 0x37 _zPHY_euls_GetPuschHarqAckInfo
+ 0x100caeaa 0x12d _zPHY_euls_DeterminePucchFmt
+ 0x100cafd7 0x26 _zPHY_euls_GetSysTimeInfo
+ 0x100caffd 0x75 _zPHY_euls_TM2_ChanExchange
+ 0x100cb072 0x66 _zPHY_euls_PuschPowerControl_Process
+ 0x100cb0d8 0x50 _zPHY_euls_NoPuschPowerControl_Process
+ 0x100cb128 0x2a _zPHY_euls_GaoTong_Statistics_Process
+ 0x100cb152 0x1 _zPHY_euls_AmtTest_DciStubProcess
+ 0x100cb153 0x39 _zPHY_euls_GetPhichSubFrmNo
+ .text 0x100cb18c 0xa6d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ 0x100cb18c 0x5 _zPHY_ecsrs_GetIdleDrxInterPssWorkTime
+ 0x100cb191 0x165 _zPHY_ecsrs_GetPssStartTime
+ 0x100cb2f6 0x63 _zPHY_ecsrs_AdjustPssStartTime
+ 0x100cb359 0x14e _zPHY_ecsrs_SetPssFirstStartInfo
+ 0x100cb4a7 0xca _zPHY_ecsrs_SetPssNotFirstStartInfo
+ 0x100cb571 0x9a _zPHY_ecsrs_GetPssStartInfo
+ 0x100cb60b 0x4f _zPHY_ecsrs_GetPssReadFlag
+ 0x100cb65a 0x23 _zPHY_ecsrs_ClearPeakList
+ 0x100cb67d 0x1a _zPHY_ecsrs_GetPssData
+ 0x100cb697 0x1c _zPHY_ecsrs_BackupPssFinger
+ 0x100cb6b3 0xb _zPHY_ecsrs_ClearPssFinger
+ 0x100cb6be 0xd _zPHY_ecsrs_ClearInnerPeakList
+ 0x100cb6cb 0x5e _zPHY_ecsrs_AdjustPeakTime
+ 0x100cb729 0x19 _zPHY_ecsrs_FindFreq
+ 0x100cb742 0x3d _zPHY_ecsrs_BackupPeakList
+ 0x100cb77f 0xa8 _zPHY_ecsrs_RecoverPeakList
+ 0x100cb827 0x215 _zPHY_ecsrs_PssResultReadNew
+ 0x100cba3c 0x63 _zPHY_ecsrs_CalBoundary
+ 0x100cba9f 0x2b _zPHY_ecsrs_CalRedoCfoBoundary
+ 0x100cbaca 0x46 _zPHY_ecsrs_PssAdjustPro
+ 0x100cbb10 0x28 _zPHY_ecsrs_PssTpuAdjust
+ 0x100cbb38 0x13 _zPHY_ecsrs_SearchMaxFinger
+ 0x100cbb4b 0xa0 _zPHY_ecsrs_FilterFinger
+ 0x100cbbeb 0xe _zPHY_ecsrs_FingerIsValid
+ .text 0x100cbbf9 0xc54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pusch.o)
+ 0x100cbbf9 0x69 _zPHY_eula_PuschAckProcess
+ 0x100cbc62 0x177 _zPHY_eula_PuschCsiProcess
+ 0x100cbdd9 0xc2 _zPHY_eula_SetPuschScale
+ 0x100cbe9b 0x1ed _zPHY_eula_PuschAckEncodedLenCalc
+ 0x100cc088 0x2b9 _zPHY_eula_TDD_PuschAckParasCalc
+ 0x100cc341 0x57 _zPHY_eula_TDD_PuschAckParasCalc_UlDl0
+ 0x100cc398 0x86 _zPHY_eula_LtxParas_acNcsPuschDmrs
+ 0x100cc41e 0xc7 _zPHY_eula_LtxParas_acUVPuschDmrs
+ 0x100cc4e5 0x290 _zPHY_eula_PuschCqiRiEncodedLenCalc
+ 0x100cc775 0x24 _zPHY_eula_FDD_PuschAckParasCalc
+ 0x100cc799 0x8e _zPHY_eula_LtxParas_adwNcsDiv6PuschDmrs
+ 0x100cc827 0x26 _zPHY_eula_HarqPuschMsg3Stub
+ .text 0x100cc84d 0x547 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
+ 0x100cc84d 0x80 _zPHY_eulpc_PuschPowParasCalc
+ 0x100cc8cd 0x119 _zPHY_eulpc_UlsRelativePuscchPowCtrlProc
+ 0x100cc9e6 0x190 _zPHY_eulpc_PuschPowCalcProc
+ 0x100ccb76 0xa9 _zPHY_eulpc_NoPuschPowCalc
+ 0x100ccc1f 0xb3 _zPHY_eulpc_DeltaTFCalc
+ 0x100cccd2 0x89 _zPHY_eulpc_Log10yLinear
+ 0x100ccd5b 0x39 _zPHY_eulpc_PuschGetCsiInfo
+ .text 0x100ccd94 0x540 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ 0x100ccd94 0x6d _zPHY_edfe_Q8log2
+ 0x100cce01 0x21 _zPHY_edfe_Logarithm
+ 0x100cce22 0x34 _zPHY_edfe_SupCalLog
+ 0x100cce56 0x8 _zPHY_edfe_SetCsrmDAGCGain
+ 0x100cce5e 0x76 _zPHY_edfe_CalcRxDAGCGain
+ 0x100cced4 0xa2 _zPHY_edfe_HandleRxDAGCGain
+ 0x100ccf76 0x57 _zPHY_edfe_FixedRXDagcGain
+ 0x100ccfcd 0x105 _zPHY_edfe_CalcCsrsDAGCGain
+ 0x100cd0d2 0x26 _zPHY_edfe_JudgeRxDagcCover
+ 0x100cd0f8 0x6d _zPHY_edfe_JudgeCsrsDagcCover
+ 0x100cd165 0xa8 _zPHY_edfe_HandleCsrsDagcInt
+ 0x100cd20d 0x39 _zPHY_edfe_ConfigDagcCalcPara
+ 0x100cd246 0x8e _zPHY_edfe_SetInterCsrsDAGCGain
+ .text 0x100cd2d4 0x777 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
+ 0x100cd2d4 0x26 _zAsn1_GetU16Bits
+ 0x100cd2fa 0x39 _zAsn1_SetU16Bits
+ 0x100cd333 0x18 _zEasn1p_perGetConVal
+ 0x100cd34b 0xc _zEasn1p_perGetDivbVal
+ 0x100cd357 0xa _zEasn1p_perGetIntVal
+ 0x100cd361 0x13 _zEasn1p_perGetBitNum
+ 0x100cd374 0x1a _zEasn1p_perGetRange
+ 0x100cd38e 0x67 _zEasn1p_DcGetBitsVal32_Dec
+ 0x100cd3f5 0x2 _zEasn1p_DcGetBitsVal32
+ 0x100cd3f7 0x13 _zEasn1p_MovePtr_Dec
+ 0x100cd40a 0x1d _zEasn1p_EcSetBitStr_Dec
+ 0x100cd427 0xa2 _zEasn1p_DcGetBitsStr_Dec
+ 0x100cd4c9 0x2 _zEasn1p_DcGetBitsStr
+ 0x100cd4cb 0x1a _zEasn1p_ChkCodeLen_Dec
+ 0x100cd4e5 0x91 _zEasn1p_per_dcOctStr
+ 0x100cd576 0xe5 _zEasn1p_per_dcLen
+ 0x100cd65b 0x2f _zEasn1p_per_DcExt
+ 0x100cd68a 0x2f _zEasn1p_per_dcIndefiniteLenWholeNum
+ 0x100cd6b9 0x2e _zEasn1p_per_dcConWholeNum
+ 0x100cd6e7 0x8f _zEasn1p_per_dcSequenceOf
+ 0x100cd776 0x2 _zEasn1p_MovePtr
+ 0x100cd778 0x24 _zEasn1p_per_dcPreamble
+ 0x100cd79c 0x29 _zEasn1p_per_dcPreamble_Sequence
+ 0x100cd7c5 0x47 _zEasn1p_per_dcSmallWholeNum
+ 0x100cd80c 0x46 _zEasn1p_per_dcSkipAllExtData
+ 0x100cd852 0xb7 _zEasn1p_per_dcInt
+ 0x100cd909 0x66 _zEasn1p_per_dcChoiceOf
+ 0x100cd96f 0x4a _zEasn1p_per_dcSkipOneExtData
+ 0x100cd9b9 0x92 _zEasn1p_per_dcBitStr
+ .text 0x100cda4b 0x391 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
+ 0x100cda4b 0x55 _zPHY_ecsrs_GetCfoStartTime
+ 0x100cdaa0 0x54 _zPHY_ecsrs_SetCfoStartInfoSymMap
+ 0x100cdaf4 0xa1 _zPHY_ecsrs_GetCfoStartInfo
+ 0x100cdb95 0x1e _zPHY_ecsrs_CalPowerNcpEcp
+ 0x100cdbb3 0x46 _zPHY_ecsrs_CfoCalcPower
+ 0x100cdbf9 0x5e _zPHY_ecsrs_CfoCalcPowerNcpEcp
+ 0x100cdc57 0x5e _zPHY_ecsrs_Codic_atan_FixPoint
+ 0x100cdcb5 0x76 _zPHY_ecsrs_CsCfoResultMerge
+ 0x100cdd2b 0xb1 _zPHY_ecsrs_CfoResultRead
+ .text 0x100cdddc 0x189 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
+ 0x100cdddc 0x186 _zPHY_edla_CalcPcfichRegFilePara
+ 0x100cdf62 0x3 _zPHY_edla_PcfichProc
+ .text 0x100cdf65 0x1107 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
+ 0x100cdf65 0xb7 _zPHY_ecsrs_SssStartFingerSort
+ 0x100ce01c 0xff _zPHY_ecsrs_SssFingerReorder
+ 0x100ce11b 0x49 _zPHY_ecsrs_AdjustSssFddProc
+ 0x100ce164 0x7c _zPHY_ecsrs_GetSssStartFinger
+ 0x100ce1e0 0x37 _zPHY_ecsrs_GetNearValidTime
+ 0x100ce217 0x33 _zPHY_ecsrs_CalSssBufferTime
+ 0x100ce24a 0x170 _zPHY_ecsrs_GetSssStartTime
+ 0x100ce3ba 0x92 _zPHY_ecsrs_GetRfcEnableInfo
+ 0x100ce44c 0x3e _zPHY_ecsrs_GetSssStartFg
+ 0x100ce48a 0x50 _zPHY_ecsrs_InitSssStartInfo
+ 0x100ce4da 0x8f _zPHY_ecsrs_SetSssFddStartInfoAllProc
+ 0x100ce569 0xb7 _zPHY_ecsrs_SetSssTddStartInfoAllProc
+ 0x100ce620 0x251 _zPHY_ecsrs_SetSssFirstStartInfo
+ 0x100ce871 0xd9 _zPHY_ecsrs_SetSssComStartInfo
+ 0x100ce94a 0x4d _zPHY_ecsrs_GetSssStartInfo
+ 0x100ce997 0x9b _zPHY_ecsrs_GetSssReadFlag
+ 0x100cea32 0xe2 _zPHY_ecsrs_GetThresholdAndFilterCell
+ 0x100ceb14 0x2ae _zPHY_ecsrs_SssResultReadNew
+ 0x100cedc2 0x1a7 _zPHY_ecsrs_SssResultReadAppointCell
+ 0x100cef69 0x28 _zPHY_ecsrs_RecodCfoInfo
+ 0x100cef91 0x3e _zPHY_ecsrs_CheckCfoValid
+ 0x100cefcf 0x77 _zPHY_ecsrs_SearchForSssHwReset
+ 0x100cf046 0x26 _zPHY_ecsrs_SetSssHwCfgTime
+ .text 0x100cf06c 0x172d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ 0x100cf06c 0x5 _zPHY_ecsrs_Init
+ 0x100cf071 0x17 _zPHY_ecsrs_Reset
+ 0x100cf088 0x1 _zPHY_ecsrs_DebugModeInitPara
+ 0x100cf089 0x24 _zPHY_ecsrs_InitCommonInfor
+ 0x100cf0ad 0x1b _zPHY_ecsrs_DeleteAllSubFrameInt
+ 0x100cf0c8 0x8 _zPHY_ecsrs_ResetSynInforTable
+ 0x100cf0d0 0x30 _zPHY_ecsrs_GetIntraEarfcnInfo
+ 0x100cf100 0x1e _zPHY_ecsrs_GetInterEarfcnInfo
+ 0x100cf11e 0x1c4 _zPHY_ecsrs_GetCommonInfor
+ 0x100cf2e2 0x34 _zPHY_ecsrs_CsRfcConfig
+ 0x100cf316 0x1a _zPHY_ecsrs_BeforeInitSearch
+ 0x100cf330 0x15 _zPHY_ecsrs_TimeRelation
+ 0x100cf345 0x88 _zPHY_ecsrs_InterFreqChange
+ 0x100cf3cd 0x62 _zPHY_ecsrs_GetHwConfigMode
+ 0x100cf42f 0x112 _zPHY_ecsrs_GetReadAndConfigIndex
+ 0x100cf541 0x1e _zPHY_ecsrs_SetSyncRelation
+ 0x100cf55f 0x25 _zPHY_ecsrs_TFConfirmSearchMode
+ 0x100cf584 0x31 _zPHY_ecsrs_SetFilterRange
+ 0x100cf5b5 0xd _zPHY_ecsrs_OpenSubFrameInt
+ 0x100cf5c2 0xd _zPHY_ecsrs_DelSubFrameInt
+ 0x100cf5cf 0x8 _zPHY_ecsrs_UpdateInnOffset
+ 0x100cf5d7 0x2b _zPHY_ecsrs_ReadSearchResult
+ 0x100cf602 0x3d _zPHY_ecsrs_GetSubTime
+ 0x100cf63f 0x31 _L1e_csrs_InitGloPara
+ 0x100cf670 0x8 _zPHY_ecsrs_OnReset
+ 0x100cf678 0x3 _zPHY_ecsrs_OnSearchMeasReset
+ 0x100cf67b 0x49 _zPHY_ecsrs_OnSearchFreqScan
+ 0x100cf6c4 0x81 _zPHY_ecsrs_OnSearchMeasStart
+ 0x100cf745 0x1f _zPHY_ecsrs_OnPssUpdateCounterCnf
+ 0x100cf764 0x70 _zPHY_ecsrs_OnTimeDelayInt
+ 0x100cf7d4 0xd _zPHY_ecsrs_OnNotSynSubFrameInt
+ 0x100cf7e1 0x57 _zPHY_ecsrs_InitFreqOffset
+ 0x100cf838 0xa6 _L1e_csrs_GetFreqOffset
+ 0x100cf8de 0x6e _L1e_csrs_SetFtErrorList
+ 0x100cf94c 0x65 _L1e_csrs_SetFreqOffsetAge
+ 0x100cf9b1 0x11 _L1e_csrs_GetMaxAgeIndex
+ 0x100cf9c2 0x2f _L1e_csrs_NormalTemp
+ 0x100cf9f1 0x89 _zPHY_ecsrs_ModifyRfCfgInfo
+ 0x100cfa7a 0x7 _zPHY_ecsrs_setMode
+ 0x100cfa81 0xa _zPHY_ecsrs_IsIntraMode
+ 0x100cfa8b 0x86 _zEcsrs_PreEvent
+ 0x100cfb11 0x9e _L1e_csrs_SfProc
+ 0x100cfbaf 0x2c _L1e_FS_SfProc
+ 0x100cfbdb 0x2e _zEcsrs_OnEvent
+ 0x100cfc09 0xb _zPHY_ecsrs_IsInitCs
+ 0x100cfc14 0x3c _zPHY_ecsrs_CsNeedReCfo
+ 0x100cfc50 0x16 _zPHY_ecsrs_CsNeedReSss
+ 0x100cfc66 0x67 _zPHY_ecsrs_IsRfOpen
+ 0x100cfccd 0x14c _zPHY_csr_RfcConfig
+ 0x100cfe19 0x1e _zPHY_ecsrs_IsOptSearch
+ 0x100cfe37 0x1a _zPHY_ecsrs_CfoAccNum
+ 0x100cfe51 0x1a _zPHY_ecsrs_GetConfigRfFlag
+ 0x100cfe6b 0x3d _zPHY_ecsrs_GetScheduleFlag
+ 0x100cfea8 0x9 _zPHY_ecsrs_CsBeforeAgc
+ 0x100cfeb1 0x17 _zPHY_ecsrs_CsNeedAgc
+ 0x100cfec8 0x6b _zPHY_ecsrs_CsNeedPss
+ 0x100cff33 0x2 _zPHY_ecsrs_CsNeedCfo
+ 0x100cff35 0x82 _zPHY_ecsrs_CsNeedSss
+ 0x100cffb7 0x16 _zPHY_ecsrs_CsNeedTempComp
+ 0x100cffcd 0x26 _zPHY_ecsrs_CsIsOnAgc
+ 0x100cfff3 0x37 _zPHY_ecsrs_CsAgcProc
+ 0x100d002a 0x1 _zPHY_ecsrs_CsAgcProcEnd
+ 0x100d002b 0xd _zPHY_ecsrs_CsNeedPssAgain
+ 0x100d0038 0x17 _zPHY_ecsrs_CsBeforePss
+ 0x100d004f 0x1a _zPHY_ecsrs_CsIsOnPss
+ 0x100d0069 0x91 _zPHY_ecsrs_CsGetPssRfCfgInfo
+ 0x100d00fa 0x50 _zPHY_ecsrs_SniffInterFreqChange
+ 0x100d014a 0x13b _zPHY_ecsrs_CsPssProc
+ 0x100d0285 0xda _zPHY_ecsrs_CsPssProcEnd
+ 0x100d035f 0x2a _zPHY_ecsrs_CsNeedMoreCfo
+ 0x100d0389 0x23 _zPHY_ecsrs_CsBeforeCfo
+ 0x100d03ac 0x12 _zPHY_ecsrs_CsCfoTpuAdjPro
+ 0x100d03be 0x14 _zPHY_ecsrs_CsIsOnCfo
+ 0x100d03d2 0x6f _zPHY_ecsrs_CsCfoProc
+ 0x100d0441 0x60 _zPHY_ecsrs_CsCfoProcEnd
+ 0x100d04a1 0x13 _zPHY_ecsrs_CsBeforeSss
+ 0x100d04b4 0x1a _zPHY_ecsrs_CsIsOnSss
+ 0x100d04ce 0x8d _zPHY_ecsrs_CsGetSssRfCfgInfo
+ 0x100d055b 0x12d _zPHY_ecsrs_CsSssProc
+ 0x100d0688 0x1d _zPHY_ecsrs_InitSearchCnf
+ 0x100d06a5 0x56 _zPHY_ecsrs_CsSssProcEnd
+ 0x100d06fb 0x18 _zPHY_ecsrs_CsNeedCs
+ 0x100d0713 0x1a _zPHY_ecsrs_CsBeforeCs
+ 0x100d072d 0xb _zPHY_ecsrs_WaitSubFrameInt
+ 0x100d0738 0x1c _zPHY_ecsrs_SSSearctT
+ 0x100d0754 0x3d _zPHY_ecsrs_CheckSssCount
+ 0x100d0791 0x8 _zPHY_ecsrs_SetSssHwRestartCnt
+ .text 0x100d0799 0x3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_ti.o)
+ .text 0x100d07d5 0x458 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ 0x100d07d5 0x13 _zPHY_ecsrs_HwIntHandle
+ 0x100d07e8 0x49 _zPHY_ecsrs_HwReset
+ 0x100d0831 0x33 _zPHY_ecsrs_AllHwReset
+ 0x100d0864 0x15 _zPHY_ecsr_HwSssTdCommonReset
+ 0x100d0879 0xa3 _zPHY_ecsrs_ConfigIcFiFoHw
+ 0x100d091c 0x8a _zPHY_ecsrs_ConfigIcHw
+ 0x100d09a6 0x4f _zPHY_ecsrs_ConfigPssHw
+ 0x100d09f5 0x36 _zPHY_ecsrs_ConfigCfoHw
+ 0x100d0a2b 0x47 _zPHY_ecsrs_ConfigSssHw
+ 0x100d0a72 0xc _zPHY_ecsrs_CfgTopClkGating
+ 0x100d0a7e 0x14 _zPHY_ecsrs_CfgTopReg
+ 0x100d0a92 0x27 _zPHY_ecsrs_SssCfgPschLocalSeq
+ 0x100d0ab9 0x31 _zPHY_ecsrs_AgcBalanceCfgRegs
+ 0x100d0aea 0xc _zPHY_ecsrs_AgcBalanceDisable
+ 0x100d0af6 0x23 _zPHY_ecsrc_SwClkGateCtrl
+ 0x100d0b19 0x49 _zPHY_ecsr_ConvertFinger
+ 0x100d0b62 0x1f _zPHY_ecsr_GetHwPssFinger
+ 0x100d0b81 0x8 _zPHY_ecsr_GetHwPssFreqInd
+ 0x100d0b89 0xd _zPHY_ecsr_GetHwPssDoneMark
+ 0x100d0b96 0xd _zPHY_ecsr_GetHwPssNumHalfFrame
+ 0x100d0ba3 0x3 _zPHY_ecsr_GetHwPssPeakValid
+ 0x100d0ba6 0x8 _zPHY_ecsr_GetHwPssMaxPower
+ 0x100d0bae 0xa _zPHY_ecsr_GetHwCfoOutput
+ 0x100d0bb8 0x10 _zPHY_ecsr_GetHwSssPeakList
+ 0x100d0bc8 0xa _zPHY_ecsr_GetHwSssComResult
+ 0x100d0bd2 0xb _zPHY_ecsr_GetHwSssProcCount
+ 0x100d0bdd 0xb _zPHY_ecsr_GetHwSssProcStatus
+ 0x100d0be8 0xd _zPHY_ecsr_GetHwSssProcEnable
+ 0x100d0bf5 0x8 _zPHY_ecsr_GetHwSssProcRdWrState
+ 0x100d0bfd 0x8 _zPHY_ecsr_GetHwIcWorkState
+ 0x100d0c05 0x8 _zPHY_ecsr_GetHwTopClkGating
+ 0x100d0c0d 0x8 _zPHY_ecsr_GetHwPssClkGatingBypass
+ 0x100d0c15 0x8 _zPHY_ecsr_GetHwIcClkGatingBypass
+ 0x100d0c1d 0x8 _zPHY_ecsr_GetHwSssClkGatingEn
+ 0x100d0c25 0x8 _zPHY_ecsr_GetHwSssWorkStatus
+ .text 0x100d0c2d 0x571 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_fs.o)
+ 0x100d0c2d 0x2f _L1e_FS_LogAddSearchResult
+ 0x100d0c5c 0x25 _L1e_FS_LogAddSearchResultFail
+ 0x100d0c81 0x14 _L1e_FS_LogGainCompenError
+ 0x100d0c95 0x17 _L1e_FS_LogMinAgcGainError
+ 0x100d0cac 0x17 _L1e_FS_LogDeleteEarfcn
+ 0x100d0cc3 0x2d _L1e_FS_LogSssResult
+ 0x100d0cf0 0x17 _L1e_FS_LogFsResultNum
+ 0x100d0d07 0x1e _L1e_FS_LogDeleteFreqPoint
+ 0x100d0d25 0x5c _L1e_FS_LogBandInfo
+ 0x100d0d81 0x40 _L1e_FS_LogProfileInfo
+ 0x100d0dc1 0x38 _L1e_FS_LogInsertPSSResult
+ 0x100d0df9 0x54 _L1e_FS_LogAddSearchwEarfcn
+ 0x100d0e4d 0x21 _L1e_FS_LogPlmnReturnSrvCell
+ 0x100d0e6e 0x95 _L1e_FS_LogPSSFinger
+ 0x100d0f03 0x14 _L1e_FS_LogPSSNoValidEarfcn
+ 0x100d0f17 0x22 _L1e_FS_LogResultNULL
+ 0x100d0f39 0x1d _L1e_FS_LogChangeAgc
+ 0x100d0f56 0x1a _L1e_FS_LogAllAgcFail
+ 0x100d0f70 0x14 _L1e_FS_LogReqMsgError
+ 0x100d0f84 0x41 _L1e_FS_LogSegmeantInfo
+ 0x100d0fc5 0x31 _L1e_FS_LogSssAgcGain
+ 0x100d0ff6 0x26 _L1e_FS_LogMpInfo
+ 0x100d101c 0x5b _L1e_FS_LogProGainInfo
+ 0x100d1077 0x1d _L1e_FS_LogAGCInfo
+ 0x100d1094 0x4a _L1e_FS_LogProRedo100KInfo
+ 0x100d10de 0x1d _L1e_FS_StartAGC
+ 0x100d10fb 0x2a _L1e_FS_AGCInfo
+ 0x100d1125 0x27 _L1e_FS_TestInfo
+ 0x100d114c 0x1e _L1e_FS_LogBackup100KResult
+ 0x100d116a 0x17 _L1e_FS_LogFreqOffsetIndex
+ 0x100d1181 0x1d _zPHY_ecsc_LogPss100KResult
+ .text 0x100d119e 0x10f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrs.o)
+ 0x100d119e 0x35 _zPHY_ecsrc_LogSlaveSearchMode
+ 0x100d11d3 0x34 _zPHY_ecsrc_LogRecvUpdateCounterCnf
+ 0x100d1207 0x64 _zPHY_ecsrc_LogPssTpuAdjust3
+ 0x100d126b 0x26 _zPHY_ecsrc_LogModifyRfCfgInfo
+ 0x100d1291 0x85 _zPHY_ecsrc_LogIsRfOpen
+ 0x100d1316 0x4f _zPHY_ecsrs_LogCommonInfor
+ 0x100d1365 0x36 _zPHY_ecsrs_LogInterFreqChange
+ 0x100d139b 0x2e _zPHY_ecsrs_LogGetHwConfigMode
+ 0x100d13c9 0x34 _zPHY_ecsrs_LogGetReadAndConfigIndex
+ 0x100d13fd 0x18 _zPHY_ecsrs_LogTFConfirmSearchMode
+ 0x100d1415 0x19 _zPHY_ecsrs_LogGetSubTime
+ 0x100d142e 0x16 _zPHY_ecsrs_LogSubFrameOnOff
+ 0x100d1444 0xba _zPHY_ecsrs_LogCsPssPro
+ 0x100d14fe 0x48 _zPHY_ecsrs_LogGetPssStartTime
+ 0x100d1546 0x14 _zPHY_ecsrs_LogCsCfoProcEnd
+ 0x100d155a 0x9a _zPHY_ecsrs_LogCsSssPro
+ 0x100d15f4 0x3e _zPHY_ecsrpss_LogAdjustPssStartTime
+ 0x100d1632 0x1c _zPHY_ecsrpss_LogUrfcnFreqIdx
+ 0x100d164e 0x57 _zPHY_ecsrpss_LogSearchResult
+ 0x100d16a5 0x5f _zPHY_ecsrpss_LogPssDb
+ 0x100d1704 0x1b _zPHY_ecsrpss_LogSendRfcOffset
+ 0x100d171f 0x2a _zPHY_ecsrpss_LogCalRedoCfoBoundary
+ 0x100d1749 0x2a _zPHY_ecsrpss_LogFilterFinger
+ 0x100d1773 0x4d _zPHY_ecsrSss_LogStartFinger
+ 0x100d17c0 0x3c _zPHY_ecsrSss_LogStartTime
+ 0x100d17fc 0x4f _zPHY_ecsrSss_LogStartFingerAll
+ 0x100d184b 0x4a _zPHY_ecsrSss_LogSLAVE_HWStart
+ 0x100d1895 0x22 _zPHY_ecsrSss_LogGetRfcEnableInfo
+ 0x100d18b7 0x27 _zPHY_ecsrSss_LogReadFlagInfor
+ 0x100d18de 0xc5 _zPHY_ecsrSss_LogThreshold
+ 0x100d19a3 0x5d _zPHY_ecsrSss_LogResultInfo
+ 0x100d1a00 0x65 _zPHY_ecsrSss_LogSssFingerReorder
+ 0x100d1a65 0x18 _zPHY_ecsrSss_LogAdjustSssFddProc
+ 0x100d1a7d 0x2e _zPHY_ecsrSss_LogSssState
+ 0x100d1aab 0x62 _zPHY_ecsrSss_LogStartFingerAfterSort
+ 0x100d1b0d 0x14 _zPHY_ecsrSss_LogGetSssStartInfo
+ 0x100d1b21 0x27 _zPHY_ecsrCfo_LogFreqOffset
+ 0x100d1b48 0x6a _zPHY_ecsrCfo_LogSLAVE_HWStart
+ 0x100d1bb2 0x28 _zPHY_ecsrCfo_LogCfoResultMerge
+ 0x100d1bda 0x41 _zPHY_ecsrIc_LogCellFlag
+ 0x100d1c1b 0x7e _zPHY_ecsrIc_LogCoverInfo
+ 0x100d1c99 0x60 _zPHY_ecsrIc_LogCellInfo
+ 0x100d1cf9 0xa9 _zPHY_ecsrs_LogCfgIcFifo
+ 0x100d1da2 0x191 _zPHY_ecsrs_LogCfgIc
+ 0x100d1f33 0x136 _zPHY_ecsrs_LogCfgPssHw
+ 0x100d2069 0x5f _zPHY_ecsrs_LogCfgCfoHw
+ 0x100d20c8 0x138 _zPHY_ecsrs_LogCfgSssHw
+ 0x100d2200 0x20 _zPHY_ecsrSss_LogCheckCfoValid
+ 0x100d2220 0x2d _L1e_csrs_LogSetFtErrorList
+ 0x100d224d 0x25 _L1e_csrs_LogSetFreqOffsetAge
+ 0x100d2272 0x1e _L1e_csrs_LogGetFreqOffset
+ .text 0x100d2290 0x4e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_list.o)
+ 0x100d2290 0x1c _zPHY_ecsrs_ListInsert
+ 0x100d22ac 0x5 _zPHY_ecsrs_ListAdd
+ 0x100d22b1 0x1a _zPHY_ecsrs_ListDelete
+ 0x100d22cb 0x3 _zPHY_ecsrs_ListFirst
+ 0x100d22ce 0x3 _zPHY_ecsrs_ListLast
+ 0x100d22d1 0x2 _zPHY_ecsrs_ListNext
+ 0x100d22d3 0x3 _zPHY_ecsrs_ListPrev
+ 0x100d22d6 0x8 _zPHY_ecsrs_IsListEmpty
+ .text 0x100d22de 0x9c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(crepool.o)
+ 0x100d22de 0x9c _s_create_pool
+ .text 0x100d237a 0x20 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cresem.o)
+ 0x100d237a 0x20 _create_sem
+ .text 0x100d239a 0x9 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(current.o)
+ 0x100d239a 0x9 _current_process
+ .text 0x100d23a3 0x50 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(delay.o)
+ 0x100d23a3 0x50 _delay
+ .text 0x100d23f3 0x63 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(free.o)
+ 0x100d23f3 0x63 _free_buf
+ .text 0x100d2456 0x49 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(get_pri.o)
+ 0x100d2456 0x49 _get_pri
+ .text 0x100d249f 0x8 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(getticks.o)
+ 0x100d249f 0x8 _get_ticks
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+ 0x10118e8b 0x101 ___ctype
+ .data 0x10118f8c 0x4 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(pr_routines.o)
+ 0x10118f8c 0x2 _ZSP_get_cycle_ZSP_overridePtr
+ 0x10118f8e 0x2 _ZSP_get_insn_ZSP_overridePtr
+ 0x10118f90 __incsram_loadaddr = .
+ 0x10118f90 0x2 LONG 0x8090000 (<code 338> (LOADADDR (.itcm)) / 0x2)
+ 0x10118f92 __incsram_size = .
+ 0x10118f92 0x2 LONG 0x37ac (SIZEOF (.itcm) / 0x2)
+ 0x10118f94 __dncsram_loadaddr = .
+ 0x10118f94 0x2 LONG 0x8094000 (<code 338> (LOADADDR (.dtcm)) / 0x2)
+ 0x10118f96 __dncsram_size = .
+ 0x10118f96 0x2 LONG 0x35ad (SIZEOF (.dtcm) / 0x2)
+ 0x10118f98 __L2_code_s_loadaddr = .
+ 0x10118f98 0x2 LONG 0x806a618 (<code 338> (LOADADDR (.c2tcm_s)) / 0x2)
+ 0x10118f9a __L2_code_s_size = .
+ 0x10118f9a 0x2 LONG 0x4 (SIZEOF (.c2tcm_s) / 0x2)
+ 0x10118f9c __L2_code_d_loadaddr = .
+ 0x10118f9c 0x2 LONG 0x806a620 (<code 338> (LOADADDR (.c2tcm_d)) / 0x2)
+ 0x10118f9e __L2_code_d_size = .
+ 0x10118f9e 0x2 LONG 0x4 (SIZEOF (.c2tcm_d) / 0x2)
+ 0x10118fa0 __L2_code_d_loadaddr_update1 = .
+ 0x10118fa0 0x2 LONG 0x806a628 (<code 338> (LOADADDR (.c2tcm_d_update1)) / 0x2)
+ 0x10118fa2 __L2_code_d_size_update1 = .
+ 0x10118fa2 0x2 LONG 0x4 (SIZEOF (.c2tcm_d_update1) / 0x2)
+ 0x10118fa4 __L2_code_d_loadaddr_update2 = .
+ 0x10118fa4 0x2 LONG 0x806a630 (<code 338> (LOADADDR (.c2tcm_d_update2)) / 0x2)
+ 0x10118fa6 __L2_code_d_size_update2 = .
+ 0x10118fa6 0x2 LONG 0x4 (SIZEOF (.c2tcm_d_update2) / 0x2)
+ 0x10118fa8 __L2_data_s_loadaddr = .
+ 0x10118fa8 0x2 LONG 0x806a638 (<code 338> (LOADADDR (.d2tcm_s)) / 0x2)
+ 0x10118faa __L2_data_s_size = .
+ 0x10118faa 0x2 LONG 0xa (SIZEOF (.d2tcm_s) / 0x2)
+ 0x10118fac __L2_data_d_loadaddr = .
+ 0x10118fac 0x2 LONG 0x806a648 (<code 338> (LOADADDR (.d2tcm_d)) / 0x2)
+ 0x10118fae __L2_data_d_size = .
+ 0x10118fae 0x2 LONG 0x0 (SIZEOF (.d2tcm_d) / 0x2)
+ 0x10118fb0 __L2_data_d_loadaddr_update1 = .
+ 0x10118fb0 0x2 LONG 0x806a650 (<code 338> (LOADADDR (.d2tcm_d_update1)) / 0x2)
+ 0x10118fb2 __L2_data_d_size_update1 = .
+ 0x10118fb2 0x2 LONG 0x0 (SIZEOF (.d2tcm_d_update1) / 0x2)
+ 0x10118fb4 __L2_data_d_loadaddr_update2 = .
+ 0x10118fb4 0x2 LONG 0x806a658 (<code 338> (LOADADDR (.d2tcm_d_update2)) / 0x2)
+ 0x10118fb6 __L2_data_d_size_update2 = .
+ 0x10118fb6 0x2 LONG 0x0 (SIZEOF (.d2tcm_d_update2) / 0x2)
+ 0x10118fb8 __lp_text_addr = .
+ 0x10118fb8 0x2 LONG 0x806a500 (<code 338> (ADDR (.lp_text)) / 0x2)
+ 0x10118fba __lp_text_loadaddr = .
+ 0x10118fba 0x2 LONG 0x806a500 (<code 338> (LOADADDR (.lp_text)) / 0x2)
+ 0x10118fbc __lp_text_size = .
+ 0x10118fbc 0x2 LONG 0x112 (SIZEOF (.lp_text) / 0x2)
-.display 0x10118fb0 0x820
+.display 0x10118fc0 0x820
*(.display_data_buffer)
.display_data_buffer
- 0x10118fb0 0x820 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_reg_eng.o)
- 0x10118fb0 0x820 _g_tDisplayDataBufferTd
+ 0x10118fc0 0x820 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_reg_eng.o)
+ 0x10118fc0 0x820 _g_tDisplayDataBufferTd
-.save_zsp 0x101197d0 0x100
+.save_zsp 0x101197e0 0x100
*(.save_zsp_data)
.save_zsp_data
- 0x101197d0 0x100 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+ 0x101197e0 0x100 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
-.bss 0x101198d0 0x65f40 load address 0x101198d0
- 0x101198d0 ___bss_start = .
+.bss 0x101198e0 0x65f50 load address 0x101198e0
+ 0x101198e0 ___bss_start = .
*(.bss)
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- .bss 0x1011a6f9 0x4d T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_tadv.o)
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- .bss 0x1011a77a 0x709 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_db.o)
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- .bss 0x1011be16 0x173 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_cs.o)
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- .bss 0x1011bfc4 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_fs.o)
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- .bss 0x1011c237 0x8b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_dpch.o)
- .bss 0x1011c2c2 0x3a T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_hsdpa.o)
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- .bss 0x1011cb2c 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
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- .bss 0x1011f0f4 0x14d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
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- .bss 0x10121e7d 0xbd2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
- *fill* 0x10122a4f 0x80000001 00
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- .bss 0x10123c0f 0x1b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
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- *fill* 0x10129393 0x80000001 00
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- .bss 0x10129694 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
- .bss 0x101296e4 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
- .bss 0x101296e7 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
- .bss 0x101296e8 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
- .bss 0x101296ea 0x34 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(userIO.o)
+ .bss 0x101198e0 0x19 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(bsp_timer_zsp880.o)
+ .bss 0x101198f9 0x40 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ .bss 0x10119939 0x22c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ .bss 0x10119b65 0x40 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ .bss 0x10119ba5 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hspadldec.o)
+ .bss 0x10119ba6 0xf T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rfc.o)
+ .bss 0x10119bb5 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hspa.o)
+ .bss 0x10119bb6 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rtx_rx.o)
+ .bss 0x10119bb7 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rtx.o)
+ .bss 0x10119bb8 0x8 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hsdpa.o)
+ .bss 0x10119bc0 0x3 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls.o)
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+ .bss 0x10119c05 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_eng.o)
+ .bss 0x10119c06 0x2 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(L1_dev_rfc_db.o)
+ .bss 0x10119c08 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_meas.o)
+ .bss 0x10119c09 0x2 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hsupa.o)
+ .bss 0x10119c0b 0x26 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_afc.o)
+ .bss 0x10119c31 0xad8 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_db.o)
+ .bss 0x1011a709 0x4d T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_tadv.o)
+ .bss 0x1011a756 0x6 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_top.o)
+ .bss 0x1011a75c 0x4 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_main.o)
+ .bss 0x1011a760 0x24 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_sync.o)
+ .bss 0x1011a784 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_meas_db.o)
+ .bss 0x1011a785 0x5 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_fsm.o)
+ .bss 0x1011a78a 0x709 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_db.o)
+ .bss 0x1011ae93 0xf91 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_res_alloc.o)
+ .bss 0x1011be24 0x2 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_amt.o)
+ .bss 0x1011be26 0x173 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_cs.o)
+ .bss 0x1011bf99 0x3b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_gap.o)
+ .bss 0x1011bfd4 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_fs.o)
+ .bss 0x1011bfd5 0x8 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_dst.o)
+ .bss 0x1011bfdd 0x26a T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_csr.o)
+ .bss 0x1011c247 0x8b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_dpch.o)
+ .bss 0x1011c2d2 0x3a T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_hsdpa.o)
+ .bss 0x1011c30c 0x5 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_ra.o)
+ .bss 0x1011c311 0x8d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o)
+ .bss 0x1011c39e 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ .bss 0x1011c39f 0x77d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ .bss 0x1011cb1c 0x1f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
+ .bss 0x1011cb3b 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ .bss 0x1011cb3c 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ .bss 0x1011cb3f 0x6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ .bss 0x1011cb45 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ .bss 0x1011cb46 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ .bss 0x1011cb86 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
+ .bss 0x1011cb87 0x22dd T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ .bss 0x1011ee64 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ .bss 0x1011ee68 0x29c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ .bss 0x1011f104 0x14d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
+ .bss 0x1011f251 0x2c3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ .bss 0x10121e8d 0xbd2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ *fill* 0x10122a5f 0x80000001 00
+ .bss 0x10122a60 0xec7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ .bss 0x10123927 0x2ef T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_ds.o)
+ .bss 0x10123c16 0x8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ .bss 0x10123c1e 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ .bss 0x10123c1f 0x1b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ .bss 0x10123c3a 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ .bss 0x10123c3d 0x439 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o)
+ .bss 0x10124076 0xf85 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
+ .bss 0x10124ffb 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas.o)
+ .bss 0x10124ffd 0x2ef T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+ .bss 0x101252ec 0x392 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_bch.o)
+ .bss 0x1012567e 0x43a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cs.o)
+ .bss 0x10125ab8 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_gap.o)
+ .bss 0x10125abb 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o)
+ .bss 0x10125abc 0x259c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
+ .bss 0x10128058 0x1d2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ .bss 0x1012822a 0x564 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ .bss 0x1012878e 0x1e1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ .bss 0x1012896f 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ .bss 0x10128970 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ .bss 0x10128973 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ .bss 0x10128979 0x981 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ .bss 0x101292fa 0x24 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ .bss 0x1012931e 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ .bss 0x1012931f 0x82 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ .bss 0x101293a1 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ *fill* 0x101293a3 0x80000001 00
+ .bss 0x101293a4 0x45 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ .bss 0x101293e9 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ .bss 0x101293ec 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ .bss 0x101293ee 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ .bss 0x101293f2 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ .bss 0x101293f3 0x234 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ .bss 0x10129627 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ .bss 0x1012962f 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ .bss 0x10129630 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ .bss 0x10129632 0x72 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ .bss 0x101296a4 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ .bss 0x101296a6 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ .bss 0x101296f6 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ .bss 0x101296f9 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ .bss 0x101296fa 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ .bss 0x101296fc 0x34 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(userIO.o)
*(COMMON)
- COMMON 0x1012971e 0x6 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ COMMON 0x10129730 0x6 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
0x0 (size before relaxing)
- 0x1012971e 0x6 _err_msg
- COMMON 0x10129724 0x18f T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ 0x10129730 0x6 _err_msg
+ COMMON 0x10129736 0x18f T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
0x0 (size before relaxing)
- 0x10129724 0x18f _odo_sys
- COMMON 0x101298b3 0x44 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ 0x10129736 0x18f _odo_sys
+ COMMON 0x101298c5 0x44 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
0x0 (size before relaxing)
- 0x101298b3 0x1 _zsp_cmm_len
- 0x101298b4 0x5 _g_L1ErrInfo
- 0x101298b9 0x3e _zsp_ramdump_regs
- COMMON 0x101298f7 0x364 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x101298c5 0x1 _zsp_cmm_len
+ 0x101298c6 0x5 _g_L1ErrInfo
+ 0x101298cb 0x3e _zsp_ramdump_regs
+ COMMON 0x10129909 0x364 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
0x0 (size before relaxing)
- 0x101298f7 0x1 _g_erfc_cnt
- 0x101298f8 0x302 _g_atHookInfo
- 0x10129bfa 0x60 _g_erfc_tpu
- 0x10129c5a 0x1 _gIramHookCnt
- COMMON 0x10129c5b 0x1c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ 0x10129909 0x1 _g_erfc_cnt
+ 0x1012990a 0x302 _g_atHookInfo
+ 0x10129c0c 0x60 _g_erfc_tpu
+ 0x10129c6c 0x1 _gIramHookCnt
+ COMMON 0x10129c6d 0x1c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
0x0 (size before relaxing)
- 0x10129c5b 0x1 _g_wRficRev
- 0x10129c5c 0x1b _g_awTempDAC
- COMMON 0x10129c77 0x1a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x10129c6d 0x1 _g_wRficRev
+ 0x10129c6e 0x1b _g_awTempDAC
+ COMMON 0x10129c89 0x1a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
0x0 (size before relaxing)
- 0x10129c77 0x1a _g_tL1wCallStackInfo
- COMMON 0x10129c91 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ 0x10129c89 0x1a _g_tL1wCallStackInfo
+ COMMON 0x10129ca3 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
0x0 (size before relaxing)
- 0x10129c91 0x1 _g_uComPhyFunc
- COMMON 0x10129c92 0xd00 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ 0x10129ca3 0x1 _g_uComPhyFunc
+ COMMON 0x10129ca4 0xd00 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
0x0 (size before relaxing)
- 0x10129c92 0x100 _gReadBlockCnt
- 0x10129d92 0x100 _RpMsgRead_Exit
- 0x10129e92 0x100 _gWriteBlockCnt
- 0x10129f92 0x100 _gRpMsgWriteMutex
- 0x1012a092 0x100 _s_RpMsgCallbackList
- 0x1012a192 0x300 _phy2ps_chinfo
- 0x1012a492 0x100 _rpMsgSem
- 0x1012a592 0x300 _ps2phy_chinfo
- 0x1012a892 0x100 _gRpMsgReadMutex
- COMMON 0x1012a992 0x9 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ 0x10129ca4 0x100 _gReadBlockCnt
+ 0x10129da4 0x100 _RpMsgRead_Exit
+ 0x10129ea4 0x100 _gWriteBlockCnt
+ 0x10129fa4 0x100 _gRpMsgWriteMutex
+ 0x1012a0a4 0x100 _s_RpMsgCallbackList
+ 0x1012a1a4 0x300 _phy2ps_chinfo
+ 0x1012a4a4 0x100 _rpMsgSem
+ 0x1012a5a4 0x300 _ps2phy_chinfo
+ 0x1012a8a4 0x100 _gRpMsgReadMutex
+ COMMON 0x1012a9a4 0x9 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
0x0 (size before relaxing)
- 0x1012a992 0x2 _g_L1_tModeState
- 0x1012a994 0x6 _g_L1_tLpmCaliTime
- 0x1012a99a 0x1 _g_L1_tLpCalibrationFlag
- COMMON 0x1012a99b 0x2f4b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_nv_param.o)
+ 0x1012a9a4 0x2 _g_L1_tModeState
+ 0x1012a9a6 0x6 _g_L1_tLpmCaliTime
+ 0x1012a9ac 0x1 _g_L1_tLpCalibrationFlag
+ COMMON 0x1012a9ad 0x2f4b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_nv_param.o)
0x0 (size before relaxing)
- 0x1012a99b 0x2 _g_tL1tdsAtNv
- 0x1012a99d 0x282 _g_tTdscdmaUserNv
- 0x1012ac1f 0x2ba2 _g_tTdscdmaCalibNv
- 0x1012d7c1 0x125 _g_tPhyNvPara
- COMMON 0x1012d8e6 0x10 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rfc.o)
+ 0x1012a9ad 0x2 _g_tL1tdsAtNv
+ 0x1012a9af 0x282 _g_tTdscdmaUserNv
+ 0x1012ac31 0x2ba2 _g_tTdscdmaCalibNv
+ 0x1012d7d3 0x125 _g_tPhyNvPara
+ COMMON 0x1012d8f8 0x10 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rfc.o)
0x0 (size before relaxing)
- 0x1012d8e6 0x2 _g_DschDelatSfn
- 0x1012d8e8 0x1 _g_wDschPerFstSlot
- 0x1012d8e9 0x4 _g_tRfcRxNotchInfo
- 0x1012d8ed 0x1 _g_wDschFirstSlotId
- 0x1012d8ee 0x1 _g_swTadv
- 0x1012d8ef 0x6 _g_tRfcRdBackInfo
- 0x1012d8f5 0x1 _g_wSscCfltCnt
- COMMON 0x1012d8f6 0xfd T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hsdpa.o)
+ 0x1012d8f8 0x2 _g_DschDelatSfn
+ 0x1012d8fa 0x1 _g_wDschPerFstSlot
+ 0x1012d8fb 0x4 _g_tRfcRxNotchInfo
+ 0x1012d8ff 0x1 _g_wDschFirstSlotId
+ 0x1012d900 0x1 _g_swTadv
+ 0x1012d901 0x6 _g_tRfcRdBackInfo
+ 0x1012d907 0x1 _g_wSscCfltCnt
+ COMMON 0x1012d908 0xfd T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hsdpa.o)
0x0 (size before relaxing)
- 0x1012d8f6 0x18 _g_atHsdpaSpsHssichInfTab
- 0x1012d90e 0x18 _g_atHsdpaHssichInfTab
- 0x1012d926 0x4f _g_tDevHsdpaPcInfo
- 0x1012d975 0x40 _g_awHsdschTbsTab
- 0x1012d9b5 0x33 _g_tHsdpaDbgInfo
- 0x1012d9e8 0x9 _g_atHsdpaScchHssichInfTab
- 0x1012d9f1 0x2 _g_pwRtbsThresholdTab
- COMMON 0x1012d9f3 0xf T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls.o)
+ 0x1012d908 0x18 _g_atHsdpaSpsHssichInfTab
+ 0x1012d920 0x18 _g_atHsdpaHssichInfTab
+ 0x1012d938 0x4f _g_tDevHsdpaPcInfo
+ 0x1012d987 0x40 _g_awHsdschTbsTab
+ 0x1012d9c7 0x33 _g_tHsdpaDbgInfo
+ 0x1012d9fa 0x9 _g_atHsdpaScchHssichInfTab
+ 0x1012da03 0x2 _g_pwRtbsThresholdTab
+ COMMON 0x1012da05 0xf T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls.o)
0x0 (size before relaxing)
- 0x1012d9f3 0xf _g_tL1DevDlsDstEng
- COMMON 0x1012da02 0x2 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_hsupa.o)
+ 0x1012da05 0xf _g_tL1DevDlsDstEng
+ COMMON 0x1012da14 0x2 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc_hsupa.o)
0x0 (size before relaxing)
- 0x1012da02 0x2 _U_TdResPos
- COMMON 0x1012da04 0x7c T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc.o)
+ 0x1012da14 0x2 _U_TdResPos
+ COMMON 0x1012da16 0x7c T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_pc.o)
0x0 (size before relaxing)
- 0x1012da04 0x18 _g_atDlpcLimitInfo
- 0x1012da1c 0x55 _g_tPcEngInfo
- 0x1012da71 0xf _g_tPcPubInfo
- COMMON 0x1012da80 0x262 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_eng.o)
+ 0x1012da16 0x18 _g_atDlpcLimitInfo
+ 0x1012da2e 0x55 _g_tPcEngInfo
+ 0x1012da83 0xf _g_tPcPubInfo
+ COMMON 0x1012da92 0x262 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_eng.o)
0x0 (size before relaxing)
- 0x1012da80 0x1f _g_awMsgTypeRpt
- 0x1012da9f 0x1 _g_wTraceDataNum
- 0x1012daa0 0x40 _g_awPrintMsgProcRpt
- 0x1012dae0 0x2 _g_tEngMissPacket
- 0x1012dae2 0x200 _g_awEngTempBuffer
- COMMON 0x1012dce2 0x1f T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_tpu.o)
+ 0x1012da92 0x1f _g_awMsgTypeRpt
+ 0x1012dab1 0x1 _g_wTraceDataNum
+ 0x1012dab2 0x40 _g_awPrintMsgProcRpt
+ 0x1012daf2 0x2 _g_tEngMissPacket
+ 0x1012daf4 0x200 _g_awEngTempBuffer
+ COMMON 0x1012dcf4 0x1f T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_tpu.o)
0x0 (size before relaxing)
- 0x1012dce2 0x18 _adwTaskID
- 0x1012dcfa 0x7 _g_tTpuFrmEventInfo
- COMMON 0x1012dd01 0x635 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(L1_dev_rfc_db.o)
+ 0x1012dcf4 0x18 _adwTaskID
+ 0x1012dd0c 0x7 _g_tTpuFrmEventInfo
+ COMMON 0x1012dd13 0x635 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(L1_dev_rfc_db.o)
0x0 (size before relaxing)
- 0x1012dd01 0x34 _g_tRfcLogDb
- 0x1012dd35 0x4bf _g_atRfcAgcInfo
- 0x1012e1f4 0x141 _g_tRfcCtrlDb
- 0x1012e335 0x1 _g_wRefFreq
- COMMON 0x1012e336 0x40 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_meas.o)
+ 0x1012dd13 0x34 _g_tRfcLogDb
+ 0x1012dd47 0x4bf _g_atRfcAgcInfo
+ 0x1012e206 0x141 _g_tRfcCtrlDb
+ 0x1012e347 0x1 _g_wRefFreq
+ COMMON 0x1012e348 0x40 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_meas.o)
0x0 (size before relaxing)
- 0x1012e336 0x3f _g_tDevMeasinfoDB
- 0x1012e375 0x1 _G_wDcTuncMode
- COMMON 0x1012e376 0x179 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hsupa.o)
+ 0x1012e348 0x3f _g_tDevMeasinfoDB
+ 0x1012e387 0x1 _G_wDcTuncMode
+ COMMON 0x1012e388 0x179 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hsupa.o)
0x0 (size before relaxing)
- 0x1012e376 0x30 _g_atHsupaEhichInfTab
- 0x1012e3a6 0x35 _g_tUpaErucchDebugInfo
- 0x1012e3db 0x8 _g_abHsupaEpuchDataReadyFlag
- 0x1012e3e3 0x40 _g_tUpaUlDebugInfo
- 0x1012e423 0x89 _g_tDevHsupaPcInfo
- 0x1012e4ac 0x40 _g_tUpaDlDebugInfo
- 0x1012e4ec 0x3 _g_tHsupaDmaInfo
- COMMON 0x1012e4ef 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_sleep.o)
+ 0x1012e388 0x30 _g_atHsupaEhichInfTab
+ 0x1012e3b8 0x35 _g_tUpaErucchDebugInfo
+ 0x1012e3ed 0x8 _g_abHsupaEpuchDataReadyFlag
+ 0x1012e3f5 0x40 _g_tUpaUlDebugInfo
+ 0x1012e435 0x89 _g_tDevHsupaPcInfo
+ 0x1012e4be 0x40 _g_tUpaDlDebugInfo
+ 0x1012e4fe 0x3 _g_tHsupaDmaInfo
+ COMMON 0x1012e501 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_sleep.o)
0x0 (size before relaxing)
- 0x1012e4ef 0x1 _g_wDwFingerValue
- COMMON 0x1012e4f0 0x411 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_afc.o)
+ 0x1012e501 0x1 _g_wDwFingerValue
+ COMMON 0x1012e502 0x411 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_afc.o)
0x0 (size before relaxing)
- 0x1012e4f0 0x4 _g_tAfcLockState
- 0x1012e4f4 0x40b _g_tMAFoeVal
- 0x1012e8ff 0x2 _g_tFoeResult
- COMMON 0x1012e901 0x10e8 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_db.o)
+ 0x1012e502 0x4 _g_tAfcLockState
+ 0x1012e506 0x40b _g_tMAFoeVal
+ 0x1012e911 0x2 _g_tFoeResult
+ COMMON 0x1012e913 0x10e8 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_db.o)
0x0 (size before relaxing)
- 0x1012e901 0xc0 _g_tDevDbHsupaCfgReqBTd
- 0x1012e9c1 0x286 _g_tDevDbDlDchTrchCfgReqA
- 0x1012ec47 0x52 _g_tDevDbDlDpchCfgReqA
- 0x1012ec99 0x196 _g_tDevDbHsdpaCfgReqB
- 0x1012ee2f 0xb4 _g_tDevDbRaRuchProcReq
- 0x1012eee3 0x26c _g_tUlDataBuf
- 0x1012f14f 0x19c _g_tDevDbUlDchTrchCfgReqA
- 0x1012f2eb 0xc0 _g_tDevDbHsupaCfgReqATd
- 0x1012f3ab 0xd8 _g_tDevDbHspaPlusFachCfgReq
- 0x1012f483 0x2ee _g_tDevDbPagingSccpchCfgReq
- 0x1012f771 0x196 _g_tDevDbHsdpaCfgReqA
- 0x1012f907 0x80 _g_tDevDbHspaPlusPchCfgReq
- 0x1012f987 0x62 _g_tDevDbUlDpchCfgReqA
- COMMON 0x1012f9e9 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_sleep.o)
+ 0x1012e913 0xc0 _g_tDevDbHsupaCfgReqBTd
+ 0x1012e9d3 0x286 _g_tDevDbDlDchTrchCfgReqA
+ 0x1012ec59 0x52 _g_tDevDbDlDpchCfgReqA
+ 0x1012ecab 0x196 _g_tDevDbHsdpaCfgReqB
+ 0x1012ee41 0xb4 _g_tDevDbRaRuchProcReq
+ 0x1012eef5 0x26c _g_tUlDataBuf
+ 0x1012f161 0x19c _g_tDevDbUlDchTrchCfgReqA
+ 0x1012f2fd 0xc0 _g_tDevDbHsupaCfgReqATd
+ 0x1012f3bd 0xd8 _g_tDevDbHspaPlusFachCfgReq
+ 0x1012f495 0x2ee _g_tDevDbPagingSccpchCfgReq
+ 0x1012f783 0x196 _g_tDevDbHsdpaCfgReqA
+ 0x1012f919 0x80 _g_tDevDbHspaPlusPchCfgReq
+ 0x1012f999 0x62 _g_tDevDbUlDpchCfgReqA
+ COMMON 0x1012f9fb 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_sleep.o)
0x0 (size before relaxing)
- 0x1012f9e9 0x1 _g_wTdComIntInfo
- COMMON 0x1012f9ea 0xc8 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_csr.o)
+ 0x1012f9fb 0x1 _g_wTdComIntInfo
+ COMMON 0x1012f9fc 0xc8 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_csr.o)
0x0 (size before relaxing)
- 0x1012f9ea 0xc8 _g_awCsrStepPower
- COMMON 0x1012fab2 0x3 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rfc.o)
+ 0x1012f9fc 0xc8 _g_awCsrStepPower
+ COMMON 0x1012fac4 0x3 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rfc.o)
0x0 (size before relaxing)
- 0x1012fab2 0x1 _g_wUpCfgPattern
- 0x1012fab3 0x2 _g_tTadvEvntAdjFlag
- COMMON 0x1012fab5 0x10 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_tpu.o)
+ 0x1012fac4 0x1 _g_wUpCfgPattern
+ 0x1012fac5 0x2 _g_tTadvEvntAdjFlag
+ COMMON 0x1012fac7 0x10 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_tpu.o)
0x0 (size before relaxing)
- 0x1012fab5 0x1 _g_wDoff
- 0x1012fab6 0xf _g_tSleepTpuReg
- COMMON 0x1012fac5 0x10 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_meas.o)
+ 0x1012fac7 0x1 _g_wDoff
+ 0x1012fac8 0xf _g_tSleepTpuReg
+ COMMON 0x1012fad7 0x10 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_meas.o)
0x0 (size before relaxing)
- 0x1012fac5 0x10 _g_adRscpSave
- COMMON 0x1012fad5 0xe T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_dpram.o)
+ 0x1012fad7 0x10 _g_adRscpSave
+ COMMON 0x1012fae7 0xe T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_dpram.o)
0x0 (size before relaxing)
- 0x1012fad5 0xe _g_tDrvDpramStruct
- COMMON 0x1012fae3 0x40 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rx.o)
+ 0x1012fae7 0xe _g_tDrvDpramStruct
+ COMMON 0x1012faf5 0x40 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rx.o)
0x0 (size before relaxing)
- 0x1012fae3 0x40 _g_awSaveRegRxInfo
- COMMON 0x1012fb23 0x4 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_dtr.o)
+ 0x1012faf5 0x40 _g_awSaveRegRxInfo
+ COMMON 0x1012fb35 0x4 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_dtr.o)
0x0 (size before relaxing)
- 0x1012fb23 0x2 _g_ptRxDrvDtrPara
- 0x1012fb25 0x2 _g_ptRxDtrRamData
- COMMON 0x1012fb27 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rfc_zx220a1.o)
+ 0x1012fb35 0x2 _g_ptRxDrvDtrPara
+ 0x1012fb37 0x2 _g_ptRxDtrRamData
+ COMMON 0x1012fb39 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_rfc_zx220a1.o)
0x0 (size before relaxing)
- 0x1012fb27 0x1 _g_wSlotTs0Freq
- COMMON 0x1012fb28 0x14 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_top.o)
+ 0x1012fb39 0x1 _g_wSlotTs0Freq
+ COMMON 0x1012fb3a 0x14 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_drv_top.o)
0x0 (size before relaxing)
- 0x1012fb28 0x14 _g_tSaveTdTopReg
- COMMON 0x1012fb3c 0xbb2 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_meas_db.o)
+ 0x1012fb3a 0x14 _g_tSaveTdTopReg
+ COMMON 0x1012fb4e 0xbb2 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_meas_db.o)
0x0 (size before relaxing)
- 0x1012fb3c 0x1b _g_tScellInfo
- 0x1012fb57 0xb97 _g_tL1MeasDb
- COMMON 0x101306ee 0x4b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_db.o)
+ 0x1012fb4e 0x1b _g_tScellInfo
+ 0x1012fb69 0xb97 _g_tL1MeasDb
+ COMMON 0x10130700 0x4b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_db.o)
0x0 (size before relaxing)
- 0x101306ee 0x1 _bBchRelFlag
- 0x101306ef 0xc _g_tL1CtrlDb
- 0x101306fb 0x3e _g_tL1ProcSetDb
- COMMON 0x10130739 0x11 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_meas.o)
+ 0x10130700 0x1 _bBchRelFlag
+ 0x10130701 0xc _g_tL1CtrlDb
+ 0x1013070d 0x3e _g_tL1ProcSetDb
+ COMMON 0x1013074b 0x11 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_meas.o)
0x0 (size before relaxing)
- 0x10130739 0x11 _g_tMaxRscpMid
- COMMON 0x1013074a 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_amt.o)
+ 0x1013074b 0x11 _g_tMaxRscpMid
+ COMMON 0x1013075c 0x1 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_amt.o)
0x0 (size before relaxing)
- 0x1013074a 0x1 _g_wNvPacketNumId
- COMMON 0x1013074b 0x58a T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_hspa.o)
+ 0x1013075c 0x1 _g_wNvPacketNumId
+ COMMON 0x1013075d 0x58a T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_hspa.o)
0x0 (size before relaxing)
- 0x1013074b 0x1 _g_wNonSchPattern2ndL
- 0x1013074c 0x1 _g_wNonSchPattern1stH
- 0x1013074d 0x2b9 _g_tL1sHsdpaProcInfo
- 0x10130a06 0x1 _g_wNonSchPattern2ndH
- 0x10130a07 0x1 _g_wHsdpaResPattern
- 0x10130a08 0x1 _g_wNonSchPattern1stL
- 0x10130a09 0x2cb _g_tL1sHsupaProcInfo
- 0x10130cd4 0x1 _g_wHsupaResPattern
- COMMON 0x10130cd5 0x79 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_gap.o)
+ 0x1013075d 0x1 _g_wNonSchPattern2ndL
+ 0x1013075e 0x1 _g_wNonSchPattern1stH
+ 0x1013075f 0x2b9 _g_tL1sHsdpaProcInfo
+ 0x10130a18 0x1 _g_wNonSchPattern2ndH
+ 0x10130a19 0x1 _g_wHsdpaResPattern
+ 0x10130a1a 0x1 _g_wNonSchPattern1stL
+ 0x10130a1b 0x2cb _g_tL1sHsupaProcInfo
+ 0x10130ce6 0x1 _g_wHsupaResPattern
+ COMMON 0x10130ce7 0x79 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_sched_proc_gap.o)
0x0 (size before relaxing)
- 0x10130cd5 0x3b _g_s_tMeasGapResReq
- 0x10130d10 0x32 _g_s_tMeasGapConfigReq
- 0x10130d42 0x2 _GAP_SLEEP_RF
- 0x10130d44 0x2 _USE_RDB_LEN
- 0x10130d46 0x8 _g_tL1sGapProcInnerInfo
- COMMON 0x10130d4e 0x18 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_td_dbg.o)
+ 0x10130ce7 0x3b _g_s_tMeasGapResReq
+ 0x10130d22 0x32 _g_s_tMeasGapConfigReq
+ 0x10130d54 0x2 _GAP_SLEEP_RF
+ 0x10130d56 0x2 _USE_RDB_LEN
+ 0x10130d58 0x8 _g_tL1sGapProcInnerInfo
+ COMMON 0x10130d60 0x18 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_td_dbg.o)
0x0 (size before relaxing)
- 0x10130d4e 0x18 _g_tCallStackInfo
- COMMON 0x10130d66 0x18b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_dst.o)
+ 0x10130d60 0x18 _g_tCallStackInfo
+ COMMON 0x10130d78 0x18b T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_dls_dst.o)
0x0 (size before relaxing)
- 0x10130d66 0x107 _g_tL1DevDstDb
- 0x10130e6d 0x80 _g_awAVPDP
- 0x10130eed 0x2 _g_tL1sTs0McheInfo
- 0x10130eef 0x1 _g_wMcheSfnCnt
- 0x10130ef0 0x1 _g_wMcheIntCnt
- COMMON 0x10130ef1 0xc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ 0x10130d78 0x107 _g_tL1DevDstDb
+ 0x10130e7f 0x80 _g_awAVPDP
+ 0x10130eff 0x2 _g_tL1sTs0McheInfo
+ 0x10130f01 0x1 _g_wMcheSfnCnt
+ 0x10130f02 0x1 _g_wMcheIntCnt
+ COMMON 0x10130f03 0xc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
0x0 (size before relaxing)
- 0x10130ef1 0x9 _g_L1wPriTaskPid
- 0x10130efa 0x3 _g_L1wIsrTaskPid
- COMMON 0x10130efd 0xc9e6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ 0x10130f03 0x9 _g_L1wPriTaskPid
+ 0x10130f0c 0x3 _g_L1wIsrTaskPid
+ COMMON 0x10130f0f 0xc9e6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
0x0 (size before relaxing)
- 0x10130efd 0xbec _g_tWcdmaUserNv
- 0x10131ae9 0x22c _g_tL1wNvBb
- 0x10131d15 0xbbca _g_tWcdmaCalibNv
- 0x1013d8df 0x4 _g_tL1wAtNv
- COMMON 0x1013d8e3 0x427 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ 0x10130f0f 0xbec _g_tWcdmaUserNv
+ 0x10131afb 0x22c _g_tL1wNvBb
+ 0x10131d27 0xbbca _g_tWcdmaCalibNv
+ 0x1013d8f1 0x4 _g_tL1wAtNv
+ COMMON 0x1013d8f5 0x427 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
0x0 (size before relaxing)
- 0x1013d8e3 0x3eb _g_tL1wDevMeasInfo
- 0x1013dcce 0x3c _g_atMeasSpsrInfo
- COMMON 0x1013dd0a 0x5b3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ 0x1013d8f5 0x3eb _g_tL1wDevMeasInfo
+ 0x1013dce0 0x3c _g_atMeasSpsrInfo
+ COMMON 0x1013dd1c 0x5b3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
0x0 (size before relaxing)
- 0x1013dd0a 0x4e4 _s_tL1wDevHsupaInfo
- 0x1013e1ee 0xcf _g_PsrUpdateReq
- COMMON 0x1013e2bd 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ 0x1013dd1c 0x4e4 _s_tL1wDevHsupaInfo
+ 0x1013e200 0xcf _g_PsrUpdateReq
+ COMMON 0x1013e2cf 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
0x0 (size before relaxing)
- 0x1013e2bd 0x1 _g_SSC_CFLT_chip
- 0x1013e2be 0x14 _g_tRfcNotchInfo
- 0x1013e2d2 0x24 _g_tWRfcRpiPwrCtl
- 0x1013e2f6 0x1 _g_wRfcResetState
- 0x1013e2f7 0x1 _g_SSC_CFLT_ssfn
- 0x1013e2f8 0x2 _g_zPHYRfcSSCDebugCnt
- COMMON 0x1013e2fa 0x13e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ 0x1013e2cf 0x1 _g_SSC_CFLT_chip
+ 0x1013e2d0 0x14 _g_tRfcNotchInfo
+ 0x1013e2e4 0x24 _g_tWRfcRpiPwrCtl
+ 0x1013e308 0x1 _g_wRfcResetState
+ 0x1013e309 0x1 _g_SSC_CFLT_ssfn
+ 0x1013e30a 0x2 _g_zPHYRfcSSCDebugCnt
+ COMMON 0x1013e30c 0x13e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
0x0 (size before relaxing)
- 0x1013e2fa 0x48 _tPcDataDb
- 0x1013e342 0x62 _tPcCnt
- 0x1013e3a4 0x94 _g_tPcDpchSirCalInfo
- COMMON 0x1013e438 0x113 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ 0x1013e30c 0x48 _tPcDataDb
+ 0x1013e354 0x62 _tPcCnt
+ 0x1013e3b6 0x94 _g_tPcDpchSirCalInfo
+ COMMON 0x1013e44a 0x113 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
0x0 (size before relaxing)
- 0x1013e438 0x2 _g_Rt
- 0x1013e43a 0x11 _g_tL1wHsdpaSnrAdjInfo
- 0x1013e44b 0x36 _g_tHsdpaAdrIcRstInfo
- 0x1013e481 0x6 _g_tL1wHsdpaDbgInfo
- 0x1013e487 0x78 _g_tL1wHsdpaPacketInfo
- 0x1013e4ff 0x19 _g_tHsdpaIcFingerDiffInfo
- 0x1013e518 0x1 _g_wAdrIcEn
- 0x1013e519 0x26 _g_tL1wHsdpaCodingInfo
- 0x1013e53f 0x1 _g_wL1wHsdpaRxDivMode
- 0x1013e540 0xb _g_tHsdpaResetInfo
- COMMON 0x1013e54b 0x191 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ 0x1013e44a 0x2 _g_Rt
+ 0x1013e44c 0x11 _g_tL1wHsdpaSnrAdjInfo
+ 0x1013e45d 0x36 _g_tHsdpaAdrIcRstInfo
+ 0x1013e493 0x6 _g_tL1wHsdpaDbgInfo
+ 0x1013e499 0x78 _g_tL1wHsdpaPacketInfo
+ 0x1013e511 0x19 _g_tHsdpaIcFingerDiffInfo
+ 0x1013e52a 0x1 _g_wAdrIcEn
+ 0x1013e52b 0x26 _g_tL1wHsdpaCodingInfo
+ 0x1013e551 0x1 _g_wL1wHsdpaRxDivMode
+ 0x1013e552 0xb _g_tHsdpaResetInfo
+ COMMON 0x1013e55d 0x191 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
0x0 (size before relaxing)
- 0x1013e54b 0x168 _g_atLessDecodeCfg
- 0x1013e6b3 0x28 _g_atLessDemoluleCfg
- 0x1013e6db 0x1 _g_wL1wLessCfgIdx
- COMMON 0x1013e6dc 0x1b6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ 0x1013e55d 0x168 _g_atLessDecodeCfg
+ 0x1013e6c5 0x28 _g_atLessDemoluleCfg
+ 0x1013e6ed 0x1 _g_wL1wLessCfgIdx
+ COMMON 0x1013e6ee 0x1b6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
0x0 (size before relaxing)
- 0x1013e6dc 0x1b6 _g_tUlRfTbl
- COMMON 0x1013e892 0x26c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ 0x1013e6ee 0x1b6 _g_tUlRfTbl
+ COMMON 0x1013e8a4 0x26c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
0x0 (size before relaxing)
- 0x1013e892 0x26c _g_tWuldataBuf
- COMMON 0x1013eafe 0x624 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ 0x1013e8a4 0x26c _g_tWuldataBuf
+ COMMON 0x1013eb10 0x624 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
0x0 (size before relaxing)
- 0x1013eafe 0x604 _g_uLSfInfo
- 0x1013f102 0x20 _g_atL1wHsupaFirstTranPara
- COMMON 0x1013f122 0xd06 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ 0x1013eb10 0x604 _g_uLSfInfo
+ 0x1013f114 0x20 _g_atL1wHsupaFirstTranPara
+ COMMON 0x1013f134 0xd06 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
0x0 (size before relaxing)
- 0x1013f122 0x12 _g_tRfcPowerAdcReadInfo
- 0x1013f134 0x5a _g_atRfcAgcDbLog
- 0x1013f18e 0x1 _g_eAntSel
- 0x1013f18f 0x1 _g_bNvCheck
- 0x1013f190 0x1 _g_wRfcTxRxState
- 0x1013f191 0x318 _g_tRfcCtrlDbRx
- 0x1013f4a9 0x26 _g_tRfcGapMixLog
- 0x1013f4cf 0x5df _g_tRfcAgcDb
- 0x1013faae 0x1e _g_atRfcStateLog
- 0x1013facc 0x1 _g_eDivState
- 0x1013facd 0xb _g_tRfcAfcDb
- 0x1013fad8 0x1 _g_eAntState
- 0x1013fad9 0x318 _g_tRfcCtrlDbTx
- 0x1013fdf1 0x23 _g_tRfcCmnInfoLOG
- 0x1013fe14 0xe _g_tRfcTxPowLog
- 0x1013fe22 0x5 _g_tRfcTmpReadInfo
- 0x1013fe27 0x1 _g_eRfcRamState
- COMMON 0x1013fe28 0x1f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ 0x1013f134 0x12 _g_tRfcPowerAdcReadInfo
+ 0x1013f146 0x5a _g_atRfcAgcDbLog
+ 0x1013f1a0 0x1 _g_eAntSel
+ 0x1013f1a1 0x1 _g_bNvCheck
+ 0x1013f1a2 0x1 _g_wRfcTxRxState
+ 0x1013f1a3 0x318 _g_tRfcCtrlDbRx
+ 0x1013f4bb 0x26 _g_tRfcGapMixLog
+ 0x1013f4e1 0x5df _g_tRfcAgcDb
+ 0x1013fac0 0x1e _g_atRfcStateLog
+ 0x1013fade 0x1 _g_eDivState
+ 0x1013fadf 0xb _g_tRfcAfcDb
+ 0x1013faea 0x1 _g_eAntState
+ 0x1013faeb 0x318 _g_tRfcCtrlDbTx
+ 0x1013fe03 0x23 _g_tRfcCmnInfoLOG
+ 0x1013fe26 0xe _g_tRfcTxPowLog
+ 0x1013fe34 0x5 _g_tRfcTmpReadInfo
+ 0x1013fe39 0x1 _g_eRfcRamState
+ COMMON 0x1013fe3a 0x1f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
0x0 (size before relaxing)
- 0x1013fe28 0x4 _g_wAdrIcCellState
- 0x1013fe2c 0x1 _g_wL1wHsdpaSfnCfnSubFrmOffset
- 0x1013fe2d 0x5 _g_awL1wHsdpaMvalue
- 0x1013fe32 0x4 _g_wSubFrmOffset
- 0x1013fe36 0x1 _g_wL1wHsdpaHsdpcchUldpcchOffset
- 0x1013fe37 0xf _g_awL1wHsdpaCfnSlot2SfnSubFrm
- 0x1013fe46 0x1 _g_wL1wHsdpaSfnCfnOffset
- COMMON 0x1013fe47 0x2824 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ 0x1013fe3a 0x4 _g_wAdrIcCellState
+ 0x1013fe3e 0x1 _g_wL1wHsdpaSfnCfnSubFrmOffset
+ 0x1013fe3f 0x5 _g_awL1wHsdpaMvalue
+ 0x1013fe44 0x4 _g_wSubFrmOffset
+ 0x1013fe48 0x1 _g_wL1wHsdpaHsdpcchUldpcchOffset
+ 0x1013fe49 0xf _g_awL1wHsdpaCfnSlot2SfnSubFrm
+ 0x1013fe58 0x1 _g_wL1wHsdpaSfnCfnOffset
+ COMMON 0x1013fe59 0x2824 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
0x0 (size before relaxing)
- 0x1013fe47 0x24 _s_tCsStatisticInfo
- 0x1013fe6b 0x2800 _dwPeakInfoInSlot
- COMMON 0x1014266b 0xc5d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ 0x1013fe59 0x24 _s_tCsStatisticInfo
+ 0x1013fe7d 0x2800 _dwPeakInfoInSlot
+ COMMON 0x1014267d 0xc5d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
0x0 (size before relaxing)
- 0x1014266b 0x26 _g_tPcUphDb
- 0x10142691 0x3e _tDevEngStardardParam
- 0x101426cf 0x559 _g_tPcOverEstDb
- 0x10142c28 0x3e3 _tPcBetaDb
- 0x1014300b 0xa _swPcTimeOff
- 0x10143015 0x1 _wTimeOff
- 0x10143016 0xa _swPcTimeOff2
- 0x10143020 0x95 _tPcCalcDb
- 0x101430b5 0x2 _g_tIqMappingCon
- 0x101430b7 0x146 _tPcInfoDb
- 0x101431fd 0xcb _tMprTest
- COMMON 0x101432c8 0x286 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ 0x1014267d 0x26 _g_tPcUphDb
+ 0x101426a3 0x3e _tDevEngStardardParam
+ 0x101426e1 0x559 _g_tPcOverEstDb
+ 0x10142c3a 0x3e3 _tPcBetaDb
+ 0x1014301d 0xa _swPcTimeOff
+ 0x10143027 0x1 _wTimeOff
+ 0x10143028 0xa _swPcTimeOff2
+ 0x10143032 0x95 _tPcCalcDb
+ 0x101430c7 0x2 _g_tIqMappingCon
+ 0x101430c9 0x146 _tPcInfoDb
+ 0x1014320f 0xcb _tMprTest
+ COMMON 0x101432da 0x286 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
0x0 (size before relaxing)
- 0x101432c8 0x4 _g_awL1wStandardMsgRpt
- 0x101432cc 0x80 _g_awL1wPrintMsgProcRpt
- 0x1014334c 0x2 _gL1w_MissLogInfo
- 0x1014334e 0x200 _g_awL1wEngTempBuffer
- COMMON 0x1014354e 0xb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ 0x101432da 0x4 _g_awL1wStandardMsgRpt
+ 0x101432de 0x80 _g_awL1wPrintMsgProcRpt
+ 0x1014335e 0x2 _gL1w_MissLogInfo
+ 0x10143360 0x200 _g_awL1wEngTempBuffer
+ COMMON 0x10143560 0xb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
0x0 (size before relaxing)
- 0x1014354e 0x5 _g_RxDataPn9Check
- 0x10143553 0x2 _g_dwCfgSsfn
- 0x10143555 0x1 _g_RxTtiNum
- 0x10143556 0x1 _g_RxTfciNum
- 0x10143557 0x2 _g_dwTtiSsfn
- COMMON 0x10143559 0x11c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ 0x10143560 0x5 _g_RxDataPn9Check
+ 0x10143565 0x2 _g_dwCfgSsfn
+ 0x10143567 0x1 _g_RxTtiNum
+ 0x10143568 0x1 _g_RxTfciNum
+ 0x10143569 0x2 _g_dwTtiSsfn
+ COMMON 0x1014356b 0x11c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
0x0 (size before relaxing)
- 0x10143559 0xe _g_tWUpaStdlogStatisitcInfo
- 0x10143567 0x2 _g_EdchNewTbTotal
- 0x10143569 0x20 _g_atWHsupaEhichInfTab
- 0x10143589 0x1 _g_EagchCnt500Ms
- 0x1014358a 0x38 _g_tWUpaStdlogPacketInfo
- 0x101435c2 0x2 _g_EdchTbTotal
- 0x101435c4 0x10 _g_atWHsupaEdchReadyFlag
- 0x101435d4 0x36 _g_tWUpaUlDebugInfo
- 0x1014360a 0x6b _g_tWUpaDlDebugInfo
- COMMON 0x10143675 0x11b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ 0x1014356b 0xe _g_tWUpaStdlogStatisitcInfo
+ 0x10143579 0x2 _g_EdchNewTbTotal
+ 0x1014357b 0x20 _g_atWHsupaEhichInfTab
+ 0x1014359b 0x1 _g_EagchCnt500Ms
+ 0x1014359c 0x38 _g_tWUpaStdlogPacketInfo
+ 0x101435d4 0x2 _g_EdchTbTotal
+ 0x101435d6 0x10 _g_atWHsupaEdchReadyFlag
+ 0x101435e6 0x36 _g_tWUpaUlDebugInfo
+ 0x1014361c 0x6b _g_tWUpaDlDebugInfo
+ COMMON 0x10143687 0x11b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
0x0 (size before relaxing)
- 0x10143675 0xc _g_atL1wCellType
- 0x10143681 0x2f _g_tL1wMeasCellReq
- 0x101436b0 0x24 _g_atL1wRlsTrace
- 0x101436d4 0x8 _g_tL1wFmoDlsPsrParaConfig
- 0x101436dc 0x2 _g_tL1wPsrAntNumPara
- 0x101436de 0x2 _g_dIntIndex
- 0x101436e0 0xe _g_tL1wCmPsrPatternInfo
- 0x101436ee 0x1 _g_wL1wDpchOffset
- 0x101436ef 0x2f _g_tL1wDchDlsLastReq
- 0x1014371e 0x2f _g_tL1wDchDlsPsrReq
- 0x1014374d 0x6 _g_asL1wAdujstFlag
- 0x10143753 0x4 _g_tL1wHsupaRlToPsr
- 0x10143757 0x7 _g_tL1wFachDlsPsrReq
- 0x1014375e 0x1 _g_sL1wUlAdujstFlag
- 0x1014375f 0x2 _g_dOldUlTiming
- 0x10143761 0x2f _g_tL1wDpaRlReqInfo
- COMMON 0x10143790 0xec T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x10143687 0xc _g_atL1wCellType
+ 0x10143693 0x2f _g_tL1wMeasCellReq
+ 0x101436c2 0x24 _g_atL1wRlsTrace
+ 0x101436e6 0x8 _g_tL1wFmoDlsPsrParaConfig
+ 0x101436ee 0x2 _g_tL1wPsrAntNumPara
+ 0x101436f0 0x2 _g_dIntIndex
+ 0x101436f2 0xe _g_tL1wCmPsrPatternInfo
+ 0x10143700 0x1 _g_wL1wDpchOffset
+ 0x10143701 0x2f _g_tL1wDchDlsLastReq
+ 0x10143730 0x2f _g_tL1wDchDlsPsrReq
+ 0x1014375f 0x6 _g_asL1wAdujstFlag
+ 0x10143765 0x4 _g_tL1wHsupaRlToPsr
+ 0x10143769 0x7 _g_tL1wFachDlsPsrReq
+ 0x10143770 0x1 _g_sL1wUlAdujstFlag
+ 0x10143771 0x2 _g_dOldUlTiming
+ 0x10143773 0x2f _g_tL1wDpaRlReqInfo
+ COMMON 0x101437a2 0xec T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
0x0 (size before relaxing)
- 0x10143790 0xe8 _g_tResInfo
- 0x10143878 0x4 _g_tSendIcpTpuTime
- COMMON 0x1014387c 0x163 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ 0x101437a2 0xe8 _g_tResInfo
+ 0x1014388a 0x4 _g_tSendIcpTpuTime
+ COMMON 0x1014388e 0x163 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
0x0 (size before relaxing)
- 0x1014387c 0x106 _g_tL1wAfcFreqOffsetValue
- 0x10143982 0x30 _g_atL1wRxHistoryIQBuffer
- 0x101439b2 0x3 _g_tAfcErrorPrint
- 0x101439b5 0x20 _g_tL1wAfcWorkPara
- 0x101439d5 0x6 _g_tL1wSlaveAfcWorkPara
- 0x101439db 0x4 _g_tL1wBchDataHistoryIQValue
- COMMON 0x101439df 0xe47 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ 0x1014388e 0x106 _g_tL1wAfcFreqOffsetValue
+ 0x10143994 0x30 _g_atL1wRxHistoryIQBuffer
+ 0x101439c4 0x3 _g_tAfcErrorPrint
+ 0x101439c7 0x20 _g_tL1wAfcWorkPara
+ 0x101439e7 0x6 _g_tL1wSlaveAfcWorkPara
+ 0x101439ed 0x4 _g_tL1wBchDataHistoryIQValue
+ COMMON 0x101439f1 0xe47 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
0x0 (size before relaxing)
- 0x101439df 0x1a _g_adL1wTpuTaskID
- 0x101439f9 0x235 _g_atL1wTpuRegRtVarEventInfo
- 0x10143c2e 0x4db _g_atL1wTpuRegNtVarEventInfo
- 0x10144109 0x4 _g_tL1wTpuLastMicroAdjustInfo
- 0x1014410d 0x1 _g_wL1wTpuDoffVal
- 0x1014410e 0x8 _g_tL1wTpuFrmInfo
- 0x10144116 0x710 _g_atL1wTpuRegNtFixedEventInfo
- *fill* 0x10144826 0x80000002 00
- COMMON 0x10144828 0x427f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ 0x101439f1 0x1a _g_adL1wTpuTaskID
+ 0x10143a0b 0x235 _g_atL1wTpuRegRtVarEventInfo
+ 0x10143c40 0x4db _g_atL1wTpuRegNtVarEventInfo
+ 0x1014411b 0x4 _g_tL1wTpuLastMicroAdjustInfo
+ 0x1014411f 0x1 _g_wL1wTpuDoffVal
+ 0x10144120 0x8 _g_tL1wTpuFrmInfo
+ 0x10144128 0x710 _g_atL1wTpuRegNtFixedEventInfo
+ COMMON 0x10144838 0x427f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
0x0 (size before relaxing)
- 0x10144828 0x7c _g_tL1wDevDbHsdpaCfgReqB
- 0x101448a4 0x7a _g_atDevBchAfcdb
- 0x1014491e 0x3d6 _g_tL1wDevDbUlDpchCfgReqA
- 0x10144cf4 0x7c _g_tL1wDevDbHsdpaCfgReqA
- 0x10144d70 0x41c _g_tL1wDevDbRtxIscpInfo
- 0x1014518c 0x4 _g_tL1wDevDbRaMacProcReq
- 0x10145190 0x7e _g_tL1wDevDbDlFdpchCfgReqA
- 0x1014520e 0xf8 _g_tDevDbHsupaCfgReqB
- 0x10145306 0x382 _g_tL1wDevDbPageFachCfgReq
- 0x10145688 0x2 _g_tL1wDevDbTrchTtiInfo
- 0x1014568a 0xf8 _g_tDevDbHsupaCfgReqA
- 0x10145782 0x39a _g_tL1wDevDbRaEraRrcReq
- 0x10145b1c 0x5 _g_tL1wDevDbHsdpaInd
- 0x10145b21 0x880 _g_tDevDbHsdpaFingMaskBuffer
- 0x101463a1 0x27 _g_tDevDbHspaToMacInfo
- 0x101463c8 0x200 _g_tDevDbHsdpaAdrCirData
- 0x101465c8 0x1a70 _g_tL1wDevDbRtxAfcInfo
- 0x10148038 0xb _g_tDevDbHsdpaAntSwitch
- 0x10148043 0x62 _g_tL1wDevDbHsdpaPlusPchCfgReq
- 0x101480a5 0x4be _g_tL1wDevDbDlDpchCfgReqA
- 0x10148563 0x544 _g_tWDevDbHspaPlusFachCfgReq
- COMMON 0x10148aa7 0x85 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ 0x10144838 0x7c _g_tL1wDevDbHsdpaCfgReqB
+ 0x101448b4 0x7a _g_atDevBchAfcdb
+ 0x1014492e 0x3d6 _g_tL1wDevDbUlDpchCfgReqA
+ 0x10144d04 0x7c _g_tL1wDevDbHsdpaCfgReqA
+ 0x10144d80 0x41c _g_tL1wDevDbRtxIscpInfo
+ 0x1014519c 0x4 _g_tL1wDevDbRaMacProcReq
+ 0x101451a0 0x7e _g_tL1wDevDbDlFdpchCfgReqA
+ 0x1014521e 0xf8 _g_tDevDbHsupaCfgReqB
+ 0x10145316 0x382 _g_tL1wDevDbPageFachCfgReq
+ 0x10145698 0x2 _g_tL1wDevDbTrchTtiInfo
+ 0x1014569a 0xf8 _g_tDevDbHsupaCfgReqA
+ 0x10145792 0x39a _g_tL1wDevDbRaEraRrcReq
+ 0x10145b2c 0x5 _g_tL1wDevDbHsdpaInd
+ 0x10145b31 0x880 _g_tDevDbHsdpaFingMaskBuffer
+ 0x101463b1 0x27 _g_tDevDbHspaToMacInfo
+ 0x101463d8 0x200 _g_tDevDbHsdpaAdrCirData
+ 0x101465d8 0x1a70 _g_tL1wDevDbRtxAfcInfo
+ 0x10148048 0xb _g_tDevDbHsdpaAntSwitch
+ 0x10148053 0x62 _g_tL1wDevDbHsdpaPlusPchCfgReq
+ 0x101480b5 0x4be _g_tL1wDevDbDlDpchCfgReqA
+ 0x10148573 0x544 _g_tWDevDbHspaPlusFachCfgReq
+ COMMON 0x10148ab7 0x85 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
0x0 (size before relaxing)
- 0x10148aa7 0x3b _g_tRxEng
- 0x10148ae2 0x4a _g_tDlCpchEng
- COMMON 0x10148b2c 0x86 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ 0x10148ab7 0x3b _g_tRxEng
+ 0x10148af2 0x4a _g_tDlCpchEng
+ COMMON 0x10148b3c 0x86 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
0x0 (size before relaxing)
- 0x10148b2c 0x4 _g_tRfcIQInfo
- 0x10148b30 0x2 _g_sdAnt0CarrierPhase
- 0x10148b32 0x78 _g_atRfcDcLog
- 0x10148baa 0x2 _g_sdAnt1CarrierPhase
- 0x10148bac 0x4 _g_tRfcDcInfo
- 0x10148bb0 0x2 _g_tRfcDagcGain
- COMMON 0x10148bb2 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ 0x10148b3c 0x4 _g_tRfcIQInfo
+ 0x10148b40 0x2 _g_sdAnt0CarrierPhase
+ 0x10148b42 0x78 _g_atRfcDcLog
+ 0x10148bba 0x2 _g_sdAnt1CarrierPhase
+ 0x10148bbc 0x4 _g_tRfcDcInfo
+ 0x10148bc0 0x2 _g_tRfcDagcGain
+ COMMON 0x10148bc2 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
0x0 (size before relaxing)
- 0x10148bb2 0x38 _g_TopRegLpcSave
- COMMON 0x10148bea 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ 0x10148bc2 0x38 _g_TopRegLpcSave
+ COMMON 0x10148bfa 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
0x0 (size before relaxing)
- 0x10148bea 0xa _g_wTpuRtRegLpcSave
- 0x10148bf4 0x36 _g_wTpuNtRegLpcSave
- COMMON 0x10148c2a 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ 0x10148bfa 0xa _g_wTpuRtRegLpcSave
+ 0x10148c04 0x36 _g_wTpuNtRegLpcSave
+ COMMON 0x10148c3a 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
0x0 (size before relaxing)
- 0x10148c2a 0xd0 _g_atL1wDrvMeasResultInfo
- COMMON 0x10148cfa 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ 0x10148c3a 0xd0 _g_atL1wDrvMeasResultInfo
+ COMMON 0x10148d0a 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
0x0 (size before relaxing)
- 0x10148cfa 0x2 _g_dL1wDprICPSSFN
- 0x10148cfc 0x1 _g_wLastSubframe
- 0x10148cfd 0x1 _g_wL1wDprModState
- 0x10148cfe 0x26 _g_tL1wDrvDpramStruct
- 0x10148d24 0x2 _g_dL1wDprResetCnfSSFN
- 0x10148d26 0x2 _g_wL1wDprSubFrmCnt
- 0x10148d28 0xa _g_awReportCFN
- COMMON 0x10148d32 0x808 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ 0x10148d0a 0x2 _g_dL1wDprICPSSFN
+ 0x10148d0c 0x1 _g_wLastSubframe
+ 0x10148d0d 0x1 _g_wL1wDprModState
+ 0x10148d0e 0x26 _g_tL1wDrvDpramStruct
+ 0x10148d34 0x2 _g_dL1wDprResetCnfSSFN
+ 0x10148d36 0x2 _g_wL1wDprSubFrmCnt
+ 0x10148d38 0xa _g_awReportCFN
+ COMMON 0x10148d42 0x808 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
0x0 (size before relaxing)
- 0x10148d32 0x808 _s_tDrvRxCfg
- COMMON 0x1014953a 0x7b8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x10148d42 0x808 _s_tDrvRxCfg
+ COMMON 0x1014954a 0x7b8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
0x0 (size before relaxing)
- 0x1014953a 0x7b8 _g_tRegRxRakeReg
- COMMON 0x10149cf2 0x7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ 0x1014954a 0x7b8 _g_tRegRxRakeReg
+ COMMON 0x10149d02 0x7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
0x0 (size before relaxing)
- 0x10149cf2 0x1 _wLastBand
- 0x10149cf3 0x2 _g_l1wATSetAPCTmpCmpVal
- 0x10149cf5 0x2 _g_l1wATOriAPCTmpCmpVal
- 0x10149cf7 0x2 _g_l1wATSetAPCFlag
- COMMON 0x10149cf9 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ 0x10149d02 0x1 _wLastBand
+ 0x10149d03 0x2 _g_l1wATSetAPCTmpCmpVal
+ 0x10149d05 0x2 _g_l1wATOriAPCTmpCmpVal
+ 0x10149d07 0x2 _g_l1wATSetAPCFlag
+ COMMON 0x10149d09 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
0x0 (size before relaxing)
- 0x10149cf9 0x1 _g_TxCfgOver
- 0x10149cfa 0x1 _g_TpuCfgOver
- COMMON 0x10149cfb 0x415 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ 0x10149d09 0x1 _g_TxCfgOver
+ 0x10149d0a 0x1 _g_TpuCfgOver
+ COMMON 0x10149d0b 0x415 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
0x0 (size before relaxing)
- 0x10149cfb 0x3a _g_tRfcDrvOpen
- 0x10149d35 0x1 _g_wRfOpCnt
- 0x10149d36 0x3a _g_atLastRfcOpen
- 0x10149d70 0x3a0 _g_atRfcOpen
- COMMON 0x1014a110 0xa3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o)
+ 0x10149d0b 0x3a _g_tRfcDrvOpen
+ 0x10149d45 0x1 _g_wRfOpCnt
+ 0x10149d46 0x3a _g_atLastRfcOpen
+ 0x10149d80 0x3a0 _g_atRfcOpen
+ COMMON 0x1014a120 0xa3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o)
0x0 (size before relaxing)
- 0x1014a110 0xa3 _g_tL1wInnerCellDb
- COMMON 0x1014a1b3 0x8f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ 0x1014a120 0xa3 _g_tL1wInnerCellDb
+ COMMON 0x1014a1c3 0x8f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
0x0 (size before relaxing)
- 0x1014a1b3 0x19 _g_tL1wCtrlDb
- 0x1014a1cc 0x1c _g_tL1MainMixInfo
- 0x1014a1e8 0x1 _g_eL1wAmtL1sStateInfo
- 0x1014a1e9 0x1a _g_tL1wStateCnt
- 0x1014a203 0x3f _g_tL1wProcSetDb
- COMMON 0x1014a242 0xf4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
+ 0x1014a1c3 0x19 _g_tL1wCtrlDb
+ 0x1014a1dc 0x1c _g_tL1MainMixInfo
+ 0x1014a1f8 0x1 _g_eL1wAmtL1sStateInfo
+ 0x1014a1f9 0x1a _g_tL1wStateCnt
+ 0x1014a213 0x3f _g_tL1wProcSetDb
+ COMMON 0x1014a252 0xf4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
0x0 (size before relaxing)
- 0x1014a242 0x1 _g_wBackupCellMainIdx
- 0x1014a243 0x79 _g_tServCellDb
- 0x1014a2bc 0x60 _g_atBackupCellInfo
- 0x1014a31c 0x1a _g_tL1wAddionCtrl
- COMMON 0x1014a336 0xa1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa.o)
+ 0x1014a252 0x1 _g_wBackupCellMainIdx
+ 0x1014a253 0x79 _g_tServCellDb
+ 0x1014a2cc 0x60 _g_atBackupCellInfo
+ 0x1014a32c 0x1a _g_tL1wAddionCtrl
+ COMMON 0x1014a346 0xa1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa.o)
0x0 (size before relaxing)
- 0x1014a336 0xa1 _g_tWL1sHsupaProcInfo
- COMMON 0x1014a3d7 0x350 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+ 0x1014a346 0xa1 _g_tWL1sHsupaProcInfo
+ COMMON 0x1014a3e7 0x350 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
0x0 (size before relaxing)
- 0x1014a3d7 0x5a _g_tL1wCmCfnN0123Bitmap
- 0x1014a431 0x78 _g_atL1wCmWaitCfgPatternDB
- 0x1014a4a9 0x5a _g_tL1wCmCfnN0123BitmapTemp
- 0x1014a503 0xdc _g_tL1wCmInnerInfo
- 0x1014a5df 0xca _g_tL1wCmInfoForN4N9
- 0x1014a6a9 0x7e _g_tL1wPsCmConfigBuffer
- COMMON 0x1014a727 0x339 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+ 0x1014a3e7 0x5a _g_tL1wCmCfnN0123Bitmap
+ 0x1014a441 0x78 _g_atL1wCmWaitCfgPatternDB
+ 0x1014a4b9 0x5a _g_tL1wCmCfnN0123BitmapTemp
+ 0x1014a513 0xdc _g_tL1wCmInnerInfo
+ 0x1014a5ef 0xca _g_tL1wCmInfoForN4N9
+ 0x1014a6b9 0x7e _g_tL1wPsCmConfigBuffer
+ COMMON 0x1014a737 0x339 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
0x0 (size before relaxing)
- 0x1014a727 0xa0 _g_atL1RfSegInfo
- 0x1014a7c7 0x4 _g_tTimerCnt
- 0x1014a7cb 0x2 _g_tL1wResCtrl
- 0x1014a7cd 0x28f _g_tL1wRfTbl
- 0x1014aa5c 0x3 _g_tL1wResAgcCtrl
- 0x1014aa5f 0x1 _g_wRfSegNum
- COMMON 0x1014aa60 0x33 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
+ 0x1014a737 0xa0 _g_atL1RfSegInfo
+ 0x1014a7d7 0x4 _g_tTimerCnt
+ 0x1014a7db 0x2 _g_tL1wResCtrl
+ 0x1014a7dd 0x28f _g_tL1wRfTbl
+ 0x1014aa6c 0x3 _g_tL1wResAgcCtrl
+ 0x1014aa6f 0x1 _g_wRfSegNum
+ COMMON 0x1014aa70 0x33 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
0x0 (size before relaxing)
- 0x1014aa60 0x33 _g_tDchAscPara
- COMMON 0x1014aa93 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ 0x1014aa70 0x33 _g_tDchAscPara
+ COMMON 0x1014aaa3 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
0x0 (size before relaxing)
- 0x1014aa93 0x1 _g_RxRachAiNum
- 0x1014aa94 0x1 _g_RxAichIntCnt
- COMMON 0x1014aa95 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ 0x1014aaa3 0x1 _g_RxRachAiNum
+ 0x1014aaa4 0x1 _g_RxAichIntCnt
+ COMMON 0x1014aaa5 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
0x0 (size before relaxing)
- 0x1014aa95 0x1 _g_wMissHdtrInt
- COMMON 0x1014aa96 0x19 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ 0x1014aaa5 0x1 _g_wMissHdtrInt
+ COMMON 0x1014aaa6 0x19 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
0x0 (size before relaxing)
- 0x1014aa96 0x5 _g_tPcPrachConfigInfo
- 0x1014aa9b 0x1 _g_swPrachSlotPower
- 0x1014aa9c 0x13 _g_tRtxPcPrachMessageInfo
- COMMON 0x1014aaaf 0x18 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ 0x1014aaa6 0x5 _g_tPcPrachConfigInfo
+ 0x1014aaab 0x1 _g_swPrachSlotPower
+ 0x1014aaac 0x13 _g_tRtxPcPrachMessageInfo
+ COMMON 0x1014aabf 0x18 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
0x0 (size before relaxing)
- 0x1014aaaf 0x18 _g_atL1wHsupaDlCmPattern
- COMMON 0x1014aac7 0x1c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x1014aabf 0x18 _g_atL1wHsupaDlCmPattern
+ COMMON 0x1014aad7 0x1d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
0x0 (size before relaxing)
- 0x1014aac7 0x3 _g_L1LteAIsrTaskPid
- 0x1014aaca 0x2 _g_pSemId_INTH1
- 0x1014aacc 0x11 _g_L1LteAPriTaskPid
- 0x1014aadd 0x2 _g_pSemId_ICP
- 0x1014aadf 0x2 _g_pSemId_TXIntPulse
- 0x1014aae1 0x2 _g_pSemId_INTH2
- COMMON 0x1014aae3 0x21f06 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ 0x1014aad7 0x4 _g_L1LteAIsrTaskPid
+ 0x1014aadb 0x2 _g_pSemId_INTH1
+ 0x1014aadd 0x11 _g_L1LteAPriTaskPid
+ 0x1014aaee 0x2 _g_pSemId_ICP
+ 0x1014aaf0 0x2 _g_pSemId_TXIntPulse
+ 0x1014aaf2 0x2 _g_pSemId_INTH2
+ COMMON 0x1014aaf4 0x21f06 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
0x0 (size before relaxing)
- 0x1014aae3 0x8 _g_tUEIdInfo
- 0x1014aaeb 0x1e000 _g_zPHY_AMT_tNVInfo
- 0x10168aeb 0x2540 _g_zPHY_tNVInfo
- 0x1016b02b 0x198c _g_zPHY_tNV_user
- 0x1016c9b7 0x2c _g_zPsPhyATNvLte
- 0x1016c9e3 0x6 _g_zPsPhyATNvcom
- COMMON 0x1016c9e9 0xe5b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ 0x1014aaf4 0x8 _g_tUEIdInfo
+ 0x1014aafc 0x1e000 _g_zPHY_AMT_tNVInfo
+ 0x10168afc 0x2540 _g_zPHY_tNVInfo
+ 0x1016b03c 0x198c _g_zPHY_tNV_user
+ 0x1016c9c8 0x2c _g_zPsPhyATNvLte
+ 0x1016c9f4 0x6 _g_zPsPhyATNvcom
+ COMMON 0x1016c9fa 0xe5b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
0x0 (size before relaxing)
- 0x1016c9e9 0x158 _g_EUL_SrsStatisticsInfo
- 0x1016cb41 0x136 _g_EDL_PDSCH_INFO
- 0x1016cc77 0x2 _g_dwUlResidualBlerCount
- 0x1016cc79 0xb8 _g_EUL_CqiHarqSimulStatisticsInfo
- 0x1016cd31 0x2 _g_EDL_PA_INFO
- 0x1016cd33 0xc _g_UL_SrHarqSimulStatisticsInfo
- 0x1016cd3f 0x2a _g_UE_BASE_INFO
- 0x1016cd69 0x4 _g_dwTxThroughPutBps
- 0x1016cd6d 0x72 _g_EDL_PCFICH_INFO
- 0x1016cddf 0x82 _g_EUL_Dci0Info
- 0x1016ce61 0x10e _g_EDL_PHICH_INFO
- 0x1016cf6f 0x4 _g_dwUlNewTransCount
- 0x1016cf73 0x8 _g_EUL_DCI3Or3AInfo
- 0x1016cf7b 0x230 _g_EDL_DCI_INFO
- 0x1016d1ab 0x4 _g_dwRxThroughPutBps
- 0x1016d1af 0x40 _g_EDL_CALC_For_SINR
- 0x1016d1ef 0x12 _g_EDLUL_FLOW_INFO
- 0x1016d201 0x20 _g_EUL_PucchFmtStatisticsInfo
- 0x1016d221 0x44 _g_UL_MutiplexingANStatisticsInfo
- 0x1016d265 0x9a _g_EDL_HARQ_INFO
- 0x1016d2ff 0x52 _g_EUL_HarqTransStatisticsInfo
- 0x1016d351 0x3c _g_EDL_WORK_INFO
- 0x1016d38d 0x22 _g_EUL_AT_INFO
- 0x1016d3af 0x3c _g_EUL_BunldingANStatisticsInfo
- 0x1016d3eb 0x52 _g_EUL_PowerCtrlInfo
- 0x1016d43d 0x2d0 _g_EDL_PDCCH_INFO
- 0x1016d70d 0x2 _gdwUlTmtFlowCount
- 0x1016d70f 0x54 _g_EDL_AT_INFO
- 0x1016d763 0x2 _g_TmtLogCnt
- 0x1016d765 0x2 _gdwTmtFlowCount
- 0x1016d767 0xd9 _g_EUL_PrachStatisticsInfo
- 0x1016d840 0x4 _g_dwUlHarqFailCount
- COMMON 0x1016d844 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ 0x1016c9fa 0x158 _g_EUL_SrsStatisticsInfo
+ 0x1016cb52 0x136 _g_EDL_PDSCH_INFO
+ 0x1016cc88 0x2 _g_dwUlResidualBlerCount
+ 0x1016cc8a 0xb8 _g_EUL_CqiHarqSimulStatisticsInfo
+ 0x1016cd42 0x2 _g_EDL_PA_INFO
+ 0x1016cd44 0xc _g_UL_SrHarqSimulStatisticsInfo
+ 0x1016cd50 0x2a _g_UE_BASE_INFO
+ 0x1016cd7a 0x4 _g_dwTxThroughPutBps
+ 0x1016cd7e 0x72 _g_EDL_PCFICH_INFO
+ 0x1016cdf0 0x82 _g_EUL_Dci0Info
+ 0x1016ce72 0x10e _g_EDL_PHICH_INFO
+ 0x1016cf80 0x4 _g_dwUlNewTransCount
+ 0x1016cf84 0x8 _g_EUL_DCI3Or3AInfo
+ 0x1016cf8c 0x230 _g_EDL_DCI_INFO
+ 0x1016d1bc 0x4 _g_dwRxThroughPutBps
+ 0x1016d1c0 0x40 _g_EDL_CALC_For_SINR
+ 0x1016d200 0x12 _g_EDLUL_FLOW_INFO
+ 0x1016d212 0x20 _g_EUL_PucchFmtStatisticsInfo
+ 0x1016d232 0x44 _g_UL_MutiplexingANStatisticsInfo
+ 0x1016d276 0x9a _g_EDL_HARQ_INFO
+ 0x1016d310 0x52 _g_EUL_HarqTransStatisticsInfo
+ 0x1016d362 0x3c _g_EDL_WORK_INFO
+ 0x1016d39e 0x22 _g_EUL_AT_INFO
+ 0x1016d3c0 0x3c _g_EUL_BunldingANStatisticsInfo
+ 0x1016d3fc 0x52 _g_EUL_PowerCtrlInfo
+ 0x1016d44e 0x2d0 _g_EDL_PDCCH_INFO
+ 0x1016d71e 0x2 _gdwUlTmtFlowCount
+ 0x1016d720 0x54 _g_EDL_AT_INFO
+ 0x1016d774 0x2 _g_TmtLogCnt
+ 0x1016d776 0x2 _gdwTmtFlowCount
+ 0x1016d778 0xd9 _g_EUL_PrachStatisticsInfo
+ 0x1016d851 0x4 _g_dwUlHarqFailCount
+ COMMON 0x1016d855 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
0x0 (size before relaxing)
- 0x1016d844 0x4 _gt_CsiPrintCtrl
- 0x1016d848 0x1 _g_wLastAbsSfn
- 0x1016d849 0x1 _g_wCsiWorkFlg
- COMMON 0x1016d84a 0x16 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ 0x1016d855 0x4 _gt_CsiPrintCtrl
+ 0x1016d859 0x1 _g_wLastAbsSfn
+ 0x1016d85a 0x1 _g_wCsiWorkFlg
+ COMMON 0x1016d85b 0x16 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
0x0 (size before relaxing)
- 0x1016d84a 0x4 _g_adwTbCbCrc
- 0x1016d84e 0x10 _g_adwDebugDLS
- 0x1016d85e 0x2 _g_awTbCrc
- COMMON 0x1016d860 0x51 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x1016d85b 0x4 _g_adwTbCbCrc
+ 0x1016d85f 0x10 _g_adwDebugDLS
+ 0x1016d86f 0x2 _g_awTbCrc
+ COMMON 0x1016d871 0x51 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
0x0 (size before relaxing)
- 0x1016d860 0x1 _g_zPHY_bDdtrWorkFlag
- 0x1016d861 0x1 _wTest
- 0x1016d862 0x2 _g_zPHY_dwDdtrCfgTimer
- 0x1016d864 0x2 _g_awHarqPrintFlg
- 0x1016d866 0x32 _g_tdbCqi2DlsPmiInfo
- 0x1016d898 0x2 _dwCrcRlt
- 0x1016d89a 0x14 _awCfgHarqErr
- 0x1016d8ae 0x2 _g_awHarqPreTime
- 0x1016d8b0 0x1 _g_wLayerNum
- COMMON 0x1016d8b1 0x89 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x1016d871 0x1 _g_zPHY_bDdtrWorkFlag
+ 0x1016d872 0x1 _wTest
+ 0x1016d873 0x2 _g_zPHY_dwDdtrCfgTimer
+ 0x1016d875 0x2 _g_awHarqPrintFlg
+ 0x1016d877 0x32 _g_tdbCqi2DlsPmiInfo
+ 0x1016d8a9 0x2 _dwCrcRlt
+ 0x1016d8ab 0x14 _awCfgHarqErr
+ 0x1016d8bf 0x2 _g_awHarqPreTime
+ 0x1016d8c1 0x1 _g_wLayerNum
+ COMMON 0x1016d8c2 0x89 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
0x0 (size before relaxing)
- 0x1016d8b1 0x2 _g_dwOffsetDelta
- 0x1016d8b3 0x2 _g_zPHY_erfc_tempDac
- 0x1016d8b5 0x1 _g_zPHY_erfc_TempStartRecordFlag
- 0x1016d8b6 0x1 _g_dwOffsetFlag
- 0x1016d8b7 0x1 _g_zPHY_erfc_wMID2RXFlag
- 0x1016d8b8 0x1 _g_slot1_nRBNum
- 0x1016d8b9 0x14 _g_asdzPHY_erfc_CirServOrNeibor
- 0x1016d8cd 0x1 _g_zPHY_erfc_Meas0SubfNum
- 0x1016d8ce 0x2 _g_dwSubframeNumForTest
- 0x1016d8d0 0x2 _g_zPHY_erfc_CleanTxoffset
- 0x1016d8d2 0x2 _g_zPHY_erfc_Meas0Offset
- 0x1016d8d4 0x1 _g_zPHY_erfc_wSyncState
- 0x1016d8d5 0x1 _g_slot0_RBStart
- 0x1016d8d6 0x2 _g_zPHY_erfc_Meas1Offset
- 0x1016d8d8 0x2 _g_zPHY_erfc_InitialTempDac
- 0x1016d8da 0x2 _g_zPHY_erfc_TxMulmOffset
- 0x1016d8dc 0x2 _g_zPHY_erfc_RxoffsetAcumulator
- 0x1016d8de 0x2 _g_AgcHwModeOnFalg
- 0x1016d8e0 0x1 _g_zPHY_erfc_eAcp405NextState
- 0x1016d8e1 0x1 _g_slot1_RBStart
- 0x1016d8e2 0x1 _g_zPHY_erfc_eAcp405CurrState
- 0x1016d8e3 0x1 _g_wReadState
- 0x1016d8e4 0x4 _g_tLteRfcTmpReadInfo
- 0x1016d8e8 0x14 _g_adzPHY_erfc_MainAntInd
- 0x1016d8fc 0x1 _g_zPHY_erfc_TaTimer
- 0x1016d8fd 0x2 _g_adzPHY_erfc_CurMainAntInd
- 0x1016d8ff 0x2 _g_dwTxoffset
- 0x1016d901 0x2 _g_dwDbgSubfCount
- 0x1016d903 0x1 _g_slot0_nRBNum
- 0x1016d904 0x33 _gtLteRfcRpiPwrCtl
- 0x1016d937 0x2 _g_zPHY_erfc_RfStateMap
- 0x1016d939 0x1 _g_zPHY_erfc_Meas0SubfDef
- COMMON 0x1016d93a 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x1016d8c2 0x2 _g_dwOffsetDelta
+ 0x1016d8c4 0x2 _g_zPHY_erfc_tempDac
+ 0x1016d8c6 0x1 _g_zPHY_erfc_TempStartRecordFlag
+ 0x1016d8c7 0x1 _g_dwOffsetFlag
+ 0x1016d8c8 0x1 _g_zPHY_erfc_wMID2RXFlag
+ 0x1016d8c9 0x1 _g_slot1_nRBNum
+ 0x1016d8ca 0x14 _g_asdzPHY_erfc_CirServOrNeibor
+ 0x1016d8de 0x1 _g_zPHY_erfc_Meas0SubfNum
+ 0x1016d8df 0x2 _g_dwSubframeNumForTest
+ 0x1016d8e1 0x2 _g_zPHY_erfc_CleanTxoffset
+ 0x1016d8e3 0x2 _g_zPHY_erfc_Meas0Offset
+ 0x1016d8e5 0x1 _g_zPHY_erfc_wSyncState
+ 0x1016d8e6 0x1 _g_slot0_RBStart
+ 0x1016d8e7 0x2 _g_zPHY_erfc_Meas1Offset
+ 0x1016d8e9 0x2 _g_zPHY_erfc_InitialTempDac
+ 0x1016d8eb 0x2 _g_zPHY_erfc_TxMulmOffset
+ 0x1016d8ed 0x2 _g_zPHY_erfc_RxoffsetAcumulator
+ 0x1016d8ef 0x2 _g_AgcHwModeOnFalg
+ 0x1016d8f1 0x1 _g_zPHY_erfc_eAcp405NextState
+ 0x1016d8f2 0x1 _g_slot1_RBStart
+ 0x1016d8f3 0x1 _g_zPHY_erfc_eAcp405CurrState
+ 0x1016d8f4 0x1 _g_wReadState
+ 0x1016d8f5 0x4 _g_tLteRfcTmpReadInfo
+ 0x1016d8f9 0x14 _g_adzPHY_erfc_MainAntInd
+ 0x1016d90d 0x1 _g_zPHY_erfc_TaTimer
+ 0x1016d90e 0x2 _g_adzPHY_erfc_CurMainAntInd
+ 0x1016d910 0x2 _g_dwTxoffset
+ 0x1016d912 0x2 _g_dwDbgSubfCount
+ 0x1016d914 0x1 _g_slot0_nRBNum
+ 0x1016d915 0x33 _gtLteRfcRpiPwrCtl
+ 0x1016d948 0x2 _g_zPHY_erfc_RfStateMap
+ 0x1016d94a 0x1 _g_zPHY_erfc_Meas0SubfDef
+ COMMON 0x1016d94b 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
0x0 (size before relaxing)
- 0x1016d93a 0x1 _g_wRi1LstCqi
- 0x1016d93b 0x1 _g_wStartCNTFlg
- 0x1016d93c 0x61 _gt_CsiFilter
- 0x1016d99d 0x1 _g_wLstTm
- 0x1016d99e 0xaa _g_atCsiPmiRiCalcResult
- 0x1016da48 0x1 _g_wCNT
- COMMON 0x1016da49 0xbb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ 0x1016d94b 0x1 _g_wRi1LstCqi
+ 0x1016d94c 0x1 _g_wStartCNTFlg
+ 0x1016d94d 0x61 _gt_CsiFilter
+ 0x1016d9ae 0x1 _g_wLstTm
+ 0x1016d9af 0xaa _g_atCsiPmiRiCalcResult
+ 0x1016da59 0x1 _g_wCNT
+ COMMON 0x1016da5a 0xbb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
0x0 (size before relaxing)
- 0x1016da49 0x28 _g_L1e_dwPbchEvtList
- 0x1016da71 0x1e _g_L1e_tPbchCB
- 0x1016da8f 0x22 _g_L1e_tMibRxReg
- 0x1016dab1 0x9 _g_L1e_tDlaparaSave
- 0x1016daba 0x14 _g_L1e_tMibPbchReg
- 0x1016dace 0x15 _g_L1e_tMibInfo
- 0x1016dae3 0xc _g_L1e_tBchOps
- 0x1016daef 0xa _g_DbgMibPerStat
- 0x1016daf9 0xb _g_L1e_tMibRfcBackUp
- COMMON 0x1016db04 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x1016da5a 0x28 _g_L1e_dwPbchEvtList
+ 0x1016da82 0x1e _g_L1e_tPbchCB
+ 0x1016daa0 0x22 _g_L1e_tMibRxReg
+ 0x1016dac2 0x9 _g_L1e_tDlaparaSave
+ 0x1016dacb 0x14 _g_L1e_tMibPbchReg
+ 0x1016dadf 0x15 _g_L1e_tMibInfo
+ 0x1016daf4 0xc _g_L1e_tBchOps
+ 0x1016db00 0xa _g_DbgMibPerStat
+ 0x1016db0a 0xb _g_L1e_tMibRfcBackUp
+ COMMON 0x1016db15 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
0x0 (size before relaxing)
- 0x1016db04 0x1 _g_wMsg4AckRaConflictCnt
- 0x1016db05 0x1 _g_wHarqGroupNum
- COMMON 0x1016db06 0x9c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ 0x1016db15 0x1 _g_wMsg4AckRaConflictCnt
+ 0x1016db16 0x1 _g_wHarqGroupNum
+ COMMON 0x1016db17 0x9c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
0x0 (size before relaxing)
- 0x1016db06 0x9 _g_atCqiCommonInfo
- 0x1016db0f 0x1 _g_awCqiPmiRiIndex
- 0x1016db10 0xd _g_atBandWidthInfo
- 0x1016db1d 0xa _g_adAperLastCqiPmiDataBuffer
- 0x1016db27 0x1 _g_awAPERLastRI
- 0x1016db28 0x32 _g_atCsiEnFinal
- 0x1016db5a 0x8 _g_atPeriodRepPara
- 0x1016db62 0x1 _g_awLastReportIndex
- 0x1016db63 0x2 _g_awLastWBPMI
- 0x1016db65 0x4 _g_tCsiTime
- 0x1016db69 0x1 _g_awLastWBCQICW0
- 0x1016db6a 0x1 _g_awRiBitLen
- 0x1016db6b 0x1 _g_awAPERLastWBCQICW0
- 0x1016db6c 0x2 _g_awLastRI
- 0x1016db6e 0x32 _g_atCqiDedicateInfo
- 0x1016dba0 0x1 _g_awLastWBCQICW1
- 0x1016dba1 0x1 _g_awMaxLayerNum
- COMMON 0x1016dba2 0x233b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+ 0x1016db17 0x9 _g_atCqiCommonInfo
+ 0x1016db20 0x1 _g_awCqiPmiRiIndex
+ 0x1016db21 0xd _g_atBandWidthInfo
+ 0x1016db2e 0xa _g_adAperLastCqiPmiDataBuffer
+ 0x1016db38 0x1 _g_awAPERLastRI
+ 0x1016db39 0x32 _g_atCsiEnFinal
+ 0x1016db6b 0x8 _g_atPeriodRepPara
+ 0x1016db73 0x1 _g_awLastReportIndex
+ 0x1016db74 0x2 _g_awLastWBPMI
+ 0x1016db76 0x4 _g_tCsiTime
+ 0x1016db7a 0x1 _g_awLastWBCQICW0
+ 0x1016db7b 0x1 _g_awRiBitLen
+ 0x1016db7c 0x1 _g_awAPERLastWBCQICW0
+ 0x1016db7d 0x2 _g_awLastRI
+ 0x1016db7f 0x32 _g_atCqiDedicateInfo
+ 0x1016dbb1 0x1 _g_awLastWBCQICW1
+ 0x1016dbb2 0x1 _g_awMaxLayerNum
+ COMMON 0x1016dbb3 0x233b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
0x0 (size before relaxing)
- 0x1016dba2 0x50 _g_awFHopSeq4SubBands
- 0x1016dbf2 0x2 _g_dwTpcPrintCnt
- 0x1016dbf4 0x50 _g_awFHopSeq3SubBands
- 0x1016dc44 0x2 _g_dwSrsPrintCnt
- 0x1016dc46 0x2 _g_dwPucchPrintCnt
- 0x1016dc48 0x2 _g_dwPrachPrintCnt
- 0x1016dc4a 0x50 _g_awFHopSeq2SubBands
- 0x1016dc9a 0x4 _g_awSpecPrachNum
- 0x1016dc9e 0x50 _g_awFmSeq
- 0x1016dcee 0xe98 _g_zPHY_etx_HarqProDbPort0
- 0x1016eb86 0x50 _g_awFmSeq_Scell
- 0x1016ebd6 0x8 _g_t_zPHY_etx_Uls_H2L_HarqProcessIDInfo
- 0x1016ebde 0x8 _g_t_zPHY_etx_HarqProcessIDInfo
- 0x1016ebe6 0x25f _g_awUlTestMacPduBuf
- 0x1016ee45 0x50 _g_awFHopSeq2SubBands_Scell
- 0x1016ee95 0xe98 _g_zPHY_etx_HarqProDbPort1
- 0x1016fd2d 0x104 _g_t_zPHY_Dls2UlsDciValue
- 0x1016fe31 0x50 _g_awFHopSeq4SubBands_Scell
- 0x1016fe81 0x2 _g_dwCloseLoopPowerPrintCnt
- 0x1016fe83 0x2 _g_dwPuschPrintCnt
- 0x1016fe85 0x50 _g_awFHopSeq3SubBands_Scell
- 0x1016fed5 0x8 _g_t_zPHY_etx_RarUlGrant
- COMMON 0x1016fedd 0x4e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ 0x1016dbb3 0x50 _g_awFHopSeq4SubBands
+ 0x1016dc03 0x2 _g_dwTpcPrintCnt
+ 0x1016dc05 0x50 _g_awFHopSeq3SubBands
+ 0x1016dc55 0x2 _g_dwSrsPrintCnt
+ 0x1016dc57 0x2 _g_dwPucchPrintCnt
+ 0x1016dc59 0x2 _g_dwPrachPrintCnt
+ 0x1016dc5b 0x50 _g_awFHopSeq2SubBands
+ 0x1016dcab 0x4 _g_awSpecPrachNum
+ 0x1016dcaf 0x50 _g_awFmSeq
+ 0x1016dcff 0xe98 _g_zPHY_etx_HarqProDbPort0
+ 0x1016eb97 0x50 _g_awFmSeq_Scell
+ 0x1016ebe7 0x8 _g_t_zPHY_etx_Uls_H2L_HarqProcessIDInfo
+ 0x1016ebef 0x8 _g_t_zPHY_etx_HarqProcessIDInfo
+ 0x1016ebf7 0x25f _g_awUlTestMacPduBuf
+ 0x1016ee56 0x50 _g_awFHopSeq2SubBands_Scell
+ 0x1016eea6 0xe98 _g_zPHY_etx_HarqProDbPort1
+ 0x1016fd3e 0x104 _g_t_zPHY_Dls2UlsDciValue
+ 0x1016fe42 0x50 _g_awFHopSeq4SubBands_Scell
+ 0x1016fe92 0x2 _g_dwCloseLoopPowerPrintCnt
+ 0x1016fe94 0x2 _g_dwPuschPrintCnt
+ 0x1016fe96 0x50 _g_awFHopSeq3SubBands_Scell
+ 0x1016fee6 0x8 _g_t_zPHY_etx_RarUlGrant
+ COMMON 0x1016feee 0x4e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
0x0 (size before relaxing)
- 0x1016fedd 0x1 _g_swPrintProNoInt
- 0x1016fede 0x10 _g_asdwL1eRxCrsRsrp
- 0x1016feee 0x4 _g_adwL1eRxCrsRssi
- 0x1016fef2 0x4 _g_lsdwNsIot_8242_SINR
- 0x1016fef6 0x18 _g_adwL1eRxDrsRsp
- 0x1016ff0e 0x1 _g_zPHY_emc_wCellComponFlag
- 0x1016ff0f 0xc _g_adwL1eRxCrsRsp
- 0x1016ff1b 0x1 _g_wLtel1IdleAccessReqInd
- 0x1016ff1c 0x1 _g_awL1eRxBfDagcFlag
- 0x1016ff1d 0x1 _g_awL1eRxBfTransFlag
- 0x1016ff1e 0x1 _g_wL1eRxNbNbSinrCalInd
- 0x1016ff1f 0xb _g_zPHY_emc_tSinrInfo
- 0x1016ff2a 0x1 _g_awL1eRxDrsAccNum
- COMMON 0x1016ff2b 0x118e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+ 0x1016feee 0x1 _g_swPrintProNoInt
+ 0x1016feef 0x10 _g_asdwL1eRxCrsRsrp
+ 0x1016feff 0x4 _g_adwL1eRxCrsRssi
+ 0x1016ff03 0x4 _g_lsdwNsIot_8242_SINR
+ 0x1016ff07 0x18 _g_adwL1eRxDrsRsp
+ 0x1016ff1f 0x1 _g_zPHY_emc_wCellComponFlag
+ 0x1016ff20 0xc _g_adwL1eRxCrsRsp
+ 0x1016ff2c 0x1 _g_wLtel1IdleAccessReqInd
+ 0x1016ff2d 0x1 _g_awL1eRxBfDagcFlag
+ 0x1016ff2e 0x1 _g_awL1eRxBfTransFlag
+ 0x1016ff2f 0x1 _g_wL1eRxNbNbSinrCalInd
+ 0x1016ff30 0xb _g_zPHY_emc_tSinrInfo
+ 0x1016ff3b 0x1 _g_awL1eRxDrsAccNum
+ COMMON 0x1016ff3c 0x118e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
0x0 (size before relaxing)
- 0x1016ff2b 0xa _g_awPSeqCellIDDiv30
- 0x1016ff35 0x12b _g_tUlaLtxParas
- 0x10170060 0x46 _g_awPSeqCellIDDiv30SS
- 0x101700a6 0x1 _g_EUL_wPuschPowerIdx
- 0x101700a7 0x1 _g_EUL_wPucchPowerIdx
- 0x101700a8 0xe7 _g_tUlaCommRelatedParasScell
- 0x1017018f 0x46 _g_awPSeqCellIDDiv30SS_Scell
- 0x101701d5 0x1 _g_EUL_wSrsPowerIdx
- 0x101701d6 0x6 _g_tUlaDediRelatedParas
- 0x101701dc 0x4 _g_tUlaCID
- 0x101701e0 0xa6d _g_t_zPHY_eula_CtrlBlock
- 0x10170c4d 0x50 _g_awPSeqCellID
- 0x10170c9d 0x1c _g_tUlaCommConfig
- 0x10170cb9 0xac _g_tUlaDediConfig
- 0x10170d65 0xa _g_awPSeqPuschSeqShift
- 0x10170d6f 0xc8 _g_tUlaScellInfo
- 0x10170e37 0xe7 _g_tUlaCommRelatedParas
- 0x10170f1e 0xa _g_awPSeqCellIDDiv30_Scell
- 0x10170f28 0x1f _g_tUlaPucchInfo
- 0x10170f47 0x120 _g_tSrsInfo
- 0x10171067 0x50 _g_awPSeqCellID_Scell
- 0x101710b7 0x1 _g_w_FirstFlgSet
- 0x101710b8 0x1 _g_EUL_wPrachPowerIdx
- COMMON 0x101710b9 0x54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x1016ff3c 0xa _g_awPSeqCellIDDiv30
+ 0x1016ff46 0x12b _g_tUlaLtxParas
+ 0x10170071 0x46 _g_awPSeqCellIDDiv30SS
+ 0x101700b7 0x1 _g_EUL_wPuschPowerIdx
+ 0x101700b8 0x1 _g_EUL_wPucchPowerIdx
+ 0x101700b9 0xe7 _g_tUlaCommRelatedParasScell
+ 0x101701a0 0x46 _g_awPSeqCellIDDiv30SS_Scell
+ 0x101701e6 0x1 _g_EUL_wSrsPowerIdx
+ 0x101701e7 0x6 _g_tUlaDediRelatedParas
+ 0x101701ed 0x4 _g_tUlaCID
+ 0x101701f1 0xa6d _g_t_zPHY_eula_CtrlBlock
+ 0x10170c5e 0x50 _g_awPSeqCellID
+ 0x10170cae 0x1c _g_tUlaCommConfig
+ 0x10170cca 0xac _g_tUlaDediConfig
+ 0x10170d76 0xa _g_awPSeqPuschSeqShift
+ 0x10170d80 0xc8 _g_tUlaScellInfo
+ 0x10170e48 0xe7 _g_tUlaCommRelatedParas
+ 0x10170f2f 0xa _g_awPSeqCellIDDiv30_Scell
+ 0x10170f39 0x1f _g_tUlaPucchInfo
+ 0x10170f58 0x120 _g_tSrsInfo
+ 0x10171078 0x50 _g_awPSeqCellID_Scell
+ 0x101710c8 0x1 _g_w_FirstFlgSet
+ 0x101710c9 0x1 _g_EUL_wPrachPowerIdx
+ COMMON 0x101710ca 0x54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
0x0 (size before relaxing)
- 0x101710b9 0x1 _g_L1l_LpmCaliIdx
- 0x101710ba 0x8 _g_L1l_MrtrBeforeWakup
- 0x101710c2 0xa _g_wTpuIntTypeforlpm
- 0x101710cc 0x2 _g_L1l_LpmCaliCnt
- 0x101710ce 0x6 _g_zPHY_tSuperFrameCtrlInfo
- 0x101710d4 0x22 _g_zPHY_tWakeupTimerInfo
- 0x101710f6 0x1 _g_zPHY_dwTpuSleepTimeLenByFrame
- 0x101710f7 0x1 _g_L1lLpAwakeTimerCtrl
- 0x101710f8 0x2 _g_zPHY_tWakeupReq
- 0x101710fa 0x1 _g_L1lLpTaskStateCtrl
- 0x101710fb 0x2 _g_L1l_LpmModemWakeupTime
- 0x101710fd 0x2 _g_L1l_LpmCaliAbortTime
- 0x101710ff 0x2 _g_tL1lLpCtrl
- 0x10171101 0x2 _g_L1l_LpmSocWakeupTime
- 0x10171103 0x2 _g_zPHY_LtePhySleepCnt
- 0x10171105 0x8 _g_L1l_MrtrAfterSleep
- COMMON 0x1017110d 0x14e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x101710ca 0x1 _g_L1l_LpmCaliIdx
+ 0x101710cb 0x8 _g_L1l_MrtrBeforeWakup
+ 0x101710d3 0xa _g_wTpuIntTypeforlpm
+ 0x101710dd 0x2 _g_L1l_LpmCaliCnt
+ 0x101710df 0x6 _g_zPHY_tSuperFrameCtrlInfo
+ 0x101710e5 0x22 _g_zPHY_tWakeupTimerInfo
+ 0x10171107 0x1 _g_zPHY_dwTpuSleepTimeLenByFrame
+ 0x10171108 0x1 _g_L1lLpAwakeTimerCtrl
+ 0x10171109 0x2 _g_zPHY_tWakeupReq
+ 0x1017110b 0x1 _g_L1lLpTaskStateCtrl
+ 0x1017110c 0x2 _g_L1l_LpmModemWakeupTime
+ 0x1017110e 0x2 _g_L1l_LpmCaliAbortTime
+ 0x10171110 0x2 _g_tL1lLpCtrl
+ 0x10171112 0x2 _g_L1l_LpmSocWakeupTime
+ 0x10171114 0x2 _g_zPHY_LtePhySleepCnt
+ 0x10171116 0x8 _g_L1l_MrtrAfterSleep
+ COMMON 0x1017111e 0x14e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
0x0 (size before relaxing)
- 0x1017110d 0x10 _g_adw_zPHY_erfc_profile_DB
- 0x1017111d 0x2 _g_dwLPTxoffset
- 0x1017111f 0x1 _g_zPHY_erfc_AfcWord
- 0x10171120 0xc0 _g_zPHY_erfc_aNVBandIndex
- 0x101711e0 0x39 _g_zPHY_erfc_atLPCSFConfig
- 0x10171219 0x2 _g_zPHY_erfc_ACP405Version
- 0x1017121b 0x40 _g_at_zPHY_erfc_atReloadData
- COMMON 0x1017125b 0x11 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ 0x1017111e 0x10 _g_adw_zPHY_erfc_profile_DB
+ 0x1017112e 0x2 _g_dwLPTxoffset
+ 0x10171130 0x1 _g_zPHY_erfc_AfcWord
+ 0x10171131 0xc0 _g_zPHY_erfc_aNVBandIndex
+ 0x101711f1 0x39 _g_zPHY_erfc_atLPCSFConfig
+ 0x1017122a 0x2 _g_zPHY_erfc_ACP405Version
+ 0x1017122c 0x40 _g_at_zPHY_erfc_atReloadData
+ COMMON 0x1017126c 0x11 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
0x0 (size before relaxing)
- 0x1017125b 0x1 _g_zPHY_ecsrm_wNextIntFlag
- 0x1017125c 0x1 _g_ZPHY_ecsrm_tMeasState
- 0x1017125d 0xf _g_zPHY_ecsrm_tCommInfo
- COMMON 0x1017126c 0x120 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ 0x1017126c 0x1 _g_zPHY_ecsrm_wNextIntFlag
+ 0x1017126d 0x1 _g_ZPHY_ecsrm_tMeasState
+ 0x1017126e 0xf _g_zPHY_ecsrm_tCommInfo
+ COMMON 0x1017127d 0x120 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
0x0 (size before relaxing)
- 0x1017126c 0x120 _g_MeasContext
- COMMON 0x1017138c 0x7 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ 0x1017127d 0x120 _g_MeasContext
+ COMMON 0x1017139d 0x7 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
0x0 (size before relaxing)
- 0x1017138c 0x7 _g_tUlBlerInfo
- *fill* 0x10171393 0x80000001 00
- COMMON 0x10171394 0x3ec T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x1017139d 0x7 _g_tUlBlerInfo
+ COMMON 0x101713a4 0x3ec T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
0x0 (size before relaxing)
- 0x10171394 0x2 _g_awMbmsClusterNum
- 0x10171396 0x1 _g_ePreRapcState
- 0x10171397 0x30 _g_aswMBMS_MaxDelay
- 0x101713c7 0x31 _g_aswMBMS_FftWinStart
- 0x101713f8 0xc4 _g_aswFreq_Inter_Coeff
- 0x101714bc 0xc4 _g_aswFreq_NormalCoeff
- 0x10171580 0x200 _g_aiInitSequence
- COMMON 0x10171780 0x1c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ 0x101713a4 0x2 _g_awMbmsClusterNum
+ 0x101713a6 0x1 _g_ePreRapcState
+ 0x101713a7 0x30 _g_aswMBMS_MaxDelay
+ 0x101713d7 0x31 _g_aswMBMS_FftWinStart
+ 0x10171408 0xc4 _g_aswFreq_Inter_Coeff
+ 0x101714cc 0xc4 _g_aswFreq_NormalCoeff
+ 0x10171590 0x200 _g_aiInitSequence
+ COMMON 0x10171790 0x1c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
0x0 (size before relaxing)
- 0x10171780 0x14 _g_tLteA1DlaRxCb
- 0x10171794 0x4 _g_awL1eRxRsrpFilter
- 0x10171798 0x4 _g_awL1eRxRsrpFilterFlag
- COMMON 0x1017179c 0x3cf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x10171790 0x14 _g_tLteA1DlaRxCb
+ 0x101717a4 0x4 _g_awL1eRxRsrpFilter
+ 0x101717a8 0x4 _g_awL1eRxRsrpFilterFlag
+ COMMON 0x101717ac 0x3cf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
0x0 (size before relaxing)
- 0x1017179c 0x1 _g_zPHY_edfe_wAgcEnEventFlag
- 0x1017179d 0x8 _g_tTempDCOffsetComp
- 0x101717a5 0xd _g_zPHY_edfe_tPlmnSaveServCellAgc
- 0x101717b2 0x1 _g_zPHY_edfe_wRxLinDagc1
- 0x101717b3 0x1 _g_zPHY_edfe_swAgcMeanPwr1
- 0x101717b4 0x2 _g_zPHY_edfe_dwScanFreqAgcCalFlag
- 0x101717b6 0x2 _g_zPHY_edfe_aswAgcMeanPwr_Samp0
- 0x101717b8 0x1 _g_zPHY_edfe_wNotSyncAGCDone
- 0x101717b9 0x1 _g_zPHY_edfe_wRfcSingleAnt
- 0x101717ba 0x8 _g_tIQComp
- 0x101717c2 0x1 _g_wAgcCntForFirstDC
- 0x101717c3 0x6 _g_awAgcGain0
- 0x101717c9 0x1 _g_zPHY_edfe_wAgcLog2Gain0
- 0x101717ca 0x1 _g_zPHY_edfe_wCsrsLinDagc0
- 0x101717cb 0x1 _g_zPHY_edfe_wCsrmLinDagc1
- 0x101717cc 0x78 _g_zPHY_edfe_MeasAgcPara
- 0x10171844 0x1 _g_wCount
- 0x10171845 0x120 _g_a_zPHY_edfe_tReloadAgcData
- 0x10171965 0x1 _g_zPHY_edfe_cRxAntennaMode
- 0x10171966 0x18 _g_zPHY_edfe_tPlmnAgcPara
- 0x1017197e 0x8 _g_tDCOffsetCompRecord
- 0x10171986 0x2 _g_dwCsrmRssiRx0
- 0x10171988 0x1 _g_zPHY_edfe_wAgcExtendModeEn
- 0x10171989 0x6 _g_awAgcGain1
- 0x1017198f 0x2 _g_zPHY_edfe_aswAgcMeanPwr_Samp7
- 0x10171991 0x1 _g_zPHY_edfe_wNotSyncAGCDoneAnt1
- 0x10171992 0x1 _g_zPHY_edfe_wRxLinDagc0
- 0x10171993 0x28 _g_a_zPHY_edfe_wCsrmTotalAgcGainLog2
- 0x101719bb 0x78 _g_tDfeNotchInfo
- 0x10171a33 0x1 _g_zPHY_edfe_wAgcIntReportFlag
- 0x10171a34 0x6 _g_awTempMeanPower1
- 0x10171a3a 0x1 _g_zPHY_edfe_wAgcMeaPwSavReg
- 0x10171a3b 0x1 _g_zPHY_edfe_wAgcLog2Gain1
- 0x10171a3c 0x1 _g_zPHY_edfe_wSaveRxBand
- 0x10171a3d 0x1 _g_wAgcWorkState
- 0x10171a3e 0x1 _g_zPHY_edfe_wCsrmLinDagc0
- 0x10171a3f 0x1 _g_zPHY_edfe_wRfcSyncState
- 0x10171a40 0xd7 _g_EDFE_SYSTEM_INFO
- 0x10171b17 0x1 _g_zPHY_edfe_swAgcMeanPwr0
- 0x10171b18 0x1 _g_zPHY_edfe_wAgcdBGain0
- 0x10171b19 0x2 _g_DcCounter
- 0x10171b1b 0x8 _g_tDCOffsetEsti
- 0x10171b23 0x2 _g_dwCsrmRssiRx1
- 0x10171b25 0x8 _g_tDCOffsetComp
- 0x10171b2d 0x1 _g_wIqCount
- 0x10171b2e 0x2 _g_zPHY_edfe_dwSearchAgcCalFlag
- 0x10171b30 0x1 _g_zPHY_edfe_wCsrsLinDagc1
- 0x10171b31 0x28 _g_a_zPHY_edfe_wRxTotalAgcGainLog2
- 0x10171b59 0x1 _g_zPHY_erfc_SlaveOutGapAGC
- 0x10171b5a 0x1 _g_wCsrs_RX_Sib1_Read_Flag
- 0x10171b5b 0x8 _g_zPHY_edfe_tRxAgcBalance
- 0x10171b63 0x6 _g_awTempMeanPower0
- 0x10171b69 0x1 _g_zPHY_edfe_wAgcdBGain1
- 0x10171b6a 0x1 _g_zPHY_edfe_wNotSyncAGCDoneAnt0
- COMMON 0x10171b6b 0x1e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ 0x101717ac 0x1 _g_zPHY_edfe_wAgcEnEventFlag
+ 0x101717ad 0x8 _g_tTempDCOffsetComp
+ 0x101717b5 0xd _g_zPHY_edfe_tPlmnSaveServCellAgc
+ 0x101717c2 0x1 _g_zPHY_edfe_wRxLinDagc1
+ 0x101717c3 0x1 _g_zPHY_edfe_swAgcMeanPwr1
+ 0x101717c4 0x2 _g_zPHY_edfe_dwScanFreqAgcCalFlag
+ 0x101717c6 0x2 _g_zPHY_edfe_aswAgcMeanPwr_Samp0
+ 0x101717c8 0x1 _g_zPHY_edfe_wNotSyncAGCDone
+ 0x101717c9 0x1 _g_zPHY_edfe_wRfcSingleAnt
+ 0x101717ca 0x8 _g_tIQComp
+ 0x101717d2 0x1 _g_wAgcCntForFirstDC
+ 0x101717d3 0x6 _g_awAgcGain0
+ 0x101717d9 0x1 _g_zPHY_edfe_wAgcLog2Gain0
+ 0x101717da 0x1 _g_zPHY_edfe_wCsrsLinDagc0
+ 0x101717db 0x1 _g_zPHY_edfe_wCsrmLinDagc1
+ 0x101717dc 0x78 _g_zPHY_edfe_MeasAgcPara
+ 0x10171854 0x1 _g_wCount
+ 0x10171855 0x120 _g_a_zPHY_edfe_tReloadAgcData
+ 0x10171975 0x1 _g_zPHY_edfe_cRxAntennaMode
+ 0x10171976 0x18 _g_zPHY_edfe_tPlmnAgcPara
+ 0x1017198e 0x8 _g_tDCOffsetCompRecord
+ 0x10171996 0x2 _g_dwCsrmRssiRx0
+ 0x10171998 0x1 _g_zPHY_edfe_wAgcExtendModeEn
+ 0x10171999 0x6 _g_awAgcGain1
+ 0x1017199f 0x2 _g_zPHY_edfe_aswAgcMeanPwr_Samp7
+ 0x101719a1 0x1 _g_zPHY_edfe_wNotSyncAGCDoneAnt1
+ 0x101719a2 0x1 _g_zPHY_edfe_wRxLinDagc0
+ 0x101719a3 0x28 _g_a_zPHY_edfe_wCsrmTotalAgcGainLog2
+ 0x101719cb 0x78 _g_tDfeNotchInfo
+ 0x10171a43 0x1 _g_zPHY_edfe_wAgcIntReportFlag
+ 0x10171a44 0x6 _g_awTempMeanPower1
+ 0x10171a4a 0x1 _g_zPHY_edfe_wAgcMeaPwSavReg
+ 0x10171a4b 0x1 _g_zPHY_edfe_wAgcLog2Gain1
+ 0x10171a4c 0x1 _g_zPHY_edfe_wSaveRxBand
+ 0x10171a4d 0x1 _g_wAgcWorkState
+ 0x10171a4e 0x1 _g_zPHY_edfe_wCsrmLinDagc0
+ 0x10171a4f 0x1 _g_zPHY_edfe_wRfcSyncState
+ 0x10171a50 0xd7 _g_EDFE_SYSTEM_INFO
+ 0x10171b27 0x1 _g_zPHY_edfe_swAgcMeanPwr0
+ 0x10171b28 0x1 _g_zPHY_edfe_wAgcdBGain0
+ 0x10171b29 0x2 _g_DcCounter
+ 0x10171b2b 0x8 _g_tDCOffsetEsti
+ 0x10171b33 0x2 _g_dwCsrmRssiRx1
+ 0x10171b35 0x8 _g_tDCOffsetComp
+ 0x10171b3d 0x1 _g_wIqCount
+ 0x10171b3e 0x2 _g_zPHY_edfe_dwSearchAgcCalFlag
+ 0x10171b40 0x1 _g_zPHY_edfe_wCsrsLinDagc1
+ 0x10171b41 0x28 _g_a_zPHY_edfe_wRxTotalAgcGainLog2
+ 0x10171b69 0x1 _g_zPHY_erfc_SlaveOutGapAGC
+ 0x10171b6a 0x1 _g_wCsrs_RX_Sib1_Read_Flag
+ 0x10171b6b 0x8 _g_zPHY_edfe_tRxAgcBalance
+ 0x10171b73 0x6 _g_awTempMeanPower0
+ 0x10171b79 0x1 _g_zPHY_edfe_wAgcdBGain1
+ 0x10171b7a 0x1 _g_zPHY_edfe_wNotSyncAGCDoneAnt0
+ COMMON 0x10171b7b 0x1e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
0x0 (size before relaxing)
- 0x10171b6b 0x1 _g_eTxCalibrationStep
- 0x10171b6c 0x1 _g_wTxSendScaleDC
- 0x10171b6d 0x4 _g_awDfeFftOutputDC
- 0x10171b71 0x4 _g_awDfeFftOutputIQ
- 0x10171b75 0x2 _g_dwCalibration_angle
- 0x10171b77 0x1d3 _g_atzPHY_UlAMTHarqProcessDB
- 0x10171d4a 0x1 _g_wTxSendScaleIQ
- 0x10171d4b 0x1 _Configdelay
- 0x10171d4c 0x2 _g_dwCalibration_amp
- COMMON 0x10171d4e 0x269d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ 0x10171b7b 0x1 _g_eTxCalibrationStep
+ 0x10171b7c 0x1 _g_wTxSendScaleDC
+ 0x10171b7d 0x4 _g_awDfeFftOutputDC
+ 0x10171b81 0x4 _g_awDfeFftOutputIQ
+ 0x10171b85 0x2 _g_dwCalibration_angle
+ 0x10171b87 0x1d3 _g_atzPHY_UlAMTHarqProcessDB
+ 0x10171d5a 0x1 _g_wTxSendScaleIQ
+ 0x10171d5b 0x1 _Configdelay
+ 0x10171d5c 0x2 _g_dwCalibration_amp
+ COMMON 0x10171d5e 0x269d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
0x0 (size before relaxing)
- 0x10171d4e 0x1 _g_wAutoDeactiveTimer
- 0x10171d4f 0x6 _g_t_zPHY_DlaDciInfo
- 0x10171d55 0xa _g_tL1eDevRxLpConvergeCb
- 0x10171d5f 0x268c _g_t_zPHY_DlaCb
- COMMON 0x101743eb 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x10171d5e 0x1 _g_wAutoDeactiveTimer
+ 0x10171d5f 0x6 _g_t_zPHY_DlaDciInfo
+ 0x10171d65 0xa _g_tL1eDevRxLpConvergeCb
+ 0x10171d6f 0x268c _g_t_zPHY_DlaCb
+ COMMON 0x101743fb 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
0x0 (size before relaxing)
- 0x101743eb 0x2 _g_Scc_Rsrp_Cfo_IntCnt
- 0x101743ed 0x1 _g_wULA_Process_SubFrame
- 0x101743ee 0x2 _gTimer1Int_RcvNum
- 0x101743f0 0x6 _g_zPHY_Int_dwDFEIntType
- 0x101743f6 0x2 _g_zPHY_Int_dwDFEIntType_agc
- COMMON 0x101743f8 0xc0a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x101743fb 0x2 _g_Scc_Rsrp_Cfo_IntCnt
+ 0x101743fd 0x1 _g_wULA_Process_SubFrame
+ 0x101743fe 0x2 _gTimer1Int_RcvNum
+ 0x10174400 0x6 _g_zPHY_Int_dwDFEIntType
+ 0x10174406 0x2 _g_zPHY_Int_dwDFEIntType_agc
+ COMMON 0x10174408 0xc0a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
0x0 (size before relaxing)
- 0x101743f8 0x2 _g_dwL1lPreHookEntry
- 0x101743fa 0x2 _gL1l_MissLogInfo
- 0x101743fc 0xc00 _g_awL1lEngTempBuffer
- 0x10174ffc 0x2 _L1L_STANDARD_LOG_ID_BASE
- 0x10174ffe 0x2 _g_dwL1lCurrentHookEntry
- 0x10175000 0x2 _g_wL1lRemainLen
- COMMON 0x10175002 0x138d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+ 0x10174408 0x2 _g_dwL1lPreHookEntry
+ 0x1017440a 0x2 _gL1l_MissLogInfo
+ 0x1017440c 0xc00 _g_awL1lEngTempBuffer
+ 0x1017500c 0x2 _L1L_STANDARD_LOG_ID_BASE
+ 0x1017500e 0x2 _g_dwL1lCurrentHookEntry
+ 0x10175010 0x2 _g_wL1lRemainLen
+ COMMON 0x10175012 0x138d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
0x0 (size before relaxing)
- 0x10175002 0xd _g_tTTIBundlingDB
- 0x1017500f 0xe _g_zPHY_euls_tTpcCommands
- 0x1017501d 0x1 _g_EUL_wRachIdx
- 0x1017501e 0x14 _g_tRarCtrlDB
- 0x10175032 0x2 _g_EUL_wDci0InfoIdx
- 0x10175034 0x2d _g_tUlSPSDB
- 0x10175061 0x2a _g_zPHY_euls_ComConfig
- 0x1017508b 0x123e _g_tShadowHarqDB
- 0x101762c9 0x8 _g_tUlsDB
- 0x101762d1 0x72 _g_atDCI0PhichSelecDB
- 0x10176343 0x4c _g_zPHY_euls_DedConfig
- COMMON 0x1017638f 0x33 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x10175012 0xd _g_tTTIBundlingDB
+ 0x1017501f 0xe _g_zPHY_euls_tTpcCommands
+ 0x1017502d 0x1 _g_EUL_wRachIdx
+ 0x1017502e 0x14 _g_tRarCtrlDB
+ 0x10175042 0x2 _g_EUL_wDci0InfoIdx
+ 0x10175044 0x2d _g_tUlSPSDB
+ 0x10175071 0x2a _g_zPHY_euls_ComConfig
+ 0x1017509b 0x123e _g_tShadowHarqDB
+ 0x101762d9 0x8 _g_tUlsDB
+ 0x101762e1 0x72 _g_atDCI0PhichSelecDB
+ 0x10176353 0x4c _g_zPHY_euls_DedConfig
+ COMMON 0x1017639f 0x33 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
0x0 (size before relaxing)
- 0x1017638f 0x4 _g_zPHY_erfc_tCordicAdjustPara
- 0x10176393 0x2 _g_ACP405_AFC_DIFF
- 0x10176395 0x5 _g_zPHY_erfc_tAfcPara
- 0x1017639a 0x28 _g_sdAtCtl_ApcOffsetTime
- COMMON 0x101763c2 0x2c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ 0x1017639f 0x4 _g_zPHY_erfc_tCordicAdjustPara
+ 0x101763a3 0x2 _g_ACP405_AFC_DIFF
+ 0x101763a5 0x5 _g_zPHY_erfc_tAfcPara
+ 0x101763aa 0x28 _g_sdAtCtl_ApcOffsetTime
+ COMMON 0x101763d2 0x2c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
0x0 (size before relaxing)
- 0x101763c2 0x2 _gadwZeroCsiRsCollideInd
- 0x101763c4 0x2 _gau_zPHY_Rx_CsiRsIdicator
- 0x101763c6 0x1 _g_PchBlerInfo_0
- 0x101763c7 0x8 _gau_zPHY_Rx_ZeroPowerCisPos
- 0x101763cf 0x1 _g_PchBlerInfo_3
- 0x101763d0 0x2 _g_dwRxPreN0Value
- 0x101763d2 0x1 _g_wPrbNoPrintFlg
- 0x101763d3 0x2 _gauZeroPowerCsiBitMap
- 0x101763d5 0x2 _gadwCsiRsCollideInd
- 0x101763d7 0x1 _g_PchBlerInfo_1
- 0x101763d8 0x1 _g_PchTiCfgInd_1
- 0x101763d9 0x2 _gadwZeroPowerCsiRsPosCalculated
- 0x101763db 0x1 _g_tRxPreState
- 0x101763dc 0x1 _g_wPchFlag
- 0x101763dd 0x1 _g_tRxCurrState
- 0x101763de 0x1 _g_PchBlerInfo_4
- 0x101763df 0x2 _g_dwTempN0
- 0x101763e1 0x1 _gwNS_IOT_8242_Ind
- 0x101763e2 0x1 _g_awL1eRxNCellRsNullEnInd
- 0x101763e3 0x2 _gadwCsiRsPosCalculated
- 0x101763e5 0x1 _g_awRxCirTiCfgInd
- 0x101763e6 0x2 _gt_zPHY_Rx_ZeroCsiRsExistInd
- 0x101763e8 0x2 _g_awCsiRsCheCfgVal
- 0x101763ea 0x1 _g_PchBlerInfo_2
- 0x101763eb 0x1 _g_PchTiCfgInd_2
- 0x101763ec 0x2 _gt_zPHY_Rx_CsiRsExistInd
- COMMON 0x101763ee 0xa04 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
+ 0x101763d2 0x2 _gadwZeroCsiRsCollideInd
+ 0x101763d4 0x2 _gau_zPHY_Rx_CsiRsIdicator
+ 0x101763d6 0x1 _g_PchBlerInfo_0
+ 0x101763d7 0x8 _gau_zPHY_Rx_ZeroPowerCisPos
+ 0x101763df 0x1 _g_PchBlerInfo_3
+ 0x101763e0 0x2 _g_dwRxPreN0Value
+ 0x101763e2 0x1 _g_wPrbNoPrintFlg
+ 0x101763e3 0x2 _gauZeroPowerCsiBitMap
+ 0x101763e5 0x2 _gadwCsiRsCollideInd
+ 0x101763e7 0x1 _g_PchBlerInfo_1
+ 0x101763e8 0x1 _g_PchTiCfgInd_1
+ 0x101763e9 0x2 _gadwZeroPowerCsiRsPosCalculated
+ 0x101763eb 0x1 _g_tRxPreState
+ 0x101763ec 0x1 _g_wPchFlag
+ 0x101763ed 0x1 _g_tRxCurrState
+ 0x101763ee 0x1 _g_PchBlerInfo_4
+ 0x101763ef 0x2 _g_dwTempN0
+ 0x101763f1 0x1 _gwNS_IOT_8242_Ind
+ 0x101763f2 0x1 _g_awL1eRxNCellRsNullEnInd
+ 0x101763f3 0x2 _gadwCsiRsPosCalculated
+ 0x101763f5 0x1 _g_awRxCirTiCfgInd
+ 0x101763f6 0x2 _gt_zPHY_Rx_ZeroCsiRsExistInd
+ 0x101763f8 0x2 _g_awCsiRsCheCfgVal
+ 0x101763fa 0x1 _g_PchBlerInfo_2
+ 0x101763fb 0x1 _g_PchTiCfgInd_2
+ 0x101763fc 0x2 _gt_zPHY_Rx_CsiRsExistInd
+ COMMON 0x101763fe 0xa04 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
0x0 (size before relaxing)
- 0x101763ee 0x510 _g_adwCommDlschPara1A
- 0x101768fe 0x300 _g_adwCommDlschPara1C
- 0x10176bfe 0x1f4 _g_adwPhyNirDivC
- COMMON 0x10176df2 0x258 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x101763fe 0x510 _g_adwCommDlschPara1A
+ 0x1017690e 0x300 _g_adwCommDlschPara1C
+ 0x10176c0e 0x1f4 _g_adwPhyNirDivC
+ COMMON 0x10176e02 0x258 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
0x0 (size before relaxing)
- 0x10176df2 0x24c _g_TopReg
- 0x1017703e 0xc _g_LteaTopIntRegBitMap
- COMMON 0x1017704a 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ 0x10176e02 0x24c _g_TopReg
+ 0x1017704e 0xc _g_LteaTopIntRegBitMap
+ COMMON 0x1017705a 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
0x0 (size before relaxing)
- 0x1017704a 0xa _g_zPHY_emc_tDlDataRecvCtrlInfo
- 0x10177054 0x1 _g_wRLMATQInFlg
- 0x10177055 0x2 _g_sdRLMATQIn
- 0x10177057 0x1 _g_zPHY_emc_wSIDataBufSel
- 0x10177058 0x2 _g_sdRLMATQOut
- 0x1017705a 0x1 _g_wRLMATQOutFlg
- 0x1017705b 0x1e _g_zPHY_emc_tScheduleSiReq
- 0x10177079 0x8 _g_zPHY_emc_tPchDataRecvCtrlInfo
- 0x10177081 0x6 _g_zPHY_emc_tReadSib1Req
- COMMON 0x10177087 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ 0x1017705a 0xa _g_zPHY_emc_tDlDataRecvCtrlInfo
+ 0x10177064 0x1 _g_wRLMATQInFlg
+ 0x10177065 0x2 _g_sdRLMATQIn
+ 0x10177067 0x1 _g_zPHY_emc_wSIDataBufSel
+ 0x10177068 0x2 _g_sdRLMATQOut
+ 0x1017706a 0x1 _g_wRLMATQOutFlg
+ 0x1017706b 0x1e _g_zPHY_emc_tScheduleSiReq
+ 0x10177089 0x8 _g_zPHY_emc_tPchDataRecvCtrlInfo
+ 0x10177091 0x6 _g_zPHY_emc_tReadSib1Req
+ COMMON 0x10177097 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
0x0 (size before relaxing)
- 0x10177087 0x8 _g_zPHY_tLpcPwrCtrlScenExpect
- COMMON 0x1017708f 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ 0x10177097 0x8 _g_zPHY_tLpcPwrCtrlScenExpect
+ COMMON 0x1017709f 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
0x0 (size before relaxing)
- 0x1017708f 0x1 _g_VrbFlag
- COMMON 0x10177090 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ 0x1017709f 0x1 _g_VrbFlag
+ COMMON 0x101770a0 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
0x0 (size before relaxing)
- 0x10177090 0x2 _g_zPHY_erfc_dwConFr40AuxAdcClkBase
- 0x10177092 0x2 _g_dwAptFixVoltageNvSet
- 0x10177094 0x2 _g_zPHY_erfc_dwConFr11_19Xtal
- 0x10177096 0x2 _g_zPHY_erfc_dwConFr24LowRefMode
- 0x10177098 0x2 _g_ACP405_RxPGC1_Word
- 0x1017709a 0x2 _g_ACP405_RxPGC0_Word
- 0x1017709c 0x2 _g_zPHY_erfc_dwConFr33RefClk
- COMMON 0x1017709e 0x28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x101770a0 0x2 _g_zPHY_erfc_dwConFr40AuxAdcClkBase
+ 0x101770a2 0x2 _g_dwAptFixVoltageNvSet
+ 0x101770a4 0x2 _g_zPHY_erfc_dwConFr11_19Xtal
+ 0x101770a6 0x2 _g_zPHY_erfc_dwConFr24LowRefMode
+ 0x101770a8 0x2 _g_ACP405_RxPGC1_Word
+ 0x101770aa 0x2 _g_ACP405_RxPGC0_Word
+ 0x101770ac 0x2 _g_zPHY_erfc_dwConFr33RefClk
+ COMMON 0x101770ae 0x28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
0x0 (size before relaxing)
- 0x1017709e 0x28 _g_a_zPHY_edfe_dwLpcSaveReg
- COMMON 0x101770c6 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ 0x101770ae 0x28 _g_a_zPHY_edfe_dwLpcSaveReg
+ COMMON 0x101770d6 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
0x0 (size before relaxing)
- 0x101770c6 0xa _g_CsrGapInfo
- COMMON 0x101770d0 0x63b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ 0x101770d6 0xa _g_CsrGapInfo
+ COMMON 0x101770e0 0x63b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
0x0 (size before relaxing)
- 0x101770d0 0x1 _g_dwCsrIntraRsrpFilterPrintCnt
- 0x101770d1 0x2 _g_swCsr_Rssi_SearCnf
- 0x101770d3 0x55d _g_zPHY_ecsrc_tFilterInterMeas
- 0x10177630 0x2 _g_swCsr_Rssi_Report
- 0x10177632 0xc4 _g_zPHY_ecsrc_tFilterIntraMeas
- 0x101776f6 0x1 _g_awAgcNoBalance
- 0x101776f7 0x12 _g_zPHY_ecsrc_tFilterFactor
- 0x10177709 0x1 _g_dwCsrInterRsrpFilterPrintCnt
- 0x1017770a 0x1 _g_dwCsrInterRsrpFilterRepPrintCnt
- COMMON 0x1017770b 0x11b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ 0x101770e0 0x1 _g_dwCsrIntraRsrpFilterPrintCnt
+ 0x101770e1 0x2 _g_swCsr_Rssi_SearCnf
+ 0x101770e3 0x55d _g_zPHY_ecsrc_tFilterInterMeas
+ 0x10177640 0x2 _g_swCsr_Rssi_Report
+ 0x10177642 0xc4 _g_zPHY_ecsrc_tFilterIntraMeas
+ 0x10177706 0x1 _g_awAgcNoBalance
+ 0x10177707 0x12 _g_zPHY_ecsrc_tFilterFactor
+ 0x10177719 0x1 _g_dwCsrInterRsrpFilterPrintCnt
+ 0x1017771a 0x1 _g_dwCsrInterRsrpFilterRepPrintCnt
+ COMMON 0x1017771b 0x11b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
0x0 (size before relaxing)
- 0x1017770b 0x78 _g_L1e_dwSirEvtList
- 0x10177783 0x5 _g_l1e_tSirRxRcv
- 0x10177788 0x95 _g_L1e_tSirDb
- 0x1017781d 0x1 _g_zPHY_wSibStartPbchTimes
- 0x1017781e 0x1 _g_L1e_wSibRptDelay
- 0x1017781f 0x6 _g_L1e_tSibCrc
- 0x10177825 0x1 _g_L1e_wSiTimingNeibState
- COMMON 0x10177826 0x3529 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x1017771b 0x78 _g_L1e_dwSirEvtList
+ 0x10177793 0x5 _g_l1e_tSirRxRcv
+ 0x10177798 0x95 _g_L1e_tSirDb
+ 0x1017782d 0x1 _g_zPHY_wSibStartPbchTimes
+ 0x1017782e 0x1 _g_L1e_wSibRptDelay
+ 0x1017782f 0x6 _g_L1e_tSibCrc
+ 0x10177835 0x1 _g_L1e_wSiTimingNeibState
+ COMMON 0x10177836 0x3529 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
0x0 (size before relaxing)
- 0x10177826 0x2ee0 _g_awSyncMsgBuff
- 0x1017a706 0x5 _g_zPHY_tRfRxOffsetCfgInfo
- 0x1017a70b 0x1 _g_zPHY_emc_wSetRfcIdleModeOkCnt
- 0x1017a70c 0x96 _g_zPHY_emc_tCommonConfigReq
- 0x1017a7a2 0x2 _g_zPHY_emc_tMcCtrlParam
- 0x1017a7a4 0x1 _g_zPHY_emc_wSoftResetOkFlag
- 0x1017a7a5 0x2 _g_dwNextX
- 0x1017a7a7 0x1 _g_zPHY_emc_bGapConfigState
- 0x1017a7a8 0x1 _g_wSCellDeactivationTimerParam
- 0x1017a7a9 0x1 _g_zPHY_emc_wReleaseDlDelayCnt
- 0x1017a7aa 0x50 _g_atzPhy_emc_SyncMsgInfo
- 0x1017a7fa 0x1 _g_wPlmnRapcConflictTimer
- 0x1017a7fb 0x1 _g_zPHY_emc_wIsCampOn
- 0x1017a7fc 0x4 _g_zPHY_emc_tTimingCtrlParam
- 0x1017a800 0x4 _g_zPHY_emc_ScellCtrlReq
- 0x1017a804 0x2 _g_dwGapStatue
- 0x1017a806 0x1 _g_zPHY_emc_wUseServeInfoFlag
- 0x1017a807 0x1 _g_zPHY_emc_wReleaseRfcIdleModeOkCnt
- 0x1017a808 0x4 _g_zPHY_emc_tTACtrlParam
- 0x1017a80c 0x2 _g_dwSubFrm
- 0x1017a80e 0x2 _g_dwErrorNum
- 0x1017a810 0x13 _g_zPHY_emc_tDrxSPSCtrlInfo
- 0x1017a823 0x1 _g_ePrePhyState
- 0x1017a824 0x4 _g_awSCellDeactivationTimer
- 0x1017a828 0x412 _g_zPHY_emc_tDedicatedConfigReq
- 0x1017ac3a 0x8 _g_zPHY_emc_tAccessReq
- 0x1017ac42 0x1 _g_zPHY_emc_wCommonMsgDisPathFlag
- 0x1017ac43 0x1 _g_wThinkWill_Flg
- 0x1017ac44 0x50 _g_CellSearchData
- 0x1017ac94 0xd _g_zPHY_emc_tRec_Tpu
- 0x1017aca1 0x1 _g_zPHY_emc_wSetModeOkFlag
- 0x1017aca2 0x84 _g_FreqScanData
- 0x1017ad26 0x2 _g_zPHY_emc_tReleaseCtrlParam
- 0x1017ad28 0x3 _g_zPHY_emc_tRaMsgHoldFlag
- 0x1017ad2b 0x24 _g_L1e_tDlRfcCfgInfo
- COMMON 0x1017ad4f 0x14fa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ 0x10177836 0x2ee0 _g_awSyncMsgBuff
+ 0x1017a716 0x5 _g_zPHY_tRfRxOffsetCfgInfo
+ 0x1017a71b 0x1 _g_zPHY_emc_wSetRfcIdleModeOkCnt
+ 0x1017a71c 0x96 _g_zPHY_emc_tCommonConfigReq
+ 0x1017a7b2 0x2 _g_zPHY_emc_tMcCtrlParam
+ 0x1017a7b4 0x1 _g_zPHY_emc_wSoftResetOkFlag
+ 0x1017a7b5 0x2 _g_dwNextX
+ 0x1017a7b7 0x1 _g_zPHY_emc_bGapConfigState
+ 0x1017a7b8 0x1 _g_wSCellDeactivationTimerParam
+ 0x1017a7b9 0x1 _g_zPHY_emc_wReleaseDlDelayCnt
+ 0x1017a7ba 0x50 _g_atzPhy_emc_SyncMsgInfo
+ 0x1017a80a 0x1 _g_wPlmnRapcConflictTimer
+ 0x1017a80b 0x1 _g_zPHY_emc_wIsCampOn
+ 0x1017a80c 0x4 _g_zPHY_emc_tTimingCtrlParam
+ 0x1017a810 0x4 _g_zPHY_emc_ScellCtrlReq
+ 0x1017a814 0x2 _g_dwGapStatue
+ 0x1017a816 0x1 _g_zPHY_emc_wUseServeInfoFlag
+ 0x1017a817 0x1 _g_zPHY_emc_wReleaseRfcIdleModeOkCnt
+ 0x1017a818 0x4 _g_zPHY_emc_tTACtrlParam
+ 0x1017a81c 0x2 _g_dwSubFrm
+ 0x1017a81e 0x2 _g_dwErrorNum
+ 0x1017a820 0x13 _g_zPHY_emc_tDrxSPSCtrlInfo
+ 0x1017a833 0x1 _g_ePrePhyState
+ 0x1017a834 0x4 _g_awSCellDeactivationTimer
+ 0x1017a838 0x412 _g_zPHY_emc_tDedicatedConfigReq
+ 0x1017ac4a 0x8 _g_zPHY_emc_tAccessReq
+ 0x1017ac52 0x1 _g_zPHY_emc_wCommonMsgDisPathFlag
+ 0x1017ac53 0x1 _g_wThinkWill_Flg
+ 0x1017ac54 0x50 _g_CellSearchData
+ 0x1017aca4 0xd _g_zPHY_emc_tRec_Tpu
+ 0x1017acb1 0x1 _g_zPHY_emc_wSetModeOkFlag
+ 0x1017acb2 0x84 _g_FreqScanData
+ 0x1017ad36 0x2 _g_zPHY_emc_tReleaseCtrlParam
+ 0x1017ad38 0x3 _g_zPHY_emc_tRaMsgHoldFlag
+ 0x1017ad3b 0x24 _g_L1e_tDlRfcCfgInfo
+ COMMON 0x1017ad5f 0x150a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
0x0 (size before relaxing)
- 0x1017ad4f 0x1 _g_zPHY_ecsrc_wGapConfigCsrRecive
- 0x1017ad50 0x1 _g_zPHY_ecsrc_wPiPeriod
- 0x1017ad51 0x8 _g_zPHY_ecsrc_tSearchMeasAgeThrold
- 0x1017ad59 0x2 _g_zPHY_ecsrs_dwTpuAdjTime
- 0x1017ad5b 0x84 _g_zPHY_ecsrc_tFreqScanReq
- 0x1017addf 0x28 _g_zPHY_ecsrc_tCommInfo
- 0x1017ae07 0x3 _g_L1e_Csrc_PreCfo
- 0x1017ae0a 0x39e _g_zPHY_ecsrc_tCsrPsInterMeasInd
- 0x1017b1a8 0x55 _g_L1e_Csrc_C0Update
- 0x1017b1fd 0x6 _g_zPHY_ecsrc_tMeasMaskSetBack
- 0x1017b203 0x50 _g_zPHY_ecsrc_tCellSearchReq
- 0x1017b253 0x1f _g_zPHY_ecsrc_tCnnDrxMeasSchedule
- 0x1017b272 0x6 _g_zPHY_ecsrc_tMeasMaskSetReq
- 0x1017b278 0x82 _g_zPHY_ecsrc_tFreqScanCnf
- 0x1017b2fa 0x4 _g_atAgeTimer
- 0x1017b2fe 0x1 _g_L1e_Csrc_DisFreqScan
- 0x1017b2ff 0x1 _g_zPHY_ecsrc_wScheduleInfoCnt
- 0x1017b300 0x1 _g_L1e_C0ConIntraRptCnt
- 0x1017b301 0x1 _g_L1e_C0ConDrxCnt
- 0x1017b302 0x1 _g_wcsrc_HoOnflag
- 0x1017b303 0x2ae _g_zPHY_ecsrc_tCsrPsIntraMeasInd
- 0x1017b5b1 0x1 _g_zPHY_ecsrc_wWorkInterFreqIndex
- 0x1017b5b2 0x6a7 _g_zPHY_ecsrc_tCsrCellDatabase
- 0x1017bc59 0x9 _g_zPHY_ecsrc_tFliterSchduInd
- 0x1017bc62 0x1 _g_zPHY_wHoStartPbchTimes
- 0x1017bc63 0x2 _g_zPHY_ecsrc_dwCsrcFlag
- 0x1017bc65 0x2 _g_L1e_csrc_tMeasPeriodChgReq
- 0x1017bc67 0x1 _g_zPHY_ecsrc_AferGapFlag
- 0x1017bc68 0x12 _g_zPHY_ecsrc_wDoneInterPerDrx
- 0x1017bc7a 0x5c8 _g_zPHY_ecsrc_tMeasConfigReq
- 0x1017c242 0x2 _g_zPHY_ecsrc_swBackupCFOFreqOffset
- 0x1017c244 0x1 _g_L1e_ConnIntraRptCnt
- 0x1017c245 0x1 _g_zPHY_ecsrs_wCsrsWorkFlag
- 0x1017c246 0x2 _g_L1eTempAdc
- 0x1017c248 0x1 _g_L1e_Csrc_bCellSearchPbch
- COMMON 0x1017c249 0x1c2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_data.o)
+ 0x1017ad5f 0x1 _g_zPHY_ecsrc_wGapConfigCsrRecive
+ 0x1017ad60 0x1 _g_zPHY_ecsrc_wPiPeriod
+ 0x1017ad61 0x8 _g_zPHY_ecsrc_tSearchMeasAgeThrold
+ 0x1017ad69 0x2 _g_zPHY_ecsrs_dwTpuAdjTime
+ 0x1017ad6b 0x84 _g_zPHY_ecsrc_tFreqScanReq
+ 0x1017adef 0x28 _g_zPHY_ecsrc_tCommInfo
+ 0x1017ae17 0x3 _g_L1e_Csrc_PreCfo
+ 0x1017ae1a 0x10 _g_zPHY_ecsrc_tEarfcnTable_B28
+ 0x1017ae2a 0x39e _g_zPHY_ecsrc_tCsrPsInterMeasInd
+ 0x1017b1c8 0x55 _g_L1e_Csrc_C0Update
+ 0x1017b21d 0x6 _g_zPHY_ecsrc_tMeasMaskSetBack
+ 0x1017b223 0x50 _g_zPHY_ecsrc_tCellSearchReq
+ 0x1017b273 0x1f _g_zPHY_ecsrc_tCnnDrxMeasSchedule
+ 0x1017b292 0x6 _g_zPHY_ecsrc_tMeasMaskSetReq
+ 0x1017b298 0x82 _g_zPHY_ecsrc_tFreqScanCnf
+ 0x1017b31a 0x4 _g_atAgeTimer
+ 0x1017b31e 0x1 _g_L1e_Csrc_DisFreqScan
+ 0x1017b31f 0x1 _g_zPHY_ecsrc_wScheduleInfoCnt
+ 0x1017b320 0x1 _g_L1e_C0ConIntraRptCnt
+ 0x1017b321 0x1 _g_L1e_C0ConDrxCnt
+ 0x1017b322 0x1 _g_wcsrc_HoOnflag
+ 0x1017b323 0x2ae _g_zPHY_ecsrc_tCsrPsIntraMeasInd
+ 0x1017b5d1 0x1 _g_zPHY_ecsrc_wWorkInterFreqIndex
+ 0x1017b5d2 0x6a7 _g_zPHY_ecsrc_tCsrCellDatabase
+ 0x1017bc79 0x9 _g_zPHY_ecsrc_tFliterSchduInd
+ 0x1017bc82 0x1 _g_zPHY_wHoStartPbchTimes
+ 0x1017bc83 0x2 _g_zPHY_ecsrc_dwCsrcFlag
+ 0x1017bc85 0x2 _g_L1e_csrc_tMeasPeriodChgReq
+ 0x1017bc87 0x1 _g_zPHY_ecsrc_AferGapFlag
+ 0x1017bc88 0x12 _g_zPHY_ecsrc_wDoneInterPerDrx
+ 0x1017bc9a 0x5c8 _g_zPHY_ecsrc_tMeasConfigReq
+ 0x1017c262 0x2 _g_zPHY_ecsrc_swBackupCFOFreqOffset
+ 0x1017c264 0x1 _g_L1e_ConnIntraRptCnt
+ 0x1017c265 0x1 _g_zPHY_ecsrs_wCsrsWorkFlag
+ 0x1017c266 0x2 _g_L1eTempAdc
+ 0x1017c268 0x1 _g_L1e_Csrc_bCellSearchPbch
+ COMMON 0x1017c269 0x1c2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_data.o)
0x0 (size before relaxing)
- 0x1017c249 0x1c1 _g_aw_RarMacPdu
- 0x1017c40a 0x1 _g_zPHY_swRsrpFilter
- COMMON 0x1017c40b 0x919 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ 0x1017c269 0x1c1 _g_aw_RarMacPdu
+ 0x1017c42a 0x1 _g_zPHY_swRsrpFilter
+ COMMON 0x1017c42b 0x919 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
0x0 (size before relaxing)
- 0x1017c40b 0x8 _g_zPHY_ecsrc_tMulmMeasGapConfigReq
- 0x1017c413 0x134 _g_zPHY_ecsrc_tMulmFreqListConfig
- 0x1017c547 0x8 _g_zPHY_ecsrc_tIratGapConfig
- 0x1017c54f 0x3 _g_tSlaveSearchMeasAgeThrold
- 0x1017c552 0x8 _g_zPHY_ecsrc_tMulmMeasGapConfigReqBackUp
- 0x1017c55a 0x1 _g_zPHY_emulm_PlmnSearchMeasCnt
- 0x1017c55b 0x6 _g_zPHY_emulm_tFilterFactor
- 0x1017c561 0x1 _g_L1e_mulm_NoSatisfyCfoCnt
- 0x1017c562 0x2 _g_zPHY_SetModeReq
- 0x1017c564 0x6 _g_zPHY_ecsrc_tMulmInactiveTimeInd
- 0x1017c56a 0x1a _g_zPHY_emulm_SlaveHwEnable
- 0x1017c584 0x6 _g_zPHY_ecsrc_tMulmIratMeasConfigBackUp
- 0x1017c58a 0x8 _g_zPHY_ecsrc_tIratGapConfig1
- 0x1017c592 0x1 _g_L1e_mulm_40msGapCnt
- 0x1017c593 0x2 _g_zPHY_emulm_tMulmIdlePeriodReqFlag
- 0x1017c595 0x3 _g_zPHY_emulm_tMulmAfcPara
- 0x1017c598 0x165 _g_zPHY_ecsrc_atSlaveMeasInfo
- 0x1017c6fd 0x621 _g_zPHY_emulm_tFilterMeas
- 0x1017cd1e 0x6 _g_zPHY_ecsrc_tMulmIratMeasConfig
- COMMON 0x1017cd24 0x11 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ 0x1017c42b 0x8 _g_zPHY_ecsrc_tMulmMeasGapConfigReq
+ 0x1017c433 0x134 _g_zPHY_ecsrc_tMulmFreqListConfig
+ 0x1017c567 0x8 _g_zPHY_ecsrc_tIratGapConfig
+ 0x1017c56f 0x3 _g_tSlaveSearchMeasAgeThrold
+ 0x1017c572 0x8 _g_zPHY_ecsrc_tMulmMeasGapConfigReqBackUp
+ 0x1017c57a 0x1 _g_zPHY_emulm_PlmnSearchMeasCnt
+ 0x1017c57b 0x6 _g_zPHY_emulm_tFilterFactor
+ 0x1017c581 0x1 _g_L1e_mulm_NoSatisfyCfoCnt
+ 0x1017c582 0x2 _g_zPHY_SetModeReq
+ 0x1017c584 0x6 _g_zPHY_ecsrc_tMulmInactiveTimeInd
+ 0x1017c58a 0x1a _g_zPHY_emulm_SlaveHwEnable
+ 0x1017c5a4 0x6 _g_zPHY_ecsrc_tMulmIratMeasConfigBackUp
+ 0x1017c5aa 0x8 _g_zPHY_ecsrc_tIratGapConfig1
+ 0x1017c5b2 0x1 _g_L1e_mulm_40msGapCnt
+ 0x1017c5b3 0x2 _g_zPHY_emulm_tMulmIdlePeriodReqFlag
+ 0x1017c5b5 0x3 _g_zPHY_emulm_tMulmAfcPara
+ 0x1017c5b8 0x165 _g_zPHY_ecsrc_atSlaveMeasInfo
+ 0x1017c71d 0x621 _g_zPHY_emulm_tFilterMeas
+ 0x1017cd3e 0x6 _g_zPHY_ecsrc_tMulmIratMeasConfig
+ COMMON 0x1017cd44 0x11 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
0x0 (size before relaxing)
- 0x1017cd24 0x11 _g_RxOpenPara
- COMMON 0x1017cd35 0x88 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ 0x1017cd44 0x11 _g_RxOpenPara
+ COMMON 0x1017cd55 0x88 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
0x0 (size before relaxing)
- 0x1017cd35 0x6c _g_zPHY_emc_tDrxCtrlInfo
- 0x1017cda1 0xa _g_wIntTypeforDrx
- 0x1017cdab 0x10 _g_awDrxUlRetranCnt
- 0x1017cdbb 0x2 _g_Next2SubFrameDrxActiveSidFlag
- COMMON 0x1017cdbd 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ 0x1017cd55 0x6c _g_zPHY_emc_tDrxCtrlInfo
+ 0x1017cdc1 0xa _g_wIntTypeforDrx
+ 0x1017cdcb 0x10 _g_awDrxUlRetranCnt
+ 0x1017cddb 0x2 _g_Next2SubFrameDrxActiveSidFlag
+ COMMON 0x1017cddd 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
0x0 (size before relaxing)
- 0x1017cdbd 0x1 _g_wFIUpdate2RLM
- 0x1017cdbe 0xf _g_zPHY_emc_tRadioLinkCtrlInfo
- COMMON 0x1017cdcd 0x198 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ 0x1017cddd 0x1 _g_wFIUpdate2RLM
+ 0x1017cdde 0xf _g_zPHY_emc_tRadioLinkCtrlInfo
+ COMMON 0x1017cded 0x198 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
0x0 (size before relaxing)
- 0x1017cdcd 0x10 _g_tLteAmtCellSyncPara
- 0x1017cddd 0x157 _g_tLteAmtInfo
- 0x1017cf34 0x2 _g_zPHY_AMT_SearchCellCnt
- 0x1017cf36 0x2 _g_zPHY_AMT_Strongest_CellId
- 0x1017cf38 0x1f _gtAmtCellSyncProc
- 0x1017cf57 0x2 _g_zPHY_AMT_Strongest_Rsrp
- 0x1017cf59 0x2 _g_zPHY_AMT_Earfcn
- 0x1017cf5b 0x6 _g_zPHY_AMT_SrvCellRsrp
- 0x1017cf61 0x2 _g_dwFdt10MsCnt
- 0x1017cf63 0x2 _g_zPHY_AMT_Frequency
- COMMON 0x1017cf65 0x48a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ 0x1017cded 0x10 _g_tLteAmtCellSyncPara
+ 0x1017cdfd 0x157 _g_tLteAmtInfo
+ 0x1017cf54 0x2 _g_zPHY_AMT_SearchCellCnt
+ 0x1017cf56 0x2 _g_zPHY_AMT_Strongest_CellId
+ 0x1017cf58 0x1f _gtAmtCellSyncProc
+ 0x1017cf77 0x2 _g_zPHY_AMT_Strongest_Rsrp
+ 0x1017cf79 0x2 _g_zPHY_AMT_Earfcn
+ 0x1017cf7b 0x6 _g_zPHY_AMT_SrvCellRsrp
+ 0x1017cf81 0x2 _g_dwFdt10MsCnt
+ 0x1017cf83 0x2 _g_zPHY_AMT_Frequency
+ COMMON 0x1017cf85 0x48a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
0x0 (size before relaxing)
- 0x1017cf65 0x2 _g_tHandoverCnf
- 0x1017cf67 0x488 _g_tHandoverReq
- COMMON 0x1017d3ef 0x5a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ 0x1017cf85 0x2 _g_tHandoverCnf
+ 0x1017cf87 0x488 _g_tHandoverReq
+ COMMON 0x1017d40f 0x5a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
0x0 (size before relaxing)
- 0x1017d3ef 0xa _g_wIntTypeforPaging
- 0x1017d3f9 0x12 _g_tL1eSchedPreSyncCb
- 0x1017d40b 0x3a _g_tL1eDcxoProcCb
- 0x1017d445 0x2 _g_zPHY_sdwRxAnt0OffsetValue
- 0x1017d447 0x2 _g_zPHY_sdwRxAnt1OffsetValue
- COMMON 0x1017d449 0x248 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x1017d40f 0xa _g_wIntTypeforPaging
+ 0x1017d419 0x12 _g_tL1eSchedPreSyncCb
+ 0x1017d42b 0x3a _g_tL1eDcxoProcCb
+ 0x1017d465 0x2 _g_zPHY_sdwRxAnt0OffsetValue
+ 0x1017d467 0x2 _g_zPHY_sdwRxAnt1OffsetValue
+ COMMON 0x1017d469 0x248 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
0x0 (size before relaxing)
- 0x1017d449 0x23a _g_atzPHY_RFSD
- 0x1017d683 0xa _g_atCsiATCMDInfo
- 0x1017d68d 0x4 _g_zPHY_LteRfWorkSet
- COMMON 0x1017d691 0x18 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ 0x1017d469 0x23a _g_atzPHY_RFSD
+ 0x1017d6a3 0xa _g_atCsiATCMDInfo
+ 0x1017d6ad 0x4 _g_zPHY_LteRfWorkSet
+ COMMON 0x1017d6b1 0x18 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
0x0 (size before relaxing)
- 0x1017d691 0x18 _g_tL1lCallStackInfo
- COMMON 0x1017d6a9 0x90 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ 0x1017d6b1 0x18 _g_tL1lCallStackInfo
+ COMMON 0x1017d6c9 0x90 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
0x0 (size before relaxing)
- 0x1017d6a9 0x48 _g_at_zPHY_NxtHiQuadPosTab
- 0x1017d6f1 0x48 _g_at_zPHY_CurHiQuadPosTab
- COMMON 0x1017d739 0x2e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ 0x1017d6c9 0x48 _g_at_zPHY_NxtHiQuadPosTab
+ 0x1017d711 0x48 _g_at_zPHY_CurHiQuadPosTab
+ COMMON 0x1017d759 0x2e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
0x0 (size before relaxing)
- 0x1017d739 0x1 _g_zPHY_edfe_wNotSyncAGCBegin
- 0x1017d73a 0x1 _g_zPHY_edfe_swMaxAGCMeanPwr1
- 0x1017d73b 0x1 _g_Connect_State_Inter_Freq_Flag
- 0x1017d73c 0x1 _g_wConnectAgcIntCounter
- 0x1017d73d 0x1 _g_zPHY_edfe_LostLock_MAX
- 0x1017d73e 0x1 _g_zPHY_edfe_wFirstInInterFreq
- 0x1017d73f 0x2 _g_wContinGreaterCount
- 0x1017d741 0x1 _g_zPHY_edfe_LostLock_MIN
- 0x1017d742 0x1 _g_zPHY_edfe_ScellActiveState
- 0x1017d743 0x61 _g_zPHY_edfe_FSNewPara
- 0x1017d7a4 0x1e _g_zPHY_edfe_tAgcDagcPara
- 0x1017d7c2 0x1 _g_dwAgcTargetSync
- 0x1017d7c3 0x1 _g_zPHY_edfe_ScellActiveCounter
- 0x1017d7c4 0x2 _g_wContinLessCount
- 0x1017d7c6 0x1 _g_zPHY_edfe_wPrePhyState
- 0x1017d7c7 0x1 _g_wAgcFactLf
- 0x1017d7c8 0x1 _g_zPHY_edfe_swMaxAGCMeanPwr0
- 0x1017d7c9 0x1 _g_zPHY_edfe_wNotSyncAgcIntCnt
- 0x1017d7ca 0xa _g_zPHY_edfe_AgcDagcIntCount
- 0x1017d7d4 0x1 _g_dwAgcAvePowLenSync
- 0x1017d7d5 0x1f0 _g_zPHY_edfe_wAgcDagcGain
- 0x1017d9c5 0x4 _g_zPHY_edfe_tMbsfnAgcInfo
- 0x1017d9c9 0x50 _g_zPHY_edfe_tMbsfnAgcGain
- COMMON 0x1017da19 0xdac T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ 0x1017d759 0x1 _g_zPHY_edfe_wNotSyncAGCBegin
+ 0x1017d75a 0x1 _g_zPHY_edfe_swMaxAGCMeanPwr1
+ 0x1017d75b 0x1 _g_Connect_State_Inter_Freq_Flag
+ 0x1017d75c 0x1 _g_wConnectAgcIntCounter
+ 0x1017d75d 0x1 _g_zPHY_edfe_LostLock_MAX
+ 0x1017d75e 0x1 _g_zPHY_edfe_wFirstInInterFreq
+ 0x1017d75f 0x2 _g_wContinGreaterCount
+ 0x1017d761 0x1 _g_zPHY_edfe_LostLock_MIN
+ 0x1017d762 0x1 _g_zPHY_edfe_ScellActiveState
+ 0x1017d763 0x61 _g_zPHY_edfe_FSNewPara
+ 0x1017d7c4 0x1e _g_zPHY_edfe_tAgcDagcPara
+ 0x1017d7e2 0x1 _g_dwAgcTargetSync
+ 0x1017d7e3 0x1 _g_zPHY_edfe_ScellActiveCounter
+ 0x1017d7e4 0x2 _g_wContinLessCount
+ 0x1017d7e6 0x1 _g_zPHY_edfe_wPrePhyState
+ 0x1017d7e7 0x1 _g_wAgcFactLf
+ 0x1017d7e8 0x1 _g_zPHY_edfe_swMaxAGCMeanPwr0
+ 0x1017d7e9 0x1 _g_zPHY_edfe_wNotSyncAgcIntCnt
+ 0x1017d7ea 0xa _g_zPHY_edfe_AgcDagcIntCount
+ 0x1017d7f4 0x1 _g_dwAgcAvePowLenSync
+ 0x1017d7f5 0x1f0 _g_zPHY_edfe_wAgcDagcGain
+ 0x1017d9e5 0x4 _g_zPHY_edfe_tMbsfnAgcInfo
+ 0x1017d9e9 0x50 _g_zPHY_edfe_tMbsfnAgcGain
+ COMMON 0x1017da39 0xdac T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
0x0 (size before relaxing)
- 0x1017da19 0xd91 _g_tzPHY_ecsrs_FSPara
- 0x1017e7aa 0x4 _g_FS_swMeanPower
- 0x1017e7ae 0x1 _g_tzPHY_ecsrs_FS_RepNum
- 0x1017e7af 0x4 _g_PssContext
- 0x1017e7b3 0x12 _g_tFS_BackUpPssResult
- COMMON 0x1017e7c5 0xd6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ 0x1017da39 0xd91 _g_tzPHY_ecsrs_FSPara
+ 0x1017e7ca 0x4 _g_FS_swMeanPower
+ 0x1017e7ce 0x1 _g_tzPHY_ecsrs_FS_RepNum
+ 0x1017e7cf 0x4 _g_PssContext
+ 0x1017e7d3 0x12 _g_tFS_BackUpPssResult
+ COMMON 0x1017e7e5 0xd6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
0x0 (size before relaxing)
- 0x1017e7c5 0x2 _TotalPuschNackTB0
- 0x1017e7c7 0x2 _TotalPuschNackTB1
- 0x1017e7c9 0x2 _TotalPuschNumTB1
- 0x1017e7cb 0x6 _g_tUlReportBlerInfo
- 0x1017e7d1 0x2 _TotalPuschNumTB0
- 0x1017e7d3 0xc8 _g_adwDebug
- COMMON 0x1017e89b 0x418 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ 0x1017e7e5 0x2 _TotalPuschNackTB0
+ 0x1017e7e7 0x2 _TotalPuschNackTB1
+ 0x1017e7e9 0x2 _TotalPuschNumTB1
+ 0x1017e7eb 0x6 _g_tUlReportBlerInfo
+ 0x1017e7f1 0x2 _TotalPuschNumTB0
+ 0x1017e7f3 0xc8 _g_adwDebug
+ COMMON 0x1017e8bb 0x418 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
0x0 (size before relaxing)
- 0x1017e89b 0x3c8 _g_atEcsrPeakList
- 0x1017ec63 0x50 _g_tPssHwResult
- COMMON 0x1017ecb3 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ 0x1017e8bb 0x3c8 _g_atEcsrPeakList
+ 0x1017ec83 0x50 _g_tPssHwResult
+ COMMON 0x1017ecd3 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
0x0 (size before relaxing)
- 0x1017ecb3 0x4 _g_zPHY_edfe_tPlmnSaveServCellCsrsDagc
- 0x1017ecb7 0x1 _g_swCsrsDagcMeanPower0
- 0x1017ecb8 0x1 _g_zPHY_edfe_wRxLog2Dagc1
- 0x1017ecb9 0x1 _g_zPHY_edfe_wCsrsLog2Dagc1
- 0x1017ecba 0x1 _g_swCsrsDagcMeanPower1
- 0x1017ecbb 0x1 _g_zPHY_edfe_wCsrsLog2Dagc0
- 0x1017ecbc 0x4 _g_zPHY_edfe_tPlmnSaveServCellCsrmDagc
- 0x1017ecc0 0x1 _g_zPHY_edfe_wRxLog2Dagc0
- COMMON 0x1017ecc1 0x8d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+ 0x1017ecd3 0x4 _g_zPHY_edfe_tPlmnSaveServCellCsrsDagc
+ 0x1017ecd7 0x1 _g_swCsrsDagcMeanPower0
+ 0x1017ecd8 0x1 _g_zPHY_edfe_wRxLog2Dagc1
+ 0x1017ecd9 0x1 _g_zPHY_edfe_wCsrsLog2Dagc1
+ 0x1017ecda 0x1 _g_swCsrsDagcMeanPower1
+ 0x1017ecdb 0x1 _g_zPHY_edfe_wCsrsLog2Dagc0
+ 0x1017ecdc 0x4 _g_zPHY_edfe_tPlmnSaveServCellCsrmDagc
+ 0x1017ece0 0x1 _g_zPHY_edfe_wRxLog2Dagc0
+ COMMON 0x1017ece1 0x8d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
0x0 (size before relaxing)
- 0x1017ecc1 0x5f _g_tzPHY_eulpc_PowerCtrlBlock
- 0x1017ed20 0x1 _g_EUL_wPuschPowerHeadroomIdx
- 0x1017ed21 0x1 _g_tzPHY_eulpc_Ulpc2DlParas
- 0x1017ed22 0x13 _g_tzPHY_eulpc_PcmaxInputInfo
- 0x1017ed35 0x6 _g_tzPHY_eulpc_TempPowerBackoffInfo
- 0x1017ed3b 0x13 _g_tzPHY_eulpc_PowerCtrlParas
- COMMON 0x1017ed4e 0x9a4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ 0x1017ece1 0x5f _g_tzPHY_eulpc_PowerCtrlBlock
+ 0x1017ed40 0x1 _g_EUL_wPuschPowerHeadroomIdx
+ 0x1017ed41 0x1 _g_tzPHY_eulpc_Ulpc2DlParas
+ 0x1017ed42 0x13 _g_tzPHY_eulpc_PcmaxInputInfo
+ 0x1017ed55 0x6 _g_tzPHY_eulpc_TempPowerBackoffInfo
+ 0x1017ed5b 0x13 _g_tzPHY_eulpc_PowerCtrlParas
+ COMMON 0x1017ed6e 0x9a4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
0x0 (size before relaxing)
- 0x1017ed4e 0x10f _g_ThreadIntraCs
- 0x1017ee5d 0xf2 _g_atEcsrSearchPeakdatabase
- 0x1017ef4f 0x1 _g_CsContext
- 0x1017ef50 0x10f _g_ThreadFreqScan
- 0x1017f05f 0x60 _g_l1e_tDcxoFtErrorList
- 0x1017f0bf 0x2e6 _g_tEcsrSearchCommonInfor
- 0x1017f3a5 0xa _g_tTddAndFddCommInfo
- 0x1017f3af 0x2 _g_zPHY_ecsrs_dwPssFrameBnd_dbg
- 0x1017f3b1 0x1 _g_eCsrsSynStatus
- 0x1017f3b2 0x4 _g_tEmulmSubFrameIntTable
- 0x1017f3b6 0xe _g_atEcsrReCfoInfo
- 0x1017f3c4 0x1 _g_wSssHwRestartCnt
- 0x1017f3c5 0x10f _g_ThreadCfoCs
- 0x1017f4d4 0x10f _g_ThreadInterCs
- 0x1017f5e3 0x10f _g_ThreadMulmCs
- COMMON 0x1017f6f2 0x11e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ 0x1017ed6e 0x10f _g_ThreadIntraCs
+ 0x1017ee7d 0xf2 _g_atEcsrSearchPeakdatabase
+ 0x1017ef6f 0x1 _g_CsContext
+ 0x1017ef70 0x10f _g_ThreadFreqScan
+ 0x1017f07f 0x60 _g_l1e_tDcxoFtErrorList
+ 0x1017f0df 0x2e6 _g_tEcsrSearchCommonInfor
+ 0x1017f3c5 0xa _g_tTddAndFddCommInfo
+ 0x1017f3cf 0x2 _g_zPHY_ecsrs_dwPssFrameBnd_dbg
+ 0x1017f3d1 0x1 _g_eCsrsSynStatus
+ 0x1017f3d2 0x4 _g_tEmulmSubFrameIntTable
+ 0x1017f3d6 0xe _g_atEcsrReCfoInfo
+ 0x1017f3e4 0x1 _g_wSssHwRestartCnt
+ 0x1017f3e5 0x10f _g_ThreadCfoCs
+ 0x1017f4f4 0x10f _g_ThreadInterCs
+ 0x1017f603 0x10f _g_ThreadMulmCs
+ COMMON 0x1017f712 0x11e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
0x0 (size before relaxing)
- 0x1017f6f2 0x11e _g_CsrDrvCfgInfor
- 0x1017f810 ___bss_end = .
+ 0x1017f712 0x11e _g_CsrDrvCfgInfor
+ 0x1017f830 ___bss_end = .
-.itcm 0x00000000 0x6f60 load address 0x10120000
+.itcm 0x00000000 0x6f58 load address 0x10120000
0x00000000 _itcm_start = .
*(.vectors)
.vectors 0x00000000 0xb8 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
@@ -15140,118 +15156,117 @@
0x00003f94 0xdb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
0x00003f94 0xdb _zPHY_edfe_SupHandleDFESyncInt
.TcmLtePhyCode
- 0x0000406f 0xff T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x0000406f 0xfb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
0x0000406f 0x60 _zPHY_eintc_InthHandler
0x000040cf 0x22 _zPHY_eintc_Inth0Handler
0x000040f1 0x22 _zPHY_eintc_Inth1Handler
0x00004113 0x22 _zPHY_eintc_Inth2Handler
- 0x00004135 0xe _zPHY_eintc_IntTimer1Handler
- 0x00004143 0x2b _zPHY_eintc_ICPHandler
+ 0x00004135 0xa _zPHY_eintc_IntTimer1Handler
+ 0x0000413f 0x2b _zPHY_eintc_ICPHandler
.TcmLtePhyCode
- 0x0000416e 0x1e6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
- 0x0000416e 0x67 _L1l_DevEng_DbgExceptLog
- 0x000041d5 0x24 _L1l_DevEng_DbgInfo
- 0x000041f9 0xc0 _L1l_DevEngDisplay
- 0x000042b9 0x58 _L1l_DevEngLogHeaderUpdate
- 0x00004311 0x43 _L1l_DevEngCopyMem2Dpram
+ 0x0000416a 0x1e6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x0000416a 0x67 _L1l_DevEng_DbgExceptLog
+ 0x000041d1 0x24 _L1l_DevEng_DbgInfo
+ 0x000041f5 0xc0 _L1l_DevEngDisplay
+ 0x000042b5 0x58 _L1l_DevEngLogHeaderUpdate
+ 0x0000430d 0x43 _L1l_DevEngCopyMem2Dpram
.TcmLtePhyCode
- 0x00004354 0x94 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
- 0x00004354 0x94 _zPHY_erfc_SupAGCControl
+ 0x00004350 0x94 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x00004350 0x94 _zPHY_erfc_SupAGCControl
.TcmLtePhyCode
- 0x000043e8 0x1894 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
- 0x000043e8 0x31 _L1e_DevDlsGetDciField
- 0x00004419 0x1bf _L1e_DevDlsDecodeDciF1A
- 0x000045d8 0x1d _L1e_DevDlsGetTpmiFieldSize
- 0x000045f5 0x6b _L1e_DevDlsGetRaType1Info
- 0x00004660 0x26b _L1e_DevDlsDecodeDualCwDci
- 0x000048cb 0x17f _L1e_DevDlsDecodeSLSMDci
- 0x00004a4a 0x176 _zPHY_edls_AdaDecodeDciF1
- 0x00004bc0 0x8e _zPHY_edls_ProDciF2ALayerCfg
- 0x00004c4e 0x59 _zPHY_edls_AdaCalRbStartRbLength
- 0x00004ca7 0x8a _zPHY_edls_AdaRbDmpType1
- 0x00004d31 0x1c2 _zPHY_edls_AdaRbDmpType2Dvrb
- 0x00004ef3 0x8e _zPHY_edls_AdaRbDmpType2Lvrb
- 0x00004f81 0x72 _zPHY_edls_AdaRbDmpType01Ctrl
- 0x00004ff3 0x36 _zPHY_edls_AdaRbDmpType0Bw100Rb
- 0x00005029 0x62 _zPHY_edls_AdaRbDmpType0Bw75Rb
- 0x0000508b 0xb5 _zPHY_edls_AdaRbDmpType0Bw50Rb
- 0x00005140 0xf9 _zPHY_edls_AdaCalTotalREs
- 0x00005239 0x5d _zPHY_edls_CsiRsSfnCal
- 0x00005296 0xde _zPHY_edls_AdaCalOverlapRbNum
- 0x00005374 0x2b8 _zPHY_edls_AdaCalTddFddNcpTbREs
- 0x0000562c 0x10e _zPHY_edls_AdaCalTddFddEcpTbREs
- 0x0000573a 0xc3 _zPHY_edls_AdaCalTddNcpSpeTbREs
- 0x000057fd 0x92 _zPHY_edls_AdaCalTddEcpSpeTbREs
- 0x0000588f 0x79 _zPHY_edls_AdaGetTbTbs
- 0x00005908 0x61 _zPHY_edls_AdaCalTbDecodeParas
- 0x00005969 0x3c _zPHY_edls_AdaCalTbCbNum
- 0x000059a5 0x1c _zPHY_edls_AdaCalTbParaKParaC
- 0x000059c1 0xf0 _zPHY_edls_AdaCalTbParaCEParaE
- 0x00005ab1 0x92 _zPHY_edls_AdaCalTbParaNcbParaK0
- 0x00005b43 0x45 _zPHY_edls_AdaCalTbK0Start
- 0x00005b88 0x85 _zPHY_edls_AdaCalTbK1Start
- 0x00005c0d 0x6f _zPHY_edls_AdaCalTbNcbStart
+ 0x000043e4 0x1894 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ 0x000043e4 0x31 _L1e_DevDlsGetDciField
+ 0x00004415 0x1bf _L1e_DevDlsDecodeDciF1A
+ 0x000045d4 0x1d _L1e_DevDlsGetTpmiFieldSize
+ 0x000045f1 0x6b _L1e_DevDlsGetRaType1Info
+ 0x0000465c 0x26b _L1e_DevDlsDecodeDualCwDci
+ 0x000048c7 0x17f _L1e_DevDlsDecodeSLSMDci
+ 0x00004a46 0x176 _zPHY_edls_AdaDecodeDciF1
+ 0x00004bbc 0x8e _zPHY_edls_ProDciF2ALayerCfg
+ 0x00004c4a 0x59 _zPHY_edls_AdaCalRbStartRbLength
+ 0x00004ca3 0x8a _zPHY_edls_AdaRbDmpType1
+ 0x00004d2d 0x1c2 _zPHY_edls_AdaRbDmpType2Dvrb
+ 0x00004eef 0x8e _zPHY_edls_AdaRbDmpType2Lvrb
+ 0x00004f7d 0x72 _zPHY_edls_AdaRbDmpType01Ctrl
+ 0x00004fef 0x36 _zPHY_edls_AdaRbDmpType0Bw100Rb
+ 0x00005025 0x62 _zPHY_edls_AdaRbDmpType0Bw75Rb
+ 0x00005087 0xb5 _zPHY_edls_AdaRbDmpType0Bw50Rb
+ 0x0000513c 0xf9 _zPHY_edls_AdaCalTotalREs
+ 0x00005235 0x5d _zPHY_edls_CsiRsSfnCal
+ 0x00005292 0xde _zPHY_edls_AdaCalOverlapRbNum
+ 0x00005370 0x2b8 _zPHY_edls_AdaCalTddFddNcpTbREs
+ 0x00005628 0x10e _zPHY_edls_AdaCalTddFddEcpTbREs
+ 0x00005736 0xc3 _zPHY_edls_AdaCalTddNcpSpeTbREs
+ 0x000057f9 0x92 _zPHY_edls_AdaCalTddEcpSpeTbREs
+ 0x0000588b 0x79 _zPHY_edls_AdaGetTbTbs
+ 0x00005904 0x61 _zPHY_edls_AdaCalTbDecodeParas
+ 0x00005965 0x3c _zPHY_edls_AdaCalTbCbNum
+ 0x000059a1 0x1c _zPHY_edls_AdaCalTbParaKParaC
+ 0x000059bd 0xf0 _zPHY_edls_AdaCalTbParaCEParaE
+ 0x00005aad 0x92 _zPHY_edls_AdaCalTbParaNcbParaK0
+ 0x00005b3f 0x45 _zPHY_edls_AdaCalTbK0Start
+ 0x00005b84 0x85 _zPHY_edls_AdaCalTbK1Start
+ 0x00005c09 0x6f _zPHY_edls_AdaCalTbNcbStart
.TcmLtePhyCode
- 0x00005c7c 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
- 0x00005c7c 0x1 _zPHY_DrvTop_IntReg_Clear
+ 0x00005c78 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x00005c78 0x1 _zPHY_DrvTop_IntReg_Clear
.TcmLtePhyCode
- 0x00005c7d 0x15 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
- 0x00005c7d 0x15 _L1L_TpuDrvTpuUnregister
+ 0x00005c79 0x15 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ 0x00005c79 0x15 _L1L_TpuDrvTpuUnregister
.TcmLtePhyCode
- 0x00005c92 0x3f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
- 0x00005c92 0x69 _zPHY_erfc_DrvSubframeEventEn
- 0x00005cfb 0xbb _zPHY_erfc_DrvEventEn
- 0x00005db6 0x174 _zPHY_erfc_DrvWriteEventEnArrayToABBRamHwReg
- 0x00005f2a 0x92 _zPHY_erfc_DrvWriteEventEnArrayToDBBNextRamHwReg
- 0x00005fbc 0x24 _zPHY_erfc_DrvWriteMainEventEnArrayToDBBRamHwReg
- 0x00005fe0 0x1c _zPHY_erfc_DrvWriteTuReg
- 0x00005ffc 0x6 _zPHY_erfc_DrvDisableTuReg
- 0x00006002 0x2c _zPHY_erfc_DrvWriteTuRegMrtr
- 0x0000602e 0x17 _zPHY_erfc_DrvTuRamDisable
- 0x00006045 0x16 _zPHY_erfc_DrvTuRamEnable
- 0x0000605b 0x2b _zPHY_erfc_DrvWriteTuRamData
+ 0x00005c8e 0x3f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x00005c8e 0x69 _zPHY_erfc_DrvSubframeEventEn
+ 0x00005cf7 0xbb _zPHY_erfc_DrvEventEn
+ 0x00005db2 0x174 _zPHY_erfc_DrvWriteEventEnArrayToABBRamHwReg
+ 0x00005f26 0x92 _zPHY_erfc_DrvWriteEventEnArrayToDBBNextRamHwReg
+ 0x00005fb8 0x24 _zPHY_erfc_DrvWriteMainEventEnArrayToDBBRamHwReg
+ 0x00005fdc 0x1c _zPHY_erfc_DrvWriteTuReg
+ 0x00005ff8 0x6 _zPHY_erfc_DrvDisableTuReg
+ 0x00005ffe 0x2c _zPHY_erfc_DrvWriteTuRegMrtr
+ 0x0000602a 0x17 _zPHY_erfc_DrvTuRamDisable
+ 0x00006041 0x16 _zPHY_erfc_DrvTuRamEnable
+ 0x00006057 0x2b _zPHY_erfc_DrvWriteTuRamData
.TcmLtePhyCode
- 0x00006086 0xdc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
- 0x00006086 0x7b _zPHY_erfc_DrvWriteOtherCmdDataToEventTable
- 0x00006101 0x61 _zPHY_erfc_DrvWriteCmdDataToEventTable
+ 0x00006082 0xdc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ 0x00006082 0x7b _zPHY_erfc_DrvWriteOtherCmdDataToEventTable
+ 0x000060fd 0x61 _zPHY_erfc_DrvWriteCmdDataToEventTable
.TcmLtePhyCode
- 0x00006162 0xa9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
- 0x00006162 0xa9 _zPHY_Phy_TdlThreadPriprintf
+ 0x0000615e 0xa9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x0000615e 0xa9 _zPHY_Phy_TdlThreadPriprintf
*(.fasttext)
- .fasttext 0x0000620b 0x242 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_pmi.o)
- 0x0000620b 0xe7 _Asm_Tx2Rx2_NL2_PMICalc
- 0x000062f2 0x85 _Asm_NL1_PMICalc
- 0x00006377 0xd6 _Asm_Tx4Rx2_NL2_PMICalc
- .fasttext 0x0000644d 0x4b4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_ri.o)
- 0x0000644d 0x42 _Asm_SumLOGNoSqrt_RICalc
- 0x0000648f 0x85 _Asm_Tx2Rx2_CL_NL1_RICalc
- 0x00006514 0x105 _Asm_Tx2Rx2_CDD_RICalc
- 0x00006619 0x122 _Asm_Tx4Rx2_CL_NL2_RICalc
- 0x0000673b 0x41 _Asm_Tx4Rx2_CL_NL1_RICalc
- 0x0000677c 0x65 _Asm_Rx2_DIV_RICalc
- 0x000067e1 0x120 _Asm_Tx4Rx2_CDD_RICalc
- .fasttext 0x00006901 0x48a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_cqi.o)
- 0x00006901 0x36 _Asm_CqiSinglePort_TX1_RX1_NL1
- 0x00006937 0x6d _Asm_CqiTransDiver_Common_NL1
- 0x000069a4 0x8d _Asm_CqiSpatiMulti_RX2_NL1
- 0x00006a31 0xf3 _Asm_CqiSpatiMulti_RX2_NL2
- 0x00006b24 0xb0 _Asm_CqiCDD_TX2_RX2_NL2
- 0x00006bd4 0xff _Asm_CqiCDD_TX4_RX2_NL2
- 0x00006cd3 0x41 _ASM_Log2
- 0x00006d14 0x77 _Asm_RLMSNR_Calc
+ .fasttext 0x00006207 0x242 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_pmi.o)
+ 0x00006207 0xe7 _Asm_Tx2Rx2_NL2_PMICalc
+ 0x000062ee 0x85 _Asm_NL1_PMICalc
+ 0x00006373 0xd6 _Asm_Tx4Rx2_NL2_PMICalc
+ .fasttext 0x00006449 0x4b4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_ri.o)
+ 0x00006449 0x42 _Asm_SumLOGNoSqrt_RICalc
+ 0x0000648b 0x85 _Asm_Tx2Rx2_CL_NL1_RICalc
+ 0x00006510 0x105 _Asm_Tx2Rx2_CDD_RICalc
+ 0x00006615 0x122 _Asm_Tx4Rx2_CL_NL2_RICalc
+ 0x00006737 0x41 _Asm_Tx4Rx2_CL_NL1_RICalc
+ 0x00006778 0x65 _Asm_Rx2_DIV_RICalc
+ 0x000067dd 0x120 _Asm_Tx4Rx2_CDD_RICalc
+ .fasttext 0x000068fd 0x48a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_cqi.o)
+ 0x000068fd 0x36 _Asm_CqiSinglePort_TX1_RX1_NL1
+ 0x00006933 0x6d _Asm_CqiTransDiver_Common_NL1
+ 0x000069a0 0x8d _Asm_CqiSpatiMulti_RX2_NL1
+ 0x00006a2d 0xf3 _Asm_CqiSpatiMulti_RX2_NL2
+ 0x00006b20 0xb0 _Asm_CqiCDD_TX2_RX2_NL2
+ 0x00006bd0 0xff _Asm_CqiCDD_TX4_RX2_NL2
+ 0x00006ccf 0x41 _ASM_Log2
+ 0x00006d10 0x77 _Asm_RLMSNR_Calc
*(.LpcCodeTcm)
- .LpcCodeTcm 0x00006d8b 0x4d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
- 0x00006d8b 0x2e _L1_SocLpModeControlCfg
- 0x00006db9 0x1f _L1_SocCpuIdle
- .LpcCodeTcm 0x00006dd8 0x2f T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
- 0x00006dd8 0x2f _L1_CpuEnterIdleMode
- .LpcCodeTcm 0x00006e07 0x105 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_sleep.o)
- 0x00006e07 0x18 _L1_DevSleepCloseIsAbleSleep
- 0x00006e1f 0xed _L1t_DevLpcSleepCheck
+ .LpcCodeTcm 0x00006d87 0x4d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ 0x00006d87 0x2e _L1_SocLpModeControlCfg
+ 0x00006db5 0x1f _L1_SocCpuIdle
+ .LpcCodeTcm 0x00006dd4 0x2f T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ 0x00006dd4 0x2f _L1_CpuEnterIdleMode
+ .LpcCodeTcm 0x00006e03 0x105 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_sleep.o)
+ 0x00006e03 0x18 _L1_DevSleepCloseIsAbleSleep
+ 0x00006e1b 0xed _L1t_DevLpcSleepCheck
*(.save_zsp_reg)
- *fill* 0x00006f0c 0x4 00
- .save_zsp_reg 0x00006f10 0x50 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
- 0x00006f10 0x50 _save_zsp880_reg
+ .save_zsp_reg 0x00006f08 0x50 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+ 0x00006f08 0x50 _save_zsp880_reg
*Cqi_control.o(.text)
*Cqi.o(.text)
*CQI_Period.o(.text)
@@ -15265,7 +15280,7 @@
receive*(.text)
set_pri*(.text)
error*(.text)
- 0x00006f60 _itcm_end = .
+ 0x00006f58 _itcm_end = .
.dtcm 0x00010000 0x6b5a load address 0x10128000
0x00010000 _dtcm_start = .
@@ -16999,7 +17014,7 @@
0x00000001 ___ZSP_G3___ = 0x1
OUTPUT(T:/cp/phy/project/7520_phy_plat_zsp/bin/debug/proj_lte_w_td.out elf32-sdsp)
-.comment 0x00000000 0x5de1
+.comment 0x00000000 0x5ebe
.comment 0x00000000 0x15 /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
.comment 0x00000015 0x3c T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
.comment 0x00000051 0x31 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/dmc_zsp_0x140.o
@@ -17048,363 +17063,364 @@
.comment 0x00000962 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o)
.comment 0x000009a0 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma_reg.o)
.comment 0x000009de 0x31 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(dmc_zsp_0x140_lp.o)
- .comment 0x00000a0f 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor.o)
- .comment 0x00000a3b 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_disableall.o)
- .comment 0x00000a66 0x29 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enable.o)
- .comment 0x00000a90 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enableall.o)
- .comment 0x00000abb 0x29 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_flush.o)
- .comment 0x00000ae4 0x2a C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_loadtcm.o)
- .comment 0x00000b0e 0x2f C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_use_dcfgr_describe.o)
- .comment 0x00000b3d 0x30 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_noncacheable_disable.o)
- .comment 0x00000b6e 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_disableall.o)
- .comment 0x00000b99 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_enableall.o)
- .comment 0x00000bc4 0x29 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_flush.o)
- .comment 0x00000bed 0x2a C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_loadtcm.o)
- .comment 0x00000c17 0x29 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_clean.o)
- .comment 0x00000c40 0x2f C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_setwritethruregion.o)
- .comment 0x00000c70 0x30 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writeallocate_enable.o)
- .comment 0x00000ca0 0x2e C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_enable.o)
- .comment 0x00000ccf 0x2f C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_disable.o)
- .comment 0x00000cfe 0x30 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_noncacheable_enable.o)
- .comment 0x00000d2e 0x32 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_extranoncacheable_enable.o)
- .comment 0x00000d60 0x3e T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1td_init.o)
- .comment 0x00000d9e 0x3f T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_nv_param.o)
- .comment 0x00000ddd 0x48 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hspadldec.o)
- .comment 0x00000e26 0x45 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rfc.o)
- .comment 0x00000e6b 0x46 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_hspa.o)
- .comment 0x00000eb1 0x46 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rtx_rx.o)
- .comment 0x00000ef7 0x45 T:/cp/phy/l1_td/lib/zx297520v3/debug/tdphy.a(l1_dev_rtx.o)
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+ .comment 0x00004cc1 0x42 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
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+ .comment 0x00004e0b 0x43 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ .comment 0x00004e4e 0x40 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_meas.o)
+ .comment 0x00004e8e 0x3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_dls.o)
+ .comment 0x00004eca 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc.o)
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+ .comment 0x00004f88 0x3b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_rx.o)
+ .comment 0x00004fc3 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_mulm.o)
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+ .comment 0x0000503e 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm.o)
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+ .comment 0x00005164 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rx_data.o)
+ .comment 0x000051a1 0x3e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ .comment 0x000051df 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ .comment 0x0000521c 0x3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
+ .comment 0x00005258 0x3b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
+ .comment 0x00005293 0x3f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft_twf.o)
+ .comment 0x000052d2 0x3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ .comment 0x0000530e 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ .comment 0x0000534c 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
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+ .comment 0x00005404 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
+ .comment 0x00005441 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ .comment 0x0000547f 0x3f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
+ .comment 0x000054be 0x3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+ .comment 0x000054fb 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
+ .comment 0x00005538 0x3e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
+ .comment 0x00005576 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
+ .comment 0x000055b3 0x3b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ .comment 0x000055ee 0x3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_ti.o)
+ .comment 0x0000562b 0x39 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ .comment 0x00005664 0x43 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1_ref.o)
+ .comment 0x000056a7 0x3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_fs.o)
+ .comment 0x000056e3 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrs.o)
+ .comment 0x00005721 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_list.o)
+ .comment 0x0000575e 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(crepool.o)
+ .comment 0x00005792 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cresem.o)
+ .comment 0x000057c5 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(current.o)
+ .comment 0x000057f8 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(delay.o)
+ .comment 0x0000582b 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(free.o)
+ .comment 0x0000585d 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(get_pri.o)
+ .comment 0x00005890 0x34 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(getticks.o)
+ .comment 0x000058c4 0x31 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(id.o)
+ .comment 0x000058f5 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(killsem.o)
+ .comment 0x00005929 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(receive.o)
+ .comment 0x0000595c 0x34 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(s_allnil.o)
+ .comment 0x00005990 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sender.o)
+ .comment 0x000059c3 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(set_pri.o)
+ .comment 0x000059f7 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(signsem.o)
+ .comment 0x00005a2a 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(start.o)
+ .comment 0x00005a5d 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o)
+ .comment 0x00005a8f 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(timer.o)
+ .comment 0x00005ac1 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(waitsem.o)
+ .comment 0x00005af5 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o)
+ .comment 0x00005b27 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(restore.o)
+ .comment 0x00005b5a 0x34 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send_w_s.o)
+ .comment 0x00005b8e 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_efuse.o)
+ .comment 0x00005bcc 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcmp.o)
+ .comment 0x00005bf8 0x34 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(sprintf.o)
+ .comment 0x00005c2c 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strchr.o)
+ .comment 0x00005c57 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strcpy.o)
+ .comment 0x00005c83 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strlen.o)
+ .comment 0x00005cae 0x34 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(vsprintf.o)
+ .comment 0x00005ce3 0x2d C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o)
+ .comment 0x00005d10 0x1b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_data.o)
+ .comment 0x00005d2b 0x2a C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(atoi.o)
+ .comment 0x00005d55 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ctype.o)
+ .comment 0x00005d80 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fputc.o)
+ .comment 0x00005dab 0x2e C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fwrite_8bit.o)
+ .comment 0x00005dd9 0x2e C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fputc.o)
+ .comment 0x00005e07 0x31 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fwrite_8bit.o)
+ .comment 0x00005e38 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fflush.o)
+ .comment 0x00005e64 0x2b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(userIO.o)
+ .comment 0x00005e8f 0x2e C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fwrite.o)
-.stab 0x00000000 0x1bf23a
+.stab 0x00000000 0x1bf2e8
.stab 0x00000000 0x22e /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
.stab 0x0000022e 0x486 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
0x48c (size before relaxing)
@@ -17804,341 +17820,341 @@
0x230a (size before relaxing)
.stab 0x000d9146 0x20f4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
0x3288 (size before relaxing)
- .stab 0x000db23a 0x7c20 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas.o)
- 0x9a3e (size before relaxing)
- .stab 0x000e2e5a 0xb04 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa.o)
+ .stab 0x000db23a 0x7c14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas.o)
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+ .stab 0x000e2e4e 0xb04 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa.o)
0x1ee4 (size before relaxing)
- .stab 0x000e395e 0x1da0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+ .stab 0x000e3952 0x1da0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
0x32f4 (size before relaxing)
- .stab 0x000e56fe 0xae6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_sc.o)
+ .stab 0x000e56f2 0xae6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_sc.o)
0x216c (size before relaxing)
- .stab 0x000e61e4 0x28c2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+ .stab 0x000e61d8 0x28c2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
0x3cae (size before relaxing)
- .stab 0x000e8aa6 0x27f0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_bch.o)
+ .stab 0x000e8a9a 0x27f0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_bch.o)
0x4026 (size before relaxing)
- .stab 0x000eb296 0x1764 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_amt.o)
+ .stab 0x000eb28a 0x1764 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_amt.o)
0x3204 (size before relaxing)
- .stab 0x000ec9fa 0x20e2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cs.o)
+ .stab 0x000ec9ee 0x20e2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cs.o)
0x3aaa (size before relaxing)
- .stab 0x000eeadc 0x810 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
+ .stab 0x000eead0 0x810 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
0x2178 (size before relaxing)
- .stab 0x000ef2ec 0x744 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fach.o)
+ .stab 0x000ef2e0 0x744 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fach.o)
0x1d2e (size before relaxing)
- .stab 0x000efa30 0xfde T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_page.o)
+ .stab 0x000efa24 0xfde T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_page.o)
0x28a4 (size before relaxing)
- .stab 0x000f0a0e 0x1878 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_dch.o)
+ .stab 0x000f0a02 0x1878 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_dch.o)
0x2f22 (size before relaxing)
- .stab 0x000f2286 0x846 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_efach.o)
+ .stab 0x000f227a 0x846 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_efach.o)
0x24de (size before relaxing)
- .stab 0x000f2acc 0x1a58 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_gap.o)
+ .stab 0x000f2ac0 0x1a58 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_gap.o)
0x30de (size before relaxing)
- .stab 0x000f4524 0xbee T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o)
+ .stab 0x000f4518 0xbee T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o)
0x2c6a (size before relaxing)
- .stab 0x000f5112 0x618 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa_efach.o)
+ .stab 0x000f5106 0x618 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa_efach.o)
0x1afa (size before relaxing)
- .stab 0x000f572a 0x708 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fmo.o)
+ .stab 0x000f571e 0x708 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fmo.o)
0x1cc2 (size before relaxing)
- .stab 0x000f5e32 0x1884 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
+ .stab 0x000f5e26 0x1884 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
0x2cca (size before relaxing)
- .stab 0x000f76b6 0xc9c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_math.o)
+ .stab 0x000f76aa 0xc9c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_math.o)
0x1512 (size before relaxing)
- .stab 0x000f8352 0x894 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_tx.o)
+ .stab 0x000f8346 0x894 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_tx.o)
0x1b36 (size before relaxing)
- .stab 0x000f8be6 0x50a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_hspa.o)
+ .stab 0x000f8bda 0x50a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_hspa.o)
0x14f4 (size before relaxing)
- .stab 0x000f90f0 0x1ec6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ .stab 0x000f90e4 0x1ec6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
0x3606 (size before relaxing)
- .stab 0x000fafb6 0x25ce T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ .stab 0x000fafaa 0x25ce T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
0x31da (size before relaxing)
- .stab 0x000fd584 0xa6e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_tx.o)
+ .stab 0x000fd578 0xa6e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_tx.o)
0x23f4 (size before relaxing)
- .stab 0x000fdff2 0x2946 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ .stab 0x000fdfe6 0x2946 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
0x437a (size before relaxing)
- .stab 0x00100938 0x708 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ .stab 0x0010092c 0x708 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
0x166e (size before relaxing)
- .stab 0x00101040 0x1a94 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ .stab 0x00101034 0x1a94 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
0x2b38 (size before relaxing)
- .stab 0x00102ad4 0x3a2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ .stab 0x00102ac8 0x3a2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
0xbfa (size before relaxing)
- .stab 0x00102e76 0x19e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_bch.o)
+ .stab 0x00102e6a 0x19e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_bch.o)
0xb0a (size before relaxing)
- .stab 0x00103014 0x1da T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dma.o)
+ .stab 0x00103008 0x1da T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dma.o)
0xb0a (size before relaxing)
- .stab 0x001031ee 0x3c6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_epch.o)
+ .stab 0x001031e2 0x3c6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_epch.o)
0x1e72 (size before relaxing)
- .stab 0x001035b4 0x1422 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
- 0x3630 (size before relaxing)
- .stab 0x001049d6 0x636 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ .stab 0x001035a8 0x1428 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x3636 (size before relaxing)
+ .stab 0x001049d0 0x636 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
0x1c26 (size before relaxing)
- .stab 0x0010500c 0x2652 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ .stab 0x00105006 0x2652 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
0x4638 (size before relaxing)
- .stab 0x0010765e 0x197a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ .stab 0x00107658 0x197a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
0x3e58 (size before relaxing)
- .stab 0x00108fd8 0x1710 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ .stab 0x00108fd2 0x1710 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
0x36a2 (size before relaxing)
- .stab 0x0010a6e8 0x4ea2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ .stab 0x0010a6e2 0x4ea2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
0x53d0 (size before relaxing)
- .stab 0x0010f58a 0x6168 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ .stab 0x0010f584 0x6168 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
0x86d0 (size before relaxing)
- .stab 0x001156f2 0x45ae T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ .stab 0x001156ec 0x45ae T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
0x6e64 (size before relaxing)
- .stab 0x00119ca0 0x5358 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ .stab 0x00119c9a 0x5358 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
0x7476 (size before relaxing)
- .stab 0x0011eff8 0x3ae0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ .stab 0x0011eff2 0x3ae0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
0x5e9e (size before relaxing)
- .stab 0x00122ad8 0x233a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ .stab 0x00122ad2 0x233a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
0x474c (size before relaxing)
- .stab 0x00124e12 0x1f86 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ .stab 0x00124e0c 0x1f86 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
0x3b7c (size before relaxing)
- .stab 0x00126d98 0x7aa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+ .stab 0x00126d92 0x7aa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
0x2238 (size before relaxing)
- .stab 0x00127542 0x375c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ .stab 0x0012753c 0x375c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
0x6444 (size before relaxing)
- .stab 0x0012ac9e 0x4c8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+ .stab 0x0012ac98 0x4c8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
0x24c6 (size before relaxing)
- .stab 0x0012b166 0x2862 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ .stab 0x0012b160 0x2862 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
0x5196 (size before relaxing)
- .stab 0x0012d9c8 0x205e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ .stab 0x0012d9c2 0x205e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
0x4ef6 (size before relaxing)
- .stab 0x0012fa26 0xe10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ .stab 0x0012fa20 0xe10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
0x37ec (size before relaxing)
- .stab 0x00130836 0x32f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ .stab 0x00130830 0x32f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
0x6636 (size before relaxing)
- .stab 0x00133b2a 0xd38 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ .stab 0x00133b24 0xd38 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
0x4080 (size before relaxing)
- .stab 0x00134862 0x9fc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_pmi.o)
+ .stab 0x0013485c 0x9fc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_pmi.o)
0xa02 (size before relaxing)
- .stab 0x0013525e 0x3876 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ .stab 0x00135258 0x3876 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
0x60cc (size before relaxing)
- .stab 0x00138ad4 0xa14 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
+ .stab 0x00138ace 0xa14 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
0xa1a (size before relaxing)
- .stab 0x001394e8 0x1584 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_ri.o)
+ .stab 0x001394e2 0x1584 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_ri.o)
0x158a (size before relaxing)
- .stab 0x0013aa6c 0xb28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ .stab 0x0013aa66 0xb28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
0x4284 (size before relaxing)
- .stab 0x0013b594 0x2ee0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ .stab 0x0013b58e 0x2ee0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
0x6648 (size before relaxing)
- .stab 0x0013e474 0x30a2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ .stab 0x0013e46e 0x30a2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
0x5d8a (size before relaxing)
- .stab 0x00141516 0x3396 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ .stab 0x00141510 0x3396 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
0x561c (size before relaxing)
- .stab 0x001448ac 0x45b4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
+ .stab 0x001448a6 0x45b4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
0x794a (size before relaxing)
- .stab 0x00148e60 0x2208 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
- 0x44dc (size before relaxing)
- .stab 0x0014b068 0x1a3a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
+ .stab 0x00148e5a 0x21fc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x44d0 (size before relaxing)
+ .stab 0x0014b056 0x1a3a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
0x442e (size before relaxing)
- .stab 0x0014caa2 0x732 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ .stab 0x0014ca90 0x732 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
0x1f14 (size before relaxing)
- .stab 0x0014d1d4 0x6a2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o)
+ .stab 0x0014d1c2 0x6a2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o)
0x87c (size before relaxing)
- .stab 0x0014d876 0x1350 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
+ .stab 0x0014d864 0x1350 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
0x3f18 (size before relaxing)
- .stab 0x0014ebc6 0x141c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_cqi.o)
+ .stab 0x0014ebb4 0x141c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_cqi.o)
0x1422 (size before relaxing)
- .stab 0x0014ffe2 0x396 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+ .stab 0x0014ffd0 0x396 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
0x2424 (size before relaxing)
- .stab 0x00150378 0x109e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ .stab 0x00150366 0x109e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
0x3fc0 (size before relaxing)
- .stab 0x00151416 0x3f12 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ .stab 0x00151404 0x3f12 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
0x5d96 (size before relaxing)
- .stab 0x00155328 0x1b72 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ .stab 0x00155316 0x1b72 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
0x4a52 (size before relaxing)
- .stab 0x00156e9a 0x588 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pucch.o)
+ .stab 0x00156e88 0x588 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pucch.o)
0x2d48 (size before relaxing)
- .stab 0x00157422 0x2be T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
+ .stab 0x00157410 0x2be T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
0x636 (size before relaxing)
- .stab 0x001576e0 0xd56 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_ddtr.o)
+ .stab 0x001576ce 0xd56 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_ddtr.o)
0x227a (size before relaxing)
- .stab 0x00158436 0xc24 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ .stab 0x00158424 0xc24 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
0x2e80 (size before relaxing)
- .stab 0x0015905a 0x870 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ .stab 0x00159048 0x870 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
0x2ad2 (size before relaxing)
- .stab 0x001598ca 0xb28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ .stab 0x001598b8 0xb28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
0x369c (size before relaxing)
- .stab 0x0015a3f2 0x1698 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ .stab 0x0015a3e0 0x1698 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
0x3ed6 (size before relaxing)
- .stab 0x0015ba8a 0x1896 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
+ .stab 0x0015ba78 0x1896 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
0x387c (size before relaxing)
- .stab 0x0015d320 0x414 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
+ .stab 0x0015d30e 0x414 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
0x2610 (size before relaxing)
- .stab 0x0015d734 0x2808 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ .stab 0x0015d722 0x2808 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
0x3d2c (size before relaxing)
- .stab 0x0015ff3c 0x8be T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
+ .stab 0x0015ff2a 0x8be T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
0x2814 (size before relaxing)
- .stab 0x001607fa 0x576 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
+ .stab 0x001607e8 0x576 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
0x26be (size before relaxing)
- .stab 0x00160d70 0x1194 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
+ .stab 0x00160d5e 0x1194 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
0x274e (size before relaxing)
- .stab 0x00161f04 0x193e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ .stab 0x00161ef2 0x193e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
0x3d98 (size before relaxing)
- .stab 0x00163842 0x2d7e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ .stab 0x00163830 0x2d7e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
0x5af6 (size before relaxing)
- .stab 0x001665c0 0x7d4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ .stab 0x001665ae 0x7d4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
0x29a6 (size before relaxing)
- .stab 0x00166d94 0x1f5c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ .stab 0x00166d82 0x1f5c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
0x49ce (size before relaxing)
- .stab 0x00168cf0 0x1440 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ .stab 0x00168cde 0x1440 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
0x34a4 (size before relaxing)
- .stab 0x0016a130 0x768 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc.o)
+ .stab 0x0016a11e 0x768 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc.o)
0x3420 (size before relaxing)
- .stab 0x0016a898 0x24f0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ .stab 0x0016a886 0x24f0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
0x597c (size before relaxing)
- .stab 0x0016cd88 0x3c42 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ .stab 0x0016cd76 0x3c42 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
0x6a98 (size before relaxing)
- .stab 0x001709ca 0x6dbc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ .stab 0x001709b8 0x6dbc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
0x99f0 (size before relaxing)
- .stab 0x00177786 0x8160 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
- 0xb66a (size before relaxing)
- .stab 0x0017f8e6 0x11e8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_fsm.o)
+ .stab 0x00177774 0x81f6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ 0xb700 (size before relaxing)
+ .stab 0x0017f96a 0x11e8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_fsm.o)
0x358e (size before relaxing)
- .stab 0x00180ace 0x258 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_data.o)
+ .stab 0x00180b52 0x258 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_data.o)
0x2304 (size before relaxing)
- .stab 0x00180d26 0x19e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_db.o)
+ .stab 0x00180daa 0x19e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_db.o)
0x4dfa (size before relaxing)
- .stab 0x00182706 0x4944 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ .stab 0x0018278a 0x4944 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
0x7488 (size before relaxing)
- .stab 0x0018704a 0x2262 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
- 0x57e4 (size before relaxing)
- .stab 0x001892ac 0x8ca T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
+ .stab 0x001870ce 0x2286 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ 0x5808 (size before relaxing)
+ .stab 0x00189354 0x8ca T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
0xaa4 (size before relaxing)
- .stab 0x00189b76 0x7a4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ .stab 0x00189c1e 0x7a4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
0x1faa (size before relaxing)
- .stab 0x0018a31a 0x2baa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ .stab 0x0018a3c2 0x2baa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
0x536a (size before relaxing)
- .stab 0x0018cec4 0xf90 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ .stab 0x0018cf6c 0xf90 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
0x35be (size before relaxing)
- .stab 0x0018de54 0x42a8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
- 0x768c (size before relaxing)
- .stab 0x001920fc 0x2baa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
+ .stab 0x0018defc 0x42ae T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ 0x7692 (size before relaxing)
+ .stab 0x001921aa 0x2baa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
0x55aa (size before relaxing)
- .stab 0x00194ca6 0x7d4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ .stab 0x00194d54 0x7d4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
0x3d44 (size before relaxing)
- .stab 0x0019547a 0x1db2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ .stab 0x00195528 0x1db2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
0x47dc (size before relaxing)
- .stab 0x0019722c 0xc3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_meas.o)
+ .stab 0x001972da 0xc3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_meas.o)
0x35f4 (size before relaxing)
- .stab 0x00197e68 0x198 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_dls.o)
+ .stab 0x00197f16 0x198 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_dls.o)
0x528 (size before relaxing)
- .stab 0x00198000 0x1098 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc.o)
+ .stab 0x001980ae 0x1098 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc.o)
0x3d20 (size before relaxing)
- .stab 0x00199098 0x59a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm_normal.o)
+ .stab 0x00199146 0x59a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm_normal.o)
0x314a (size before relaxing)
- .stab 0x00199632 0x1062 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_cs.o)
+ .stab 0x001996e0 0x1062 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_cs.o)
0x3d0e (size before relaxing)
- .stab 0x0019a694 0x34e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_rx.o)
+ .stab 0x0019a742 0x34e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_rx.o)
0x6de (size before relaxing)
- .stab 0x0019a9e2 0x1086 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_mulm.o)
+ .stab 0x0019aa90 0x1086 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_mulm.o)
0x3bac (size before relaxing)
- .stab 0x0019ba68 0x1f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_cmn_mbms.o)
+ .stab 0x0019bb16 0x1f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_cmn_mbms.o)
0x198c (size before relaxing)
- .stab 0x0019bc5a 0x52e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm.o)
+ .stab 0x0019bd08 0x52e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm.o)
0x31f8 (size before relaxing)
- .stab 0x0019c188 0x75c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_func.o)
+ .stab 0x0019c236 0x75c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_func.o)
0x1f4a (size before relaxing)
- .stab 0x0019c8e4 0x240 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ .stab 0x0019c992 0x240 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
0x1a28 (size before relaxing)
- .stab 0x0019cb24 0x27c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ .stab 0x0019cbd2 0x27c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
0x1a16 (size before relaxing)
- .stab 0x0019cda0 0x3a3e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_srs.o)
+ .stab 0x0019ce4e 0x3a3e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_srs.o)
0x5c6a (size before relaxing)
- .stab 0x001a07de 0x1a4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rx_data.o)
+ .stab 0x001a088c 0x1a4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rx_data.o)
0x177c (size before relaxing)
- .stab 0x001a0982 0x942 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ .stab 0x001a0a30 0x942 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
0x2d5a (size before relaxing)
- .stab 0x001a12c4 0x28b0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ .stab 0x001a1372 0x28b0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
0x5676 (size before relaxing)
- .stab 0x001a3b74 0x516 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
+ .stab 0x001a3c22 0x516 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
0x259e (size before relaxing)
- .stab 0x001a408a 0x1b2a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
+ .stab 0x001a4138 0x1b2a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
0x4746 (size before relaxing)
- .stab 0x001a5bb4 0x13e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft_twf.o)
+ .stab 0x001a5c62 0x13e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft_twf.o)
0x4b6 (size before relaxing)
- .stab 0x001a5cf2 0x3c78 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ .stab 0x001a5da0 0x3c78 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
0x709e (size before relaxing)
- .stab 0x001a996a 0x4eea T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ .stab 0x001a9a18 0x4eea T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
0x7f9e (size before relaxing)
- .stab 0x001ae854 0x1170 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ .stab 0x001ae902 0x1170 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
0x3fd2 (size before relaxing)
- .stab 0x001af9c4 0x1fe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_data.o)
+ .stab 0x001afa72 0x1fe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_data.o)
0x260a (size before relaxing)
- .stab 0x001afbc2 0x1458 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pusch.o)
+ .stab 0x001afc70 0x1458 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pusch.o)
0x3d98 (size before relaxing)
- .stab 0x001b101a 0xa92 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
+ .stab 0x001b10c8 0xa92 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
0x3216 (size before relaxing)
- .stab 0x001b1aac 0x139e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ .stab 0x001b1b5a 0x139e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
0x3b64 (size before relaxing)
- .stab 0x001b2e4a 0x1278 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
+ .stab 0x001b2ef8 0x1278 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
0x146a (size before relaxing)
- .stab 0x001b40c2 0x270 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+ .stab 0x001b4170 0x270 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
0x22c8 (size before relaxing)
- .stab 0x001b4332 0x840 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
+ .stab 0x001b43e0 0x840 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
0x366c (size before relaxing)
- .stab 0x001b4b72 0x3ae T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
+ .stab 0x001b4c20 0x3ae T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
0x27ba (size before relaxing)
- .stab 0x001b4f20 0x1746 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
+ .stab 0x001b4fce 0x1746 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
0x4602 (size before relaxing)
- .stab 0x001b6666 0x2d60 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ .stab 0x001b6714 0x2d60 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
0x6216 (size before relaxing)
- .stab 0x001b93c6 0xe88 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_ti.o)
+ .stab 0x001b9474 0xe88 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_ti.o)
0x38dc (size before relaxing)
- .stab 0x001ba24e 0xd08 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ .stab 0x001ba2fc 0xd08 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
0x382e (size before relaxing)
- .stab 0x001baf56 0x1fe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1_ref.o)
+ .stab 0x001bb004 0x1fe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1_ref.o)
0x266a (size before relaxing)
- .stab 0x001bb154 0xa14 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_fs.o)
+ .stab 0x001bb202 0xa14 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_fs.o)
0x35fa (size before relaxing)
- .stab 0x001bbb68 0x1026 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrs.o)
+ .stab 0x001bbc16 0x1026 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrs.o)
0x3ba0 (size before relaxing)
- .stab 0x001bcb8e 0x2a0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_list.o)
+ .stab 0x001bcc3c 0x2a0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_list.o)
0x492 (size before relaxing)
- .stab 0x001bce2e 0x1b0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(crepool.o)
+ .stab 0x001bcedc 0x1b0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(crepool.o)
0x324 (size before relaxing)
- .stab 0x001bcfde 0x10e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cresem.o)
+ .stab 0x001bd08c 0x10e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cresem.o)
0x258 (size before relaxing)
- .stab 0x001bd0ec 0xe4 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(current.o)
+ .stab 0x001bd19a 0xe4 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(current.o)
0x22e (size before relaxing)
- .stab 0x001bd1d0 0x186 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(delay.o)
+ .stab 0x001bd27e 0x186 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(delay.o)
0x2d0 (size before relaxing)
- .stab 0x001bd356 0x180 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(free.o)
+ .stab 0x001bd404 0x180 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(free.o)
0x2ca (size before relaxing)
- .stab 0x001bd4d6 0x126 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(get_pri.o)
+ .stab 0x001bd584 0x126 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(get_pri.o)
0x270 (size before relaxing)
- .stab 0x001bd5fc 0xe4 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(getticks.o)
+ .stab 0x001bd6aa 0xe4 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(getticks.o)
0x22e (size before relaxing)
- .stab 0x001bd6e0 0xc0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(id.o)
+ .stab 0x001bd78e 0xc0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(id.o)
0xc6 (size before relaxing)
- .stab 0x001bd7a0 0x13e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(killsem.o)
+ .stab 0x001bd84e 0x13e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(killsem.o)
0x288 (size before relaxing)
- .stab 0x001bd8de 0x1e0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(receive.o)
+ .stab 0x001bd98c 0x1e0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(receive.o)
0x32a (size before relaxing)
- .stab 0x001bdabe 0x216 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(s_allnil.o)
+ .stab 0x001bdb6c 0x216 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(s_allnil.o)
0x360 (size before relaxing)
- .stab 0x001bdcd4 0x10e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sender.o)
+ .stab 0x001bdd82 0x10e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sender.o)
0x258 (size before relaxing)
- .stab 0x001bdde2 0x294 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(set_pri.o)
+ .stab 0x001bde90 0x294 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(set_pri.o)
0x3de (size before relaxing)
- .stab 0x001be076 0x14a T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(signsem.o)
+ .stab 0x001be124 0x14a T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(signsem.o)
0x294 (size before relaxing)
- .stab 0x001be1c0 0x15c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(start.o)
+ .stab 0x001be26e 0x15c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(start.o)
0x2a6 (size before relaxing)
- .stab 0x001be31c 0x480 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o)
+ .stab 0x001be3ca 0x480 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o)
0x5f4 (size before relaxing)
- .stab 0x001be79c 0x1c8 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(timer.o)
+ .stab 0x001be84a 0x1c8 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(timer.o)
0x312 (size before relaxing)
- .stab 0x001be964 0x180 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(waitsem.o)
+ .stab 0x001bea12 0x180 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(waitsem.o)
0x2ca (size before relaxing)
- .stab 0x001beae4 0x288 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o)
+ .stab 0x001beb92 0x288 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o)
0x3fc (size before relaxing)
- .stab 0x001bed6c 0x13e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(restore.o)
+ .stab 0x001bee1a 0x13e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(restore.o)
0x288 (size before relaxing)
- .stab 0x001beeaa 0x1bc T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send_w_s.o)
+ .stab 0x001bef58 0x1bc T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send_w_s.o)
0x306 (size before relaxing)
- .stab 0x001bf066 0x1d4 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_efuse.o)
+ .stab 0x001bf114 0x1d4 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_efuse.o)
0x660 (size before relaxing)
-.stabstr 0x00000000 0x3a93f0
- .stabstr 0x00000000 0x3a93f0 /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+.stabstr 0x00000000 0x3a93f4
+ .stabstr 0x00000000 0x3a93f4 /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
0x0 (size before relaxing)
.dmc_data 0x00000000 0x0
diff --git a/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy_out.7z b/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy_out.7z
index 2d0053a..b80dfcb 100755
--- a/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy_out.7z
+++ b/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy_out.7z
Binary files differ
diff --git a/cp/ps/plat/src/oss/psm/src/psm_297520v3.c b/cp/ps/plat/src/oss/psm/src/psm_297520v3.c
old mode 100644
new mode 100755
index 45ce900..c6d27cc
--- a/cp/ps/plat/src/oss/psm/src/psm_297520v3.c
+++ b/cp/ps/plat/src/oss/psm/src/psm_297520v3.c
@@ -327,6 +327,10 @@
return;
}
#endif
+
+ // ÉèÖÃCAP bypass
+ pow_ApBypassClosePwrDomain(1);
+
//zDrvInt_MaskIrq(TIMER0_INT);
zDrvPow_DisPcuWakeInt();
#if defined(_OS_LINUX) && (defined CONFIG_PM)
diff --git a/mk_T106.sh b/mk_T106.sh
index 145e993..dee3b4f 100644
--- a/mk_T106.sh
+++ b/mk_T106.sh
@@ -10,7 +10,7 @@
cd ../../../../..
cd cap/zx297520v3/
#ln -s ~/T106_downloads/downloads/ ./
-DISTRO=vehicle_dc MACHINE=zx297520v3 source zxic-setup-release.sh -b build-vehicle_dc
+DISTRO=vehicle_dc MACHINE=zx297520v3 SDK=yes source zxic-setup-release.sh -b build-vehicle_dc
bitbake zxic-image && bitbake mkimgsig
cd ${TOP}/allbins/zx297520v3/prj_vehicle/scripts_linux
bash copybin_vehicle_dc.sh
diff --git a/pub/include/infra/pub_debug_info.h b/pub/include/infra/pub_debug_info.h
index 5adb04b..53b1fad 100755
--- a/pub/include/infra/pub_debug_info.h
+++ b/pub/include/infra/pub_debug_info.h
@@ -33,7 +33,7 @@
#define MODULE_ID_CAP_TSC (402)
#define MODULE_ID_CAP_PSM (403)
#define MODULE_ID_CAP_NAND (404)
-
+#define MODULE_ID_CAP_SPI (405)
#define MODULE_ID_CAP_DRIVES_END (500)
#define MODULE_ID_AP_FS_START (501)