Merge "[Feature][ZXW-52][ETH]jy3103 PHY Support ping external network"
diff --git a/cap/zx297520v3/sources/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf b/cap/zx297520v3/sources/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf
index f4036e7..e1ad73d 100755
--- a/cap/zx297520v3/sources/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf
+++ b/cap/zx297520v3/sources/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf
@@ -40,7 +40,7 @@
DISTRO_FEATURES_append=" selinux "
# 默认是强制模式 enforcing ，调试建议采用宽容模式 permissive
-DEFAULT_ENFORCING = "enforcing"
+DEFAULT_ENFORCING = "permissive"
# selinux 策略
PREFERRED_PROVIDER_virtual/refpolicy ?= "refpolicy-mls"
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/arch/arm/boot/dts/zx297520v3.dtsi b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/arch/arm/boot/dts/zx297520v3.dtsi
index 3a19b4f..94587cb 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/arch/arm/boot/dts/zx297520v3.dtsi
+++ b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/arch/arm/boot/dts/zx297520v3.dtsi
@@ -351,6 +351,9 @@
<GIC_SPI UART0_RXD_INT IRQ_TYPE_EDGE_FALLING>;
clocks = <&clkc UART0_WCLK>, <&clkc UART0_PCLK>;
clock-names = "uartclk", "apb_pclk";
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start*/
+ uart-max-bus-freq = <104000000>;
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end*/
status = "disabled";
};
@@ -372,6 +375,9 @@
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "uart2_tx_rx";
pinctrl-0 = <&uart2_pins>;
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start*/
+ uart-max-bus-freq = <104000000>;
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end*/
status = "disabled";
};
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/tty/serial/zx29_uart.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/tty/serial/zx29_uart.c
index f199d9c..26f5d98 100755
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/tty/serial/zx29_uart.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/drivers/tty/serial/zx29_uart.c
@@ -3235,7 +3235,9 @@
unsigned int offset=(unsigned int)(pdev->id);
struct device_node *np = pdev->dev.of_node;
unsigned int baud, ibrd, fbrd;
-
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start*/
+ unsigned int max_bus_clk;
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end*/
struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
//struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -3259,6 +3261,12 @@
printk("failed to get zx29_port->wclk: %d\n", ret);
return ret;
}
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start*/
+ if(0 == pdev->id || 2 == pdev->id){
+ device_property_read_u32(&pdev->dev, "uart-max-bus-freq", &max_bus_clk);
+ clk_set_rate(zx29_port->wclk, max_bus_clk);
+ }
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end*/
if(offset == 0){
clk_set_rate(zx29_port->wclk, 104 * 1000000);
}
@@ -3288,6 +3296,11 @@
//here is temple def
if(port->uartclk == 0){
printk("---zx29_init_ports, uartclk hard set to 26M\n");
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start*/
+ if(0 == pdev->id || 2 == pdev->id)
+ port->uartclk = 104000000;
+ else
+ /*cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end*/
port->uartclk = 26000000;
}
printk("---zx29_init_ports, line:%d, irq:%d, membase:%08x, uartclk:%d\n", port->line, port->irq, port->membase, port->uartclk);
diff --git a/update_version.sh b/update_version.sh
index 97552c8..e99f7ef 100644
--- a/update_version.sh
+++ b/update_version.sh
@@ -1,8 +1,8 @@
#!/bin/bash
#export LYNQ_VERSION="T106_lynq_version_ap_build_sh"
-LYNQ_AP_VERSION="T106CN-ZS03.V2.01.01.02P50.AP.07.00"
-LYNQ_CAP_INSIDE_VERSION="CAP.07.00"
-LYNQ_CAP_VERSION="CAP.07.00"
+LYNQ_AP_VERSION="T106CN-ZS03.V2.01.01.02P50.AP.07.01"
+LYNQ_CAP_INSIDE_VERSION="CAP.07.01"
+LYNQ_CAP_VERSION="CAP.07.01"
COMMIT_ID="$(git rev-parse HEAD)"
LYNQ_SW_INSIDE_VERSION="LYNQ_CONFIG_VERSION = \"${LYNQ_AP_VERSION}_${LYNQ_CAP_INSIDE_VERSION}\""