[Feature][ZXW-65]merged P49 base code
Change-Id: I3e09c0c3d47483bc645f02310380ecb7fc6f4041
diff --git a/boot/common/src/loader/drivers/efuse.c b/boot/common/src/loader/drivers/efuse.c
index 0aa6bf8..c4dc051 100644
--- a/boot/common/src/loader/drivers/efuse.c
+++ b/boot/common/src/loader/drivers/efuse.c
@@ -46,7 +46,8 @@
{
ddr_flag = CHIP_DDR_64M;
}
- else if((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOSC_GW_NYC_2G_DDR)
+ else if(((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOSC_GW_NYC_2G_DDR)
+ ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOGG_GW_NYC_2G_DDR))
{
ddr_flag = CHIP_DDR_256M;
}
diff --git a/boot/common/src/loader/drivers/efuse.h b/boot/common/src/loader/drivers/efuse.h
index 7a891a1..7089952 100644
--- a/boot/common/src/loader/drivers/efuse.h
+++ b/boot/common/src/loader/drivers/efuse.h
@@ -18,6 +18,7 @@
#define CHIP_DDR_64M 1
#define CHIP_DDR_128M 2
#define CHIP_DDR_256M 3
+#define CHIP_DDR_512M 4
#define SECURE_VERIFY_ENABLE 0
@@ -39,6 +40,9 @@
#define ZX297520V3ECOSC_GW_NYC_1G_DDR 0xF8630f
#define ZX297520V3ECOSC_GW_UNILC_1G_DDR 0xF86310
#define ZX297520V3ECOSC_GW_NYC_2G_DDR 0xF86311
+#define ZX297520V3ECOSCC_GW_NYB_4G_DDR 0xF86313
+#define ZX297520V3ECOGG_GW_NYC_2G_DDR 0xF86314
+#define ZX297520V3ECOGG_GW_NYB_4G_DDR 0xF86315
#define ZX297520V3_ZW_NYB_1G_DDR 0x1E871E
#define ZX297520V3_ZW_NYC_1G_DDR 0x1E871F
diff --git a/boot/common/src/loader/drivers/spifc.c b/boot/common/src/loader/drivers/spifc.c
index 5fe3fce..61ea186 100755
--- a/boot/common/src/loader/drivers/spifc.c
+++ b/boot/common/src/loader/drivers/spifc.c
@@ -75,6 +75,8 @@
{0x2C, 0x25, 0x77, 2048, 11, 128, 17, 2048, 0x20000, 2},
/* ESMT F50D44G41XB (2X) 512MB SPI-NAND*/
{0x2C, 0x35, 0x77, 4096, 12, 256, 18, 2048, 0x40000, 1},
+ /*XTX XT26Q04D 512M SPI-NAND*/
+ {0x0B, 0x53, 0x77, 4096, 12, 256, 18, 2048, 0x40000, 1},
{0}
};
diff --git a/boot/common/src/loader/include/ddr.h b/boot/common/src/loader/include/ddr.h
index 07bf118..09a6e4c 100644
--- a/boot/common/src/loader/include/ddr.h
+++ b/boot/common/src/loader/include/ddr.h
@@ -64,6 +64,7 @@
#define CHIP_DDR_IS_64M 1
#define CHIP_DDR_IS_128M 2
#define CHIP_DDR_IS_256M 3
+#define CHIP_DDR_IS_512M 4
int ddr_init(int flag);