[Feature][ZXW-265]merge P56U03 version
Only Configure: No
Affected branch: master
Affected module: unknow
Is it affected on both ZXIC and MTK: only ZXIC
Self-test: Yes
Doc Update: No
Change-Id: I873f6df64e2605a77b8b8bfec35b21e7f33c5444
diff --git a/ap/libc/glibc/glibc-2.23/sysdeps/arm/armv7/multiarch/memcpy_impl.S b/ap/libc/glibc/glibc-2.23/sysdeps/arm/armv7/multiarch/memcpy_impl.S
old mode 100644
new mode 100755
index a1f6266..ee562e8
--- a/ap/libc/glibc/glibc-2.23/sysdeps/arm/armv7/multiarch/memcpy_impl.S
+++ b/ap/libc/glibc/glibc-2.23/sysdeps/arm/armv7/multiarch/memcpy_impl.S
@@ -1,5 +1,5 @@
/* NEON/VFP/ARM version of memcpy optimized for Cortex-A15.
- Copyright (C) 2013-2016 Free Software Foundation, Inc.
+ Copyright (C) 2013-2021 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -14,7 +14,7 @@
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>.
+ <https://www.gnu.org/licenses/>.
This memcpy routine is optimised for Cortex-A15 cores and takes advantage
of VFP or NEON when built with the appropriate flags.
@@ -226,71 +226,40 @@
#ifdef USE_VFP
.macro cpy_line_vfp vreg, base
- sfi_breg dst, \
- vstr \vreg, [\B, #\base]
- sfi_breg src, \
- vldr \vreg, [\B, #\base]
- sfi_breg dst, \
- vstr d0, [\B, #\base + 8]
- sfi_breg src, \
- vldr d0, [\B, #\base + 8]
- sfi_breg dst, \
- vstr d1, [\B, #\base + 16]
- sfi_breg src, \
- vldr d1, [\B, #\base + 16]
- sfi_breg dst, \
- vstr d2, [\B, #\base + 24]
- sfi_breg src, \
- vldr d2, [\B, #\base + 24]
- sfi_breg dst, \
- vstr \vreg, [\B, #\base + 32]
- sfi_breg src, \
- vldr \vreg, [\B, #\base + prefetch_lines * 64 - 32]
- sfi_breg dst, \
- vstr d0, [\B, #\base + 40]
- sfi_breg src, \
- vldr d0, [\B, #\base + 40]
- sfi_breg dst, \
- vstr d1, [\B, #\base + 48]
- sfi_breg src, \
- vldr d1, [\B, #\base + 48]
- sfi_breg dst, \
- vstr d2, [\B, #\base + 56]
- sfi_breg src, \
- vldr d2, [\B, #\base + 56]
+ vstr \vreg, [dst, #\base]
+ vldr \vreg, [src, #\base]
+ vstr d0, [dst, #\base + 8]
+ vldr d0, [src, #\base + 8]
+ vstr d1, [dst, #\base + 16]
+ vldr d1, [src, #\base + 16]
+ vstr d2, [dst, #\base + 24]
+ vldr d2, [src, #\base + 24]
+ vstr \vreg, [dst, #\base + 32]
+ vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
+ vstr d0, [dst, #\base + 40]
+ vldr d0, [src, #\base + 40]
+ vstr d1, [dst, #\base + 48]
+ vldr d1, [src, #\base + 48]
+ vstr d2, [dst, #\base + 56]
+ vldr d2, [src, #\base + 56]
.endm
.macro cpy_tail_vfp vreg, base
- sfi_breg dst, \
- vstr \vreg, [\B, #\base]
- sfi_breg src, \
- vldr \vreg, [\B, #\base]
- sfi_breg dst, \
- vstr d0, [\B, #\base + 8]
- sfi_breg src, \
- vldr d0, [\B, #\base + 8]
- sfi_breg dst, \
- vstr d1, [\B, #\base + 16]
- sfi_breg src, \
- vldr d1, [\B, #\base + 16]
- sfi_breg dst, \
- vstr d2, [\B, #\base + 24]
- sfi_breg src, \
- vldr d2, [\B, #\base + 24]
- sfi_breg dst, \
- vstr \vreg, [\B, #\base + 32]
- sfi_breg dst, \
- vstr d0, [\B, #\base + 40]
- sfi_breg src, \
- vldr d0, [\B, #\base + 40]
- sfi_breg dst, \
- vstr d1, [\B, #\base + 48]
- sfi_breg src, \
- vldr d1, [\B, #\base + 48]
- sfi_breg dst, \
- vstr d2, [\B, #\base + 56]
- sfi_breg src, \
- vldr d2, [\B, #\base + 56]
+ vstr \vreg, [dst, #\base]
+ vldr \vreg, [src, #\base]
+ vstr d0, [dst, #\base + 8]
+ vldr d0, [src, #\base + 8]
+ vstr d1, [dst, #\base + 16]
+ vldr d1, [src, #\base + 16]
+ vstr d2, [dst, #\base + 24]
+ vldr d2, [src, #\base + 24]
+ vstr \vreg, [dst, #\base + 32]
+ vstr d0, [dst, #\base + 40]
+ vldr d0, [src, #\base + 40]
+ vstr d1, [dst, #\base + 48]
+ vldr d1, [src, #\base + 48]
+ vstr d2, [dst, #\base + 56]
+ vldr d2, [src, #\base + 56]
.endm
#endif
@@ -299,7 +268,7 @@
mov dst, dstin /* Preserve dstin, we need to return it. */
cmp count, #64
- bge .Lcpy_not_short
+ bhs .Lcpy_not_short
/* Deal with small copies quickly by dropping straight into the
exit block. */
@@ -307,7 +276,7 @@
#ifdef USE_NEON
/* These need an extra layer of macro just to work around a
bug in the assembler's parser when an operand starts with
- a {...}. http://sourceware.org/bugzilla/show_bug.cgi?id=15647
+ a {...}. https://sourceware.org/bugzilla/show_bug.cgi?id=15647
tracks that bug; it was not fixed as of binutils-2.23.2. */
.macro neon_load_d0 reg
vld1.8 {d0}, [\reg]!
@@ -316,26 +285,16 @@
vst1.8 {d0}, [\reg]!
.endm
- /* These are used by the NaCl sfi_breg macro. */
- .macro _sfi_breg_dmask_neon_load_d0 reg
- _sfi_dmask \reg
- .endm
- .macro _sfi_breg_dmask_neon_store_d0 reg
- _sfi_dmask \reg
- .endm
-
and tmp1, count, #0x38
.macro dispatch_step i
- sfi_breg src, neon_load_d0 \B
- sfi_breg dst, neon_store_d0 \B
+ neon_load_d0 src
+ neon_store_d0 dst
.endm
dispatch_7_dword
tst count, #4
- sfi_breg src, \
- ldrne tmp1, [\B], #4
- sfi_breg dst, \
- strne tmp1, [\B], #4
+ ldrne tmp1, [src], #4
+ strne tmp1, [dst], #4
#else
/* Copy up to 15 full words of data. May not be aligned. */
/* Cannot use VFP for unaligned data. */
@@ -344,23 +303,17 @@
add src, src, tmp1
/* Jump directly into the sequence below at the correct offset. */
.macro dispatch_step i
- sfi_breg src, \
- ldr tmp1, [\B, #-(\i * 4)]
- sfi_breg dst, \
- str tmp1, [\B, #-(\i * 4)]
+ ldr tmp1, [src, #-(\i * 4)]
+ str tmp1, [dst, #-(\i * 4)]
.endm
dispatch_15_word
#endif
lsls count, count, #31
- sfi_breg src, \
- ldrhcs tmp1, [\B], #2
- sfi_breg src, \
- ldrbne src, [\B] /* Src is dead, use as a scratch. */
- sfi_breg dst, \
- strhcs tmp1, [\B], #2
- sfi_breg dst, \
- strbne src, [\B]
+ ldrhcs tmp1, [src], #2
+ ldrbne src, [src] /* Src is dead, use as a scratch. */
+ strhcs tmp1, [dst], #2
+ strbne src, [dst]
bx lr
.Lcpy_not_short:
@@ -388,66 +341,44 @@
beq 1f
rsbs tmp2, tmp2, #0
sub count, count, tmp2, lsr #29
- sfi_breg src, \
- ldrmi tmp1, [\B], #4
- sfi_breg dst, \
- strmi tmp1, [\B], #4
+ ldrmi tmp1, [src], #4
+ strmi tmp1, [dst], #4
lsls tmp2, tmp2, #2
- sfi_breg src, \
- ldrhcs tmp1, [\B], #2
- sfi_breg src, \
- ldrbne tmp2, [\B], #1
- sfi_breg dst, \
- strhcs tmp1, [\B], #2
- sfi_breg dst, \
- strbne tmp2, [\B], #1
+ ldrhcs tmp1, [src], #2
+ ldrbne tmp2, [src], #1
+ strhcs tmp1, [dst], #2
+ strbne tmp2, [dst], #1
1:
subs tmp2, count, #64 /* Use tmp2 for count. */
- blt .Ltail63aligned
+ blo .Ltail63aligned
cmp tmp2, #512
- bge .Lcpy_body_long
+ bhs .Lcpy_body_long
.Lcpy_body_medium: /* Count in tmp2. */
#ifdef USE_VFP
1:
- sfi_breg src, \
- vldr d0, [\B, #0]
+ vldr d0, [src, #0]
subs tmp2, tmp2, #64
- sfi_breg src, \
- vldr d1, [\B, #8]
- sfi_breg dst, \
- vstr d0, [\B, #0]
- sfi_breg src, \
- vldr d0, [\B, #16]
- sfi_breg dst, \
- vstr d1, [\B, #8]
- sfi_breg src, \
- vldr d1, [\B, #24]
- sfi_breg dst, \
- vstr d0, [\B, #16]
- sfi_breg src, \
- vldr d0, [\B, #32]
- sfi_breg dst, \
- vstr d1, [\B, #24]
- sfi_breg src, \
- vldr d1, [\B, #40]
- sfi_breg dst, \
- vstr d0, [\B, #32]
- sfi_breg src, \
- vldr d0, [\B, #48]
- sfi_breg dst, \
- vstr d1, [\B, #40]
- sfi_breg src, \
- vldr d1, [\B, #56]
- sfi_breg dst, \
- vstr d0, [\B, #48]
+ vldr d1, [src, #8]
+ vstr d0, [dst, #0]
+ vldr d0, [src, #16]
+ vstr d1, [dst, #8]
+ vldr d1, [src, #24]
+ vstr d0, [dst, #16]
+ vldr d0, [src, #32]
+ vstr d1, [dst, #24]
+ vldr d1, [src, #40]
+ vstr d0, [dst, #32]
+ vldr d0, [src, #48]
+ vstr d1, [dst, #40]
+ vldr d1, [src, #56]
+ vstr d0, [dst, #48]
add src, src, #64
- sfi_breg dst, \
- vstr d1, [\B, #56]
+ vstr d1, [dst, #56]
add dst, dst, #64
- bge 1b
+ bhs 1b
tst tmp2, #0x3f
beq .Ldone
@@ -456,50 +387,32 @@
add dst, dst, tmp1
add src, src, tmp1
.macro dispatch_step i
- sfi_breg src, \
- vldr d0, [\B, #-(\i * 8)]
- sfi_breg dst, \
- vstr d0, [\B, #-(\i * 8)]
+ vldr d0, [src, #-(\i * 8)]
+ vstr d0, [dst, #-(\i * 8)]
.endm
dispatch_7_dword
#else
sub src, src, #8
sub dst, dst, #8
1:
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #8]
- sfi_breg dst, \
- strd A_l, A_h, [\B, #8]
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #16]
- sfi_breg dst, \
- strd A_l, A_h, [\B, #16]
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #24]
- sfi_breg dst, \
- strd A_l, A_h, [\B, #24]
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #32]
- sfi_breg dst, \
- strd A_l, A_h, [\B, #32]
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #40]
- sfi_breg dst, \
- strd A_l, A_h, [\B, #40]
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #48]
- sfi_breg dst, \
- strd A_l, A_h, [\B, #48]
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #56]
- sfi_breg dst, \
- strd A_l, A_h, [\B, #56]
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #64]!
- sfi_breg dst, \
- strd A_l, A_h, [\B, #64]!
+ ldrd A_l, A_h, [src, #8]
+ strd A_l, A_h, [dst, #8]
+ ldrd A_l, A_h, [src, #16]
+ strd A_l, A_h, [dst, #16]
+ ldrd A_l, A_h, [src, #24]
+ strd A_l, A_h, [dst, #24]
+ ldrd A_l, A_h, [src, #32]
+ strd A_l, A_h, [dst, #32]
+ ldrd A_l, A_h, [src, #40]
+ strd A_l, A_h, [dst, #40]
+ ldrd A_l, A_h, [src, #48]
+ strd A_l, A_h, [dst, #48]
+ ldrd A_l, A_h, [src, #56]
+ strd A_l, A_h, [dst, #56]
+ ldrd A_l, A_h, [src, #64]!
+ strd A_l, A_h, [dst, #64]!
subs tmp2, tmp2, #64
- bge 1b
+ bhs 1b
tst tmp2, #0x3f
bne 1f
ldr tmp2,[sp], #FRAME_SIZE
@@ -524,28 +437,20 @@
add dst, dst, tmp1
add src, src, tmp1
.macro dispatch_step i
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #-(\i * 8)]
- sfi_breg dst, \
- strd A_l, A_h, [\B, #-(\i * 8)]
+ ldrd A_l, A_h, [src, #-(\i * 8)]
+ strd A_l, A_h, [dst, #-(\i * 8)]
.endm
dispatch_7_dword
#endif
tst tmp2, #4
- sfi_breg src, \
- ldrne tmp1, [\B], #4
- sfi_breg dst, \
- strne tmp1, [\B], #4
+ ldrne tmp1, [src], #4
+ strne tmp1, [dst], #4
lsls tmp2, tmp2, #31 /* Count (tmp2) now dead. */
- sfi_breg src, \
- ldrhcs tmp1, [\B], #2
- sfi_breg src, \
- ldrbne tmp2, [\B]
- sfi_breg dst, \
- strhcs tmp1, [\B], #2
- sfi_breg dst, \
- strbne tmp2, [\B]
+ ldrhcs tmp1, [src], #2
+ ldrbne tmp2, [src]
+ strhcs tmp1, [dst], #2
+ strbne tmp2, [dst]
.Ldone:
ldr tmp2, [sp], #FRAME_SIZE
@@ -565,27 +470,19 @@
copy position into a register. This should act like a PLD
operation but we won't have to repeat the transfer. */
- sfi_breg src, \
- vldr d3, [\B, #0]
- sfi_breg src, \
- vldr d4, [\B, #64]
- sfi_breg src, \
- vldr d5, [\B, #128]
- sfi_breg src, \
- vldr d6, [\B, #192]
- sfi_breg src, \
- vldr d7, [\B, #256]
+ vldr d3, [src, #0]
+ vldr d4, [src, #64]
+ vldr d5, [src, #128]
+ vldr d6, [src, #192]
+ vldr d7, [src, #256]
- sfi_breg src, \
- vldr d0, [\B, #8]
- sfi_breg src, \
- vldr d1, [\B, #16]
- sfi_breg src, \
- vldr d2, [\B, #24]
+ vldr d0, [src, #8]
+ vldr d1, [src, #16]
+ vldr d2, [src, #24]
add src, src, #32
subs tmp2, tmp2, #prefetch_lines * 64 * 2
- blt 2f
+ blo 2f
1:
cpy_line_vfp d3, 0
cpy_line_vfp d4, 64
@@ -597,7 +494,7 @@
add dst, dst, #2 * 64
add src, src, #2 * 64
subs tmp2, tmp2, #prefetch_lines * 64
- bge 1b
+ bhs 1b
2:
cpy_tail_vfp d3, 0
@@ -606,31 +503,19 @@
add src, src, #3 * 64
add dst, dst, #3 * 64
cpy_tail_vfp d6, 0
- sfi_breg dst, \
- vstr d7, [\B, #64]
- sfi_breg src, \
- vldr d7, [\B, #64]
- sfi_breg dst, \
- vstr d0, [\B, #64 + 8]
- sfi_breg src, \
- vldr d0, [\B, #64 + 8]
- sfi_breg dst, \
- vstr d1, [\B, #64 + 16]
- sfi_breg src, \
- vldr d1, [\B, #64 + 16]
- sfi_breg dst, \
- vstr d2, [\B, #64 + 24]
- sfi_breg src, \
- vldr d2, [\B, #64 + 24]
- sfi_breg dst, \
- vstr d7, [\B, #64 + 32]
+ vstr d7, [dst, #64]
+ vldr d7, [src, #64]
+ vstr d0, [dst, #64 + 8]
+ vldr d0, [src, #64 + 8]
+ vstr d1, [dst, #64 + 16]
+ vldr d1, [src, #64 + 16]
+ vstr d2, [dst, #64 + 24]
+ vldr d2, [src, #64 + 24]
+ vstr d7, [dst, #64 + 32]
add src, src, #96
- sfi_breg dst, \
- vstr d0, [\B, #64 + 40]
- sfi_breg dst, \
- vstr d1, [\B, #64 + 48]
- sfi_breg dst, \
- vstr d2, [\B, #64 + 56]
+ vstr d0, [dst, #64 + 40]
+ vstr d1, [dst, #64 + 48]
+ vstr d2, [dst, #64 + 56]
add dst, dst, #128
add tmp2, tmp2, #prefetch_lines * 64
b .Lcpy_body_medium
@@ -641,83 +526,59 @@
/* Pre-bias src and dst. */
sub src, src, #8
sub dst, dst, #8
- sfi_pld src, #8
- sfi_pld src, #72
+ pld [src, #8]
+ pld [src, #72]
subs tmp2, tmp2, #64
- sfi_pld src, #136
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #8]
+ pld [src, #136]
+ ldrd A_l, A_h, [src, #8]
strd B_l, B_h, [sp, #8]
cfi_rel_offset (B_l, 8)
cfi_rel_offset (B_h, 12)
- sfi_breg src, \
- ldrd B_l, B_h, [\B, #16]
+ ldrd B_l, B_h, [src, #16]
strd C_l, C_h, [sp, #16]
cfi_rel_offset (C_l, 16)
cfi_rel_offset (C_h, 20)
- sfi_breg src, \
- ldrd C_l, C_h, [\B, #24]
+ ldrd C_l, C_h, [src, #24]
strd D_l, D_h, [sp, #24]
cfi_rel_offset (D_l, 24)
cfi_rel_offset (D_h, 28)
- sfi_pld src, #200
- sfi_breg src, \
- ldrd D_l, D_h, [\B, #32]!
+ pld [src, #200]
+ ldrd D_l, D_h, [src, #32]!
b 1f
.p2align 6
2:
- sfi_pld src, #232
- sfi_breg dst, \
- strd A_l, A_h, [\B, #40]
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #40]
- sfi_breg dst, \
- strd B_l, B_h, [\B, #48]
- sfi_breg src, \
- ldrd B_l, B_h, [\B, #48]
- sfi_breg dst, \
- strd C_l, C_h, [\B, #56]
- sfi_breg src, \
- ldrd C_l, C_h, [\B, #56]
- sfi_breg dst, \
- strd D_l, D_h, [\B, #64]!
- sfi_breg src, \
- ldrd D_l, D_h, [\B, #64]!
+ pld [src, #232]
+ strd A_l, A_h, [dst, #40]
+ ldrd A_l, A_h, [src, #40]
+ strd B_l, B_h, [dst, #48]
+ ldrd B_l, B_h, [src, #48]
+ strd C_l, C_h, [dst, #56]
+ ldrd C_l, C_h, [src, #56]
+ strd D_l, D_h, [dst, #64]!
+ ldrd D_l, D_h, [src, #64]!
subs tmp2, tmp2, #64
1:
- sfi_breg dst, \
- strd A_l, A_h, [\B, #8]
- sfi_breg src, \
- ldrd A_l, A_h, [\B, #8]
- sfi_breg dst, \
- strd B_l, B_h, [\B, #16]
- sfi_breg src, \
- ldrd B_l, B_h, [\B, #16]
- sfi_breg dst, \
- strd C_l, C_h, [\B, #24]
- sfi_breg src, \
- ldrd C_l, C_h, [\B, #24]
- sfi_breg dst, \
- strd D_l, D_h, [\B, #32]
- sfi_breg src, \
- ldrd D_l, D_h, [\B, #32]
+ strd A_l, A_h, [dst, #8]
+ ldrd A_l, A_h, [src, #8]
+ strd B_l, B_h, [dst, #16]
+ ldrd B_l, B_h, [src, #16]
+ strd C_l, C_h, [dst, #24]
+ ldrd C_l, C_h, [src, #24]
+ strd D_l, D_h, [dst, #32]
+ ldrd D_l, D_h, [src, #32]
bcs 2b
/* Save the remaining bytes and restore the callee-saved regs. */
- sfi_breg dst, \
- strd A_l, A_h, [\B, #40]
+ strd A_l, A_h, [dst, #40]
add src, src, #40
- sfi_breg dst, \
- strd B_l, B_h, [\B, #48]
+ strd B_l, B_h, [dst, #48]
ldrd B_l, B_h, [sp, #8]
cfi_restore (B_l)
cfi_restore (B_h)
- sfi_breg dst, \
- strd C_l, C_h, [\B, #56]
+ strd C_l, C_h, [dst, #56]
ldrd C_l, C_h, [sp, #16]
cfi_restore (C_l)
cfi_restore (C_h)
- sfi_breg dst, \
- strd D_l, D_h, [\B, #64]
+ strd D_l, D_h, [dst, #64]
ldrd D_l, D_h, [sp, #24]
cfi_restore (D_l)
cfi_restore (D_h)
@@ -734,35 +595,29 @@
cfi_remember_state
.Lcpy_notaligned:
- sfi_pld src
- sfi_pld src, #64
+ pld [src, #0]
+ pld [src, #64]
/* There's at least 64 bytes to copy, but there is no mutual
alignment. */
/* Bring DST to 64-bit alignment. */
lsls tmp2, dst, #29
- sfi_pld src, #(2 * 64)
+ pld [src, #(2 * 64)]
beq 1f
rsbs tmp2, tmp2, #0
sub count, count, tmp2, lsr #29
- sfi_breg src, \
- ldrmi tmp1, [\B], #4
- sfi_breg dst, \
- strmi tmp1, [\B], #4
+ ldrmi tmp1, [src], #4
+ strmi tmp1, [dst], #4
lsls tmp2, tmp2, #2
- sfi_breg src, \
- ldrbne tmp1, [\B], #1
- sfi_breg src, \
- ldrhcs tmp2, [\B], #2
- sfi_breg dst, \
- strbne tmp1, [\B], #1
- sfi_breg dst, \
- strhcs tmp2, [\B], #2
+ ldrbne tmp1, [src], #1
+ ldrhcs tmp2, [src], #2
+ strbne tmp1, [dst], #1
+ strhcs tmp2, [dst], #2
1:
- sfi_pld src, #(3 * 64)
+ pld [src, #(3 * 64)]
subs count, count, #64
- ldrmi tmp2, [sp], #FRAME_SIZE
- bmi .Ltail63unaligned
- sfi_pld src, #(4 * 64)
+ ldrlo tmp2, [sp], #FRAME_SIZE
+ blo .Ltail63unaligned
+ pld [src, #(4 * 64)]
#ifdef USE_NEON
/* These need an extra layer of macro just to work around a
@@ -775,132 +630,88 @@
vst1.8 {\reglist}, [ALIGN (\basereg, 64)]!
.endm
- /* These are used by the NaCl sfi_breg macro. */
- .macro _sfi_breg_dmask_neon_load_multi reg
- _sfi_dmask \reg
- .endm
- .macro _sfi_breg_dmask_neon_store_multi reg
- _sfi_dmask \reg
- .endm
-
- sfi_breg src, neon_load_multi d0-d3, \B
- sfi_breg src, neon_load_multi d4-d7, \B
+ neon_load_multi d0-d3, src
+ neon_load_multi d4-d7, src
subs count, count, #64
- bmi 2f
+ blo 2f
1:
- sfi_pld src, #(4 * 64)
- sfi_breg dst, neon_store_multi d0-d3, \B
- sfi_breg src, neon_load_multi d0-d3, \B
- sfi_breg dst, neon_store_multi d4-d7, \B
- sfi_breg src, neon_load_multi d4-d7, \B
+ pld [src, #(4 * 64)]
+ neon_store_multi d0-d3, dst
+ neon_load_multi d0-d3, src
+ neon_store_multi d4-d7, dst
+ neon_load_multi d4-d7, src
subs count, count, #64
- bpl 1b
+ bhs 1b
2:
- sfi_breg dst, neon_store_multi d0-d3, \B
- sfi_breg dst, neon_store_multi d4-d7, \B
+ neon_store_multi d0-d3, dst
+ neon_store_multi d4-d7, dst
ands count, count, #0x3f
#else
/* Use an SMS style loop to maximize the I/O bandwidth. */
sub src, src, #4
sub dst, dst, #8
subs tmp2, count, #64 /* Use tmp2 for count. */
- sfi_breg src, \
- ldr A_l, [\B, #4]
- sfi_breg src, \
- ldr A_h, [\B, #8]
+ ldr A_l, [src, #4]
+ ldr A_h, [src, #8]
strd B_l, B_h, [sp, #8]
cfi_rel_offset (B_l, 8)
cfi_rel_offset (B_h, 12)
- sfi_breg src, \
- ldr B_l, [\B, #12]
- sfi_breg src, \
- ldr B_h, [\B, #16]
+ ldr B_l, [src, #12]
+ ldr B_h, [src, #16]
strd C_l, C_h, [sp, #16]
cfi_rel_offset (C_l, 16)
cfi_rel_offset (C_h, 20)
- sfi_breg src, \
- ldr C_l, [\B, #20]
- sfi_breg src, \
- ldr C_h, [\B, #24]
+ ldr C_l, [src, #20]
+ ldr C_h, [src, #24]
strd D_l, D_h, [sp, #24]
cfi_rel_offset (D_l, 24)
cfi_rel_offset (D_h, 28)
- sfi_breg src, \
- ldr D_l, [\B, #28]
- sfi_breg src, \
- ldr D_h, [\B, #32]!
+ ldr D_l, [src, #28]
+ ldr D_h, [src, #32]!
b 1f
.p2align 6
2:
- sfi_pld src, #(5 * 64) - (32 - 4)
- sfi_breg dst, \
- strd A_l, A_h, [\B, #40]
- sfi_breg src, \
- ldr A_l, [\B, #36]
- sfi_breg src, \
- ldr A_h, [\B, #40]
- sfi_breg dst, \
- strd B_l, B_h, [\B, #48]
- sfi_breg src, \
- ldr B_l, [\B, #44]
- sfi_breg src, \
- ldr B_h, [\B, #48]
- sfi_breg dst, \
- strd C_l, C_h, [\B, #56]
- sfi_breg src, \
- ldr C_l, [\B, #52]
- sfi_breg src, \
- ldr C_h, [\B, #56]
- sfi_breg dst, \
- strd D_l, D_h, [\B, #64]!
- sfi_breg src, \
- ldr D_l, [\B, #60]
- sfi_breg src, \
- ldr D_h, [\B, #64]!
+ pld [src, #(5 * 64) - (32 - 4)]
+ strd A_l, A_h, [dst, #40]
+ ldr A_l, [src, #36]
+ ldr A_h, [src, #40]
+ strd B_l, B_h, [dst, #48]
+ ldr B_l, [src, #44]
+ ldr B_h, [src, #48]
+ strd C_l, C_h, [dst, #56]
+ ldr C_l, [src, #52]
+ ldr C_h, [src, #56]
+ strd D_l, D_h, [dst, #64]!
+ ldr D_l, [src, #60]
+ ldr D_h, [src, #64]!
subs tmp2, tmp2, #64
1:
- sfi_breg dst, \
- strd A_l, A_h, [\B, #8]
- sfi_breg src, \
- ldr A_l, [\B, #4]
- sfi_breg src, \
- ldr A_h, [\B, #8]
- sfi_breg dst, \
- strd B_l, B_h, [\B, #16]
- sfi_breg src, \
- ldr B_l, [\B, #12]
- sfi_breg src, \
- ldr B_h, [\B, #16]
- sfi_breg dst, \
- strd C_l, C_h, [\B, #24]
- sfi_breg src, \
- ldr C_l, [\B, #20]
- sfi_breg src, \
- ldr C_h, [\B, #24]
- sfi_breg dst, \
- strd D_l, D_h, [\B, #32]
- sfi_breg src, \
- ldr D_l, [\B, #28]
- sfi_breg src, \
- ldr D_h, [\B, #32]
+ strd A_l, A_h, [dst, #8]
+ ldr A_l, [src, #4]
+ ldr A_h, [src, #8]
+ strd B_l, B_h, [dst, #16]
+ ldr B_l, [src, #12]
+ ldr B_h, [src, #16]
+ strd C_l, C_h, [dst, #24]
+ ldr C_l, [src, #20]
+ ldr C_h, [src, #24]
+ strd D_l, D_h, [dst, #32]
+ ldr D_l, [src, #28]
+ ldr D_h, [src, #32]
bcs 2b
/* Save the remaining bytes and restore the callee-saved regs. */
- sfi_breg dst, \
- strd A_l, A_h, [\B, #40]
+ strd A_l, A_h, [dst, #40]
add src, src, #36
- sfi_breg dst, \
- strd B_l, B_h, [\B, #48]
+ strd B_l, B_h, [dst, #48]
ldrd B_l, B_h, [sp, #8]
cfi_restore (B_l)
cfi_restore (B_h)
- sfi_breg dst, \
- strd C_l, C_h, [\B, #56]
+ strd C_l, C_h, [dst, #56]
ldrd C_l, C_h, [sp, #16]
cfi_restore (C_l)
cfi_restore (C_h)
- sfi_breg dst, \
- strd D_l, D_h, [\B, #64]
+ strd D_l, D_h, [dst, #64]
ldrd D_l, D_h, [sp, #24]
cfi_restore (D_l)
cfi_restore (D_h)
diff --git a/ap/libc/glibc/glibc-2.23/sysdeps/arm/memcpy.S b/ap/libc/glibc/glibc-2.23/sysdeps/arm/memcpy.S
old mode 100644
new mode 100755
index db8ba50..04e3f77
--- a/ap/libc/glibc/glibc-2.23/sysdeps/arm/memcpy.S
+++ b/ap/libc/glibc/glibc-2.23/sysdeps/arm/memcpy.S
@@ -1,4 +1,4 @@
-/* Copyright (C) 2006-2016 Free Software Foundation, Inc.
+/* Copyright (C) 2006-2021 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by MontaVista Software, Inc. (written by Nicolas Pitre)
@@ -15,7 +15,7 @@
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
+ <https://www.gnu.org/licenses/>. */
/* Thumb requires excessive IT insns here. */
#define NO_THUMB
@@ -68,9 +68,9 @@
cfi_remember_state
subs r2, r2, #4
- blt 8f
+ blo 8f
ands ip, r0, #3
- PLD( sfi_pld r1, #0 )
+ PLD( pld [r1, #0] )
bne 9f
ands ip, r1, #3
bne 10f
@@ -82,7 +82,7 @@
cfi_rel_offset (r6, 4)
cfi_rel_offset (r7, 8)
cfi_rel_offset (r8, 12)
- blt 5f
+ blo 5f
CALGN( ands ip, r1, #31 )
CALGN( rsb r3, ip, #32 )
@@ -97,22 +97,18 @@
CALGN( bx r4 )
#endif
- PLD( sfi_pld r1, #0 )
-2: PLD( subs r2, r2, #96 )
- PLD( sfi_pld r1, #28 )
- PLD( blt 4f )
- PLD( sfi_pld r1, #60 )
- PLD( sfi_pld r1, #92 )
+ PLD( pld [r1, #0] )
+2: PLD( cmp r2, #96 )
+ PLD( pld [r1, #28] )
+ PLD( blo 4f )
+ PLD( pld [r1, #60] )
+ PLD( pld [r1, #92] )
-3: PLD( sfi_pld r1, #124 )
-4: sfi_breg r1, \
- ldmia \B!, {r3, r4, r5, r6, r7, r8, ip, lr}
+3: PLD( pld [r1, #124] )
+4: ldmia r1!, {r3, r4, r5, r6, r7, r8, ip, lr}
subs r2, r2, #32
- sfi_breg r0, \
- stmia \B!, {r3, r4, r5, r6, r7, r8, ip, lr}
- bge 3b
- PLD( cmn r2, #96 )
- PLD( bge 4b )
+ stmia r0!, {r3, r4, r5, r6, r7, r8, ip, lr}
+ bhs 3b
5: ands ip, r2, #28
rsb ip, ip, #32
@@ -136,26 +132,19 @@
.p2align ARM_BX_ALIGN_LOG2
6: nop
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r3, [\B], #4
+ ldr r3, [r1], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r4, [\B], #4
+ ldr r4, [r1], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r5, [\B], #4
+ ldr r5, [r1], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r6, [\B], #4
+ ldr r6, [r1], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r7, [\B], #4
+ ldr r7, [r1], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r8, [\B], #4
+ ldr r8, [r1], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr lr, [\B], #4
+ ldr lr, [r1], #4
#ifndef ARM_ALWAYS_BX
add pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
@@ -172,26 +161,19 @@
.p2align ARM_BX_ALIGN_LOG2
66: nop
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r3, [\B], #4
+ str r3, [r0], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r4, [\B], #4
+ str r4, [r0], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r5, [\B], #4
+ str r5, [r0], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r6, [\B], #4
+ str r6, [r0], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r7, [\B], #4
+ str r7, [r0], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r8, [\B], #4
+ str r8, [r0], #4
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str lr, [\B], #4
+ str lr, [r0], #4
#ifdef ARM_ALWAYS_BX
pop {r10}
@@ -209,18 +191,12 @@
cfi_restore (r8)
8: movs r2, r2, lsl #31
- sfi_breg r1, \
- ldrbne r3, [\B], #1
- sfi_breg r1, \
- ldrbcs r4, [\B], #1
- sfi_breg r1, \
- ldrbcs ip, [\B]
- sfi_breg r0, \
- strbne r3, [\B], #1
- sfi_breg r0, \
- strbcs r4, [\B], #1
- sfi_breg r0, \
- strbcs ip, [\B]
+ ldrbne r3, [r1], #1
+ ldrbcs r4, [r1], #1
+ ldrbcs ip, [r1]
+ strbne r3, [r0], #1
+ strbcs r4, [r0], #1
+ strbcs ip, [r0]
#if ((defined (__ARM_ARCH_4T__) && defined(__THUMB_INTERWORK__)) \
|| defined (ARM_ALWAYS_BX))
@@ -237,27 +213,20 @@
9: rsb ip, ip, #4
cmp ip, #2
- sfi_breg r1, \
- ldrbgt r3, [\B], #1
- sfi_breg r1, \
- ldrbge r4, [\B], #1
- sfi_breg r1, \
- ldrb lr, [\B], #1
- sfi_breg r0, \
- strbgt r3, [\B], #1
- sfi_breg r0, \
- strbge r4, [\B], #1
+ ldrbgt r3, [r1], #1
+ ldrbge r4, [r1], #1
+ ldrb lr, [r1], #1
+ strbgt r3, [r0], #1
+ strbge r4, [r0], #1
subs r2, r2, ip
- sfi_breg r0, \
- strb lr, [\B], #1
- blt 8b
+ strb lr, [r0], #1
+ blo 8b
ands ip, r1, #3
beq 1b
10: bic r1, r1, #3
cmp ip, #2
- sfi_breg r1, \
- ldr lr, [\B], #4
+ ldr lr, [r1], #4
beq 17f
bgt 18f
@@ -265,7 +234,7 @@
.macro forward_copy_shift pull push
subs r2, r2, #28
- blt 14f
+ blo 14f
CALGN( ands ip, r1, #31 )
CALGN( rsb ip, ip, #32 )
@@ -281,20 +250,18 @@
cfi_rel_offset (r8, 12)
cfi_rel_offset (r10, 16)
- PLD( sfi_pld r1, #0 )
- PLD( subs r2, r2, #96 )
- PLD( sfi_pld r1, #28 )
- PLD( blt 13f )
- PLD( sfi_pld r1, #60 )
- PLD( sfi_pld r1, #92 )
+ PLD( pld [r1, #0] )
+ PLD( cmp r2, #96 )
+ PLD( pld [r1, #28] )
+ PLD( blo 13f )
+ PLD( pld [r1, #60] )
+ PLD( pld [r1, #92] )
-12: PLD( sfi_pld r1, #124 )
-13: sfi_breg r1, \
- ldmia \B!, {r4, r5, r6, r7}
+12: PLD( pld [r1, #124] )
+13: ldmia r1!, {r4, r5, r6, r7}
mov r3, lr, PULL #\pull
subs r2, r2, #32
- sfi_breg r1, \
- ldmia \B!, {r8, r10, ip, lr}
+ ldmia r1!, {r8, r10, ip, lr}
orr r3, r3, r4, PUSH #\push
mov r4, r4, PULL #\pull
orr r4, r4, r5, PUSH #\push
@@ -310,11 +277,8 @@
orr r10, r10, ip, PUSH #\push
mov ip, ip, PULL #\pull
orr ip, ip, lr, PUSH #\push
- sfi_breg r0, \
- stmia \B!, {r3, r4, r5, r6, r7, r8, r10, ip}
- bge 12b
- PLD( cmn r2, #96 )
- PLD( bge 13b )
+ stmia r0!, {r3, r4, r5, r6, r7, r8, r10, ip}
+ bhs 12b
pop {r5 - r8, r10}
cfi_adjust_cfa_offset (-20)
@@ -328,12 +292,10 @@
beq 16f
15: mov r3, lr, PULL #\pull
- sfi_breg r1, \
- ldr lr, [\B], #4
+ ldr lr, [r1], #4
subs ip, ip, #4
orr r3, r3, lr, PUSH #\push
- sfi_breg r0, \
- str r3, [\B], #4
+ str r3, [r0], #4
bgt 15b
CALGN( cmp r2, #0 )
CALGN( bge 11b )
diff --git a/ap/libc/glibc/glibc-2.23/sysdeps/arm/memmove.S b/ap/libc/glibc/glibc-2.23/sysdeps/arm/memmove.S
old mode 100644
new mode 100755
index 96b2366..b01164a
--- a/ap/libc/glibc/glibc-2.23/sysdeps/arm/memmove.S
+++ b/ap/libc/glibc/glibc-2.23/sysdeps/arm/memmove.S
@@ -1,4 +1,4 @@
-/* Copyright (C) 2006-2016 Free Software Foundation, Inc.
+/* Copyright (C) 2006-2021 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by MontaVista Software, Inc. (written by Nicolas Pitre)
@@ -15,7 +15,7 @@
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
+ <https://www.gnu.org/licenses/>. */
/* Thumb requires excessive IT insns here. */
#define NO_THUMB
@@ -85,9 +85,9 @@
add r1, r1, r2
add r0, r0, r2
subs r2, r2, #4
- blt 8f
+ blo 8f
ands ip, r0, #3
- PLD( sfi_pld r1, #-4 )
+ PLD( pld [r1, #-4] )
bne 9f
ands ip, r1, #3
bne 10f
@@ -99,7 +99,7 @@
cfi_rel_offset (r6, 4)
cfi_rel_offset (r7, 8)
cfi_rel_offset (r8, 12)
- blt 5f
+ blo 5f
CALGN( ands ip, r1, #31 )
CALGN( sbcsne r4, ip, r2 ) @ C is always set here
@@ -113,22 +113,18 @@
CALGN( bx r4 )
#endif
- PLD( sfi_pld r1, #-4 )
-2: PLD( subs r2, r2, #96 )
- PLD( sfi_pld r1, #-32 )
- PLD( blt 4f )
- PLD( sfi_pld r1, #-64 )
- PLD( sfi_pld r1, #-96 )
+ PLD( pld [r1, #-4] )
+2: PLD( cmp r2, #96 )
+ PLD( pld [r1, #-32] )
+ PLD( blo 4f )
+ PLD( pld [r1, #-64] )
+ PLD( pld [r1, #-96] )
-3: PLD( sfi_pld r1, #-128 )
-4: sfi_breg r1, \
- ldmdb \B!, {r3, r4, r5, r6, r7, r8, ip, lr}
+3: PLD( pld [r1, #-128] )
+4: ldmdb r1!, {r3, r4, r5, r6, r7, r8, ip, lr}
subs r2, r2, #32
- sfi_breg r0, \
- stmdb \B!, {r3, r4, r5, r6, r7, r8, ip, lr}
- bge 3b
- PLD( cmn r2, #96 )
- PLD( bge 4b )
+ stmdb r0!, {r3, r4, r5, r6, r7, r8, ip, lr}
+ bhs 3b
5: ands ip, r2, #28
rsb ip, ip, #32
@@ -152,26 +148,19 @@
.p2align ARM_BX_ALIGN_LOG2
6: nop
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r3, [\B, #-4]!
+ ldr r3, [r1, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r4, [\B, #-4]!
+ ldr r4, [r1, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r5, [\B, #-4]!
+ ldr r5, [r1, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r6, [\B, #-4]!
+ ldr r6, [r1, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r7, [\B, #-4]!
+ ldr r7, [r1, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr r8, [\B, #-4]!
+ ldr r8, [r1, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r1, \
- ldr lr, [\B, #-4]!
+ ldr lr, [r1, #-4]!
#ifndef ARM_ALWAYS_BX
add pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
@@ -188,26 +177,19 @@
.p2align ARM_BX_ALIGN_LOG2
66: nop
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r3, [\B, #-4]!
+ str r3, [r0, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r4, [\B, #-4]!
+ str r4, [r0, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r5, [\B, #-4]!
+ str r5, [r0, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r6, [\B, #-4]!
+ str r6, [r0, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r7, [\B, #-4]!
+ str r7, [r0, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str r8, [\B, #-4]!
+ str r8, [r0, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- sfi_breg r0, \
- str lr, [\B, #-4]!
+ str lr, [r0, #-4]!
#ifdef ARM_ALWAYS_BX
pop {r10}
@@ -225,18 +207,12 @@
cfi_restore (r8)
8: movs r2, r2, lsl #31
- sfi_breg r1, \
- ldrbne r3, [\B, #-1]!
- sfi_breg r1, \
- ldrbcs r4, [\B, #-1]!
- sfi_breg r1, \
- ldrbcs ip, [\B, #-1]
- sfi_breg r0, \
- strbne r3, [\B, #-1]!
- sfi_breg r0, \
- strbcs r4, [\B, #-1]!
- sfi_breg r0, \
- strbcs ip, [\B, #-1]
+ ldrbne r3, [r1, #-1]!
+ ldrbcs r4, [r1, #-1]!
+ ldrbcs ip, [r1, #-1]
+ strbne r3, [r0, #-1]!
+ strbcs r4, [r0, #-1]!
+ strbcs ip, [r0, #-1]
#if ((defined (__ARM_ARCH_4T__) && defined (__THUMB_INTERWORK__)) \
|| defined (ARM_ALWAYS_BX))
@@ -252,27 +228,20 @@
cfi_restore_state
9: cmp ip, #2
- sfi_breg r1, \
- ldrbgt r3, [\B, #-1]!
- sfi_breg r1, \
- ldrbge r4, [\B, #-1]!
- sfi_breg r1, \
- ldrb lr, [\B, #-1]!
- sfi_breg r0, \
- strbgt r3, [\B, #-1]!
- sfi_breg r0, \
- strbge r4, [\B, #-1]!
+ ldrbgt r3, [r1, #-1]!
+ ldrbge r4, [r1, #-1]!
+ ldrb lr, [r1, #-1]!
+ strbgt r3, [r0, #-1]!
+ strbge r4, [r0, #-1]!
subs r2, r2, ip
- sfi_breg r0, \
- strb lr, [\B, #-1]!
- blt 8b
+ strb lr, [r0, #-1]!
+ blo 8b
ands ip, r1, #3
beq 1b
10: bic r1, r1, #3
cmp ip, #2
- sfi_breg r1, \
- ldr r3, [\B, #0]
+ ldr r3, [r1, #0]
beq 17f
blt 18f
@@ -280,7 +249,7 @@
.macro backward_copy_shift push pull
subs r2, r2, #28
- blt 14f
+ blo 14f
CALGN( ands ip, r1, #31 )
CALGN( rsb ip, ip, #32 )
@@ -296,20 +265,18 @@
cfi_rel_offset (r8, 12)
cfi_rel_offset (r10, 16)
- PLD( sfi_pld r1, #-4 )
- PLD( subs r2, r2, #96 )
- PLD( sfi_pld r1, #-32 )
- PLD( blt 13f )
- PLD( sfi_pld r1, #-64 )
- PLD( sfi_pld r1, #-96 )
+ PLD( pld [r1, #-4] )
+ PLD( cmp r2, #96 )
+ PLD( pld [r1, #-32] )
+ PLD( blo 13f )
+ PLD( pld [r1, #-64] )
+ PLD( pld [r1, #-96] )
-12: PLD( sfi_pld r1, #-128 )
-13: sfi_breg r1, \
- ldmdb \B!, {r7, r8, r10, ip}
+12: PLD( pld [r1, #-128] )
+13: ldmdb r1!, {r7, r8, r10, ip}
mov lr, r3, PUSH #\push
subs r2, r2, #32
- sfi_breg r1, \
- ldmdb \B!, {r3, r4, r5, r6}
+ ldmdb r1!, {r3, r4, r5, r6}
orr lr, lr, ip, PULL #\pull
mov ip, ip, PUSH #\push
orr ip, ip, r10, PULL #\pull
@@ -325,11 +292,8 @@
orr r5, r5, r4, PULL #\pull
mov r4, r4, PUSH #\push
orr r4, r4, r3, PULL #\pull
- sfi_breg r0, \
- stmdb \B!, {r4 - r8, r10, ip, lr}
- bge 12b
- PLD( cmn r2, #96 )
- PLD( bge 13b )
+ stmdb r0!, {r4 - r8, r10, ip, lr}
+ bhs 12b
pop {r5 - r8, r10}
cfi_adjust_cfa_offset (-20)
@@ -343,12 +307,10 @@
beq 16f
15: mov lr, r3, PUSH #\push
- sfi_breg r1, \
- ldr r3, [\B, #-4]!
+ ldr r3, [r1, #-4]!
subs ip, ip, #4
orr lr, lr, r3, PULL #\pull
- sfi_breg r0, \
- str lr, [\B, #-4]!
+ str lr, [r0, #-4]!
bgt 15b
CALGN( cmp r2, #0 )
CALGN( bge 11b )
diff --git a/ap/libc/glibc/glibc-2.23/sysdeps/ieee754/ldbl-96/e_rem_pio2l.c b/ap/libc/glibc/glibc-2.23/sysdeps/ieee754/ldbl-96/e_rem_pio2l.c
old mode 100644
new mode 100755
index 0d8e646..accd7dc
--- a/ap/libc/glibc/glibc-2.23/sysdeps/ieee754/ldbl-96/e_rem_pio2l.c
+++ b/ap/libc/glibc/glibc-2.23/sysdeps/ieee754/ldbl-96/e_rem_pio2l.c
@@ -209,6 +209,18 @@
y[1] = y[0];
return 0;
}
+
+ if ((i0 & 0x80000000) == 0)
+ {
+ /* Pseudo-zero and unnormal representations are not valid
+ representations of long double. We need to avoid stack
+ corruption in __kernel_rem_pio2, which expects input in a
+ particular normal form, but those representations do not need
+ to be consistently handled like any particular floating-point
+ value. */
+ y[1] = y[0] = __builtin_nanl ("");
+ return 0;
+ }
/* Split the 64 bits of the mantissa into three 24-bit integers
stored in a double array. */
diff --git a/ap/libc/glibc/glibc-2.23/sysdeps/posix/getcwd.c b/ap/libc/glibc/glibc-2.23/sysdeps/posix/getcwd.c
old mode 100644
new mode 100755
index 38cf4e7..23e77cd
--- a/ap/libc/glibc/glibc-2.23/sysdeps/posix/getcwd.c
+++ b/ap/libc/glibc/glibc-2.23/sysdeps/posix/getcwd.c
@@ -241,6 +241,13 @@
char *path;
#ifndef NO_ALLOCATION
size_t allocated = size;
+
+ /* A size of 1 byte is never useful. */
+ if (allocated == 1)
+ {
+ __set_errno (ERANGE);
+ return NULL;
+ }
if (size == 0)
{
if (buf != NULL)