[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/ap/build/scripts/build_env_mini/Makefile b/ap/build/scripts/build_env_mini/Makefile
new file mode 100755
index 0000000..9a9a0e9
--- /dev/null
+++ b/ap/build/scripts/build_env_mini/Makefile
@@ -0,0 +1,126 @@
+
+include $(ZTE_PS_LINK_SCRIPT)
+-include $(OUTPUT_DIR)/sys_type.mk
+
+.PHONY: help all allclean app appclean lib libclean check
+
+help: check
+ @echo "=========================Make help start========================="
+ @echo "make [help] this help"
+ @echo "make all[clean] compile all, include recovery and normal system"
+ @echo "make normal[clean] compile normal system,include kernel uClibc lib and app"
+ @echo "make normal2 continue to compile normal system"
+ @echo "make normal_rootfs make rootfs for normal system"
+ @echo "make normal_copybin copy bins to project for normal system"
+ @echo "make rootfs make rootfs for normal or recovery automatically based on config"
+ @echo "make copybin copy bins to project for normal or recovery automatically based on config"
+ @echo "make lib[clean] compile lib"
+ @echo "make app[clean] compile app"
+ @echo "=========================Make help end========================="
+
+check:
+ifeq ($(PRJ_NAME),)
+ $(error ONLY execute the make command in the project/CHIP_NAME/prj_xxx/build directory)
+endif
+ bash $(BUILD_DIR)/env_check.sh
+
+normal_check:
+ifneq ($(AP_BUILD_TYPE),normal)
+ $(error current config is not normal,make normal first)
+endif
+
+all:
+ make AP_BUILD_TYPE=normal normal
+
+allclean: normalclean
+
+sys: check
+ make lib
+ make app
+ @echo "all modules build done"
+
+sysclean: check
+ make libclean
+ make appclean
+ -@rm -fr $(OUTPUT_DIR)
+ @echo "all modules clean done"
+
+app:
+ mkdir -p $(ROOTFS_DIR)/bin $(ROOTFS_DIR)/sbin $(ROOTFS_DIR)/lib $(ROOTFS_DIR)/recovery/bin
+ make -C app
+
+appclean:
+ make -C app clean
+
+lib:
+ mkdir -p $(ROOTFS_DIR)/bin $(ROOTFS_DIR)/sbin $(ROOTFS_DIR)/lib $(ROOTFS_DIR)/recovery/bin
+ make -C lib
+
+libclean:
+ make -C lib clean
+
+normal_conf:
+ mkdir -p $(OUTPUT_DIR)
+ mkdir -p $(IMAGE_DIR)
+ echo "AP_BUILD_TYPE = normal" > $(OUTPUT_DIR)/sys_type.mk
+ echo "AP_BUILD_PRJ = $(PRJ_NAME)" >> $(OUTPUT_DIR)/sys_type.mk
+
+normal:
+ make AP_BUILD_TYPE=normal sysclean
+ make AP_BUILD_TYPE=normal normal_conf
+ make AP_BUILD_TYPE=normal sys
+ make AP_BUILD_TYPE=normal normal_rootfs
+ make AP_BUILD_TYPE=normal normal_copybin
+
+normal2: sys normal_rootfs normal_copybin
+
+normalclean:
+ -make AP_BUILD_TYPE=normal sysclean
+ make normal_conf
+ make AP_BUILD_TYPE=normal sysclean
+
+rootfs:
+ make normal_rootfs
+
+copybin:
+
+ make normal_copybin
+
+normal_rootfs: normal_check
+ mkdir -p $(PRJ_BIN_DIR)/allbins $(PRJ_BIN_DIR)/elfs
+ rm -fr $(ROOTFS_DIR)/etc_rw
+ cp -afvp $(PRJ_PRODUCT_DIR)/fs/normal/rootfs/* $(ROOTFS_DIR)/
+ #cp -v $(PRJ_BIN_DIR)/allbins/ap_userdata.img $(ROOTFS_DIR)/etc_ro/
+ chmod -R a+r $(ROOTFS_DIR)/etc_ro
+ #find $(ROOTFS_DIR)/bin -type f | xargs chmod a+x
+ #-find $(ROOTFS_DIR)/sbin -type f | xargs chmod a+x
+ chmod a+x $(ROOTFS_DIR)/etc/rc
+ #@cd $(BUILD_DIR); bash ./install_libc.sh $(ROOTFS_DIR)
+ find $(ROOTFS_DIR)/ -type d -name '.gitkeep' -print0 | xargs -0 rm -fr
+ find $(ROOTFS_DIR)/ -type d -name '.git' -print0 | xargs -0 rm -fr
+ find $(ROOTFS_DIR)/ -name '.gitignore' -print0 | xargs -0 rm -fr
+
+ifeq ($(ROOT_FS_TYPE),ubifs)
+ bash $(BUILD_DIR)/ubifs.sh rootfs $(ROOTFS_SIZE) $(ROOTFS_DIR) $(IMAGE_DIR)/rootfs.img
+else
+ifeq ($(ROOT_FS_TYPE),jffs2)
+ifeq ($(PRJ_IS_MIN),yes)
+ bash $(BUILD_DIR)/jffs2_lzma.sh $(ROOTFS_DIR) $(IMAGE_DIR)/rootfs.img lzma
+else
+ bash $(BUILD_DIR)/jffs2_lzma.sh $(ROOTFS_DIR) $(IMAGE_DIR)/rootfs.img lzo
+endif
+endif
+endif
+
+ (cd $(ROOTFS_DIR) && find . -type f -printf '"/%P" Regular 14 %04m:%4U:%4G\n' > ../rootfs_attr.txt)
+ (cd $(ROOTFS_DIR) && find . -type l -printf '"/%P" SymLink 14 %04m:%4U:%4G\n' >> ../rootfs_attr.txt)
+ (cd $(ROOTFS_DIR) && find . -type d -printf '"/%P" Regular 14 %04m:%4U:%4G\n' >> ../rootfs_attr.txt)
+ (cd $(ROOTFS_DIR)/../ && tar -zcvf $(PRJ_BIN_DIR)/allbins/rootfs.tgz rootfs rootfs_attr.txt)
+ @rm $(ROOTFS_DIR)/../rootfs_attr.txt
+
+normal_copybin: normal_check
+ mkdir -p $(PRJ_BIN_DIR)/allbins $(PRJ_BIN_DIR)/elfs/normalelfs
+ cp -v $(IMAGE_DIR)/rootfs.img $(PRJ_BIN_DIR)/allbins/ap_rootfs.img
+ find $(APP_DIR)/ -name *.elf -exec cp {} $(PRJ_BIN_DIR)/elfs/normalelfs \;
+ find $(LIB_DIR)/ -type f -name "lib*.so" -exec cp {} $(PRJ_BIN_DIR)/elfs/normalelfs \;
+ find $(STAGEDIR)/uClibc/lib -type f -name "*.so" -exec cp {} $(PRJ_BIN_DIR)/elfs/normalelfs \;
diff --git a/ap/build/scripts/build_env_mini/build_env_mini.sh b/ap/build/scripts/build_env_mini/build_env_mini.sh
new file mode 100755
index 0000000..23ba23f
--- /dev/null
+++ b/ap/build/scripts/build_env_mini/build_env_mini.sh
@@ -0,0 +1,78 @@
+#!/bin/bash
+
+CROSS_DIR=v3t_build_env_mini
+
+LIB_SET="libdemo zlib"
+APP_SET="appdemo"
+PRJ_NAME=prj_mifi
+
+if [ ! -d build/compiler ]; then
+ echo "[ERROR] CAN not found build/compiler and run in directory containing ap and build."
+ exit -1
+fi
+
+RSYNC_OPT="rsync -aq --delete --exclude=.svn --exclude=.git"
+
+rm -fr $CROSS_DIR
+rm -fv $CROSS_DIR.tar.gz
+mkdir -p $CROSS_DIR
+
+#±àÒëÁ´
+mkdir -p $CROSS_DIR/build/compiler/gcc-4.9.4_thumb_linux/
+$RSYNC_OPT ./build/compiler/gcc-4.9.4_thumb_linux/ $CROSS_DIR/build/compiler/gcc-4.9.4_thumb_linux/
+
+#libc
+mkdir -p $CROSS_DIR/ap/staging/
+$RSYNC_OPT ./ap/staging/ $CROSS_DIR/ap/staging/
+
+#ap/build
+mkdir -p $CROSS_DIR/ap/build/
+$RSYNC_OPT ./ap2/build/ $CROSS_DIR/ap/build/
+
+#prj
+mkdir -p $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME
+$RSYNC_OPT ./ap2/project/zx297520v3/$PRJ_NAME/ $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/
+cp -v ./ap2/project/pubconf.mk $CROSS_DIR/ap/project/
+cp -v ./ap2/project/zx297520v3/chip_pubconf.mk $CROSS_DIR/ap/project/zx297520v3/
+
+#demo lib
+mkdir -p $CROSS_DIR/ap/lib/
+for item in $LIB_SET;do
+ mkdir -p $CROSS_DIR/ap/lib/$item/
+ $RSYNC_OPT ./ap2/lib/$item/ $CROSS_DIR/ap/lib/$item/
+done
+cp -v ./ap2/lib/Makefile $CROSS_DIR/ap/lib/
+
+#demo app
+mkdir -p $CROSS_DIR/ap/app/
+for item in $APP_SET;do
+ mkdir -p $CROSS_DIR/ap/app/$item/
+ $RSYNC_OPT ./ap2/app/$item/ $CROSS_DIR/ap/app/$item/
+done
+cp -v ./ap2/app/Makefile $CROSS_DIR/ap/app/
+#mkdir -p $CROSS_DIR/ap/app/include/
+#$RSYNC_OPT ./ap/app/include/ $CROSS_DIR/ap/app/include/
+
+rm -fr $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/normal/*
+echo "zte_lib := $LIB_SET" > $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/normal/config_lib.mk
+echo "zte_app := $APP_SET" > $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/normal/config_app.mk
+cp -v $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/normal/config_lib.mk $CROSS_DIR/ap/lib/
+cp -v $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/normal/config_app.mk $CROSS_DIR/ap/app/
+
+
+cp -v ./ap/build/scripts/build_env_mini/Makefile $CROSS_DIR/ap/
+cp -v ./ap/build/scripts/build_env_mini/readme.txt $CROSS_DIR/
+
+#clean
+rm -fr $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/fs/normal/rootfs/*
+mkdir -p $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/fs/normal/rootfs/etc
+mkdir -p $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/fs/normal/rootfs/etc_ro
+touch $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/fs/normal/rootfs/etc/rc
+rm -fr $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/fs/recovery
+rm -fr $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/recovery
+rm -fr $CROSS_DIR/ap/build/scripts
+rm -fr $CROSS_DIR/ap/build/uClibc
+
+echo "compress files to ${CROSS_DIR}.tar.gz"
+tar -czf ${CROSS_DIR}.tar.gz $CROSS_DIR/
+echo "all done"
diff --git a/ap/build/scripts/build_env_mini/readme.txt b/ap/build/scripts/build_env_mini/readme.txt
new file mode 100755
index 0000000..0e24683
--- /dev/null
+++ b/ap/build/scripts/build_env_mini/readme.txt
@@ -0,0 +1,32 @@
+运行平台要求x86_64 Linux，建议ubuntu 12.04、ubuntu 14.04、ubuntu 16.04，其他Linux平台未测试，理论上其他64位Linux环境也可以。
+本编译环境无需安装，解压即可使用。
+
+如果不使用本编译框架，直接使用编译链，参考ap/build/build.sh里CC、AR等定义，CFLAGS和LDFLAGS等建议参数定义在ap/build/base.mk。
+如果软件交叉编译configure需要指定--host和--target，可以配置成--host=arm-linux --target=arm-linux，参见ap/build/base.mk。
+
+如果使用本编译环境编译框架，以prj_mdl为例，只能在project/CHIP_NAME/prj_mdl/build目录运行make命令。
+1、完整编译：make all, 注意本编译链只有normal版本,make normal等同make all。make help可以获得更多信息。
+
+2、增量编译命令
+ normal版本编译：make normal，编译完成打包的文件系统映像ap_userdata.img在project/CHIP_NAME/prj_mdl/bin目录
+ 如果编译报错，代码修改后增量编译：make normal2
+
+3、normal版本下，修改了lib代码，make lib app normal_rootfs normal_copybin，或者可以用make normal2
+ ap_userdata.img为根文件系统,在project/CHIP_NAME/prj_mdl/bin目录
+ 如果app用了lib的静态库，app的Makefile发现不了依赖，所以最好make appclean一下
+
+ 只解决库编译错误，可以make zte_lib=libdemo lib方式，这样只编译libdemo应用
+ make zte_lib=libdemo libclean只清空libdemo的编译
+
+4、normal版本下，修改了app代码，make app normal_rootfs normal_copybin，或者可以用make normal2
+ ap_userdata.img为根文件系统,在project/CHIP_NAME/prj_mdl/bin目录
+
+ 只解决应用编译错误，可以make zte_app=appdemo app方式，这样只编译appdemo应用
+ make zte_app=appdemo appclean只清空appdemo应用的编译
+
+5、增加应用和库编译
+应用和库的Makefile要包含COMMON_BASE_MK或COMMON_MK，参看app和lib目录的demo实例。
+COMMON_MK比COMMON_BASE_MK多了一些宏定义，如果不需要,包含COMMON_BASE_MK即可。
+5.1 经过configure生成Makefile的开源应用和库建议包含COMMON_BASE_MK，因为某些开源应用如果CFLAGS里包含宏定义会导致configure失败。
+5.2 增加应用编译，应用名称增加到ap/app/config_app.mk里
+5.3 增加库编译，库名称增加到ap/lib/config_lib.mk里
diff --git a/ap/build/scripts/build_env_mini_readme.txt b/ap/build/scripts/build_env_mini_readme.txt
new file mode 100755
index 0000000..c3d8069
--- /dev/null
+++ b/ap/build/scripts/build_env_mini_readme.txt
@@ -0,0 +1,51 @@
+build_env_mini ½Å±¾ÖÆ×÷×îС±àÒëÁ´£¬¿ÉÓÃÓÚµÚÈý·½¿âºÍÓ¦ÓñàÒë
+build_env_mini_with_kernel ½Å±¾ÖÆ×÷×îС±àÒëÁ´£¬¿ÉÓÃÓÚµÚÈý·½¿â¡¢Ó¦ÓñàÒëºÍÄÚºËkoÄ£¿éµÄ±àÒë
+
+
+Èç¹û´æÔÚµÚÈý·½ko·â¿âµÄÇé¿ö£¬×îºÃ¹Ø±ÕÄÚºËko°æ±¾ºÅ¼ì²é¡£·ñÔòÄں˴úÂëÐÞ¸ÄÐèÒªµÚÈý·½koÖØбàÒë¡£
+¹Ø±Õ·½·¨£º
+
+1)¡¢ÄÚºËconfig.linuxÀïCONFIG_MODVERSIONSºÍCONFIG_MODULE_SRCVERSION_ALL ¸Ä³ÉÏÂÃæÅäÖÃ
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+
+2£©¡¢¹Ø±ÕcpkoºÍloadcpÁ½¸ökoµÄmodpost
+ÓÃÏÂÃæÃüÁî²éÕÒ
+cat ap/Makefile | grep -n Module.symvers | grep modpost
+Á½ÐмÓ#×¢Ê͵ô
+ #(cd $(LINUX_DIR) && scripts/mod/modpost -m -a -o $(LINUX_DIR)/Module.symvers -c -s vmlinux drivers/cpko/cpko.ko)
+ #(cd $(LINUX_DIR) && scripts/mod/modpost -m -a -o $(LINUX_DIR)/Module.symvers -c -s vmlinux drivers/loadcp/loadcp.ko)
+
+
+
+²Ù×÷ÔËÐв½Ö裺
+1¡¢´Ógit/svn»ñÈ¡¸É¾»µÄ¹¤³Ìµ½codeĿ¼¡£codeĿ¼°üº¬ap¡¢cp¡¢build¡¢pub¡¢toolsµÈĿ¼
+2¡¢ÓÃÏÂÃæÃüÁ¸É¾»µÄap±¸·ÝÒ»¸öap2¡£±¸·ÝµÄʱºòapµÄĿ¼һ¶¨ÒªÊÇûÓбàÒë¹ýµÄ¡£
+
+cd code
+rsync -aq --delete --exclude=.svn --exclude=.git ./ap/ ./ap2/
+
+
+3¡¢ÖÆ×÷×îС±àÒëÁ´
+cd ap/project/zx297520v3/prj_mifi/build
+make normal
+cd code
+
+1)ÖÆ×÷×îС±àÒë
+ÖÆ×÷build_env_mini£¬ÔÚcodeĿ¼ÔËÐÐ
+bash ap/build/scripts/build_env_mini/build_env_mini.sh
+
+2)ÖÆ×÷´øÄں˵Ä×îС±àÒë
+ÖÆ×÷build_env_mini_with_kernel£¬ÔÚcodeĿ¼ÔËÐÐ
+bash ap/build/scripts/build_env_mini_with_kernel/build_env_mini.sh
+
+4¡¢ÖÆ×÷populate_sdk
+ÐÞ¸Äap/project/zx297520v3/prj_mifi/config/normal/config_lib.mk£¬¶¨Òåpopulate_sdk_lib´ò°üµ½±àÒëÁ´sysrootµÄlib¿â
+populate_sdk_lib := libsqlite libcurl libssl expat dbus glib
+
+cd ap/project/zx297520v3/prj_mifi/build
+make normal populate_sdk
+cd code
+bash ap/build/scripts/build_env_mini/build_env_mini.sh
+
+
diff --git a/ap/build/scripts/build_env_mini_with_kernel/Makefile b/ap/build/scripts/build_env_mini_with_kernel/Makefile
new file mode 100755
index 0000000..e8efb3a
--- /dev/null
+++ b/ap/build/scripts/build_env_mini_with_kernel/Makefile
@@ -0,0 +1,145 @@
+
+include $(ZTE_PS_LINK_SCRIPT)
+-include $(OUTPUT_DIR)/sys_type.mk
+
+.PHONY: help all allclean app appclean lib libclean check
+
+help: check
+ @echo "=========================Make help start========================="
+ @echo "make [help] this help"
+ @echo "make all[clean] compile all, include recovery and normal system"
+ @echo "make normal[clean] compile normal system,include kernel uClibc lib and app"
+ @echo "make normal2 continue to compile normal system"
+ @echo "make normal_rootfs make rootfs for normal system"
+ @echo "make normal_copybin copy bins to project for normal system"
+ @echo "make rootfs make rootfs for normal or recovery automatically based on config"
+ @echo "make copybin copy bins to project for normal or recovery automatically based on config"
+ @echo "make lib[clean] compile lib"
+ @echo "make app[clean] compile app"
+ @echo "=========================Make help end========================="
+
+check:
+ifeq ($(PRJ_NAME),)
+ $(error ONLY execute the make command in the project/CHIP_NAME/prj_xxx/build directory)
+endif
+ bash $(BUILD_DIR)/env_check.sh
+
+normal_check:
+ifneq ($(AP_BUILD_TYPE),normal)
+ $(error current config is not normal,make normal first)
+endif
+
+all:
+ make AP_BUILD_TYPE=normal normal
+
+allclean: normalclean
+
+sys: check
+ make lib
+ make app
+ @echo "all modules build done"
+
+sysclean: check
+ make libclean
+ make appclean
+ -@rm -fr $(OUTPUT_DIR)
+ @echo "all modules clean done"
+
+kernel:
+ -rm -v $(LINUX_DIR)/arch/arm/boot/*Image
+ -rm -v $(LINUX_DIR)/vmlinux*
+ #make -j1 ARCH=arm KBUILD_VERBOSE=1 CROSS_COMPILE=$(CROSS_COMPILE) -C $(LINUX_DIR) all
+ #make -j1 ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(LINUX_DIR) all
+ make -j1 ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(LINUX_DIR) prepare
+ make -j1 ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(LINUX_DIR) scripts
+
+kernel_menuconfig:
+ make ARCH=arm -C $(LINUX_DIR) menuconfig
+
+kernel_mod:
+ make ARCH=arm -C $(LINUX_DIR) M=fs/yaffs2 modules
+
+kernel_mod_clean:
+ make ARCH=arm -C $(LINUX_DIR) M=fs/yaffs2 clean
+
+app:
+ mkdir -p $(ROOTFS_DIR)/bin $(ROOTFS_DIR)/sbin $(ROOTFS_DIR)/lib $(ROOTFS_DIR)/recovery/bin
+ make -C app
+
+appclean:
+ make -C app clean
+
+lib:
+ mkdir -p $(ROOTFS_DIR)/bin $(ROOTFS_DIR)/sbin $(ROOTFS_DIR)/lib $(ROOTFS_DIR)/recovery/bin
+ make -C lib
+
+libclean:
+ make -C lib clean
+
+normal_conf:
+ @cp -v $(PRJ_CONF_DIR)/normal/config.linux $(LINUX_DIR)/arch/arm/configs/zte_defconfig
+ make ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(LINUX_DIR) zte_defconfig
+ mkdir -p $(OUTPUT_DIR)
+ mkdir -p $(IMAGE_DIR)
+ echo "AP_BUILD_TYPE = normal" > $(OUTPUT_DIR)/sys_type.mk
+ echo "AP_BUILD_PRJ = $(PRJ_NAME)" >> $(OUTPUT_DIR)/sys_type.mk
+
+normal:
+ make AP_BUILD_TYPE=normal sysclean
+ make AP_BUILD_TYPE=normal normal_conf
+ make AP_BUILD_TYPE=normal sys
+ make AP_BUILD_TYPE=normal normal_rootfs
+ make AP_BUILD_TYPE=normal normal_copybin
+
+normal2: sys normal_rootfs normal_copybin
+
+normalclean:
+ -make AP_BUILD_TYPE=normal sysclean
+ make normal_conf
+ make AP_BUILD_TYPE=normal sysclean
+
+rootfs:
+ make normal_rootfs
+
+copybin:
+
+ make normal_copybin
+
+normal_rootfs: normal_check
+ mkdir -p $(PRJ_BIN_DIR)/allbins $(PRJ_BIN_DIR)/elfs
+ rm -fr $(ROOTFS_DIR)/etc_rw
+ cp -afvp $(PRJ_PRODUCT_DIR)/fs/normal/rootfs/* $(ROOTFS_DIR)/
+ #cp -v $(PRJ_BIN_DIR)/allbins/ap_userdata.img $(ROOTFS_DIR)/etc_ro/
+ chmod -R a+r $(ROOTFS_DIR)/etc_ro
+ #find $(ROOTFS_DIR)/bin -type f | xargs chmod a+x
+ #-find $(ROOTFS_DIR)/sbin -type f | xargs chmod a+x
+ chmod a+x $(ROOTFS_DIR)/etc/rc
+ #@cd $(BUILD_DIR); bash ./install_libc.sh $(ROOTFS_DIR)
+ find $(ROOTFS_DIR)/ -type d -name '.gitkeep' -print0 | xargs -0 rm -fr
+ find $(ROOTFS_DIR)/ -type d -name '.git' -print0 | xargs -0 rm -fr
+ find $(ROOTFS_DIR)/ -name '.gitignore' -print0 | xargs -0 rm -fr
+
+ifeq ($(ROOT_FS_TYPE),ubifs)
+ bash $(BUILD_DIR)/ubifs.sh rootfs $(ROOTFS_SIZE) $(ROOTFS_DIR) $(IMAGE_DIR)/rootfs.img
+else
+ifeq ($(ROOT_FS_TYPE),jffs2)
+ifeq ($(PRJ_IS_MIN),yes)
+ bash $(BUILD_DIR)/jffs2_lzma.sh $(ROOTFS_DIR) $(IMAGE_DIR)/rootfs.img lzma
+else
+ bash $(BUILD_DIR)/jffs2_lzma.sh $(ROOTFS_DIR) $(IMAGE_DIR)/rootfs.img lzo
+endif
+endif
+endif
+
+ (cd $(ROOTFS_DIR) && find . -type f -printf '"/%P" Regular 14 %04m:%4U:%4G\n' > ../rootfs_attr.txt)
+ (cd $(ROOTFS_DIR) && find . -type l -printf '"/%P" SymLink 14 %04m:%4U:%4G\n' >> ../rootfs_attr.txt)
+ (cd $(ROOTFS_DIR) && find . -type d -printf '"/%P" Regular 14 %04m:%4U:%4G\n' >> ../rootfs_attr.txt)
+ (cd $(ROOTFS_DIR)/../ && tar -zcvf $(PRJ_BIN_DIR)/allbins/rootfs.tgz rootfs rootfs_attr.txt)
+ @rm $(ROOTFS_DIR)/../rootfs_attr.txt
+
+normal_copybin: normal_check
+ mkdir -p $(PRJ_BIN_DIR)/allbins $(PRJ_BIN_DIR)/elfs/normalelfs
+ cp -v $(IMAGE_DIR)/rootfs.img $(PRJ_BIN_DIR)/allbins/ap_rootfs.img
+ find $(APP_DIR)/ -name *.elf -exec cp {} $(PRJ_BIN_DIR)/elfs/normalelfs \;
+ find $(LIB_DIR)/ -type f -name "lib*.so" -exec cp {} $(PRJ_BIN_DIR)/elfs/normalelfs \;
+ find $(STAGEDIR)/uClibc/lib -type f -name "*.so" -exec cp {} $(PRJ_BIN_DIR)/elfs/normalelfs \;
diff --git a/ap/build/scripts/build_env_mini_with_kernel/build_env_mini.sh b/ap/build/scripts/build_env_mini_with_kernel/build_env_mini.sh
new file mode 100755
index 0000000..5e62279
--- /dev/null
+++ b/ap/build/scripts/build_env_mini_with_kernel/build_env_mini.sh
@@ -0,0 +1,107 @@
+#!/bin/bash
+
+CROSS_DIR=v3t_build_env_mini_with_kernel
+
+LIB_SET="libdemo zlib"
+APP_SET="appdemo"
+PRJ_NAME=prj_mdl
+
+RSYNC_OPT="rsync -aq --delete --exclude=.svn --exclude=.git"
+
+
+cat ap/Makefile | grep -n Module.symvers | grep modpost | grep -v "#"
+if [ $? -ne 1 ]; then
+ echo "[ERROR]please comment modpost in ap/Makefile"
+ exit -1
+else
+ echo "ap/Makefile mode post check ok"
+fi
+cat ap/os/linux/linux-3.4.x/.config | grep "# CONFIG_MODVERSIONS is not set"
+if [ $? -ne 0 ]; then
+ echo "[ERROR]please set #CONFIG_MODVERSIONS is not set in config.linux"
+ exit -1
+else
+ echo "CONFIG_MODVERSIONS check ok"
+fi
+cat ap/os/linux/linux-3.4.x/.config | grep "# CONFIG_MODULE_SRCVERSION_ALL is not set"
+if [ $? -ne 0 ]; then
+ echo "[ERROR]please set #CONFIG_MODULE_SRCVERSION_ALL is not set in config.linux"
+ exit -1
+else
+ echo "CONFIG_MODULE_SRCVERSION_ALL check ok"
+fi
+
+rm -fr $CROSS_DIR
+rm -fv $CROSS_DIR.tar.gz
+mkdir -p $CROSS_DIR
+
+#±àÒëÁ´
+mkdir -p $CROSS_DIR/build/compiler/gcc-4.9.4_thumb_linux/
+$RSYNC_OPT ./build/compiler/gcc-4.9.4_thumb_linux/ $CROSS_DIR/build/compiler/gcc-4.9.4_thumb_linux/
+
+#libc
+mkdir -p $CROSS_DIR/ap/staging/
+$RSYNC_OPT ./ap/staging/ $CROSS_DIR/ap/staging/
+
+#ap/build
+mkdir -p $CROSS_DIR/ap/build/
+$RSYNC_OPT ./ap2/build/ $CROSS_DIR/ap/build/
+
+#prj
+mkdir -p $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME
+$RSYNC_OPT ./ap2/project/zx297520v3/$PRJ_NAME/ $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/
+cp -v ./ap2/project/pubconf.mk $CROSS_DIR/ap/project/
+cp -v ./ap2/project/zx297520v3/chip_pubconf.mk $CROSS_DIR/ap/project/zx297520v3/
+
+#demo lib
+mkdir -p $CROSS_DIR/ap/lib/
+for item in $LIB_SET;do
+ mkdir -p $CROSS_DIR/ap/lib/$item/
+ $RSYNC_OPT ./ap2/lib/$item/ $CROSS_DIR/ap/lib/$item/
+done
+cp -v ./ap2/lib/Makefile $CROSS_DIR/ap/lib/
+
+#demo app
+mkdir -p $CROSS_DIR/ap/app/
+for item in $APP_SET;do
+ mkdir -p $CROSS_DIR/ap/app/$item/
+ $RSYNC_OPT ./ap2/app/$item/ $CROSS_DIR/ap/app/$item/
+done
+cp -v ./ap2/app/Makefile $CROSS_DIR/ap/app/
+#mkdir -p $CROSS_DIR/ap/app/include/
+#$RSYNC_OPT ./ap/app/include/ $CROSS_DIR/ap/app/include/
+
+#linux kernel
+echo "sync linux kernel"
+mkdir -p $CROSS_DIR/ap/os/
+$RSYNC_OPT ./ap2/os/ $CROSS_DIR/ap/os/
+cp -v ap/os/linux/linux-3.4.x/Module.symvers $CROSS_DIR/ap/os/linux/linux-3.4.x/
+
+#pub for kernel
+rm -v $CROSS_DIR/ap/os/linux/linux-3.4.x/arch/arm/mach-zx297520v3/include/mach/ram_base_config_7520v3.h
+cp -v pub/project/zx297520v3/include/infra/ram_base_config_7520v3.h $CROSS_DIR/ap/os/linux/linux-3.4.x/arch/arm/mach-zx297520v3/include/mach/
+
+rm -fr $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/normal/*
+cp -v ap/project/zx297520v3/$PRJ_NAME/config/normal/config.linux $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/normal/
+echo "zte_lib := $LIB_SET" > $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/normal/config_lib.mk
+echo "zte_app := $APP_SET" > $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/normal/config_app.mk
+cp -v $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/normal/config_lib.mk $CROSS_DIR/ap/lib/
+cp -v $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/normal/config_app.mk $CROSS_DIR/ap/app/
+
+
+cp -v ./ap/build/scripts/build_env_mini_with_kernel/Makefile $CROSS_DIR/ap/
+cp -v ./ap/build/scripts/build_env_mini_with_kernel/readme.txt $CROSS_DIR/
+
+#clean
+rm -fr $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/fs/normal/rootfs/*
+mkdir -p $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/fs/normal/rootfs/etc
+mkdir -p $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/fs/normal/rootfs/etc_ro
+touch $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/fs/normal/rootfs/etc/rc
+rm -fr $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/fs/recovery
+rm -fr $CROSS_DIR/ap/project/zx297520v3/$PRJ_NAME/config/recovery
+rm -fr $CROSS_DIR/ap/build/scripts
+rm -fr $CROSS_DIR/ap/build/uClibc
+
+echo "compress files to ${CROSS_DIR}.tar.gz"
+tar -czf ${CROSS_DIR}.tar.gz $CROSS_DIR/
+echo "all done"
diff --git a/ap/build/scripts/build_env_mini_with_kernel/readme.txt b/ap/build/scripts/build_env_mini_with_kernel/readme.txt
new file mode 100755
index 0000000..b40ba82
--- /dev/null
+++ b/ap/build/scripts/build_env_mini_with_kernel/readme.txt
@@ -0,0 +1,40 @@
+运行平台要求x86_64 Linux，建议ubuntu 12.04、ubuntu 14.04、ubuntu 16.04，其他Linux平台未测试，理论上其他64位Linux环境也可以。
+本编译环境无需安装，解压即可使用。
+
+如果不使用本编译框架，直接使用编译链，参考ap/build/build.sh里CC、AR等定义，CFLAGS和LDFLAGS等建议参数定义在ap/build/base.mk。
+如果软件交叉编译configure需要指定--host和--target，可以配置成--host=arm-linux --target=arm-linux，参见ap/build/base.mk。
+
+如果使用本编译环境编译框架，以prj_mdl为例，只能在project/CHIP_NAME/prj_mdl/build目录运行make命令。
+1、完整编译：make all, 注意本编译链只有normal版本,make normal等同make all。make help可以获得更多信息。
+
+2、增量编译命令
+ normal版本编译：make normal，编译完成打包的文件系统映像ap_userdata.img在project/CHIP_NAME/prj_mdl/bin目录
+ 如果编译报错，代码修改后增量编译：make normal2
+
+3、normal版本下，修改了lib代码，make lib app normal_rootfs normal_copybin，或者可以用make normal2
+ ap_userdata.img为根文件系统,在project/CHIP_NAME/prj_mdl/bin目录
+ 如果app用了lib的静态库，app的Makefile发现不了依赖，所以最好make appclean一下
+
+ 只解决库编译错误，可以make zte_lib=libdemo lib方式，这样只编译libdemo应用
+ make zte_lib=libdemo libclean只清空libdemo的编译
+
+4、normal版本下，修改了app代码，make app normal_rootfs normal_copybin，或者可以用make normal2
+ ap_userdata.img为根文件系统,在project/CHIP_NAME/prj_mdl/bin目录
+
+ 只解决应用编译错误，可以make zte_app=appdemo app方式，这样只编译appdemo应用
+ make zte_app=appdemo appclean只清空appdemo应用的编译
+
+5、增加应用和库编译
+应用和库的Makefile要包含COMMON_BASE_MK或COMMON_MK，参看app和lib目录的demo实例。
+COMMON_MK比COMMON_BASE_MK多了一些宏定义，如果不需要,包含COMMON_BASE_MK即可。
+5.1 经过configure生成Makefile的开源应用和库建议包含COMMON_BASE_MK，因为某些开源应用如果CFLAGS里包含宏定义会导致configure失败。
+5.2 增加应用编译，应用名称增加到ap/app/config_app.mk里
+5.3 增加库编译，库名称增加到ap/lib/config_lib.mk里
+
+6、编译内核ko
+ 1）先用make all或者make normal完整编译
+ 2) 合入ko模块代码，运行make kernel_menuconfig会打开内核配置窗口，将该模块配置成M
+ 3）运行make kernel，这步会生成内核的autoconf头文件，模块编译需要
+ 4）修改ap/Makefile里kernel_mod和kernel_mod_clean编译目标，将M=fs/yaffs2路径换成要编译的模块路径。
+ 运行make kernel_mod_clean kernel_mod即可编译出ko文件
+
diff --git a/ap/build/scripts/trace32/zx297520v3/7520V3_DDR_1Gb_312.cmm b/ap/build/scripts/trace32/zx297520v3/7520V3_DDR_1Gb_312.cmm
new file mode 100755
index 0000000..5c3c141
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/7520V3_DDR_1Gb_312.cmm
@@ -0,0 +1,34 @@
+area.reset
+sys.cpu CortexM0
+sys.bdmclock 3.0MHz ;cortex-m0
+sys.o enreset OFF
+sys.up
+
+wait 0.2s
+do ./sys/clk_init.cmm
+do ./sys/ddr_init_312m.cmm
+
+
+wait 0.2s
+//M0 address remap bit23
+data.set 0x00140000 %long 0x00871000
+
+//clear iram0
+data.set 0x82000000--0x8201ffff 0x0
+wait 0.1s
+//set here the ps-cpu to 32bit mode,this must be set before reset ps-cpu
+;data.set 0x001401E0 %long 0x20 //ap
+;data.set 0x001401EC %long 0x20 //ps
+
+
+// Release R7/A9 reset signal
+;data.set 0x013b138 %long 0x00000001 // PS
+data.set 0x0013b134 %long 0x00000001 // AP
+
+//jtag0 to ps
+;do ./sys/jtag_switch_script.cmm 0 1
+
+//jtag0 to ap
+do ./sys/jtag_switch_script.cmm 0 3
+
+
diff --git a/ap/build/scripts/trace32/zx297520v3/atag-list.cmm b/ap/build/scripts/trace32/zx297520v3/atag-list.cmm
new file mode 100755
index 0000000..c31e974
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/atag-list.cmm
@@ -0,0 +1,66 @@
+;--------------------------------------------------------------------------
+; Setup parameter tags for 297520v2fpga Linux boot
+; created by ZTE-TSP at 2015.08.07
+;--------------------------------------------------------------------------
+
+&tagAddr=0x22300100
+
+; ATAG_CORE
+data.set &tagAddr %LONG %LE 0x5
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr %LONG %LE 0x54410001
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr %LONG %LE 0x1
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr %LONG %LE 0x1000
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr %LONG %LE 0x0
+&tagAddr=&tagAddr+0x4
+
+; ATAG_MEM
+data.set &tagAddr %LONG %LE 0x4
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr %LONG %LE 0x54410002
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr %LONG %LE 0x3000000 // size 48MB
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr %LONG %LE 0x22300000 // start
+&tagAddr=&tagAddr+0x4
+
+; ATAG_INITRD2
+data.set &tagAddr %LONG %LE 0x4
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr %LONG %LE 0x54420005
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr %LONG %LE 0x22D00000 // start
+&tagAddr=&tagAddr+0x4
+&initrd_size=os.file.size(&INITRD_PATH)
+data.set &tagAddr %LONG %LE &initrd_size // file size in bytes
+&tagAddr=&tagAddr+0x4
+
+; ATAG_CMDLINE
+;&cmdline="console=ttyS0,115200"
+;&cmdline="console=ttyS0,115200 root=/dev/ram0 rw rdinit=/linuxrc mtdparts=denali-nand:1m@0x0(zloader),2m@0x100000(uboot),1m@0x300000(cpum0),2m@0x400000(nvro),8m@0x600000(nvrw),2m@0xe00000(nvfac),1m@0x1000000(fotaflag),7m@0x1100000(cpuzsp),1m@0x1800000(sms),15m@0x1900000(cpur7),10m@0x2800000(cpuap),4m@0x3200000(cpfs),8m@0x3600000(ramdisk),7m@0x3e00000(recovery),6m@0x4500000(recovery-kernel),16m@0x4b00000(cdrom),80m@0x5b00000(userdata),60m@0xab00000(fotaupdate),7m@0xf500000(cpuzspamt),2m@0xfc00000(securefs)"
+;&cmdline="console=ttyS0,115200 no_console_suspend mtdparts=denali-nand:1m@0x0(zloader),2m@0x100000(uboot),1m@0x300000(cpum0),2m@0x400000(nvro),8m@0x600000(nvrw),2m@0xe00000(nvfac),1m@0x1000000(fotaflag),7m@0x1100000(cpuphy),1m@0x1800000(sms),15m@0x1900000(cpuproxy),10m@0x2800000(cpuap),4m@0x3200000(cpfs),8m@0x3600000(ramdisk),7m@0x3e00000(recovery),6m@0x4500000(recovery-kernel),16m@0x4b00000(cdrom),80m@0x5b00000(userdata),60m@0xab00000(fotaupdate),2m@0xfc00000(securefs),4194303k@0x0(ddr) root=/dev/mtdblock16 rw rootfstype=jffs2 boot_reason=0"
+;&cmdline="console=ttyS0,115200 root=/dev/ram0 rw rdinit=/linuxrc mtdparts=denali-nand:1m@0x0(zloader),2m@0x100000(uboot),1m@0x300000(cpum0),1m@0x400000(nvro),8m@0x500000(nvrw),1m@0xd00000(fotaflag),9m@0xe00000(cpuzsp),1m@0x1700000(sms),15m@0x1800000(cpur7),10m@0x2700000(a9),1m@0x3100000(fotabackup),64m@0x3200000(fotaupdate),16m@0x7200000(cdrom),32m@0x8200000(userdata),80m@0xa200000(jffs2)"
+;&cmdline="console=ttyS0,115200 no_console_suspend mtdparts=denali-nand:1m@0x0(zloader),2m@0x100000(uboot),1m@0x300000(cpum0),1m@0x400000(nvro),8m@0x500000(nvrw),1m@0xd00000(fotaflag),9m@0xe00000(cpuzsp),1m@0x1700000(sms),15m@0x1800000(cpur7),10m@0x2700000(a9),1m@0x3100000(fotabackup),64m@0x3200000(fotaupdate),16m@0x7200000(cdrom),32m@0x8200000(userdata),80m@0xa200000(jffs2) root=/dev/mtdblock13 rw rootfstype=jffs2"
+;&cmdline="console=ttyS0,115200 no_console_suspend mtdparts=denali-nand:1m@0x0(zloader),2m@0x100000(uboot),1m@0x300000(cpum0),1m@0x400000(nvro),8m@0x500000(nvrw),2m@0xd00000(nvfac),1m@0xf00000(fotaflag),7m@0x1000000(cpuzsp),1m@0x1700000(sms),15m@0x1800000(cpur7),10m@0x2700000(cpuap),4m@0x3100000(cpfs),8m@0x3500000(ramdisk),7m@0x3d00000(recovery),6m@0x4400000(recovery-kernel),80m@0x4a00000(cdrom),40m@0x9a00000(userdata),30m@0xc200000(fotaupdate) root=/dev/mtdblock16 rw rootfstype=jffs2"
+&cmdline="console=ttyS1,115200 root=/dev/ram0 rw rdinit=/linuxrc"
+&cmdsize=(string.len("&cmdline")+16)&~0x3
+data.set &tagAddr %LONG %LE &cmdsize/4
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr %LONG %LE 0x54410009
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr "&cmdline" 0
+&tagAddr=&tagAddr+(&cmdsize-8)
+
+; ATAG_NONE
+data.set &tagAddr %LONG %LE 0x0
+&tagAddr=&tagAddr+0x4
+data.set &tagAddr %LONG %LE 0x0
+&tagAddr=&tagAddr+0x4
+
+
+enddo
+
+
diff --git a/ap/build/scripts/trace32/zx297520v3/boot_attach_CortexA53_ap.cmm b/ap/build/scripts/trace32/zx297520v3/boot_attach_CortexA53_ap.cmm
new file mode 100755
index 0000000..699170f
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/boot_attach_CortexA53_ap.cmm
@@ -0,0 +1,14 @@
+area.reset
+sys.cpu CortexM0
+sys.bdmclock 3.0MHz
+sys.o enreset OFF
+sys.attach
+break
+Wait 0.2s
+
+//stop m0 wdt
+data.set 0x0014801C %long 0x12340000 //m0
+
+//jtag0 to ap
+do .\sys\jtag_switch_script.cmm 0 1
+
diff --git a/ap/build/scripts/trace32/zx297520v3/console_evb.cmm b/ap/build/scripts/trace32/zx297520v3/console_evb.cmm
new file mode 100755
index 0000000..eb9b743
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/console_evb.cmm
@@ -0,0 +1,72 @@
+;--------------------------------------------------------------------------
+; Initialize SERIAL 0 as console for zx297520v3_fpga linux: 115200 8/N/1
+; created by xuzhiguo / ZTE-TSP at 03.18.2013
+;--------------------------------------------------------------------------
+&UART_BASE_SYS=0x1408000 // UART1 Base Address
+&DBGU_DR=&UART_BASE_SYS+0x4 // data Register
+&DBGU_SC=&UART_BASE_SYS+0x8 // special character Register
+&DBGU_FR=&UART_BASE_SYS+0x14 // flag Register
+&DBGU_IBRD=&UART_BASE_SYS+0x24 // integer Baud Rate Generator Register
+&DBGU_FBRD=&UART_BASE_SYS+0x28 // fractional Baud Rate Generator Register
+&DBGU_LCR_H=&UART_BASE_SYS+0x30 // Line Control Register
+&DBGU_CR=&UART_BASE_SYS+0x34 // Control Register
+&DBGU_IMSC=&UART_BASE_SYS+0x40 // Interrupt Mask Register
+
+&TOP_FUNC_SEL_BASE=0x0013C000 // 0-AON FUNC
+&AON_FUNC_SEL_BASE=0x0013C000 // 0-rxd or txd func
+&UART0_TOP_FUNC=&TOP_FUNC_SEL_BASE+0x10
+&UART0_AON_FUNC=&AON_FUNC_SEL_BASE+0
+
+// set gpio function to UART0 TX and RX
+;&tmp=data.long(D:&UART0_TOP_FUNC)
+;&tmp=&tmp&0xFFE7FFFF // AON func
+;&tmp=data.long(D:&UART0_AON_FUNC)
+;&tmp=&tmp&0xFFFF0FFF // UART FUNC
+
+//set uart1 works clock divison to 1
+; it is done in evb297510.cmm
+data.set 0x1400028 %long 0xfffff
+
+//disable uart
+data.set &DBGU_CR %LONG 0x0
+// mask all interrupt
+data.set &DBGU_IMSC %LONG 0x0
+
+// Set baud rate 115200
+data.set &DBGU_IBRD %LONG 0x38 //on EVB platform, uart work clock is 104MHz
+data.set &DBGU_FBRD %LONG 0x1B
+
+// set the port to no parity, no loopback, 8/N/1, enable FIFO
+data.set &DBGU_LCR_H %LONG 0x70
+
+
+
+// Enable
+data.set &DBGU_CR %LONG 0x301
+
+print "printing 'UART OK' on console"
+data.set &DBGU_DR %BYTE 0x0a //next line
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x0d //enter
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x55 //U
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x41 //A
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x52 //R
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x54 //T
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x20 //space
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x4f //O
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x4b //K
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x0a //next line
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x0d //enter
+wait 10.ms
+
+enddo
+
diff --git a/ap/build/scripts/trace32/zx297520v3/console_fpga.cmm b/ap/build/scripts/trace32/zx297520v3/console_fpga.cmm
new file mode 100755
index 0000000..0a405b9
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/console_fpga.cmm
@@ -0,0 +1,71 @@
+;--------------------------------------------------------------------------
+; Initialize SERIAL 0 as console for zx297520v3_fpga linux: 115200 8/N/1
+; created by xuzhiguo / ZTE-TSP at 03.18.2013
+;--------------------------------------------------------------------------
+&UART_BASE_SYS=0x1408000 // UART1 Base Address
+
+&DBGU_DR=&UART_BASE_SYS+0x4 // data Register
+&DBGU_SC=&UART_BASE_SYS+0x8 // special character Register
+&DBGU_FR=&UART_BASE_SYS+0x14 // flag Register
+&DBGU_IBRD=&UART_BASE_SYS+0x24 // integer Baud Rate Generator Register
+&DBGU_FBRD=&UART_BASE_SYS+0x28 // fractional Baud Rate Generator Register
+&DBGU_LCR_H=&UART_BASE_SYS+0x30 // Line Control Register
+&DBGU_CR=&UART_BASE_SYS+0x34 // Control Register
+&DBGU_IMSC=&UART_BASE_SYS+0x40 // Interrupt Mask Register
+
+&TOP_FUNC_SEL_BASE=0x0013C000 // 0-AON FUNC
+&AON_FUNC_SEL_BASE=0x0013C000 // 0-rxd or txd func
+&UART0_TOP_FUNC=&TOP_FUNC_SEL_BASE+0x10
+&UART0_AON_FUNC=&AON_FUNC_SEL_BASE+0
+
+// set gpio function to UART0 TX and RX
+;&tmp=data.long(D:&UART0_TOP_FUNC)
+;&tmp=&tmp&0xFFE7FFFF // AON func
+;&tmp=data.long(D:&UART0_AON_FUNC)
+;&tmp=&tmp&0xFFFF0FFF // UART FUNC
+
+//set uart1 works clock divison to 1
+; it is done in evb297510.cmm
+
+//disable uart
+data.set &DBGU_CR %LONG 0x0
+
+// mask all interrupt
+data.set &DBGU_IMSC %LONG 0x0
+
+// Set baud rate 115200
+data.set &DBGU_IBRD %LONG 0xD //on FPGA platform, uart work clock is 25MHz
+data.set &DBGU_FBRD %LONG 0x24
+
+// set the port to no parity, no loopback, 8/N/1, enable FIFO
+data.set &DBGU_LCR_H %LONG 0x70
+
+// Enable
+data.set &DBGU_CR %LONG 0x301
+
+print "printing 'UART OK' on console"
+data.set &DBGU_DR %BYTE 0x0a //next line
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x0d //enter
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x55 //U
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x41 //A
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x52 //R
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x54 //T
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x20 //space
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x4f //O
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x4b //K
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x0a //next line
+wait 10.ms
+data.set &DBGU_DR %BYTE 0x0d //enter
+wait 10.ms
+
+enddo
+
diff --git a/ap/build/scripts/trace32/zx297520v3/cpio_ramdisk.gz b/ap/build/scripts/trace32/zx297520v3/cpio_ramdisk.gz
new file mode 100755
index 0000000..a047374
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/cpio_ramdisk.gz
Binary files differ
diff --git a/ap/build/scripts/trace32/zx297520v3/linux.men b/ap/build/scripts/trace32/zx297520v3/linux.men
new file mode 100755
index 0000000..002b9db
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/linux.men
@@ -0,0 +1,901 @@
+; Linux specific menu
+
+add
+menu
+(
+ popup "&Linux"
+ (
+ default
+ menuitem "Display &Processes" "TASK.Process"
+ menuitem "Display &ps-like" "TASK.PS"
+ menuitem "Display &Tasks" "TASK.DTask"
+ menuitem "Display &Modules" "TASK.MODule"
+ popup "Display &File System"
+ (
+ menuitem "Display FS Types" "TASK.FS.Types"
+ menuitem "Display Mount Points" "TASK.FS.Mount"
+ menuitem "Display Mounted Devices" "TASK.FS.MountDevs"
+ menuitem "Display /proc" "TASK.FS.PROC"
+ menuitem "Display /sys" "TASK.FS.SYS"
+ )
+ separator
+ popup "&Process Debugging"
+ (
+ menuitem "&Load Symbols..."
+ (
+ dialog
+ (
+ header "TASK.sYmbol.LOAD"
+ pos 0. 0. 30. 3.
+ box "Process name"
+ pos 1. 1. 20. 1.
+procl: defedit "" ""
+ pos 22. 1. 7. 1.
+ button "Browse..."
+ (
+ dialog.file "*"
+ entry %line &file
+ dialog.set procl "&file"
+ )
+ pos 6. 3. 7. 1.
+ defbutton "Ok"
+ (
+ local &procl &cwd
+ &procl=dialog.string(procl)
+ TASK.sYmbol.LOAD "&procl"
+ dialog.end
+ )
+ pos 17. 3. 7. 1.
+ button "Cancel" "dialog.end"
+ )
+ )
+ menuitem "&Delete Symbols..."
+ (
+ dialog
+ (
+ header "TASK.sYmbol.DELete"
+ pos 0. 0. 30. 3.
+ box "Process name"
+ pos 1. 1. 20. 1.
+procd: defedit "" ""
+ pos 22. 1. 7. 1.
+ button "Browse..."
+ (
+ dialog.file "*"
+ entry %line &file
+ dialog.set procd "&file"
+ )
+ pos 6. 3. 7. 1.
+ defbutton "Ok"
+ (
+ local &procd
+ &procd=dialog.string(procd)
+ TASK.sYmbol.DELete "&procd"
+ dialog.end
+ )
+ pos 17. 3. 7. 1.
+ button "Cancel" "dialog.end"
+ )
+ )
+ menuitem "Debug Process on main..."
+ (
+
+ &cpufamily=string.lwr(cpufamily())
+ do ~~/demo/&cpufamily/kernel/linux/app_debug /dialog
+
+ )
+ addhere
+ popup "&Watch Processes"
+ (
+ menuitem "&Add..."
+ (
+ dialog
+ (
+ header "TASK.Watch.Add"
+ pos 0. 0. 24. 3.
+ box "Process name"
+ pos 1. 1. 22. 1.
+wproca: defedit "" ""
+ pos 2. 3. 7. 1.
+ defbutton "Ok"
+ (
+ local &wproca
+ &wproca=dialog.string(wproca)
+ TASK.Watch.View "&wproca"
+ dialog.end
+ )
+ pos 15. 3. 7. 1.
+ button "Cancel" "dialog.end"
+ )
+ )
+ menuitem "&Remove..."
+ (
+ dialog
+ (
+ header "TASK.Watch.DELete"
+ pos 0. 0. 24. 3.
+ box "Process name"
+ pos 1. 1. 22. 1.
+wprocd: defedit "" ""
+ pos 2. 3. 7. 1.
+ defbutton "Ok"
+ (
+ local &wprocd
+ &wprocd=dialog.string(wprocd)
+ TASK.Watch.DELete "&wprocd"
+ dialog.end
+ )
+ pos 15. 3. 7. 1.
+ button "Cancel" "dialog.end"
+ )
+ )
+ )
+ separator
+ menuitem "Scan Process MMU Pages..."
+ (
+ dialog
+ (
+ header "MMU.SCAN TaskPageTable"
+ pos 0. 0. 24. 3.
+ box "Process name"
+ pos 1. 1. 22. 1.
+wproca: defedit "" ""
+ pos 2. 3. 7. 1.
+ defbutton "Ok"
+ (
+ local &wproca
+ &wproca=dialog.string(wproca)
+ MMU.SCAN TaskPageTable "&wproca"
+ dialog.end
+ )
+ pos 15. 3. 7. 1.
+ button "Cancel" "dialog.end"
+ )
+ )
+ menuitem "Scan All MMU Tables" "MMU.SCAN.ALL"
+ ;separator
+ ;menuitem "Help Process Debugging" "HELP __RTOS_LINUX__S_User_Processes"
+ )
+ popup "&Module Debugging"
+ (
+ menuitem "&Load Symbols..."
+ (
+ dialog
+ (
+ header "TASK.sYmbol.LOADMod"
+ pos 0. 0. 30. 3.
+ box "Module name"
+ pos 1. 1. 20. 1.
+modl: defedit "" ""
+ pos 22. 1. 7. 1.
+ button "Browse..."
+ (
+ dialog.file "*.ko"
+ entry %line &file
+ dialog.set modl "&file"
+ )
+ pos 6. 3. 7. 1.
+ defbutton "Ok"
+ (
+ local &modl
+ &modl=dialog.string(modl)
+ TASK.sYmbol.LOADMod "&modl"
+ dialog.end
+ )
+ pos 17. 3. 7. 1.
+ button "Cancel" "dialog.end"
+ )
+ )
+ menuitem "&Delete Symbols..."
+ (
+ dialog
+ (
+ header "TASK.sYmbol.DELeteMod"
+ pos 0. 0. 30. 3.
+ box "Module name"
+ pos 1. 1. 20. 1.
+modd: defedit "" ""
+ pos 22. 1. 7. 1.
+ button "Browse..."
+ (
+ dialog.file "*.ko"
+ entry %line &file
+ dialog.set modd "&file"
+ )
+ pos 6. 3. 7. 1.
+ defbutton "Ok"
+ (
+ local &modd
+ &modd=dialog.string(modd)
+ TASK.sYmbol.DELeteMod "&modd"
+ dialog.end
+ )
+ pos 17. 3. 7. 1.
+ button "Cancel" "dialog.end"
+ )
+ )
+ menuitem "Debug Module on init..."
+ (
+
+ &cpufamily=string.lwr(cpufamily())
+ do ~~/demo/&cpufamily/kernel/linux/mod_debug /dialog
+
+ )
+ separator
+ menuitem "Scan All MMU Tables" "MMU.SCAN.ALL"
+ )
+ popup "&Library Debugging"
+ (
+ menuitem "&Load Symbols..."
+ (
+ dialog
+ (
+ header "TASK.sYmbol.LOADLib"
+ pos 0. 0. 30. 3.
+ box "Process name"
+ pos 1. 1. 28. 1.
+libpl: defedit "" ""
+ pos 0. 3. 30. 3.
+ box "Library name"
+ pos 1. 4. 20. 1.
+libll: defedit "" ""
+ pos 22. 4. 7. 1.
+ button "Browse..."
+ (
+ dialog.file "*.so*"
+ entry %line &file
+ dialog.set libll "&file"
+ )
+ pos 6. 6. 7. 1.
+ defbutton "Ok"
+ (
+ local &libpl &libll
+ &libpl=dialog.string(libpl)
+ &libll=dialog.string(libll)
+ TASK.sYmbol.LOADLib "&libpl" "&libll"
+ dialog.end
+ )
+ pos 17. 6. 7. 1.
+ button "Cancel" "dialog.end"
+ )
+ )
+ menuitem "&Delete Symbols..."
+ (
+ dialog
+ (
+ header "TASK.sYmbol.DELeteLib"
+ pos 0. 0. 30. 3.
+ box "Process name"
+ pos 1. 1. 28. 1.
+libpd: defedit "" ""
+ pos 0. 3. 30. 3.
+ box "Library name"
+ pos 1. 4. 20. 1.
+libld: defedit "" ""
+ pos 22. 4. 7. 1.
+ button "Browse..."
+ (
+ dialog.file "*.so*"
+ entry %line &file
+ dialog.set libld "&file"
+ )
+ pos 6. 6. 7. 1.
+ defbutton "Ok"
+ (
+ local &libpd &libld
+ &libpd=dialog.string(libpd)
+ &libld=dialog.string(libld)
+ TASK.sYmbol.DELeteLib "&libpd" "&libld"
+ dialog.end
+ )
+ pos 17. 6. 7. 1.
+ button "Cancel" "dialog.end"
+ )
+ )
+ separator
+ menuitem "Scan Process MMU Pages..."
+ (
+ dialog
+ (
+ header "MMU.SCAN TaskPageTable"
+ pos 0. 0. 24. 3.
+ box "Process name"
+ pos 1. 1. 22. 1.
+wproca: defedit "" ""
+ pos 2. 3. 7. 1.
+ defbutton "Ok"
+ (
+ local &wproca
+ &wproca=dialog.string(wproca)
+ MMU.SCAN TaskPageTable "&wproca"
+ dialog.end
+ )
+ pos 15. 3. 7. 1.
+ button "Cancel" "dialog.end"
+ )
+ )
+ menuitem "Scan All MMU Tables" "MMU.SCAN.ALL"
+ )
+ separator
+ popup "Symbol &Autoloader"
+ (
+ menuitem "List Components" "sYmbol.AutoLoad.List"
+ menuitem "Check Now!" "sYmbol.AutoLoad.CHECK"
+ menuitem "Set Components Checked"
+ (
+ dialog
+ (
+ header "TASK.sYmbol.Option AutoLoad"
+ pos 0. 0. 25.
+ proc: checkbox "Process (Processes)"
+ (
+ if dialog.boolean(proc)
+ TASK.sYmbol.Option AutoLoad Process
+ else
+ TASK.sYmbol.Option AutoLoad NoProcess
+ )
+ mod: checkbox "Module (Modules)"
+ (
+ if dialog.boolean(mod)
+ TASK.sYmbol.Option AutoLoad Module
+ else
+ TASK.sYmbol.Option AutoLoad NoModule
+ )
+ lib: checkbox "Library (All Libraries)"
+ (
+ if dialog.boolean(lib)
+ TASK.sYmbol.Option AutoLoad Library
+ else
+ TASK.sYmbol.Option AutoLoad NoLibrary
+ dialog.set clib "FALSE"
+ )
+ clib: checkbox "CurrLib (Libraries of Current Process)"
+ (
+ if dialog.boolean(clib)
+ TASK.sYmbol.Option AutoLoad CurrLib
+ else
+ TASK.sYmbol.Option AutoLoad NoLibrary
+ dialog.set lib "FALSE"
+ )
+ )
+ dialog.set proc ((task.y.o(autoload)&0x1)!=0)
+ dialog.set mod ((task.y.o(autoload)&0x4)!=0)
+ dialog.set lib ((task.y.o(autoload)&0x2)!=0)
+ dialog.set clib ((task.y.o(autoload)&0x8)!=0)
+ )
+ separator
+ menuitem "Set Loader Script"
+ (
+ dialog
+ (
+ header "sYmbol.AutoLoad.CHECKLINUX"
+ pos 0. 0. 40. 3.
+ box "autoload batch script"
+ pos 1. 1. 30. 1
+cmmfile: edit "autoload.cmm" ""
+ pos 32. 1. 7. 1.
+ button "Browse..."
+ (
+ dialog.file "*.cmm"
+ entry %line &file
+ dialog.set cmmfile "&file"
+ )
+ pos 1. 3. 16. 1.
+checkon: checkbox "automatic check" ""
+ pos 4. 4.5 8.
+ defbutton "Ok"
+ (
+ local &log &cmm
+ &cmm=dialog.string(cmmfile)
+ sYmbol.AutoLoad.CHECKLINUX "do &cmm "
+ sYmbol.AutoLoad.CHECK ; trigger check manually
+ if dialog.boolean(checkon)
+ sYmbol.AutoLoad.CHECK ON ; automatic check enabled
+ else
+ sYmbol.AutoLoad.CHECK OFF ; automatic check disabled
+ dialog.end
+ )
+ pos 16. 4.5 8.
+ button "Cancel" "dialog.end"
+ pos 28. 4.5 8.
+ button "Help" "HELP __RTOS_LINUX_S_Y_ALOAD"
+ )
+ )
+ menuitem "Set Target Root Path"
+ (
+ dialog
+ (
+ header "TASK.sYmbol.Option ROOTPATH"
+ pos 0. 0. 40. 3.
+ box "target root path on host"
+ pos 1. 1. 30. 1
+rootdir: edit "" ""
+ pos 32. 1. 7. 1.
+ button "Browse..."
+ (
+ dialog.dir "*"
+ entry %line &dir
+ dialog.set rootdir "&dir"
+ )
+ pos 4. 3.5 8.
+ defbutton "Ok"
+ (
+ local &dir
+ &dir=dialog.string(rootdir)
+ TASK.sYmbol.Option ROOTPATH "&dir"
+ dialog.end
+ )
+ pos 16. 3.5 8.
+ button "Cancel" "dialog.end"
+ pos 28. 3.5 8.
+ button "Help" "HELP __RTOS_LINUX__TASK_Y_O_ROOTPATH"
+ )
+ )
+ separator
+ menuitem "Symbol Autoloader Help" "HELP __RTOS_LINUX_S_Y_ALOAD"
+ )
+ separator
+ menuitem "&Linux Terminal"
+ (
+ if !window.name(term)
+ (
+ winpos ,,,,,, term
+ TERM
+ )
+ else
+ wintop term
+ )
+ menuitem "Configure Terminal..."
+ (
+ if window.name(term)
+ dialog.ok "Please close terminal window first!"
+ else
+ (
+ dialog
+ (
+ header "TERM.Protocol"
+ pos 0. 0. 9.
+ tp.be: choosebox "BufferE"
+ (
+ dialog.disable tp.com.dev
+ dialog.disable tp.com.bd
+ dialog.enable tp.be.out
+ dialog.enable tp.be.in
+ )
+ pos 10. 0. 5.
+ text "out:"
+ pos 15. 0. 6.
+ tp.be.out: edit "T32OUTBUF" ""
+ pos 23. 0. 6.
+ text "in:"
+ pos 29. 0. 6.
+ tp.be.in: edit "T32INBUF" ""
+ pos 0. 1. 9.
+ tp.dcc: choosebox "DCC"
+ (
+ dialog.disable tp.com.dev
+ dialog.disable tp.com.bd
+ dialog.disable tp.be.out
+ dialog.disable tp.be.in
+ )
+ pos 0. 2. 9.
+ tp.com: choosebox "COM"
+ (
+ dialog.disable tp.be.out
+ dialog.disable tp.be.in
+ dialog.enable tp.com.dev
+ dialog.enable tp.com.bd
+ )
+ pos 10. 2. 5.
+ text "device:"
+ pos 15. 2. 6.
+ tp.com.dev: edit "COM1" ""
+ pos 23. 2. 6.
+ text "baudrate:"
+ pos 29. 2. 6.
+ tp.com.bd: edit "115200." ""
+ pos 9. 3.5 7.
+ defbutton "Ok"
+ (
+ &tpbeout=dialog.string(tp.be.out)
+ &tpbein=dialog.string(tp.be.in)
+ &tpcomdev=dialog.string(tp.com.dev)
+ &tpcombd=dialog.string(tp.com.bd)
+ if dialog.boolean(tp.be)
+ TERM.METHOD BufferE &tpbeout &tpbein
+ else if dialog.boolean(tp.dcc)
+ TERM.METHOD DCC
+ else if dialog.boolean(tp.com)
+ TERM.METHOD COM &tpcomdev &tpcombd 8 NONE 1STOP NONE
+ dialog.end
+ )
+ pos 19. 3.5 7.
+ button "Cancel" "dialog.end"
+ )
+ dialog.disable tp.be.out
+ dialog.disable tp.be.in
+ dialog.disable tp.com.dev
+ dialog.disable tp.com.bd
+ if cpufamily()!="ARM"
+ dialog.disable tp.dcc
+ )
+ )
+ ;separator
+ ;popup "&Stack Coverage"
+ ;(
+ ; menuitem "&List Stacks"
+ ; (
+ ; if icd()||simulator()
+ ; TASK.STacK.PATtern 0
+ ; TASK.STacK
+ ; )
+ ; menuitem "Add Task" "TASK.STacK.ADD"
+ ; menuitem "Remove Task" "TASK.STacK.ReMove"
+ ; enable ice()||fire()
+ ; menuitem "&Reset Coverage" "TASK.STacK.RESet"
+ ;)
+ separator
+ menuitem "Help Linux Awareness" "HELP __RTOS_LINUX_S_"
+ )
+ popup "Trace"
+ (
+ popup "List"
+ (
+ separator
+ menuitem "&Task Switches" "Trace.List List.TASK"
+ menuitem "&Default and Tasks" "Trace.List List.TASK DEFault"
+ )
+ )
+ popup "Perf"
+ (
+ separator
+ popup "&Task Runtime"
+ (
+ menuitem "&Prepare"
+ (
+ if t.method.analyzer()
+ (
+ Analyzer.AutoInit on
+ )
+ if (ice()||fire())&&!a.mode.flow()
+ (
+ Analyzer.ReProgram
+ (
+ Sample.Enable if AlphaBreak&&Write
+ )
+ Break.Delete /Alpha
+ Break.Set task.config(magic)++(task.config(magicsize)-1) /Alpha
+ )
+ if a.mode.flow()
+ (
+ Break.Delete /TraceEnable
+ Break.Set task.config(magic) /TraceEnable
+ )
+ )
+ menuitem "[:perf]Show &Numerical" "Trace.STATistic.TASK"
+ menuitem "[:achart]Show as &Timing" "Trace.CHART.TASK"
+ menuitem "[:achart]Tracking with Trace &List"
+ (
+ Trace.List List.TASK DEFault /Track
+ Trace.CHART.TASK /Track
+ )
+ )
+ popup "Task &Function Runtime"
+ (
+ menuitem "&Prepare"
+ (
+ if t.method.analyzer()
+ (
+ Analyzer.AutoInit on
+ Analyzer.STATistic.PreFetch on
+ )
+
+ if (ice()||fire())&&!a.mode.flow()
+ (
+ if a.config.hac()
+ (
+ Analyzer.ReProgram
+ (
+ Sample.Enable if AlphaBreak
+ Sample.Enable if BetaBreak
+ Mark.A if AlphaBreak
+ Mark.B if BetaBreak
+ )
+ )
+ else
+ (
+ Analyzer.ReProgram
+ (
+ Sample.Enable if AlphaBreak||BetaBreak
+ Mark.A if AlphaBreak
+ Mark.B if BetaBreak
+ )
+ )
+ Break.Delete /Alpha /Beta /Charly
+ Break.SetFunc
+ Break.Set task.config(magic)++(task.config(magicsize)-1) /Alpha
+ )
+ if a.mode.flow()
+ (
+ Break.Delete /TraceData
+ Break.Set task.config(magic) /TraceData
+ )
+ )
+ menuitem "[:perf]Show &Numerical" "Trace.STATistic.TASKFUNC"
+ menuitem "[:perf]Show as &Tree" "Trace.STATistic.TASKTREE"
+ menuitem "[:perf]Show &Detailed Tree" "Trace.STATistic.TASKTREE ALL"
+ menuitem "[:achart]Show as &Timing" "Trace.CHART.TASKFUNC"
+ menuitem "[:alist]Show N&esting" "Trace.List List.TASK FUNC TI.FUNC"
+ )
+ popup "Task &Status"
+ (
+ menuitem "&Prepare"
+ (
+ if t.method.analyzer()
+ (
+ Analyzer.AutoInit on
+ )
+ if (ice()||fire())&&!a.mode.flow()
+ (
+ Analyzer.ReProgram
+ (
+ Sample.Enable if AlphaBreak&&Write
+ )
+ Break.Delete /Alpha
+ Break.Set task.config(magic)++(task.config(magicsize)-1) /Alpha
+ TASK.TASKState
+ )
+ )
+ menuitem "[:perf]Show &Numerical" "Trace.STATistic.TASKSTATE"
+ menuitem "[:achart]Show as &Timing" "Trace.CHART.TASKSTATE"
+ menuitem "[:achart]Tracking with Trace &List"
+ (
+ Trace.List List.TASK DEFault /Track
+ Trace.CHART.TASKSTATE /Track
+ )
+ )
+ )
+ popup "&Help"
+ (
+ menuitem "Linux Awareness Manual" "HELP __RTOS_LINUX_S_"
+ )
+)
+
+
+menu "task.dt"
+(
+ default
+ menuitem "Display detailed"
+ (
+ &address=address.offset(track.address())
+ TASK.DTask &address
+ )
+ menuitem "Display task struct"
+ (
+ &address=task.proc.tcb(address.offset(track.address()))
+ Var.View %m %s (struct task_struct)*&address
+ )
+ separator
+ menuitem "Display Stack Frame" "Var.Frame /Locals /Caller /Task track.address()"
+ menuitem "Display Registers" "Register /Task track.address()"
+ menuitem "Switch Context" "Register.TASK track.address()"
+ separator
+ menuitem "Load Process Symbols" "TASK.sYmbol.LOAD track.address()"
+ menuitem "Delete Process Symbols" "TASK.sYmbol.DELete track.address()"
+ menuitem "Add Libraries to Symbol Autoloader"
+ (
+ TASK.sYmbol.Option AutoLoad ProcLib track.address()
+ sYmbol.AutoLOAD.CHECK
+ )
+ menuitem "Add to Watched Processes"
+ (
+ &address=address.offset(track.address())
+ TASK.Watch.View &address
+ )
+ menuitem "Delete from Watched Processes" "TASK.Watch.DELete track.address()"
+ ;separator
+ ;menuitem "Add to Stack Cov" "TASK.STK.ADD address.offset(track.address())"
+ ;menuitem "Rm from Stack Cov" "TASK.STK.RM address.offset(track.address())"
+ separator
+ menuitem "Scan MMU Pages"
+ (
+ &address=address.offset(track.address())
+ MMU.SCAN TaskPageTable &address
+ )
+ separator
+ menuitem "Dump task entry"
+ (
+ &address=task.proc.tcb(address.offset(track.address()))
+ Data.dump &address /l /dialog
+ )
+ separator
+ menuitem "Kill task"
+ (
+ local &rkmagic &rktname
+ &rkmagic=task.proc.tcb(address.offset(track.address()))
+ &rktname=task.proc.name(&rkmagic)
+ dialog.yesno "Really kill task &rktname?"
+ entry &yn
+ if &yn
+ (
+ var.set ((struct task_struct)*&rkmagic).pending.signal.sig[0]=0x100
+ print "Signal SIGKILL sent to task &rktname"
+ )
+ )
+ separator
+ enable t.method.analyzer()
+ menuitem "Trace this task"
+ (
+ local &magic
+ if run()
+ break
+ &magic=address.offset(track.address())
+ &sid=task.proc.magic2sid(&magic)
+ if etm.contextcomp()>0
+ (
+ TrOnchip.ContextID ON
+ Break.Set &sid:0--0xffffffff /Program /TraceEnable /TASK &magic
+ )
+ else
+ (
+ Break.Set task.config(magic) /Write /Data &magic /TraceON
+ Break.Set task.config(magic) /Write /Data !&magic /TraceOFF
+ )
+ )
+)
+
+
+menu "task.mod"
+(
+ default
+ ;menuitem "Display detailed"
+ ;(
+ ; &address=address.offset(track.address())
+ ; TASK.MODule &address
+ ;)
+ menuitem "Display module struct"
+ (
+ &address=task.mod.mcb(address.offset(track.address()))
+ Var.View %m %s (struct module)*&address
+ )
+ separator
+ menuitem "Load Module Symbols" "TASK.sYmbol.LOADMod track.address()"
+ menuitem "Delete Module Symbols" "TASK.sYmbol.DELeteMod track.address()"
+ separator
+ menuitem "Dump module entry"
+ (
+ &address=address.offset(track.address())
+ Data.dump &address /l /dialog
+ )
+)
+
+
+menu "task.fs.t"
+(
+ default
+ menuitem "Display detailed"
+ (
+ &address=address.offset(track.address())
+ TASK.FS.Types &address
+ )
+ menuitem "Display type struct"
+ (
+ &address=address.offset(track.address())
+ Var.View %m %s (struct file_system_type)*&address
+ )
+ separator
+ menuitem "Dump type entry"
+ (
+ &address=address.offset(track.address())
+ Data.dump &address /l /dialog
+ )
+)
+
+
+menu "task.fs.md"
+(
+ default
+ menuitem "Display detailed"
+ (
+ &address=address.offset(track.address())
+ TASK.FS.MountDevs &address
+ )
+ menuitem "Display superblock struct"
+ (
+ &address=address.offset(track.address())
+ Var.View %m %s (struct super_block)*&address
+ )
+ separator
+ menuitem "Dump superblock entry"
+ (
+ &address=address.offset(track.address())
+ Data.dump &address /l /dialog
+ )
+)
+
+
+menu "task.fs.proc"
+(
+ ;default
+ ;menuitem "Display detailed"
+ ;(
+ ; &address=address.offset(track.address())
+ ; TASK.FS.PROC &address
+ ;)
+ menuitem "Display proc struct"
+ (
+ &address=address.offset(track.address())
+ Var.View %m %s (struct proc_dir_entry)*&address
+ )
+ separator
+ menuitem "Dump proc dir entry"
+ (
+ &address=address.offset(track.address())
+ Data.dump &address /l /dialog
+ )
+)
+
+
+menu "task.fs.m"
+(
+ default
+ ;menuitem "Display detailed"
+ ;(
+ ; &address=address.offset(track.address())
+ ; TASK.FS.Mount &address
+ ;)
+ menuitem "Display mount struct"
+ (
+ &address=address.offset(track.address())
+ Var.View %o %h %s (struct vfsmount)*&address
+ )
+ separator
+ menuitem "Dump mount entry"
+ (
+ &address=address.offset(track.address())
+ Data.dump &address /l /dialog
+ )
+)
+
+
+menu "task.lib"
+(
+ default
+ ;menuitem "Display detailed"
+ ;(
+ ; &address=address.offset(track.address())
+ ; TASK.DTask &address
+ ;)
+ menuitem "Display Library struct"
+ (
+ &address=address.offset(track.address())
+ Var.View %m %s (struct vm_area_struct)*&address
+ )
+ separator
+ menuitem "Load Library Symbols" "TASK.sYmbol.LOADLib track.string() track.address()"
+ menuitem "Delete Library Symbols" "TASK.sYmbol.DELeteLib track.string() track.address()"
+ separator
+ menuitem "Dump Library entry"
+ (
+ &address=address.offset(track.address())
+ Data.dump &address /l /dialog
+ )
+)
+
+
+menu "task.w"
+(
+ default
+ menuitem "Display Process"
+ (
+ &address=address.offset(track.address())
+ TASK.DTask &address
+ )
+ menuitem "Delete from List"
+ (
+ &name=track.string()
+ TASK.Watch.DELete "&name"
+ )
+)
+
+
diff --git a/ap/build/scripts/trace32/zx297520v3/linux.t32 b/ap/build/scripts/trace32/zx297520v3/linux.t32
new file mode 100755
index 0000000..290bff2
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/linux.t32
Binary files differ
diff --git a/ap/build/scripts/trace32/zx297520v3/linux_297520V3_restore_ramdump_linux-kernel.cmm b/ap/build/scripts/trace32/zx297520v3/linux_297520V3_restore_ramdump_linux-kernel.cmm
new file mode 100755
index 0000000..b161213
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/linux_297520V3_restore_ramdump_linux-kernel.cmm
@@ -0,0 +1,63 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2012 ZTE Corporation.
+//*
+//**************************************************************************
+//* Ä£ ¿é Ãû :
+//* ÎÄ ¼þ Ãû : linux_297510_restore_ramdump_linux-kernel.cmm
+//* Ïà¹ØÎļþ :
+//* ʵÏÖ¹¦ÄÜ : 7510 linux ramdump»Ö¸´½Å±¾£»
+//* ×÷ Õß : JKZ
+//* °æ ±¾ : V1.0
+//* Íê³ÉÈÕÆÚ : 2015/12/12
+//* ÆäËü˵Ã÷ :
+//**************************************************************************
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &elfname
+local &target_state_cmm
+local &dumpdir
+
+sys.down
+area.reset
+sys.cpu CortexA9
+sys.jtagclock 3.0MHz ; CPU needs 10M * 8 = 80M frequency. It should be reduced to 3.0MHz
+sys.option enreset Off
+sys.option resbreak off
+sys.up
+
+DIALOG.File *
+entry &elfname
+&dumpdir=os.file.path(&elfname)
+
+DIALOG.File *.cmm
+entry &target_state_cmm
+&dumpdir=os.file.path(&target_state_cmm)
+
+//¼ÓÔØelfÎļþ
+data.load.elf &elfname /nocode
+
+//ÉèÖÃÔ´ÎļþµÄ·¾¶ÐÅÏ¢,ÐèÊÖ¶¯ÉèÖóɱ¾µØ¶ÔӦ·¾¶
+symbol.sourcepath.reset
+;sYmbol.SourcePATH.SetRecurseDir \\10.42.218.169\plat\public\daikang\zhouguopo\patch-diff-test\7520V2\ZMP_BASE_SVN\AP\linux_plat\base\linux\kernels\linux-3.4.5
+;sYmbol.SourcePATH.SetRecurseDir \\10.42.217.237\zhaojunkui\project\7520-uClinux-real\7520MV2.3.0B01\CPU_R7\platform
+
+//¼ÓÔØramdump
+do &target_state_cmm &dumpdir
+
+//ÉèÖÃMMUÆô¶¯
+TRANSlation.TableWalk ON ;debugger uses table walk to decode virtual address
+TRANSlation.ON ;switch on debugger address translation
+
+TASK.CONFIG linux //Init Multitask Debugger
+MENU.ReProgram linux //Init ARTK Spezific Menu Part's
+TASK.STacK.PATTERN 0xCC //Init stack space with 0xCC
+//´úÂë¶Î±È½Ï
+do ./os_code_compare.cmm
+do ./linux_cpko_attach.cmm
+enddo
+
diff --git a/ap/build/scripts/trace32/zx297520v3/linux_297520v3_evb.cmm b/ap/build/scripts/trace32/zx297520v3/linux_297520v3_evb.cmm
new file mode 100755
index 0000000..eb716c4
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/linux_297520v3_evb.cmm
@@ -0,0 +1,173 @@
+;--------------------------------------------------------------------------
+;
+; Linux Demo for TRACE32 multitask debugger
+;
+; This batchfile demonstrates the use of
+; the Multitask-Debugger for Linux
+;
+; The example is generated for the evb297520v2fpga board using an ICD.
+; It will NOT run on any other board, but may be used as a template for
+; others.
+; Linux is downloaded to the board via ICD.
+;
+; modified by ZTE-TSP at 2015.08.07
+;
+; NOTICE:
+; this script can only be used on NO jtag chain mode
+;--------------------------------------------------------------------------
+
+;do ./7520V2_DDR_1Gb_312.cmm
+
+GLOBAL &VMLINUX_PATH
+GLOBAL &INITRD_PATH
+GLOBAL &SOURCE_PATH
+GLOBAL &DDR_BASE
+GLOBAL &INITRD_LOAD_ADDR
+GLOBAL &IMAGE_LOAD_ADDR
+
+&VMLINUX_PATH= "..\..\linux_plat\base\linux\kernels\linux-3.4.5\vmlinux"
+&IMAGE_PATH="..\..\linux_plat\base\linux\kernels\linux-3.4.5\zImage"
+&INITRD_PATH= ".\cpio_ramdisk.gz"
+&SOURCE_PATH="..\..\linux_plat\base\linux\kernels\linux-3.4.5"
+&DDR_BASE=0x22300000
+&INITRD_LOAD_ADDR=&DDR_BASE+0xA00000
+&IMAGE_LOAD_ADDR=&DDR_BASE+0x8000
+
+area.reset
+print "resetting..."
+TASK.RESet
+sYmbol.RESet
+MMU.RESet
+
+;do ./boot.cmm
+
+; setup of ICD
+
+ print "initializing..."
+sys.cpu CortexA53
+SYStem.Option MMUSPACES ON ; enable space ids to virtual addresses
+SYStem.JtagClock 3.0MHz ; use adaptive clocking for most speed
+sys.option enreset Off
+sys.option resbreak off
+
+Sys.Config.COREBASE 0x80410000 ; Cortex-A53
+Sys.Config.CTIBASE 0x80420000
+Sys.Config.debugaccessport 0
+Sys.Mode PREPARE
+Wait 0.1s
+
+sys.up
+;data.set 0x01306100 %long 0xffffffff ;DDR config
+
+SETUP.IMASKASM ON ; lock interrupts while single steppingle stepping
+ ;l2 divison -- no need
+; data.set 0x00803004 %LE %LONG 0x33111;
+
+//A9 select 624M, bit0-2, 0=26, 1=624, 2=480, 3=312, 4=156
+;data.set 0x01306040 %long 0x00000001
+
+; Target Setup: initialize LPDDR controller and peripherals(e.g. UART1)
+print "initialize board ..."
+
+; use the debugger to initialize it
+; do basic setup on board;
+; we don't need this step on zx297510 platform, because jtag_debug code or T32 script has run before this step.
+; jtag_debug code or T32 script running on cortex-m0 initiates system clock, DDR, gpio multiplex, and so on....
+
+do .\console_evb.cmm ; setup serial console
+
+; Load the Linux kernel
+
+; If you are using a flashed kernel, or if you're
+; loading your kernel via TFTP, use the boot monitor
+; to do so.
+
+; Use the next lines only to load the kernel into
+; RAM using the debugger.
+
+; vmlinux starts physically at RAM start (=0x28000000) + 0x8000
+; (see arch/arm/kernel/head-armv.S)
+print "loading Linux image..."
+;Data.LOAD.Binary &IMAGE_PATH &IMAGE_LOAD_ADDR ; loading zImage here, it will uncompress itself
+;data.load.elf &VMLINUX_PATH (&DDR_BASE+0x8000) /gnu /nosymbol
+Register.RESet
+
+ Data.LOAD.Elf &VMLINUX_PATH 0x22308000-0xc0008000 /gnu /nosymbol
+
+; Set PC on start address of image
+Register.Set PC (&DDR_BASE+0x8000)
+
+
+; Set machine type in R1; see arch/arm/tools/mach-types 7520 = 0x1d63
+Register.Set R1 0x1d63
+
+; Set parameter tags for linux boot
+do .\atag-list.cmm
+Register.Set R2 (&DDR_BASE+0x0100)
+
+; Loading RAM disk
+print "loading ram disk"
+
+; Load ram file system image into ram disk
+;Data.LOAD.Binary &INITRD_PATH &INITRD_LOAD_ADDR
+Data.LOAD.Binary &INITRD_PATH &INITRD_LOAD_ADDR /noclear /nosymbol
+
+; Load the Linux kernel symbols into the debugger
+print "loading Linux kernel symbols..."
+Data.LOAD.Elf &VMLINUX_PATH /gnu /nocode /strippart "linux-3.4.5" /SourcePATH ..\linux-3.4.5
+;Data.LOAD.Elf &VMLINUX_PATH /gnu /nocode /SourcePATH ..\linux-3.4.5
+
+; Open a Code Window -- we like to see something
+Data.List
+
+
+; Run over MMU & Interrupt initialization
+
+ ;Go __init_end /Onchip
+ ;print "initializing target and debugger MMU..."
+ ;wait !run()
+
+ ; Map the virtual kernel symbols to physical addresses
+ ; to give the debugger access to it before CPU MMU is
+ ; initialized
+ MMU.FORMAT LINUX swapper_pg_dir 0xc0000000--0xc0ffffff &DDR_BASE
+ TRANSlation.COMMON 0xbf000000--0xffffffff ; common area for kernel and processes
+ TRANSlation.TableWalk ON ;debugger uses table walk to decode virtual address
+ TRANSlation.ON ;switch on debugger address translation
+
+ ; set source path
+ print "set source path ..."
+ ;sYmbol.SourcePATH.RESet
+ sYmbol.SourcePATH.SetBaseDir &SOURCE_PATH
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\arch\arm\mach-zx297520v3
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\arch\arm
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\init
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\kernel
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\tty
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\clk
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\gpio
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\dma
+; sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers
+
+
+ ; Note that the Linux awareness needs the kernel symbols to work
+ print "initializing multitask support..."
+ TASK.CONFIG .\linux ; loads Linux awareness (linux.t32)
+ MENU.ReProgram .\linux ; loads Linux menu (linux.men)
+ HELP.FILTER.Add rtoslinux ; add linux awareness manual to help filter
+ MENU.ReProgram .\sys\board ; add board tools
+
+; switch on symbol autoloader
+sYmbol.AutoLoad.CHECKLINUX "do "+os.ppd()+"/autoload "
+ ; Group kernel area to be displayed with red bar
+
+ GROUP.Create "kernel" 0xc0000000--0xffffffff /RED
+ GROUP.Create "module" 0xbf000000--0xbfffffff /blue
+; Ok, we're done, let's start Linux
+
+ SYStem.Option MMUSPACES OFF
+
+
+
+enddo
+
diff --git a/ap/build/scripts/trace32/zx297520v3/linux_297520v3_fpga.cmm b/ap/build/scripts/trace32/zx297520v3/linux_297520v3_fpga.cmm
new file mode 100755
index 0000000..de93204
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/linux_297520v3_fpga.cmm
@@ -0,0 +1,173 @@
+;--------------------------------------------------------------------------
+;
+; Linux Demo for TRACE32 multitask debugger
+;
+; This batchfile demonstrates the use of
+; the Multitask-Debugger for Linux
+;
+; The example is generated for the evb297520v2fpga board using an ICD.
+; It will NOT run on any other board, but may be used as a template for
+; others.
+; Linux is downloaded to the board via ICD.
+;
+; modified by ZTE-TSP at 2015.08.07
+;
+; NOTICE:
+; this script can only be used on NO jtag chain mode
+;--------------------------------------------------------------------------
+
+;do ./7520V2_DDR_1Gb_312.cmm
+
+GLOBAL &VMLINUX_PATH
+GLOBAL &INITRD_PATH
+GLOBAL &SOURCE_PATH
+GLOBAL &DDR_BASE
+GLOBAL &INITRD_LOAD_ADDR
+GLOBAL &IMAGE_LOAD_ADDR
+
+&VMLINUX_PATH= ".\vmlinux"
+&IMAGE_PATH="..\..\linux_plat\base\linux\kernels\linux-3.4.5\zImage"
+&INITRD_PATH= ".\cpio_ramdisk.gz"
+&SOURCE_PATH="F:\7520V3\linux-3.4.5"
+&DDR_BASE=0x22300000
+&INITRD_LOAD_ADDR=&DDR_BASE+0xA00000
+&IMAGE_LOAD_ADDR=&DDR_BASE+0x8000
+
+area.reset
+print "resetting..."
+TASK.RESet
+sYmbol.RESet
+MMU.RESet
+
+;do ./boot.cmm
+
+; setup of ICD
+
+ print "initializing..."
+sys.cpu CortexA53
+SYStem.Option MMUSPACES ON ; enable space ids to virtual addresses
+SYStem.JtagClock 3.0MHz ; use adaptive clocking for most speed
+sys.option enreset Off
+sys.option resbreak off
+
+Sys.Config.COREBASE 0x80410000 ; Cortex-A53
+Sys.Config.CTIBASE 0x80420000
+Sys.Config.debugaccessport 0
+Sys.Mode PREPARE
+Wait 0.1s
+
+sys.up
+;data.set 0x01306100 %long 0xffffffff ;DDR config
+
+SETUP.IMASKASM ON ; lock interrupts while single steppingle stepping
+ ;l2 divison -- no need
+; data.set 0x00803004 %LE %LONG 0x33111;
+
+//A9 select 624M, bit0-2, 0=26, 1=624, 2=480, 3=312, 4=156
+;data.set 0x01306040 %long 0x00000001
+
+; Target Setup: initialize LPDDR controller and peripherals(e.g. UART1)
+print "initialize board ..."
+
+; use the debugger to initialize it
+; do basic setup on board;
+; we don't need this step on zx297510 platform, because jtag_debug code or T32 script has run before this step.
+; jtag_debug code or T32 script running on cortex-m0 initiates system clock, DDR, gpio multiplex, and so on....
+
+do .\console_fpga.cmm ; setup serial console
+
+; Load the Linux kernel
+
+; If you are using a flashed kernel, or if you're
+; loading your kernel via TFTP, use the boot monitor
+; to do so.
+
+; Use the next lines only to load the kernel into
+; RAM using the debugger.
+
+; vmlinux starts physically at RAM start (=0x28000000) + 0x8000
+; (see arch/arm/kernel/head-armv.S)
+print "loading Linux image..."
+;Data.LOAD.Binary &IMAGE_PATH &IMAGE_LOAD_ADDR ; loading zImage here, it will uncompress itself
+;data.load.elf &VMLINUX_PATH (&DDR_BASE+0x8000) /gnu /nosymbol
+Register.RESet
+
+ Data.LOAD.Elf &VMLINUX_PATH 0x22308000-0xc0008000 /gnu /nosymbol
+
+; Set PC on start address of image
+Register.Set PC (&DDR_BASE+0x8000)
+
+
+; Set machine type in R1; see arch/arm/tools/mach-types 7520 = 0x1d63
+Register.Set R1 0x1d63
+
+; Set parameter tags for linux boot
+do .\atag-list.cmm
+Register.Set R2 (&DDR_BASE+0x0100)
+
+; Loading RAM disk
+print "loading ram disk"
+
+; Load ram file system image into ram disk
+;Data.LOAD.Binary &INITRD_PATH &INITRD_LOAD_ADDR
+Data.LOAD.Binary &INITRD_PATH &INITRD_LOAD_ADDR /noclear /nosymbol
+
+; Load the Linux kernel symbols into the debugger
+print "loading Linux kernel symbols..."
+Data.LOAD.Elf &VMLINUX_PATH /gnu /nocode /strippart "linux-3.4.5" /SourcePATH ..\linux-3.4.5
+;Data.LOAD.Elf &VMLINUX_PATH /gnu /nocode /SourcePATH ..\linux-3.4.5
+
+; Open a Code Window -- we like to see something
+Data.List
+
+
+; Run over MMU & Interrupt initialization
+
+ ;Go __init_end /Onchip
+ ;print "initializing target and debugger MMU..."
+ ;wait !run()
+
+ ; Map the virtual kernel symbols to physical addresses
+ ; to give the debugger access to it before CPU MMU is
+ ; initialized
+ MMU.FORMAT LINUX swapper_pg_dir 0xc0000000--0xc0ffffff &DDR_BASE
+ TRANSlation.COMMON 0xbf000000--0xffffffff ; common area for kernel and processes
+ TRANSlation.TableWalk ON ;debugger uses table walk to decode virtual address
+ TRANSlation.ON ;switch on debugger address translation
+
+ ; set source path
+ print "set source path ..."
+ ;sYmbol.SourcePATH.RESet
+ sYmbol.SourcePATH.SetBaseDir &SOURCE_PATH
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\arch\arm\mach-zx297520v3
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\arch\arm
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\init
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\kernel
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\tty
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\clk
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\gpio
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\dma
+; sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers
+
+
+ ; Note that the Linux awareness needs the kernel symbols to work
+ print "initializing multitask support..."
+ TASK.CONFIG .\linux ; loads Linux awareness (linux.t32)
+ MENU.ReProgram .\linux ; loads Linux menu (linux.men)
+ HELP.FILTER.Add rtoslinux ; add linux awareness manual to help filter
+ MENU.ReProgram .\sys\board ; add board tools
+
+; switch on symbol autoloader
+sYmbol.AutoLoad.CHECKLINUX "do "+os.ppd()+"/autoload "
+ ; Group kernel area to be displayed with red bar
+
+ GROUP.Create "kernel" 0xc0000000--0xffffffff /RED
+ GROUP.Create "module" 0xbf000000--0xbfffffff /blue
+; Ok, we're done, let's start Linux
+
+ SYStem.Option MMUSPACES OFF
+
+
+
+enddo
+
diff --git a/ap/build/scripts/trace32/zx297520v3/linux_297520v3evb_attach.cmm b/ap/build/scripts/trace32/zx297520v3/linux_297520v3evb_attach.cmm
new file mode 100755
index 0000000..78c246a
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/linux_297520v3evb_attach.cmm
@@ -0,0 +1,92 @@
+;/*it is used for attaching while zx297510evb running*/
+
+;do ./boot_attach_CortexA9.cmm
+
+GLOBAL &VMLINUX_PATH
+GLOBAL &SOURCE_PATH
+GLOBAL &DDR_BASE
+
+&SOURCE_PATH="..\..\linux_plat\base\linux\kernels\linux-3.4.5"
+&VMLINUX_PATH="..\..\linux_plat\base\linux\kernels\linux-3.4.5\vmlinux"
+
+&DDR_BASE=0x20440000
+
+ area.reset
+ sYmbol.RESet
+MMU.RESet
+
+; setup of ICD
+
+ print "initializing..."
+ SYStem.CPU CortexA53 ; ;ZX297520v3 CortexA53 core
+ SYStem.Option MMUSPACES ON ; enable space ids to virtual addresses
+SYStem.JtagClock 3.0MHz ; use adaptive clocking for most speed
+
+ system.option resbreak off
+ system.option enreset off
+
+Sys.Config.COREBASE 0x80410000 ;
+Sys.Config.CTIBASE 0x80420000
+Sys.Config.debugaccessport 0
+Sys.Mode PREPARE
+
+
+ wait 0.1s
+
+ sys.mode attach
+ SETUP.IMASKASM ON ; lock interrupts while single stepping
+
+; Load the Linux kernel symbols into the debugger
+
+ print "loading Linux kernel symbols..."
+
+ ;Data.LOAD.Elf &VMLINUX_PATH /gnu /nocode /SourcePATH ..\..\..\..\
+
+Data.LOAD.Elf &VMLINUX_PATH /gnu /nocode /strippart "linux-3.4.5" /SourcePATH ..\linux-3.4.5
+
+ ; Map the virtual kernel symbols to physical addresses
+ ; to give the debugger access to it before CPU MMU is
+ ; initialized
+ MMU.FORMAT LINUX swapper_pg_dir 0xc0040000--0xc30fffff &DDR_BASE
+ TRANSlation.COMMON 0xbf000000--0xffffffff ; common area for kernel and processes
+ TRANSlation.TableWalk ON ;debugger uses table walk to decode virtual address
+ TRANSlation.ON ;switch on debugger address translation
+
+ ; set source path
+ print "set source path ..."
+ sYmbol.SourcePATH.RESet
+ sYmbol.SourcePATH.SetBaseDir &SOURCE_PATH
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\arch\arm
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\arch\arm\mach-zx297520v3
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\init
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\kernel
+ ;sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\base
+ ;sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\tty
+ ;sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\gpio
+ ;sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\i2c
+ ;sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\usb
+ ;sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers\mmc
+ ;sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\mm
+ sYmbol.SourcePATH.SetRecurseDir &SOURCE_PATH\drivers
+
+; Initialize Linux Awareness
+
+ ; Note that the Linux awareness needs the kernel symbols to work
+ print "initializing multitask support..."
+ TASK.CONFIG .\linux ; loads Linux awareness (linux.t32)
+ MENU.ReProgram .\linux ; loads Linux menu (linux.men)
+ HELP.FILTER.Add rtoslinux ; add linux awareness manual to help filter
+ MENU.ReProgram .\sys\board ; add board tools
+
+ ; Group kernel area to be displayed with red bar
+
+ GROUP.Create "kernel" 0xc0000000--0xffffffff /RED
+ GROUP.Create "module" 0xbf000000--0xbfffffff /blue
+; Ok, we're done, let's start Linux
+
+break
+
+enddo
+
+
+
diff --git a/ap/build/scripts/trace32/zx297520v3/linux_buddy_debug.cmm b/ap/build/scripts/trace32/zx297520v3/linux_buddy_debug.cmm
new file mode 100755
index 0000000..e244fab
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/linux_buddy_debug.cmm
@@ -0,0 +1,71 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2016 ZTE Corporation.
+//*
+//**************************************************************************
+// geanfeng
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=50.
+&nameWidth=20.
+&fileColumns=1000.
+&fileLines=1000.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log_buddfy"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\result.txt"
+area.open trace &file
+area.view trace
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+&node=v.value(buddy_employ_head.next)
+&head=v.value(&buddy_employ_head)
+while !(&node==&head)
+(
+ &addr=v.value(((struct heap_record*)&node)->addr)
+ &size=v.value(((struct heap_record*)&node)->size)
+ &thread=v.string(((struct heap_record*)&node)->task_name)
+ &i=0
+ &stack=""
+ &stack_value=v.value(((struct heap_record*)&node)->stack_frame[&i])
+ while &i<0xa
+ (
+ if !(&stack_value==0)
+ (
+ &stack_frame=Y.function(P:&stack_value)
+ &stack_frame=os.file.name("&stack_frame")
+ &stack="&stack"+"&i:"+"&stack_frame "
+ &i=&i+1
+ &stack_value=v.value(((struct heap_record*)&node)->stack_frame[&i])
+ )
+ else
+ (
+ goto next
+ )
+ )
+next:
+ &size=format.decimal(10., &size)
+ print "node: "+"&node"+" addr: "+"&addr"+" size:"+"&size"+" thread:"+"&thread"+" stack_frame:"+"&stack"
+ &node=v.value(((struct list_head*)&node)->next)
+)
+
+print "allocated hobby End-----------------------------"
+
+area.close trace
+ENDDO
+//****ÔËÐнáÊø*****
diff --git a/ap/build/scripts/trace32/zx297520v3/linux_cpko_attach.cmm b/ap/build/scripts/trace32/zx297520v3/linux_cpko_attach.cmm
new file mode 100644
index 0000000..f74e525
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/linux_cpko_attach.cmm
@@ -0,0 +1,22 @@
+ //**************************************************************************
+//*
+//* Copyright (c) 2016 ZTE Corporation.
+//*
+//**************************************************************************
+// geanfeng
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+//´´½¨Ò»¸ö´°¿Ú£»
+local &elfname
+DIALOG.File *
+entry &elfname
+&cpkodir=os.file.path(&elfname)
+
+&cpko_text_start=v.value(cpps_global_var.cpko_text_start)
+&cpko_data_start=v.value(cpps_global_var.cpko_data_start)
+&cpko_bss_start=v.value(cpps_global_var.cpko_bss_start)
+
+data.load.elf "&elfname" /gnu /noclear /nocode /reloc .text at &cpko_text_start /reloc .data at &cpko_data_start /reloc .bss at &cpko_bss_start
+//****ÔËÐнáÊø*****
diff --git a/ap/build/scripts/trace32/zx297520v3/linux_kmalloc_debug.cmm b/ap/build/scripts/trace32/zx297520v3/linux_kmalloc_debug.cmm
new file mode 100755
index 0000000..fe1cf0e
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/linux_kmalloc_debug.cmm
@@ -0,0 +1,74 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2016 ZTE Corporation.
+//*
+//**************************************************************************
+// geanfeng
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=50.
+&nameWidth=20.
+&fileColumns=1000.
+&fileLines=1000.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log_kmalloc"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\result.txt"
+area.open trace &file
+area.view trace
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+&node=v.value(kmem_employ_head.next)
+
+&head=v.value(&kmem_employ_head)
+
+while !(&node==&head)
+(
+ &addr=v.value(((struct heap_record*)&node)->addr)
+ &size=v.value(((struct heap_record*)&node)->size)
+ &thread=v.string(((struct heap_record*)&node)->task_name)
+ &i=0
+ &stack=""
+ &stack_value=v.value(((struct heap_record*)&node)->stack_frame[&i])
+ while &i<0xa
+ (
+ if !(&stack_value==0)
+ (
+ &stack_frame=Y.function(P:&stack_value)
+ &stack_frame=os.file.name("&stack_frame")
+ &stack="&stack"+"&i:"+"&stack_frame "
+ &i=&i+1
+ &stack_value=v.value(((struct heap_record*)&node)->stack_frame[&i])
+ )
+ else
+ (
+ goto next
+ )
+ )
+next:
+ &size=format.decimal(10., &size)
+ print "node: "+"&node"+" addr: "+"&addr"+" size:"+"&size"+" thread:"+"&thread"+" stack_frame:"+"&stack"
+ &node=v.value(((struct list_head*)&node)->next)
+)
+
+print "allocated kmalloc End-----------------------------"
+
+area.close trace
+ENDDO
+//****ÔËÐнáÊø*****
diff --git a/ap/build/scripts/trace32/zx297520v3/net_trace/data_free.cmm b/ap/build/scripts/trace32/zx297520v3/net_trace/data_free.cmm
new file mode 100755
index 0000000..16c7315
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/net_trace/data_free.cmm
@@ -0,0 +1,61 @@
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &p_init_task &ptask &pnext &active_mm &mmap &pName &startaddr &endaddr &mmapsize &appmemsize &appallsize
+local &ifindex &macaddr &tempmac &count &devaddr &ipaddr &tempipaddr
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=20.
+&nameWidth=20.
+&fileColumns=300.
+&fileLines=3000.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\alltask.txt"
+area.open trace &file
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+if !y.exist(init_task)
+(
+ print %string "OS is not uClinux"
+ area.view trace
+ area.close trace
+ endo
+)
+
+&ptask=v.value((((struct leak_list*)&data_free)[leak_set]).next)
+&count=v.value((((struct leak_list*)&data_free)[leak_set]).count)
+&num=0
+repeat
+(
+&pnext=v.value(((struct track_info*)&ptask)->next)
+&ptr=v.string(((struct track_info*)&ptask)->func_track)
+&ptr1=v.string(((struct track_info*)&ptask)->func_track+200)
+&ptask=&pnext
+print %string "&num &ptr"
+print %string "&ptr1"
+print %string "------------------------"
+&num=&num+1
+)
+while (&num<&count)
+print FORMAT.CHAR('-',&fileColumns,'-')
+
+area.view trace
+area.close trace
+enddo
+
diff --git a/ap/build/scripts/trace32/zx297520v3/net_trace/data_leak.cmm b/ap/build/scripts/trace32/zx297520v3/net_trace/data_leak.cmm
new file mode 100755
index 0000000..3a0545a
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/net_trace/data_leak.cmm
@@ -0,0 +1,58 @@
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &p_init_task &ptask &pnext &active_mm &mmap &pName &startaddr &endaddr &mmapsize &appmemsize &appallsize
+local &ifindex &macaddr &tempmac &count &devaddr &ipaddr &tempipaddr
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=20.
+&nameWidth=20.
+&fileColumns=150.
+&fileLines=3000.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\alltask.txt"
+area.open trace &file
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+if !y.exist(init_task)
+(
+ print %string "OS is not uClinux"
+ area.view trace
+ area.close trace
+ endo
+)
+
+&ptask=v.value((((struct leak_list*)&data_leak)[leak_set]).next)
+&count=v.value((((struct leak_list*)&data_leak)[leak_set]).count)
+&num=0
+repeat
+(
+&pnext=v.value(((struct track_info*)&ptask)->next)
+&ptr=v.string(((struct track_info*)&ptask)->func_track)
+&ptask=&pnext
+print %string "&ptr &num"
+&num=&num+1
+)
+while (&num<&count)
+print FORMAT.CHAR('-',&fileColumns,'-')
+
+area.view trace
+area.close trace
+enddo
+
diff --git a/ap/build/scripts/trace32/zx297520v3/net_trace/linux_conn_hash_info .cmm b/ap/build/scripts/trace32/zx297520v3/net_trace/linux_conn_hash_info .cmm
new file mode 100755
index 0000000..4673d25
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/net_trace/linux_conn_hash_info .cmm
@@ -0,0 +1,87 @@
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//ËùÓÐÒѽ¨Á´½ÓÐÅÏ¢
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &p_init_task &ptask &hash_shift &active_mm &mmap &pName &hash_buckets &endaddr &mmapsize &appmemsize &appallsize
+local &macaddr &tempmac &count &devaddr &ipaddr &tempipaddr &hashinfo
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=20.
+&nameWidth=20.
+&fileColumns=800.
+&fileLines=200.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\hash.txt"
+area.open trace &file
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+if !y.exist(init_task)
+(
+ print %string "OS is not uClinux"
+ area.view trace
+ area.close trace
+ endo
+)
+
+print "conn info:"
+&ptask=v.value(&init_net.ct)
+&htable_size=v.value(((struct netns_ct*)&ptask)->htable_size)
+&hash=v.value(((struct netns_ct*)&ptask)->hash)
+&offset=v.value(((struct nf_conn*)0x0)->tuplehash)
+print %string "&offset"
+&count=0
+while (&count<&htable_size)
+(
+ &hashinfo=v.value(((struct hlist_nulls_head*)&hash)[&count]->first)
+ repeat
+ (
+ if &hashinfo>0xC0000000
+ (
+ &conn=&hashinfo-&offset
+ &src_tuple=v.value(((struct nf_conn*)&conn)->tuplehash.tuple.src.u3.ip)
+ &src_port=v.value(((struct nf_conn*)&conn)->tuplehash.tuple.src.u.all)
+ &dst_tuple=v.value(((struct nf_conn*)&conn)->tuplehash.tuple.dst.u3.ip)
+ &dst_port=v.value(((struct nf_conn*)&conn)->tuplehash.tuple.dst.u.all)
+ &proto=v.value(((struct nf_conn*)&conn)->tuplehash.tuple.dst.protonum)
+ &dir=v.value(((struct nf_conn*)&conn)->tuplehash.tuple.dst.dir)
+ if &proto==0x11
+ &proto="UDP"
+ else if &proto==0x6
+ &proto="TCP"
+ if &dir==0
+ &dir="original"
+ else
+ &dir="reply"
+ print %string "src &src_tuple:&src_port -> dst &dst_tuple:&dst_port proto: &proto dir: &dir"
+ print %string "conn &conn"
+ &hashinfo=v.value(((struct hlist_nulls_node*)&hashinfo)->next)
+
+ )
+ )
+ while (&hashinfo>0xC0000000)
+// print %string "hashinfo &hashinfo"
+ &count=&count+1
+)
+//while (&count<&hash_shift)
+print FORMAT.CHAR('-',&fileColumns,'-')
+
+area.view trace
+area.close trace
+enddo
+
diff --git a/ap/build/scripts/trace32/zx297520v3/net_trace/linux_device_addr.cmm b/ap/build/scripts/trace32/zx297520v3/net_trace/linux_device_addr.cmm
new file mode 100755
index 0000000..388e37a
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/net_trace/linux_device_addr.cmm
@@ -0,0 +1,86 @@
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &p_init_task &ptask &pnext &active_mm &mmap &pName &startaddr &endaddr &mmapsize &appmemsize &appallsize
+
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=20.
+&nameWidth=20.
+&fileColumns=800.
+&fileLines=200.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\alltask.txt"
+area.open trace &file
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+if !y.exist(init_task)
+(
+ print %string "OS is not uClinux"
+ area.view trace
+ area.close trace
+ endo
+)
+
+
+&ptask=v.value(((struct net*)&init_net)->dev_base_head.next)
+&pnext=&ptask
+&p_init_task=&ptask
+
+repeat
+(
+ print %string "&ptask"
+ &ptask=&pnext-8C
+ &pnext=v.value(((struct net_device*)&ptask)->dev_list.next)
+
+ &pName=v.string(((struct net_device*)&ptask)->name)
+
+ &string=""
+ &string="&string"+" &pName"
+ print %string "&string"
+
+ //&active_mm=v.value(((struct task_struct*)&ptask)->active_mm)
+ //if &active_mm!=0
+ // (
+ // &pName=v.string(((struct task_struct *)&ptask)->comm)
+ // &thread_info=v.value(((struct task_struct *)&ptask)->stack)
+ // &start_code=v.value(((struct task_struct *)&ptask)->active_mm.start_code)
+ // &end_code=v.value(((struct task_struct *)&ptask)->active_mm.end_code)
+ // &start_stack=v.value(((struct task_struct *)&ptask)->active_mm.start_stack)
+ // &low_stack=v.value(((struct task_struct *)&ptask)->active_mm.brk)
+
+ // &string=""
+ // &string="&string"+" (struct task_struct*)"+format.string("&ptask",10,' ')
+ // &string="&string"+" (struct thread_info*)"+format.string("&thread_info",10,' ')
+ // &string="&string"+" start_code:"+format.string("&start_code",10,' ')
+ // &string="&string"+" end_code:"+format.string("&end_code",10,' ')
+// &string="&string"+" stack_high:"+format.string("&start_stack",10,' ')
+// &string="&string"+" stack_low:"+format.string("&low_stack",10,' ')
+// &string="&string"+" &pName"
+ // print %string "&string"
+
+ // )
+)
+while (&pnext!=&p_init_task)
+print FORMAT.CHAR('-',&fileColumns,'-')
+
+area.view trace
+area.close trace
+enddo
+
diff --git a/ap/build/scripts/trace32/zx297520v3/net_trace/linux_device_info.cmm b/ap/build/scripts/trace32/zx297520v3/net_trace/linux_device_info.cmm
new file mode 100755
index 0000000..2936535
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/net_trace/linux_device_info.cmm
@@ -0,0 +1,78 @@
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &p_init_task &ptask &pnext &active_mm &mmap &pName &startaddr &endaddr &mmapsize &appmemsize &appallsize
+local &ifindex &macaddr &tempmac &count &devaddr &ipaddr &tempipaddr
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=20.
+&nameWidth=20.
+&fileColumns=800.
+&fileLines=200.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\alltask.txt"
+area.open trace &file
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+if !y.exist(init_task)
+(
+ print %string "OS is not uClinux"
+ area.view trace
+ area.close trace
+ endo
+)
+
+
+&ptask=v.value(((struct net*)&init_net)->dev_base_head.next)
+&pnext=&ptask
+&p_init_task=&ptask
+&offset=v.value(&(((struct net_device*)0)->dev_list))
+repeat
+(
+ &ptask=&pnext-0x90
+ &pnext=v.value(((struct net_device*)&ptask)->dev_list.next)
+ &devaddr=v.value(((struct net_device*)&ptask)->dev_addr)
+ &pName=v.string(((struct net_device*)&ptask)->name)
+ &ifindex=v.string(((struct net_device*)&ptask)->ifindex)
+ &count=0
+ &macaddr=""
+repeat
+(
+ &tempmac=v.value((unsigned char*)(&devaddr)[&count])
+ &macaddr="&macaddr"+"&tempmac"
+ if &count<5
+ &macaddr="&macaddr"+":"
+ &count=&count+1
+)
+while (&count<6)
+ &count=0
+ &ipaddr=v.value(((struct net_device*)&ptask)->ip_ptr->ifa_list->ifa_address)
+ &string=""
+ &string="&string"+" &pName"+" id "+"&ifindex"+" mac_addr "+format.string("&macaddr",25,' ')+" ip_addr "+"&ipaddr"
+ print %string "&string"
+ print %string "&ptask"
+
+)
+while (&pnext!=&p_init_task)
+print FORMAT.CHAR('-',&fileColumns,'-')
+
+area.view trace
+area.close trace
+enddo
+
diff --git a/ap/build/scripts/trace32/zx297520v3/net_trace/linux_hash_info.cmm b/ap/build/scripts/trace32/zx297520v3/net_trace/linux_hash_info.cmm
new file mode 100755
index 0000000..a4c419d
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/net_trace/linux_hash_info.cmm
@@ -0,0 +1,94 @@
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &p_init_task &ptask &hash_shift &active_mm &mmap &pName &hash_buckets &endaddr &mmapsize &appmemsize &appallsize
+local &macaddr &tempmac &count &devaddr &ipaddr &tempipaddr
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=20.
+&nameWidth=20.
+&fileColumns=800.
+&fileLines=200.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\hash.txt"
+area.open trace &file
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+if !y.exist(init_task)
+(
+ print %string "OS is not uClinux"
+ area.view trace
+ area.close trace
+ endo
+)
+
+print "arp_tbl info:"
+&ptask=v.value(((struct neigh_table *)&arp_tbl)->nht)
+&hash_shift=v.value(((struct neigh_hash_table*)&ptask)->hash_shift)
+&hash_buckets=v.value(((struct neigh_hash_table*)&ptask)->hash_buckets)
+&p_init_task=&ptask
+&count=0
+&count_ip=0
+print %string "&hash_shift"
+while (&count<(1<<&hash_shift))
+(
+ &neighbour=v.value(((struct neighbour**)&hash_buckets)[&count])
+ repeat
+ (
+ if &neighbour>0x10000000
+ (
+ print %string "&neighbour"
+ &ipaddr=""
+ &tempipaddr=v.value(((struct neighbour*)&neighbour)->primary_key)
+ &dev_name=v.string(((struct neighbour*)&neighbour)->dev->name)
+ repeat
+ (
+ &partipaddr=v.value((unsigned char*)(&tempipaddr)[&count_ip])
+ &ipaddr="&ipaddr"+"&partipaddr"
+ if &count_ip<3
+ &ipaddr="&ipaddr"+"."
+ &count_ip=&count_ip+1
+ )
+ while (&count_ip<4)
+ &count_mac=0
+ &tempmac=v.value(((struct neighbour*)&neighbour)->ha)
+ &macaddr=""
+ repeat
+ (
+ &partmacaddr=v.value((unsigned char*)(&tempmac)[&count_mac])
+ &macaddr="&macaddr"+"&partmacaddr"
+ if &count_mac<5
+ &macaddr="&macaddr"+":"
+ &count_mac=&count_mac+1
+ )
+ while (&count_mac<6)
+ &count_ip=0
+ &count_mac=0
+ print %string "devname &dev_name"+" ipaddr &ipaddr"+" macaddr &macaddr"
+ )
+ &neighbour=v.value(((struct neighbour*)&neighbour)->next)
+ )
+ while (&neighbour>0x10000000)
+ &count=&count+1
+)
+
+area.view trace
+area.close trace
+enddo
+
diff --git a/ap/build/scripts/trace32/zx297520v3/net_trace/linux_tcp_hash_info.cmm b/ap/build/scripts/trace32/zx297520v3/net_trace/linux_tcp_hash_info.cmm
new file mode 100755
index 0000000..fab5312
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/net_trace/linux_tcp_hash_info.cmm
@@ -0,0 +1,125 @@
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//ËùÓÐÒѽ¨Á´½ÓÐÅÏ¢
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &p_init_task &ptask &hash_shift &active_mm &mmap &pName &hash_buckets &endaddr &mmapsize &appmemsize &appallsize
+local &macaddr &tempmac &count &devaddr &ipaddr &tempipaddr &hashinfo
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=20.
+&nameWidth=20.
+&fileColumns=800.
+&fileLines=200.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\hash.txt"
+area.open trace &file
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+if !y.exist(init_task)
+(
+ print %string "OS is not uClinux"
+ area.view trace
+ area.close trace
+ endo
+)
+
+
+print "conn info:"
+&ptask=v.value(&tcp_hashinfo)
+&ehash_size=v.value(((struct inet_hashinfo*)&ptask)->ehash_mask)
+&ehash=v.value(((struct inet_hashinfo*)&ptask)->ehash)
+&offset=v.value(&(((struct sock_common*)0)->skc_nulls_node))
+//print %string "&offset "
+
+&string="chain"
+print "ehash.chain"
+GOSUB PRINTHASH &ehash &ehash_size &offset &string
+
+print
+print "ehash.twchain"
+&string="twchain"
+GOSUB PRINTHASH &ehash &ehash_size &offset &string
+
+print
+//print "bhash.chain"
+//&ehash=v.value(((struct inet_hashinfo*)&ptask)->bhash)
+//&ehash_size=v.value(((struct inet_hashinfo*)&ptask)->bhash_size)
+//&string="bchain"
+//GOSUB PRINTHASH &ehash &ehash_size &offset &string
+
+print "listenning_hash"
+&ehash=v.value(((struct inet_hashinfo*)&ptask)->listening_hash)
+&string="head"
+&ehash_size=32
+GOSUB PRINTHASH &ehash &ehash_size &offset &string
+
+enddo
+
+PRINTHASH:
+local &count &ehash_size &hashinfo &ehash &sk &state &string &struct_type &struct_type1
+entry &ehash &ehash_size &offset &string
+&count=0
+&struct_type="inet_ehash_bucket"
+&struct_type1="hlist_nulls_node"
+//print %string "&ehash_size "
+while (&count<&ehash_size)
+(
+ if "&string"=="bchain"
+ (
+ &string="chain"
+ &struct_type="inet_bind_hashbucket"
+ &struct_type1="hlist_node"
+ )
+ if "&string"=="head"
+ &struct_type="inet_listen_hashbucket"
+
+ &hashinfo=v.value(((struct &struct_type*)&ehash)[&count]->&string.first)
+ repeat
+ (
+ if (&hashinfo>0xC0000000)
+ (
+ &sk=&hashinfo-&offset
+ &hashinfo=v.value(((struct &struct_type1*)&hashinfo)->next)
+ &state=v.value(((struct sock*)&sk)->sk_socket.state)
+ if &state==0
+ &state="SS_FREE"
+ else if &state==1
+ &state="SS_UNCONNECTED"
+ else if &state==2
+ &state="SS_CONNECTING"
+ else if &state==3
+ &state="SS_CONNECTED"
+ else if &state==4
+ &state="SS_DISCONNECTING"
+ print %string "skaddr: &sk, socket_state: &state"
+ )
+ )
+ while (&hashinfo>0xC0000000)
+// print %string "hashinfo &hashinfo"
+ &count=&count+1
+)
+area.view trace
+area.close trace
+return 1
+
+//while (&count<&ehash_shift)
+//print FORMAT.CHAR('-',&fileColumns,'-')
+
+
+
diff --git a/ap/build/scripts/trace32/zx297520v3/net_trace/readme.txt b/ap/build/scripts/trace32/zx297520v3/net_trace/readme.txt
new file mode 100755
index 0000000..e065bf6
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/net_trace/readme.txt
@@ -0,0 +1,10 @@
+ÍøÂçtrace½Å±¾£¬ÓÃÓÚ·½±ã²é¿´Ò»Ð©¹Ø¼üµÄÈ«¾ÖÐÅÏ¢
+
+ÎļþÃû ¹¦ÄÜ
+data_free.cmm ²é¿´È«¾Ö±äÁ¿data_freeµÄÐÅÏ¢
+data_leak.cmm ²é¿´È«¾Ö±äÁ¿data_leakµÄÐÅÏ¢
+linux_conn_hash_info .cmm ²é¿´ËùÓÐÍøÂçÁ´½ÓµÄÐÅÏ¢
+linux_device_addr.cmm ²é¿´ÍøÂçÉ豸µÄµØÖ·
+linux_device_info.cmm ²é¿´ÍøÂçÉ豸ÐÅÏ¢
+linux_tcp_hash_info.cmm ²é¿´tcpµÄskÐÅÏ¢
+linux_hash_info.cmm ²é¿´arp_tblÐÅÏ¢
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/os_code_compare.cmm b/ap/build/scripts/trace32/zx297520v3/os_code_compare.cmm
new file mode 100755
index 0000000..03a5389
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/os_code_compare.cmm
@@ -0,0 +1,108 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2017 ZTE Corporation.
+//*
+//**************************************************************************
+// penglei
+
+//**************************************************************************
+//* tos/linux/uClinux²Ù×÷ϵͳÄں˴úÂë¶Î±È½Ï£¬²é¿´´úÂë¶ÎÊÇ·ñÓÐÍ»±äµÄÇé¿ö
+//**************************************************************************
+
+local &addressStart
+local &addressEnd
+local &position
+local &knowndiff
+
+&knowndiff="__aeabi_uidiv __aeabi_idiv"
+
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=20.
+&nameWidth=20.
+&fileColumns=90.
+&fileLines=500.
+&diffCount=0
+
+area.create codeDiff &fileColumns &fileLines
+area.clear codeDiff
+area.select codeDiff
+area.open codeDiff codeDiff.txt
+area.view codeDiff
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\codeDiff.txt"
+
+;Load Code from Binary and verify specific sections with the Elf file
+//¸ù¾Ý²Ù×÷ϵͳÀàÐÍ»ñÈ¡´úÂë¶ÎÆðʼµØÖ·ºÍ½áÊøµØÖ·
+if symbol.exist(init_task) //linux or uClinux
+(
+ &version=TASK.OS.VERSION()
+ if (&version>0x500E0)
+ (
+ &addressStart=sYmbol.SECADDRESS(".text")
+ &addressEnd=sYmbol.SECEND(".text")
+ )
+ else
+ (
+ &addressStart=sYmbol.SECADDRESS(".head.text")
+ &addressEnd=sYmbol.SECEND(".text")
+ )
+)
+else if symbol.exist(tos_except) //tos
+(
+ &addressStart=sYmbol.SECADDRESS(".rom_vectors")
+ &addressEnd=sYmbol.SECADDRESS(".data")
+)
+else
+(
+ area.close codeDiff
+ ENDDO
+)
+print FORMAT.CHAR('-',&fileColumns,'-')
+//´òÓ¡title
+&string=format.string(" ",&fileColumns/3,' ')
+&string="&string"+"elfÓëbinÎļþµÄ´úÂë¶Î²îÒì"
+print %string "&string"
+print FORMAT.CHAR('-',&fileColumns,'-')
+repeat
+(
+ Data.LOAD.Elf &elfname &addressStart--&addressEnd /DIFF /NoRegister /NosYmbol
+ &find=FOUND()
+ if &find
+ (
+ &addressStart=ADDRESS.OFFSET(TRACK.ADDRESS())
+ &result="P:"+format.string("&addressStart",10,'')
+ &string=format.string("different address=",-&width,' ')+"&result"
+ &result=sYmbol.NAME(&result)
+ &result=os.file.name("&result")
+ &position=STRing.SCAN("&knowndiff","&result",0)
+ if &position<0
+ (
+ &string="&string"+" symbol="+format.string("&result",20,'')
+ print %string "&string"
+ &diffCount=&diffCount+1
+ )
+ &addressStart=(&addressStart&(~0x3))+4
+ &addressStart="P:"+format.string("&addressStart",10,'')
+ )
+ else
+ (
+ &addressStart=""
+ )
+)
+while ("&addressStart"!="")&&(&diffCount!=0x78)
+if (&diffCount==0x0)
+(
+ &string=format.string(" ",&fileColumns/3,' ')
+ &string="&string"+"Äں˴úÂë¶Î²»´æÔÚÍ»±ä"
+ print %string "&string"
+)
+print FORMAT.CHAR('-',&fileColumns,'-')
+area.close codeDiff
+ENDDO
+RETURN
diff --git a/ap/build/scripts/trace32/zx297520v3/print_os_statistics.cmm b/ap/build/scripts/trace32/zx297520v3/print_os_statistics.cmm
new file mode 100644
index 0000000..e73951b
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/print_os_statistics.cmm
@@ -0,0 +1,646 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2016 ZTE Corporation.
+//*
+//**************************************************************************
+// geanfeng
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &os_time0 &os_time1 &os_time2 &os_time3 &os_time4 &os_time5 &os_time6 &os_time7
+local &os_time_cnt &os_next_time
+local &os_swap_last &os_swap_cnt &os_swap_next
+local &os_irq_start_last &os_irq_start_cnt &os_irq_start_next
+local &os_irq_end_last &os_irq_end_cnt &os_irq_end_next
+
+//for linux
+local &os_softirq_start_last &os_softirq_start_cnt &os_softirq_start_next
+local &os_softirq_end_last &os_softirq_end_cnt &os_softirq_end_next
+local &os_timer_start_last &os_timer_start_cnt &os_timer_start_next
+local &os_timer_end_last &os_timer_end_cnt &os_timer_end_next
+
+local &os_irq_enable &os_softirq_enable &os_timer_enable
+&os_irq_enable=1
+&os_softirq_enable=0
+&os_timer_enable=0
+
+//for tos
+local &os_dsr_start_last &os_dsr_start_cnt &os_dsr_start_next
+local &os_dsr_end_last &os_dsr_end_cnt &os_dsr_end_next
+&os_dsr_enable=0
+
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=20.
+&nameWidth=20.
+&fileColumns=200.
+&fileLines=500.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\result.txt"
+area.open trace &file
+area.view trace
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+if symbol.exist(init_task)
+(
+ gosub LinuxTrace
+)
+
+if symbol.exist(tos_except)
+(
+ gosub TosTrace
+)
+
+area.close trace
+
+ENDDO
+//****ÔËÐнáÊø*****
+
+//*****************º¯Êý¶¨Òå**********************
+
+; ---------------------------------------------------------
+LinuxTrace:
+local &result
+
+if v.value(g_os_ddr_swapin_statistic)==0
+(
+ RETURN
+)
+
+&os_swap_last=v.value(g_os_ddr_swapin_statistic->index)
+&os_swap_cnt=v.value(sizeof(g_os_ddr_swapin_statistic->statistics)/sizeof(g_os_ddr_swapin_statistic->statistics[0]))
+&os_swap_next=&os_swap_last
+
+if &os_irq_enable==1
+(
+ &os_irq_start_last=v.value(g_os_ddr_irq_start_statistic->index)
+ &os_irq_start_cnt=v.value(sizeof(g_os_ddr_irq_start_statistic->statistics)/sizeof(g_os_ddr_irq_start_statistic->statistics[0]))
+ &os_irq_start_next=&os_irq_start_last
+ &os_irq_end_last=v.value(g_os_ddr_irq_end_statistic->index)
+ &os_irq_end_cnt=v.value(sizeof(g_os_ddr_irq_end_statistic->statistics)/sizeof(g_os_ddr_irq_end_statistic->statistics[0]))
+ &os_irq_end_next=&os_irq_end_last
+)
+else
+(
+ &os_irq_start_next=-1
+ &os_irq_end_next=-1
+)
+
+if &os_softirq_enable==1
+(
+ &os_softirq_start_last=v.value(g_os_ddr_softirq_start_statistic->index)
+ &os_softirq_start_cnt=v.value(sizeof(g_os_ddr_softirq_start_statistic->statistics)/sizeof(g_os_ddr_softirq_start_statistic->statistics[0]))
+ &os_softirq_start_next=&os_softirq_start_last
+ &os_softirq_end_last=v.value(g_os_ddr_softirq_end_statistic->index)
+ &os_softirq_end_cnt=v.value(sizeof(g_os_ddr_softirq_end_statistic->statistics)/sizeof(g_os_ddr_softirq_end_statistic->statistics[0]))
+ &os_softirq_end_next=&os_softirq_end_last
+)
+else
+(
+ &os_softirq_start_next=-1
+ &os_softirq_end_next=-1
+)
+
+if &os_timer_enable==1
+(
+ &os_timer_start_last=v.value(g_os_ddr_timer_start_statistic->index)
+ &os_timer_start_cnt=v.value(sizeof(g_os_ddr_timer_start_statistic->statistics)/sizeof(g_os_ddr_timer_start_statistic->statistics[0]))
+ &os_timer_start_next=&os_timer_start_last
+ &os_timer_end_last=v.value(g_os_ddr_timer_end_statistic->index)
+ &os_timer_end_cnt=v.value(sizeof(g_os_ddr_timer_end_statistic->statistics)/sizeof(g_os_ddr_timer_end_statistic->statistics[0]))
+ &os_timer_end_next=&os_timer_end_last
+)
+else
+(
+ &os_timer_start_next=-1
+ &os_timer_end_next=-1
+)
+
+//³õʼ»¯timeÊýÖµ
+if &os_swap_next==-1
+(
+ &os_time0=-1
+)
+else
+(
+ &os_time0=v.value(g_os_ddr_swapin_statistic->statistics[&os_swap_next].data2)
+)
+if &os_irq_start_next==-1
+(
+ &os_time1=-1
+)
+else
+(
+ &os_time1=v.value(g_os_ddr_irq_start_statistic->statistics[&os_irq_start_next].data2)
+)
+if &os_irq_end_next==-1
+(
+ &os_time2=-1
+)
+else
+(
+ &os_time2=v.value(g_os_ddr_irq_end_statistic->statistics[&os_irq_end_next].data2)
+)
+if &os_softirq_start_next==-1
+(
+ &os_time3=-1
+)
+else
+(
+ &os_time3=v.value(g_os_ddr_softirq_start_statistic->statistics[&os_softirq_start_next].data2)
+)
+if &os_softirq_end_next==-1
+(
+ &os_time4=-1
+)
+else
+(
+ &os_time4=v.value(g_os_ddr_softirq_end_statistic->statistics[&os_softirq_end_next].data2)
+)
+if &os_timer_start_next==-1
+(
+ &os_time5=-1
+)
+else
+(
+ &os_time5=v.value(g_os_ddr_timer_start_statistic->statistics[&os_timer_start_next].data2)
+)
+if &os_timer_end_next==-1
+(
+ &os_time6=-1
+)
+else
+(
+ &os_time6=v.value(g_os_ddr_timer_end_statistic->statistics[&os_timer_end_next].data2)
+)
+
+&os_time_cnt=7.
+&os_next_time=0.
+
+print format.string("Name",32,' ')+" "+"Index"+" "+"Time"+" "+"Exce"
+
+&result=0
+while &result==0
+(
+ gosub LinuxPrintNextLine
+ if ((&os_swap_next==-1)&&(&os_irq_start_next==-1)&&(&os_irq_end_next==-1)&&(&os_softirq_start_next==-1)&&(&os_softirq_end_next==-1)&&(&os_timer_start_next==-1)&&(&os_timer_end_next==-1))
+ (
+ print "END"
+ &result=-1
+ )
+)
+RETURN
+
+; ---------------------------------------------------------
+LinuxPrintNextLine:
+local &time &str &line_index
+
+gosub GetMinTimeIndex &os_time_cnt
+ENTRY &index
+
+if &index==0
+(
+ local &task &addr
+ &task=v.value(g_os_ddr_swapin_statistic->statistics[&os_swap_next].data1)
+ &addr=v.value(&((struct task_struct*)&task)->comm)
+ &str="THREAD: "+data.string(D:&addr)
+ &line_index=&os_swap_next
+ &time=&os_time0
+ gosub GetNextIndex &os_swap_cnt &os_swap_last &os_swap_next
+ ENTRY &os_swap_next
+ if &os_swap_next==-1
+ (
+ &os_time0=-1
+ )
+ else
+ (
+ &os_time0=v.value(g_os_ddr_swapin_statistic->statistics[&os_swap_next].data2)
+ )
+)
+else if &index==1
+(
+ local &irq &addr
+ &irq=v.value(g_os_ddr_irq_start_statistic->statistics[&os_irq_start_next].data1)
+ &addr=v.value(irq_desc[&irq].action->name)
+ &str="IRQSTA: "+data.string(D:&addr)+" S"
+ &line_index=&os_irq_start_next
+ &time=&os_time1
+ gosub GetNextIndex &os_irq_start_cnt &os_irq_start_last &os_irq_start_next
+ ENTRY &os_irq_start_next
+ if &os_irq_start_next==-1
+ (
+ &os_time1=-1
+ )
+ else
+ (
+ &os_time1=v.value(g_os_ddr_irq_start_statistic->statistics[&os_irq_start_next].data2)
+ )
+)
+else if &index==2
+(
+ local &irq &addr
+ &irq=v.value(g_os_ddr_irq_end_statistic->statistics[&os_irq_end_next].data1)
+ &addr=v.value(irq_desc[&irq].action->name)
+ &str="IRQEND: "+data.string(D:&addr)+" E"
+ &line_index=&os_irq_end_next
+ &time=&os_time2
+ gosub GetNextIndex &os_irq_end_cnt &os_irq_end_last &os_irq_end_next
+ ENTRY &os_irq_end_next
+ if &os_irq_end_next==-1
+ (
+ &os_time2=-1
+ )
+ else
+ (
+ &os_time2=v.value(g_os_ddr_irq_end_statistic->statistics[&os_irq_end_next].data2)
+ )
+)
+else if &index==3
+(
+ local &vec &func
+ &time=v.value(g_os_ddr_softirq_start_statistic->statistics[&os_softirq_start_next].data2)
+ &vec=v.value(g_os_ddr_softirq_start_statistic->statistics[&os_softirq_start_next].data1)
+ &func=v.value(softirq_vec[&vec].action)
+ &str="SIRQS: "+symbol.function(P:&func)+" S"
+ &line_index=&os_softirq_start_next
+ &time=&os_time3
+ gosub GetNextIndex &os_softirq_start_cnt &os_softirq_start_last &os_softirq_start_next
+ ENTRY &os_softirq_start_next
+ if &os_softirq_start_next==-1
+ (
+ &os_time3=-1
+ )
+ else
+ (
+ &os_time3=v.value(g_os_ddr_softirq_start_statistic->statistics[&os_softirq_start_next].data2)
+ )
+)
+else if &index==4
+(
+ local &vec &func
+ &time=v.value(g_os_ddr_softirq_end_statistic->statistics[&os_softirq_end_next].data2)
+ &vec=v.value(g_os_ddr_softirq_end_statistic->statistics[&os_softirq_end_next].data1)
+ &func=v.value(softirq_vec[&vec].action)
+ &str="SIRQE: "+symbol.function(P:&func)+" E"
+ &line_index=&os_softirq_end_next
+ &time=&os_time4
+ gosub GetNextIndex &os_softirq_end_cnt &os_softirq_end_last &os_softirq_end_next
+ ENTRY &os_softirq_end_next
+ if &os_softirq_end_next==-1
+ (
+ &os_time4=-1
+ )
+ else
+ (
+ &os_time4=v.value(g_os_ddr_softirq_end_statistic->statistics[&os_softirq_end_next].data2)
+ )
+)
+else if &index==5
+(
+ local &func
+ &time=v.value(g_os_ddr_timer_start_statistic->statistics[&os_timer_start_next].data2)
+ &func=v.value(g_os_ddr_timer_start_statistic->statistics[&os_timer_start_next].data1)
+ &str="TIMERS: "+symbol.function(P:&func)+" S"
+ &line_index=&os_timer_start_next
+ &time=&os_time5
+ gosub GetNextIndex &os_timer_start_cnt &os_timer_start_last &os_timer_start_next
+ ENTRY &os_timer_start_next
+ if &os_timer_start_next==-1
+ (
+ &os_time5=-1
+ )
+ else
+ (
+ &os_time5=v.value(g_os_ddr_timer_start_statistic->statistics[&os_timer_start_next].data2)
+ )
+)
+else if &index==6
+(
+ local &func
+ &time=v.value(g_os_ddr_timer_end_statistic->statistics[&os_timer_end_next].data2)
+ &func=v.value(g_os_ddr_timer_end_statistic->statistics[&os_timer_end_next].data1)
+ &str="TIMERE: "+symbol.function(P:&func)+" E"
+ &line_index=&os_timer_end_next
+ &time=&os_time6
+ gosub GetNextIndex &os_timer_end_cnt &os_timer_end_last &os_timer_end_next
+ ENTRY &os_timer_end_next
+ if &os_timer_end_next==-1
+ (
+ &os_time6=-1
+ )
+ else
+ (
+ &os_time6=v.value(g_os_ddr_timer_end_statistic->statistics[&os_timer_end_next].data2)
+ )
+)
+else
+(
+ print "Unknown Type"
+)
+
+gosub GetMinTime &os_time_cnt
+ENTRY &os_next_time
+
+print format.string("&str",32,' ')+" "+format.DecimalU(8,&line_index)+" "+format.DecimalU(1,&time)+" "+format.DecimalU(1,&os_next_time-&time)
+
+RETURN
+
+; ---------------------------------------------------------
+GetNextIndex:
+ENTRY &cnt &last_index &cur_index
+local &index
+
+if !((&cur_index>=0.)&&(&cur_index<&cnt))
+(
+ RETURN -1
+)
+
+&index=&cur_index+1
+if &index>=&cnt
+(
+ &index=0
+)
+if &index==&last_index
+(
+ &index=-1
+)
+RETURN &index
+
+; ---------------------------------------------------------
+GetMinTimeIndex:
+ENTRY &cnt
+local &i &min_index &min_val
+local &value &index
+
+&i=0.
+&min_index=0.
+&min_val=0xFFFFFFFF
+
+while &i<&cnt
+(
+ &index=string.cut("&i",-1)
+ &&value=&os_time&index
+ if (&value!=-1)&&(&min_val>=&value)
+ (
+ &min_val=&value
+ &min_index=&i
+ )
+ &i=&i+1
+)
+
+RETURN &min_index
+
+; ---------------------------------------------------------
+GetMinTime:
+ENTRY &cnt
+local &i &min_index &min_val
+local &value &index
+
+&i=0.
+&min_index=0.
+&min_val=0xFFFFFFFF
+
+while &i<&cnt
+(
+ &index=string.cut("&i",-1)
+ &&value=&os_time&index
+ if (&value!=-1)&&(&min_val>=&value)
+ (
+ &min_val=&value
+ &min_index=&i
+ )
+ &i=&i+1
+)
+
+RETURN &min_val
+
+; ---------------------------------------------------------
+TosPrintNextLine:
+local &time &str &line_index
+
+
+gosub GetMinTimeIndex &os_time_cnt
+ENTRY &index
+
+if &index==0
+(
+ local &task &addr
+ &task=v.value(g_os_ddr_swapin_statistic->statistics[&os_swap_next].data1)
+ &addr=v.value(&((Cyg_Thread*)&task)->thread_name)
+ &str="THREAD: "+data.string(D:&addr)
+ &line_index=&os_swap_next
+ &time=&os_time0
+ gosub GetNextIndex &os_swap_cnt &os_swap_last &os_swap_next
+ ENTRY &os_swap_next
+ if &os_swap_next==-1
+ (
+ &os_time0=-1
+ )
+ else
+ (
+ &os_time0=v.value(g_os_ddr_swapin_statistic->statistics[&os_swap_next].data2)
+ )
+)
+else if &index==1
+(
+ local &irq &addr
+ &irq=v.value(g_os_ddr_irq_start_statistic->statistics[&os_irq_start_next].data1)
+ &str="IRQSTA: "+format.DecimalU(1,&irq)+" S"
+ &line_index=&os_irq_start_next
+ &time=&os_time1
+ gosub GetNextIndex &os_irq_start_cnt &os_irq_start_last &os_irq_start_next
+ ENTRY &os_irq_start_next
+ if &os_irq_start_next==-1
+ (
+ &os_time1=-1
+ )
+ else
+ (
+ &os_time1=v.value(g_os_ddr_irq_start_statistic->statistics[&os_irq_start_next].data2)
+ )
+)
+else if &index==2
+(
+ local &irq &addr
+ &irq=v.value(g_os_ddr_irq_end_statistic->statistics[&os_irq_end_next].data1)
+ &str="IRQEND: "+format.DecimalU(1,&irq)+" E"
+ &line_index=&os_irq_end_next
+ &time=&os_time2
+ gosub GetNextIndex &os_irq_end_cnt &os_irq_end_last &os_irq_end_next
+ ENTRY &os_irq_end_next
+ if &os_irq_end_next==-1
+ (
+ &os_time2=-1
+ )
+ else
+ (
+ &os_time2=v.value(g_os_ddr_irq_end_statistic->statistics[&os_irq_end_next].data2)
+ )
+)
+else if &index==3
+(
+ local &dsr &addr
+ &dsr=v.value(g_os_ddr_dsr_start_statistic->statistics[&os_dsr_start_next].data1)
+ &str="DSRSTA: "+format.DecimalU(1,&dsr)+" S"
+ &line_index=&os_dsr_start_next
+ &time=&os_time3
+ gosub GetNextIndex &os_dsr_start_cnt &os_dsr_start_last &os_dsr_start_next
+ ENTRY &os_dsr_start_next
+ if &os_dsr_start_next==-1
+ (
+ &os_time3=-1
+ )
+ else
+ (
+ &os_time3=v.value(g_os_ddr_dsr_start_statistic->statistics[&os_dsr_start_next].data2)
+ )
+)
+else if &index==4
+(
+ local &dsr &addr
+ &dsr=v.value(g_os_ddr_dsr_end_statistic->statistics[&os_dsr_end_next].data1)
+ &str="DSREND: "+format.DecimalU(1,&dsr)+" E"
+ &line_index=&os_dsr_end_next
+ &time=&os_time4
+ gosub GetNextIndex &os_dsr_end_cnt &os_dsr_end_last &os_dsr_end_next
+ ENTRY &os_dsr_end_next
+ if &os_dsr_end_next==-1
+ (
+ &os_time4=-1
+ )
+ else
+ (
+ &os_time4=v.value(g_os_ddr_dsr_end_statistic->statistics[&os_dsr_end_next].data2)
+ )
+)
+else
+(
+ print "Unknown Type"
+)
+
+gosub GetMinTime &os_time_cnt
+ENTRY &os_next_time
+
+print format.string("&str",32,' ')+" "+format.DecimalU(8,&line_index)+" "+format.DecimalU(1,&time)+" "+format.DecimalU(1,&os_next_time-&time)
+
+RETURN
+
+; ---------------------------------------------------------
+TosTrace:
+local &result
+
+if v.value(g_os_ddr_swapin_statistic)==0
+(
+ RETURN
+)
+
+&os_swap_last=v.value(g_os_ddr_swapin_statistic->index)
+&os_swap_cnt=v.value(sizeof(g_os_ddr_swapin_statistic->statistics)/sizeof(g_os_ddr_swapin_statistic->statistics[0]))
+&os_swap_next=&os_swap_last
+
+if &os_irq_enable==1
+(
+ &os_irq_start_last=v.value(g_os_ddr_irq_start_statistic->index)
+ &os_irq_start_cnt=v.value(sizeof(g_os_ddr_irq_start_statistic->statistics)/sizeof(g_os_ddr_irq_start_statistic->statistics[0]))
+ &os_irq_start_next=&os_irq_start_last
+ &os_irq_end_last=v.value(g_os_ddr_irq_end_statistic->index)
+ &os_irq_end_cnt=v.value(sizeof(g_os_ddr_irq_end_statistic->statistics)/sizeof(g_os_ddr_irq_end_statistic->statistics[0]))
+ &os_irq_end_next=&os_irq_end_last
+)
+else
+(
+ &os_irq_start_next=-1
+ &os_irq_end_next=-1
+)
+
+if &os_dsr_enable==1
+(
+ &os_dsr_start_last=v.value(g_os_ddr_dsr_start_statistic->index)
+ &os_dsr_start_cnt=v.value(sizeof(g_os_ddr_dsr_start_statistic->statistics)/sizeof(g_os_ddr_dsr_start_statistic->statistics[0]))
+ &os_dsr_start_next=&os_dsr_start_last
+ &os_dsr_end_last=v.value(g_os_ddr_dsr_end_statistic->index)
+ &os_dsr_end_cnt=v.value(sizeof(g_os_ddr_dsr_end_statistic->statistics)/sizeof(g_os_ddr_dsr_end_statistic->statistics[0]))
+ &os_dsr_end_next=&os_dsr_end_last
+)
+else
+(
+ &os_dsr_start_next=-1
+ &os_dsr_end_next=-1
+)
+
+if &os_swap_next==-1
+(
+ &os_time0=-1
+)
+else
+(
+ &os_time0=v.value(g_os_ddr_swapin_statistic->statistics[&os_swap_next].data2)
+)
+if &os_irq_start_next==-1
+(
+ &os_time1=-1
+)
+else
+(
+ &os_time1=v.value(g_os_ddr_irq_start_statistic->statistics[&os_irq_start_next].data2)
+)
+if &os_irq_end_next==-1
+(
+ &os_time2=-1
+)
+else
+(
+ &os_time2=v.value(g_os_ddr_irq_end_statistic->statistics[&os_irq_end_next].data2)
+)
+
+if &os_dsr_start_next==-1
+(
+ &os_time3=-1
+)
+else
+(
+ &os_time3=v.value(g_os_ddr_dsr_start_statistic->statistics[&os_dsr_start_next].data2)
+)
+if &os_dsr_end_next==-1
+(
+ &os_time4=-1
+)
+else
+(
+ &os_time4=v.value(g_os_ddr_dsr_end_statistic->statistics[&os_dsr_end_next].data2)
+)
+
+&os_time_cnt=5.
+&os_next_time=0.
+
+print format.string("Name",32,' ')+" "+"Index"+" "+"Time"+" "+"Exce"
+
+&result=0
+while &result==0
+(
+ gosub TosPrintNextLine
+ if ((&os_swap_next==-1)&&(&os_irq_start_next==-1)&&(&os_irq_end_next==-1)&&(&os_dsr_start_next==-1)&&(&os_dsr_end_next==-1))
+ (
+ print "END"
+ &result=-1
+ )
+)
+
+RETURN
diff --git a/ap/build/scripts/trace32/zx297520v3/readme b/ap/build/scripts/trace32/zx297520v3/readme
new file mode 100755
index 0000000..8f8bade
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/readme
@@ -0,0 +1,17 @@
+£»----------------------------
+£»7520v3
+£»----------------------------
+1) load(jtag0)
+step1: run 7520V3_DDR_1Gb_312.cmm
+step2: run linux_297520v3_evb.cmm
+
+2) attach(jtag0):
+step1: run boot_attach_CortexA53_ap.cmm
+step2: run linux_297520v3evb_attach.cmm
+
+3) switch core_ap-->core_ps(jtag0)
+step1: T32 Menu
+ ==> 7520Board
+ ==> Jtag Switch Use CMM
+ ==> Switch to PsJtag
+
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_clean_cache.cmm b/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_clean_cache.cmm
new file mode 100755
index 0000000..4ca0a64
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_clean_cache.cmm
@@ -0,0 +1,56 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2012 ZTE Corporation.
+//*
+//**************************************************************************
+//* Ä£ ¿é Ãû :
+//* ÎÄ ¼þ Ãû : lib_clean_cache.cmm
+//* Ïà¹ØÎļþ :
+//* ʵÏÖ¹¦ÄÜ : Çå³ýÊý¾Ýcache»º´æµÄ½Å±¾£»
+//* ×÷ Õß :
+//* °æ ±¾ : V1.0
+//* Íê³ÉÈÕÆÚ : 2013/08/18
+//* ÆäËü˵Ã÷ :
+//**************************************************************************
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &cache_type_reg
+local &data_cache_size
+local &data_cache_assoc
+local &data_cache_len
+local &loop_index_assoc
+local &max_assoc_loop
+local &loop_index_set
+local &max_set_loop
+local &data
+
+print "Cleaning all Data cache..."
+
+&cache_type_reg=data.long(C15:0X100)
+&data_cache_size=(&cache_type_reg&0x1c0000)>>0x12
+&data_cache_assoc=(&cache_type_reg&0x38000)>>0xf
+&data_cache_len=(&cache_type_reg&0x3000)>>0xc
+&max_assoc_loop=1<<(&data_cache_assoc)
+&max_set_loop=1<<(&data_cache_size+6-&data_cache_assoc-&data_cache_len)
+&loop_index_assoc=0
+while &loop_index_assoc<&max_assoc_loop
+(
+ &loop_index_set=0
+ while &loop_index_set<&max_set_loop
+ (
+ &data=(&loop_index_assoc<<(0x20-&data_cache_assoc))+(&loop_index_set<<(&data_cache_len+3))
+ d.s C15:0x2a7 %long &data
+ &loop_index_set=&loop_index_set+0x1
+ )
+ wait 10.ms
+ &loop_index_assoc=&loop_index_assoc+0x1
+)
+
+print "...done cleaning all Data cache"
+
+ENDDO
+
diff --git a/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_get_func_mode.cmm b/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_get_func_mode.cmm
new file mode 100755
index 0000000..2b6071c
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_get_func_mode.cmm
@@ -0,0 +1,80 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2012 ZTE Corporation.
+//*
+//**************************************************************************
+//* Ä£ ¿é Ãû :
+//* ÎÄ ¼þ Ãû : lib_get_func_mode.cmm
+//* Ïà¹ØÎļþ :
+//* ʵÏÖ¹¦ÄÜ : »ñÈ¡º¯Êý²ÉÓÃÄÄÖÖ±àÂ뷽ʽ(arm¡¢thumb)
+//* ×÷ Õß : ¸ß»ª·å
+//* °æ ±¾ : V1.0
+//* Íê³ÉÈÕÆÚ : 2013/08/18
+//* ÆäËü˵Ã÷ :
+//**************************************************************************
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿£»
+local &startAddr &endAddr &result
+
+entry &startAddr &endAddr
+gosub zT32_GetFuncMode &startAddr &endAddr
+entry &result
+enddo &result
+
+//**************************************************************************
+//* º¯ÊýÃû³Æ£ºzT32_GetFuncMode
+//* ¹¦ÄÜÃèÊö£º»ñÈ¡º¯Êý²ÉÓõıàÂ뷽ʽ(armÖ¸Áîģʽ»¹ÊÇthumbÖ¸Áî)
+//* ²ÎÊý˵Ã÷£º(IN)
+//* insStartAddr : Ö¸ÁîµÄÆðʼµØÖ·£»
+//* insEndAddr : Ö¸ÁîµÄ½áÊøµØÖ·£»
+//*
+//* ·µ »Ø Öµ£º
+//* ÆäËü˵Ã÷£ºÕë¶ÔÓÐѹջ²Ù×÷µÄº¯Êý£»
+//***************************************************************************
+zT32_GetFuncMode:
+ local &pushIns &pushMask &insStartAddr &insEndAddr
+ local &stm1Ins &stm1Mask &stm2Ins &stm2Mask
+
+ entry &insStartAddr &insEndAddr
+ if &insStartAddr>=&insEndAddr
+ (
+ return &ZT32_NOMODE
+ )
+ &pushIns=0xb400
+ &pushMask=0xfe00
+ &stm1Ins=0x9000000
+ &stm1Mask=0xFD00000
+ &stm2Ins=0x9400000
+ &stm2Mask=0xFF00000
+ &instruction=data.word(d:&insStartAddr)
+
+ //ÅжÏÊÇ·ñÊÇpushÓï¾ä
+ &result=v.value((&instruction)&(&pushMask))
+ if &result==&pushIns
+ (
+ return &ZT32_THUMBMODE
+ )
+ else
+ (
+ &instruction=data.long(d:&insStartAddr)
+ &result=v.value((&instruction)&(&stm1Mask))
+ if &result==&stm1Ins
+ (
+ return &ZT32_ARMMODE
+ )
+ &result=v.value((&instruction)&(&stm2Mask))
+ if &result==&stm2Ins
+ (
+ &result=&ZT32_ARMMODE
+ return &result
+ )
+ &insStartAddr=&insStartAddr+2
+ gosub zT32_GetFuncMode &insStartAddr &insEndAddr
+ entry &result
+ return &result
+ )
+
diff --git a/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_left_align.cmm b/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_left_align.cmm
new file mode 100755
index 0000000..95da068
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_left_align.cmm
@@ -0,0 +1,44 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2012 ZTE Corporation.
+//*
+//**************************************************************************
+//* Ä£ ¿é Ãû :
+//* ÎÄ ¼þ Ãû : lib_left_align.cmm
+//* Ïà¹ØÎļþ :
+//* ʵÏÖ¹¦ÄÜ : ×Ö·û´®×ó¶ÔÆ룻
+//* ×÷ Õß : ¸ß»ª·å
+//* °æ ±¾ : V1.0
+//* Íê³ÉÈÕÆÚ : 2013/08/18
+//* ÆäËü˵Ã÷ :
+//**************************************************************************
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &string &spaceNum
+
+//ʵÏÖ×Ö·û´®×ó¶ÔÆëµÄ¹¦ÄÜ£»
+entry &formatWidth &formatTitle
+&result=string.len("&formatTitle")
+if &formatWidth<=&result
+(
+ &string="&formatTitle"
+)
+else
+(
+ &string="&string"+"&formatTitle"
+ repeat &formatWidth-&result
+ (
+ &string="&string"+" "
+ )
+)
+&spaceNum=5
+repeat &spaceNum
+(
+ &string="&string"+" "
+)
+enddo "&string"
+
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_print.cmm b/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_print.cmm
new file mode 100755
index 0000000..03635e8
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_print.cmm
@@ -0,0 +1,32 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2012 ZTE Corporation.
+//*
+//**************************************************************************
+//* Ä£ ¿é Ãû :
+//* ÎÄ ¼þ Ãû : lib_print.cmm
+//* Ïà¹ØÎļþ :
+//* ʵÏÖ¹¦ÄÜ : ´òÓ¡¶à´Îij¸ö×Ö·û´®£»
+//* ×÷ Õß : ¸ß»ª·å
+//* °æ ±¾ : V1.0
+//* Íê³ÉÈÕÆÚ : 2013/08/18
+//* ÆäËü˵Ã÷ :
+//**************************************************************************
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &string
+
+//ʵÏÖ´òÓ¡¶à´Îij¸ö×Ö·û´®µÄ¹¦ÄÜ
+entry &title &num
+&string=""
+repeat &num
+(
+ &string="&string"+&title
+)
+print %string "&string"
+enddo
+
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_right_align.cmm b/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_right_align.cmm
new file mode 100755
index 0000000..b64f495
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/stack_analysis/lib_right_align.cmm
@@ -0,0 +1,46 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2012 ZTE Corporation.
+//*
+//**************************************************************************
+//* Ä£ ¿é Ãû :
+//* ÎÄ ¼þ Ãû : lib_right_align.cmm
+//* Ïà¹ØÎļþ :
+//* ʵÏÖ¹¦ÄÜ :
+//* ×÷ Õß : ¸ß»ª·å
+//* °æ ±¾ : V1.0
+//* Íê³ÉÈÕÆÚ : 2013/08/18
+//* ÆäËü˵Ã÷ :
+//**************************************************************************
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &string &spaceNum
+
+//ʵÏÖ×Ö·û´®ÓÒ¶ÔÆëµÄ¹¦ÄÜ
+entry &formatWidth &formatTitle
+&result=string.len("&formatTitle")
+if &formatWidth<=&result
+(
+ &string="&formatTitle"
+)
+else
+(
+ &string="&string"+"&formatTitle"
+ repeat &formatWidth-&result
+ (
+ &string=" "+"&string"
+ )
+)
+
+&spaceNum=5
+repeat &spaceNum
+(
+ &string="&string"+" "
+)
+
+enddo "&string"
+
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/stack_analysis/linux_stack_analysis.cmm b/ap/build/scripts/trace32/zx297520v3/stack_analysis/linux_stack_analysis.cmm
new file mode 100755
index 0000000..1f41713
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/stack_analysis/linux_stack_analysis.cmm
@@ -0,0 +1,420 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2012 ZTE Corporation.
+//*
+//**************************************************************************
+//* Ä£ ¿é Ãû :
+//* ÎÄ ¼þ Ãû : linux_stack_analysis.cmm
+//* Ïà¹ØÎļþ :
+//* ʵÏÖ¹¦ÄÜ : linuxÏÂÓ¦Óýø³ÌÕ»½âÎö½Å±¾£»
+//* ×÷ Õß :
+//* °æ ±¾ : V1.0
+//* Íê³ÉÈÕÆÚ : 2013/08/18
+//* ÆäËü˵Ã÷ :
+//**************************************************************************
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+
+//Ñ¡ÔñÓû§Ì¬Õ»»òÕßÄÚºË̬ջ:1:»Ö¸´Ó¦ÓÃ̬ջ;0:»Ö¸´ÄÚºË̬ջ
+local &usr_or_kernel_flag
+
+&usr_or_kernel_flag=1
+
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &fileColumns &fileLines
+local &stackBegin &stackEnd &stackAddress
+local &functionName &result &level &value
+local &width &string
+local &blIns &blxIns &ldrIns
+local &blInsMask &blxInsMask &ldrInsMask
+local &blThumbIns &blx1ThumbIns &blx2ThumbIns &b1ThumbIns &b2ThumbIns &bxThumbIns &bxThumbIns
+local &blInsThumbMask &blx1InsThumbMask &blx2InsThumbMask
+local &b1InsThumbMask &b2InsThumbMask &bxInsThumbMask
+local &pcbMagic &pName &first &pc &preFunStack
+local &mmu_cr &mmuFirstBase
+local &stmr13 &subr13
+local &stmr13Mask &subr13Mask
+local &usercpsr &usersp &kernelstartsp &kernelendsp
+
+//»ñÈ¡»·¾³±äÁ¿
+&first=1
+&pc=""
+
+//armÖ¸ÁîÌøתָÁîÂë(B BX BL BLX)
+&blInsMask=0x0E000000 //BIT27:25(101)
+&blIns=0x0A000000
+&blxInsMask=0X0FFFFF00 //BIT27:8(00010010111111111111)
+&blxIns=0x012FFF00
+&ldrInsMask=0x0C00f000 //BIT27:26(01) BIT15:12(10)
+&ldrIns=0x0400f000
+
+//thumbÖ¸ÁîÏÂÌøתָÁîÂë
+&blThumbIns=0xf800
+&blInsThumbMask=0xf800
+&blx1ThumbIns=0xf000
+&blx1InsThumbMask=0xf800
+&blx2ThumbIns=0x4780
+&blx2InsThumbMask=0xff80
+&b1ThumbIns=0xd000
+&b1InsThumbMask=0xf000
+&b2ThumbIns=0xd000
+&b2InsThumbMask=0xf800
+&bxThumbIns=0x4700
+&bxInsThumbMask=0xf800
+
+//´´½¨ÏÔʾ´°¿Ú£»
+&fileColumns=100.
+&fileLines=500.
+
+area.create stack &fileColumns &fileLines
+area.clear stack
+area.select stack
+area.view stack
+
+//´ò¿ªÎļþ
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\stack.txt"
+area.open stack &file
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+//»ñÈ¡Óû§Ì¬µ±Ç°µÄÕ»Ö¸Õ뼰״̬¼Ä´æÆ÷µÄÖµ£¬ÄÚºË̬µ±Ç°Õ»Ö¸Õë
+&kernelstartsp=R(R13)
+FRAME.COPY
+while (R(CPSR)&0x1F)!=0x10
+(
+ FRAME.UP
+)
+
+&usercpsr=R(CPSR)
+&usersp=R(R13)
+FRAME.DOWN
+&kernelendsp=R(R13)
+FRAME.SWAP
+
+if &usr_or_kernel_flag==0x1
+(
+ //&pcbMagic=v.value(((struct rq)runqueues)->curr)
+ &stackBegin=v.value(((struct rq)runqueues)->curr->mm->start_stack)
+ &stackEnd=&usersp-0x400
+ &pName=v.string(((struct rq)runqueues)->curr->comm)+"Óû§Ì¬"
+)
+else
+(
+ &stackBegin=&kernelendsp
+ &stackEnd=&kernelstartsp
+ &pName=v.string(((struct rq)runqueues)->curr->comm)+"ÄÚºË̬"
+)
+
+if &stackEnd>=&stackBegin
+(
+ print " µØÖ·ÎÞЧ"
+ print ""
+ enddo
+)
+
+//title
+
+&nameWidth=0x30
+&string="&pNameµÄÕ»ÐÅÏ¢"
+do lib_right_align.cmm &nameWidth &string
+entry &string
+print %string &string
+print %string "-------------------------------------------------------------------------------"
+
+//¸ñʽ»¯´òÓ¡title " level sp lr func"
+&width=10.
+&title="level"
+do lib_left_align.cmm &width &title
+entry &result
+&string=&result
+&width=15.
+&title="sp"
+do lib_left_align.cmm &width &title
+entry &result
+&string="&string"+&result
+&title="lr"
+do lib_left_align.cmm &width &title
+entry &result
+&string="&string"+&result
+&title="func"
+do lib_left_align.cmm &width &title
+entry &result
+&string="&string"+&result
+print %string "&string"
+&string=""
+//Ä£ÄâÆ÷ÎÞÐè·ÖÎöMMUÒ³±í
+if SIMULATOR()
+(
+ &mmu_cr=data.long(C15:0X1)
+ &mmuFirstBase=data.long(C15:0X2)
+)
+
+&stackAddress=&stackBegin
+&level=0
+WHILE &stackAddress>=&stackEnd
+(
+ gosub zT32_IsValidAdd &stackAddress
+ entry &result
+ &stackSize=4
+ if &result==0
+ (
+ goto addressIncrease
+ )
+ &value=data.long(d:&stackAddress)
+
+ &functionName=""
+ GOSUB zT32_IsFuncRetAddr &value "&functionName"
+ entry &result
+ if &result==1
+ (
+ &width=10.
+ &level=&level+1
+ &title=format.decimal(1., &level)
+ do lib_left_align.cmm &width &title
+ entry &result
+ &string=&result
+ &width=15.
+ &title="0x"+format.hex(1., &stackAddress)
+ do lib_left_align.cmm &width &title
+ entry &result
+ &string="&string"+&result
+ &title="0x"+format.hex(1., &value)
+ do lib_left_align.cmm &width &title
+ entry &result
+ &string="&string"+&result
+ &functionName=os.file.name("&functionName") //¹ýÂËÇ°Ãæ·¾¶
+ &string="&string"+"&functionName"+"()"
+ print %string "&string"
+ )
+
+addressIncrease:
+ &stackAddress=&stackAddress-4
+)
+
+if &stackAddress<&stackEnd&&&first==1
+(
+ &first=0
+ &pc=&value
+ print %string "-------------------------------------------------------------------------------"
+)
+
+if &first==0&&&usr_or_kernel_flag==1
+(
+ print %string "-------------------------------------------------------------------------------"
+ print %string " Óû§Ì¬¶ÑÕ»»ØËݲ鿴º¯Êýµ÷ÓÃ,ÇëÌæ»»ÈçϼĴæÆ÷"
+ print %string " r13=sp+4 pc=lr usrcpsr=&usercpsr"
+)
+
+print %string "-------------------------------------------------------------------------------"
+area.view stack
+area.close stack
+enddo
+
+//**************************************************************************
+//* º¯ÊýÃû³Æ£ºzT32_IsFuncRetAddr
+//* ¹¦ÄÜÃèÊö£ºÅжÏÕ»ÄÚÈÝÊÇ·ñÊǺ¯ÊýµÄ·µ»ØµØÖ·
+//* ²ÎÊý˵Ã÷£º(IN)
+//* value :Õ»ÄÚÈÝ
+//* (OUT)
+//* functionName :º¯ÊýµÄÃû×Ö
+//* ·µ »Ø Öµ£º
+//* ÆäËü˵Ã÷£º
+//***************************************************************************
+zT32_IsFuncRetAddr:
+ local &instruction &preName
+ local &findByFunction
+
+ entry &value &functionName
+ &preName=""
+ &findByFunction=1
+
+ //ÅжÏÕ»µØÖ·ÄÚÈÝ×÷ΪµØÖ·ÊÇ·ñ¿É·ÃÎÊ
+ gosub zT32_IsValidAdd &value
+ entry &result
+ if &result==0
+ (
+ return 0
+ )
+ gosub zT32_IsValidAdd (&value-0x4)
+ entry &result
+ if &result==0
+ (
+ return 0
+ )
+ &value=(&value/4)*4
+
+ //ÅжÏÕ»µØÖ·ÄÚÈÝÊÇ·ñÊǺ¯Êý
+ &functionName=Y.function(p:&value)
+ if "&functionName"==""
+ (
+ //&findByFunction=0
+ //&functionName=Y.name(p:&value)
+ //if "&functionName"==""
+ //(
+ return 0
+ //)
+ )
+
+ //ÅжÏ*sp-4Óë*spÊÇ·ñÔÚͬһº¯ÊýÌåÄÚ
+ if &findByFunction==1
+ (
+ &preName=Y.function(p:&value-4)
+ )
+ //else
+ //(
+ // &preName=Y.name(p:&value-4)
+ //)
+ if "&preName"!="&functionName"
+ (
+ return 0
+ )
+ &value=(&value/4)*4
+ //ÅжÏ*sp-4ÊÇ·ñÊÇÌøתÓï¾ä
+ &instruction=data.long(d:&value-4)
+
+ //ÅжÏ*sp-4ÊÇ·ñÊÇARMÖ¸ÁîģʽϵÄb,bl,blx(1)Óï¾ä
+ &result=v.value((&instruction)&(&blInsMask))
+ if &result==&blIns
+ (
+ return 1
+ )
+ //ÅжÏ*sp-4ÊÇ·ñÊÇARMÖ¸ÁîģʽϵÄblx(2),bxÓï¾ä
+ &result=v.value((&instruction)&(&blxInsMask))
+ if &result==&blxIns
+ (
+ return 1
+ )
+
+ //ÅжÏÊÇ·ñÊÇARMÖ¸ÁîģʽϵÄldr pc,*Óï¾ä
+ &result=v.value((&instruction)&(&ldrInsMask))
+ if &result==&ldrIns
+ (
+ return 1
+ )
+
+ //ÅжÏÊÇ·ñthumbÖ¸Áî
+ if (&value&0x1)==0x1
+ (
+ &value=&value-1
+ )
+ else
+ (
+ return 0
+ )
+
+ gosub zT32_IsValidAdd (&value-2)
+ entry &result
+ if &result==0
+ (
+ return 0
+ )
+
+ //ÅжÏ*sp-2ÊÇ·ñÊÇthumbÖ¸ÁîģʽϵÄblÓï¾ä
+ &instruction=data.word(d:&value-2)
+ &result=v.value((&instruction)&(&blThumbIns))
+ if &result==&blThumbIns
+ (
+ return 1
+ )
+
+ //ÅжÏ*sp-2ÊÇ·ñÊÇthumbÖ¸ÁîģʽϵÄblx(1)Óï¾ä
+ &result=v.value((&instruction)&(&blx1ThumbIns))
+ if &result==&blx1ThumbIns
+ (
+ return 1
+ )
+
+ //ÅжÏ*sp-2ÊÇ·ñÊÇthumbÖ¸ÁîģʽϵÄblx(2)Óï¾ä
+ &result=v.value((&instruction)&(&blx2ThumbIns))
+ if &result==&blx2ThumbIns
+ (
+ return 1
+ )
+
+ //ÅжÏ*sp-2ÊÇ·ñÊÇthumbÖ¸ÁîģʽϵÄb(1)Óï¾ä
+ &result=v.value((&instruction)&(&b1InsThumbMask))
+ if &result==&b1ThumbIns
+ (
+ return 1
+ )
+
+ //ÅжÏ*sp-2ÊÇ·ñÊÇthumbÖ¸ÁîģʽϵÄb(2)Óï¾ä
+ &result=v.value((&instruction)&(&b2InsThumbMask))
+ if &result==&b2ThumbIns
+ (
+ return 1
+ )
+
+ //ÅжÏ*sp-2ÊÇ·ñÊÇthumbÖ¸ÁîģʽϵÄbxÓï¾ä
+ &result=v.value((&instruction)&(&bxInsThumbMask))
+ if &result==&bxThumbIns
+ (
+ return 1
+ )
+ else
+ (
+ return 0
+ )
+
+//**************************************************************************
+//* º¯ÊýÃû³Æ£ºisValidAddress
+//* ¹¦ÄÜÃèÊö£ºÅжÏÂß¼µØÖ·ÊÇ·ñºÏ·¨
+//* ²ÎÊý˵Ã÷£º(IN)
+//* logicAddress :Âß¼µØÖ·
+//* ·µ »Ø Öµ£º
+//* ÆäËü˵Ã÷£º
+//***************************************************************************
+zT32_IsValidAdd:
+ local &mmuSecondBase &mmuDiscript &mmuOffset
+
+ entry &logicAddress
+
+ //Ä£ÄâÆ÷ÎÞÐè·ÖÎöMMUÒ³±í
+ if SIMULATOR()
+ (
+ return 1
+ )
+ //&logicAddress=0x2CB40
+ //disable MMU
+ per.s c15:0x1 %long (&mmu_cr&0xfffffffe)
+ &mmuOffset=&logicAddress>>20.
+ &mmuDiscript=v.value(((UINT32 *)&mmuFirstBase)[&mmuOffset])
+ &mmuvalue=&mmuDiscript&0x3
+ if &mmuvalue==0 //ÎÞЧ
+ (
+ //restore MMU Âß¼µØÖ·ÓëÎïÀíµØÖ·²»¶ÔÓ¦£¬²»ÄܽûÖ¹MMU
+ per.s c15:0x1 %long &mmu_cr
+ return 0
+ )
+
+ if &mmuvalue==2 //¶ÎÒ³±í
+ (
+ per.s c15:0x1 %long &mmu_cr
+ return 1
+ )
+
+ //´ÖÁ£¶È¶þ¼¶Ò³±í
+ &mmuSecondBase=&mmuDiscript&0xfffffc00
+ &mmuOffset=(&logicAddress&0xff000)>>12.
+ &mmuDiscript=v.value(((UINT32 *)&mmuSecondBase)[&mmuOffset])
+ &mmuvalue=&mmuDiscript&0Xff0
+ per.s c15:0x1 %long &mmu_cr
+ if &mmuvalue==0 //ûÓзÃÎÊȨÏÞ
+ (
+ return 0
+ )
+
+ return 1
+
diff --git a/ap/build/scripts/trace32/zx297520v3/stack_analysis/os_search_nv_list.cmm b/ap/build/scripts/trace32/zx297520v3/stack_analysis/os_search_nv_list.cmm
new file mode 100755
index 0000000..b76212d
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/stack_analysis/os_search_nv_list.cmm
@@ -0,0 +1,79 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2017 ZTE Corporation.
+//*
+//**************************************************************************
+// pl
+
+//**************************************************************************
+//* tos msgrcvÏûÏ¢¶ÓÁнű¾½âÎö
+//* ´«ÈëÏûÏ¢µÄlTgtMsgIDºÍµ¥¸öÏûÏ¢µÄ½á¹¹Ìå
+//**************************************************************************
+
+//¶¨Òå¾Ö²¿±äÁ¿
+local &searchAddress
+local &listHead &next
+local &i &count
+local &nvItem &nvNextItem &count
+
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=200.
+&nameWidth=20.
+&fileColumns=200.
+&fileLines=500.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\result.txt"
+area.open trace &file
+area.view trace
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+print %string "--------------------------------------------------------------------"
+
+&count=0
+while &count!=0x200
+(
+ &nvItem=v.value((*(nv_list)).nvTable[&count])
+ if &nvItem!=0x0
+ (
+ &nvkey=v.string(((T_NV_ITEM*)&nvItem)->key)
+ &nvkey=format.string("&nvkey",200,' ')
+ &nvvalue=v.string(((T_NV_ITEM *)&nvItem).value)
+ &nvvalue=format.string("&nvvalue",200,' ')
+ print "NV Key:&nvkey"
+ print "NV Value:&nvvalue"
+ print %string "--------------------------------------------------------------------"
+ &nvnext=v.value(((T_NV_ITEM *)&nvItem).next)
+ while &nvnext!=0x0
+ (
+ &nvkey=v.string(((T_NV_ITEM*)&nvnext)->key)
+ &nvvalue=v.string(((T_NV_ITEM *)&nvnext).value)
+ &nvkey=format.string("&nvkey",200,' ')
+ &nvvalue=format.string("&nvvalue",200,' ')
+ print "NV Key:&nvkey"
+ print "NV Value:&nvvalue"
+ print %string "--------------------------------------------------------------------"
+ &nvnext=v.value(((T_NV_ITEM *)&nvnext).next)
+ )
+ )
+ &count=&count+1
+)
+print "&count----------------------------------------------------------------"
+area.close trace
+ENDDO
+//****ÔËÐнáÊø*****
+
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/board.men b/ap/build/scripts/trace32/zx297520v3/sys/board.men
new file mode 100755
index 0000000..2d15a5b
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/board.men
@@ -0,0 +1,93 @@
+;==========================================================================
+; Name:
+; zte.mem
+; Description:
+; Éú³ÉOSE²Ëµ¥
+;==========================================================================
+
+;==========================================================================
+; EDIT HISTRORY FOR MODULE
+;
+; when who what, where, why
+;07/25/13 ¸ð°²·å¡¡¡¡¡¡¡¡¡¡´´½¨
+;06/10/14 ÀîÃÀ·æ 7520ÐÞ¸Ä
+;==========================================================================
+
+add
+menu
+(
+ popup "&7520Board"
+ (
+ popup "&Jtag Switch Use CMM"
+ (
+ popup "&Jtag0"
+ (
+ menuitem "&Switch to M0Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 0 0
+ )
+ menuitem "&Switch to PsJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 0 1
+ )
+ menuitem "&Switch to ZspJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 0 2
+ )
+ menuitem "&Switch to A53Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 0 3
+ )
+ )
+
+ popup "&Jtag1"
+ (
+ menuitem "&Switch to M0Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 1 0
+ )
+ menuitem "&Switch to PsJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 1 1
+ )
+ menuitem "&Switch to ZspJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 1 2
+ )
+ menuitem "&Switch to A53Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 1 3
+ )
+ )
+
+ popup "&Jtag2"
+ (
+ menuitem "&Switch to M0Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 2 0
+ )
+ menuitem "&Switch to PsJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 2 1
+ )
+ menuitem "&Switch to ZspJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 2 2
+ )
+ menuitem "&Switch to A953Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 2 3
+ )
+ )
+
+ )
+
+ separator
+ menuitem "Clocks"
+ (
+ run .\sys\clocks.cmm
+ )
+ separator
+
+ )
+)
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/boot.cmm b/ap/build/scripts/trace32/zx297520v3/sys/boot.cmm
new file mode 100755
index 0000000..2d7b910
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/boot.cmm
@@ -0,0 +1,18 @@
+area.reset
+sys.cpu CortexM0
+sys.bdmclock 3.0MHz ;cortex-m0
+sys.o enreset OFF
+sys.up
+
+do ./sys/clk_init.cmm
+do ./sys/ddr_init_312m.cmm
+
+//M0 address remap bit23
+data.set 0x00140000 %long 0x00870000
+
+// Release R7/A53 reset signal
+data.set 0x0013b138 %long 0x00000001 // R7
+data.set 0x0013b134 %long 0x00000001 // A53
+
+//jtag0 to ap
+do ./sys/jtag_switch_script.cmm 0 3
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/clk_init.cmm b/ap/build/scripts/trace32/zx297520v3/sys/clk_init.cmm
new file mode 100755
index 0000000..57acdec
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/clk_init.cmm
@@ -0,0 +1,22 @@
+//MPLL power on
+data.set 0x0013b008 %long 0x08040c11
+//UPLL power on
+data.set 0x0013b010 %long 0x08347811
+//DPLL power on, ref clk sel bit25-26, 0=dpll1, 1=sys_clk_in, 2=lte_ref_clk, 3=main_clk
+//data.set 0x0013b018 %long 0x0c040c19
+//GPLL power on
+data.set 0x0013b110 %long 0x08347d29
+
+//M0 select 104M, bit0-1, 0=104, 1=26, 2=78, 3=32k
+data.set 0x0013b038 %long 0x00000005
+//hs_ahb_clk select 104M, bit4-5, 0=104, 1=26, 2=78, 3=32k
+data.set 0x0013b03c %long 0x00000010
+
+//AXI select 156M, bit0-2, 0=156, 1=26, 2=122.88, 3=104, 4=78, 5=52, 6=39
+data.set 0x01306000 %long 0x00010001
+//R7 select 624M, bit0-2, 0=624, 1=26, 2=491.5, 3=312, 4=208, 5=104, 6=78, 7=52
+data.set 0x01306020 %long 0x00000001
+//ZSP880 select 491M, bit0-2, 0=491.52, 1=26, 2=312, 3=208, 4=156, 5=104, 6=78
+data.set 0x01306030 %long 0x00000001
+//A53 select 624M, bit0-2, 0=624, 1=26, 2=491.52, 3=312, 4=208, 5=104, 6=78, 7=52
+data.set 0x01306040 %long 0x00000001
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/clocks.cmm b/ap/build/scripts/trace32/zx297520v3/sys/clocks.cmm
new file mode 100755
index 0000000..8e99377
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/clocks.cmm
@@ -0,0 +1,238 @@
+;create clocks area
+local &pll_reg
+local &foutvco
+local &fout2
+local &fout3
+
+area.create clocks 200 300
+area.clear clocks
+
+area.select clocks
+area.view clocks
+
+if state.run()
+(
+ break
+)
+
+;disable mmu
+&cr=data.long(c15:0x1)
+&tmp=&cr&(~0x1)
+per.s c15:0x1 %LONG &tmp
+
+print "*********************PLL********************************************"
+&pll_reg=0x0013b008
+&fref=26000000.
+print "check mpll..."
+Gosub calc_pll
+
+&pll_reg=0x0013b010
+&fref=26000000.
+print "check upll..."
+Gosub calc_pll
+
+&pll_reg=0x0013B018
+&tmp=data.long(D:0x0013B018)
+&tmp=(&tmp>>25)&0x3
+if (&tmp==1)
+(
+&fref=30720000.
+)
+else
+(
+&fref=26000000.
+)
+print "check dpll..."
+Gosub calc_pll
+
+&pll_reg=0x0013b110
+&fref=26000000.
+print "check gpll..."
+Gosub calc_pll
+
+print "*********************M0 CLK********************************************"
+&tmp=data.long(D:0x0013b038)
+&tmp=&tmp&0x3
+if (&tmp==0)
+(
+ print "M0 clk sel main_clk"
+)
+if (&tmp==1)
+(
+ print "M0 clk sel 104M"
+)
+if (&tmp==2)
+(
+ print "M0 clk sel 78M"
+)
+if (&tmp==3)
+(
+ print "M0 clk sel 32K"
+)
+
+print "*********************A53 CLK********************************************"
+&tmp=data.long(D:0x01306040)
+&tmp=&tmp&0x3
+if (&tmp==0)
+(
+
+ print "ufi clk sel main_clk"
+)
+if (&tmp==1)
+(
+ print "ufi clk sel 624M"
+)
+if (&tmp==2)
+(
+ print "ufi clk sel 312M"
+)
+if (&tmp==3)
+(
+ print "ufi clk sel 156M"
+)
+
+print "*********************PS CLK********************************************"
+&tmp=data.long(D:0x01306020)
+&tmp=&tmp&0x3
+if (&tmp==0)
+(
+ print "pscpu clk sel main_clk"
+)
+if (&tmp==1)
+(
+ print "pscpu clk sel 624M"
+)
+if (&tmp==2)
+(
+ print "pscpu clk sel 312M"
+)
+if (&tmp==3)
+(
+ print "pscpu clk sel 156M"
+)
+
+print "*********************PHY CLK********************************************"
+&tmp=data.long(D:0x01306030)
+&tmp=&tmp&0x3
+if (&tmp==0)
+(
+ print "phycpu clk sel main_clk"
+)
+if (&tmp==1)
+(
+ print "phycpu clk sel 491M"
+)
+if (&tmp==2)
+(
+ print "phycpu clk sel 312M"
+)
+if (&tmp==3)
+(
+ print "phycpu clk sel 156M"
+)
+
+print "*********************AXI CLK********************************************"
+&tmp=data.long(D:0x01306000)
+&tmp=&tmp&0x7
+if (&tmp==0)
+(
+ print "axi clk sel main_clk"
+)
+if (&tmp==1)
+(
+ print "axi clk sel 156M"
+)
+if (&tmp==2)
+(
+ print "axi clk sel 124.8M"
+)
+if (&tmp==3)
+(
+ print "axi clk sel 104M"
+)
+if (&tmp==4)
+(
+ print "axi clk sel 78M"
+)
+if (&tmp==5)
+(
+ print "axi clk sel 52M"
+)
+if (&tmp==6)
+(
+ print "axi clk sel 39M"
+)
+if (&tmp==7)
+(
+ print "axi clk sel 6.5M"
+)
+
+print "*********************DDR CLK********************************************"
+&tmp=data.long(D:0x01306050)
+&tmp=&tmp&0x3
+if (&tmp==0)
+(
+ print "ddr io clk sel 312M"
+)
+if (&tmp==1)
+(
+ print "ddr io clk sel 400M"
+)
+if (&tmp==2)
+(
+ print "ddr io clk sel 208M"
+)
+if (&tmp==3)
+(
+ print "ddr io clk sel 156M"
+)
+;restore mmu config
+per.s c15:0x1 %LONG &cr
+ENDDO
+
+
+;*****************************************************************
+calc_pll:
+
+local &tmp1
+local &tmp2
+&tmp1=data.long(D:&pll_reg)
+&tmp2=data.long(D:&pll_reg+0x4)
+&power=(&tmp1>>0x1f)&0x1
+if (&power==1)
+(
+ print "pll is power down"
+)
+else
+(
+ print "pll is power up"
+)
+
+&lock=(&tmp1>>0x1e)&0x1
+if (&lock==1)
+(
+ print "pll is locked"
+)
+else
+(
+ print "pll is unlocked"
+)
+
+&refdiv=(&tmp1>>0x12)&((0x1<<0x6)-1)
+&fbdiv=(&tmp1>>0x6)&((0x1<<0xc)-1)
+&frac=(&tmp2)&((0x1<<0x18)-1)
+&foutvco=(&fref/&refdiv)*(&fbdiv+&frac)
+print "pll foutvco="+"&foutvco"
+
+&postdiv1=(&tmp1>>0x3)&((0x1<<0x3)-0x1)
+&postdiv2=(&tmp1)&((0x1<<0x3)-0x1)
+&foutpostdiv=&foutvco/&postdiv1/&postdiv2
+&fout2=&foutpostdiv/0x2
+&fout3=&foutpostdiv/0x3
+&fout4=&foutpostdiv/0x4
+print "pll foutpostdiv="+"&foutpostdiv"
+print "pll fout2="+"&fout2"
+print "pll fout3="+"&fout3"
+print "pll fout4="+"&fout4"
+
+RETURN
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/ddr_init.cmm b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init.cmm
new file mode 100755
index 0000000..7a24e37
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init.cmm
@@ -0,0 +1,175 @@
+data.set 0x01306100 %long 0x00cfe000 //ddr all reset enable bit6-12=0
+Wait 0.01s
+data.set 0x01306100 %long 0x00cff400 //release ddr apb(bit10) and phy reset(bit12)
+Wait 0.01s
+
+data.set 0x0121a004 %long 0xf0000001 //PIR //bypass pll lock, DDL cal and ZQ cal
+//check 0x0121a018 bit0=1
+Wait 0.01s
+
+//select ddr work mode here, then select ddr top clk
+data.set 0x0121a020 %long 0xa01b8000 //bypass
+//data.set 0x0121a020 %long 0x001b8000 //misson
+
+//DDR top clock select top clk 624M, bit0-2, 0=624, 1=26, 2=416, 3=312, 4=208, 5=200, 6=104
+//0: top clk=624M, ddr use bypss mode , dram io clk=312M
+//1: top clk=26M, ddr use bypss mode , dram io clk=13M
+//2: top clk=416M, ddr use bypss mode , dram io clk=208M
+//3: top clk=312M, ddr use bypss mode , dram io clk=156M
+//4: top clk=208M, ddr use bypss mode , dram io clk=104M, ddr use mission mode , dram io clk=416M
+//5: top clk=200M, ddr use bypss mode , dram io clk=100M, ddr use mission mode , dram io clk=400M
+//6: top clk=104M, ddr use bypss mode , dram io clk=52M
+data.set 0x01306050 %long 0x01511110
+
+//phy register init
+data.set 0x0121a00C %long 0x0380c7a0 //VALUE_PGCR1 / LBMODE:RW:31:1:=0x0 LBGDQS:RW:29:2:=0x0 LBDQSS:RW:28:1:=0x0 IOLB:RW:27:1:=0x0 INHVT:RW:26:1:=0x0 PHYHRST:RW:25:1:=0x1 ACBVT:RW:24:1:=0x1 ACDLVT:RW:23:1:=0x1 DLDLMT:RW:15:8:=0x1 FDEPTH:RW:13:2:=0x2 LPFDEPTH:RW:11:2:=0x0 LPFEN:RW:10:1:=0x1 MDLEN:RW:9:1:=0x1 IODDRM:RW:7:2:=0x3 WLSELT:RW:6:1:=0x0 DDLBYPMODE:RW:4:2:=0x2 WLUNCRT:RW:3:1:=0x0 WLSTEP:RW:2:1:=0x0 WLMODE:RW:1:1:=0x0 GPULSE:RW:0:1:=0x0
+data.set 0x0121a014 %long 0x90aa0060 //VALUE_PGCR3 / LPWAKEUP_THRSH:RW:28:4:=0x9 cfg_pub_mode:RW:26:1:=0x0 GDQSS:RW:25:1:=0x0 PRFBYP:RW:24:1:=0x0 CKEN:RW:16:8:=0xaa GATEDXRDCLK:RW:15:1:=0x1 GATEDXDDRCLK:RW:14:1:=0x1 GATEDXCTLCLK:RW:13:1:=0x1 DISACOE:RW:12:1:=0x0 GATEACRDCLK:RW:11:1:=0x1 GATEACDDRCLK:RW:10:1:=0x1 GATEACCTLCLK:RW:9:1:=0x1 RDDLY:RW:5:4:=0x3 RDMODE:RW:3:2:=0x0 DISRST:RW:2:1:=0x0 CLKLEVEL:RW:0:2:=0x0
+data.set 0x0121a024 %long 0x0d20684f //VALUE_PTR0 / tPLLPD:RW:21:11:=0x69 tPLLGS:RW:6:15:=0x1a1 tPHYRST:RW:0:6:=0xf
+data.set 0x0121a028 %long 0x0a2903a9 //VALUE_PTR1 / tPLLLOCK:RW:16:16:=0xa29 tPLLRST:RW:0:13:=0x3a9
+data.set 0x0121a030 %long 0x0200f362 //VALUE_PTR3 / tDINIT1:RW:20:9:=0x20 tDINIT0:RW:0:20:=0xf362
+data.set 0x0121a034 %long 0x04e00d64 //VALUE_PTR4 / tDINIT3:RW:18:11:=0x138 tDINIT2:RW:0:18:=0xd64
+data.set 0x0121a080 %long 0x00181224 //VALUE_DXCCR / UDQIOM:RW:21:1:=0x0 UDQPDR:RW:20:1:=0x1 UDQPDD:RW:19:1:=0x1 UDQODT:RW:18:1:=0x0 MSBUDQ:RW:15:3:=0x0 DXSR:RW:13:2:=0x0 DQSNRES:RW:9:4:=0x9 DQSRES:RW:5:4:=0x1 MDLEN:RW:2:1:=0x1 DXIOM:RW:1:1:=0x0 DXODT:RW:0:1:=0x0
+//dfi lowpower enable io powerdown and pll powerdown
+data.set 0x0121a084 %long 0x00046487 //VALUE_DSGCR / RSTOE:RW:21:1:=0x0 SDRMODE:RW:19:2:=0x0 RRMODE:RW:18:1:=0x1 ATOAE:RW:17:1:=0x0 DTOOE:RW:16:1:=0x0 DTOIOM:RW:15:1:=0x0 DTOPDR:RW:14:1:=0x1 DTOPDD:RW:13:1:=0x1 DTOODT:RW:12:1:=0x0 PUAD:RW:8:4:=0x4 DQSGX:RW:6:2:=0x2 CUAEN:RW:5:1:=0x0 LPPLLPD:RW:4:1:=0x1 LPIOPD:RW:3:1:=0x0 ZUEN:RW:2:1:=0x1 BDISEN:RW:1:1:=0x1 PUREN:RW:0:1:=0x1
+data.set 0x0121a088 %long 0x00000408 //VALUE_DCR / UDIMM:RW:29:1:=0x0 DDR2T:RW:28:1:=0x0 NOSRA:RW:27:1:=0x0 BYTEMASK:RW:10:8:=0x1 MPRDQ:RW:7:1:=0x0 PDQ:RW:4:3:=0x0 DDR8BNK:RW:3:1:=0x1 DDRMD:RW:0:3:=0x0
+data.set 0x0121a08C %long 0x150e0583 //VALUE_DTPR0 / tRCD:RW:26:5:=0x5 tRRD:RW:22:4:=0x4 tRAS:RW:16:6:=0xe tRP:RW:8:5:=0x5 tWTR:RW:4:4:=0x8 tRTP:RW:0:4:=0x3
+data.set 0x0121a090 %long 0x22814a10 //VALUE_DTPR1 / tAOND_AOFD:RW:30:2:=0x0 tWLO:RW:26:4:=0x8 tWLMRD:RW:20:6:=0x28 tRFC:RW:11:9:=0x29 tFAW:RW:5:6:=0x10 tMOD:RW:2:3:=0x4
+data.set 0x0121a094 %long 0x10000c2c //VALUE_DTPR2 / tCCD:RW:31:1:=0x0 tRTW:RW:30:1:=0x0 tRTODT:RW:29:1:=0x0 tDLLK:RW:19:10:=0x200 tXP:RW:10:5:=0x3 tXS:RW:0:10:=0x2c
+data.set 0x0121a098 %long 0x001464d1 //VALUE_DTPR3 / tAOFDx:RW:29:3:=0x0 tMRD:RW:18:5:=0x5 tCKE:RW:13:5:=0x3 tRC:RW:6:7:=0x13 tDQSCKmax:RW:3:3:=0x2 tDQSCK:RW:0:3:=0x1
+data.set 0x0121a0A4 %long 0x00000003 //VALUE_MR2 / WRLEVELING:RW:7:1:=0x0 WLSELECT:RW:6:1:=0x0 nWRE:RW:4:1:=0x0 rl_wl:RW:0:4:=0x6
+data.set 0x0121a0A0 %long 0x00000063 //VALUE_MR1 / nWR:W:5:3:=0x3 WC:W:4:1:=0x0 BT:W:3:1:=0x0 BL:W:0:3:=0x3
+data.set 0x0121a0A8 %long 0x00000002 //VALUE_MR3 / DS:RW:0:4:=0x2
+data.set 0x0121a1A0 %long 0x00000000 //VALUE_MR11 / PDCTL:RW:2:1:=0x0 DQODT:RW:0:2:=0x0
+data.set 0x0121a240 %long 0x04058900 //VALUE_ZQCR / FORCE_ZCAL_VT_UPDATE:RW:27:1:=0x0 DIS_NON_LIN_COMP:RW:26:1:=0x1 PU_ODT_ONLY:RW:25:1:=0x0 ASYM_DRV_EN:RW:24:1:=0x0 IODLMT:RW:17:7:=0x2 AVGEN:RW:16:1:=0x1 AVGMAX:RW:14:2:=0x2 ZCAL:RW:11:3:=0x1 PGWAIT:RW:8:3:=0x1 ZQPD:RW:2:1:=0x0 TERM_OFF:RW:1:1:=0x0 ZCALBYP:RW:0:1:=0x0
+//bit0-3 output:lpddr2(5=80ohm£¬7=60ohm£¬9=48ohm£¬b=40ohm£¬d=34.3ohm),lpddr3(1=240ohm£¬3=120ohm£¬9=48ohm£¬b=40ohm£¬d=34.3ohm)
+data.set 0x0121a244 %long 0x0007bb2b //VALUE_ZQnPR / ZPROG_PU_ODT_ONLY:RW:16:4:=0x7 ZPROG_ASYM_DRV_PD:RW:12:4:=0xb ZPROG_ASYM_DRV_PU:RW:8:4:=0xb ZQDIV_ODT:RW:4:4:=0x7 ZQDIV_DS:RW:0:4:=0xb
+data.set 0x0121a254 %long 0x0007bb2b //VALUE_ZQnPR / ZPROG_PU_ODT_ONLY:RW:16:4:=0x7 ZPROG_ASYM_DRV_PD:RW:12:4:=0xb ZPROG_ASYM_DRV_PU:RW:8:4:=0xb ZQDIV_ODT:RW:4:4:=0x7 ZQDIV_DS:RW:0:4:=0xb
+data.set 0x0121a238 %long 0x00480048 //VALUE_IOVCR0 / EDXVREF:RW:24:7:=0x0 IDXVREF:RW:16:7:=0x48 EACVREF:RW:8:7:=0x0 IACVREF:RW:0:7:=0x48
+data.set 0x0121a23C %long 0x00000048 //VALUE_IOVCR1 / ZQVREF:RW:0:7:=0x48
+
+//controller register init
+data.set 0x01216000 %long 0x03040004 //VALUE_MSTR / device_config:RW:30:2:=0x0 frequency_mode:RW:29:1:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 lpddr4:RW:5:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0
+data.set 0x01216010 %long 0x00000030 //VALUE_MRCTRL0 / mr_wr:RW:31:1:=0x0 mr_addr:RW:12:4:=0x0 mr_rank:RW:4:4:=0x3 sw_init_int:RW:3:1:=0x0 pda_en:RW:2:1:=0x0 mpr_en:RW:1:1:=0x0 mr_type:RW:0:1:=0x0
+data.set 0x01216030 %long 0x00000000 //VALUE_PWRCTL / stay_in_selfref:RW:6:1:=0x0 selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+data.set 0x01216034 %long 0x00052002 //VALUE_PWRTMG / selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2
+data.set 0x01216038 %long 0x00040003 //VALUE_HWLPCTL / hw_lp_idle_x32:RW:16:12:=0x4 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1
+data.set 0x01216050 %long 0x00210000 //VALUE_RFSHCTL0 / refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0
+data.set 0x01216064 %long 0x00260014 //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x26 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0x14
+data.set 0x012160d0 %long 0x001f0001 //VALUE_INIT0 / skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x1f pre_cke_x1024:RW:0:11:=0x1
+data.set 0x012160d4 %long 0x00000000 //VALUE_INIT1 / dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0
+data.set 0x012160d8 %long 0x00000405 //VALUE_INIT2 / idle_after_reset_x32:RW:8:8:=0x4 min_stable_clock_x1:RW:0:4:=0x5
+data.set 0x012160dc %long 0x00630006 //VALUE_INIT3 / mr:RW:16:16:=0x63 emr:RW:0:16:=0x6
+//dram DS:[19:16] 1:34ohm, 2:40ohm, 3:48ohm
+data.set 0x012160e0 %long 0x00020000 //VALUE_INIT4 / emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0
+data.set 0x012160e4 %long 0x00050002 //VALUE_INIT5 / dev_zqinit_x32:RW:16:8:=0x5 max_auto_init_x1024:RW:0:10:=0x2
+data.set 0x012160f4 %long 0x0000066f //VALUE_RANKCTL / diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf
+data.set 0x01216100 %long 0x06080a07 //VALUE_DRAMTMG0 / wr2pre:RW:24:6:=0x6 t_faw:RW:16:6:=0x8 t_ras_max:RW:8:7:=0xa t_ras_min:RW:0:6:=0x7
+data.set 0x01216104 %long 0x00020209 //VALUE_DRAMTMG1 / t_xp:RW:16:5:=0x2 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0x9
+data.set 0x01216108 %long 0x02040606 //VALUE_DRAMTMG2 / write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:6:=0x6 wr2rd:RW:0:6:=0x6
+data.set 0x0121610c %long 0x00501000 //VALUE_DRAMTMG3 / t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0
+data.set 0x01216110 %long 0x03010204 //VALUE_DRAMTMG4 / t_rcd:RW:24:5:=0x3 t_ccd:RW:16:4:=0x1 t_rrd:RW:8:4:=0x2 t_rp:RW:0:5:=0x4
+data.set 0x01216114 %long 0x01010303 //VALUE_DRAMTMG5 / t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x3 t_cke:RW:0:4:=0x3
+data.set 0x01216118 %long 0x02020003 //VALUE_DRAMTMG6 / t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x3
+data.set 0x0121611c %long 0x00000202 //VALUE_DRAMTMG7 / t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2
+data.set 0x01216138 %long 0x00000016 //VALUE_DRAMTMG14 / t_xsr:RW:0:12:=0x16
+data.set 0x01216180 %long 0x4039000f //VALUE_ZQCTL0 / dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x1 zq_resistor_shared:RW:29:1:=0x0 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x39 t_zq_short_nop:RW:0:10:=0xf
+data.set 0x01216184 %long 0x00800100 //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0x8 t_zq_short_interval_x1024:RW:0:20:=0x100
+data.set 0x01216188 %long 0x00000000 //VALUE_ZQCTL2 / zq_reset:RW:0:1:=0x0
+data.set 0x01216190 %long 0x07030101 //VALUE_DFITMG0 / dfi_t_ctrl_delay:RW:24:5:=0x7 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x3 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x1 dfi_tphy_wrlat:RW:0:6:=0x1
+data.set 0x01216194 %long 0x00030404 //VALUE_DFITMG1 / dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x3 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4
+data.set 0x01216198 %long 0x07000101 //VALUE_DFILPCFG0 / dfi_tlp_resp:RW:24:4:=0x7 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x0 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x0 dfi_lp_en_pd:RW:0:1:=0x1
+data.set 0x012161a0 %long 0x80400003 //VALUE_DFIUPD0 / dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3
+data.set 0x012161a4 %long 0x00000000 //VALUE_DFIUPD1 / dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0
+data.set 0x012161a8 %long 0x80100010 //VALUE_DFIUPD2 / dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10
+data.set 0x012161ac %long 0x00100010 //VALUE_DFIUPD3 / dfi_phyupd_type3:RW:16:12:=0x10 dfi_phyupd_type2:RW:0:12:=0x10
+data.set 0x012161b0 %long 0x00000000 //VALUE_DFIMISC / dfi_data_cs_polarity:RW:2:1:=0x0 phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+data.set 0x01216200 %long 0x0000001f //VALUE_ADDRMAP0 / addrmap_dch_bit0:RW:16:5:=0x0 addrmap_cs_bit1:RW:8:5:=0x0 addrmap_cs_bit0:RW:0:5:=0x1f
+data.set 0x01216204 %long 0x00070707 //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+data.set 0x01216208 %long 0x00000000 //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+data.set 0x0121620c %long 0x0f000000 //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+data.set 0x01216210 %long 0x00000f0f //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+data.set 0x01216214 %long 0x06060606 //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+data.set 0x01216218 %long 0x0f0f0f06 //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
+data.set 0x01216240 %long 0x04000400 //VALUE_ODTCFG / wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0
+data.set 0x01216244 %long 0x00000000 //VALUE_ODTMAP / rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0
+data.set 0x01216250 %long 0x00001005 //VALUE_SCHED / rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x10 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1
+data.set 0x01216254 %long 0x00000000 //VALUE_SCHED1 / pageclose_timer:RW:0:8:=0x0
+
+ //ddr_prority_config
+ //port read static priority bit0-9, bit0-4 timeout, bit5-9 prority
+ data.set 0x01216404 %long 0x000013ff //VALUE_PCFGR_0 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff
+ data.set 0x012164b4 %long 0x000010ff //VALUE_PCFGR_1 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20
+ data.set 0x01216564 %long 0x0000103f //VALUE_PCFGR_2 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0
+ data.set 0x01216614 %long 0x0000105f //VALUE_PCFGR_3 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4
+ //port write static priority bit0-9
+ data.set 0x01216408 %long 0x000013ff //VALUE_PCFGW_0 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff
+ data.set 0x012164b8 %long 0x000010ff //VALUE_PCFGW_1 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff
+ data.set 0x01216568 %long 0x0000103f //VALUE_PCFGW_2 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f
+ data.set 0x01216618 %long 0x0000105f //VALUE_PCFGW_3 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f
+ //port read region set
+ //data.set 0x01216494 %long 0x02000e00 //VALUE_PCFGQOS0_0 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0
+ //data.set 0x01216544 %long 0x02000e00 //VALUE_PCFGQOS0_1 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0
+ //data.set 0x012165f4 %long 0x02000e00 //VALUE_PCFGQOS0_2 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0
+ //data.set 0x012166a4 %long 0x02000e00 //VALUE_PCFGQOS0_3 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0
+ //port write region set
+ //data.set 0x0121649c %long 0x00000000 //VALUE_PCFGWQOS0_0 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+ //data.set 0x0121654c %long 0x00000000 //VALUE_PCFGWQOS0_1 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+ //data.set 0x012165fc %long 0x00000000 //VALUE_PCFGWQOS0_2 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+ //data.set 0x012166ac %long 0x00000000 //VALUE_PCFGWQOS0_3 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+ //vpr timeout, region2 is red queue
+ //data.set 0x01216498 %long 0x00000000 //VALUE_PCFGQOS1_0 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+ //data.set 0x01216548 %long 0x00000000 //VALUE_PCFGQOS1_1 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+ //data.set 0x012165f8 %long 0x00000000 //VALUE_PCFGQOS1_2 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+ //data.set 0x012166a8 %long 0x00000000 //VALUE_PCFGQOS1_3 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+ //vpw timeout
+ //data.set 0x012164a0 %long 0x00000000 //VALUE_PCFGWQOS1_0 / wqos_map_timeout:RW:0:11:=0x0
+ //data.set 0x01216550 %long 0x00000000 //VALUE_PCFGWQOS1_1 / wqos_map_timeout:RW:0:11:=0x0
+ //data.set 0x01216600 %long 0x00000000 //VALUE_PCFGWQOS1_2 / wqos_map_timeout:RW:0:11:=0x0
+ //data.set 0x012166b0 %long 0x00000000 //VALUE_PCFGWQOS1_3 / wqos_map_timeout:RW:0:11:=0x0
+ //in CAM set
+ //data,set 0x0121625c %long 0x0f000001 //VALUE_PERFHPR1 / hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1
+ //data,set 0x01216264 %long 0x0f00007f //VALUE_PERFLPR1 / lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f
+ //data,set 0x0121626c %long 0x0f00007f //VALUE_PERFWR1 / w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f
+ //data,set 0x01216274 %long 0x00000000 //VALUE_PERFVPR1 / vpr_timeout_range:RW:0:11:=0x0
+ //data,set 0x01216278 %long 0x00000000 //VALUE_PERFVPW1 / vpw_timeout_range:RW:0:11:=0x0
+ //port extern static priority
+ //REG32(0x00146064) = 0x00000000; //port0,1 level=0=LP; port2,3 level=0=LP
+
+//wait all register config into hardware
+Wait 0.01s
+
+data.set 0x01306100 %long 0x00cfffc0 //release ddr ctl(bit11) and axi_sn reset(bit6-9)
+Wait 0.01s
+
+//sw config done
+data.set 0x01216320 %long 0x00000000 //SWCTL // sw_done:RW:0:1:=0x0
+//check phy auto init done, wait 0x01216324 bit0 =0
+Wait 0.01s
+
+data.set 0x0121a004 %long 0x00040001 //PIR //notify phy that sdram will be initialized by controller
+//check 0x0121a018 bit0=1 and bit4=1
+Wait 0.01s
+
+//manual trigger calibrate
+data.set 0x0121a004 %long 0x00000023 //PIR //DDL cal, ZQ cal (for bypass)
+//data.set 0x0121a004 %long 0x00000033 //PIR //DDL cal, ZQ cal, PLL init (for mission)
+//check 0x0121a018 bit0-3=1011
+Wait 0.01s
+
+//enable controller dfi_init_complete_en to start sdram init, then will send dram init cmd
+data.set 0x012161b0 %long 0x00000001 //DFIMISC // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x1
+//check controller status is sdram init done,wait 0x01216004 bit0-2 !=0
+Wait 0.01s
+
+//training
+//bit0-1 auto enter powerdown and selfrefresh, training must close this function
+//data.set 0x01216030 %long 0x00000000 //PWRCTL // selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+//data.set 0x0121a0b0 %long 0x81001097 //DTCR //only select rank0 do training 0x91001087 bit13ÊÇ·ñ´ò¿ª£¿
+//data.set 0x0121a004 %long 0xf001
+//check 0x0121a018 bit0=1 and bit8-11=1111
+Wait 0.01s
+
+data.set 0x01216490 %long 0x00000001 //VALUE_PCTRL_0 / port_en:RW:0:1:=0x1
+data.set 0x01216540 %long 0x00000001 //VALUE_PCTRL_1 / port_en:RW:0:1:=0x1
+data.set 0x012165f0 %long 0x00000001 //VALUE_PCTRL_2 / port_en:RW:0:1:=0x1
+data.set 0x012166a0 %long 0x00000001 //VALUE_PCTRL_3 / port_en:RW:0:1:=0x1
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_156m.cmm b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_156m.cmm
new file mode 100755
index 0000000..843c4a7
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_156m.cmm
@@ -0,0 +1,210 @@
+// ********************************************************************
+//* ZX297521 Project uMCTL2 DDR controller parameter configuration
+//* uMCTL2 Rev.: 2.50a
+//* Author: Chen Jianhong
+//* Department: IP design
+//* Option: Memory Type = LPDDR2
+//* Option: Memory Frequency(MHz) = 156
+//* Option: Memory Space(Gb) = 1
+//* Option: DRAM drive impedance(Ohm) = 40
+// ********************************************************************
+
+//-------------------below is ddr setting--------------------------
+
+//data.set 0x01306100 %long 0xffffe000 //ddr all reset enable bit6-12=0
+data.set 0x01306100 %long 0x0affe000 //ddr all reset enable bit6-12=0
+Wait 0.01s
+data.set 0x01306100 %long 0x0affe400 //release ddr apb(bit10)
+Wait 0.01s
+
+//DDR top clock select top clk 156M, bit0-1, 0=156, 1=200, 2=104, 3=78
+//0: top clk=156M, ddr use mission mode , dram io clk=312M
+//1: top clk=200M, ddr use mission mode , dram io clk=400M
+//2: top clk=104M, ddr use mission mode , dram io clk=208M
+//3: top clk=78M, ddr use mission mode , dram io clk=156M
+data.set 0x01306050 %long 0x00000003 //·ÖƵÉèÖ㬶ÔÓ¦ÐèÒªÐÞ¸ÄÂð
+
+//phy register init
+data.set 0x00154004 %long 0x00000007 //VALUE_PHYREG01 / Reserved:RW:2:6:=0x1, PHY_MODE:RW:0:2:=0x2(LPDDR2:0x3,LPDDR3:0x2)
+data.set 0x0015402c %long 0x00000080 //VALUE_PHYREG0B / RL:RW:4:4:=0x8
+data.set 0x00154030 %long 0x00000004 //VALUE_PHYREG0C / WL:RW:0:4:=0x4
+
+data.set 0x001543b0 %long 0x00000020 //VALUE_PHYREGEC / fbdiv[7:0]=0x20
+data.set 0x001543b4 %long 0x0000001a //VALUE_PHYREGED / PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pllpd:RW:1:1:=0x1, fbdiv[8]:RW:0:1:=0x0
+data.set 0x001543b8 %long 0x00000042 //VALUE_PHYREGEE / prediv[4:0]:RW:0:5:=0x2,postdiv[2:0]:RW:5:3:=0x2
+
+//Internal VREF generation(defualt)
+data.set 0x0015428c %long 0x00000030 //VALUE_PHYREGA3 / Channel A/B hith 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+data.set 0x001542b8 %long 0x00000030 //VALUE_PHYREGAE / Channel A/B low 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+
+//Drive strength(defualt)
+data.set 0x00154044 %long 0x0000000a //VALUE_PHYREG11 / CMD drive strength: cmd_nrcomp[4:0]:RW:0:5:=0xa
+data.set 0x00154058 %long 0x0000000a //VALUE_PHYREG16 / CK drive strength: ck_nrcomp [4:0]:RW:0:5:=0xa
+data.set 0x00154064 %long 0x0000000a //VALUE_PHYREG19 / CK pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154068 %long 0x0000000a //VALUE_PHYREG1A / CMD pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154080 %long 0x0000000a //VALUE_PHYREG20 / A_DQ0~A_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154084 %long 0x0000000a //VALUE_PHYREG21 / A_DQ0~A_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x001540b8 %long 0x0000008a //VALUE_PHYREG2E / A_DQ0~A_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540bc %long 0x0000008a //VALUE_PHYREG2F / A_DQ0~A_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540c0 %long 0x0000008a //VALUE_PHYREG30 / A_DQ8~A_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540c4 %long 0x0000008a //VALUE_PHYREG31 / A_DQ8~A_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540f8 %long 0x0000000a //VALUE_PHYREG3E / A_DQ8~A_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x001540fc %long 0x0000000a //VALUE_PHYREG3F / A_DQ8~A_DQ15 pull_up ODT:RW:0:5:=0xa
+
+data.set 0x00154100 %long 0x0000000a //VALUE_PHYREG40 / B_DQ0~B_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154104 %long 0x0000000a //VALUE_PHYREG41 / B_DQ0~B_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x00154138 %long 0x0000008a //VALUE_PHYREG4E / B_DQ0~B_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x0015413c %long 0x0000008a //VALUE_PHYREG4F / B_DQ0~B_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+
+data.set 0x00154140 %long 0x0000008a //VALUE_PHYREG50 / B_DQ8~B_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x00154144 %long 0x0000008a //VALUE_PHYREG51 / B_DQ8~B_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x00154178 %long 0x0000000a //VALUE_PHYREG5E / B_DQ8~B_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x0015417c %long 0x0000002a //VALUE_PHYREG5F / B_DQ8~B_DQ15 pull_up ODT:RW:0:5:=0xa
+
+//controller register init
+data.set 0x00150000 %long 0x01040004 //VALUE_MSTR / device_config:RW:30:2:=0x0 frequency_mode:RW:29:1:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 lpddr4:RW:5:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0
+data.set 0x00150010 %long 0x00000030 //VALUE_MRCTRL0 / mr_wr:RW:31:1:=0x0 mr_addr:RW:12:4:=0x0 mr_rank:RW:4:4:=0x3 sw_init_int:RW:3:1:=0x0 pda_en:RW:2:1:=0x0 mpr_en:RW:1:1:=0x0 mr_type:RW:0:1:=0x0
+data.set 0x00150014 %long 0x00000000 //VALUE_MRCTRL1 /mr_data:RW:0:16:=0x0
+data.set 0x00150020 %long 0x00000000 //VALUE_DERATEEN /rc_derate_value:RW:8:2:=0x0 derate_byte:RW:4:4:=0x0 derate_value:RW:1:1:=0x0 derate_enable:RW:0:1:=0x0
+data.set 0x00150024 %long 0x00800000 //VALUE_DERATEINT /mr4_read_interval:RW:0:32:=0x800000
+
+data.set 0x00150030 %long 0x00000000 //VALUE_PWRCTL / stay_in_selfref:RW:6:1:=0x0 selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+data.set 0x00150034 %long 0x00052002 //VALUE_PWRTMG / selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2
+data.set 0x00150038 %long 0x00040003 //VALUE_HWLPCTL / hw_lp_idle_x32:RW:16:12:=0x4 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1
+data.set 0x00150050 %long 0x00210000 //VALUE_RFSHCTL0 / refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0
+data.set 0x00150054 %long 0x00000000 //VALUE_RFSHCTL1 / refresh_timer1_start_value_x32:RW:16:12:=0x0 refresh_timer0_start_value_x32:RW:0:12:=0x0
+data.set 0x00150058 %long 0x00000000 //VALUE_RFSHCTL2 / refresh_timer3_start_value_x32:RW:16:12:=0x0 refresh_timer2_start_value_x32:RW:0:12:=0x0
+data.set 0x00150060 %long 0x00000000 //VALUE_RFSHCTL3 / refresh_mode:RW:4:3:=0x0 refresh_update_level:RW:1:1:=0x0 dis_auto_refresh:RW:0:1:=0x0
+data.set 0x00150064 %long 0x0013000a //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x13 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0xa
+data.set 0x001500d0 %long 0x00100001 //VALUE_INIT0 / skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x10 pre_cke_x1024:RW:0:11:=0x1
+data.set 0x001500d4 %long 0x00000000 //VALUE_INIT1 / dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0
+data.set 0x001500d8 %long 0x00000205 //VALUE_INIT2 / idle_after_reset_x32:RW:8:8:=0x2 min_stable_clock_x1:RW:0:4:=0x5
+//MR2=RL/WL£¬1£ºRL3/WL1£¬2£ºRL4/WL2£¬3£ºRL:5/WL2£¬4£ºRL6/WL3:£¬5£ºRL7/WL4£¬6£ºRL8/WL4
+data.set 0x001500dc %long 0x00230006 //VALUE_INIT3 / mr:RW:16:16:=0x23 emr:RW:0:16:=0x6
+//bit16-31£¬LPDDR2 MR3 value£¬Æ÷¼þDSĬÈÏÊÇ40ohm£¬£¨1=34.3£¬2=40,3=48,4=60,6=80£©
+data.set 0x001500e0 %long 0x00020000 //VALUE_INIT4 / emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0
+data.set 0x001500e4 %long 0x00030001 //VALUE_INIT5 / dev_zqinit_x32:RW:16:8:=0x3 max_auto_init_x1024:RW:0:10:=0x2
+data.set 0x001500f4 %long 0x0000066f //VALUE_RANKCTL / diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf
+data.set 0x00150100 %long 0x05040503 //VALUE_DRAMTMG0 / wr2pre:RW:24:6:=0x5 t_faw:RW:16:6:=0x4 t_ras_max:RW:8:7:=0x5 t_ras_min:RW:0:6:=0x3
+data.set 0x00150104 %long 0x00010205 //VALUE_DRAMTMG1 / t_xp:RW:16:5:=0x1 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0x5
+//RL=bit16-21£¬1£ºRL=2£¬2£ºRL=4£¬3£ºRL=6£¬4£ºR=8£¬WL=bit24-29£¬1£ºWL=2£¬2£ºWL=4
+//ÕâÀïµ¼ÖÂMR2µÄÅäÖã¨0x012160dc£©²»ÄÜÑ¡Ôñº¬ÓÐÆæÊýµÄÖµ?
+data.set 0x00150108 %long 0x02040506 //VALUE_DRAMTMG2 / write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:6:=0x5 wr2rd:RW:0:6:=0x5
+data.set 0x0015010c %long 0x00501000 //VALUE_DRAMTMG3 / t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0
+data.set 0x00150110 %long 0x02010103 //VALUE_DRAMTMG4 / t_rcd:RW:24:5:=0x2 t_ccd:RW:16:4:=0x1 t_rrd:RW:8:4:=0x1 t_rp:RW:0:5:=0x3
+data.set 0x00150114 %long 0x01010202 //VALUE_DRAMTMG5 / t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x2 t_cke:RW:0:4:=0x2
+data.set 0x00150118 %long 0x02020002 //VALUE_DRAMTMG6 / t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x2
+data.set 0x0015011c %long 0x00000202 //VALUE_DRAMTMG7 / t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2
+data.set 0x00150138 %long 0x0000000b //VALUE_DRAMTMG14 / t_xsr:RW:0:12:=0xb
+//bit30=1 Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit £¬7520×ʼÅäÖÃΪ0£¬µ¼ÖÂ×Ô¶¯×Ôˢй¦ÄÜÍ˳öʱÑÓʱºÜ´ó£¬sdio¶ÁÊý¾Ý³ö´í
+data.set 0x00150180 %long 0x401d0008 //VALUE_ZQCTL0 / dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x1 zq_resistor_shared:RW:29:1:=0x0 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x1d t_zq_short_nop:RW:0:10:=0x8
+data.set 0x00150184 %long 0x00400100 //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0x4 t_zq_short_interval_x1024:RW:0:20:=0x100
+data.set 0x00150188 %long 0x00000000 //VALUE_ZQCTL2 / zq_reset:RW:0:1:=0x0
+//dfi_t_rddata_en=3,֮ǰ7520ÉÏÉè³É2»áµ¼Ö¶Ámr¶Á´í
+data.set 0x00150190 %long 0x04030001 //VALUE_DFITMG0 / dfi_t_ctrl_delay:RW:24:5:=0x4 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x3 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x0 dfi_tphy_wrlat:RW:0:6:=0x1
+data.set 0x00150194 %long 0x00020404 //VALUE_DFITMG1 / dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x2 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4
+data.set 0x00150198 %long 0x09001111 //VALUE_DFILPCFG0 / dfi_tlp_resp:RW:24:4:=0x9 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x1 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x1 dfi_lp_en_pd:RW:0:1:=0x1
+data.set 0x001501a0 %long 0x80400003 //VALUE_DFIUPD0 / dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3
+data.set 0x001501a4 %long 0x00000000 //VALUE_DFIUPD1 / dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0
+data.set 0x001501a8 %long 0x80100010 //VALUE_DFIUPD2 / dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10
+data.set 0x001501b0 %long 0x00000000 //VALUE_DFIMISC / dfi_data_cs_polarity:RW:2:1:=0x0 phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+data.set 0x00150200 %long 0x0000001f //VALUE_ADDRMAP0 / addrmap_dch_bit0:RW:16:5:=0x0 addrmap_cs_bit1:RW:8:5:=0x0 addrmap_cs_bit0:RW:0:5:=0x1f
+data.set 0x00150204 %long 0x00070707 //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+data.set 0x00150208 %long 0x00000000 //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+data.set 0x0015020c %long 0x0f000000 //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+data.set 0x00150210 %long 0x00000f0f //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+data.set 0x00150214 %long 0x06060606 //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+data.set 0x00150218 %long 0x0f0f0f06 //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
+data.set 0x00150240 %long 0x04000400 //VALUE_ODTCFG / wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0
+data.set 0x00150244 %long 0x00000000 //VALUE_ODTMAP / rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0
+data.set 0x00150250 %long 0x00001805 //VALUE_SCHED / rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x18 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1
+data.set 0x00150254 %long 0x00000000 //VALUE_SCHED1 / pageclose_timer:RW:0:8:=0x0
+
+data.set 0x00150300 %long 0x00000000 //VALUE_DBG0 / dis_collision_page_opt:RW:4:1:=0x0 dis_act_bypass:RW:2:1:=0x0 dis_rd_bypass:RW:1:1:=0x0 dis_wc:RW:0:1:=0x0
+data.set 0x00150304 %long 0x00000000 //VALUE_DBG1 / dis_dq:RW:1:1:=0x0 dis_hig:RW:0:1:=0x0
+data.set 0x0015030c %long 0x00000000 //VALUE_DBGCMD / ctrlupd:RWSC:5:1:=0x0 zq_calib_short:RWSC:4:1:=0x0 rank3_refresh:RWSC:3:1:=0x0 rank2_refresh:RWSC:2:1:=0x0 rank1_refresh:RWSC:1:1:=0x0 rank0_refresh:RWSC:0:1:=0x0
+
+data.set 0x00150400 %long 0x00000000 //VALUE_PCCFG / bl_exp_mode:RW:8:1:=0x0 pagematch_limit:RW:1:1:=0x0 go2critical_en:RW:0:1:=0x0
+
+//ddr_prority_config
+//port read static priority bit0-9, bit0-4 timeout, bit5-9 prority
+data.set 0x00150404 %long 0x000013ff //VALUE_PCFGR_0 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b4 %long 0x00001020 //VALUE_PCFGR_1 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20
+data.set 0x00150564 %long 0x00001000 //VALUE_PCFGR_2 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0
+data.set 0x00150614 %long 0x00001004 //VALUE_PCFGR_3 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4
+//port write static priority bit0-9
+data.set 0x00150408 %long 0x000013ff //VALUE_PCFGW_0 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b8 %long 0x000010ff //VALUE_PCFGW_1 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff
+data.set 0x00150568 %long 0x0000103f //VALUE_PCFGW_2 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f
+data.set 0x00150618 %long 0x0000105f //VALUE_PCFGW_3 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f
+//port read region set
+data.set 0x00150494 %long 0x0020000e //VALUE_PCFGQOS0_0 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x00150544 %long 0x0020000e //VALUE_PCFGQOS0_1 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001505f4 %long 0x0020000e //VALUE_PCFGQOS0_2 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001506a4 %long 0x0020000e //VALUE_PCFGQOS0_3 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+//port write region set
+data.set 0x0015049c %long 0x00000000 //VALUE_PCFGWQOS0_0 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x0015054c %long 0x00000000 //VALUE_PCFGWQOS0_1 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001505fc %long 0x00000000 //VALUE_PCFGWQOS0_2 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001506ac %long 0x00000000 //VALUE_PCFGWQOS0_3 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+//vpr timeout, region2 is red queue
+data.set 0x00150498 %long 0x00000000 //VALUE_PCFGQOS1_0 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x00150548 %long 0x00000000 //VALUE_PCFGQOS1_1 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001505f8 %long 0x00000000 //VALUE_PCFGQOS1_2 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001506a8 %long 0x00000000 //VALUE_PCFGQOS1_3 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+//vpw timeout
+data.set 0x001504a0 %long 0x00000000 //VALUE_PCFGWQOS1_0 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150550 %long 0x00000000 //VALUE_PCFGWQOS1_1 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150600 %long 0x00000000 //VALUE_PCFGWQOS1_2 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x001506b0 %long 0x00000000 //VALUE_PCFGWQOS1_3 / wqos_map_timeout:RW:0:11:=0x0
+//in CAM set
+data.set 0x0015025c %long 0x0f000001 //VALUE_PERFHPR1 / hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1
+data.set 0x00150264 %long 0x0f00007f //VALUE_PERFLPR1 / lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f
+data.set 0x0015026c %long 0x0f00007f //VALUE_PERFWR1 / w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f
+data.set 0x00150274 %long 0x00000000 //VALUE_PERFVPR1 / vpr_timeout_range:RW:0:11:=0x0
+data.set 0x00150278 %long 0x00000000 //VALUE_PERFVPW1 / vpw_timeout_range:RW:0:11:=0x0
+//port extern static priority
+//data.set 0x0013d034 %long 0xf0f00000 //port0,1 rqos=0(LPR); port2,3 rqos=F(HPR)
+//wait all register configer done in hardware
+Wait 0.01s
+
+//***********************************************************
+//ctroller and inno phy registers configer done
+//***********************************************************
+data.set 0x01306100 %long 0x0affffc0 //release ddr ctl(bit11) and axi_sn reset(bit6-9) and phy reset(bit12) //ÉèÖÃϵͳ¼Ä´æÆ÷Öµ
+Wait 0.01s
+
+//sw config done
+data.set 0x00150320 %long 0x00000000 //SWCTL // sw_done:RW:0:1:=0x0
+//check phy auto init done, wait 0x00150324 bit0 =0
+Wait 0.01s
+
+//power on PHY PLL
+data.set 0x001543b4 %long 0x00000018 //PHYREGED,PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pll_pd_en:RW:1:1:=0x0, fbdiv[8]:RW:0:1:=0x0
+//wait PHY PLL lock,PHYREGF8[0]Pll lock indicate signal
+
+Wait 0.01s
+
+//PHY DLL init start, fall edge trigger
+data.set 0x0015417c %long 0x0000000a //PHYREG5F, PHY init start:5:1:=0x1
+//wait dll lock, phy init done, PHYREGF8[1]Phy init complete signal
+Wait 0.01s
+
+//enable controller dfi_init_complete_en to start sdram init, then will send dram init cmd
+data.set 0x001501b0 %long 0x00000001 //DFIMISC // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x1 ÊÇ·ñÈ¥µô£¬»òÕ߶ÔÓ¦ÐÞ¸Ä
+//check controller status is sdram init done,wait 0x00150004 bit0-2 !=0
+Wait 0.01s
+data.set 0x001501b0 %long 0x00000000 //dfimisc[0] phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+
+//phy DQS gate training start
+data.set 0x00154008 %long 0x00000001 //PHYREG02,bit0:DQS gating calibration control=1, bit1:DQS gating bypass mode select=0
+//wait training done
+Wait 0.1s
+//phy DQS gate training stop
+data.set 0x00154008 %long 0x00000000 //PHYREG02,bit0:DQS gating calibration control=0, bit1:DQS gating bypass mode select=0
+
+//enable port_n
+data.set 0x00150490 %long 0x00000001 //VALUE_PCTRL_0 / port_en:RW:0:1:=0x1
+data.set 0x00150540 %long 0x00000001 //VALUE_PCTRL_1 / port_en:RW:0:1:=0x1
+data.set 0x001505f0 %long 0x00000001 //VALUE_PCTRL_2 / port_en:RW:0:1:=0x1
+data.set 0x001506a0 %long 0x00000001 //VALUE_PCTRL_3 / port_en:RW:0:1:=0x1
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_208m.cmm b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_208m.cmm
new file mode 100755
index 0000000..02bb5e8
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_208m.cmm
@@ -0,0 +1,210 @@
+// ********************************************************************
+//* ZX297521 Project uMCTL2 DDR controller parameter configuration
+//* uMCTL2 Rev.: 2.50a
+//* Author: Chen Jianhong
+//* Department: IP design
+//* Option: Memory Type = LPDDR2
+//* Option: Memory Frequency(MHz) = 208
+//* Option: Memory Space(Gb) = 1
+//* Option: DRAM drive impedance(Ohm) = 40
+// ********************************************************************
+
+//-------------------below is ddr setting--------------------------
+
+//data.set 0x01306100 %long 0xffffe000 //ddr all reset enable bit6-12=0
+data.set 0x01306100 %long 0x0affe000 //ddr all reset enable bit6-12=0
+Wait 0.01s
+data.set 0x01306100 %long 0x0affe400 //release ddr apb(bit10)
+Wait 0.01s
+
+//DDR top clock select top clk 156M, bit0-1, 0=156, 1=200, 2=104, 3=78
+//0: top clk=156M, ddr use mission mode , dram io clk=312M
+//1: top clk=200M, ddr use mission mode , dram io clk=400M
+//2: top clk=104M, ddr use mission mode , dram io clk=208M
+//3: top clk=78M, ddr use mission mode , dram io clk=156M
+data.set 0x01306050 %long 0x00000002 //·ÖƵÉèÖ㬶ÔÓ¦ÐèÒªÐÞ¸ÄÂð
+
+//phy register init
+data.set 0x00154004 %long 0x00000007 //VALUE_PHYREG01 / Reserved:RW:2:6:=0x1, PHY_MODE:RW:0:2:=0x2(LPDDR2:0x3,LPDDR3:0x2)
+data.set 0x0015402c %long 0x00000080 //VALUE_PHYREG0B / RL:RW:4:4:=0x8
+data.set 0x00154030 %long 0x00000004 //VALUE_PHYREG0C / WL:RW:0:4:=0x4
+
+data.set 0x001543b0 %long 0x00000010 //VALUE_PHYREGEC / fbdiv[7:0]=0x10
+data.set 0x001543b4 %long 0x0000001a //VALUE_PHYREGED / PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pllpd:RW:1:1:=0x1, fbdiv[8]:RW:0:1:=0x0
+data.set 0x001543b8 %long 0x00000022 //VALUE_PHYREGEE / prediv[4:0]:RW:0:5:=0x2,postdiv[2:0]:RW:5:3:=0x1
+
+//Internal VREF generation(defualt)
+data.set 0x0015428c %long 0x00000030 //VALUE_PHYREGA3 / Channel A/B hith 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+data.set 0x001542b8 %long 0x00000030 //VALUE_PHYREGAE / Channel A/B low 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+
+//Drive strength(defualt)
+data.set 0x00154044 %long 0x0000000a //VALUE_PHYREG11 / CMD drive strength: cmd_nrcomp[4:0]:RW:0:5:=0xa
+data.set 0x00154058 %long 0x0000000a //VALUE_PHYREG16 / CK drive strength: ck_nrcomp [4:0]:RW:0:5:=0xa
+data.set 0x00154064 %long 0x0000000a //VALUE_PHYREG19 / CK pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154068 %long 0x0000000a //VALUE_PHYREG1A / CMD pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154080 %long 0x0000000a //VALUE_PHYREG20 / A_DQ0~A_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154084 %long 0x0000000a //VALUE_PHYREG21 / A_DQ0~A_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x001540b8 %long 0x0000008a //VALUE_PHYREG2E / A_DQ0~A_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540bc %long 0x0000008a //VALUE_PHYREG2F / A_DQ0~A_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540c0 %long 0x0000008a //VALUE_PHYREG30 / A_DQ8~A_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540c4 %long 0x0000008a //VALUE_PHYREG31 / A_DQ8~A_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540f8 %long 0x0000000a //VALUE_PHYREG3E / A_DQ8~A_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x001540fc %long 0x0000000a //VALUE_PHYREG3F / A_DQ8~A_DQ15 pull_up ODT:RW:0:5:=0xa
+
+data.set 0x00154100 %long 0x0000000a //VALUE_PHYREG40 / B_DQ0~B_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154104 %long 0x0000000a //VALUE_PHYREG41 / B_DQ0~B_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x00154138 %long 0x0000008a //VALUE_PHYREG4E / B_DQ0~B_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x0015413c %long 0x0000008a //VALUE_PHYREG4F / B_DQ0~B_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+
+data.set 0x00154140 %long 0x0000008a //VALUE_PHYREG50 / B_DQ8~B_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x00154144 %long 0x0000008a //VALUE_PHYREG51 / B_DQ8~B_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x00154178 %long 0x0000000a //VALUE_PHYREG5E / B_DQ8~B_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x0015417c %long 0x0000002a //VALUE_PHYREG5F / B_DQ8~B_DQ15 pull_up ODT:RW:0:5:=0xa
+
+//controller register init
+data.set 0x00150000 %long 0x01040004 //VALUE_MSTR / device_config:RW:30:2:=0x0 frequency_mode:RW:29:1:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 lpddr4:RW:5:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0
+data.set 0x00150010 %long 0x00000030 //VALUE_MRCTRL0 / mr_wr:RW:31:1:=0x0 mr_addr:RW:12:4:=0x0 mr_rank:RW:4:4:=0x3 sw_init_int:RW:3:1:=0x0 pda_en:RW:2:1:=0x0 mpr_en:RW:1:1:=0x0 mr_type:RW:0:1:=0x0
+data.set 0x00150014 %long 0x00000000 //VALUE_MRCTRL1 /mr_data:RW:0:16:=0x0
+data.set 0x00150020 %long 0x00000000 //VALUE_DERATEEN /rc_derate_value:RW:8:2:=0x0 derate_byte:RW:4:4:=0x0 derate_value:RW:1:1:=0x0 derate_enable:RW:0:1:=0x0
+data.set 0x00150024 %long 0x00800000 //VALUE_DERATEINT /mr4_read_interval:RW:0:32:=0x800000
+
+data.set 0x00150030 %long 0x00000000 //VALUE_PWRCTL / stay_in_selfref:RW:6:1:=0x0 selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+data.set 0x00150034 %long 0x00052002 //VALUE_PWRTMG / selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2
+data.set 0x00150038 %long 0x00040003 //VALUE_HWLPCTL / hw_lp_idle_x32:RW:16:12:=0x4 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1
+data.set 0x00150050 %long 0x00210000 //VALUE_RFSHCTL0 / refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0
+data.set 0x00150054 %long 0x00000000 //VALUE_RFSHCTL1 / refresh_timer1_start_value_x32:RW:16:12:=0x0 refresh_timer0_start_value_x32:RW:0:12:=0x0
+data.set 0x00150058 %long 0x00000000 //VALUE_RFSHCTL2 / refresh_timer3_start_value_x32:RW:16:12:=0x0 refresh_timer2_start_value_x32:RW:0:12:=0x0
+data.set 0x00150060 %long 0x00000000 //VALUE_RFSHCTL3 / refresh_mode:RW:4:3:=0x0 refresh_update_level:RW:1:1:=0x0 dis_auto_refresh:RW:0:1:=0x0
+data.set 0x00150064 %long 0x0019000e //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x19 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0xe
+data.set 0x001500d0 %long 0x00150001 //VALUE_INIT0 / skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x15 pre_cke_x1024:RW:0:11:=0x1
+data.set 0x001500d4 %long 0x00000000 //VALUE_INIT1 / dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0
+data.set 0x001500d8 %long 0x00000305 //VALUE_INIT2 / idle_after_reset_x32:RW:8:8:=0x3 min_stable_clock_x1:RW:0:4:=0x5
+//MR2=RL/WL£¬1£ºRL3/WL1£¬2£ºRL4/WL2£¬3£ºRL:5/WL2£¬4£ºRL6/WL3:£¬5£ºRL7/WL4£¬6£ºRL8/WL4
+data.set 0x001500dc %long 0x00430006 //VALUE_INIT3 / mr:RW:16:16:=0x43 emr:RW:0:16:=0x6
+//bit16-31£¬LPDDR2 MR3 value£¬Æ÷¼þDSĬÈÏÊÇ40ohm£¬£¨1=34.3£¬2=40,3=48,4=60,6=80£©
+data.set 0x001500e0 %long 0x00020000 //VALUE_INIT4 / emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0
+data.set 0x001500e4 %long 0x00040002 //VALUE_INIT5 / dev_zqinit_x32:RW:16:8:=0x4 max_auto_init_x1024:RW:0:10:=0x2
+data.set 0x001500f4 %long 0x0000066f //VALUE_RANKCTL / diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf
+data.set 0x00150100 %long 0x06060704 //VALUE_DRAMTMG0 / wr2pre:RW:24:6:=0x6 t_faw:RW:16:6:=0x6 t_ras_max:RW:8:7:=0x7 t_ras_min:RW:0:6:=0x4
+data.set 0x00150104 %long 0x00010207 //VALUE_DRAMTMG1 / t_xp:RW:16:5:=0x1 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0x7
+//RL=bit16-21£¬1£ºRL=2£¬2£ºRL=4£¬3£ºRL=6£¬4£ºR=8£¬WL=bit24-29£¬1£ºWL=2£¬2£ºWL=4
+//ÕâÀïµ¼ÖÂMR2µÄÅäÖã¨0x012160dc£©²»ÄÜÑ¡Ôñº¬ÓÐÆæÊýµÄÖµ?
+data.set 0x00150108 %long 0x02040606 //VALUE_DRAMTMG2 / write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:6:=0x6 wr2rd:RW:0:6:=0x5
+data.set 0x0015010c %long 0x00501000 //VALUE_DRAMTMG3 / t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0
+data.set 0x00150110 %long 0x02010203 //VALUE_DRAMTMG4 / t_rcd:RW:24:5:=0x2 t_ccd:RW:16:4:=0x1 t_rrd:RW:8:4:=0x2 t_rp:RW:0:5:=0x3
+data.set 0x00150114 %long 0x01010202 //VALUE_DRAMTMG5 / t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x2 t_cke:RW:0:4:=0x2
+data.set 0x00150118 %long 0x02020002 //VALUE_DRAMTMG6 / t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x2
+data.set 0x0015011c %long 0x00000202 //VALUE_DRAMTMG7 / t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2
+data.set 0x00150138 %long 0x0000000f //VALUE_DRAMTMG14 / t_xsr:RW:0:12:=0xf
+//bit30=1 Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit £¬7520×ʼÅäÖÃΪ0£¬µ¼ÖÂ×Ô¶¯×Ôˢй¦ÄÜÍ˳öʱÑÓʱºÜ´ó£¬sdio¶ÁÊý¾Ý³ö´í
+data.set 0x00150180 %long 0x4026000a //VALUE_ZQCTL0 / dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x1 zq_resistor_shared:RW:29:1:=0x0 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x26 t_zq_short_nop:RW:0:10:=0xa
+data.set 0x00150184 %long 0x00600100 //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0x6 t_zq_short_interval_x1024:RW:0:20:=0x100
+data.set 0x00150188 %long 0x00000000 //VALUE_ZQCTL2 / zq_reset:RW:0:1:=0x0
+//dfi_t_rddata_en=3,֮ǰ7520ÉÏÉè³É2»áµ¼Ö¶Ámr¶Á´í
+data.set 0x00150190 %long 0x04030001 //VALUE_DFITMG0 / dfi_t_ctrl_delay:RW:24:5:=0x4 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x3 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x0 dfi_tphy_wrlat:RW:0:6:=0x1
+data.set 0x00150194 %long 0x00020404 //VALUE_DFITMG1 / dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x2 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4
+data.set 0x00150198 %long 0x09001111 //VALUE_DFILPCFG0 / dfi_tlp_resp:RW:24:4:=0x9 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x1 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x1 dfi_lp_en_pd:RW:0:1:=0x1
+data.set 0x001501a0 %long 0x80400003 //VALUE_DFIUPD0 / dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3
+data.set 0x001501a4 %long 0x00000000 //VALUE_DFIUPD1 / dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0
+data.set 0x001501a8 %long 0x80100010 //VALUE_DFIUPD2 / dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10
+data.set 0x001501b0 %long 0x00000000 //VALUE_DFIMISC / dfi_data_cs_polarity:RW:2:1:=0x0 phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+data.set 0x00150200 %long 0x0000001f //VALUE_ADDRMAP0 / addrmap_dch_bit0:RW:16:5:=0x0 addrmap_cs_bit1:RW:8:5:=0x0 addrmap_cs_bit0:RW:0:5:=0x1f
+data.set 0x00150204 %long 0x00070707 //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+data.set 0x00150208 %long 0x00000000 //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+data.set 0x0015020c %long 0x0f000000 //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+data.set 0x00150210 %long 0x00000f0f //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+data.set 0x00150214 %long 0x06060606 //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+data.set 0x00150218 %long 0x0f0f0f06 //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
+data.set 0x00150240 %long 0x04000400 //VALUE_ODTCFG / wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0
+data.set 0x00150244 %long 0x00000000 //VALUE_ODTMAP / rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0
+data.set 0x00150250 %long 0x00001805 //VALUE_SCHED / rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x18 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1
+data.set 0x00150254 %long 0x00000000 //VALUE_SCHED1 / pageclose_timer:RW:0:8:=0x0
+
+data.set 0x00150300 %long 0x00000000 //VALUE_DBG0 / dis_collision_page_opt:RW:4:1:=0x0 dis_act_bypass:RW:2:1:=0x0 dis_rd_bypass:RW:1:1:=0x0 dis_wc:RW:0:1:=0x0
+data.set 0x00150304 %long 0x00000000 //VALUE_DBG1 / dis_dq:RW:1:1:=0x0 dis_hig:RW:0:1:=0x0
+data.set 0x0015030c %long 0x00000000 //VALUE_DBGCMD / ctrlupd:RWSC:5:1:=0x0 zq_calib_short:RWSC:4:1:=0x0 rank3_refresh:RWSC:3:1:=0x0 rank2_refresh:RWSC:2:1:=0x0 rank1_refresh:RWSC:1:1:=0x0 rank0_refresh:RWSC:0:1:=0x0
+
+data.set 0x00150400 %long 0x00000000 //VALUE_PCCFG / bl_exp_mode:RW:8:1:=0x0 pagematch_limit:RW:1:1:=0x0 go2critical_en:RW:0:1:=0x0
+
+//ddr_prority_config
+//port read static priority bit0-9, bit0-4 timeout, bit5-9 prority
+data.set 0x00150404 %long 0x000013ff //VALUE_PCFGR_0 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b4 %long 0x00001020 //VALUE_PCFGR_1 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20
+data.set 0x00150564 %long 0x00001000 //VALUE_PCFGR_2 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0
+data.set 0x00150614 %long 0x00001004 //VALUE_PCFGR_3 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4
+//port write static priority bit0-9
+data.set 0x00150408 %long 0x000013ff //VALUE_PCFGW_0 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b8 %long 0x000010ff //VALUE_PCFGW_1 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff
+data.set 0x00150568 %long 0x0000103f //VALUE_PCFGW_2 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f
+data.set 0x00150618 %long 0x0000105f //VALUE_PCFGW_3 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f
+//port read region set
+data.set 0x00150494 %long 0x0020000e //VALUE_PCFGQOS0_0 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x00150544 %long 0x0020000e //VALUE_PCFGQOS0_1 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001505f4 %long 0x0020000e //VALUE_PCFGQOS0_2 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001506a4 %long 0x0020000e //VALUE_PCFGQOS0_3 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+//port write region set
+data.set 0x0015049c %long 0x00000000 //VALUE_PCFGWQOS0_0 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x0015054c %long 0x00000000 //VALUE_PCFGWQOS0_1 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001505fc %long 0x00000000 //VALUE_PCFGWQOS0_2 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001506ac %long 0x00000000 //VALUE_PCFGWQOS0_3 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+//vpr timeout, region2 is red queue
+data.set 0x00150498 %long 0x00000000 //VALUE_PCFGQOS1_0 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x00150548 %long 0x00000000 //VALUE_PCFGQOS1_1 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001505f8 %long 0x00000000 //VALUE_PCFGQOS1_2 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001506a8 %long 0x00000000 //VALUE_PCFGQOS1_3 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+//vpw timeout
+data.set 0x001504a0 %long 0x00000000 //VALUE_PCFGWQOS1_0 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150550 %long 0x00000000 //VALUE_PCFGWQOS1_1 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150600 %long 0x00000000 //VALUE_PCFGWQOS1_2 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x001506b0 %long 0x00000000 //VALUE_PCFGWQOS1_3 / wqos_map_timeout:RW:0:11:=0x0
+//in CAM set
+data.set 0x0015025c %long 0x0f000001 //VALUE_PERFHPR1 / hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1
+data.set 0x00150264 %long 0x0f00007f //VALUE_PERFLPR1 / lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f
+data.set 0x0015026c %long 0x0f00007f //VALUE_PERFWR1 / w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f
+data.set 0x00150274 %long 0x00000000 //VALUE_PERFVPR1 / vpr_timeout_range:RW:0:11:=0x0
+data.set 0x00150278 %long 0x00000000 //VALUE_PERFVPW1 / vpw_timeout_range:RW:0:11:=0x0
+//port extern static priority
+//data.set 0x0013d034 %long 0xf0f00000 //port0,1 rqos=0(LPR); port2,3 rqos=F(HPR)
+//wait all register configer done in hardware
+Wait 0.01s
+
+//***********************************************************
+//ctroller and inno phy registers configer done
+//***********************************************************
+data.set 0x01306100 %long 0x0affffc0 //release ddr ctl(bit11) and axi_sn reset(bit6-9) and phy reset(bit12) //ÉèÖÃϵͳ¼Ä´æÆ÷Öµ
+Wait 0.01s
+
+//sw config done
+data.set 0x00150320 %long 0x00000000 //SWCTL // sw_done:RW:0:1:=0x0
+//check phy auto init done, wait 0x00150324 bit0 =0
+Wait 0.01s
+
+//power on PHY PLL
+data.set 0x001543b4 %long 0x00000018 //PHYREGED,PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pll_pd_en:RW:1:1:=0x0, fbdiv[8]:RW:0:1:=0x0
+//wait PHY PLL lock,PHYREGF8[0]Pll lock indicate signal
+
+Wait 0.01s
+
+//PHY DLL init start, fall edge trigger
+data.set 0x0015417c %long 0x0000000a //PHYREG5F, PHY init start:5:1:=0x1
+//wait dll lock, phy init done, PHYREGF8[1]Phy init complete signal
+Wait 0.01s
+
+//enable controller dfi_init_complete_en to start sdram init, then will send dram init cmd
+data.set 0x001501b0 %long 0x00000001 //DFIMISC // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x1 ÊÇ·ñÈ¥µô£¬»òÕ߶ÔÓ¦ÐÞ¸Ä
+//check controller status is sdram init done,wait 0x00150004 bit0-2 !=0
+Wait 0.01s
+data.set 0x001501b0 %long 0x00000000 //dfimisc[0] phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+
+//phy DQS gate training start
+data.set 0x00154008 %long 0x00000001 //PHYREG02,bit0:DQS gating calibration control=1, bit1:DQS gating bypass mode select=0
+//wait training done
+Wait 0.1s
+//phy DQS gate training stop
+data.set 0x00154008 %long 0x00000000 //PHYREG02,bit0:DQS gating calibration control=0, bit1:DQS gating bypass mode select=0
+
+//enable port_n
+data.set 0x00150490 %long 0x00000001 //VALUE_PCTRL_0 / port_en:RW:0:1:=0x1
+data.set 0x00150540 %long 0x00000001 //VALUE_PCTRL_1 / port_en:RW:0:1:=0x1
+data.set 0x001505f0 %long 0x00000001 //VALUE_PCTRL_2 / port_en:RW:0:1:=0x1
+data.set 0x001506a0 %long 0x00000001 //VALUE_PCTRL_3 / port_en:RW:0:1:=0x1
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_312m.cmm b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_312m.cmm
new file mode 100755
index 0000000..ae4de4d
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_312m.cmm
@@ -0,0 +1,210 @@
+// ********************************************************************
+//* ZX297521 Project uMCTL2 DDR controller parameter configuration
+//* uMCTL2 Rev.: 2.50a
+//* Author: Chen Jianhong
+//* Department: IP design
+//* Option: Memory Type = LPDDR2
+//* Option: Memory Frequency(MHz) = 312
+//* Option: Memory Space(Gb) = 1
+//* Option: DRAM drive impedance(Ohm) = 40
+// ********************************************************************
+
+//-------------------below is ddr setting--------------------------
+
+//data.set 0x01306100 %long 0xffffe000 //ddr all reset enable bit6-12=0
+data.set 0x01306100 %long 0x0affe000 //ddr all reset enable bit6-12=0
+Wait 0.01s
+data.set 0x01306100 %long 0x0affe400 //release ddr apb(bit10)
+Wait 0.01s
+
+//DDR top clock select top clk 156M, bit0-1, 0=156, 1=200, 2=104, 3=78
+//0: top clk=156M, ddr use mission mode , dram io clk=312M
+//1: top clk=200M, ddr use mission mode , dram io clk=400M
+//2: top clk=104M, ddr use mission mode , dram io clk=208M
+//3: top clk=78M, ddr use mission mode , dram io clk=156M
+data.set 0x01306050 %long 0x00000000 //·ÖƵÉèÖ㬶ÔÓ¦ÐèÒªÐÞ¸ÄÂð
+
+//phy register init
+data.set 0x00154004 %long 0x00000007 //VALUE_PHYREG01 / Reserved:RW:2:6:=0x1, PHY_MODE:RW:0:2:=0x2(LPDDR2:0x3,LPDDR3:0x2)
+data.set 0x0015402c %long 0x00000080 //VALUE_PHYREG0B / RL:RW:4:4:=0x8
+data.set 0x00154030 %long 0x00000004 //VALUE_PHYREG0C / WL:RW:0:4:=0x4
+
+data.set 0x001543b0 %long 0x00000010 //VALUE_PHYREGEC / fbdiv[7:0]=0x10
+data.set 0x001543b4 %long 0x0000001a //VALUE_PHYREGED / PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pllpd:RW:1:1:=0x1, fbdiv[8]:RW:0:1:=0x0
+data.set 0x001543b8 %long 0x00000022 //VALUE_PHYREGEE / prediv[4:0]:RW:0:5:=0x2,postdiv[2:0]:RW:5:3:=0x1
+
+//Internal VREF generation(defualt)
+data.set 0x0015428c %long 0x00000030 //VALUE_PHYREGA3 / Channel A/B hith 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+data.set 0x001542b8 %long 0x00000030 //VALUE_PHYREGAE / Channel A/B low 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+
+//Drive strength(defualt)
+data.set 0x00154044 %long 0x0000000a //VALUE_PHYREG11 / CMD drive strength: cmd_nrcomp[4:0]:RW:0:5:=0xa
+data.set 0x00154058 %long 0x0000000a //VALUE_PHYREG16 / CK drive strength: ck_nrcomp [4:0]:RW:0:5:=0xa
+data.set 0x00154064 %long 0x0000000a //VALUE_PHYREG19 / CK pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154068 %long 0x0000000a //VALUE_PHYREG1A / CMD pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154080 %long 0x0000000a //VALUE_PHYREG20 / A_DQ0~A_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154084 %long 0x0000000a //VALUE_PHYREG21 / A_DQ0~A_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x001540b8 %long 0x0000008a //VALUE_PHYREG2E / A_DQ0~A_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540bc %long 0x0000008a //VALUE_PHYREG2F / A_DQ0~A_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540c0 %long 0x0000008a //VALUE_PHYREG30 / A_DQ8~A_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540c4 %long 0x0000008a //VALUE_PHYREG31 / A_DQ8~A_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540f8 %long 0x0000000a //VALUE_PHYREG3E / A_DQ8~A_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x001540fc %long 0x0000000a //VALUE_PHYREG3F / A_DQ8~A_DQ15 pull_up ODT:RW:0:5:=0xa
+
+data.set 0x00154100 %long 0x0000000a //VALUE_PHYREG40 / B_DQ0~B_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154104 %long 0x0000000a //VALUE_PHYREG41 / B_DQ0~B_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x00154138 %long 0x0000008a //VALUE_PHYREG4E / B_DQ0~B_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x0015413c %long 0x0000008a //VALUE_PHYREG4F / B_DQ0~B_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+
+data.set 0x00154140 %long 0x0000008a //VALUE_PHYREG50 / B_DQ8~B_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x00154144 %long 0x0000008a //VALUE_PHYREG51 / B_DQ8~B_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x00154178 %long 0x0000000a //VALUE_PHYREG5E / B_DQ8~B_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x0015417c %long 0x0000002a //VALUE_PHYREG5F / B_DQ8~B_DQ15 pull_up ODT:RW:0:5:=0xa
+
+//controller register init
+data.set 0x00150000 %long 0x01040004 //VALUE_MSTR / device_config:RW:30:2:=0x0 frequency_mode:RW:29:1:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 lpddr4:RW:5:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0
+data.set 0x00150010 %long 0x00000030 //VALUE_MRCTRL0 / mr_wr:RW:31:1:=0x0 mr_addr:RW:12:4:=0x0 mr_rank:RW:4:4:=0x3 sw_init_int:RW:3:1:=0x0 pda_en:RW:2:1:=0x0 mpr_en:RW:1:1:=0x0 mr_type:RW:0:1:=0x0
+data.set 0x00150014 %long 0x00000000 //VALUE_MRCTRL1 /mr_data:RW:0:16:=0x0
+data.set 0x00150020 %long 0x00000000 //VALUE_DERATEEN /rc_derate_value:RW:8:2:=0x0 derate_byte:RW:4:4:=0x0 derate_value:RW:1:1:=0x0 derate_enable:RW:0:1:=0x0
+data.set 0x00150024 %long 0x00800000 //VALUE_DERATEINT /mr4_read_interval:RW:0:32:=0x800000
+
+data.set 0x00150030 %long 0x00000000 //VALUE_PWRCTL / stay_in_selfref:RW:6:1:=0x0 selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+data.set 0x00150034 %long 0x00052002 //VALUE_PWRTMG / selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2
+data.set 0x00150038 %long 0x00040003 //VALUE_HWLPCTL / hw_lp_idle_x32:RW:16:12:=0x4 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1
+data.set 0x00150050 %long 0x00210000 //VALUE_RFSHCTL0 / refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0
+data.set 0x00150054 %long 0x00000000 //VALUE_RFSHCTL1 / refresh_timer1_start_value_x32:RW:16:12:=0x0 refresh_timer0_start_value_x32:RW:0:12:=0x0
+data.set 0x00150058 %long 0x00000000 //VALUE_RFSHCTL2 / refresh_timer3_start_value_x32:RW:16:12:=0x0 refresh_timer2_start_value_x32:RW:0:12:=0x0
+data.set 0x00150060 %long 0x00000000 //VALUE_RFSHCTL3 / refresh_mode:RW:4:3:=0x0 refresh_update_level:RW:1:1:=0x0 dis_auto_refresh:RW:0:1:=0x0
+data.set 0x00150064 %long 0x00260014 //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x26 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0x14
+data.set 0x001500d0 %long 0x001f0001 //VALUE_INIT0 / skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x1f pre_cke_x1024:RW:0:11:=0x1
+data.set 0x001500d4 %long 0x00000000 //VALUE_INIT1 / dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0
+data.set 0x001500d8 %long 0x00000405 //VALUE_INIT2 / idle_after_reset_x32:RW:8:8:=0x4 min_stable_clock_x1:RW:0:4:=0x5
+//MR2=RL/WL£¬1£ºRL3/WL1£¬2£ºRL4/WL2£¬3£ºRL:5/WL2£¬4£ºRL6/WL3:£¬5£ºRL7/WL4£¬6£ºRL8/WL4
+data.set 0x001500dc %long 0x00630006 //VALUE_INIT3 / mr:RW:16:16:=0x63 emr:RW:0:16:=0x6
+//bit16-31£¬LPDDR2 MR3 value£¬Æ÷¼þDSĬÈÏÊÇ40ohm£¬£¨1=34.3£¬2=40,3=48,4=60,6=80£©
+data.set 0x001500e0 %long 0x00020000 //VALUE_INIT4 / emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0
+data.set 0x001500e4 %long 0x00050002 //VALUE_INIT5 / dev_zqinit_x32:RW:16:8:=0x5 max_auto_init_x1024:RW:0:10:=0x2
+data.set 0x001500f4 %long 0x0000066f //VALUE_RANKCTL / diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf
+data.set 0x00150100 %long 0x06080a07 //VALUE_DRAMTMG0 / wr2pre:RW:24:6:=0x6 t_faw:RW:16:6:=0x8 t_ras_max:RW:8:7:=0xa t_ras_min:RW:0:6:=0x7
+data.set 0x00150104 %long 0x0002020a //VALUE_DRAMTMG1 / t_xp:RW:16:5:=0x2 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0x9
+//RL=bit16-21£¬1£ºRL=2£¬2£ºRL=4£¬3£ºRL=6£¬4£ºR=8£¬WL=bit24-29£¬1£ºWL=2£¬2£ºWL=4
+//ÕâÀïµ¼ÖÂMR2µÄÅäÖã¨0x012160dc£©²»ÄÜÑ¡Ôñº¬ÓÐÆæÊýµÄÖµ?
+data.set 0x00150108 %long 0x02040606 //VALUE_DRAMTMG2 / write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:6:=0x6 wr2rd:RW:0:6:=0x6
+data.set 0x0015010c %long 0x00501000 //VALUE_DRAMTMG3 / t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0
+data.set 0x00150110 %long 0x03010204 //VALUE_DRAMTMG4 / t_rcd:RW:24:5:=0x3 t_ccd:RW:16:4:=0x1 t_rrd:RW:8:4:=0x2 t_rp:RW:0:5:=0x4
+data.set 0x00150114 %long 0x01010303 //VALUE_DRAMTMG5 / t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x3 t_cke:RW:0:4:=0x3
+data.set 0x00150118 %long 0x02020003 //VALUE_DRAMTMG6 / t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x3
+data.set 0x0015011c %long 0x00000202 //VALUE_DRAMTMG7 / t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2
+data.set 0x00150138 %long 0x00000016 //VALUE_DRAMTMG14 / t_xsr:RW:0:12:=0x16
+//bit30=1 Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit £¬7520×ʼÅäÖÃΪ0£¬µ¼ÖÂ×Ô¶¯×Ôˢй¦ÄÜÍ˳öʱÑÓʱºÜ´ó£¬sdio¶ÁÊý¾Ý³ö´í
+data.set 0x00150180 %long 0x4039000f //VALUE_ZQCTL0 / dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x1 zq_resistor_shared:RW:29:1:=0x0 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x39 t_zq_short_nop:RW:0:10:=0xf
+data.set 0x00150184 %long 0x00800100 //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0x8 t_zq_short_interval_x1024:RW:0:20:=0x100
+data.set 0x00150188 %long 0x00000000 //VALUE_ZQCTL2 / zq_reset:RW:0:1:=0x0
+//dfi_t_rddata_en=3,֮ǰ7520ÉÏÉè³É2»áµ¼Ö¶Ámr¶Á´í
+data.set 0x00150190 %long 0x04030001 //VALUE_DFITMG0 / dfi_t_ctrl_delay:RW:24:5:=0x4 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x3 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x0 dfi_tphy_wrlat:RW:0:6:=0x1
+data.set 0x00150194 %long 0x00020404 //VALUE_DFITMG1 / dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x2 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4
+data.set 0x00150198 %long 0x09001111 //VALUE_DFILPCFG0 / dfi_tlp_resp:RW:24:4:=0x9 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x1 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x1 dfi_lp_en_pd:RW:0:1:=0x1
+data.set 0x001501a0 %long 0x80400003 //VALUE_DFIUPD0 / dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3
+data.set 0x001501a4 %long 0x00000000 //VALUE_DFIUPD1 / dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0
+data.set 0x001501a8 %long 0x80100010 //VALUE_DFIUPD2 / dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10
+data.set 0x001501b0 %long 0x00000000 //VALUE_DFIMISC / dfi_data_cs_polarity:RW:2:1:=0x0 phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+data.set 0x00150200 %long 0x0000001f //VALUE_ADDRMAP0 / addrmap_dch_bit0:RW:16:5:=0x0 addrmap_cs_bit1:RW:8:5:=0x0 addrmap_cs_bit0:RW:0:5:=0x1f
+data.set 0x00150204 %long 0x00070707 //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+data.set 0x00150208 %long 0x00000000 //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+data.set 0x0015020c %long 0x0f000000 //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+data.set 0x00150210 %long 0x00000f0f //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+data.set 0x00150214 %long 0x06060606 //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+data.set 0x00150218 %long 0x0f0f0f06 //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
+data.set 0x00150240 %long 0x04000400 //VALUE_ODTCFG / wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0
+data.set 0x00150244 %long 0x00000000 //VALUE_ODTMAP / rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0
+data.set 0x00150250 %long 0x00001805 //VALUE_SCHED / rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x18 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1
+data.set 0x00150254 %long 0x00000000 //VALUE_SCHED1 / pageclose_timer:RW:0:8:=0x0
+
+data.set 0x00150300 %long 0x00000000 //VALUE_DBG0 / dis_collision_page_opt:RW:4:1:=0x0 dis_act_bypass:RW:2:1:=0x0 dis_rd_bypass:RW:1:1:=0x0 dis_wc:RW:0:1:=0x0
+data.set 0x00150304 %long 0x00000000 //VALUE_DBG1 / dis_dq:RW:1:1:=0x0 dis_hig:RW:0:1:=0x0
+data.set 0x0015030c %long 0x00000000 //VALUE_DBGCMD / ctrlupd:RWSC:5:1:=0x0 zq_calib_short:RWSC:4:1:=0x0 rank3_refresh:RWSC:3:1:=0x0 rank2_refresh:RWSC:2:1:=0x0 rank1_refresh:RWSC:1:1:=0x0 rank0_refresh:RWSC:0:1:=0x0
+
+data.set 0x00150400 %long 0x00000000 //VALUE_PCCFG / bl_exp_mode:RW:8:1:=0x0 pagematch_limit:RW:1:1:=0x0 go2critical_en:RW:0:1:=0x0
+
+//ddr_prority_config
+//port read static priority bit0-9, bit0-4 timeout, bit5-9 prority
+data.set 0x00150404 %long 0x000013ff //VALUE_PCFGR_0 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b4 %long 0x00001020 //VALUE_PCFGR_1 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20
+data.set 0x00150564 %long 0x00001000 //VALUE_PCFGR_2 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0
+data.set 0x00150614 %long 0x00001004 //VALUE_PCFGR_3 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4
+//port write static priority bit0-9
+data.set 0x00150408 %long 0x000013ff //VALUE_PCFGW_0 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b8 %long 0x000010ff //VALUE_PCFGW_1 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff
+data.set 0x00150568 %long 0x0000103f //VALUE_PCFGW_2 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f
+data.set 0x00150618 %long 0x0000105f //VALUE_PCFGW_3 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f
+//port read region set
+data.set 0x00150494 %long 0x0020000e //VALUE_PCFGQOS0_0 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x00150544 %long 0x0020000e //VALUE_PCFGQOS0_1 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001505f4 %long 0x0020000e //VALUE_PCFGQOS0_2 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001506a4 %long 0x0020000e //VALUE_PCFGQOS0_3 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+//port write region set
+data.set 0x0015049c %long 0x00000000 //VALUE_PCFGWQOS0_0 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x0015054c %long 0x00000000 //VALUE_PCFGWQOS0_1 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001505fc %long 0x00000000 //VALUE_PCFGWQOS0_2 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001506ac %long 0x00000000 //VALUE_PCFGWQOS0_3 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+//vpr timeout, region2 is red queue
+data.set 0x00150498 %long 0x00000000 //VALUE_PCFGQOS1_0 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x00150548 %long 0x00000000 //VALUE_PCFGQOS1_1 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001505f8 %long 0x00000000 //VALUE_PCFGQOS1_2 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001506a8 %long 0x00000000 //VALUE_PCFGQOS1_3 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+//vpw timeout
+data.set 0x001504a0 %long 0x00000000 //VALUE_PCFGWQOS1_0 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150550 %long 0x00000000 //VALUE_PCFGWQOS1_1 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150600 %long 0x00000000 //VALUE_PCFGWQOS1_2 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x001506b0 %long 0x00000000 //VALUE_PCFGWQOS1_3 / wqos_map_timeout:RW:0:11:=0x0
+//in CAM set
+data.set 0x0015025c %long 0x0f000001 //VALUE_PERFHPR1 / hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1
+data.set 0x00150264 %long 0x0f00007f //VALUE_PERFLPR1 / lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f
+data.set 0x0015026c %long 0x0f00007f //VALUE_PERFWR1 / w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f
+data.set 0x00150274 %long 0x00000000 //VALUE_PERFVPR1 / vpr_timeout_range:RW:0:11:=0x0
+data.set 0x00150278 %long 0x00000000 //VALUE_PERFVPW1 / vpw_timeout_range:RW:0:11:=0x0
+//port extern static priority
+//data.set 0x0013d034 %long 0xf0f00000 //port0,1 rqos=0(LPR); port2,3 rqos=F(HPR)
+//wait all register configer done in hardware
+Wait 0.01s
+
+//***********************************************************
+//ctroller and inno phy registers configer done
+//***********************************************************
+data.set 0x01306100 %long 0x0affffc0 //release ddr ctl(bit11) and axi_sn reset(bit6-9) and phy reset(bit12) //ÉèÖÃϵͳ¼Ä´æÆ÷Öµ
+Wait 0.01s
+
+//sw config done
+data.set 0x00150320 %long 0x00000000 //SWCTL // sw_done:RW:0:1:=0x0
+//check phy auto init done, wait 0x00150324 bit0 =0
+Wait 0.01s
+
+//power on PHY PLL
+data.set 0x001543b4 %long 0x00000018 //PHYREGED,PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pll_pd_en:RW:1:1:=0x0, fbdiv[8]:RW:0:1:=0x0
+//wait PHY PLL lock,PHYREGF8[0]Pll lock indicate signal
+
+Wait 0.01s
+
+//PHY DLL init start, fall edge trigger
+data.set 0x0015417c %long 0x0000000a //PHYREG5F, PHY init start:5:1:=0x1
+//wait dll lock, phy init done, PHYREGF8[1]Phy init complete signal
+Wait 0.01s
+
+//enable controller dfi_init_complete_en to start sdram init, then will send dram init cmd
+data.set 0x001501b0 %long 0x00000001 //DFIMISC // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x1 ÊÇ·ñÈ¥µô£¬»òÕ߶ÔÓ¦ÐÞ¸Ä
+//check controller status is sdram init done,wait 0x00150004 bit0-2 !=0
+Wait 0.01s
+data.set 0x001501b0 %long 0x00000000 //dfimisc[0] phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+
+//phy DQS gate training start
+data.set 0x00154008 %long 0x00000001 //PHYREG02,bit0:DQS gating calibration control=1, bit1:DQS gating bypass mode select=0
+//wait training done
+Wait 0.1s
+//phy DQS gate training stop
+data.set 0x00154008 %long 0x00000000 //PHYREG02,bit0:DQS gating calibration control=0, bit1:DQS gating bypass mode select=0
+
+//enable port_n
+data.set 0x00150490 %long 0x00000001 //VALUE_PCTRL_0 / port_en:RW:0:1:=0x1
+data.set 0x00150540 %long 0x00000001 //VALUE_PCTRL_1 / port_en:RW:0:1:=0x1
+data.set 0x001505f0 %long 0x00000001 //VALUE_PCTRL_2 / port_en:RW:0:1:=0x1
+data.set 0x001506a0 %long 0x00000001 //VALUE_PCTRL_3 / port_en:RW:0:1:=0x1
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_400m.cmm b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_400m.cmm
new file mode 100755
index 0000000..2e770ca
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_400m.cmm
@@ -0,0 +1,210 @@
+// ********************************************************************
+//* ZX297521 Project uMCTL2 DDR controller parameter configuration
+//* uMCTL2 Rev.: 2.50a
+//* Author: Chen Jianhong
+//* Department: IP design
+//* Option: Memory Type = LPDDR2
+//* Option: Memory Frequency(MHz) = 400
+//* Option: Memory Space(Gb) = 1
+//* Option: DRAM drive impedance(Ohm) = 40
+// ********************************************************************
+
+//-------------------below is ddr setting--------------------------
+
+//data.set 0x01306100 %long 0xffffe000 //ddr all reset enable bit6-12=0
+data.set 0x01306100 %long 0x0affe000 //ddr all reset enable bit6-12=0
+Wait 0.01s
+data.set 0x01306100 %long 0x0affe400 //release ddr apb(bit10)
+Wait 0.01s
+
+//DDR top clock select top clk 156M, bit0-1, 0=156, 1=200, 2=104, 3=78
+//0: top clk=156M, ddr use mission mode , dram io clk=312M
+//1: top clk=200M, ddr use mission mode , dram io clk=400M
+//2: top clk=104M, ddr use mission mode , dram io clk=208M
+//3: top clk=78M, ddr use mission mode , dram io clk=156M
+data.set 0x01306050 %long 0x00000001 //·ÖƵÉèÖ㬶ÔÓ¦ÐèÒªÐÞ¸ÄÂð
+
+//phy register init
+data.set 0x00154004 %long 0x00000007 //VALUE_PHYREG01 / Reserved:RW:2:6:=0x1, PHY_MODE:RW:0:2:=0x2(LPDDR2:0x3,LPDDR3:0x2)
+data.set 0x0015402c %long 0x00000080 //VALUE_PHYREG0B / RL:RW:4:4:=0x8
+data.set 0x00154030 %long 0x00000004 //VALUE_PHYREG0C / WL:RW:0:4:=0x4
+
+data.set 0x001543b0 %long 0x00000010 //VALUE_PHYREGEC / fbdiv[7:0]=0x10
+data.set 0x001543b4 %long 0x0000001a //VALUE_PHYREGED / PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pllpd:RW:1:1:=0x1, fbdiv[8]:RW:0:1:=0x0
+data.set 0x001543b8 %long 0x00000022 //VALUE_PHYREGEE / prediv[4:0]:RW:0:5:=0x2,postdiv[2:0]:RW:5:3:=0x1
+
+//Internal VREF generation(defualt)
+data.set 0x0015428c %long 0x00000030 //VALUE_PHYREGA3 / Channel A/B hith 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+data.set 0x001542b8 %long 0x00000030 //VALUE_PHYREGAE / Channel A/B low 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+
+//Drive strength(defualt)
+data.set 0x00154044 %long 0x0000000a //VALUE_PHYREG11 / CMD drive strength: cmd_nrcomp[4:0]:RW:0:5:=0xa
+data.set 0x00154058 %long 0x0000000a //VALUE_PHYREG16 / CK drive strength: ck_nrcomp [4:0]:RW:0:5:=0xa
+data.set 0x00154064 %long 0x0000000a //VALUE_PHYREG19 / CK pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154068 %long 0x0000000a //VALUE_PHYREG1A / CMD pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154080 %long 0x0000000a //VALUE_PHYREG20 / A_DQ0~A_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154084 %long 0x0000000a //VALUE_PHYREG21 / A_DQ0~A_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x001540b8 %long 0x0000008a //VALUE_PHYREG2E / A_DQ0~A_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540bc %long 0x0000008a //VALUE_PHYREG2F / A_DQ0~A_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540c0 %long 0x0000008a //VALUE_PHYREG30 / A_DQ8~A_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540c4 %long 0x0000008a //VALUE_PHYREG31 / A_DQ8~A_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540f8 %long 0x0000000a //VALUE_PHYREG3E / A_DQ8~A_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x001540fc %long 0x0000000a //VALUE_PHYREG3F / A_DQ8~A_DQ15 pull_up ODT:RW:0:5:=0xa
+
+data.set 0x00154100 %long 0x0000000a //VALUE_PHYREG40 / B_DQ0~B_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154104 %long 0x0000000a //VALUE_PHYREG41 / B_DQ0~B_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x00154138 %long 0x0000008a //VALUE_PHYREG4E / B_DQ0~B_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x0015413c %long 0x0000008a //VALUE_PHYREG4F / B_DQ0~B_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+
+data.set 0x00154140 %long 0x0000008a //VALUE_PHYREG50 / B_DQ8~B_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x00154144 %long 0x0000008a //VALUE_PHYREG51 / B_DQ8~B_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x00154178 %long 0x0000000a //VALUE_PHYREG5E / B_DQ8~B_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x0015417c %long 0x0000002a //VALUE_PHYREG5F / B_DQ8~B_DQ15 pull_up ODT:RW:0:5:=0xa
+
+//controller register init
+data.set 0x00150000 %long 0x01040004 //VALUE_MSTR / device_config:RW:30:2:=0x0 frequency_mode:RW:29:1:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 lpddr4:RW:5:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0
+data.set 0x00150010 %long 0x00000030 //VALUE_MRCTRL0 / mr_wr:RW:31:1:=0x0 mr_addr:RW:12:4:=0x0 mr_rank:RW:4:4:=0x3 sw_init_int:RW:3:1:=0x0 pda_en:RW:2:1:=0x0 mpr_en:RW:1:1:=0x0 mr_type:RW:0:1:=0x0
+data.set 0x00150014 %long 0x00000000 //VALUE_MRCTRL1 /mr_data:RW:0:16:=0x0
+data.set 0x00150020 %long 0x00000000 //VALUE_DERATEEN /rc_derate_value:RW:8:2:=0x0 derate_byte:RW:4:4:=0x0 derate_value:RW:1:1:=0x0 derate_enable:RW:0:1:=0x0
+data.set 0x00150024 %long 0x00800000 //VALUE_DERATEINT /mr4_read_interval:RW:0:32:=0x800000
+
+data.set 0x00150030 %long 0x00000000 //VALUE_PWRCTL / stay_in_selfref:RW:6:1:=0x0 selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+data.set 0x00150034 %long 0x00052002 //VALUE_PWRTMG / selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2
+data.set 0x00150038 %long 0x00040003 //VALUE_HWLPCTL / hw_lp_idle_x32:RW:16:12:=0x4 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1
+data.set 0x00150050 %long 0x00210000 //VALUE_RFSHCTL0 / refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0
+data.set 0x00150054 %long 0x00000000 //VALUE_RFSHCTL1 / refresh_timer1_start_value_x32:RW:16:12:=0x0 refresh_timer0_start_value_x32:RW:0:12:=0x0
+data.set 0x00150058 %long 0x00000000 //VALUE_RFSHCTL2 / refresh_timer3_start_value_x32:RW:16:12:=0x0 refresh_timer2_start_value_x32:RW:0:12:=0x0
+data.set 0x00150060 %long 0x00000000 //VALUE_RFSHCTL3 / refresh_mode:RW:4:3:=0x0 refresh_update_level:RW:1:1:=0x0 dis_auto_refresh:RW:0:1:=0x0
+data.set 0x00150064 %long 0x0030001a //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x30 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0x1a
+data.set 0x001500d0 %long 0x00280001 //VALUE_INIT0 / skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x28 pre_cke_x1024:RW:0:11:=0x1
+data.set 0x001500d4 %long 0x00000000 //VALUE_INIT1 / dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0
+data.set 0x001500d8 %long 0x00000605 //VALUE_INIT2 / idle_after_reset_x32:RW:8:8:=0x6 min_stable_clock_x1:RW:0:4:=0x5
+//MR2=RL/WL£¬1£ºRL3/WL1£¬2£ºRL4/WL2£¬3£ºRL:5/WL2£¬4£ºRL6/WL3:£¬5£ºRL7/WL4£¬6£ºRL8/WL4
+data.set 0x001500dc %long 0x00830006 //VALUE_INIT3 / mr:RW:16:16:=0x83 emr:RW:0:16:=0x6
+//bit16-31£¬LPDDR2 MR3 value£¬Æ÷¼þDSĬÈÏÊÇ40ohm£¬£¨1=34.3£¬2=40,3=48,4=60,6=80£©
+data.set 0x001500e0 %long 0x00020000 //VALUE_INIT4 / emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0
+data.set 0x001500e4 %long 0x00070002 //VALUE_INIT5 / dev_zqinit_x32:RW:16:8:=0x7 max_auto_init_x1024:RW:0:10:=0x2
+data.set 0x001500f4 %long 0x0000066f //VALUE_RANKCTL / diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf
+data.set 0x00150100 %long 0x070a0d08 //VALUE_DRAMTMG0 / wr2pre:RW:24:6:=0x7 t_faw:RW:16:6:=0xa t_ras_max:RW:8:7:=0xd t_ras_min:RW:0:6:=0x8
+data.set 0x00150104 %long 0x0002020d //VALUE_DRAMTMG1 / t_xp:RW:16:5:=0x2 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0xd
+//RL=bit16-21£¬1£ºRL=2£¬2£ºRL=4£¬3£ºRL=6£¬4£ºR=8£¬WL=bit24-29£¬1£ºWL=2£¬2£ºWL=4
+//ÕâÀïµ¼ÖÂMR2µÄÅäÖã¨0x012160dc£©²»ÄÜÑ¡Ôñº¬ÓÐÆæÊýµÄÖµ?
+data.set 0x00150108 %long 0x02040606 //VALUE_DRAMTMG2 / write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:6:=0x6 wr2rd:RW:0:6:=0x6
+data.set 0x0015010c %long 0x00501000 //VALUE_DRAMTMG3 / t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0
+data.set 0x00150110 %long 0x04010205 //VALUE_DRAMTMG4 / t_rcd:RW:24:5:=0x4 t_ccd:RW:16:4:=0x1 t_rrd:RW:8:4:=0x2 t_rp:RW:0:5:=0x5
+data.set 0x00150114 %long 0x01010303 //VALUE_DRAMTMG5 / t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x3 t_cke:RW:0:4:=0x3
+data.set 0x00150118 %long 0x02020003 //VALUE_DRAMTMG6 / t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x3
+data.set 0x0015011c %long 0x00000202 //VALUE_DRAMTMG7 / t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2
+data.set 0x00150138 %long 0x0000001c //VALUE_DRAMTMG14 / t_xsr:RW:0:12:=0x1c
+//bit30=1 Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit £¬7520×ʼÅäÖÃΪ0£¬µ¼ÖÂ×Ô¶¯×Ôˢй¦ÄÜÍ˳öʱÑÓʱºÜ´ó£¬sdio¶ÁÊý¾Ý³ö´í
+data.set 0x00150180 %long 0x40480012 //VALUE_ZQCTL0 / dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x1 zq_resistor_shared:RW:29:1:=0x0 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x48 t_zq_short_nop:RW:0:10:=0x12
+data.set 0x00150184 %long 0x00a00100 //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0xa t_zq_short_interval_x1024:RW:0:20:=0x100
+data.set 0x00150188 %long 0x00000000 //VALUE_ZQCTL2 / zq_reset:RW:0:1:=0x0
+//dfi_t_rddata_en=3,֮ǰ7520ÉÏÉè³É2»áµ¼Ö¶Ámr¶Á´í
+data.set 0x00150190 %long 0x04030001 //VALUE_DFITMG0 / dfi_t_ctrl_delay:RW:24:5:=0x4 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x3 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x0 dfi_tphy_wrlat:RW:0:6:=0x1
+data.set 0x00150194 %long 0x00020404 //VALUE_DFITMG1 / dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x2 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4
+data.set 0x00150198 %long 0x09001111 //VALUE_DFILPCFG0 / dfi_tlp_resp:RW:24:4:=0x9 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x1 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x1 dfi_lp_en_pd:RW:0:1:=0x1
+data.set 0x001501a0 %long 0x80400003 //VALUE_DFIUPD0 / dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3
+data.set 0x001501a4 %long 0x00000000 //VALUE_DFIUPD1 / dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0
+data.set 0x001501a8 %long 0x80100010 //VALUE_DFIUPD2 / dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10
+data.set 0x001501b0 %long 0x00000000 //VALUE_DFIMISC / dfi_data_cs_polarity:RW:2:1:=0x0 phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+data.set 0x00150200 %long 0x0000001f //VALUE_ADDRMAP0 / addrmap_dch_bit0:RW:16:5:=0x0 addrmap_cs_bit1:RW:8:5:=0x0 addrmap_cs_bit0:RW:0:5:=0x1f
+data.set 0x00150204 %long 0x00070707 //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+data.set 0x00150208 %long 0x00000000 //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+data.set 0x0015020c %long 0x0f000000 //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+data.set 0x00150210 %long 0x00000f0f //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+data.set 0x00150214 %long 0x06060606 //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+data.set 0x00150218 %long 0x0f0f0f06 //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
+data.set 0x00150240 %long 0x04000400 //VALUE_ODTCFG / wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0
+data.set 0x00150244 %long 0x00000000 //VALUE_ODTMAP / rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0
+data.set 0x00150250 %long 0x00001805 //VALUE_SCHED / rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x18 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1
+data.set 0x00150254 %long 0x00000000 //VALUE_SCHED1 / pageclose_timer:RW:0:8:=0x0
+
+data.set 0x00150300 %long 0x00000000 //VALUE_DBG0 / dis_collision_page_opt:RW:4:1:=0x0 dis_act_bypass:RW:2:1:=0x0 dis_rd_bypass:RW:1:1:=0x0 dis_wc:RW:0:1:=0x0
+data.set 0x00150304 %long 0x00000000 //VALUE_DBG1 / dis_dq:RW:1:1:=0x0 dis_hig:RW:0:1:=0x0
+data.set 0x0015030c %long 0x00000000 //VALUE_DBGCMD / ctrlupd:RWSC:5:1:=0x0 zq_calib_short:RWSC:4:1:=0x0 rank3_refresh:RWSC:3:1:=0x0 rank2_refresh:RWSC:2:1:=0x0 rank1_refresh:RWSC:1:1:=0x0 rank0_refresh:RWSC:0:1:=0x0
+
+data.set 0x00150400 %long 0x00000000 //VALUE_PCCFG / bl_exp_mode:RW:8:1:=0x0 pagematch_limit:RW:1:1:=0x0 go2critical_en:RW:0:1:=0x0
+
+//ddr_prority_config
+//port read static priority bit0-9, bit0-4 timeout, bit5-9 prority
+data.set 0x00150404 %long 0x000013ff //VALUE_PCFGR_0 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b4 %long 0x00001020 //VALUE_PCFGR_1 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20
+data.set 0x00150564 %long 0x00001000 //VALUE_PCFGR_2 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0
+data.set 0x00150614 %long 0x00001004 //VALUE_PCFGR_3 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4
+//port write static priority bit0-9
+data.set 0x00150408 %long 0x000013ff //VALUE_PCFGW_0 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b8 %long 0x000010ff //VALUE_PCFGW_1 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff
+data.set 0x00150568 %long 0x0000103f //VALUE_PCFGW_2 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f
+data.set 0x00150618 %long 0x0000105f //VALUE_PCFGW_3 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f
+//port read region set
+data.set 0x00150494 %long 0x0020000e //VALUE_PCFGQOS0_0 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x00150544 %long 0x0020000e //VALUE_PCFGQOS0_1 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001505f4 %long 0x0020000e //VALUE_PCFGQOS0_2 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001506a4 %long 0x0020000e //VALUE_PCFGQOS0_3 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+//port write region set
+data.set 0x0015049c %long 0x00000000 //VALUE_PCFGWQOS0_0 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x0015054c %long 0x00000000 //VALUE_PCFGWQOS0_1 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001505fc %long 0x00000000 //VALUE_PCFGWQOS0_2 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001506ac %long 0x00000000 //VALUE_PCFGWQOS0_3 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+//vpr timeout, region2 is red queue
+data.set 0x00150498 %long 0x00000000 //VALUE_PCFGQOS1_0 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x00150548 %long 0x00000000 //VALUE_PCFGQOS1_1 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001505f8 %long 0x00000000 //VALUE_PCFGQOS1_2 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001506a8 %long 0x00000000 //VALUE_PCFGQOS1_3 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+//vpw timeout
+data.set 0x001504a0 %long 0x00000000 //VALUE_PCFGWQOS1_0 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150550 %long 0x00000000 //VALUE_PCFGWQOS1_1 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150600 %long 0x00000000 //VALUE_PCFGWQOS1_2 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x001506b0 %long 0x00000000 //VALUE_PCFGWQOS1_3 / wqos_map_timeout:RW:0:11:=0x0
+//in CAM set
+data.set 0x0015025c %long 0x0f000001 //VALUE_PERFHPR1 / hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1
+data.set 0x00150264 %long 0x0f00007f //VALUE_PERFLPR1 / lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f
+data.set 0x0015026c %long 0x0f00007f //VALUE_PERFWR1 / w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f
+data.set 0x00150274 %long 0x00000000 //VALUE_PERFVPR1 / vpr_timeout_range:RW:0:11:=0x0
+data.set 0x00150278 %long 0x00000000 //VALUE_PERFVPW1 / vpw_timeout_range:RW:0:11:=0x0
+//port extern static priority
+//data.set 0x0013d034 %long 0xf0f00000 //port0,1 rqos=0(LPR); port2,3 rqos=F(HPR)
+//wait all register configer done in hardware
+Wait 0.01s
+
+//***********************************************************
+//ctroller and inno phy registers configer done
+//***********************************************************
+data.set 0x01306100 %long 0x0affffc0 //release ddr ctl(bit11) and axi_sn reset(bit6-9) and phy reset(bit12) //ÉèÖÃϵͳ¼Ä´æÆ÷Öµ
+Wait 0.01s
+
+//sw config done
+data.set 0x00150320 %long 0x00000000 //SWCTL // sw_done:RW:0:1:=0x0
+//check phy auto init done, wait 0x00150324 bit0 =0
+Wait 0.01s
+
+//power on PHY PLL
+data.set 0x001543b4 %long 0x00000018 //PHYREGED,PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pll_pd_en:RW:1:1:=0x0, fbdiv[8]:RW:0:1:=0x0
+//wait PHY PLL lock,PHYREGF8[0]Pll lock indicate signal
+
+Wait 0.01s
+
+//PHY DLL init start, fall edge trigger
+data.set 0x0015417c %long 0x0000000a //PHYREG5F, PHY init start:5:1:=0x1
+//wait dll lock, phy init done, PHYREGF8[1]Phy init complete signal
+Wait 0.01s
+
+//enable controller dfi_init_complete_en to start sdram init, then will send dram init cmd
+data.set 0x001501b0 %long 0x00000001 //DFIMISC // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x1 ÊÇ·ñÈ¥µô£¬»òÕ߶ÔÓ¦ÐÞ¸Ä
+//check controller status is sdram init done,wait 0x00150004 bit0-2 !=0
+Wait 0.01s
+data.set 0x001501b0 %long 0x00000000 //dfimisc[0] phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+
+//phy DQS gate training start
+data.set 0x00154008 %long 0x00000001 //PHYREG02,bit0:DQS gating calibration control=1, bit1:DQS gating bypass mode select=0
+//wait training done
+Wait 0.1s
+//phy DQS gate training stop
+data.set 0x00154008 %long 0x00000000 //PHYREG02,bit0:DQS gating calibration control=0, bit1:DQS gating bypass mode select=0
+
+//enable port_n
+data.set 0x00150490 %long 0x00000001 //VALUE_PCTRL_0 / port_en:RW:0:1:=0x1
+data.set 0x00150540 %long 0x00000001 //VALUE_PCTRL_1 / port_en:RW:0:1:=0x1
+data.set 0x001505f0 %long 0x00000001 //VALUE_PCTRL_2 / port_en:RW:0:1:=0x1
+data.set 0x001506a0 %long 0x00000001 //VALUE_PCTRL_3 / port_en:RW:0:1:=0x1
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/jtag_switch_script.cmm b/ap/build/scripts/trace32/zx297520v3/sys/jtag_switch_script.cmm
new file mode 100755
index 0000000..7f332c9
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/jtag_switch_script.cmm
@@ -0,0 +1,174 @@
+area.reset
+
+local &jtagnum &jtagfunc
+
+entry &jtagnum &jtagfunc
+
+if state.run()
+(
+ break
+)
+
+;disable mmu
+;&cr=data.long(c15:0x1)
+;tmp=&cr&(~0x1)
+;per.s c15:0x1 %LONG &tmp
+
+; set Jtag pad
+; Jtag0, 0:m0 jtag, 1:r7 jtag, 2:zsp jtag, 3:a53 jtag
+if (&jtagnum==0)
+(
+ if (&jtagfunc==0)
+ (
+ &tmp0=data.long(SD:0x0013c00c)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffc00
+ &tmp1=&tmp1&0xf83fffff
+ data.set SD:0x0013c00c %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==1)
+ (
+ &tmp0=data.long(SD:0x0130300c)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffc00
+ &tmp1=&tmp1|0x7c00000
+ data.set SD:0x0130300c %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==2)
+ (
+ &tmp0=data.long(SD:0x0130300c)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffc00
+ &tmp0=&tmp0|0x155
+ &tmp1=&tmp1|0x7c00000
+ data.set SD:0x0130300c %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==3)
+ (
+ &tmp0=data.long(SD:0x0130300c)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffc00
+ &tmp0=&tmp0|0x2aa
+ &tmp1=&tmp1|0x7c00000
+ data.set SD:0x0130300c %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+)
+
+
+; set Jtag pad
+; SD0/Jtag1, 0:m0 jtag, 1:r7 jtag, 2:zsp jtag, 3:a53 jtag
+if (&jtagnum==1)
+(
+ if (&jtagfunc==0)
+ (
+ &tmp0=data.long(SD:0x0013c008)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xffc00fff
+ &tmp0=&tmp0|0x155000
+ &tmp1=&tmp1&0xffc1ffff
+ data.set SD:0x0013c008 %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==1)
+ (
+ &tmp0=data.long(SD:0x01303008)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x155
+ &tmp1=&tmp1|0x3e0000
+ data.set SD:0x01303008 %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==2)
+ (
+ &tmp0=data.long(SD:0x01303008)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x2aa
+ &tmp1=&tmp1|0x3e0000
+ data.set SD:0x01303008 %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==3)
+ (
+ &tmp0=data.long(SD:0x01303008)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x3ff
+ &tmp1=&tmp1|0x0x3e0000
+ data.set SD:0x01303008 %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+)
+
+; set Jtag pad
+; 0:m0 jtag, 1:r7 jtag, 2:zsp jtag, 3:a53 jtag
+if (&jtagnum==2)
+(
+ if (&jtagfunc==0)
+ (
+ &tmp0=data.long(SD:0x0013c010)
+ &tmp1=data.long(SD:0x0013c02c)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x2aa
+ &tmp1=&tmp1&0xffffffe0
+ data.set SD:0x0013c010 %LE %LONG &tmp0
+ data.set SD:0x0013c02c %LE %LONG &tmp1
+ )
+ if (&jtagfunc==1)
+ (
+ &tmp0=data.long(SD:0x01303028)
+ &tmp1=data.long(SD:0x0013c02c)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp1=&tmp1|0x1f
+ data.set SD:0x01303028 %LE %LONG &tmp0
+ data.set SD:0x0013c02c %LE %LONG &tmp1
+ )
+ if (&jtagfunc==2)
+ (
+ &tmp0=data.long(SD:0x01303028)
+ &tmp1=data.long(SD:0x0013c02c)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x155
+ &tmp1=&tmp1|0x1f
+ data.set SD:0x01303028 %LE %LONG &tmp0
+ data.set SD:0x0013c02c %LE %LONG &tmp1
+ )
+ if (&jtagfunc==3)
+ (
+ &tmp0=data.long(SD:0x01303028)
+ &tmp1=data.long(SD:0x0013c02c)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x2aa
+ &tmp1=&tmp1|0x1f
+ data.set SD:0x01303028 %LE %LONG &tmp0
+ data.set SD:0x0013c02c %LE %LONG &tmp1
+ )
+)
+
+
+ DIALOG
+ (
+ header "Jtag Switch"
+
+ POS 0. 0. 50. 5.
+ BOX ""
+
+ POS 1. 1. 39. 1.
+ TEXT "Çл»³É¹¦£¬ÇëÖØÐÂÑ¡ÔñJtag£¬²¢¼ÓÔؽű¾."
+
+ POS 20. 3. 10. 1.
+ BUTTON "OK" "DIALOG.END"
+ )
+
+
+;exit:
+;restore mmu config
+;per.s c15:0x1 %LONG &cr
+print "Jtag &jtagnum switch to function &jtagfunc"
+
+enddo
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/v3e_linux_pool_debug.cmm b/ap/build/scripts/trace32/zx297520v3/v3e_linux_pool_debug.cmm
new file mode 100755
index 0000000..0210a7e
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/v3e_linux_pool_debug.cmm
@@ -0,0 +1,63 @@
+//**************************************************************************
+//*
+//* Copyright (c) 2016 ZTE Corporation.
+//*
+//**************************************************************************
+// geanfeng
+
+//**************************************************************************
+//* ½Å±¾½âÎöÇøÓò
+//**************************************************************************
+//´´½¨Ò»¸ö´°¿Ú£»
+&width=20.
+&nameWidth=20.
+&fileColumns=200.
+&fileLines=500.
+
+area.create trace &fileColumns &fileLines
+area.clear trace
+area.select trace
+
+//´ò¿ªÎļþ£»
+&dir=os.pwd()+"\log"
+if !os.dir(&dir)
+(
+ mkdir &dir
+)
+&file="&dir\result.txt"
+area.open trace &file
+area.view trace
+
+//Èç¹ûT32ÔÚÔËÐÐÒª¶Ïס£»
+if run()
+(
+ break
+)
+
+&node=v.value(g_PoolAllocInfo.head.HEAD)
+
+print "allocated ub Start:--------------------------"
+while !(&node==0)
+(
+ &file=v.value(((pool_debug_node_t*)&node)->file)
+ &line=v.value(((pool_debug_node_t*)&node)->line)
+ &size=v.value(((pool_debug_node_t*)&node)->size)
+ &thread=v.value(((pool_debug_node_t*)&node)->thread_id)
+ &name=v.string(((struct task_struct*)&thread)->comm)
+ &tick=v.value(((pool_debug_node_t*)&node)->time)
+
+ &file=data.string(d:&file)
+ &line=format.decimal(10., &line)
+ &size=format.decimal(10., &size)
+ &tick=format.decimal(10., &tick)
+ print "node: "+"&node"+" alloc_tick: "+"&tick"+" size: "+"&size"+" line: "+"&line"+" file: "+"&file"+" thread: "+"&name"
+ &node=v.value(((T_ZOss_Node*)&node)->next)
+)
+
+print "allocated ub End-----------------------------"
+
+
+
+area.close trace
+ENDDO
+//****ÔËÐнáÊø*****