[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/board.men b/ap/build/scripts/trace32/zx297520v3/sys/board.men
new file mode 100755
index 0000000..2d15a5b
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/board.men
@@ -0,0 +1,93 @@
+;==========================================================================
+; Name:
+; zte.mem
+; Description:
+; Éú³ÉOSE²Ëµ¥
+;==========================================================================
+
+;==========================================================================
+; EDIT HISTRORY FOR MODULE
+;
+; when who what, where, why
+;07/25/13 ¸ð°²·å¡¡¡¡¡¡¡¡¡¡´´½¨
+;06/10/14 ÀîÃÀ·æ 7520ÐÞ¸Ä
+;==========================================================================
+
+add
+menu
+(
+ popup "&7520Board"
+ (
+ popup "&Jtag Switch Use CMM"
+ (
+ popup "&Jtag0"
+ (
+ menuitem "&Switch to M0Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 0 0
+ )
+ menuitem "&Switch to PsJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 0 1
+ )
+ menuitem "&Switch to ZspJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 0 2
+ )
+ menuitem "&Switch to A53Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 0 3
+ )
+ )
+
+ popup "&Jtag1"
+ (
+ menuitem "&Switch to M0Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 1 0
+ )
+ menuitem "&Switch to PsJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 1 1
+ )
+ menuitem "&Switch to ZspJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 1 2
+ )
+ menuitem "&Switch to A53Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 1 3
+ )
+ )
+
+ popup "&Jtag2"
+ (
+ menuitem "&Switch to M0Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 2 0
+ )
+ menuitem "&Switch to PsJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 2 1
+ )
+ menuitem "&Switch to ZspJtag"
+ (
+ run .\sys\jtag_switch_script.cmm 2 2
+ )
+ menuitem "&Switch to A953Jtag"
+ (
+ run .\sys\jtag_switch_script.cmm 2 3
+ )
+ )
+
+ )
+
+ separator
+ menuitem "Clocks"
+ (
+ run .\sys\clocks.cmm
+ )
+ separator
+
+ )
+)
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/boot.cmm b/ap/build/scripts/trace32/zx297520v3/sys/boot.cmm
new file mode 100755
index 0000000..2d7b910
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/boot.cmm
@@ -0,0 +1,18 @@
+area.reset
+sys.cpu CortexM0
+sys.bdmclock 3.0MHz ;cortex-m0
+sys.o enreset OFF
+sys.up
+
+do ./sys/clk_init.cmm
+do ./sys/ddr_init_312m.cmm
+
+//M0 address remap bit23
+data.set 0x00140000 %long 0x00870000
+
+// Release R7/A53 reset signal
+data.set 0x0013b138 %long 0x00000001 // R7
+data.set 0x0013b134 %long 0x00000001 // A53
+
+//jtag0 to ap
+do ./sys/jtag_switch_script.cmm 0 3
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/clk_init.cmm b/ap/build/scripts/trace32/zx297520v3/sys/clk_init.cmm
new file mode 100755
index 0000000..57acdec
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/clk_init.cmm
@@ -0,0 +1,22 @@
+//MPLL power on
+data.set 0x0013b008 %long 0x08040c11
+//UPLL power on
+data.set 0x0013b010 %long 0x08347811
+//DPLL power on, ref clk sel bit25-26, 0=dpll1, 1=sys_clk_in, 2=lte_ref_clk, 3=main_clk
+//data.set 0x0013b018 %long 0x0c040c19
+//GPLL power on
+data.set 0x0013b110 %long 0x08347d29
+
+//M0 select 104M, bit0-1, 0=104, 1=26, 2=78, 3=32k
+data.set 0x0013b038 %long 0x00000005
+//hs_ahb_clk select 104M, bit4-5, 0=104, 1=26, 2=78, 3=32k
+data.set 0x0013b03c %long 0x00000010
+
+//AXI select 156M, bit0-2, 0=156, 1=26, 2=122.88, 3=104, 4=78, 5=52, 6=39
+data.set 0x01306000 %long 0x00010001
+//R7 select 624M, bit0-2, 0=624, 1=26, 2=491.5, 3=312, 4=208, 5=104, 6=78, 7=52
+data.set 0x01306020 %long 0x00000001
+//ZSP880 select 491M, bit0-2, 0=491.52, 1=26, 2=312, 3=208, 4=156, 5=104, 6=78
+data.set 0x01306030 %long 0x00000001
+//A53 select 624M, bit0-2, 0=624, 1=26, 2=491.52, 3=312, 4=208, 5=104, 6=78, 7=52
+data.set 0x01306040 %long 0x00000001
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/clocks.cmm b/ap/build/scripts/trace32/zx297520v3/sys/clocks.cmm
new file mode 100755
index 0000000..8e99377
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/clocks.cmm
@@ -0,0 +1,238 @@
+;create clocks area
+local &pll_reg
+local &foutvco
+local &fout2
+local &fout3
+
+area.create clocks 200 300
+area.clear clocks
+
+area.select clocks
+area.view clocks
+
+if state.run()
+(
+ break
+)
+
+;disable mmu
+&cr=data.long(c15:0x1)
+&tmp=&cr&(~0x1)
+per.s c15:0x1 %LONG &tmp
+
+print "*********************PLL********************************************"
+&pll_reg=0x0013b008
+&fref=26000000.
+print "check mpll..."
+Gosub calc_pll
+
+&pll_reg=0x0013b010
+&fref=26000000.
+print "check upll..."
+Gosub calc_pll
+
+&pll_reg=0x0013B018
+&tmp=data.long(D:0x0013B018)
+&tmp=(&tmp>>25)&0x3
+if (&tmp==1)
+(
+&fref=30720000.
+)
+else
+(
+&fref=26000000.
+)
+print "check dpll..."
+Gosub calc_pll
+
+&pll_reg=0x0013b110
+&fref=26000000.
+print "check gpll..."
+Gosub calc_pll
+
+print "*********************M0 CLK********************************************"
+&tmp=data.long(D:0x0013b038)
+&tmp=&tmp&0x3
+if (&tmp==0)
+(
+ print "M0 clk sel main_clk"
+)
+if (&tmp==1)
+(
+ print "M0 clk sel 104M"
+)
+if (&tmp==2)
+(
+ print "M0 clk sel 78M"
+)
+if (&tmp==3)
+(
+ print "M0 clk sel 32K"
+)
+
+print "*********************A53 CLK********************************************"
+&tmp=data.long(D:0x01306040)
+&tmp=&tmp&0x3
+if (&tmp==0)
+(
+
+ print "ufi clk sel main_clk"
+)
+if (&tmp==1)
+(
+ print "ufi clk sel 624M"
+)
+if (&tmp==2)
+(
+ print "ufi clk sel 312M"
+)
+if (&tmp==3)
+(
+ print "ufi clk sel 156M"
+)
+
+print "*********************PS CLK********************************************"
+&tmp=data.long(D:0x01306020)
+&tmp=&tmp&0x3
+if (&tmp==0)
+(
+ print "pscpu clk sel main_clk"
+)
+if (&tmp==1)
+(
+ print "pscpu clk sel 624M"
+)
+if (&tmp==2)
+(
+ print "pscpu clk sel 312M"
+)
+if (&tmp==3)
+(
+ print "pscpu clk sel 156M"
+)
+
+print "*********************PHY CLK********************************************"
+&tmp=data.long(D:0x01306030)
+&tmp=&tmp&0x3
+if (&tmp==0)
+(
+ print "phycpu clk sel main_clk"
+)
+if (&tmp==1)
+(
+ print "phycpu clk sel 491M"
+)
+if (&tmp==2)
+(
+ print "phycpu clk sel 312M"
+)
+if (&tmp==3)
+(
+ print "phycpu clk sel 156M"
+)
+
+print "*********************AXI CLK********************************************"
+&tmp=data.long(D:0x01306000)
+&tmp=&tmp&0x7
+if (&tmp==0)
+(
+ print "axi clk sel main_clk"
+)
+if (&tmp==1)
+(
+ print "axi clk sel 156M"
+)
+if (&tmp==2)
+(
+ print "axi clk sel 124.8M"
+)
+if (&tmp==3)
+(
+ print "axi clk sel 104M"
+)
+if (&tmp==4)
+(
+ print "axi clk sel 78M"
+)
+if (&tmp==5)
+(
+ print "axi clk sel 52M"
+)
+if (&tmp==6)
+(
+ print "axi clk sel 39M"
+)
+if (&tmp==7)
+(
+ print "axi clk sel 6.5M"
+)
+
+print "*********************DDR CLK********************************************"
+&tmp=data.long(D:0x01306050)
+&tmp=&tmp&0x3
+if (&tmp==0)
+(
+ print "ddr io clk sel 312M"
+)
+if (&tmp==1)
+(
+ print "ddr io clk sel 400M"
+)
+if (&tmp==2)
+(
+ print "ddr io clk sel 208M"
+)
+if (&tmp==3)
+(
+ print "ddr io clk sel 156M"
+)
+;restore mmu config
+per.s c15:0x1 %LONG &cr
+ENDDO
+
+
+;*****************************************************************
+calc_pll:
+
+local &tmp1
+local &tmp2
+&tmp1=data.long(D:&pll_reg)
+&tmp2=data.long(D:&pll_reg+0x4)
+&power=(&tmp1>>0x1f)&0x1
+if (&power==1)
+(
+ print "pll is power down"
+)
+else
+(
+ print "pll is power up"
+)
+
+&lock=(&tmp1>>0x1e)&0x1
+if (&lock==1)
+(
+ print "pll is locked"
+)
+else
+(
+ print "pll is unlocked"
+)
+
+&refdiv=(&tmp1>>0x12)&((0x1<<0x6)-1)
+&fbdiv=(&tmp1>>0x6)&((0x1<<0xc)-1)
+&frac=(&tmp2)&((0x1<<0x18)-1)
+&foutvco=(&fref/&refdiv)*(&fbdiv+&frac)
+print "pll foutvco="+"&foutvco"
+
+&postdiv1=(&tmp1>>0x3)&((0x1<<0x3)-0x1)
+&postdiv2=(&tmp1)&((0x1<<0x3)-0x1)
+&foutpostdiv=&foutvco/&postdiv1/&postdiv2
+&fout2=&foutpostdiv/0x2
+&fout3=&foutpostdiv/0x3
+&fout4=&foutpostdiv/0x4
+print "pll foutpostdiv="+"&foutpostdiv"
+print "pll fout2="+"&fout2"
+print "pll fout3="+"&fout3"
+print "pll fout4="+"&fout4"
+
+RETURN
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/ddr_init.cmm b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init.cmm
new file mode 100755
index 0000000..7a24e37
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init.cmm
@@ -0,0 +1,175 @@
+data.set 0x01306100 %long 0x00cfe000 //ddr all reset enable bit6-12=0
+Wait 0.01s
+data.set 0x01306100 %long 0x00cff400 //release ddr apb(bit10) and phy reset(bit12)
+Wait 0.01s
+
+data.set 0x0121a004 %long 0xf0000001 //PIR //bypass pll lock, DDL cal and ZQ cal
+//check 0x0121a018 bit0=1
+Wait 0.01s
+
+//select ddr work mode here, then select ddr top clk
+data.set 0x0121a020 %long 0xa01b8000 //bypass
+//data.set 0x0121a020 %long 0x001b8000 //misson
+
+//DDR top clock select top clk 624M, bit0-2, 0=624, 1=26, 2=416, 3=312, 4=208, 5=200, 6=104
+//0: top clk=624M, ddr use bypss mode , dram io clk=312M
+//1: top clk=26M, ddr use bypss mode , dram io clk=13M
+//2: top clk=416M, ddr use bypss mode , dram io clk=208M
+//3: top clk=312M, ddr use bypss mode , dram io clk=156M
+//4: top clk=208M, ddr use bypss mode , dram io clk=104M, ddr use mission mode , dram io clk=416M
+//5: top clk=200M, ddr use bypss mode , dram io clk=100M, ddr use mission mode , dram io clk=400M
+//6: top clk=104M, ddr use bypss mode , dram io clk=52M
+data.set 0x01306050 %long 0x01511110
+
+//phy register init
+data.set 0x0121a00C %long 0x0380c7a0 //VALUE_PGCR1 / LBMODE:RW:31:1:=0x0 LBGDQS:RW:29:2:=0x0 LBDQSS:RW:28:1:=0x0 IOLB:RW:27:1:=0x0 INHVT:RW:26:1:=0x0 PHYHRST:RW:25:1:=0x1 ACBVT:RW:24:1:=0x1 ACDLVT:RW:23:1:=0x1 DLDLMT:RW:15:8:=0x1 FDEPTH:RW:13:2:=0x2 LPFDEPTH:RW:11:2:=0x0 LPFEN:RW:10:1:=0x1 MDLEN:RW:9:1:=0x1 IODDRM:RW:7:2:=0x3 WLSELT:RW:6:1:=0x0 DDLBYPMODE:RW:4:2:=0x2 WLUNCRT:RW:3:1:=0x0 WLSTEP:RW:2:1:=0x0 WLMODE:RW:1:1:=0x0 GPULSE:RW:0:1:=0x0
+data.set 0x0121a014 %long 0x90aa0060 //VALUE_PGCR3 / LPWAKEUP_THRSH:RW:28:4:=0x9 cfg_pub_mode:RW:26:1:=0x0 GDQSS:RW:25:1:=0x0 PRFBYP:RW:24:1:=0x0 CKEN:RW:16:8:=0xaa GATEDXRDCLK:RW:15:1:=0x1 GATEDXDDRCLK:RW:14:1:=0x1 GATEDXCTLCLK:RW:13:1:=0x1 DISACOE:RW:12:1:=0x0 GATEACRDCLK:RW:11:1:=0x1 GATEACDDRCLK:RW:10:1:=0x1 GATEACCTLCLK:RW:9:1:=0x1 RDDLY:RW:5:4:=0x3 RDMODE:RW:3:2:=0x0 DISRST:RW:2:1:=0x0 CLKLEVEL:RW:0:2:=0x0
+data.set 0x0121a024 %long 0x0d20684f //VALUE_PTR0 / tPLLPD:RW:21:11:=0x69 tPLLGS:RW:6:15:=0x1a1 tPHYRST:RW:0:6:=0xf
+data.set 0x0121a028 %long 0x0a2903a9 //VALUE_PTR1 / tPLLLOCK:RW:16:16:=0xa29 tPLLRST:RW:0:13:=0x3a9
+data.set 0x0121a030 %long 0x0200f362 //VALUE_PTR3 / tDINIT1:RW:20:9:=0x20 tDINIT0:RW:0:20:=0xf362
+data.set 0x0121a034 %long 0x04e00d64 //VALUE_PTR4 / tDINIT3:RW:18:11:=0x138 tDINIT2:RW:0:18:=0xd64
+data.set 0x0121a080 %long 0x00181224 //VALUE_DXCCR / UDQIOM:RW:21:1:=0x0 UDQPDR:RW:20:1:=0x1 UDQPDD:RW:19:1:=0x1 UDQODT:RW:18:1:=0x0 MSBUDQ:RW:15:3:=0x0 DXSR:RW:13:2:=0x0 DQSNRES:RW:9:4:=0x9 DQSRES:RW:5:4:=0x1 MDLEN:RW:2:1:=0x1 DXIOM:RW:1:1:=0x0 DXODT:RW:0:1:=0x0
+//dfi lowpower enable io powerdown and pll powerdown
+data.set 0x0121a084 %long 0x00046487 //VALUE_DSGCR / RSTOE:RW:21:1:=0x0 SDRMODE:RW:19:2:=0x0 RRMODE:RW:18:1:=0x1 ATOAE:RW:17:1:=0x0 DTOOE:RW:16:1:=0x0 DTOIOM:RW:15:1:=0x0 DTOPDR:RW:14:1:=0x1 DTOPDD:RW:13:1:=0x1 DTOODT:RW:12:1:=0x0 PUAD:RW:8:4:=0x4 DQSGX:RW:6:2:=0x2 CUAEN:RW:5:1:=0x0 LPPLLPD:RW:4:1:=0x1 LPIOPD:RW:3:1:=0x0 ZUEN:RW:2:1:=0x1 BDISEN:RW:1:1:=0x1 PUREN:RW:0:1:=0x1
+data.set 0x0121a088 %long 0x00000408 //VALUE_DCR / UDIMM:RW:29:1:=0x0 DDR2T:RW:28:1:=0x0 NOSRA:RW:27:1:=0x0 BYTEMASK:RW:10:8:=0x1 MPRDQ:RW:7:1:=0x0 PDQ:RW:4:3:=0x0 DDR8BNK:RW:3:1:=0x1 DDRMD:RW:0:3:=0x0
+data.set 0x0121a08C %long 0x150e0583 //VALUE_DTPR0 / tRCD:RW:26:5:=0x5 tRRD:RW:22:4:=0x4 tRAS:RW:16:6:=0xe tRP:RW:8:5:=0x5 tWTR:RW:4:4:=0x8 tRTP:RW:0:4:=0x3
+data.set 0x0121a090 %long 0x22814a10 //VALUE_DTPR1 / tAOND_AOFD:RW:30:2:=0x0 tWLO:RW:26:4:=0x8 tWLMRD:RW:20:6:=0x28 tRFC:RW:11:9:=0x29 tFAW:RW:5:6:=0x10 tMOD:RW:2:3:=0x4
+data.set 0x0121a094 %long 0x10000c2c //VALUE_DTPR2 / tCCD:RW:31:1:=0x0 tRTW:RW:30:1:=0x0 tRTODT:RW:29:1:=0x0 tDLLK:RW:19:10:=0x200 tXP:RW:10:5:=0x3 tXS:RW:0:10:=0x2c
+data.set 0x0121a098 %long 0x001464d1 //VALUE_DTPR3 / tAOFDx:RW:29:3:=0x0 tMRD:RW:18:5:=0x5 tCKE:RW:13:5:=0x3 tRC:RW:6:7:=0x13 tDQSCKmax:RW:3:3:=0x2 tDQSCK:RW:0:3:=0x1
+data.set 0x0121a0A4 %long 0x00000003 //VALUE_MR2 / WRLEVELING:RW:7:1:=0x0 WLSELECT:RW:6:1:=0x0 nWRE:RW:4:1:=0x0 rl_wl:RW:0:4:=0x6
+data.set 0x0121a0A0 %long 0x00000063 //VALUE_MR1 / nWR:W:5:3:=0x3 WC:W:4:1:=0x0 BT:W:3:1:=0x0 BL:W:0:3:=0x3
+data.set 0x0121a0A8 %long 0x00000002 //VALUE_MR3 / DS:RW:0:4:=0x2
+data.set 0x0121a1A0 %long 0x00000000 //VALUE_MR11 / PDCTL:RW:2:1:=0x0 DQODT:RW:0:2:=0x0
+data.set 0x0121a240 %long 0x04058900 //VALUE_ZQCR / FORCE_ZCAL_VT_UPDATE:RW:27:1:=0x0 DIS_NON_LIN_COMP:RW:26:1:=0x1 PU_ODT_ONLY:RW:25:1:=0x0 ASYM_DRV_EN:RW:24:1:=0x0 IODLMT:RW:17:7:=0x2 AVGEN:RW:16:1:=0x1 AVGMAX:RW:14:2:=0x2 ZCAL:RW:11:3:=0x1 PGWAIT:RW:8:3:=0x1 ZQPD:RW:2:1:=0x0 TERM_OFF:RW:1:1:=0x0 ZCALBYP:RW:0:1:=0x0
+//bit0-3 output:lpddr2(5=80ohm£¬7=60ohm£¬9=48ohm£¬b=40ohm£¬d=34.3ohm),lpddr3(1=240ohm£¬3=120ohm£¬9=48ohm£¬b=40ohm£¬d=34.3ohm)
+data.set 0x0121a244 %long 0x0007bb2b //VALUE_ZQnPR / ZPROG_PU_ODT_ONLY:RW:16:4:=0x7 ZPROG_ASYM_DRV_PD:RW:12:4:=0xb ZPROG_ASYM_DRV_PU:RW:8:4:=0xb ZQDIV_ODT:RW:4:4:=0x7 ZQDIV_DS:RW:0:4:=0xb
+data.set 0x0121a254 %long 0x0007bb2b //VALUE_ZQnPR / ZPROG_PU_ODT_ONLY:RW:16:4:=0x7 ZPROG_ASYM_DRV_PD:RW:12:4:=0xb ZPROG_ASYM_DRV_PU:RW:8:4:=0xb ZQDIV_ODT:RW:4:4:=0x7 ZQDIV_DS:RW:0:4:=0xb
+data.set 0x0121a238 %long 0x00480048 //VALUE_IOVCR0 / EDXVREF:RW:24:7:=0x0 IDXVREF:RW:16:7:=0x48 EACVREF:RW:8:7:=0x0 IACVREF:RW:0:7:=0x48
+data.set 0x0121a23C %long 0x00000048 //VALUE_IOVCR1 / ZQVREF:RW:0:7:=0x48
+
+//controller register init
+data.set 0x01216000 %long 0x03040004 //VALUE_MSTR / device_config:RW:30:2:=0x0 frequency_mode:RW:29:1:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 lpddr4:RW:5:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0
+data.set 0x01216010 %long 0x00000030 //VALUE_MRCTRL0 / mr_wr:RW:31:1:=0x0 mr_addr:RW:12:4:=0x0 mr_rank:RW:4:4:=0x3 sw_init_int:RW:3:1:=0x0 pda_en:RW:2:1:=0x0 mpr_en:RW:1:1:=0x0 mr_type:RW:0:1:=0x0
+data.set 0x01216030 %long 0x00000000 //VALUE_PWRCTL / stay_in_selfref:RW:6:1:=0x0 selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+data.set 0x01216034 %long 0x00052002 //VALUE_PWRTMG / selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2
+data.set 0x01216038 %long 0x00040003 //VALUE_HWLPCTL / hw_lp_idle_x32:RW:16:12:=0x4 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1
+data.set 0x01216050 %long 0x00210000 //VALUE_RFSHCTL0 / refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0
+data.set 0x01216064 %long 0x00260014 //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x26 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0x14
+data.set 0x012160d0 %long 0x001f0001 //VALUE_INIT0 / skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x1f pre_cke_x1024:RW:0:11:=0x1
+data.set 0x012160d4 %long 0x00000000 //VALUE_INIT1 / dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0
+data.set 0x012160d8 %long 0x00000405 //VALUE_INIT2 / idle_after_reset_x32:RW:8:8:=0x4 min_stable_clock_x1:RW:0:4:=0x5
+data.set 0x012160dc %long 0x00630006 //VALUE_INIT3 / mr:RW:16:16:=0x63 emr:RW:0:16:=0x6
+//dram DS:[19:16] 1:34ohm, 2:40ohm, 3:48ohm
+data.set 0x012160e0 %long 0x00020000 //VALUE_INIT4 / emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0
+data.set 0x012160e4 %long 0x00050002 //VALUE_INIT5 / dev_zqinit_x32:RW:16:8:=0x5 max_auto_init_x1024:RW:0:10:=0x2
+data.set 0x012160f4 %long 0x0000066f //VALUE_RANKCTL / diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf
+data.set 0x01216100 %long 0x06080a07 //VALUE_DRAMTMG0 / wr2pre:RW:24:6:=0x6 t_faw:RW:16:6:=0x8 t_ras_max:RW:8:7:=0xa t_ras_min:RW:0:6:=0x7
+data.set 0x01216104 %long 0x00020209 //VALUE_DRAMTMG1 / t_xp:RW:16:5:=0x2 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0x9
+data.set 0x01216108 %long 0x02040606 //VALUE_DRAMTMG2 / write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:6:=0x6 wr2rd:RW:0:6:=0x6
+data.set 0x0121610c %long 0x00501000 //VALUE_DRAMTMG3 / t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0
+data.set 0x01216110 %long 0x03010204 //VALUE_DRAMTMG4 / t_rcd:RW:24:5:=0x3 t_ccd:RW:16:4:=0x1 t_rrd:RW:8:4:=0x2 t_rp:RW:0:5:=0x4
+data.set 0x01216114 %long 0x01010303 //VALUE_DRAMTMG5 / t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x3 t_cke:RW:0:4:=0x3
+data.set 0x01216118 %long 0x02020003 //VALUE_DRAMTMG6 / t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x3
+data.set 0x0121611c %long 0x00000202 //VALUE_DRAMTMG7 / t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2
+data.set 0x01216138 %long 0x00000016 //VALUE_DRAMTMG14 / t_xsr:RW:0:12:=0x16
+data.set 0x01216180 %long 0x4039000f //VALUE_ZQCTL0 / dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x1 zq_resistor_shared:RW:29:1:=0x0 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x39 t_zq_short_nop:RW:0:10:=0xf
+data.set 0x01216184 %long 0x00800100 //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0x8 t_zq_short_interval_x1024:RW:0:20:=0x100
+data.set 0x01216188 %long 0x00000000 //VALUE_ZQCTL2 / zq_reset:RW:0:1:=0x0
+data.set 0x01216190 %long 0x07030101 //VALUE_DFITMG0 / dfi_t_ctrl_delay:RW:24:5:=0x7 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x3 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x1 dfi_tphy_wrlat:RW:0:6:=0x1
+data.set 0x01216194 %long 0x00030404 //VALUE_DFITMG1 / dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x3 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4
+data.set 0x01216198 %long 0x07000101 //VALUE_DFILPCFG0 / dfi_tlp_resp:RW:24:4:=0x7 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x0 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x0 dfi_lp_en_pd:RW:0:1:=0x1
+data.set 0x012161a0 %long 0x80400003 //VALUE_DFIUPD0 / dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3
+data.set 0x012161a4 %long 0x00000000 //VALUE_DFIUPD1 / dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0
+data.set 0x012161a8 %long 0x80100010 //VALUE_DFIUPD2 / dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10
+data.set 0x012161ac %long 0x00100010 //VALUE_DFIUPD3 / dfi_phyupd_type3:RW:16:12:=0x10 dfi_phyupd_type2:RW:0:12:=0x10
+data.set 0x012161b0 %long 0x00000000 //VALUE_DFIMISC / dfi_data_cs_polarity:RW:2:1:=0x0 phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+data.set 0x01216200 %long 0x0000001f //VALUE_ADDRMAP0 / addrmap_dch_bit0:RW:16:5:=0x0 addrmap_cs_bit1:RW:8:5:=0x0 addrmap_cs_bit0:RW:0:5:=0x1f
+data.set 0x01216204 %long 0x00070707 //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+data.set 0x01216208 %long 0x00000000 //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+data.set 0x0121620c %long 0x0f000000 //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+data.set 0x01216210 %long 0x00000f0f //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+data.set 0x01216214 %long 0x06060606 //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+data.set 0x01216218 %long 0x0f0f0f06 //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
+data.set 0x01216240 %long 0x04000400 //VALUE_ODTCFG / wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0
+data.set 0x01216244 %long 0x00000000 //VALUE_ODTMAP / rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0
+data.set 0x01216250 %long 0x00001005 //VALUE_SCHED / rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x10 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1
+data.set 0x01216254 %long 0x00000000 //VALUE_SCHED1 / pageclose_timer:RW:0:8:=0x0
+
+ //ddr_prority_config
+ //port read static priority bit0-9, bit0-4 timeout, bit5-9 prority
+ data.set 0x01216404 %long 0x000013ff //VALUE_PCFGR_0 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff
+ data.set 0x012164b4 %long 0x000010ff //VALUE_PCFGR_1 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20
+ data.set 0x01216564 %long 0x0000103f //VALUE_PCFGR_2 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0
+ data.set 0x01216614 %long 0x0000105f //VALUE_PCFGR_3 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4
+ //port write static priority bit0-9
+ data.set 0x01216408 %long 0x000013ff //VALUE_PCFGW_0 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff
+ data.set 0x012164b8 %long 0x000010ff //VALUE_PCFGW_1 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff
+ data.set 0x01216568 %long 0x0000103f //VALUE_PCFGW_2 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f
+ data.set 0x01216618 %long 0x0000105f //VALUE_PCFGW_3 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f
+ //port read region set
+ //data.set 0x01216494 %long 0x02000e00 //VALUE_PCFGQOS0_0 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0
+ //data.set 0x01216544 %long 0x02000e00 //VALUE_PCFGQOS0_1 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0
+ //data.set 0x012165f4 %long 0x02000e00 //VALUE_PCFGQOS0_2 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0
+ //data.set 0x012166a4 %long 0x02000e00 //VALUE_PCFGQOS0_3 / rqos_map_region2:RW:24:2:=0x2 rqos_map_region1:RW:20:2:=0x0 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0xe rqos_map_level1:RW:0:4:=0x0
+ //port write region set
+ //data.set 0x0121649c %long 0x00000000 //VALUE_PCFGWQOS0_0 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+ //data.set 0x0121654c %long 0x00000000 //VALUE_PCFGWQOS0_1 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+ //data.set 0x012165fc %long 0x00000000 //VALUE_PCFGWQOS0_2 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+ //data.set 0x012166ac %long 0x00000000 //VALUE_PCFGWQOS0_3 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+ //vpr timeout, region2 is red queue
+ //data.set 0x01216498 %long 0x00000000 //VALUE_PCFGQOS1_0 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+ //data.set 0x01216548 %long 0x00000000 //VALUE_PCFGQOS1_1 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+ //data.set 0x012165f8 %long 0x00000000 //VALUE_PCFGQOS1_2 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+ //data.set 0x012166a8 %long 0x00000000 //VALUE_PCFGQOS1_3 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+ //vpw timeout
+ //data.set 0x012164a0 %long 0x00000000 //VALUE_PCFGWQOS1_0 / wqos_map_timeout:RW:0:11:=0x0
+ //data.set 0x01216550 %long 0x00000000 //VALUE_PCFGWQOS1_1 / wqos_map_timeout:RW:0:11:=0x0
+ //data.set 0x01216600 %long 0x00000000 //VALUE_PCFGWQOS1_2 / wqos_map_timeout:RW:0:11:=0x0
+ //data.set 0x012166b0 %long 0x00000000 //VALUE_PCFGWQOS1_3 / wqos_map_timeout:RW:0:11:=0x0
+ //in CAM set
+ //data,set 0x0121625c %long 0x0f000001 //VALUE_PERFHPR1 / hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1
+ //data,set 0x01216264 %long 0x0f00007f //VALUE_PERFLPR1 / lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f
+ //data,set 0x0121626c %long 0x0f00007f //VALUE_PERFWR1 / w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f
+ //data,set 0x01216274 %long 0x00000000 //VALUE_PERFVPR1 / vpr_timeout_range:RW:0:11:=0x0
+ //data,set 0x01216278 %long 0x00000000 //VALUE_PERFVPW1 / vpw_timeout_range:RW:0:11:=0x0
+ //port extern static priority
+ //REG32(0x00146064) = 0x00000000; //port0,1 level=0=LP; port2,3 level=0=LP
+
+//wait all register config into hardware
+Wait 0.01s
+
+data.set 0x01306100 %long 0x00cfffc0 //release ddr ctl(bit11) and axi_sn reset(bit6-9)
+Wait 0.01s
+
+//sw config done
+data.set 0x01216320 %long 0x00000000 //SWCTL // sw_done:RW:0:1:=0x0
+//check phy auto init done, wait 0x01216324 bit0 =0
+Wait 0.01s
+
+data.set 0x0121a004 %long 0x00040001 //PIR //notify phy that sdram will be initialized by controller
+//check 0x0121a018 bit0=1 and bit4=1
+Wait 0.01s
+
+//manual trigger calibrate
+data.set 0x0121a004 %long 0x00000023 //PIR //DDL cal, ZQ cal (for bypass)
+//data.set 0x0121a004 %long 0x00000033 //PIR //DDL cal, ZQ cal, PLL init (for mission)
+//check 0x0121a018 bit0-3=1011
+Wait 0.01s
+
+//enable controller dfi_init_complete_en to start sdram init, then will send dram init cmd
+data.set 0x012161b0 %long 0x00000001 //DFIMISC // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x1
+//check controller status is sdram init done,wait 0x01216004 bit0-2 !=0
+Wait 0.01s
+
+//training
+//bit0-1 auto enter powerdown and selfrefresh, training must close this function
+//data.set 0x01216030 %long 0x00000000 //PWRCTL // selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+//data.set 0x0121a0b0 %long 0x81001097 //DTCR //only select rank0 do training 0x91001087 bit13ÊÇ·ñ´ò¿ª£¿
+//data.set 0x0121a004 %long 0xf001
+//check 0x0121a018 bit0=1 and bit8-11=1111
+Wait 0.01s
+
+data.set 0x01216490 %long 0x00000001 //VALUE_PCTRL_0 / port_en:RW:0:1:=0x1
+data.set 0x01216540 %long 0x00000001 //VALUE_PCTRL_1 / port_en:RW:0:1:=0x1
+data.set 0x012165f0 %long 0x00000001 //VALUE_PCTRL_2 / port_en:RW:0:1:=0x1
+data.set 0x012166a0 %long 0x00000001 //VALUE_PCTRL_3 / port_en:RW:0:1:=0x1
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_156m.cmm b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_156m.cmm
new file mode 100755
index 0000000..843c4a7
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_156m.cmm
@@ -0,0 +1,210 @@
+// ********************************************************************
+//* ZX297521 Project uMCTL2 DDR controller parameter configuration
+//* uMCTL2 Rev.: 2.50a
+//* Author: Chen Jianhong
+//* Department: IP design
+//* Option: Memory Type = LPDDR2
+//* Option: Memory Frequency(MHz) = 156
+//* Option: Memory Space(Gb) = 1
+//* Option: DRAM drive impedance(Ohm) = 40
+// ********************************************************************
+
+//-------------------below is ddr setting--------------------------
+
+//data.set 0x01306100 %long 0xffffe000 //ddr all reset enable bit6-12=0
+data.set 0x01306100 %long 0x0affe000 //ddr all reset enable bit6-12=0
+Wait 0.01s
+data.set 0x01306100 %long 0x0affe400 //release ddr apb(bit10)
+Wait 0.01s
+
+//DDR top clock select top clk 156M, bit0-1, 0=156, 1=200, 2=104, 3=78
+//0: top clk=156M, ddr use mission mode , dram io clk=312M
+//1: top clk=200M, ddr use mission mode , dram io clk=400M
+//2: top clk=104M, ddr use mission mode , dram io clk=208M
+//3: top clk=78M, ddr use mission mode , dram io clk=156M
+data.set 0x01306050 %long 0x00000003 //·ÖƵÉèÖ㬶ÔÓ¦ÐèÒªÐÞ¸ÄÂð
+
+//phy register init
+data.set 0x00154004 %long 0x00000007 //VALUE_PHYREG01 / Reserved:RW:2:6:=0x1, PHY_MODE:RW:0:2:=0x2(LPDDR2:0x3,LPDDR3:0x2)
+data.set 0x0015402c %long 0x00000080 //VALUE_PHYREG0B / RL:RW:4:4:=0x8
+data.set 0x00154030 %long 0x00000004 //VALUE_PHYREG0C / WL:RW:0:4:=0x4
+
+data.set 0x001543b0 %long 0x00000020 //VALUE_PHYREGEC / fbdiv[7:0]=0x20
+data.set 0x001543b4 %long 0x0000001a //VALUE_PHYREGED / PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pllpd:RW:1:1:=0x1, fbdiv[8]:RW:0:1:=0x0
+data.set 0x001543b8 %long 0x00000042 //VALUE_PHYREGEE / prediv[4:0]:RW:0:5:=0x2,postdiv[2:0]:RW:5:3:=0x2
+
+//Internal VREF generation(defualt)
+data.set 0x0015428c %long 0x00000030 //VALUE_PHYREGA3 / Channel A/B hith 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+data.set 0x001542b8 %long 0x00000030 //VALUE_PHYREGAE / Channel A/B low 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+
+//Drive strength(defualt)
+data.set 0x00154044 %long 0x0000000a //VALUE_PHYREG11 / CMD drive strength: cmd_nrcomp[4:0]:RW:0:5:=0xa
+data.set 0x00154058 %long 0x0000000a //VALUE_PHYREG16 / CK drive strength: ck_nrcomp [4:0]:RW:0:5:=0xa
+data.set 0x00154064 %long 0x0000000a //VALUE_PHYREG19 / CK pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154068 %long 0x0000000a //VALUE_PHYREG1A / CMD pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154080 %long 0x0000000a //VALUE_PHYREG20 / A_DQ0~A_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154084 %long 0x0000000a //VALUE_PHYREG21 / A_DQ0~A_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x001540b8 %long 0x0000008a //VALUE_PHYREG2E / A_DQ0~A_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540bc %long 0x0000008a //VALUE_PHYREG2F / A_DQ0~A_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540c0 %long 0x0000008a //VALUE_PHYREG30 / A_DQ8~A_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540c4 %long 0x0000008a //VALUE_PHYREG31 / A_DQ8~A_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540f8 %long 0x0000000a //VALUE_PHYREG3E / A_DQ8~A_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x001540fc %long 0x0000000a //VALUE_PHYREG3F / A_DQ8~A_DQ15 pull_up ODT:RW:0:5:=0xa
+
+data.set 0x00154100 %long 0x0000000a //VALUE_PHYREG40 / B_DQ0~B_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154104 %long 0x0000000a //VALUE_PHYREG41 / B_DQ0~B_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x00154138 %long 0x0000008a //VALUE_PHYREG4E / B_DQ0~B_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x0015413c %long 0x0000008a //VALUE_PHYREG4F / B_DQ0~B_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+
+data.set 0x00154140 %long 0x0000008a //VALUE_PHYREG50 / B_DQ8~B_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x00154144 %long 0x0000008a //VALUE_PHYREG51 / B_DQ8~B_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x00154178 %long 0x0000000a //VALUE_PHYREG5E / B_DQ8~B_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x0015417c %long 0x0000002a //VALUE_PHYREG5F / B_DQ8~B_DQ15 pull_up ODT:RW:0:5:=0xa
+
+//controller register init
+data.set 0x00150000 %long 0x01040004 //VALUE_MSTR / device_config:RW:30:2:=0x0 frequency_mode:RW:29:1:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 lpddr4:RW:5:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0
+data.set 0x00150010 %long 0x00000030 //VALUE_MRCTRL0 / mr_wr:RW:31:1:=0x0 mr_addr:RW:12:4:=0x0 mr_rank:RW:4:4:=0x3 sw_init_int:RW:3:1:=0x0 pda_en:RW:2:1:=0x0 mpr_en:RW:1:1:=0x0 mr_type:RW:0:1:=0x0
+data.set 0x00150014 %long 0x00000000 //VALUE_MRCTRL1 /mr_data:RW:0:16:=0x0
+data.set 0x00150020 %long 0x00000000 //VALUE_DERATEEN /rc_derate_value:RW:8:2:=0x0 derate_byte:RW:4:4:=0x0 derate_value:RW:1:1:=0x0 derate_enable:RW:0:1:=0x0
+data.set 0x00150024 %long 0x00800000 //VALUE_DERATEINT /mr4_read_interval:RW:0:32:=0x800000
+
+data.set 0x00150030 %long 0x00000000 //VALUE_PWRCTL / stay_in_selfref:RW:6:1:=0x0 selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+data.set 0x00150034 %long 0x00052002 //VALUE_PWRTMG / selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2
+data.set 0x00150038 %long 0x00040003 //VALUE_HWLPCTL / hw_lp_idle_x32:RW:16:12:=0x4 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1
+data.set 0x00150050 %long 0x00210000 //VALUE_RFSHCTL0 / refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0
+data.set 0x00150054 %long 0x00000000 //VALUE_RFSHCTL1 / refresh_timer1_start_value_x32:RW:16:12:=0x0 refresh_timer0_start_value_x32:RW:0:12:=0x0
+data.set 0x00150058 %long 0x00000000 //VALUE_RFSHCTL2 / refresh_timer3_start_value_x32:RW:16:12:=0x0 refresh_timer2_start_value_x32:RW:0:12:=0x0
+data.set 0x00150060 %long 0x00000000 //VALUE_RFSHCTL3 / refresh_mode:RW:4:3:=0x0 refresh_update_level:RW:1:1:=0x0 dis_auto_refresh:RW:0:1:=0x0
+data.set 0x00150064 %long 0x0013000a //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x13 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0xa
+data.set 0x001500d0 %long 0x00100001 //VALUE_INIT0 / skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x10 pre_cke_x1024:RW:0:11:=0x1
+data.set 0x001500d4 %long 0x00000000 //VALUE_INIT1 / dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0
+data.set 0x001500d8 %long 0x00000205 //VALUE_INIT2 / idle_after_reset_x32:RW:8:8:=0x2 min_stable_clock_x1:RW:0:4:=0x5
+//MR2=RL/WL£¬1£ºRL3/WL1£¬2£ºRL4/WL2£¬3£ºRL:5/WL2£¬4£ºRL6/WL3:£¬5£ºRL7/WL4£¬6£ºRL8/WL4
+data.set 0x001500dc %long 0x00230006 //VALUE_INIT3 / mr:RW:16:16:=0x23 emr:RW:0:16:=0x6
+//bit16-31£¬LPDDR2 MR3 value£¬Æ÷¼þDSĬÈÏÊÇ40ohm£¬£¨1=34.3£¬2=40,3=48,4=60,6=80£©
+data.set 0x001500e0 %long 0x00020000 //VALUE_INIT4 / emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0
+data.set 0x001500e4 %long 0x00030001 //VALUE_INIT5 / dev_zqinit_x32:RW:16:8:=0x3 max_auto_init_x1024:RW:0:10:=0x2
+data.set 0x001500f4 %long 0x0000066f //VALUE_RANKCTL / diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf
+data.set 0x00150100 %long 0x05040503 //VALUE_DRAMTMG0 / wr2pre:RW:24:6:=0x5 t_faw:RW:16:6:=0x4 t_ras_max:RW:8:7:=0x5 t_ras_min:RW:0:6:=0x3
+data.set 0x00150104 %long 0x00010205 //VALUE_DRAMTMG1 / t_xp:RW:16:5:=0x1 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0x5
+//RL=bit16-21£¬1£ºRL=2£¬2£ºRL=4£¬3£ºRL=6£¬4£ºR=8£¬WL=bit24-29£¬1£ºWL=2£¬2£ºWL=4
+//ÕâÀïµ¼ÖÂMR2µÄÅäÖã¨0x012160dc£©²»ÄÜÑ¡Ôñº¬ÓÐÆæÊýµÄÖµ?
+data.set 0x00150108 %long 0x02040506 //VALUE_DRAMTMG2 / write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:6:=0x5 wr2rd:RW:0:6:=0x5
+data.set 0x0015010c %long 0x00501000 //VALUE_DRAMTMG3 / t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0
+data.set 0x00150110 %long 0x02010103 //VALUE_DRAMTMG4 / t_rcd:RW:24:5:=0x2 t_ccd:RW:16:4:=0x1 t_rrd:RW:8:4:=0x1 t_rp:RW:0:5:=0x3
+data.set 0x00150114 %long 0x01010202 //VALUE_DRAMTMG5 / t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x2 t_cke:RW:0:4:=0x2
+data.set 0x00150118 %long 0x02020002 //VALUE_DRAMTMG6 / t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x2
+data.set 0x0015011c %long 0x00000202 //VALUE_DRAMTMG7 / t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2
+data.set 0x00150138 %long 0x0000000b //VALUE_DRAMTMG14 / t_xsr:RW:0:12:=0xb
+//bit30=1 Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit £¬7520×ʼÅäÖÃΪ0£¬µ¼ÖÂ×Ô¶¯×Ôˢй¦ÄÜÍ˳öʱÑÓʱºÜ´ó£¬sdio¶ÁÊý¾Ý³ö´í
+data.set 0x00150180 %long 0x401d0008 //VALUE_ZQCTL0 / dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x1 zq_resistor_shared:RW:29:1:=0x0 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x1d t_zq_short_nop:RW:0:10:=0x8
+data.set 0x00150184 %long 0x00400100 //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0x4 t_zq_short_interval_x1024:RW:0:20:=0x100
+data.set 0x00150188 %long 0x00000000 //VALUE_ZQCTL2 / zq_reset:RW:0:1:=0x0
+//dfi_t_rddata_en=3,֮ǰ7520ÉÏÉè³É2»áµ¼Ö¶Ámr¶Á´í
+data.set 0x00150190 %long 0x04030001 //VALUE_DFITMG0 / dfi_t_ctrl_delay:RW:24:5:=0x4 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x3 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x0 dfi_tphy_wrlat:RW:0:6:=0x1
+data.set 0x00150194 %long 0x00020404 //VALUE_DFITMG1 / dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x2 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4
+data.set 0x00150198 %long 0x09001111 //VALUE_DFILPCFG0 / dfi_tlp_resp:RW:24:4:=0x9 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x1 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x1 dfi_lp_en_pd:RW:0:1:=0x1
+data.set 0x001501a0 %long 0x80400003 //VALUE_DFIUPD0 / dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3
+data.set 0x001501a4 %long 0x00000000 //VALUE_DFIUPD1 / dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0
+data.set 0x001501a8 %long 0x80100010 //VALUE_DFIUPD2 / dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10
+data.set 0x001501b0 %long 0x00000000 //VALUE_DFIMISC / dfi_data_cs_polarity:RW:2:1:=0x0 phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+data.set 0x00150200 %long 0x0000001f //VALUE_ADDRMAP0 / addrmap_dch_bit0:RW:16:5:=0x0 addrmap_cs_bit1:RW:8:5:=0x0 addrmap_cs_bit0:RW:0:5:=0x1f
+data.set 0x00150204 %long 0x00070707 //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+data.set 0x00150208 %long 0x00000000 //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+data.set 0x0015020c %long 0x0f000000 //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+data.set 0x00150210 %long 0x00000f0f //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+data.set 0x00150214 %long 0x06060606 //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+data.set 0x00150218 %long 0x0f0f0f06 //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
+data.set 0x00150240 %long 0x04000400 //VALUE_ODTCFG / wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0
+data.set 0x00150244 %long 0x00000000 //VALUE_ODTMAP / rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0
+data.set 0x00150250 %long 0x00001805 //VALUE_SCHED / rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x18 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1
+data.set 0x00150254 %long 0x00000000 //VALUE_SCHED1 / pageclose_timer:RW:0:8:=0x0
+
+data.set 0x00150300 %long 0x00000000 //VALUE_DBG0 / dis_collision_page_opt:RW:4:1:=0x0 dis_act_bypass:RW:2:1:=0x0 dis_rd_bypass:RW:1:1:=0x0 dis_wc:RW:0:1:=0x0
+data.set 0x00150304 %long 0x00000000 //VALUE_DBG1 / dis_dq:RW:1:1:=0x0 dis_hig:RW:0:1:=0x0
+data.set 0x0015030c %long 0x00000000 //VALUE_DBGCMD / ctrlupd:RWSC:5:1:=0x0 zq_calib_short:RWSC:4:1:=0x0 rank3_refresh:RWSC:3:1:=0x0 rank2_refresh:RWSC:2:1:=0x0 rank1_refresh:RWSC:1:1:=0x0 rank0_refresh:RWSC:0:1:=0x0
+
+data.set 0x00150400 %long 0x00000000 //VALUE_PCCFG / bl_exp_mode:RW:8:1:=0x0 pagematch_limit:RW:1:1:=0x0 go2critical_en:RW:0:1:=0x0
+
+//ddr_prority_config
+//port read static priority bit0-9, bit0-4 timeout, bit5-9 prority
+data.set 0x00150404 %long 0x000013ff //VALUE_PCFGR_0 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b4 %long 0x00001020 //VALUE_PCFGR_1 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20
+data.set 0x00150564 %long 0x00001000 //VALUE_PCFGR_2 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0
+data.set 0x00150614 %long 0x00001004 //VALUE_PCFGR_3 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4
+//port write static priority bit0-9
+data.set 0x00150408 %long 0x000013ff //VALUE_PCFGW_0 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b8 %long 0x000010ff //VALUE_PCFGW_1 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff
+data.set 0x00150568 %long 0x0000103f //VALUE_PCFGW_2 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f
+data.set 0x00150618 %long 0x0000105f //VALUE_PCFGW_3 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f
+//port read region set
+data.set 0x00150494 %long 0x0020000e //VALUE_PCFGQOS0_0 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x00150544 %long 0x0020000e //VALUE_PCFGQOS0_1 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001505f4 %long 0x0020000e //VALUE_PCFGQOS0_2 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001506a4 %long 0x0020000e //VALUE_PCFGQOS0_3 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+//port write region set
+data.set 0x0015049c %long 0x00000000 //VALUE_PCFGWQOS0_0 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x0015054c %long 0x00000000 //VALUE_PCFGWQOS0_1 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001505fc %long 0x00000000 //VALUE_PCFGWQOS0_2 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001506ac %long 0x00000000 //VALUE_PCFGWQOS0_3 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+//vpr timeout, region2 is red queue
+data.set 0x00150498 %long 0x00000000 //VALUE_PCFGQOS1_0 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x00150548 %long 0x00000000 //VALUE_PCFGQOS1_1 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001505f8 %long 0x00000000 //VALUE_PCFGQOS1_2 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001506a8 %long 0x00000000 //VALUE_PCFGQOS1_3 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+//vpw timeout
+data.set 0x001504a0 %long 0x00000000 //VALUE_PCFGWQOS1_0 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150550 %long 0x00000000 //VALUE_PCFGWQOS1_1 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150600 %long 0x00000000 //VALUE_PCFGWQOS1_2 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x001506b0 %long 0x00000000 //VALUE_PCFGWQOS1_3 / wqos_map_timeout:RW:0:11:=0x0
+//in CAM set
+data.set 0x0015025c %long 0x0f000001 //VALUE_PERFHPR1 / hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1
+data.set 0x00150264 %long 0x0f00007f //VALUE_PERFLPR1 / lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f
+data.set 0x0015026c %long 0x0f00007f //VALUE_PERFWR1 / w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f
+data.set 0x00150274 %long 0x00000000 //VALUE_PERFVPR1 / vpr_timeout_range:RW:0:11:=0x0
+data.set 0x00150278 %long 0x00000000 //VALUE_PERFVPW1 / vpw_timeout_range:RW:0:11:=0x0
+//port extern static priority
+//data.set 0x0013d034 %long 0xf0f00000 //port0,1 rqos=0(LPR); port2,3 rqos=F(HPR)
+//wait all register configer done in hardware
+Wait 0.01s
+
+//***********************************************************
+//ctroller and inno phy registers configer done
+//***********************************************************
+data.set 0x01306100 %long 0x0affffc0 //release ddr ctl(bit11) and axi_sn reset(bit6-9) and phy reset(bit12) //ÉèÖÃϵͳ¼Ä´æÆ÷Öµ
+Wait 0.01s
+
+//sw config done
+data.set 0x00150320 %long 0x00000000 //SWCTL // sw_done:RW:0:1:=0x0
+//check phy auto init done, wait 0x00150324 bit0 =0
+Wait 0.01s
+
+//power on PHY PLL
+data.set 0x001543b4 %long 0x00000018 //PHYREGED,PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pll_pd_en:RW:1:1:=0x0, fbdiv[8]:RW:0:1:=0x0
+//wait PHY PLL lock,PHYREGF8[0]Pll lock indicate signal
+
+Wait 0.01s
+
+//PHY DLL init start, fall edge trigger
+data.set 0x0015417c %long 0x0000000a //PHYREG5F, PHY init start:5:1:=0x1
+//wait dll lock, phy init done, PHYREGF8[1]Phy init complete signal
+Wait 0.01s
+
+//enable controller dfi_init_complete_en to start sdram init, then will send dram init cmd
+data.set 0x001501b0 %long 0x00000001 //DFIMISC // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x1 ÊÇ·ñÈ¥µô£¬»òÕ߶ÔÓ¦ÐÞ¸Ä
+//check controller status is sdram init done,wait 0x00150004 bit0-2 !=0
+Wait 0.01s
+data.set 0x001501b0 %long 0x00000000 //dfimisc[0] phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+
+//phy DQS gate training start
+data.set 0x00154008 %long 0x00000001 //PHYREG02,bit0:DQS gating calibration control=1, bit1:DQS gating bypass mode select=0
+//wait training done
+Wait 0.1s
+//phy DQS gate training stop
+data.set 0x00154008 %long 0x00000000 //PHYREG02,bit0:DQS gating calibration control=0, bit1:DQS gating bypass mode select=0
+
+//enable port_n
+data.set 0x00150490 %long 0x00000001 //VALUE_PCTRL_0 / port_en:RW:0:1:=0x1
+data.set 0x00150540 %long 0x00000001 //VALUE_PCTRL_1 / port_en:RW:0:1:=0x1
+data.set 0x001505f0 %long 0x00000001 //VALUE_PCTRL_2 / port_en:RW:0:1:=0x1
+data.set 0x001506a0 %long 0x00000001 //VALUE_PCTRL_3 / port_en:RW:0:1:=0x1
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_208m.cmm b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_208m.cmm
new file mode 100755
index 0000000..02bb5e8
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_208m.cmm
@@ -0,0 +1,210 @@
+// ********************************************************************
+//* ZX297521 Project uMCTL2 DDR controller parameter configuration
+//* uMCTL2 Rev.: 2.50a
+//* Author: Chen Jianhong
+//* Department: IP design
+//* Option: Memory Type = LPDDR2
+//* Option: Memory Frequency(MHz) = 208
+//* Option: Memory Space(Gb) = 1
+//* Option: DRAM drive impedance(Ohm) = 40
+// ********************************************************************
+
+//-------------------below is ddr setting--------------------------
+
+//data.set 0x01306100 %long 0xffffe000 //ddr all reset enable bit6-12=0
+data.set 0x01306100 %long 0x0affe000 //ddr all reset enable bit6-12=0
+Wait 0.01s
+data.set 0x01306100 %long 0x0affe400 //release ddr apb(bit10)
+Wait 0.01s
+
+//DDR top clock select top clk 156M, bit0-1, 0=156, 1=200, 2=104, 3=78
+//0: top clk=156M, ddr use mission mode , dram io clk=312M
+//1: top clk=200M, ddr use mission mode , dram io clk=400M
+//2: top clk=104M, ddr use mission mode , dram io clk=208M
+//3: top clk=78M, ddr use mission mode , dram io clk=156M
+data.set 0x01306050 %long 0x00000002 //·ÖƵÉèÖ㬶ÔÓ¦ÐèÒªÐÞ¸ÄÂð
+
+//phy register init
+data.set 0x00154004 %long 0x00000007 //VALUE_PHYREG01 / Reserved:RW:2:6:=0x1, PHY_MODE:RW:0:2:=0x2(LPDDR2:0x3,LPDDR3:0x2)
+data.set 0x0015402c %long 0x00000080 //VALUE_PHYREG0B / RL:RW:4:4:=0x8
+data.set 0x00154030 %long 0x00000004 //VALUE_PHYREG0C / WL:RW:0:4:=0x4
+
+data.set 0x001543b0 %long 0x00000010 //VALUE_PHYREGEC / fbdiv[7:0]=0x10
+data.set 0x001543b4 %long 0x0000001a //VALUE_PHYREGED / PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pllpd:RW:1:1:=0x1, fbdiv[8]:RW:0:1:=0x0
+data.set 0x001543b8 %long 0x00000022 //VALUE_PHYREGEE / prediv[4:0]:RW:0:5:=0x2,postdiv[2:0]:RW:5:3:=0x1
+
+//Internal VREF generation(defualt)
+data.set 0x0015428c %long 0x00000030 //VALUE_PHYREGA3 / Channel A/B hith 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+data.set 0x001542b8 %long 0x00000030 //VALUE_PHYREGAE / Channel A/B low 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+
+//Drive strength(defualt)
+data.set 0x00154044 %long 0x0000000a //VALUE_PHYREG11 / CMD drive strength: cmd_nrcomp[4:0]:RW:0:5:=0xa
+data.set 0x00154058 %long 0x0000000a //VALUE_PHYREG16 / CK drive strength: ck_nrcomp [4:0]:RW:0:5:=0xa
+data.set 0x00154064 %long 0x0000000a //VALUE_PHYREG19 / CK pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154068 %long 0x0000000a //VALUE_PHYREG1A / CMD pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154080 %long 0x0000000a //VALUE_PHYREG20 / A_DQ0~A_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154084 %long 0x0000000a //VALUE_PHYREG21 / A_DQ0~A_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x001540b8 %long 0x0000008a //VALUE_PHYREG2E / A_DQ0~A_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540bc %long 0x0000008a //VALUE_PHYREG2F / A_DQ0~A_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540c0 %long 0x0000008a //VALUE_PHYREG30 / A_DQ8~A_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540c4 %long 0x0000008a //VALUE_PHYREG31 / A_DQ8~A_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540f8 %long 0x0000000a //VALUE_PHYREG3E / A_DQ8~A_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x001540fc %long 0x0000000a //VALUE_PHYREG3F / A_DQ8~A_DQ15 pull_up ODT:RW:0:5:=0xa
+
+data.set 0x00154100 %long 0x0000000a //VALUE_PHYREG40 / B_DQ0~B_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154104 %long 0x0000000a //VALUE_PHYREG41 / B_DQ0~B_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x00154138 %long 0x0000008a //VALUE_PHYREG4E / B_DQ0~B_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x0015413c %long 0x0000008a //VALUE_PHYREG4F / B_DQ0~B_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+
+data.set 0x00154140 %long 0x0000008a //VALUE_PHYREG50 / B_DQ8~B_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x00154144 %long 0x0000008a //VALUE_PHYREG51 / B_DQ8~B_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x00154178 %long 0x0000000a //VALUE_PHYREG5E / B_DQ8~B_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x0015417c %long 0x0000002a //VALUE_PHYREG5F / B_DQ8~B_DQ15 pull_up ODT:RW:0:5:=0xa
+
+//controller register init
+data.set 0x00150000 %long 0x01040004 //VALUE_MSTR / device_config:RW:30:2:=0x0 frequency_mode:RW:29:1:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 lpddr4:RW:5:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0
+data.set 0x00150010 %long 0x00000030 //VALUE_MRCTRL0 / mr_wr:RW:31:1:=0x0 mr_addr:RW:12:4:=0x0 mr_rank:RW:4:4:=0x3 sw_init_int:RW:3:1:=0x0 pda_en:RW:2:1:=0x0 mpr_en:RW:1:1:=0x0 mr_type:RW:0:1:=0x0
+data.set 0x00150014 %long 0x00000000 //VALUE_MRCTRL1 /mr_data:RW:0:16:=0x0
+data.set 0x00150020 %long 0x00000000 //VALUE_DERATEEN /rc_derate_value:RW:8:2:=0x0 derate_byte:RW:4:4:=0x0 derate_value:RW:1:1:=0x0 derate_enable:RW:0:1:=0x0
+data.set 0x00150024 %long 0x00800000 //VALUE_DERATEINT /mr4_read_interval:RW:0:32:=0x800000
+
+data.set 0x00150030 %long 0x00000000 //VALUE_PWRCTL / stay_in_selfref:RW:6:1:=0x0 selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+data.set 0x00150034 %long 0x00052002 //VALUE_PWRTMG / selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2
+data.set 0x00150038 %long 0x00040003 //VALUE_HWLPCTL / hw_lp_idle_x32:RW:16:12:=0x4 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1
+data.set 0x00150050 %long 0x00210000 //VALUE_RFSHCTL0 / refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0
+data.set 0x00150054 %long 0x00000000 //VALUE_RFSHCTL1 / refresh_timer1_start_value_x32:RW:16:12:=0x0 refresh_timer0_start_value_x32:RW:0:12:=0x0
+data.set 0x00150058 %long 0x00000000 //VALUE_RFSHCTL2 / refresh_timer3_start_value_x32:RW:16:12:=0x0 refresh_timer2_start_value_x32:RW:0:12:=0x0
+data.set 0x00150060 %long 0x00000000 //VALUE_RFSHCTL3 / refresh_mode:RW:4:3:=0x0 refresh_update_level:RW:1:1:=0x0 dis_auto_refresh:RW:0:1:=0x0
+data.set 0x00150064 %long 0x0019000e //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x19 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0xe
+data.set 0x001500d0 %long 0x00150001 //VALUE_INIT0 / skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x15 pre_cke_x1024:RW:0:11:=0x1
+data.set 0x001500d4 %long 0x00000000 //VALUE_INIT1 / dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0
+data.set 0x001500d8 %long 0x00000305 //VALUE_INIT2 / idle_after_reset_x32:RW:8:8:=0x3 min_stable_clock_x1:RW:0:4:=0x5
+//MR2=RL/WL£¬1£ºRL3/WL1£¬2£ºRL4/WL2£¬3£ºRL:5/WL2£¬4£ºRL6/WL3:£¬5£ºRL7/WL4£¬6£ºRL8/WL4
+data.set 0x001500dc %long 0x00430006 //VALUE_INIT3 / mr:RW:16:16:=0x43 emr:RW:0:16:=0x6
+//bit16-31£¬LPDDR2 MR3 value£¬Æ÷¼þDSĬÈÏÊÇ40ohm£¬£¨1=34.3£¬2=40,3=48,4=60,6=80£©
+data.set 0x001500e0 %long 0x00020000 //VALUE_INIT4 / emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0
+data.set 0x001500e4 %long 0x00040002 //VALUE_INIT5 / dev_zqinit_x32:RW:16:8:=0x4 max_auto_init_x1024:RW:0:10:=0x2
+data.set 0x001500f4 %long 0x0000066f //VALUE_RANKCTL / diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf
+data.set 0x00150100 %long 0x06060704 //VALUE_DRAMTMG0 / wr2pre:RW:24:6:=0x6 t_faw:RW:16:6:=0x6 t_ras_max:RW:8:7:=0x7 t_ras_min:RW:0:6:=0x4
+data.set 0x00150104 %long 0x00010207 //VALUE_DRAMTMG1 / t_xp:RW:16:5:=0x1 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0x7
+//RL=bit16-21£¬1£ºRL=2£¬2£ºRL=4£¬3£ºRL=6£¬4£ºR=8£¬WL=bit24-29£¬1£ºWL=2£¬2£ºWL=4
+//ÕâÀïµ¼ÖÂMR2µÄÅäÖã¨0x012160dc£©²»ÄÜÑ¡Ôñº¬ÓÐÆæÊýµÄÖµ?
+data.set 0x00150108 %long 0x02040606 //VALUE_DRAMTMG2 / write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:6:=0x6 wr2rd:RW:0:6:=0x5
+data.set 0x0015010c %long 0x00501000 //VALUE_DRAMTMG3 / t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0
+data.set 0x00150110 %long 0x02010203 //VALUE_DRAMTMG4 / t_rcd:RW:24:5:=0x2 t_ccd:RW:16:4:=0x1 t_rrd:RW:8:4:=0x2 t_rp:RW:0:5:=0x3
+data.set 0x00150114 %long 0x01010202 //VALUE_DRAMTMG5 / t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x2 t_cke:RW:0:4:=0x2
+data.set 0x00150118 %long 0x02020002 //VALUE_DRAMTMG6 / t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x2
+data.set 0x0015011c %long 0x00000202 //VALUE_DRAMTMG7 / t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2
+data.set 0x00150138 %long 0x0000000f //VALUE_DRAMTMG14 / t_xsr:RW:0:12:=0xf
+//bit30=1 Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit £¬7520×ʼÅäÖÃΪ0£¬µ¼ÖÂ×Ô¶¯×Ôˢй¦ÄÜÍ˳öʱÑÓʱºÜ´ó£¬sdio¶ÁÊý¾Ý³ö´í
+data.set 0x00150180 %long 0x4026000a //VALUE_ZQCTL0 / dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x1 zq_resistor_shared:RW:29:1:=0x0 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x26 t_zq_short_nop:RW:0:10:=0xa
+data.set 0x00150184 %long 0x00600100 //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0x6 t_zq_short_interval_x1024:RW:0:20:=0x100
+data.set 0x00150188 %long 0x00000000 //VALUE_ZQCTL2 / zq_reset:RW:0:1:=0x0
+//dfi_t_rddata_en=3,֮ǰ7520ÉÏÉè³É2»áµ¼Ö¶Ámr¶Á´í
+data.set 0x00150190 %long 0x04030001 //VALUE_DFITMG0 / dfi_t_ctrl_delay:RW:24:5:=0x4 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x3 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x0 dfi_tphy_wrlat:RW:0:6:=0x1
+data.set 0x00150194 %long 0x00020404 //VALUE_DFITMG1 / dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x2 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4
+data.set 0x00150198 %long 0x09001111 //VALUE_DFILPCFG0 / dfi_tlp_resp:RW:24:4:=0x9 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x1 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x1 dfi_lp_en_pd:RW:0:1:=0x1
+data.set 0x001501a0 %long 0x80400003 //VALUE_DFIUPD0 / dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3
+data.set 0x001501a4 %long 0x00000000 //VALUE_DFIUPD1 / dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0
+data.set 0x001501a8 %long 0x80100010 //VALUE_DFIUPD2 / dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10
+data.set 0x001501b0 %long 0x00000000 //VALUE_DFIMISC / dfi_data_cs_polarity:RW:2:1:=0x0 phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+data.set 0x00150200 %long 0x0000001f //VALUE_ADDRMAP0 / addrmap_dch_bit0:RW:16:5:=0x0 addrmap_cs_bit1:RW:8:5:=0x0 addrmap_cs_bit0:RW:0:5:=0x1f
+data.set 0x00150204 %long 0x00070707 //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+data.set 0x00150208 %long 0x00000000 //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+data.set 0x0015020c %long 0x0f000000 //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+data.set 0x00150210 %long 0x00000f0f //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+data.set 0x00150214 %long 0x06060606 //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+data.set 0x00150218 %long 0x0f0f0f06 //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
+data.set 0x00150240 %long 0x04000400 //VALUE_ODTCFG / wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0
+data.set 0x00150244 %long 0x00000000 //VALUE_ODTMAP / rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0
+data.set 0x00150250 %long 0x00001805 //VALUE_SCHED / rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x18 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1
+data.set 0x00150254 %long 0x00000000 //VALUE_SCHED1 / pageclose_timer:RW:0:8:=0x0
+
+data.set 0x00150300 %long 0x00000000 //VALUE_DBG0 / dis_collision_page_opt:RW:4:1:=0x0 dis_act_bypass:RW:2:1:=0x0 dis_rd_bypass:RW:1:1:=0x0 dis_wc:RW:0:1:=0x0
+data.set 0x00150304 %long 0x00000000 //VALUE_DBG1 / dis_dq:RW:1:1:=0x0 dis_hig:RW:0:1:=0x0
+data.set 0x0015030c %long 0x00000000 //VALUE_DBGCMD / ctrlupd:RWSC:5:1:=0x0 zq_calib_short:RWSC:4:1:=0x0 rank3_refresh:RWSC:3:1:=0x0 rank2_refresh:RWSC:2:1:=0x0 rank1_refresh:RWSC:1:1:=0x0 rank0_refresh:RWSC:0:1:=0x0
+
+data.set 0x00150400 %long 0x00000000 //VALUE_PCCFG / bl_exp_mode:RW:8:1:=0x0 pagematch_limit:RW:1:1:=0x0 go2critical_en:RW:0:1:=0x0
+
+//ddr_prority_config
+//port read static priority bit0-9, bit0-4 timeout, bit5-9 prority
+data.set 0x00150404 %long 0x000013ff //VALUE_PCFGR_0 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b4 %long 0x00001020 //VALUE_PCFGR_1 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20
+data.set 0x00150564 %long 0x00001000 //VALUE_PCFGR_2 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0
+data.set 0x00150614 %long 0x00001004 //VALUE_PCFGR_3 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4
+//port write static priority bit0-9
+data.set 0x00150408 %long 0x000013ff //VALUE_PCFGW_0 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b8 %long 0x000010ff //VALUE_PCFGW_1 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff
+data.set 0x00150568 %long 0x0000103f //VALUE_PCFGW_2 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f
+data.set 0x00150618 %long 0x0000105f //VALUE_PCFGW_3 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f
+//port read region set
+data.set 0x00150494 %long 0x0020000e //VALUE_PCFGQOS0_0 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x00150544 %long 0x0020000e //VALUE_PCFGQOS0_1 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001505f4 %long 0x0020000e //VALUE_PCFGQOS0_2 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001506a4 %long 0x0020000e //VALUE_PCFGQOS0_3 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+//port write region set
+data.set 0x0015049c %long 0x00000000 //VALUE_PCFGWQOS0_0 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x0015054c %long 0x00000000 //VALUE_PCFGWQOS0_1 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001505fc %long 0x00000000 //VALUE_PCFGWQOS0_2 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001506ac %long 0x00000000 //VALUE_PCFGWQOS0_3 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+//vpr timeout, region2 is red queue
+data.set 0x00150498 %long 0x00000000 //VALUE_PCFGQOS1_0 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x00150548 %long 0x00000000 //VALUE_PCFGQOS1_1 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001505f8 %long 0x00000000 //VALUE_PCFGQOS1_2 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001506a8 %long 0x00000000 //VALUE_PCFGQOS1_3 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+//vpw timeout
+data.set 0x001504a0 %long 0x00000000 //VALUE_PCFGWQOS1_0 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150550 %long 0x00000000 //VALUE_PCFGWQOS1_1 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150600 %long 0x00000000 //VALUE_PCFGWQOS1_2 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x001506b0 %long 0x00000000 //VALUE_PCFGWQOS1_3 / wqos_map_timeout:RW:0:11:=0x0
+//in CAM set
+data.set 0x0015025c %long 0x0f000001 //VALUE_PERFHPR1 / hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1
+data.set 0x00150264 %long 0x0f00007f //VALUE_PERFLPR1 / lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f
+data.set 0x0015026c %long 0x0f00007f //VALUE_PERFWR1 / w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f
+data.set 0x00150274 %long 0x00000000 //VALUE_PERFVPR1 / vpr_timeout_range:RW:0:11:=0x0
+data.set 0x00150278 %long 0x00000000 //VALUE_PERFVPW1 / vpw_timeout_range:RW:0:11:=0x0
+//port extern static priority
+//data.set 0x0013d034 %long 0xf0f00000 //port0,1 rqos=0(LPR); port2,3 rqos=F(HPR)
+//wait all register configer done in hardware
+Wait 0.01s
+
+//***********************************************************
+//ctroller and inno phy registers configer done
+//***********************************************************
+data.set 0x01306100 %long 0x0affffc0 //release ddr ctl(bit11) and axi_sn reset(bit6-9) and phy reset(bit12) //ÉèÖÃϵͳ¼Ä´æÆ÷Öµ
+Wait 0.01s
+
+//sw config done
+data.set 0x00150320 %long 0x00000000 //SWCTL // sw_done:RW:0:1:=0x0
+//check phy auto init done, wait 0x00150324 bit0 =0
+Wait 0.01s
+
+//power on PHY PLL
+data.set 0x001543b4 %long 0x00000018 //PHYREGED,PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pll_pd_en:RW:1:1:=0x0, fbdiv[8]:RW:0:1:=0x0
+//wait PHY PLL lock,PHYREGF8[0]Pll lock indicate signal
+
+Wait 0.01s
+
+//PHY DLL init start, fall edge trigger
+data.set 0x0015417c %long 0x0000000a //PHYREG5F, PHY init start:5:1:=0x1
+//wait dll lock, phy init done, PHYREGF8[1]Phy init complete signal
+Wait 0.01s
+
+//enable controller dfi_init_complete_en to start sdram init, then will send dram init cmd
+data.set 0x001501b0 %long 0x00000001 //DFIMISC // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x1 ÊÇ·ñÈ¥µô£¬»òÕ߶ÔÓ¦ÐÞ¸Ä
+//check controller status is sdram init done,wait 0x00150004 bit0-2 !=0
+Wait 0.01s
+data.set 0x001501b0 %long 0x00000000 //dfimisc[0] phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+
+//phy DQS gate training start
+data.set 0x00154008 %long 0x00000001 //PHYREG02,bit0:DQS gating calibration control=1, bit1:DQS gating bypass mode select=0
+//wait training done
+Wait 0.1s
+//phy DQS gate training stop
+data.set 0x00154008 %long 0x00000000 //PHYREG02,bit0:DQS gating calibration control=0, bit1:DQS gating bypass mode select=0
+
+//enable port_n
+data.set 0x00150490 %long 0x00000001 //VALUE_PCTRL_0 / port_en:RW:0:1:=0x1
+data.set 0x00150540 %long 0x00000001 //VALUE_PCTRL_1 / port_en:RW:0:1:=0x1
+data.set 0x001505f0 %long 0x00000001 //VALUE_PCTRL_2 / port_en:RW:0:1:=0x1
+data.set 0x001506a0 %long 0x00000001 //VALUE_PCTRL_3 / port_en:RW:0:1:=0x1
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_312m.cmm b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_312m.cmm
new file mode 100755
index 0000000..ae4de4d
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_312m.cmm
@@ -0,0 +1,210 @@
+// ********************************************************************
+//* ZX297521 Project uMCTL2 DDR controller parameter configuration
+//* uMCTL2 Rev.: 2.50a
+//* Author: Chen Jianhong
+//* Department: IP design
+//* Option: Memory Type = LPDDR2
+//* Option: Memory Frequency(MHz) = 312
+//* Option: Memory Space(Gb) = 1
+//* Option: DRAM drive impedance(Ohm) = 40
+// ********************************************************************
+
+//-------------------below is ddr setting--------------------------
+
+//data.set 0x01306100 %long 0xffffe000 //ddr all reset enable bit6-12=0
+data.set 0x01306100 %long 0x0affe000 //ddr all reset enable bit6-12=0
+Wait 0.01s
+data.set 0x01306100 %long 0x0affe400 //release ddr apb(bit10)
+Wait 0.01s
+
+//DDR top clock select top clk 156M, bit0-1, 0=156, 1=200, 2=104, 3=78
+//0: top clk=156M, ddr use mission mode , dram io clk=312M
+//1: top clk=200M, ddr use mission mode , dram io clk=400M
+//2: top clk=104M, ddr use mission mode , dram io clk=208M
+//3: top clk=78M, ddr use mission mode , dram io clk=156M
+data.set 0x01306050 %long 0x00000000 //·ÖƵÉèÖ㬶ÔÓ¦ÐèÒªÐÞ¸ÄÂð
+
+//phy register init
+data.set 0x00154004 %long 0x00000007 //VALUE_PHYREG01 / Reserved:RW:2:6:=0x1, PHY_MODE:RW:0:2:=0x2(LPDDR2:0x3,LPDDR3:0x2)
+data.set 0x0015402c %long 0x00000080 //VALUE_PHYREG0B / RL:RW:4:4:=0x8
+data.set 0x00154030 %long 0x00000004 //VALUE_PHYREG0C / WL:RW:0:4:=0x4
+
+data.set 0x001543b0 %long 0x00000010 //VALUE_PHYREGEC / fbdiv[7:0]=0x10
+data.set 0x001543b4 %long 0x0000001a //VALUE_PHYREGED / PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pllpd:RW:1:1:=0x1, fbdiv[8]:RW:0:1:=0x0
+data.set 0x001543b8 %long 0x00000022 //VALUE_PHYREGEE / prediv[4:0]:RW:0:5:=0x2,postdiv[2:0]:RW:5:3:=0x1
+
+//Internal VREF generation(defualt)
+data.set 0x0015428c %long 0x00000030 //VALUE_PHYREGA3 / Channel A/B hith 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+data.set 0x001542b8 %long 0x00000030 //VALUE_PHYREGAE / Channel A/B low 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+
+//Drive strength(defualt)
+data.set 0x00154044 %long 0x0000000a //VALUE_PHYREG11 / CMD drive strength: cmd_nrcomp[4:0]:RW:0:5:=0xa
+data.set 0x00154058 %long 0x0000000a //VALUE_PHYREG16 / CK drive strength: ck_nrcomp [4:0]:RW:0:5:=0xa
+data.set 0x00154064 %long 0x0000000a //VALUE_PHYREG19 / CK pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154068 %long 0x0000000a //VALUE_PHYREG1A / CMD pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154080 %long 0x0000000a //VALUE_PHYREG20 / A_DQ0~A_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154084 %long 0x0000000a //VALUE_PHYREG21 / A_DQ0~A_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x001540b8 %long 0x0000008a //VALUE_PHYREG2E / A_DQ0~A_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540bc %long 0x0000008a //VALUE_PHYREG2F / A_DQ0~A_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540c0 %long 0x0000008a //VALUE_PHYREG30 / A_DQ8~A_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540c4 %long 0x0000008a //VALUE_PHYREG31 / A_DQ8~A_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540f8 %long 0x0000000a //VALUE_PHYREG3E / A_DQ8~A_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x001540fc %long 0x0000000a //VALUE_PHYREG3F / A_DQ8~A_DQ15 pull_up ODT:RW:0:5:=0xa
+
+data.set 0x00154100 %long 0x0000000a //VALUE_PHYREG40 / B_DQ0~B_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154104 %long 0x0000000a //VALUE_PHYREG41 / B_DQ0~B_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x00154138 %long 0x0000008a //VALUE_PHYREG4E / B_DQ0~B_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x0015413c %long 0x0000008a //VALUE_PHYREG4F / B_DQ0~B_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+
+data.set 0x00154140 %long 0x0000008a //VALUE_PHYREG50 / B_DQ8~B_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x00154144 %long 0x0000008a //VALUE_PHYREG51 / B_DQ8~B_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x00154178 %long 0x0000000a //VALUE_PHYREG5E / B_DQ8~B_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x0015417c %long 0x0000002a //VALUE_PHYREG5F / B_DQ8~B_DQ15 pull_up ODT:RW:0:5:=0xa
+
+//controller register init
+data.set 0x00150000 %long 0x01040004 //VALUE_MSTR / device_config:RW:30:2:=0x0 frequency_mode:RW:29:1:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 lpddr4:RW:5:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0
+data.set 0x00150010 %long 0x00000030 //VALUE_MRCTRL0 / mr_wr:RW:31:1:=0x0 mr_addr:RW:12:4:=0x0 mr_rank:RW:4:4:=0x3 sw_init_int:RW:3:1:=0x0 pda_en:RW:2:1:=0x0 mpr_en:RW:1:1:=0x0 mr_type:RW:0:1:=0x0
+data.set 0x00150014 %long 0x00000000 //VALUE_MRCTRL1 /mr_data:RW:0:16:=0x0
+data.set 0x00150020 %long 0x00000000 //VALUE_DERATEEN /rc_derate_value:RW:8:2:=0x0 derate_byte:RW:4:4:=0x0 derate_value:RW:1:1:=0x0 derate_enable:RW:0:1:=0x0
+data.set 0x00150024 %long 0x00800000 //VALUE_DERATEINT /mr4_read_interval:RW:0:32:=0x800000
+
+data.set 0x00150030 %long 0x00000000 //VALUE_PWRCTL / stay_in_selfref:RW:6:1:=0x0 selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+data.set 0x00150034 %long 0x00052002 //VALUE_PWRTMG / selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2
+data.set 0x00150038 %long 0x00040003 //VALUE_HWLPCTL / hw_lp_idle_x32:RW:16:12:=0x4 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1
+data.set 0x00150050 %long 0x00210000 //VALUE_RFSHCTL0 / refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0
+data.set 0x00150054 %long 0x00000000 //VALUE_RFSHCTL1 / refresh_timer1_start_value_x32:RW:16:12:=0x0 refresh_timer0_start_value_x32:RW:0:12:=0x0
+data.set 0x00150058 %long 0x00000000 //VALUE_RFSHCTL2 / refresh_timer3_start_value_x32:RW:16:12:=0x0 refresh_timer2_start_value_x32:RW:0:12:=0x0
+data.set 0x00150060 %long 0x00000000 //VALUE_RFSHCTL3 / refresh_mode:RW:4:3:=0x0 refresh_update_level:RW:1:1:=0x0 dis_auto_refresh:RW:0:1:=0x0
+data.set 0x00150064 %long 0x00260014 //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x26 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0x14
+data.set 0x001500d0 %long 0x001f0001 //VALUE_INIT0 / skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x1f pre_cke_x1024:RW:0:11:=0x1
+data.set 0x001500d4 %long 0x00000000 //VALUE_INIT1 / dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0
+data.set 0x001500d8 %long 0x00000405 //VALUE_INIT2 / idle_after_reset_x32:RW:8:8:=0x4 min_stable_clock_x1:RW:0:4:=0x5
+//MR2=RL/WL£¬1£ºRL3/WL1£¬2£ºRL4/WL2£¬3£ºRL:5/WL2£¬4£ºRL6/WL3:£¬5£ºRL7/WL4£¬6£ºRL8/WL4
+data.set 0x001500dc %long 0x00630006 //VALUE_INIT3 / mr:RW:16:16:=0x63 emr:RW:0:16:=0x6
+//bit16-31£¬LPDDR2 MR3 value£¬Æ÷¼þDSĬÈÏÊÇ40ohm£¬£¨1=34.3£¬2=40,3=48,4=60,6=80£©
+data.set 0x001500e0 %long 0x00020000 //VALUE_INIT4 / emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0
+data.set 0x001500e4 %long 0x00050002 //VALUE_INIT5 / dev_zqinit_x32:RW:16:8:=0x5 max_auto_init_x1024:RW:0:10:=0x2
+data.set 0x001500f4 %long 0x0000066f //VALUE_RANKCTL / diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf
+data.set 0x00150100 %long 0x06080a07 //VALUE_DRAMTMG0 / wr2pre:RW:24:6:=0x6 t_faw:RW:16:6:=0x8 t_ras_max:RW:8:7:=0xa t_ras_min:RW:0:6:=0x7
+data.set 0x00150104 %long 0x0002020a //VALUE_DRAMTMG1 / t_xp:RW:16:5:=0x2 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0x9
+//RL=bit16-21£¬1£ºRL=2£¬2£ºRL=4£¬3£ºRL=6£¬4£ºR=8£¬WL=bit24-29£¬1£ºWL=2£¬2£ºWL=4
+//ÕâÀïµ¼ÖÂMR2µÄÅäÖã¨0x012160dc£©²»ÄÜÑ¡Ôñº¬ÓÐÆæÊýµÄÖµ?
+data.set 0x00150108 %long 0x02040606 //VALUE_DRAMTMG2 / write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:6:=0x6 wr2rd:RW:0:6:=0x6
+data.set 0x0015010c %long 0x00501000 //VALUE_DRAMTMG3 / t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0
+data.set 0x00150110 %long 0x03010204 //VALUE_DRAMTMG4 / t_rcd:RW:24:5:=0x3 t_ccd:RW:16:4:=0x1 t_rrd:RW:8:4:=0x2 t_rp:RW:0:5:=0x4
+data.set 0x00150114 %long 0x01010303 //VALUE_DRAMTMG5 / t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x3 t_cke:RW:0:4:=0x3
+data.set 0x00150118 %long 0x02020003 //VALUE_DRAMTMG6 / t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x3
+data.set 0x0015011c %long 0x00000202 //VALUE_DRAMTMG7 / t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2
+data.set 0x00150138 %long 0x00000016 //VALUE_DRAMTMG14 / t_xsr:RW:0:12:=0x16
+//bit30=1 Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit £¬7520×ʼÅäÖÃΪ0£¬µ¼ÖÂ×Ô¶¯×Ôˢй¦ÄÜÍ˳öʱÑÓʱºÜ´ó£¬sdio¶ÁÊý¾Ý³ö´í
+data.set 0x00150180 %long 0x4039000f //VALUE_ZQCTL0 / dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x1 zq_resistor_shared:RW:29:1:=0x0 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x39 t_zq_short_nop:RW:0:10:=0xf
+data.set 0x00150184 %long 0x00800100 //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0x8 t_zq_short_interval_x1024:RW:0:20:=0x100
+data.set 0x00150188 %long 0x00000000 //VALUE_ZQCTL2 / zq_reset:RW:0:1:=0x0
+//dfi_t_rddata_en=3,֮ǰ7520ÉÏÉè³É2»áµ¼Ö¶Ámr¶Á´í
+data.set 0x00150190 %long 0x04030001 //VALUE_DFITMG0 / dfi_t_ctrl_delay:RW:24:5:=0x4 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x3 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x0 dfi_tphy_wrlat:RW:0:6:=0x1
+data.set 0x00150194 %long 0x00020404 //VALUE_DFITMG1 / dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x2 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4
+data.set 0x00150198 %long 0x09001111 //VALUE_DFILPCFG0 / dfi_tlp_resp:RW:24:4:=0x9 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x1 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x1 dfi_lp_en_pd:RW:0:1:=0x1
+data.set 0x001501a0 %long 0x80400003 //VALUE_DFIUPD0 / dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3
+data.set 0x001501a4 %long 0x00000000 //VALUE_DFIUPD1 / dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0
+data.set 0x001501a8 %long 0x80100010 //VALUE_DFIUPD2 / dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10
+data.set 0x001501b0 %long 0x00000000 //VALUE_DFIMISC / dfi_data_cs_polarity:RW:2:1:=0x0 phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+data.set 0x00150200 %long 0x0000001f //VALUE_ADDRMAP0 / addrmap_dch_bit0:RW:16:5:=0x0 addrmap_cs_bit1:RW:8:5:=0x0 addrmap_cs_bit0:RW:0:5:=0x1f
+data.set 0x00150204 %long 0x00070707 //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+data.set 0x00150208 %long 0x00000000 //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+data.set 0x0015020c %long 0x0f000000 //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+data.set 0x00150210 %long 0x00000f0f //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+data.set 0x00150214 %long 0x06060606 //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+data.set 0x00150218 %long 0x0f0f0f06 //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
+data.set 0x00150240 %long 0x04000400 //VALUE_ODTCFG / wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0
+data.set 0x00150244 %long 0x00000000 //VALUE_ODTMAP / rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0
+data.set 0x00150250 %long 0x00001805 //VALUE_SCHED / rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x18 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1
+data.set 0x00150254 %long 0x00000000 //VALUE_SCHED1 / pageclose_timer:RW:0:8:=0x0
+
+data.set 0x00150300 %long 0x00000000 //VALUE_DBG0 / dis_collision_page_opt:RW:4:1:=0x0 dis_act_bypass:RW:2:1:=0x0 dis_rd_bypass:RW:1:1:=0x0 dis_wc:RW:0:1:=0x0
+data.set 0x00150304 %long 0x00000000 //VALUE_DBG1 / dis_dq:RW:1:1:=0x0 dis_hig:RW:0:1:=0x0
+data.set 0x0015030c %long 0x00000000 //VALUE_DBGCMD / ctrlupd:RWSC:5:1:=0x0 zq_calib_short:RWSC:4:1:=0x0 rank3_refresh:RWSC:3:1:=0x0 rank2_refresh:RWSC:2:1:=0x0 rank1_refresh:RWSC:1:1:=0x0 rank0_refresh:RWSC:0:1:=0x0
+
+data.set 0x00150400 %long 0x00000000 //VALUE_PCCFG / bl_exp_mode:RW:8:1:=0x0 pagematch_limit:RW:1:1:=0x0 go2critical_en:RW:0:1:=0x0
+
+//ddr_prority_config
+//port read static priority bit0-9, bit0-4 timeout, bit5-9 prority
+data.set 0x00150404 %long 0x000013ff //VALUE_PCFGR_0 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b4 %long 0x00001020 //VALUE_PCFGR_1 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20
+data.set 0x00150564 %long 0x00001000 //VALUE_PCFGR_2 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0
+data.set 0x00150614 %long 0x00001004 //VALUE_PCFGR_3 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4
+//port write static priority bit0-9
+data.set 0x00150408 %long 0x000013ff //VALUE_PCFGW_0 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b8 %long 0x000010ff //VALUE_PCFGW_1 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff
+data.set 0x00150568 %long 0x0000103f //VALUE_PCFGW_2 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f
+data.set 0x00150618 %long 0x0000105f //VALUE_PCFGW_3 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f
+//port read region set
+data.set 0x00150494 %long 0x0020000e //VALUE_PCFGQOS0_0 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x00150544 %long 0x0020000e //VALUE_PCFGQOS0_1 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001505f4 %long 0x0020000e //VALUE_PCFGQOS0_2 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001506a4 %long 0x0020000e //VALUE_PCFGQOS0_3 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+//port write region set
+data.set 0x0015049c %long 0x00000000 //VALUE_PCFGWQOS0_0 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x0015054c %long 0x00000000 //VALUE_PCFGWQOS0_1 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001505fc %long 0x00000000 //VALUE_PCFGWQOS0_2 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001506ac %long 0x00000000 //VALUE_PCFGWQOS0_3 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+//vpr timeout, region2 is red queue
+data.set 0x00150498 %long 0x00000000 //VALUE_PCFGQOS1_0 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x00150548 %long 0x00000000 //VALUE_PCFGQOS1_1 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001505f8 %long 0x00000000 //VALUE_PCFGQOS1_2 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001506a8 %long 0x00000000 //VALUE_PCFGQOS1_3 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+//vpw timeout
+data.set 0x001504a0 %long 0x00000000 //VALUE_PCFGWQOS1_0 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150550 %long 0x00000000 //VALUE_PCFGWQOS1_1 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150600 %long 0x00000000 //VALUE_PCFGWQOS1_2 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x001506b0 %long 0x00000000 //VALUE_PCFGWQOS1_3 / wqos_map_timeout:RW:0:11:=0x0
+//in CAM set
+data.set 0x0015025c %long 0x0f000001 //VALUE_PERFHPR1 / hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1
+data.set 0x00150264 %long 0x0f00007f //VALUE_PERFLPR1 / lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f
+data.set 0x0015026c %long 0x0f00007f //VALUE_PERFWR1 / w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f
+data.set 0x00150274 %long 0x00000000 //VALUE_PERFVPR1 / vpr_timeout_range:RW:0:11:=0x0
+data.set 0x00150278 %long 0x00000000 //VALUE_PERFVPW1 / vpw_timeout_range:RW:0:11:=0x0
+//port extern static priority
+//data.set 0x0013d034 %long 0xf0f00000 //port0,1 rqos=0(LPR); port2,3 rqos=F(HPR)
+//wait all register configer done in hardware
+Wait 0.01s
+
+//***********************************************************
+//ctroller and inno phy registers configer done
+//***********************************************************
+data.set 0x01306100 %long 0x0affffc0 //release ddr ctl(bit11) and axi_sn reset(bit6-9) and phy reset(bit12) //ÉèÖÃϵͳ¼Ä´æÆ÷Öµ
+Wait 0.01s
+
+//sw config done
+data.set 0x00150320 %long 0x00000000 //SWCTL // sw_done:RW:0:1:=0x0
+//check phy auto init done, wait 0x00150324 bit0 =0
+Wait 0.01s
+
+//power on PHY PLL
+data.set 0x001543b4 %long 0x00000018 //PHYREGED,PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pll_pd_en:RW:1:1:=0x0, fbdiv[8]:RW:0:1:=0x0
+//wait PHY PLL lock,PHYREGF8[0]Pll lock indicate signal
+
+Wait 0.01s
+
+//PHY DLL init start, fall edge trigger
+data.set 0x0015417c %long 0x0000000a //PHYREG5F, PHY init start:5:1:=0x1
+//wait dll lock, phy init done, PHYREGF8[1]Phy init complete signal
+Wait 0.01s
+
+//enable controller dfi_init_complete_en to start sdram init, then will send dram init cmd
+data.set 0x001501b0 %long 0x00000001 //DFIMISC // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x1 ÊÇ·ñÈ¥µô£¬»òÕ߶ÔÓ¦ÐÞ¸Ä
+//check controller status is sdram init done,wait 0x00150004 bit0-2 !=0
+Wait 0.01s
+data.set 0x001501b0 %long 0x00000000 //dfimisc[0] phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+
+//phy DQS gate training start
+data.set 0x00154008 %long 0x00000001 //PHYREG02,bit0:DQS gating calibration control=1, bit1:DQS gating bypass mode select=0
+//wait training done
+Wait 0.1s
+//phy DQS gate training stop
+data.set 0x00154008 %long 0x00000000 //PHYREG02,bit0:DQS gating calibration control=0, bit1:DQS gating bypass mode select=0
+
+//enable port_n
+data.set 0x00150490 %long 0x00000001 //VALUE_PCTRL_0 / port_en:RW:0:1:=0x1
+data.set 0x00150540 %long 0x00000001 //VALUE_PCTRL_1 / port_en:RW:0:1:=0x1
+data.set 0x001505f0 %long 0x00000001 //VALUE_PCTRL_2 / port_en:RW:0:1:=0x1
+data.set 0x001506a0 %long 0x00000001 //VALUE_PCTRL_3 / port_en:RW:0:1:=0x1
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_400m.cmm b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_400m.cmm
new file mode 100755
index 0000000..2e770ca
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/ddr_init_400m.cmm
@@ -0,0 +1,210 @@
+// ********************************************************************
+//* ZX297521 Project uMCTL2 DDR controller parameter configuration
+//* uMCTL2 Rev.: 2.50a
+//* Author: Chen Jianhong
+//* Department: IP design
+//* Option: Memory Type = LPDDR2
+//* Option: Memory Frequency(MHz) = 400
+//* Option: Memory Space(Gb) = 1
+//* Option: DRAM drive impedance(Ohm) = 40
+// ********************************************************************
+
+//-------------------below is ddr setting--------------------------
+
+//data.set 0x01306100 %long 0xffffe000 //ddr all reset enable bit6-12=0
+data.set 0x01306100 %long 0x0affe000 //ddr all reset enable bit6-12=0
+Wait 0.01s
+data.set 0x01306100 %long 0x0affe400 //release ddr apb(bit10)
+Wait 0.01s
+
+//DDR top clock select top clk 156M, bit0-1, 0=156, 1=200, 2=104, 3=78
+//0: top clk=156M, ddr use mission mode , dram io clk=312M
+//1: top clk=200M, ddr use mission mode , dram io clk=400M
+//2: top clk=104M, ddr use mission mode , dram io clk=208M
+//3: top clk=78M, ddr use mission mode , dram io clk=156M
+data.set 0x01306050 %long 0x00000001 //·ÖƵÉèÖ㬶ÔÓ¦ÐèÒªÐÞ¸ÄÂð
+
+//phy register init
+data.set 0x00154004 %long 0x00000007 //VALUE_PHYREG01 / Reserved:RW:2:6:=0x1, PHY_MODE:RW:0:2:=0x2(LPDDR2:0x3,LPDDR3:0x2)
+data.set 0x0015402c %long 0x00000080 //VALUE_PHYREG0B / RL:RW:4:4:=0x8
+data.set 0x00154030 %long 0x00000004 //VALUE_PHYREG0C / WL:RW:0:4:=0x4
+
+data.set 0x001543b0 %long 0x00000010 //VALUE_PHYREGEC / fbdiv[7:0]=0x10
+data.set 0x001543b4 %long 0x0000001a //VALUE_PHYREGED / PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pllpd:RW:1:1:=0x1, fbdiv[8]:RW:0:1:=0x0
+data.set 0x001543b8 %long 0x00000022 //VALUE_PHYREGEE / prediv[4:0]:RW:0:5:=0x2,postdiv[2:0]:RW:5:3:=0x1
+
+//Internal VREF generation(defualt)
+data.set 0x0015428c %long 0x00000030 //VALUE_PHYREGA3 / Channel A/B hith 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+data.set 0x001542b8 %long 0x00000030 //VALUE_PHYREGAE / Channel A/B low 8bits: vref_sel:RW:5:1:=0x1,vref_value[4:0]:RW:0:5:=0x10
+
+//Drive strength(defualt)
+data.set 0x00154044 %long 0x0000000a //VALUE_PHYREG11 / CMD drive strength: cmd_nrcomp[4:0]:RW:0:5:=0xa
+data.set 0x00154058 %long 0x0000000a //VALUE_PHYREG16 / CK drive strength: ck_nrcomp [4:0]:RW:0:5:=0xa
+data.set 0x00154064 %long 0x0000000a //VALUE_PHYREG19 / CK pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154068 %long 0x0000000a //VALUE_PHYREG1A / CMD pull_up drive strength(DS):RW:0:5:=0xa
+data.set 0x00154080 %long 0x0000000a //VALUE_PHYREG20 / A_DQ0~A_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154084 %long 0x0000000a //VALUE_PHYREG21 / A_DQ0~A_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x001540b8 %long 0x0000008a //VALUE_PHYREG2E / A_DQ0~A_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540bc %long 0x0000008a //VALUE_PHYREG2F / A_DQ0~A_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540c0 %long 0x0000008a //VALUE_PHYREG30 / A_DQ8~A_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x001540c4 %long 0x0000008a //VALUE_PHYREG31 / A_DQ8~A_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x001540f8 %long 0x0000000a //VALUE_PHYREG3E / A_DQ8~A_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x001540fc %long 0x0000000a //VALUE_PHYREG3F / A_DQ8~A_DQ15 pull_up ODT:RW:0:5:=0xa
+
+data.set 0x00154100 %long 0x0000000a //VALUE_PHYREG40 / B_DQ0~B_DQ7 pull_down DS :RW:0:5:=0xa
+data.set 0x00154104 %long 0x0000000a //VALUE_PHYREG41 / B_DQ0~B_DQ7 pull_down ODT:RW:0:5:=0xa
+data.set 0x00154138 %long 0x0000008a //VALUE_PHYREG4E / B_DQ0~B_DQ7 pull_up DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x0015413c %long 0x0000008a //VALUE_PHYREG4F / B_DQ0~B_DQ7 pull_up ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+
+data.set 0x00154140 %long 0x0000008a //VALUE_PHYREG50 / B_DQ8~B_DQ15 pull_down DS :RW:0:5:=0xa, falling edge slew rate:RW:5:3:=0x4
+data.set 0x00154144 %long 0x0000008a //VALUE_PHYREG51 / B_DQ8~B_DQ15 pull_down ODT:RW:0:5:=0xa, rising edge slew rate:RW:5:3:=0x4
+data.set 0x00154178 %long 0x0000000a //VALUE_PHYREG5E / B_DQ8~B_DQ15 pull_up DS :RW:0:5:=0xa
+data.set 0x0015417c %long 0x0000002a //VALUE_PHYREG5F / B_DQ8~B_DQ15 pull_up ODT:RW:0:5:=0xa
+
+//controller register init
+data.set 0x00150000 %long 0x01040004 //VALUE_MSTR / device_config:RW:30:2:=0x0 frequency_mode:RW:29:1:=0x0 active_ranks:RW:24:4:=0x3 burst_rdwr:RW:16:4:=0x4 dll_off_mode:RW:15:1:=0x0 data_bus_width:RW:12:2:=0x0 geardown_mode:RW:11:1:=0x0 en_2t_timing_mode:RW:10:1:=0x0 burstchop:RW:9:1:=0x0 burst_mode:RW:8:1:=0x0 lpddr4:RW:5:1:=0x0 ddr4:RW:4:1:=0x0 lpddr3:RW:3:1:=0x0 lpddr2:RW:2:1:=0x1 mobile:RW:1:1:=0x0 ddr3:RW:0:1:=0x0
+data.set 0x00150010 %long 0x00000030 //VALUE_MRCTRL0 / mr_wr:RW:31:1:=0x0 mr_addr:RW:12:4:=0x0 mr_rank:RW:4:4:=0x3 sw_init_int:RW:3:1:=0x0 pda_en:RW:2:1:=0x0 mpr_en:RW:1:1:=0x0 mr_type:RW:0:1:=0x0
+data.set 0x00150014 %long 0x00000000 //VALUE_MRCTRL1 /mr_data:RW:0:16:=0x0
+data.set 0x00150020 %long 0x00000000 //VALUE_DERATEEN /rc_derate_value:RW:8:2:=0x0 derate_byte:RW:4:4:=0x0 derate_value:RW:1:1:=0x0 derate_enable:RW:0:1:=0x0
+data.set 0x00150024 %long 0x00800000 //VALUE_DERATEINT /mr4_read_interval:RW:0:32:=0x800000
+
+data.set 0x00150030 %long 0x00000000 //VALUE_PWRCTL / stay_in_selfref:RW:6:1:=0x0 selfref_sw:RW:5:1:=0x0 mpsm_en:RW:4:1:=0x0 en_dfi_dram_clk_disable:RW:3:1:=0x0 deeppowerdown_en:RW:2:1:=0x0 powerdown_en:RW:1:1:=0x1 selfref_en:RW:0:1:=0x1
+data.set 0x00150034 %long 0x00052002 //VALUE_PWRTMG / selfref_to_x32:RW:16:8:=0x5 deeppowerdown_to_x1024:RW:8:8:=0x20 powerdown_to_x32:RW:0:5:=0x2
+data.set 0x00150038 %long 0x00040003 //VALUE_HWLPCTL / hw_lp_idle_x32:RW:16:12:=0x4 hw_lp_exit_idle_en:RW:1:1:=0x1 hw_lp_en:RW:0:1:=0x1
+data.set 0x00150050 %long 0x00210000 //VALUE_RFSHCTL0 / refresh_margin:RW:20:4:=0x2 refresh_to_x32:RW:12:5:=0x10 refresh_burst:RW:4:5:=0x0 per_bank_refresh:RW:2:1:=0x0
+data.set 0x00150054 %long 0x00000000 //VALUE_RFSHCTL1 / refresh_timer1_start_value_x32:RW:16:12:=0x0 refresh_timer0_start_value_x32:RW:0:12:=0x0
+data.set 0x00150058 %long 0x00000000 //VALUE_RFSHCTL2 / refresh_timer3_start_value_x32:RW:16:12:=0x0 refresh_timer2_start_value_x32:RW:0:12:=0x0
+data.set 0x00150060 %long 0x00000000 //VALUE_RFSHCTL3 / refresh_mode:RW:4:3:=0x0 refresh_update_level:RW:1:1:=0x0 dis_auto_refresh:RW:0:1:=0x0
+data.set 0x00150064 %long 0x0030001a //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x30 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0x1a
+data.set 0x001500d0 %long 0x00280001 //VALUE_INIT0 / skip_dram_init:RW:31:2:=0x0 post_cke_x1024:RW:16:10:=0x28 pre_cke_x1024:RW:0:11:=0x1
+data.set 0x001500d4 %long 0x00000000 //VALUE_INIT1 / dram_rstn_x1024:RW:16:8:=0x0 final_wait_x32:RW:8:7:=0x0 pre_ocd_x32:RW:0:4:=0x0
+data.set 0x001500d8 %long 0x00000605 //VALUE_INIT2 / idle_after_reset_x32:RW:8:8:=0x6 min_stable_clock_x1:RW:0:4:=0x5
+//MR2=RL/WL£¬1£ºRL3/WL1£¬2£ºRL4/WL2£¬3£ºRL:5/WL2£¬4£ºRL6/WL3:£¬5£ºRL7/WL4£¬6£ºRL8/WL4
+data.set 0x001500dc %long 0x00830006 //VALUE_INIT3 / mr:RW:16:16:=0x83 emr:RW:0:16:=0x6
+//bit16-31£¬LPDDR2 MR3 value£¬Æ÷¼þDSĬÈÏÊÇ40ohm£¬£¨1=34.3£¬2=40,3=48,4=60,6=80£©
+data.set 0x001500e0 %long 0x00020000 //VALUE_INIT4 / emr2:RW:16:16:=0x2 emr3:RW:0:16:=0x0
+data.set 0x001500e4 %long 0x00070002 //VALUE_INIT5 / dev_zqinit_x32:RW:16:8:=0x7 max_auto_init_x1024:RW:0:10:=0x2
+data.set 0x001500f4 %long 0x0000066f //VALUE_RANKCTL / diff_rank_wr_gap:RW:8:4:=0x6 diff_rank_rd_gap:RW:4:4:=0x6 max_rank_rd:RW:0:4:=0xf
+data.set 0x00150100 %long 0x070a0d08 //VALUE_DRAMTMG0 / wr2pre:RW:24:6:=0x7 t_faw:RW:16:6:=0xa t_ras_max:RW:8:7:=0xd t_ras_min:RW:0:6:=0x8
+data.set 0x00150104 %long 0x0002020d //VALUE_DRAMTMG1 / t_xp:RW:16:5:=0x2 rd2pre:RW:8:5:=0x2 t_rc:RW:0:6:=0xd
+//RL=bit16-21£¬1£ºRL=2£¬2£ºRL=4£¬3£ºRL=6£¬4£ºR=8£¬WL=bit24-29£¬1£ºWL=2£¬2£ºWL=4
+//ÕâÀïµ¼ÖÂMR2µÄÅäÖã¨0x012160dc£©²»ÄÜÑ¡Ôñº¬ÓÐÆæÊýµÄÖµ?
+data.set 0x00150108 %long 0x02040606 //VALUE_DRAMTMG2 / write_latency:RW:24:6:=0x2 read_latency:RW:16:6:=0x4 rd2wr:RW:8:6:=0x6 wr2rd:RW:0:6:=0x6
+data.set 0x0015010c %long 0x00501000 //VALUE_DRAMTMG3 / t_mrw:RW:20:10:=0x5 t_mrd:RW:12:6:=0x1 t_mod:RW:0:10:=0x0
+data.set 0x00150110 %long 0x04010205 //VALUE_DRAMTMG4 / t_rcd:RW:24:5:=0x4 t_ccd:RW:16:4:=0x1 t_rrd:RW:8:4:=0x2 t_rp:RW:0:5:=0x5
+data.set 0x00150114 %long 0x01010303 //VALUE_DRAMTMG5 / t_cksrx:RW:24:4:=0x1 t_cksre:RW:16:4:=0x1 t_ckesr:RW:8:6:=0x3 t_cke:RW:0:4:=0x3
+data.set 0x00150118 %long 0x02020003 //VALUE_DRAMTMG6 / t_ckdpde:RW:24:4:=0x2 t_ckdpdx:RW:16:4:=0x2 t_ckcsx:RW:0:4:=0x3
+data.set 0x0015011c %long 0x00000202 //VALUE_DRAMTMG7 / t_ckpde:RW:8:4:=0x2 t_ckpdx:RW:0:4:=0x2
+data.set 0x00150138 %long 0x0000001c //VALUE_DRAMTMG14 / t_xsr:RW:0:12:=0x1c
+//bit30=1 Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit £¬7520×ʼÅäÖÃΪ0£¬µ¼ÖÂ×Ô¶¯×Ôˢй¦ÄÜÍ˳öʱÑÓʱºÜ´ó£¬sdio¶ÁÊý¾Ý³ö´í
+data.set 0x00150180 %long 0x40480012 //VALUE_ZQCTL0 / dis_auto_zq:RW:31:1:=0x0 dis_srx_zqcl:RW:30:1:=0x1 zq_resistor_shared:RW:29:1:=0x0 dis_mpsmx_zqcl:RW:28:1:=0x0 t_zq_long_nop:RW:16:10:=0x48 t_zq_short_nop:RW:0:10:=0x12
+data.set 0x00150184 %long 0x00a00100 //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0xa t_zq_short_interval_x1024:RW:0:20:=0x100
+data.set 0x00150188 %long 0x00000000 //VALUE_ZQCTL2 / zq_reset:RW:0:1:=0x0
+//dfi_t_rddata_en=3,֮ǰ7520ÉÏÉè³É2»áµ¼Ö¶Ámr¶Á´í
+data.set 0x00150190 %long 0x04030001 //VALUE_DFITMG0 / dfi_t_ctrl_delay:RW:24:5:=0x4 dfi_rddata_use_sdr:RW:23:1:=0x0 dfi_t_rddata_en:RW:16:6:=0x3 dfi_wrdata_use_sdr:RW:15:1:=0x0 dfi_tphy_wrdata:RW:8:6:=0x0 dfi_tphy_wrlat:RW:0:6:=0x1
+data.set 0x00150194 %long 0x00020404 //VALUE_DFITMG1 / dfi_t_cmd_lat:RW:28:4:=0x0 dfi_t_parin_lat:RW:24:2:=0x0 dfi_t_wrdata_delay:RW:16:5:=0x2 dfi_t_dram_clk_disable:RW:8:4:=0x4 dfi_t_dram_clk_enable:RW:0:4:=0x4
+data.set 0x00150198 %long 0x09001111 //VALUE_DFILPCFG0 / dfi_tlp_resp:RW:24:4:=0x9 dfi_lp_wakeup_dpd:RW:20:4:=0x0 dfi_lp_en_dpd:RW:16:1:=0x0 dfi_lp_wakeup_sr:RW:12:4:=0x1 dfi_lp_en_sr:RW:8:1:=0x1 dfi_lp_wakeup_pd:RW:4:4:=0x1 dfi_lp_en_pd:RW:0:1:=0x1
+data.set 0x001501a0 %long 0x80400003 //VALUE_DFIUPD0 / dis_auto_ctrlupd:RW:31:1:=0x1 dfi_t_ctrlup_max:RW:16:10:=0x40 dfi_t_ctrlup_min:RW:0:10:=0x3
+data.set 0x001501a4 %long 0x00000000 //VALUE_DFIUPD1 / dfi_t_ctrlupd_interval_min_x1024:RW:16:8:=0x0 dfi_t_ctrlupd_interval_max_x1024:RW:0:8:=0x0
+data.set 0x001501a8 %long 0x80100010 //VALUE_DFIUPD2 / dfi_phyupd_en:RW:31:1:=0x1 dfi_phyupd_type1:RW:16:12:=0x10 dfi_phyupd_type0:RW:0:12:=0x10
+data.set 0x001501b0 %long 0x00000000 //VALUE_DFIMISC / dfi_data_cs_polarity:RW:2:1:=0x0 phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+data.set 0x00150200 %long 0x0000001f //VALUE_ADDRMAP0 / addrmap_dch_bit0:RW:16:5:=0x0 addrmap_cs_bit1:RW:8:5:=0x0 addrmap_cs_bit0:RW:0:5:=0x1f
+data.set 0x00150204 %long 0x00070707 //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+data.set 0x00150208 %long 0x00000000 //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+data.set 0x0015020c %long 0x0f000000 //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+data.set 0x00150210 %long 0x00000f0f //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+data.set 0x00150214 %long 0x06060606 //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+data.set 0x00150218 %long 0x0f0f0f06 //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
+data.set 0x00150240 %long 0x04000400 //VALUE_ODTCFG / wr_odt_hold:RW:24:4:=0x4 wr_odt_delay:RW:16:4:=0x0 rd_odt_hold:RW:8:4:=0x4 rd_odt_delay:RW:2:4:=0x0
+data.set 0x00150244 %long 0x00000000 //VALUE_ODTMAP / rank3_rd_odt:RW:28:4:=0x0 rank3_wr_odt:RW:24:4:=0x0 rank2_rd_odt:RW:20:4:=0x0 rank2_wr_odt:RW:16:4:=0x0 rank1_rd_odt:RW:12:4:=0x0 rank1_wr_odt:RW:8:4:=0x0 rank0_rd_odt:RW:4:4:=0x0 rank0_wr_odt:RW:0:4:=0x0
+data.set 0x00150250 %long 0x00001805 //VALUE_SCHED / rdwr_idle_gap:RW:24:7:=0x0 go2critical_hysteresis:RW:16:8:=0x0 lpr_num_entries:RW:8:6:=0x18 pageclose:RW:2:1:=0x1 prefer_write:RW:1:1:=0x0 force_low_pri_n:RW:0:1:=0x1
+data.set 0x00150254 %long 0x00000000 //VALUE_SCHED1 / pageclose_timer:RW:0:8:=0x0
+
+data.set 0x00150300 %long 0x00000000 //VALUE_DBG0 / dis_collision_page_opt:RW:4:1:=0x0 dis_act_bypass:RW:2:1:=0x0 dis_rd_bypass:RW:1:1:=0x0 dis_wc:RW:0:1:=0x0
+data.set 0x00150304 %long 0x00000000 //VALUE_DBG1 / dis_dq:RW:1:1:=0x0 dis_hig:RW:0:1:=0x0
+data.set 0x0015030c %long 0x00000000 //VALUE_DBGCMD / ctrlupd:RWSC:5:1:=0x0 zq_calib_short:RWSC:4:1:=0x0 rank3_refresh:RWSC:3:1:=0x0 rank2_refresh:RWSC:2:1:=0x0 rank1_refresh:RWSC:1:1:=0x0 rank0_refresh:RWSC:0:1:=0x0
+
+data.set 0x00150400 %long 0x00000000 //VALUE_PCCFG / bl_exp_mode:RW:8:1:=0x0 pagematch_limit:RW:1:1:=0x0 go2critical_en:RW:0:1:=0x0
+
+//ddr_prority_config
+//port read static priority bit0-9, bit0-4 timeout, bit5-9 prority
+data.set 0x00150404 %long 0x000013ff //VALUE_PCFGR_0 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b4 %long 0x00001020 //VALUE_PCFGR_1 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x20
+data.set 0x00150564 %long 0x00001000 //VALUE_PCFGR_2 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x0
+data.set 0x00150614 %long 0x00001004 //VALUE_PCFGR_3 / rdwr_ordered_en:RW:16:1:=0x0 rd_port_pagematch_en:RW:14:1:=0x0 rd_port_urgent_en:RW:13:1:=0x0 rd_port_aging_en:RW:12:1:=0x1 read_reorder_bypass_en:RW:11:1:=0x0 rd_port_priority:RW:0:10:=0x4
+//port write static priority bit0-9
+data.set 0x00150408 %long 0x000013ff //VALUE_PCFGW_0 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3ff
+data.set 0x001504b8 %long 0x000010ff //VALUE_PCFGW_1 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0xff
+data.set 0x00150568 %long 0x0000103f //VALUE_PCFGW_2 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x3f
+data.set 0x00150618 %long 0x0000105f //VALUE_PCFGW_3 / wr_port_pagematch_en:RW:14:1:=0x0 wr_port_urgent_en:RW:13:1:=0x0 wr_port_aging_en:RW:12:1:=0x1 wr_port_priority:RW:0:10:=0x5f
+//port read region set
+data.set 0x00150494 %long 0x0020000e //VALUE_PCFGQOS0_0 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x00150544 %long 0x0020000e //VALUE_PCFGQOS0_1 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001505f4 %long 0x0020000e //VALUE_PCFGQOS0_2 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+data.set 0x001506a4 %long 0x0020000e //VALUE_PCFGQOS0_3 / rqos_map_region2:RW:24:2:=0x0 rqos_map_region1:RW:20:2:=0x2 rqos_map_region0:RW:16:2:=0x0 rqos_map_level2:RW:8:4:=0x0 rqos_map_level1:RW:0:4:=0xe
+//port write region set
+data.set 0x0015049c %long 0x00000000 //VALUE_PCFGWQOS0_0 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x0015054c %long 0x00000000 //VALUE_PCFGWQOS0_1 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001505fc %long 0x00000000 //VALUE_PCFGWQOS0_2 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+data.set 0x001506ac %long 0x00000000 //VALUE_PCFGWQOS0_3 / wqos_map_region1:RW:20:2:=0x0 wqos_map_region0:RW:16:2:=0x0 wqos_map_level:RW:0:4:=0x0
+//vpr timeout, region2 is red queue
+data.set 0x00150498 %long 0x00000000 //VALUE_PCFGQOS1_0 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x00150548 %long 0x00000000 //VALUE_PCFGQOS1_1 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001505f8 %long 0x00000000 //VALUE_PCFGQOS1_2 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+data.set 0x001506a8 %long 0x00000000 //VALUE_PCFGQOS1_3 / rqos_map_timeoutr:RW:16:11:=0x0 rqos_map_timeoutb:RW:0:11:=0x0
+//vpw timeout
+data.set 0x001504a0 %long 0x00000000 //VALUE_PCFGWQOS1_0 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150550 %long 0x00000000 //VALUE_PCFGWQOS1_1 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x00150600 %long 0x00000000 //VALUE_PCFGWQOS1_2 / wqos_map_timeout:RW:0:11:=0x0
+data.set 0x001506b0 %long 0x00000000 //VALUE_PCFGWQOS1_3 / wqos_map_timeout:RW:0:11:=0x0
+//in CAM set
+data.set 0x0015025c %long 0x0f000001 //VALUE_PERFHPR1 / hpr_xact_run_length:RW:24:8:=0xf hpr_max_starve:RW:0:16:=0x1
+data.set 0x00150264 %long 0x0f00007f //VALUE_PERFLPR1 / lpr_xact_run_length:RW:24:8:=0xf lpr_max_starve:RW:0:16:=0x7f
+data.set 0x0015026c %long 0x0f00007f //VALUE_PERFWR1 / w_xact_run_length:RW:24:8:=0xf w_max_starve:RW:0:16:=0x7f
+data.set 0x00150274 %long 0x00000000 //VALUE_PERFVPR1 / vpr_timeout_range:RW:0:11:=0x0
+data.set 0x00150278 %long 0x00000000 //VALUE_PERFVPW1 / vpw_timeout_range:RW:0:11:=0x0
+//port extern static priority
+//data.set 0x0013d034 %long 0xf0f00000 //port0,1 rqos=0(LPR); port2,3 rqos=F(HPR)
+//wait all register configer done in hardware
+Wait 0.01s
+
+//***********************************************************
+//ctroller and inno phy registers configer done
+//***********************************************************
+data.set 0x01306100 %long 0x0affffc0 //release ddr ctl(bit11) and axi_sn reset(bit6-9) and phy reset(bit12) //ÉèÖÃϵͳ¼Ä´æÆ÷Öµ
+Wait 0.01s
+
+//sw config done
+data.set 0x00150320 %long 0x00000000 //SWCTL // sw_done:RW:0:1:=0x0
+//check phy auto init done, wait 0x00150324 bit0 =0
+Wait 0.01s
+
+//power on PHY PLL
+data.set 0x001543b4 %long 0x00000018 //PHYREGED,PLLCLKOUTEN:RW:4:1:=0x1,Reserved:RW:2:2:=0x2, pll_pd_en:RW:1:1:=0x0, fbdiv[8]:RW:0:1:=0x0
+//wait PHY PLL lock,PHYREGF8[0]Pll lock indicate signal
+
+Wait 0.01s
+
+//PHY DLL init start, fall edge trigger
+data.set 0x0015417c %long 0x0000000a //PHYREG5F, PHY init start:5:1:=0x1
+//wait dll lock, phy init done, PHYREGF8[1]Phy init complete signal
+Wait 0.01s
+
+//enable controller dfi_init_complete_en to start sdram init, then will send dram init cmd
+data.set 0x001501b0 %long 0x00000001 //DFIMISC // phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x1 ÊÇ·ñÈ¥µô£¬»òÕ߶ÔÓ¦ÐÞ¸Ä
+//check controller status is sdram init done,wait 0x00150004 bit0-2 !=0
+Wait 0.01s
+data.set 0x001501b0 %long 0x00000000 //dfimisc[0] phy_dbi_mode:RW:1:1:=0x0 dfi_init_complete_en:RW:0:1:=0x0
+
+//phy DQS gate training start
+data.set 0x00154008 %long 0x00000001 //PHYREG02,bit0:DQS gating calibration control=1, bit1:DQS gating bypass mode select=0
+//wait training done
+Wait 0.1s
+//phy DQS gate training stop
+data.set 0x00154008 %long 0x00000000 //PHYREG02,bit0:DQS gating calibration control=0, bit1:DQS gating bypass mode select=0
+
+//enable port_n
+data.set 0x00150490 %long 0x00000001 //VALUE_PCTRL_0 / port_en:RW:0:1:=0x1
+data.set 0x00150540 %long 0x00000001 //VALUE_PCTRL_1 / port_en:RW:0:1:=0x1
+data.set 0x001505f0 %long 0x00000001 //VALUE_PCTRL_2 / port_en:RW:0:1:=0x1
+data.set 0x001506a0 %long 0x00000001 //VALUE_PCTRL_3 / port_en:RW:0:1:=0x1
\ No newline at end of file
diff --git a/ap/build/scripts/trace32/zx297520v3/sys/jtag_switch_script.cmm b/ap/build/scripts/trace32/zx297520v3/sys/jtag_switch_script.cmm
new file mode 100755
index 0000000..7f332c9
--- /dev/null
+++ b/ap/build/scripts/trace32/zx297520v3/sys/jtag_switch_script.cmm
@@ -0,0 +1,174 @@
+area.reset
+
+local &jtagnum &jtagfunc
+
+entry &jtagnum &jtagfunc
+
+if state.run()
+(
+ break
+)
+
+;disable mmu
+;&cr=data.long(c15:0x1)
+;tmp=&cr&(~0x1)
+;per.s c15:0x1 %LONG &tmp
+
+; set Jtag pad
+; Jtag0, 0:m0 jtag, 1:r7 jtag, 2:zsp jtag, 3:a53 jtag
+if (&jtagnum==0)
+(
+ if (&jtagfunc==0)
+ (
+ &tmp0=data.long(SD:0x0013c00c)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffc00
+ &tmp1=&tmp1&0xf83fffff
+ data.set SD:0x0013c00c %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==1)
+ (
+ &tmp0=data.long(SD:0x0130300c)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffc00
+ &tmp1=&tmp1|0x7c00000
+ data.set SD:0x0130300c %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==2)
+ (
+ &tmp0=data.long(SD:0x0130300c)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffc00
+ &tmp0=&tmp0|0x155
+ &tmp1=&tmp1|0x7c00000
+ data.set SD:0x0130300c %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==3)
+ (
+ &tmp0=data.long(SD:0x0130300c)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffc00
+ &tmp0=&tmp0|0x2aa
+ &tmp1=&tmp1|0x7c00000
+ data.set SD:0x0130300c %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+)
+
+
+; set Jtag pad
+; SD0/Jtag1, 0:m0 jtag, 1:r7 jtag, 2:zsp jtag, 3:a53 jtag
+if (&jtagnum==1)
+(
+ if (&jtagfunc==0)
+ (
+ &tmp0=data.long(SD:0x0013c008)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xffc00fff
+ &tmp0=&tmp0|0x155000
+ &tmp1=&tmp1&0xffc1ffff
+ data.set SD:0x0013c008 %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==1)
+ (
+ &tmp0=data.long(SD:0x01303008)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x155
+ &tmp1=&tmp1|0x3e0000
+ data.set SD:0x01303008 %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==2)
+ (
+ &tmp0=data.long(SD:0x01303008)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x2aa
+ &tmp1=&tmp1|0x3e0000
+ data.set SD:0x01303008 %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+ if (&jtagfunc==3)
+ (
+ &tmp0=data.long(SD:0x01303008)
+ &tmp1=data.long(SD:0x0013c024)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x3ff
+ &tmp1=&tmp1|0x0x3e0000
+ data.set SD:0x01303008 %LE %LONG &tmp0
+ data.set SD:0x0013c024 %LE %LONG &tmp1
+ )
+)
+
+; set Jtag pad
+; 0:m0 jtag, 1:r7 jtag, 2:zsp jtag, 3:a53 jtag
+if (&jtagnum==2)
+(
+ if (&jtagfunc==0)
+ (
+ &tmp0=data.long(SD:0x0013c010)
+ &tmp1=data.long(SD:0x0013c02c)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x2aa
+ &tmp1=&tmp1&0xffffffe0
+ data.set SD:0x0013c010 %LE %LONG &tmp0
+ data.set SD:0x0013c02c %LE %LONG &tmp1
+ )
+ if (&jtagfunc==1)
+ (
+ &tmp0=data.long(SD:0x01303028)
+ &tmp1=data.long(SD:0x0013c02c)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp1=&tmp1|0x1f
+ data.set SD:0x01303028 %LE %LONG &tmp0
+ data.set SD:0x0013c02c %LE %LONG &tmp1
+ )
+ if (&jtagfunc==2)
+ (
+ &tmp0=data.long(SD:0x01303028)
+ &tmp1=data.long(SD:0x0013c02c)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x155
+ &tmp1=&tmp1|0x1f
+ data.set SD:0x01303028 %LE %LONG &tmp0
+ data.set SD:0x0013c02c %LE %LONG &tmp1
+ )
+ if (&jtagfunc==3)
+ (
+ &tmp0=data.long(SD:0x01303028)
+ &tmp1=data.long(SD:0x0013c02c)
+ &tmp0=&tmp0&0xfffffe00
+ &tmp0=&tmp0|0x2aa
+ &tmp1=&tmp1|0x1f
+ data.set SD:0x01303028 %LE %LONG &tmp0
+ data.set SD:0x0013c02c %LE %LONG &tmp1
+ )
+)
+
+
+ DIALOG
+ (
+ header "Jtag Switch"
+
+ POS 0. 0. 50. 5.
+ BOX ""
+
+ POS 1. 1. 39. 1.
+ TEXT "Çл»³É¹¦£¬ÇëÖØÐÂÑ¡ÔñJtag£¬²¢¼ÓÔؽű¾."
+
+ POS 20. 3. 10. 1.
+ BUTTON "OK" "DIALOG.END"
+ )
+
+
+;exit:
+;restore mmu config
+;per.s c15:0x1 %LONG &cr
+print "Jtag &jtagnum switch to function &jtagfunc"
+
+enddo
\ No newline at end of file