[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/boot/common/src/loader/cpu/m0/Makefile b/boot/common/src/loader/cpu/m0/Makefile
new file mode 100644
index 0000000..778190b
--- /dev/null
+++ b/boot/common/src/loader/cpu/m0/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o
+OBJS = cpu.o clk.o udivmod.o udivmodsi4.o divmod.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+sinclude .depend
+
+#########################################################################
diff --git a/boot/common/src/loader/cpu/m0/clk.c b/boot/common/src/loader/cpu/m0/clk.c
new file mode 100644
index 0000000..19f4967
--- /dev/null
+++ b/boot/common/src/loader/cpu/m0/clk.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2016 ZXIC Inc.
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/top_clock.h>
+#include <board.h>
+
+
+void clk_init (void)
+{
+ __REG(MPLL_CFG0_REG) = 0x08040c11;
+ //__REG(APLL_CFG0_REG) = 0x08081009; /*APLL ,832M*/
+ __REG(UPLL_CFG0_REG) = 0x08347811;
+ __REG(GPLL_CFG0_REG) = 0x08347d29;
+ //__REG(DPLL_CFG0_REG) = 0x0a040c19; /*DPLL,26M*/
+
+ //__REG(PLL_LOCK_CNT0) = 0x03e003e0; /*PLL_LOCK_CNT0*/
+ //__REG(PLL_LOCK_CNT1) = 0x03e003e0; /*PLL_LOCK_CNT1*/
+ //__REG(RMCORE_CLK_CFG_REG) = 0x80000100; /*rm apb div 4*/
+ while( !(__REG(MPLL_CFG0_REG) & (0x1 << 30) ));
+ while( !(__REG(UPLL_CFG0_REG) & (0x1 << 30) ));
+ while( !(__REG(GPLL_CFG0_REG) & (0x1 << 30) ));
+
+ //M0 select 104M, bit0-1, 0=104, 1=26, 2=78, 3=32k
+ __REG(M0_CORE_SEL) = 0x00000005;
+ //hs_ahb_clk select 104M, bit4-5, 0=104, 1=26, 2=78, 3=32k
+ __REG(HS_AHB_CLK) = 0x00000010;
+
+ __REG(MATRIX_AXI_SEL) = 0x00010001; /*AXI select 156M*/
+ __REG(PS_CORE_SEL) = 0x00000001; /*R7 select 624M*/
+ __REG(PHY_CORE_SEL) = 0x00000001; /*ZSP880 select 491M*/
+ __REG(AP_CORE_SEL) = 0x00000001; /*AP A53 select 624M*/
+
+ //__REG(RM_MOD_CLKSEL) = 0x80000034;/*high speed aclk 156M*/
+}
+
diff --git a/boot/common/src/loader/cpu/m0/config.mk b/boot/common/src/loader/cpu/m0/config.mk
new file mode 100644
index 0000000..560ee59
--- /dev/null
+++ b/boot/common/src/loader/cpu/m0/config.mk
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common
+
+PLATFORM_CPPFLAGS += -march=armv6-m -mcpu=cortex-m0 -mtune=cortex-m0 -msoft-float -mthumb
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+#PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) geanfeng
+
+# Try if EABI is supported, else fall back to old API,
+# i. e. for example:
+# - with ELDK 4.2 (EABI supported), use:
+# -mabi=aapcs-linux -mno-thumb-interwork
+# - with ELDK 4.1 (gcc 4.x, no EABI), use:
+# -mabi=apcs-gnu -mno-thumb-interwork
+# - with ELDK 3.1 (gcc 3.x), use:
+# -mapcs-32 -mno-thumb-interwork
+PLATFORM_CPPFLAGS += $(call cc-option,\
+ aapcs-linux -mno-thumb-interwork,\
+ $(call cc-option,\
+ -mapcs-32,\
+ $(call cc-option,\
+ -mabi=apcs-gnu -mno-thumb-interwork,\
+ )\
+ ) $(call cc-option,-mno-thumb-interwork,)\
+ )
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
+
diff --git a/boot/common/src/loader/cpu/m0/cpu.c b/boot/common/src/loader/cpu/m0/cpu.c
new file mode 100644
index 0000000..084bdb6
--- /dev/null
+++ b/boot/common/src/loader/cpu/m0/cpu.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2016 ZXIC Inc.
+ *
+ */
+
+#include <common.h>
+#include "../../drivers/config.h"
+
+
+// ϵͳʱÖÓ
+typedef struct
+{
+ u32 ctrl; // ϵͳʱÖÓ¿ØÖÆ
+ u32 reload; // ÖØÔØÖµ
+ u32 count; // µ±Ç°Öµ
+ u32 calibration; // Уֵ
+
+} t_tick;
+
+
+volatile t_tick g_tick;
+
+
+// ʱÖÓ³õʼ»¯
+void timer_init(void)
+{
+ volatile t_tick *tick = (t_tick*)(&g_tick);
+ tick->ctrl = 0;
+ tick->count = 0;
+ tick->reload = (u32)-1;
+ tick->ctrl = 0x05;
+}
+
+// ×¢Òâ×î´ó¼Æʱ 24λ
+void usdelay(u32 us)
+{
+ int t0, t1, t2, t3;
+
+ volatile t_tick *tick = (t_tick*)(&g_tick);
+
+ t0 = tick->count;
+ t1 = us * (SYS_CPU_FREQ / 1000000);
+
+ if(t1 <= t0)
+ {
+ t2 = t0 - t1;
+ while((t3 = tick->count) > t2)
+ {
+ if(t3 > 0xFFFF00) break;
+ }
+ }
+ else
+ {
+ t2 = 0x00FFFFFF + t0 - t1;
+ while(1)
+ {
+ t1 = tick->count;
+ if((t1 >= t0) && (t1 <= t2)) break;
+ }
+ }
+}
+
diff --git a/boot/common/src/loader/cpu/m0/divmod.c b/boot/common/src/loader/cpu/m0/divmod.c
new file mode 100644
index 0000000..a978f7a
--- /dev/null
+++ b/boot/common/src/loader/cpu/m0/divmod.c
@@ -0,0 +1,52 @@
+
+extern unsigned long udivmodsi4(unsigned long num, unsigned long den, int modwanted);
+
+
+long
+__divsi3 (long a, long b)
+{
+ int neg = 0;
+ long res;
+
+ if (a < 0)
+ {
+ a = -a;
+ neg = !neg;
+ }
+
+ if (b < 0)
+ {
+ b = -b;
+ neg = !neg;
+ }
+
+ res = udivmodsi4 (a, b, 0);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
+
+long
+__modsi3 (long a, long b)
+{
+ int neg = 0;
+ long res;
+
+ if (a < 0)
+ {
+ a = -a;
+ neg = 1;
+ }
+
+ if (b < 0)
+ b = -b;
+
+ res = udivmodsi4 (a, b, 1);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
diff --git a/boot/common/src/loader/cpu/m0/start.S b/boot/common/src/loader/cpu/m0/start.S
new file mode 100644
index 0000000..848b5a0
--- /dev/null
+++ b/boot/common/src/loader/cpu/m0/start.S
@@ -0,0 +1,226 @@
+/*
+ * (C) Copyright 2016 ZXIC Inc.
+ *
+ */
+
+#include <config.h>
+#include <board.h>
+#include <load_mode.h>
+
+.globl stack_setup
+
+stack:
+#if (CONFIG_DL_DISABLE)
+ .word 0x045A0000 /* DL port: 0x5A->Disable. */
+#else
+ .word 0x04000000 /* DL port: 0x00->Enable. */
+#endif
+ .word 0x3537585A /* = string "57XZ" */
+ .word 0x31563132 /* = string "1V12" */
+ .word 0x00001E70 /* zdata size = 8K - HdrSize = 8192 - 400 = 7792 Bytes = 0x1E70*/
+
+ /* NOT used now, Just reverse memory for RSA/HASH in near future. */
+ .word 0x00000000 /*puk_rsa_d*/
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+
+ .word 0x00000000 /*puk_rsa_n*/
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+
+ .word 0x00000000 /*hash_y*/
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000
+ .word 0x00000000 /* VID+PID */
+#if defined(CFG_ZLOAD)
+ .word 0x00102800
+ .word _start - 0x100000 + 0x8A001 /* TBD: MACRO instead of number. */
+#else
+ .word 0x0008A000
+ .word _start + 0x1
+#endif
+ .word loop + 1
+ .word loop + 1
+
+.globl _bss_start
+_bss_start:
+ .word __bss_start
+ nop
+ nop
+
+.globl _bss_end
+_bss_end:
+ .word __bss_end
+
+.globl _para_start
+_para_start:
+ .word __para_start
+
+.globl _para_end
+_para_end:
+ .word __para_end
+
+.globl _start
+_start:
+
+#if defined(CFG_ZLOAD)
+ /* check stage1 state */
+ ldr r3,=CFG_START_STAGE1_ADDR
+ ldr r4,=CFG_START_STAGE1_STATE
+ ldr r5, [r3]
+ cmp r4, r5
+ beq set_stack
+
+ ldr r0, =0x8a000
+ msr MSP, r0
+
+ bl copy_to_iram1
+ ldr r3,=0x1001B1 /* 0x1b1 = 0x194(header len) + 0x1c(first Ins. offset) + 0x1(16bit thumb instruction) */
+ mov pc,r3
+set_stack:
+ /* Set up the stack */
+ ldr r2, =0x100000
+ ldr r3,=0x194 /*header len=0x194*/
+ add r2,r3
+ ldr r0, [r2]
+ msr MSP, r0
+
+#else
+
+ /* Set up the stack */
+ ldr r2, =stack
+ ldr r3,=0x194 /*header len=0x194*/
+ add r2,r3
+ ldr r0, [r2]
+ msr MSP, r0
+
+#endif /* CFG_ZLOAD */
+
+/* clear the bss */
+clear_bss:
+ ldr r3, =_bss_start
+ ldr r0, [r3] /* find start of bss segment */
+ ldr r3, =_bss_end
+ ldr r1, [r3] /* stop here */
+ cmp r0, r1
+ beq clbss_over
+ mov r2, #0x0 /* clear value */
+clbss_l:
+ str r2, [r0] /* clear BSS location */
+ add r0, r0, #4 /* increment clear index pointer */
+ cmp r0, r1 /* are we at the end yet */
+ bne clbss_l /* keep clearing till at end */
+clbss_over:
+
+/* remove the para section */
+ ldr r3, =_para_start
+ ldr r4, [r3]
+ ldr r3, =_para_end
+ ldr r1, [r3]
+ sub r1, r1, r4
+ ldr r3, =_bss_end
+ ldr r0, [r3]
+ add r1, r1, r0
+ cmp r0, r1
+ beq remove_over
+re_move:
+ ldr r2, [r0]
+ str r2, [r4]
+ add r4, r4, #4
+ add r0, r0, #4 /* increment clear index pointer */
+ cmp r0, r1 /* are we at the end yet */
+ bne re_move
+remove_over:
+
+ b start_armboot
+
+loop:
+ b loop
+
diff --git a/boot/common/src/loader/cpu/m0/udivmod.c b/boot/common/src/loader/cpu/m0/udivmod.c
new file mode 100644
index 0000000..ad59a22
--- /dev/null
+++ b/boot/common/src/loader/cpu/m0/udivmod.c
@@ -0,0 +1,16 @@
+
+extern unsigned long udivmodsi4(unsigned long num, unsigned long den, int modwanted);
+
+
+long
+__udivsi3 (long a, long b)
+{
+ return udivmodsi4 (a, b, 0);
+}
+
+long
+__umodsi3 (long a, long b)
+{
+ return udivmodsi4 (a, b, 1);
+}
+
diff --git a/boot/common/src/loader/cpu/m0/udivmodsi4.c b/boot/common/src/loader/cpu/m0/udivmodsi4.c
new file mode 100755
index 0000000..c556a50
--- /dev/null
+++ b/boot/common/src/loader/cpu/m0/udivmodsi4.c
@@ -0,0 +1,27 @@
+
+unsigned long udivmodsi4(unsigned long num, unsigned long den, int modwanted)
+{
+ unsigned long bits = 1;
+ unsigned long ret = 0;
+ unsigned long tmpnum = num;
+ unsigned long tmpden = den;
+
+ while (tmpden < tmpnum && bits && !(tmpden & (1L<<31)))
+ {
+ tmpden <<=1;
+ bits <<=1;
+ }
+ while (bits)
+ {
+ if (tmpnum >= tmpden)
+ {
+ tmpnum -= tmpden;
+ ret |= bits;
+ }
+ bits >>=1;
+ tmpden >>=1;
+ }
+ if (modwanted) return tmpnum;
+
+ return ret;
+}
diff --git a/boot/common/src/loader/cpu/m0/z-load.lds b/boot/common/src/loader/cpu/m0/z-load.lds
new file mode 100644
index 0000000..905dcf6
--- /dev/null
+++ b/boot/common/src/loader/cpu/m0/z-load.lds
@@ -0,0 +1,64 @@
+/*
+ * November 2006 - Changed to support 3430sdp device
+ * Copyright (c) 2004-2006 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/m0/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ __bss_end = .;
+
+ . = ALIGN(4);
+ .para 0x82000000 : AT(__bss_end)
+ {
+ __para_start = .;
+ *(.para)
+ __para_end = .;
+ }
+
+ __end = .;
+}