[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/boot/common/src/loader/cpu/m0/clk.c b/boot/common/src/loader/cpu/m0/clk.c
new file mode 100644
index 0000000..19f4967
--- /dev/null
+++ b/boot/common/src/loader/cpu/m0/clk.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2016 ZXIC Inc.
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/top_clock.h>
+#include <board.h>
+
+
+void clk_init (void)
+{
+ __REG(MPLL_CFG0_REG) = 0x08040c11;
+ //__REG(APLL_CFG0_REG) = 0x08081009; /*APLL ,832M*/
+ __REG(UPLL_CFG0_REG) = 0x08347811;
+ __REG(GPLL_CFG0_REG) = 0x08347d29;
+ //__REG(DPLL_CFG0_REG) = 0x0a040c19; /*DPLL,26M*/
+
+ //__REG(PLL_LOCK_CNT0) = 0x03e003e0; /*PLL_LOCK_CNT0*/
+ //__REG(PLL_LOCK_CNT1) = 0x03e003e0; /*PLL_LOCK_CNT1*/
+ //__REG(RMCORE_CLK_CFG_REG) = 0x80000100; /*rm apb div 4*/
+ while( !(__REG(MPLL_CFG0_REG) & (0x1 << 30) ));
+ while( !(__REG(UPLL_CFG0_REG) & (0x1 << 30) ));
+ while( !(__REG(GPLL_CFG0_REG) & (0x1 << 30) ));
+
+ //M0 select 104M, bit0-1, 0=104, 1=26, 2=78, 3=32k
+ __REG(M0_CORE_SEL) = 0x00000005;
+ //hs_ahb_clk select 104M, bit4-5, 0=104, 1=26, 2=78, 3=32k
+ __REG(HS_AHB_CLK) = 0x00000010;
+
+ __REG(MATRIX_AXI_SEL) = 0x00010001; /*AXI select 156M*/
+ __REG(PS_CORE_SEL) = 0x00000001; /*R7 select 624M*/
+ __REG(PHY_CORE_SEL) = 0x00000001; /*ZSP880 select 491M*/
+ __REG(AP_CORE_SEL) = 0x00000001; /*AP A53 select 624M*/
+
+ //__REG(RM_MOD_CLKSEL) = 0x80000034;/*high speed aclk 156M*/
+}
+