[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/boot/common/src/loader/include/ddr.h b/boot/common/src/loader/include/ddr.h
new file mode 100644
index 0000000..07bf118
--- /dev/null
+++ b/boot/common/src/loader/include/ddr.h
@@ -0,0 +1,74 @@
+/*******************************************************************************
+ * Copyright (C) 2016, ZXIC Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: v1.0
+ * Author: zhouqi
+ * Date: 2013-8-21
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _ZX297510_DDR_H_
+#define _ZX297510_DDR_H_
+
+
+//#define DDR_FFC
+typedef unsigned int UINT32;
+typedef unsigned char UINT8;
+#if 0
+/*ddr É豸¼Ä´æÆ÷½á¹¹Ìå*/
+struct ddr_device_para
+{
+ unsigned int reg_0x12030f4; /* ¼Ä´æÆ÷ 0x12030f4 */
+};
+#endif
+
+
+typedef enum
+{
+ DDR_156M = 0,
+ DDR_208M = 1,
+ DDR_312M = 2,
+ DDR_400M = 3,
+ DDR_CLKEND
+}T_zDrvPow_DDRCLK;
+
+
+/*DDR*/
+#define DDR_CTRL_BASE (0x00150000)
+#define DDR_PHY_BASE (0x00154000)
+#define DDR_FFC_ADDR_BASE (0x00155000)
+
+
+#define STD_CRM_REG_BASE (0x01306000)
+
+#define CRTL_PWRCTL (DDR_CTRL_BASE+0x030)
+
+/*DDR CTRL MP*/
+
+#define CTRL_STAT (DDR_CTRL_BASE+0x004)
+
+#define MOD_CLK_SEL (STD_CRM_REG_BASE+0x50)
+
+#define SELFREF_SW (5)
+
+#define CHIP_DDR_IS_32M 0
+#define CHIP_DDR_IS_64M 1
+#define CHIP_DDR_IS_128M 2
+#define CHIP_DDR_IS_256M 3
+
+
+int ddr_init(int flag);
+
+
+#endif/*_ZX297510_DDR_H_*/
+
+