[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/boot/common/src/loader/lib/config.h b/boot/common/src/loader/lib/config.h
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+++ b/boot/common/src/loader/lib/config.h
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+/*******************************************************************************
+* °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ£º config.h
+* Îļþ±êʶ£º /include/config.h
+* ÄÚÈÝÕªÒª£º ÒýÈ뿪·¢°åµÄÅäÖÃÎļþ
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº ÎÌÔÆ·å
+* Íê³ÉÈÕÆÚ£º 2010-9-30
+*
+*
+*******************************************************************************/
+#ifndef __INCLUDE_CONFIG_H_
+#define __INCLUDE_CONFIG_H_
+/*********************************************************************************
+1:open 0:close
+* ¹¦ÄÜ SIM_EN USE_ASIC SYNC_USB_CTRL SYNC_USB_HSIC SYNC_SETADDRESS
+* FPGA 1 0 0 0 0
+* usb_ctrlÑéÖ¤ 0 1 1 1 1
+* usb_hsicÑéÖ¤ 0 1 1 1 1
+* usbtimeoutÑéÖ¤0 1 1 1 1
+* asic 1 1 0 0 0
+**********************************************************************************/
+#define SIM_EN 1
+#define USE_ASIC 1
+#define SYNC_USB_CTRL 0
+#define SYNC_USB_HSIC 0
+#define SYNC_SETADDRESS 0
+
+#if !USE_ASIC ///0:fpga 1:asic
+// CPUʱÖÓƵÂÊ
+#define SYS_CPU_FREQ 50000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
+#define SYS_UART_CLK_CONFIG_PLL 25000000 // ʱÖÓƵÂÊ
+#else
+// CPUʱÖÓƵÂÊ
+#define SYS_CPU_FREQ 208000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK (26000000/6) // ʱÖÓƵÂÊ
+#define SYS_UART_CLK_CONFIG_PLL 104000000 // ʱÖÓƵÂÊ
+#endif
+// Æô¶¯Ä£Ê½Ñ¡Ôñ¼Ä´æÆ÷
+#define SYS_BOOTSEL_BASE 0x0013b004 // ¶¨ÒåBOOTSEL¼Ä´æÆ÷µØÖ·
+
+#define SOC_CRM_BASE (0x0010c000)
+#define BOOT_SEL (0x3c)
+#define NAND_CFG (0x34)
+//#define SOC_MOD_CLKEN0 (0x0010c00c)
+//#define SOC_MOD_CLKEN1 (0x0010c010)
+//#define SOC_MOD_RSTEN (0x0010c018)
+#define SOC_MOD_USBSTATECTRL (0x0013B084)
+#define SOC_MOD_RSTEN1 (0x0010c064)
+
+#define CFG_STACK_TOP 0x0008AFE0 // ¶¨ÒåÁËÕ»¶¥
+
+// UART ²ÎÊý
+#define SYS_UART_BASE 0x00102000 // »ùµØÖ·
+//#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
+#define CFG_UART_BAUDRATE 115200 // ²¨ÌØÂÊ
+#define CFG_BUF_SIZE 64 // Êý¾Ý»º³åÇø´óС
+#if !USE_ASIC
+// USB ²ÎÊý
+#define SYS_USB_BASE 0x01500000 // »ùµØÖ·
+#define SYS_USB_HSIC_BASE 0x01500000 // »ùµØÖ·
+#else
+#define SYS_USB_BASE 0x01500000 // »ùµØÖ·
+#define SYS_USB_HSIC_BASE 0x01500000 // »ùµØÖ·
+#endif
+
+
+// NAND FLASH ²ÎÊý
+#define SYS_NAND_BASE 0x01207000 // ¼Ä´æÆ÷»ùµØÖ·
+#define SYS_NAND_DATA 0x01208000 // Êý¾Ý»ùµØÖ·
+
+// ͨÓòÎÊý
+#define CFG_LOAD_BASE 0x0008B000 // ¼ÓÔØ´úÂëµ½¸ÃµØÖ·,±ØÐë4K¶ÔÆë
+#define SYS_LOAD_LEN 0x1000 // ¼ÓÔس¤¶È
+#define CFG_PRINT_BUF_SIZE 256
+
+//#define POWER_DOMAIN_ISO (0x0010d200+0x41*4)
+//#define POWER_DOMAIN_POWERON (0x0010d200+0x42*4)
+//#define POWER_DOMAIN_RST (0x0010d200+0x40*4)
+
+//ÑéÖ¤ÐèÒª
+#if SYNC_USB_CTRL
+#define ARM_PORTA (0x102040)
+#endif
+
+#if SYNC_USB_HSIC
+#define REG_GPIO_OUT 0x01400014
+#define REG_GPIO_IN 0x01409020
+#endif
+#endif