[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/boot/common/src/uboot/downloader/boot_usb.c b/boot/common/src/uboot/downloader/boot_usb.c
new file mode 100644
index 0000000..a632802
--- /dev/null
+++ b/boot/common/src/uboot/downloader/boot_usb.c
@@ -0,0 +1,248 @@
+#include <usb/global.h>
+#include <usb/config.h>
+extern WORD32 USB_CDC_Enum(WORD32 USB_ADDR);
+//extern void USB_Pll_Clk_Rst_InitEnv(void);
+
+void USB_TstDev_InitEnv(void);
+
+#if 0
+void tsp_usb_init(WORD32 USB_ADDR)
+{
+ WORD32 dwConnect;
+
+ /*ÅäÖÃÍâΧ»·¾³*/
+
+ USB_Pll_Clk_Rst_InitEnv();
+
+ dwConnect=USB_CDC_Enum(USB_ADDR);
+
+ if(0==dwConnect)
+ {
+ printk("NOLINK\n");
+ return ;
+ }
+
+ printk("FAILED\n");
+
+}
+#endif
+
+int tsp_usb_init(void)
+{
+ WORD32 retVal = 0;
+ WORD32 usb_addr = 0;
+// BYTE boot_mode = get_boot_mode();
+ BYTE boot_mode = 1;
+ data_init();
+ /*add by sunyunchen*/
+ if(2 == boot_mode)
+ //if(0)
+ {
+ printf("hsic\n");
+ global.g_USB_MODE = 1;
+ usb_addr = SYS_USB_HSIC_BASE;
+ }
+ else
+ {
+ printf("usb\n");
+ global.g_USB_MODE = 0;
+ usb_addr = SYS_USB_BASE;
+ }
+ if((REG32(usb_addr+DWC_DEV_GLOBAL_REG_OFFSET)&0x7f0)!=0)//dcfg register
+ {
+ //printf("usb_g_enum!\n");
+ global.g_enum =DONOT_NEED_ENUM;
+
+
+ //global.g_enum =NEED_ENUM;
+ }
+ if(NEED_ENUM == global.g_enum)
+ {
+ //printf("need enum\n");
+ USB_TstDev_InitEnv();
+ }
+ else
+ {
+ //printf("global.g_dwc\n");
+ global.g_dwc_otg_pcd_tp.ep0state = EP0_IDLE;
+ global.dwRxQuit = 1;
+ global.dwTxQuit = 1;
+ global.g_dwc_otg_pcd_tp.request_config = 1;
+ }
+
+ retVal = USB_CDC_Enum(usb_addr);
+
+ return retVal;
+}
+
+void USB_TstDev_InitEnv(void)
+{
+#if USE_ASIC
+ WORD32 i;
+ if(0 == global.g_USB_MODE)
+ {
+
+ //ÊÍ·ÅUSB¸ôÀë8bit for usb ctrl
+ REG32(POWER_DOMAIN_ISO) |= (1<<8);
+ usdelay(10);
+
+ REG32(POWER_DOMAIN_RST) |= (1<<8);
+ usdelay(10);
+
+ REG32(POWER_DOMAIN_POWERON) &= ~(1<<8);
+ usdelay(10);
+
+ REG32(POWER_DOMAIN_POWERON) |= (1<<8);
+ usdelay(10);
+
+ REG32(POWER_DOMAIN_RST) &= ~(1<<8);
+ usdelay(10);
+
+ REG32(POWER_DOMAIN_ISO) &= ~(1<<8);
+ usdelay(10);
+
+ //usb ahb clock enable
+ REG32(SOC_MOD_CLKEN0)&=~(1<<4);
+ usdelay(20);
+ REG32(SOC_MOD_CLKEN0)|=(1<<4);
+ //usb phy clock enable
+ REG32(SOC_MOD_CLKEN1)&=~(1<<3);
+ usdelay(20);
+ REG32(SOC_MOD_CLKEN1)|=(1<<3);
+
+ // usb ahb reset ÏÈ×ÜÏߺó¹¤×÷
+ REG32(SOC_MOD_RSTEN)&=~(1<<5);
+ usdelay(100);
+ REG32(SOC_MOD_RSTEN)|=(1<<5);
+ usdelay(100);
+
+ // usb work reset
+ REG32(SOC_MOD_RSTEN)&=~(1<<4);
+ usdelay(100);
+ REG32(SOC_MOD_RSTEN)|=(1<<4);
+ usdelay(100);
+
+ //release usb phy reset
+ REG32(SOC_MOD_RSTEN)&=~(1<<3);
+ usdelay(100);
+ REG32(SOC_MOD_RSTEN) |= 1<<3;
+ usdelay(100);
+
+ i = 0;
+ while((REG32(SOC_MOD_USBSTATECTRL)&0x2) == 0)
+ {
+ i++;
+ usdelay(20);
+ if(i>50000) break;
+ }
+ }
+ else
+ {
+ //ÊÍ·ÅUSB_HSIC¸ôÀë9bit for hsic
+ REG32(POWER_DOMAIN_ISO) |= (1<<9);
+ usdelay(10);
+
+ REG32(POWER_DOMAIN_RST) |= (1<<9);
+ usdelay(10);
+
+ REG32(POWER_DOMAIN_POWERON) &= ~(1<<9);
+ usdelay(10);
+
+ REG32(POWER_DOMAIN_POWERON) |= (1<<9);
+ usdelay(10);
+
+ REG32(POWER_DOMAIN_RST) &= ~(1<<9);
+ usdelay(10);
+
+ REG32(POWER_DOMAIN_ISO) &= ~(1<<9);
+ usdelay(10);
+
+ //usb hsic ahb clock enable
+ REG32(SOC_MOD_CLKEN0)&=~(1<<2);
+ usdelay(20);
+ REG32(SOC_MOD_CLKEN0)|=(1<<2);
+ //usb hsic phy clock enable
+ REG32(SOC_MOD_CLKEN0)&=~(1<<1);
+ usdelay(20);
+ REG32(SOC_MOD_CLKEN0)|=(1<<1);
+
+ //usb hsic 480M clock enable
+ REG32(SOC_MOD_CLKEN0)&=~(1<<0);
+ usdelay(20);
+ REG32(SOC_MOD_CLKEN0)|=(1<<0);
+
+ // usb hsic ahb reset
+ REG32(SOC_MOD_RSTEN)&=~(1<<2);
+ usdelay(20);
+ REG32(SOC_MOD_RSTEN)|=(1<<2);
+ usdelay(10);
+
+ // usb hsic work reset
+ REG32(SOC_MOD_RSTEN)&=~(1<<1);
+ usdelay(20);
+ REG32(SOC_MOD_RSTEN)|=(1<<1);
+ //release usb hsic phy reset
+ REG32(SOC_MOD_RSTEN)&=~(1<<0);
+ usdelay(20);
+ REG32(SOC_MOD_RSTEN)|=(1<<0);
+
+ usdelay(100);
+ i = 0;
+ while((REG32(SOC_MOD_USBSTATECTRL)&0x1) == 0)
+ {
+ i++;
+ usdelay(20);
+ if(i>50000) break;
+ }
+
+#if SYNC_USB_HSIC
+ usdelay(20);
+ REG32(REG_GPIO_OUT)=1;
+ while(REG32(REG_GPIO_IN)!=0xFF);
+ usdelay(1);
+ REG32(REG_GPIO_OUT)=0;
+#endif
+ }
+#endif
+#if !USE_ASIC
+#if 1
+//usb power on
+ REG32(POWER_DOMAIN_POWERON) |= 0x300;
+ usdelay(10);
+//usb disable reset
+ REG32(POWER_DOMAIN_RST) &= 0xfffffcff; //
+ usdelay(10);
+//usb disable iso
+ REG32(POWER_DOMAIN_ISO) &= 0xfffffcff;
+ usdelay(10);
+
+//open usb0 and usb1
+ //usb ahb clock enable
+ REG32(SOC_MOD_CLKEN0)&=0xeffffffb;
+ usdelay(20);
+ REG32(SOC_MOD_CLKEN0)|=0x10000004;
+ //usb phy clock enable
+ REG32(SOC_MOD_CLKEN1)&=~(3<<16);
+ usdelay(20);
+ REG32(SOC_MOD_CLKEN1)|=(3<<16);
+
+
+ // usb ctr reset
+ REG32(SOC_MOD_RSTEN)&=0xeffffff7;
+ usdelay(20);
+ REG32(SOC_MOD_RSTEN)|=0x10000008;
+
+ // usb ahb reset
+ REG32(SOC_MOD_RSTEN)&=0xf7fffffb;
+ usdelay(20);
+ REG32(SOC_MOD_RSTEN)|=0x8000004;
+#endif
+/*
+ usb ctr and ahb reset release ,delay 60us, check usb reset state,
+ if the reset state is 0, reset ,if 1,reset release.
+*/
+#endif
+}
+
+
+