[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/boot/common/src/uboot/include/usb/common.h b/boot/common/src/uboot/include/usb/common.h
new file mode 100644
index 0000000..f7b103b
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/common.h
@@ -0,0 +1,43 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ£º common.h
+* ÄÚÈÝÕªÒª£º
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº ÎÌÔÆ·å
+* Íê³ÉÈÕÆÚ£º 2010-9-30
+*
+*
+*******************************************************************************/
+#ifndef __INCLUDE_COMMON_H_
+#define __INCLUDE_COMMON_H_
+
+#include "type.h"
+#include "config.h"
+
+extern void uart_init(WORD32 PLL_H);
+extern char uart_getc(void);
+extern void uart_putc(const char c);
+extern void uart_puts(const char *s);
+extern int uart_ctrlc(void);
+
+extern int timer_init(void);
+
+extern void hex_to_str(unsigned d, unsigned char w);
+extern int nand_read_4k(void);
+extern void usb_boot(WORD32 USB_ADDR);
+
+extern void run_at(unsigned);
+extern void usdelay(unsigned us);
+extern void print(const char *fmt, ...);
+#define Para_Section __attribute__((__section__ (".para")));
+
+//#define getc uart_getc
+#define putc uart_putc
+#define puts uart_puts
+#define ctrlc uart_ctrlc
+
+#define printk(x) printf(x)
+
+#endif
diff --git a/boot/common/src/uboot/include/usb/config.h b/boot/common/src/uboot/include/usb/config.h
new file mode 100644
index 0000000..7973739
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/config.h
@@ -0,0 +1,226 @@
+
+#if 0
+
+/*******************************************************************************
+* °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ£º config.h
+* Îļþ±êʶ£º /include/config.h
+* ÄÚÈÝÕªÒª£º ÒýÈ뿪·¢°åµÄÅäÖÃÎļþ
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº ÎÌÔÆ·å
+* Íê³ÉÈÕÆÚ£º 2010-9-30
+*
+*
+
+*******************************************************************************/
+
+
+
+#ifndef __INCLUDE_CONFIG_H_
+#define __INCLUDE_CONFIG_H_
+/*********************************************************************************
+1:open 0:close
+* ¹¦ÄÜ SIM_EN USE_ASIC SYNC_USB_CTRL SYNC_USB_HSIC SYNC_SETADDRESS
+* FPGA 1 0 0 0 0
+* usb_ctrlÑéÖ¤ 0 1 1 1 1
+* usb_hsicÑéÖ¤ 0 1 1 1 1
+* usbtimeoutÑéÖ¤0 1 1 1 1
+* asic 1 1 0 0 0
+**********************************************************************************/
+#define SIM_EN 1
+#define USE_ASIC 0
+#define SYNC_USB_CTRL 0
+#define SYNC_USB_HSIC 0
+#define SYNC_SETADDRESS 0
+
+#if !USE_ASIC ///0:fpga 1:asic
+// CPUʱÖÓƵÂÊ
+#define SYS_CPU_FREQ 50000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
+#define SYS_UART_CLK_CONFIG_PLL 25000000 // ʱÖÓƵÂÊ
+#else
+// CPUʱÖÓƵÂÊ
+#define SYS_CPU_FREQ 208000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK (26000000/6) // ʱÖÓƵÂÊ
+#define SYS_UART_CLK_CONFIG_PLL 104000000 // ʱÖÓƵÂÊ
+#endif
+// Æô¶¯Ä£Ê½Ñ¡Ôñ¼Ä´æÆ÷
+#define SYS_BOOTSEL_BASE 0x0010c03c // ¶¨ÒåBOOTSEL¼Ä´æÆ÷µØÖ·
+
+#define SOC_CRM_BASE (0x0010c000)
+#define BOOT_SEL (0x3c)
+#define NAND_CFG (0x34)
+#define SOC_MOD_CLKEN0 (0x0010c00c)
+#define SOC_MOD_CLKEN1 (0x0010c010)
+#define SOC_MOD_RSTEN (0x0010c018)
+#define SOC_MOD_USBSTATECTRL (0x0010c05c)
+#define SOC_MOD_RSTEN1 (0x0010c064)
+
+#define CFG_STACK_TOP 0x0008AFE0 // ¶¨ÒåÁËÕ»¶¥
+
+// UART ²ÎÊý
+#define SYS_UART_BASE 0x00102000 // »ùµØÖ·
+//#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
+#define CFG_UART_BAUDRATE 115200 // ²¨ÌØÂÊ
+#define CFG_BUF_SIZE 64 // Êý¾Ý»º³åÇø´óС
+#if !USE_ASIC
+// USB ²ÎÊý
+#define SYS_USB_BASE 0x01240000 // »ùµØÖ·
+#define SYS_USB_HSIC_BASE 0x01280000 // »ùµØÖ·
+#else
+#define SYS_USB_BASE 0x01280000 // »ùµØÖ·
+#define SYS_USB_HSIC_BASE 0x01240000 // »ùµØÖ·
+#endif
+
+
+// NAND FLASH ²ÎÊý
+#define SYS_NAND_BASE 0x01207000 // ¼Ä´æÆ÷»ùµØÖ·
+#define SYS_NAND_DATA 0x01208000 // Êý¾Ý»ùµØÖ·
+
+// ͨÓòÎÊý
+#define CFG_LOAD_BASE 0x0008B000 // ¼ÓÔØ´úÂëµ½¸ÃµØÖ·,±ØÐë4K¶ÔÆë
+#define SYS_LOAD_LEN 0x1000 // ¼ÓÔس¤¶È
+#define CFG_PRINT_BUF_SIZE 256
+
+#define POWER_DOMAIN_ISO (0x0010d200+0x41*4)
+#define POWER_DOMAIN_POWERON (0x0010d200+0x42*4)
+#define POWER_DOMAIN_RST (0x0010d200+0x40*4)
+
+//ÑéÖ¤ÐèÒª
+#if SYNC_USB_CTRL
+#define ARM_PORTA (0x102040)
+#endif
+
+#if SYNC_USB_HSIC
+#define REG_GPIO_OUT 0x01400014
+#define REG_GPIO_IN 0x01409020
+#endif
+#define CFG_USB30_LOAD_BASE 0x62000000 //USB30 ÄÚ²¿DMAÊý¾ÝÏÂÔصØÖ·
+#endif
+#endif
+/******************************************************************************/
+/*******************************************************************************
+* °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ£º config.h
+* Îļþ±êʶ£º /include/config.h
+* ÄÚÈÝÕªÒª£º ÒýÈ뿪·¢°åµÄÅäÖÃÎļþ
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº
+* Íê³ÉÈÕÆÚ£º
+*
+*
+*******************************************************************************/
+#ifndef __INCLUDE_CONFIG_H_
+#define __INCLUDE_CONFIG_H_
+
+#define FPGA 0
+#define ASIC 1
+#define EMULATION 2
+#define ULPI 0
+#define UTMI 1
+
+/*ͨ¹ýºê¶¨ÒåÀ´Ñ¡Ôñ°æ±¾·½Ê½*/
+#define SIM_EN FPGA
+
+#define USB_PHY UTMI
+
+//IRAM0 0x62000000 IRAM2 0x80000 IRAM1 0x100000(δÓÃ)
+#define CFG_USB30_LOAD_BASE 0x62000000 //USB30 ÄÚ²¿DMAÊý¾ÝÏÂÔصØÖ·
+#define CFG_SDIO_LOAD_BASE 0x62000000 // SDIO DMA Êý¾Ý°áÔ˵ØÖ·
+#define CFG_LOAD_BASE 0x00087000 // ¼ÓÔØ´úÂëµ½¸ÃµØÖ·,±ØÐë4K¶ÔÆë
+#define SYS_LOAD_LEN 0x1000 // ¼ÓÔس¤¶È
+#define CFG_PRINT_BUF_SIZE 256
+#define CFG_STACK_TOP 0x86800
+
+#if ((SIM_EN == ASIC)||(SIM_EN == EMULATION))
+// CPUʱÖÓƵÂÊ,usb³¬Ê±»úÖƼÆʱ²ÉÓÃtick£¬Óëm0ͬƵ£¬ÇÒusb bootÐèpllʱÖÓÅäÖá£
+#define SYS_CPU_FREQ 208000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK 26000000 // ʱÖÓƵÂÊ
+#define PLL_8X(x) ((x)>>3) //pllδÅäÖÃÇ°£¬´æÔÚ8±¶µÄ¹Øϵ
+#elif (SIM_EN == FPGA)
+// CPUʱÖÓƵÂÊ
+#define SYS_CPU_FREQ 30000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
+#define PLL_8X(x) (x) //²»´æÔÚ±¶Êý²îÒì
+#endif
+
+// Æô¶¯Ä£Ê½Ñ¡Ôñ¼Ä´æÆ÷
+/*bootsel_info*/
+/*[0:3] bootsel0,bootsel1,bootsel2,bootsel3
+ [4:5] nand page size
+ [6] nand data width
+ [7] nand addr cycles*/
+/*
+#define SYS_BOOTSEL_INFO 0x0013b04c // ¶¨ÒåBOOTSEL¼Ä´æÆ÷µØÖ·
+#define SYS_STD_CRM_BASE 0x1307000
+#define SYS_LSP_CRM_BASE 0x01400000
+#define SYS_SOC_CRM_BASE 0x0013b000
+#define SYS_PAD_CTRL0_BASE 0x143000
+*/
+
+#define SOC_CRM_BASE (0x0013b000)
+#define BOOT_SEL (0x3c)
+#define NAND_CFG (0x34)
+#define SOC_MOD_CLKEN0 (0x0013b06c)
+#define SOC_MOD_CLKEN1 (0x0013b06c)
+#define SOC_MOD_RSTEN (0x0013b080)
+#define SOC_MOD_USBSTATECTRL (0x0010c05c)
+#define SOC_MOD_RSTEN1 (0x0010c064)
+
+
+
+
+
+/*UART ²ÎÊý*/
+#define SYS_UART_BASE 0x0138000 // UART0 »ùµØÖ· //
+
+#define CFG_UART_BAUDRATE 115200 // ²¨ÌØÂÊ
+#define CFG_BUF_SIZE 64 // Êý¾Ý»º³åÇø´óС
+
+/*USB BASE ADDRESS*/
+//#define SYS_USB_BASE 0x02000000 // 3.0»ùµØÖ·
+//#define SYS_USB_HSIC_BASE 0x01500000 // HSIC»ùµØÖ·
+
+#define SYS_USB_BASE 0x01500000 // 2.0»ùµØÖ·
+#define SYS_USB_HSIC_BASE 0x01600000 // HSIC»ùµØÖ·
+//ÒÔÉÏÊÇ7520V2оƬÖж¨ÒåµÄUSB»ùÖ·
+
+
+
+
+/* NAND FLASH ²ÎÊý*/
+#define SYS_NAND_BASE 0x01211000 // ¼Ä´æÆ÷»ùµØÖ·
+#define SYS_NAND_DATA 0x01212000 // Êý¾Ý»ùµØÖ·
+
+/*SPI_FLASH²ÎÊý*/
+#define SYS_SPI_FLASH_BASE 0x140c000
+
+/*SD/MMC ²ÎÊý*/
+#define SYS_EMMC_REGS_BASE 0x01210000 //SD0
+#define CFG_EMMC_CLK_REF 26000000
+#define CFG_EMMC_CLK_ENUM 400000
+#define CFG_EMMC_CLK_WORK 26000000
+
+/*SDIO SLAVE ²ÎÊý*/
+#define SYS_SDIO_REGS_BASE 0x01540000 //SD1
+
+
+#define POWER_DOMAIN_ISO (0x00140110)
+#define POWER_DOMAIN_POWERON (0x00140114)
+#define POWER_DOMAIN_RST (0x0014010c)
+
+
+//ÑéÖ¤ÐèÒª
+#if SIM_EN == EMULATION
+/*USB2.0*/
+#define ARM_PORTA (REG_GPIO_OUT)
+/*HSIC*/
+#define REG_GPIO_OUT 0x00145060 //7520
+#define REG_GPIO_IN 0x00145014
+#endif
+#endif
+
diff --git a/boot/common/src/uboot/include/usb/drv_usb3slave.h b/boot/common/src/uboot/include/usb/drv_usb3slave.h
new file mode 100755
index 0000000..632aed5
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/drv_usb3slave.h
@@ -0,0 +1,642 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ£º drv_usb3slave.h
+* Îļþ±êʶ£º
+* ÄÚÈÝÕªÒª£º
+* ÆäËü˵Ã÷£º zx297520 project
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº tangjian
+* Íê³ÉÈÕÆÚ£º
+*
+*
+*******************************************************************************/
+
+#ifndef __USB3_SLAVE_DRV_H
+#define __USB3_SLAVE_DRV_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*
+**==================================================================
+** Include files
+**==================================================================
+*/
+#include "usb.h"
+#include "global.h"
+#include "drv_usb3slave_reg.h"
+#include "dwc_otg_cil.h" //ÓÃÓÚ¶¨Òå»Øµ÷º¯Êý
+#include <linux/types.h>
+typedef void (*F_USB_CB)(WORD32 dwPara, WORD32 dwResult, WORD32 dwLen, WORD32 dwWantLen);
+
+/* DRV´íÎóÂë */
+#define SOK (0) /**< ÕýÈ· */
+#define ERR_FAIL (0x01) /**< Ò»°ã´íÎó */
+#define ERR_INUSE (0x02) /**< ÍâÉè×ÊÔ´ÕýÔÚʹÓà */
+#define ERR_XIO (0x03) /**< ¹²Ïí×ÊÔ´¾ºÕù */
+#define ERR_OVFL (0x04) /**< ¿ÉÓÃ×ÊÔ´ºÄ¾¡ */
+#define ERR_INVHANDLE (0x05) /**< ´«Èë¾ä±úÎÞЧ */
+#define ERR_INVPARAMS (0x06) /**< ²ÎÊýÎÞЧ */
+#define ERR_INVCMD (0x07) /**< ÃüÁîÎÞЧ */
+#define ERR_NOMEM (0x08) /**< ÄÚ´æºÄ¾¡ */
+#define ERR_UNSUPPORTED (0x09) /**< ÐÐΪ²»Ö§³Ö */
+#define ERR_INVHWVERSION (0x10) /**< Ó²¼þ°æ±¾²»Æ¥Åä */
+
+#define FALSE 0
+#define TRUE 1
+
+#define DWC3_DCFG_SPEED_MASK (7 << 0)
+
+#define DWC3_DCFG 0xc700
+#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
+#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
+#define DWC3_DCTL 0xc704
+#define DWC3_DCTL_CSFTRST (1 << 30)
+/*0x200-0x23c*/
+#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
+/*0x2C0-0x2fc*/
+#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
+
+/*0x300-0x37C*/
+#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
+
+/*0x380-0x3fc*/
+#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
+
+#define DWC3_GCTL 0xc110
+#define DWC3_DCTL_RUN_STOP (1 << 31)
+
+#define DWC3_DEVTEN_USBSUSPENDEN (1 << 6)
+#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
+#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
+#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
+#define DWC3_DEVTEN_USBRSTEN (1 << 1)
+#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
+
+#define DWC3_DEVTEN 0xc708
+#define DWC3_DSTS 0xc70c
+
+#define DWC3_DALEPENA 0xc720
+/** ¶¨ÒåÃèÊö·ûÀàÐÍ */
+#define USB_DT_DEVICE 0x01
+#define USB_DT_CONFIG 0x02
+#define USB_DT_STRING 0x03
+#define USB_DT_INTERFACE 0x04
+#define USB_DT_ENDPOINT 0x05
+#define USB_DT_DEVICE_QUALIFIER 0x06
+#define USB_DT_OTHER_SPEED_CONFIG 0x07
+#define USB_DT_INTERFACE_POWER 0x08
+/** these are from a minor usb 2.0 revision (ECN) */
+#define USB_DT_OTG 0x09
+#define USB_DT_DEBUG 0x0a
+#define USB_DT_INTERFACE_ASSOCIATION 0x0b
+/** these are from the Wireless USB spec */
+#define USB_DT_SECURITY 0x0c
+#define USB_DT_KEY 0x0d
+#define USB_DT_ENCRYPTION_TYPE 0x0e
+#define USB_DT_BOS 0x0f
+#define USB_DT_DEVICE_CAPABILITY 0x10
+#define USB_DT_WIRELESS_ENDPOINT_COMP 0x11
+#define USB_DT_WIRE_ADAPTER 0x21
+#define USB_DT_RPIPE 0x22
+#define USB_DT_CS_RADIO_CONTROL 0x23
+/** From the T10 UAS specification */
+#define USB_DT_PIPE_USAGE 0x24
+/** From the USB 3.0 spec */
+#define USB_DT_SS_ENDPOINT_COMP 0x30
+/** USB directions */
+#define USB_DIR_OUT 0 /* to device */
+#define USB_DIR_IN 0x80 /* to host */
+/** USB types, the second of three bmRequestType fields, ÐÒé9.3.1 */
+#define USB_TYPE_MASK (0x03 << 5)
+#define USB_TYPE_STANDARD (0x00 << 5)
+#define USB_TYPE_CLASS (0x01 << 5)
+#define USB_TYPE_VENDOR (0x02 << 5)
+#define USB_TYPE_RESERVED (0x03 << 5)
+/** USB recipients, the third of three bmRequestType fields */
+#define USB_RECIP_MASK 0x1f
+#define USB_RECIP_DEVICE 0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT 0x02
+#define USB_RECIP_OTHER 0x03
+/** From Wireless USB 1.0 */
+#define USB_RECIP_PORT 0x04
+#define USB_RECIP_RPIPE 0x05
+/*
+* Standard requests, for the bRequest field of a SETUP packet.
+*
+* These are qualified by the bmRequestType field, so that for example
+* TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
+* by a GET_STATUS request.
+*/
+#define USB_REQ_GET_STATUS 0x00
+#define USB_REQ_CLEAR_FEATURE 0x01
+#define USB_REQ_SET_FEATURE 0x03
+#define USB_REQ_SET_ADDRESS 0x05
+#define USB_REQ_GET_DESCRIPTOR 0x06
+#define USB_REQ_SET_DESCRIPTOR 0x07
+#define USB_REQ_GET_CONFIGURATION 0x08
+#define USB_REQ_SET_CONFIGURATION 0x09
+#define USB_REQ_GET_INTERFACE 0x0A
+#define USB_REQ_SET_INTERFACE 0x0B
+#define USB_REQ_SYNCH_FRAME 0x0C
+#define USB_REQ_GET_MAX_LUN 0xFE
+/*
+* USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and
+* are read as a bit array returned by USB_REQ_GET_STATUS. (So there
+* are at most sixteen features of each type.) Hubs may also support a
+* new USB_REQ_TEST_AND_SET_FEATURE to put ports into L1 suspend.
+*/
+#define USB_DEVICE_SELF_POWERED 0 /**< (read only) */
+#define USB_DEVICE_REMOTE_WAKEUP 1 /**< dev may initiate wakeup */
+#define USB_DEVICE_TEST_MODE 2 /**< (wired high speed only) */
+#define USB_DEVICE_BATTERY 2 /**< (wireless) */
+#define USB_DEVICE_B_HNP_ENABLE 3 /**< (otg) dev may initiate HNP */
+#define USB_DEVICE_WUSB_DEVICE 3 /**< (wireless)*/
+#define USB_DEVICE_A_HNP_SUPPORT 4 /**< (otg) RH port supports HNP */
+#define USB_DEVICE_A_ALT_HNP_SUPPORT 5 /**< (otg) other RH port does */
+#define USB_DEVICE_DEBUG_MODE 6 /**< (special devices only) */
+/*
+* New Feature Selectors as added by USB 3.0
+* See USB 3.0 spec Table 9-7
+* Suspend Options, Table 9-7 USB 3.0 spec
+*/
+#define USB_DEVICE_U1_ENABLE 48 /**< dev may initiate U1 transition */
+#define USB_DEVICE_U2_ENABLE 49 /**< dev may initiate U2 transition */
+#define USB_DEVICE_LTM_ENABLE 50 /**< dev may send LTM */
+
+#define USB_INTRF_FUNC_SUSPEND 0 /**< function suspend */
+#define USB_INTR_FUNC_SUSPEND_OPT_MASK 0xFF00
+#define USB_INTRF_FUNC_SUSPEND_LP (1 << (8 + 0))
+#define USB_INTRF_FUNC_SUSPEND_RW (1 << (8 + 1))
+
+#define USB_ENDPOINT_HALT 0 /**< IN/OUT will STALL */
+
+/** Bit array elements as returned by the USB_REQ_GET_STATUS request */
+#define USB_DEV_STAT_U1_ENABLED 2 /**< transition into U1 state */
+#define USB_DEV_STAT_U2_ENABLED 3 /**< transition into U2 state */
+#define USB_DEV_STAT_LTM_ENABLED 4 /**< Latency tolerance messages */
+/**
+* USB function drivers should return USB_GADGET_DELAYED_STATUS if they
+* wish to delay the data/status stages of the control transfer till they
+* are ready. The control transfer will then be kept from completing till
+* all the function drivers that requested for USB_GADGET_DELAYED_STAUS
+* invoke usb_composite_setup_continue().
+*/
+#define USB_GADGET_DELAYED_STATUS 0x7fff /**< Impossibly large value */
+//#define EP0_PACKET_SIZE 64
+//#define MAX_EPS (0x8)
+
+/**
+* struct usb_ctrlrequest - SETUP data for a USB device control request
+* Note that the driver for any interface can issue control requests.
+* For most devices, interfaces don't coordinate with each other, so
+* such requests may be made at any time.
+*/
+
+ typedef struct T_USB3Slave_CtrlReq
+{
+ u8 bmRequestType; /**< Æ¥Åäsetup°übmRequestTypeÓò */
+ u8 bRequest; /**< Æ¥Åäsetup°übRequestÓò */
+ u16 wValue; /**< Æ¥Åäsetup°üwValueÓò */
+ u16 wIndex; /**< Æ¥Åäsetup°üwIndexÓò */
+ u16 wLength; /**< Æ¥Åäsetup°üwLengthÓò */
+}__attribute__ ((__packed__)) T_USB3Slave_CtrlReq;
+
+/** ¶Ëµã´«ÊäÀàÐ͵Ⱥ궨Òå */
+#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK 0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL 0
+#define USB_ENDPOINT_XFER_ISOC 1
+#define USB_ENDPOINT_XFER_BULK 2
+#define USB_ENDPOINT_XFER_INT 3
+#define USB_ENDPOINT_MAX_ADJUSTABLE 0x80
+
+/** ×î´ó°ü´óС£¬²ÎÕÕÐÒ飬¾ù¿ÉÉèÖÃΪ1024 */
+#define HS_MAX_PACKET_SIZE 512
+#define FS_MAX_PACKET_SIZE 64
+/** ¿ØÖÆ´«Êä×î´ó°ü´óС */
+/** ¶ËµãÊýÄ¿ */
+#define ENDPOINTS_NUM 6
+/** ÐÒé¶ËµãÃèÊö·û */
+
+/** TRB¿ØÖÆÖи÷¸öλ¶ÎµÄºê¶¨Òå*/
+#define TRBCTL_NORMAL 1
+#define TRBCTL_CONTROL_SETUP 2
+#define TRBCTL_CONTROL_STATUS2 3
+#define TRBCTL_CONTROL_STATUS3 4
+#define TRBCTL_CONTROL_DATA 5
+#define TRBCTL_ISOCHRONOUS_FIRST 6
+#define TRBCTL_ISOCHRONOUS 7
+#define TRBCTL_LINK_TRB 8
+/** struct T_USB3Slave_TRBToHW - transfer request block (hw format) */
+typedef struct T_USB3Slave_TRBToHW
+{
+ u32 udBpl; /**< Ö¸ÏòbufferµÄµÍ32λµØÖ· */
+ u32 udBph; /**< Ö¸ÏòbufferµÄ¸ß32λµØÖ· */
+ u32 udSize; /**< Êý¾Ý´«ÊäµÄ³¤¶È */
+ u32 udCtrl; /**< TRB¿ØÖÆ */
+}__attribute__ ((__packed__)) T_USB3Slave_TRBToHW;
+
+/** struct T_USB3Slave_TRB - transfer request block */
+ typedef struct T_USB3Slave_TRB
+{
+ u64 bplh; /**< Ö¸ÏòbufferµØÖ· */
+
+ union
+ {
+ struct
+ {
+ u32 BUFSIZ:24; /**< Êý¾Ý´«ÊäµÄ³¤¶È */
+ u32 PCM1:2; /**< Packet Count M1 */
+ u32 Reserved27_26:2;
+ u32 TRBSTS:4; /**< TRB״̬ */
+ }bit;
+ u32 udVal;
+ }len_pcm;
+
+ union
+ {
+ struct
+ {
+ u32 HWO:1; /**< ָʾӲ¼þÓµÓеÄTRB */
+ u32 LST:1; /**< ×îºóÒ»¸öTRB */
+ u32 CHN:1; /**< ´ËTRBÓëÏÂÒ»¸öTRBÏà¹ØÁª */
+ u32 CSP:1; /**< µ±½ÓÊÕµ½Ò»¸ö¶Ì°ücore½«»á¼ÌÐøµ½ÏÂÒ»¸öBuffer Descriptor */
+ u32 TRBCTL:6; /**< TRB ¿ØÖÆ */
+ u32 ISP_IMI:1; /**< Interrupt on Short Packet/Interrupt on Missed ISOC */
+ u32 IOC:1; /**< Èç¹û±»ÉèÖ㬱íʾ´«ÊäÍê³Éºó²úÉúÖÐ¶Ï */
+ u32 Reserved13_12:2;
+ u32 StreamID_SOFNum:16; /**< Stream ID/SOF Number */
+ u32 Reserved31_30:2;
+ }bit;
+ u32 udVal;
+ }control;
+}__attribute__ ((__packed__)) T_USB3Slave_TRB;
+
+/** EVENT buffer´óС */
+#define EVENT_BUFFERS_SIZE 256//256
+
+/**
+* struct T_USB3Slave_EventBuf - Software event buffer representation
+*/
+
+typedef struct
+{
+ u32 EvtBuf[EVENT_BUFFERS_SIZE]; /**< ·ÖÅäµÄEVENT Buffer */
+ u32 udLength; /**< ·ÖÅäEVENT Buffer ´óС */
+ u32 udLpos; /**< ÓÃÓÚָʾµ±Ç°EVENTµÄÆðʼλÖà */
+}T_USB3Slave_EventBuf;
+
+
+/** EVENTÀàÐÍ */
+#define EVENT_TYPE_MASK 0xfe
+#define EVENT_TYPE_DEV 0
+#define EVENT_TYPE_CARKIT 3
+#define EVENT_TYPE_I2C 4
+typedef struct T_USB3Slave_EventType
+{
+ u32 udIs_devspec:1; /**< ÓÃÓÚÅжÏÊǶ˵ãÀàÐÍEVENT»¹ÊÇÉ豸ÀàÐÍEVENT */
+ u32 udType:6; /**< EVENT ÀàÐÍ */
+ u32 udReserved8_31:25;
+}__attribute__ ((__packed__)) T_USB3Slave_EventType;
+
+/** ¶ËµãÀàÐÍEVENTÀàÐÍ */
+#define DEPEVT_XFERCOMPLETE 0x01
+#define DEPEVT_XFERINPROGRESS 0x02
+#define DEPEVT_XFERNOTREADY 0x03
+#define DEPEVT_RXTXFIFOEVT 0x04
+#define DEPEVT_STREAMEVT 0x06
+#define DEPEVT_EPCMDCMPLT 0x07
+
+#define DEPEVT_STATUS_BUSERR (1 << 0)
+#define DEPEVT_STATUS_SHORT (1 << 1)
+#define DEPEVT_STATUS_IOC (1 << 2)
+#define DEPEVT_STATUS_LST (1 << 3)
+/** Stream event only */
+#define DEPEVT_STREAMEVT_FOUND 1
+#define DEPEVT_STREAMEVT_NOTFOUND 2
+/** Control-only Status */
+#define DEPEVT_STATUS_CONTROL_SETUP 0
+#define DEPEVT_STATUS_CONTROL_DATA 1
+#define DEPEVT_STATUS_CONTROL_STATUS 2
+#define DEPEVT_STATUS_STATUS_SETUP 10
+/**
+* struct dwc3_event_depvt - Device Endpoint Events
+* @udOne_bit: indicates this is an endpoint event (not used)
+* @udEndpoint_number: number of the endpoint
+* @udEndpoint_event: The event we have:
+* 0x00 - Reserved
+* 0x01 - XferComplete
+* 0x02 - XferInProgress
+* 0x03 - XferNotReady
+* 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
+* 0x05 - Reserved
+* 0x06 - StreamEvt
+* 0x07 - EPCmdCmplt
+* @udReserved11_10: Reserved, don't use.
+* @EventStatus: Indicates the status of the event. Refer to databook for more information.
+* @EventParam: Parameters of the current event. Refer to databook for more information.
+*/
+/** ²Î¼ûÊÖ²á7.2.8.1ÃèÊö¶ËµãÀàÐÍEVENT */
+ typedef struct T_USB3Slave_EpEvt
+{
+ u32 udOne_bit:1; /**< 1bitÓÃÓÚÅжÏÊǶ˵ãÀàÐÍevent»¹ÊÇÉ豸ÀàÐÍevent */
+ u32 udEndpoint_number:5; /**< ָʾÎïÀí¶ËµãºÅ */
+ u32 udEndpoint_event:4; /**< ָʾ¶ËµãÀàÐÍevent */
+ u32 udReserved11_10:2;
+ u32 EventStatus:4; /**< ָʾevent״̬£¬Refer to databook for more information*/
+ u32 EventParam:16; /**< µ±Ç°event²ÎÊý. Refer to databook for more information */
+}__attribute__ ((__packed__)) T_USB3Slave_EpEvt;
+
+/**
+* struct T_USB3Slave_DevEvt - Device Events
+* @udOne_bit: indicates this is a non-endpoint event (not used)
+* @udDevice_event: indicates it's a device event. Should read as 0x00
+* @udType: indicates the type of device event.
+* 0 - DisconnEvt
+* 1 - USBRst
+* 2 - ConnectDone
+* 3 - ULStChng
+* 4 - WkUpEvt
+* 5 - Reserved
+* 6 - EOPF
+* 7 - SOF
+* 8 - Reserved
+* 9 - ErrticErr
+* 10 - CmdCmplt
+* 11 - EvntOverflow
+* 12 - VndrDevTstRcved
+* @udReserved15_12: Reserved, not used
+* @udEvtInfo: Information about this event
+* @udReserved31_24: Reserved, not used
+*/
+/** DEVICE EVENT ÀàÐÍ */
+#define DEVICE_EVENT_DISCONNECT 0
+#define DEVICE_EVENT_RESET 1
+#define DEVICE_EVENT_CONNECT_DONE 2
+#define DEVICE_EVENT_LINK_STATUS_CHANGE 3
+#define DEVICE_EVENT_WAKEUP 4
+#define DEVICE_EVENT_EOPF 6
+#define DEVICE_EVENT_SOF 7
+#define DEVICE_EVENT_ERRATIC_ERROR 9
+#define DEVICE_EVENT_CMD_CMPL 10
+#define DEVICE_EVENT_OVERFLOW 11
+
+typedef struct T_USB3Slave_DevEvt
+{
+ u32 udOne_bit:1; /**< 1bitÓÃÓÚÅжÏÊǶ˵ãÀàÐÍevent»¹ÊÇÉ豸ÀàÐÍevent */
+ u32 udDevice_event:7; /**< É豸ÀàÐÍevent */
+ u32 udType:4; /**< ָʾ·¢ÉúµÄ¸÷ÖÖevent */
+ u32 udReserved15_12:4;
+ u32 udEvtInfo:8; /**< event ÐÅÏ¢±ÈÌØ¡£ÓÃÓÚָʾÊÇ·ñÊÇSSºÍlink state */
+ u32 udReserved31_24:8;
+}__attribute__ ((__packed__)) T_USB3Slave_DevEvt;
+
+/**
+* struct T_USB3Slave_Event_GEvt - Other Core Events
+* @udOne_bit: indicates this is a non-endpoint event (not used)
+* @udDevice_event: indicates it's (0x03) Carkit or (0x04) I2C event.
+* @udPhy_port_number: self-explanatory
+* @udReserved31_12: Reserved, not used.
+*/
+
+ typedef struct T_USB3Slave_Event_GEvt
+{
+ u32 udOne_bit:1;
+ u32 udDevice_event:7;
+ u32 udPhy_port_number:4;
+ u32 udReserved31_12:20;
+}__attribute__ ((__packed__)) T_USB3Slave_Event_GEvt;
+
+/** union T_USB3Slave_Event - representation of Event Buffer contents */
+
+typedef union
+{
+ u32 udRaw; /**< ָʾµ±Ç°eventµÄÖµ */
+ T_USB3Slave_EventType tType; /**< ָʾevent ÀàÐÍ(00h±íʾdevice specific event) */
+ T_USB3Slave_EpEvt tEpEvt; /**< ¶ËµãÀàÐÍevent */
+ T_USB3Slave_DevEvt tDevEvt; /**< É豸ÀàÐÍevent */
+ T_USB3Slave_Event_GEvt tGetEvt; /**< Other Core Events */
+}T_USB3Slave_Event;
+
+/** ¶¨ÒåEPµÄ±ê¼Çºê */
+#define EP_ENABLED (1 << 0)
+#define EP_STALL (1 << 1)
+#define EP_WEDGE (1 << 2)
+#define EP_BUSY (1 << 4)
+#define EP_PENDING_REQUEST (1 << 5)
+/** This last one is specific to EP0 */
+#define EP0_DIR_IN ((u32)1 << 31)
+/** EP񈬀 */
+#define EP_FLAG_STALLED (1 << 0)
+#define EP_FLAG_WEDGED (1 << 1)
+/** EP·½Ïò */
+#define EP_DIRECTION_TX true
+#define EP_DIRECTION_RX false
+
+/** ¶ËµãµÄ״̬±ä»¯*/
+typedef enum
+{
+ EP_IDLE = 0, /**< EP¿ÕÏÐ */
+ EP_HALTED, /**< EP halt */
+ EP0_CTRLIN_SETUP, /**< EP0¿ØÖƽ¨Á¢IN½×¶Î */
+ EP0_CTRLOUT_SETUP, /**< EP0¿ØÖƽ¨Á¢OUT½×¶Î */
+ EP0_CTRLNULL_SETUP, /**< EP0¿ØÖƽ¨Á¢Îª¿Õ */
+ EP0_CTRL_INDATA, /**< EP0¿ØÖÆINÊý¾Ý½×¶Î */
+ EP0_CTRL_OUTDATA, /**< EP0¿ØÖÆOUTÊý¾Ý½×¶Î */
+ EP0_CTRL_INSTATUS, /**< EP0¿ØÖÆIN״̬½×¶Î */
+ EP0_CTRL_OUTSTATUS, /**< EP0¿ØÖÆOUT״̬½×¶Î */
+ EP_RX, /**< EP½ÓÊÕ״ָ̬ʾ */
+ EP_TX /**< EP·¢ËÍ״ָ̬ʾ */
+}E_USB3Slave_EpState;
+
+/** ָʾEp0ÏÂÒ»¸öEVENTÀàÐÍ */
+typedef enum
+{
+ EP0_UNKNOWN = 0,
+ EP0_COMPLETE, /**< EP0״ָ̬ʾΪÍê³É*/
+ EP0_NRDY_SETUP, /**< EP0״̬NRDYָʾΪ½¨Á¢½×¶Î*/
+ EP0_NRDY_DATA, /**< EP0״̬NRDYָʾΪÊý¾Ý½×¶Î*/
+ EP0_NRDY_STATUS, /**< EP0״̬NRDYָʾΪ״̬½×¶Î*/
+} E_USB3Slave_Ep0Next;
+/** ָʾEP0¿ØÖÆ´«ÊäµÄÈý¸ö½×¶Î */
+typedef enum
+{
+ EP0_UNCONNECTED = 0,
+ EP0_SETUP_PHASE, /**< EP0¿ØÖÆ´«ÊäµÄ½¨Á¢½×¶Î */
+ EP0_DATA_PHASE, /**< EP0¿ØÖÆ´«ÊäµÄÊý¾Ý½×¶Î */
+ EP0_STATUS_PHASE, /**< EP0¿ØÖÆ´«ÊäµÄ״̬½×¶Î */
+}E_USB3Slave_Ep0State;
+/** ³¬¸ßËÙģʽϵÄÁ¬½Ó״̬ */
+
+
+/** ¿ØÖÆ´«ÊäÖÐö¾ÙËù´¦µÄ״̬½×¶Î */
+typedef enum
+{
+ DEFAULT_STATE = 0, /**< ȱʡ״̬ */
+ ADDRESS_STATE, /**< µØַ״̬ */
+ CONFIGURED_STATE, /**< ÅäÖÃ״̬ */
+ SETINTERFACE_STATE, /**< ÉèÖýӿÚ״̬*/
+ GETMAXLUN_STATE, /**<GET MAX lUN*/
+ BULKIN_CMPL, /**< BULK IN´«ÊäÍê³É״̬ */
+ BULKOUT_CMPL, /**< BULK OUT´«ÊäÍê³É״̬ */
+ IntrIN_CMPL, /**< Interrupt IN´«ÊäÍê³É״̬ */
+ IntrOUT_CMPL, /**< Interrupt OUT´«ÊäÍê³É״̬ */
+}E_USB3Slave_ReqState;
+
+/** ¶¨ÒåUSB3.0µÄËÙ¶ÈÀàÐÍ£¬²ÎÕÕ¿ØÖÆÆ÷ÊÖ²áP513, DCFG¼Ä´æÆ÷0:2±ÈÌØ */
+typedef enum
+{
+ USB3_HIGHSPEED = 0, /**< 3'b000 USB2.0 PHY clock is 30 MHz or 60 MHz */
+ USB3_FULLSPEED = 1, /**< 3'b001 USB2.0 PHY clock is 30 MHz or 60 MHz */
+ USB3_SUPERSPEED = 4, /**< 3'b100 USB3.0 PHY clock is 30 MHz or 60 MH */
+}E_USB3Slave_SpeedMode;
+/** ָʾÁ¬½ÓµÄÉ豸µÄËÙ¶ÈÀàÐÍ */
+typedef enum
+{
+ USB30_SPEED_UNKNOWN = 0, /**< enumerating */
+ USB30_SPEED_LOW, USB30_SPEED_FULL, /**< usb 1.1 */
+ USB30_SPEED_HIGH, /**< usb 2.0 */
+ USB30_SPEED_WIRELESS, /**< wireless (usb 2.5) */
+ USB30_SPEED_SUPER, /**< usb 3.0 */
+}E_USB3Slave_Speed;
+
+/** T_USB3Slave_HWPARAMS - copy of HWPARAMS registers */
+
+typedef struct
+{
+ u32 udHwparams0; /**< ¶ÔÓ¦ÓÚGHWPARAMS0¼Ä´æÆ÷¶ÁÈ¡µÄÖµ */
+ u32 udHwparams1; /**< ¶ÔÓ¦ÓÚGHWPARAMS1¼Ä´æÆ÷¶ÁÈ¡µÄÖµ */
+ u32 udHwparams2; /**< ¶ÔÓ¦ÓÚGHWPARAMS2¼Ä´æÆ÷¶ÁÈ¡µÄÖµ */
+ u32 udHwparams3; /**< ¶ÔÓ¦ÓÚGHWPARAMS3¼Ä´æÆ÷¶ÁÈ¡µÄÖµ */
+ u32 udHwparams4; /**< ¶ÔÓ¦ÓÚGHWPARAMS4¼Ä´æÆ÷¶ÁÈ¡µÄÖµ */
+ u32 udHwparams5; /**< ¶ÔÓ¦ÓÚGHWPARAMS5¼Ä´æÆ÷¶ÁÈ¡µÄÖµ */
+ u32 udHwparams6; /**< ¶ÔÓ¦ÓÚGHWPARAMS6¼Ä´æÆ÷¶ÁÈ¡µÄÖµ */
+ u32 udHwparams7; /**< ¶ÔÓ¦ÓÚGHWPARAMS7¼Ä´æÆ÷¶ÁÈ¡µÄÖµ */
+ u32 udHwparams8; /**< ¶ÔÓ¦ÓÚGHWPARAMS8¼Ä´æÆ÷¶ÁÈ¡µÄÖµ */
+}T_USB3Slave_HWPARAMS;
+
+
+/** ÓÃÓڶ˵ãÃüÁîµÄÈý¸ö²ÎÊý */
+ typedef struct T_USB3Slave_EpCmdPara
+{
+ u32 Parameter2; /**< ָʾÉ豸ÎïÀí¶ËµãÃüÁî²ÎÊý2 */
+ u32 Parameter1; /**< ָʾÉ豸ÎïÀí¶ËµãÃüÁî²ÎÊý1 */
+ u32 Parameter0; /**< ָʾÉ豸ÎïÀí¶ËµãÃüÁî²ÎÊý0 */
+}__attribute__ ((__packed__)) T_USB3Slave_EpCmdPara;
+
+/** DEPCFG parameter 1 */
+#define DEPCFG_INT_NUM(n) ((n) << 0)
+#define DEPCFG_XFER_COMPLETE_EN (1 << 8)
+#define DEPCFG_XFER_IN_PROGRESS_EN (1 << 9)
+#define DEPCFG_XFER_NOT_READY_EN (1 << 10)
+#define DEPCFG_FIFO_ERROR_EN (1 << 11)
+#define DEPCFG_STREAM_EVENT_EN (1 << 13)
+#define DEPCFG_BINTERVAL_M1(n) ((n) << 16)
+#define DEPCFG_STREAM_CAPABLE (1 << 24)
+#define DEPCFG_EP_NUMBER(n) ((n) << 25)
+#define DEPCFG_BULK_BASED (1 << 30)
+#define DEPCFG_FIFO_BASED (1 << 31)
+
+/** DEPCFG parameter 0 */
+#define DEPCFG_EP_TYPE(n) ((n) << 1)
+#define DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3)
+#define DEPCFG_FIFO_NUMBER(n) ((n) << 17)
+#define DEPCFG_BURST_SIZE(n) ((n) << 22)
+#define DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
+#define DEPCFG_IGN_SEQ_NUM (1 << 31)
+
+/** DEPXFERCFG parameter 0 */
+#define DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
+
+/** ¶ËµãÐÅÏ¢½á¹¹Ìå */
+#pragma pack (4) /*Ö¸¶¨°´4×Ö½Ú¶ÔÆë*/
+typedef struct
+{
+
+ u32 udEpNum; /**< µ±Ç°epºÅ */
+ u8 *pucBuf; /**< »º³åÇøÖ¸Õë */
+ u32 udPos; /**< »º³åÇø¶ÁдָÕë */
+ u32 udLen; /**< »º³åÇø×ܳ¤¶È */
+ u32 udMaxPacket; /**< ×î´ó°üµÄ´óС */
+ u32 udMaxStream; /**< Ö§³ÖµÄ×î´óÁ÷Êý */
+ u32 udMaxBurst; /**< ¸Ã¶ËµãÖ§³ÖµÄ×î´óburstÊý */
+ T_USB3Slave_TRBToHW *ptTRB; /**< ×¼±¸ÓÃÓÚtrbµÄ»º³åÇø */
+ u32 udDMAChannel; /**< ¶ËµãʹÓõÄdmaͨµÀ, ¸ß16Ϊģʽ£¬µÍ16ΪͨµÀºÅ */
+ u8 ucType; /**< Ö§³ÖµÄ´«ÊäÀàÐÍ */
+ void *pPara; /**< »Øµ÷º¯ÊýµÄ²ÎÊý */
+ E_USB3Slave_EpState eEpState; /**< ¶Ëµã״̬ */
+ u32 udDirection; /**< ¶Ëµã´«Êä·½Ïò * @direction: true for TX, false for RX */
+ void *DriverData; /**< Êý¾ÝÓÃÓÚ´«Êä,ºóÐøµ÷ÊÔ¿ÉÄÜ»áÓõ½*/
+ u32 udInterval; /**< ¶ËµãµÄInterval */
+ u32 udBusySlot; /**< ´¦ÓÚæ״̬TRB¸öÊý */
+ u32 udFreeSlot; /**< ´¦ÓÚ¿ÕÏÐ״̬TRB¸öÊý */
+ u32 *pudAddrData; /**< Ä¿Ç°Ö÷ÒªÊÇBULK´«ÊäÓÃÓÚ½ÓÊպͷ¢ËÍÊý¾ÝµÄµØÖ· */
+ u8 ucAddress; /**< µØÖ· */
+ u32 udFlags; /**< ¶Ëµã±ê¼Ç */
+ u32 udCurrentTrb; /**< µ±Ç°TRB */
+ u8 ucResTransIdx; /**< ´«Êä×ÊÔ´Ë÷Òý */
+ u32 udStreamCapable; /**< ÊÇ·ñ¾ßÓÐÁ÷ÄÜÁ¦ */
+ F_USB_CB fnUsbCb; //¶Ëµã²Ù×÷Íê³ÉºóµÄ»Øµ÷º¯Êý
+}T_USB3Slave_Ep;
+#pragma pack () /*È¡Ïû¶ÔÆë*/
+/** struct dwc3 - representation of our controller */
+/** È«¾ÖdeviceÐÅÏ¢½á¹¹Ì壬ÓÃÓÚÈí¼þ */
+#pragma pack (4) /*Ö¸¶¨°´4×Ö½Ú¶ÔÆë*/
+typedef struct
+{
+
+ u32 udRegs_base; /**< ¼Ç¼¼Ä´æÆ÷»ùÖ· */
+ E_USB3Slave_SpeedMode eSpeedMode; /**< µ±Ç°É豸µÄËÙ¶È */
+ E_USB3Slave_Speed eDeviceSpeedType; /**< ËÙ¶ÈÀàÐÍ£¬¼æÈÝlinuxÇý¶¯Ëù×÷£¬¾ßÌåʹÓôýÒé */
+ T_USB3Slave_HWPARAMS tHwParams; /**< ±£´æËùÓÐÓ²¼þ²ÎÊý */
+ u32 udMode; /**< ±£´æ¿ØÖÆÆ÷µ±Ç°Ëù´¦Ä£Ê½ */
+ T_USB3Slave_EventBuf *ptEvtBuffs; /**< ±£´æevent */
+ u32 udNumEvtBufs; /**< ¼Ç¼evnet¸öÊý£¬´ÓÓ²¼þ²ÎÊýÖлñµÃ*/
+ T_USB3Slave_Ep tEps[ENDPOINTS_NUM]; /**< ±£´æ¶ËµãÐÅÏ¢ */
+ u32 udIsSelfPowered; /**< ×Ô¹©µçture*/
+ u32 udThreeStageSetup; /**< Èý½×¶ÎÉèÖÃ*/
+ u32 udEp0Bounced; /**< bounce buffer for ep0 */
+ u32 udEp0ExpectIn; /**< true when we expect a DATA IN transfer */
+ u32 udSetupPacketPending; /**< true when there's a Setup Packet in FIFO. Workaround */
+ u32 udDelayedStatus; /**< ÑÓ³Ù״̬*/
+ u32 udEventsequence; /**< eventÐòºÅ */
+ E_USB3Slave_Ep0Next eEp0NextEvent; /**< ָʾ¶ËµãµÄÏÂÒ»¸öEVENT */
+ E_USB3Slave_Ep0State eEp0State; /**< ep0״̬*/
+ E_USB3Slave_ReqState eDevState; /**< É豸״̬ */
+ u32 udUSBSate; /**< ö¾Ù״̬ */
+/*ÒÔÏÂÊý¾Ý³ÉÔ±³¤¶ÈÉèÖòÎÕÕlinux 3.3.6ÖжÔusb3¿ØÖÆÆ÷µÄ³õʼº¯Êý*/
+ T_USB3Slave_CtrlReq *tCtrlReq; /**< ¿ØÖÆÇëÇó */
+ T_USB3Slave_TRBToHW *ptEp0TRB; /**< ep0 TRBÉèÖÃ*/
+ u8 aucSetupBuf[2]; /**< ½¨Á¢buffer δÓÃÄ¿Ç° */
+ u8 ucSpeed; /**< ËÙ¶È */
+ u32 *pudTxData; /**< Ö¸Ïò·¢Ë͵ÄÊý¾Ý´óС */
+}T_USB3Slave_SlaveObj;
+#pragma pack () /*È¡Ïû¶ÔÆë*/
+
+/** ¶¨ÒåSlaveObj ¶ÔÏóµÄÈ«¾Ö±äÁ¿*/
+
+/** DWC3 Features to be used as Driver Data ĿǰûÓÐÓõ½ÔÝʱ·ÅÔÚÕâÀï*/
+/*#define HAS_PERIPHERAL BIT(0)
+#define HAS_XHCI BIT(1)
+#define HAS_OTG BIT(3)*/
+#define DATA_32BIT_MASK 0xFFFFFFFF
+#define ADDRESS_MAX 127
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+}
+#endif
+/* *INDENT-ON* */
+
+#endif /* __USB3_SLAVE_DRV_H */
+
+
+/** @} */
diff --git a/boot/common/src/uboot/include/usb/drv_usb3slave_reg.h b/boot/common/src/uboot/include/usb/drv_usb3slave_reg.h
new file mode 100644
index 0000000..3ec2de5
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/drv_usb3slave_reg.h
@@ -0,0 +1,95 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ£º drv_usb3slave_reg.h
+* Îļþ±êʶ£º
+* ÄÚÈÝÕªÒª£º
+* ÆäËü˵Ã÷£º zx297520 project
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº tangjian
+* Íê³ÉÈÕÆÚ£º
+*
+*
+*******************************************************************************/
+
+
+#ifndef __DRV_USB3SLAVE_REG_H
+#define __DRV_USB3SLAVE_REG_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#include "common.h"
+
+
+/** ÏÂÃæµÄ¼¸¸ö¼Ä´æÆ÷µÄ¸ñʽÓÐЩÌر𣬼ĴæÆ÷ÊDz»Á¬ÐøµÄ£¬¹Ê±£ÁôÁËlinuxÖмĴæÆ÷µÄ¸ñʽ*/
+
+ /*0x200-0x23c*/
+#define GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
+
+ /*0x240-0x27c*/
+#define GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
+
+ /*0x280-0x2bc*/
+#define GUSB2PHYACC(n) (0xc280 + (n * 0x04))
+
+ /*0x2C0-0x2fc*/
+#define GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
+
+ /*0x300-0x37C*/
+#define GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
+
+ /*0x380-0x3fc*/
+#define GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
+
+#define GHWPARAMS0 0xc140
+#define GHWPARAMS1 0xc144
+#define GHWPARAMS2 0xc148
+#define GHWPARAMS3 0xc14c
+#define GHWPARAMS4 0xc150
+#define GHWPARAMS5 0xc154
+#define GHWPARAMS6 0xc158
+#define GHWPARAMS7 0xc15c
+#define GHWPARAMS8 0xc600
+
+#define GEVNTADRLO(n) (0xc400 + (n * 0x10))
+#define GEVNTADRHI(n) (0xc404 + (n * 0x10))
+#define GEVNTSIZ(n) (0xc408 + (n * 0x10))
+#define GEVNTCOUNT(n) (0xc40c + (n * 0x10))
+
+#define DEPCMDPAR2(n) (0xc800 + (n * 0x10))
+#define DEPCMDPAR1(n) (0xc804 + (n * 0x10))
+#define DEPCMDPAR0(n) (0xc808 + (n * 0x10))
+#define DEPCMD(n) (0xc80c + (n * 0x10))
+
+/** @} */
+/* RAMʱÖÓÑ¡Ôñλ */
+#define USB3Slave_GCTL_RAMCLKSEL_POS (6)
+#define USB3Slave_GCTL_CLK_BUS (0 << USB3Slave_GCTL_RAMCLKSEL_POS)
+
+#define USB3Slave_DEPCMD_COMMANDPARAM_POS (16)
+#define USB2Slave_DEPCMD_PARAM(x) (x << USB3Slave_DEPCMD_COMMANDPARAM_POS)
+/* ÃüÁ»îÉèÖÃλ */
+//#define USB3Slave_DEPCMD_CMDACT USB3Slave_DEPCMD_CMDACT
+#define USB3Slave_DEPCMD_CMDACT_POS (10)
+#define USB3Slave_DEPCMD_CMDACT_1 (1 << USB3Slave_DEPCMD_CMDACT_POS)
+/* ÃüÁîÀàÐÍ */
+//#define USB3Slave_DEPCMD_CMDTYP USB3Slave_DEPCMD_CMDTYP
+#define USB3Slave_DEPCMD_CMDTYP_POS (0)
+#define USB3Slave_DEPCMD_DEPSTARTCFG (0x09 << USB3Slave_DEPCMD_CMDTYP_POS)
+#define USB3Slave_DEPCMD_ENDTRANSFER (0x08 << USB3Slave_DEPCMD_CMDTYP_POS)
+#define USB3Slave_DEPCMD_UPDATETRANSFER (0x07 << USB3Slave_DEPCMD_CMDTYP_POS)
+#define USB3Slave_DEPCMD_STARTTRANSFER (0x06 << USB3Slave_DEPCMD_CMDTYP_POS)
+#define USB3Slave_DEPCMD_CLEARSTALL (0x05 << USB3Slave_DEPCMD_CMDTYP_POS)
+#define USB3Slave_DEPCMD_SETSTALL (0x04 << USB3Slave_DEPCMD_CMDTYP_POS)
+#define USB3Slave_DEPCMD_GETSEQNUMBER (0x03 << USB3Slave_DEPCMD_CMDTYP_POS)
+#define USB3Slave_DEPCMD_SETTRANSFRESOURCE (0x02 << USB3Slave_DEPCMD_CMDTYP_POS)
+#define USB3Slave_DEPCMD_SETEPCONFIG (0x01 << USB3Slave_DEPCMD_CMDTYP_POS)
+
+#endif /* __DRV_USB3SLAVE_REG_H */
+
+
+
diff --git a/boot/common/src/uboot/include/usb/dwc_otg_cil.h b/boot/common/src/uboot/include/usb/dwc_otg_cil.h
new file mode 100644
index 0000000..acaa91a
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/dwc_otg_cil.h
@@ -0,0 +1,404 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
+ * $Revision: #123 $
+ * $Date: 2012/08/10 $
+ * $Change: 2047372 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+#ifndef __DWC_CIL_H__
+#define __DWC_CIL_H__
+
+#include "dwc_otg_regs.h"
+
+#include "dwc_otg_core_if.h"
+
+//ÊÕ·¢»Øµ÷º¯ÊýµÄÔÐÍ
+typedef void (*F_USB_CB)(WORD32 dwPara, WORD32 dwResult, WORD32 dwLen, WORD32 dwWantLen);
+
+
+/** Macros defined for DWC OTG HW Release version */
+
+#define OTG_CORE_REV_2_60a 0x4F54260A
+#define OTG_CORE_REV_2_94a 0x4F54294A
+/**
+ * The <code>dwc_ep</code> structure represents the state of a single
+ * endpoint when acting in device mode. It contains the data items
+ * needed for an endpoint to be activated and transfer packets.
+ */
+#define DWC_OTG_EP_TYPE_ISOC 1
+#define DWC_OTG_EP_TYPE_BULK 2
+#define DWC_OTG_EP_TYPE_INTR 3
+
+typedef struct dwc_ep
+{
+ /** EP number used for register address lookup */
+ uint8_t num;
+ /** EP direction 0 = OUT */
+ unsigned is_in;//:1;
+ /** EP active. */
+ unsigned active;//:1;
+ /**
+ * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
+ * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
+ unsigned tx_fifo_num;//:4;
+ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
+ unsigned type;//:2;
+ /** DATA start PID for INTR and BULK EP */
+ unsigned data_pid_start;//:1;
+ /** Frame (even/odd) for ISOC EP */
+ unsigned even_odd_frame;//:1;
+ /** Max Packet bytes */
+ unsigned maxpacket;//:11;
+
+ /** Max Transfer size */
+ uint32_t maxxfer;
+
+ F_USB_CB fnUsbCb;
+
+ void *pPara;
+
+ uint8_t *start_xfer_buff;
+ /** pointer to the transfer buffer */
+ uint8_t *xfer_buff;
+ /** Number of bytes to transfer */
+ unsigned xfer_len;//:19;
+ /** Number of bytes transferred. */
+ unsigned xfer_count;//:19;
+ /** Sent ZLP */
+ unsigned sent_zlp;//:1;
+ /** Total len for control transfer */
+ unsigned total_len;//:19;
+
+ /** stall clear flag */
+ unsigned stall_clear_flag;//:1;
+
+ /** SETUP pkt cnt rollover flag for EP0 out*/
+ unsigned stp_rollover;
+
+} dwc_ep_t;
+
+/**
+ * The following parameters may be specified when starting the module. These
+ * parameters define how the DWC_otg controller should be configured.
+ */
+typedef struct dwc_otg_core_params
+{
+ /**
+ * Specifies the OTG capabilities. The driver will automatically
+ * detect the value for this parameter if none is specified.
+ * 0 - HNP and SRP capable (default)
+ * 1 - SRP Only capable
+ * 2 - No HNP/SRP capable
+ */
+ int32_t otg_cap;
+
+
+ /**
+ * Specifies the maximum speed of operation in host and device mode.
+ * The actual speed depends on the speed of the attached device and
+ * the value of phy_type. The actual speed depends on the speed of the
+ * attached device.
+ * 0 - High Speed (default)
+ * 1 - Full Speed
+ */
+ int32_t speed;
+
+ /**
+ * Specifies the type of PHY interface to use. By default, the driver
+ * will automatically detect the phy_type.
+ *
+ * 0 - Full Speed PHY
+ * 1 - UTMI+ (default)
+ * 2 - ULPI
+ */
+ int32_t phy_type;
+
+ /**
+ * Specifies the UTMI+ Data Width. This parameter is
+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
+ * PHY_TYPE, this parameter indicates the data width between
+ * the MAC and the ULPI Wrapper.) Also, this parameter is
+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
+ * to "8 and 16 bits", meaning that the core has been
+ * configured to work at either data path width.
+ *
+ * 8 or 16 bits (default 16)
+ */
+ int32_t phy_utmi_width;
+
+ /**
+ * Specifies whether the ULPI operates at double or single
+ * data rate. This parameter is only applicable if PHY_TYPE is
+ * ULPI.
+ *
+ * 0 - single data rate ULPI interface with 8 bit wide data
+ * bus (default)
+ * 1 - double data rate ULPI interface with 4 bit wide data
+ * bus
+ */
+ int32_t phy_ulpi_ddr;
+
+ /**
+ * Specifies whether to use the internal or external supply to
+ * drive the vbus with a ULPI phy.
+ */
+ int32_t phy_ulpi_ext_vbus;
+
+ int32_t ulpi_fs_ls;
+
+ int32_t ts_dline;
+
+ /**
+ * Specifies whether dedicated transmit FIFOs are
+ * enabled for non periodic IN endpoints in device mode
+ * 0 - No
+ * 1 - Yes
+ */
+ int32_t en_multiple_tx_fifo;
+
+ /** Number of 4-byte words in each of the Tx FIFOs in device
+ * mode when dynamic FIFO sizing is enabled.
+ * 4 to 768 (default 256)
+ */
+ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
+
+ /** Thresholding enable flag-
+ * bit 0 - enable non-ISO Tx thresholding
+ * bit 1 - enable ISO Tx thresholding
+ * bit 2 - enable Rx thresholding
+ */
+ //uint32_t thr_ctl;
+
+ /** Thresholding length for Tx
+ * FIFOs in 32 bit DWORDs
+ */
+ //uint32_t tx_thr_length;
+
+ /** Thresholding length for Rx
+ * FIFOs in 32 bit DWORDs
+ */
+ //uint32_t rx_thr_length;
+
+
+ /** Per Transfer Interrupt
+ * mode enable flag
+ * 1 - Enabled
+ * 0 - Disabled
+ */
+ int32_t pti_enable;
+
+
+ /** HFIR Reload Control
+ * 0 - The HFIR cannot be reloaded dynamically.
+ * 1 - Allow dynamic reloading of the HFIR register during runtime.
+ */
+ //int32_t reload_ctl;
+ /** DCFG: Enable device Out NAK
+ * 0 - The core does not set NAK after Bulk Out transfer complete.
+ * 1 - The core sets NAK after Bulk OUT transfer complete.
+ */
+ int32_t dev_out_nak;
+
+
+ /** OTG revision supported
+ * 0 - OTG 1.3 revision
+ * 1 - OTG 2.0 revision
+ */
+ int32_t otg_ver;
+
+} dwc_otg_core_params_t;
+/**
+ * The <code>dwc_otg_core_if</code> structure contains information needed to manage
+ * the DWC_otg controller acting in either host or device mode. It
+ * represents the programming view of the controller as a whole.
+ */
+#define DWC_OTG_PCGCCTL_OFFSET 0xE00
+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
+#define DWC_OTG_DATA_FIFO_SIZE 0x1000
+#define A_HOST (1)
+#define A_SUSPEND (2)
+#define A_PERIPHERAL (3)
+#define B_PERIPHERAL (4)
+#define B_HOST (5)
+
+struct dwc_otg_core_if
+{
+ dwc_otg_core_params_t *core_params;
+
+ dwc_otg_core_global_regs_t *core_global_regs;
+
+ dwc_otg_dev_if_t *dev_if;
+ uint8_t phy_init_done;
+
+
+ volatile uint32_t *pcgcctl;
+
+ uint32_t *data_fifo[MAX_EPS_CHANNELS];
+
+ uint16_t total_fifo_size;
+ uint16_t rx_fifo_size;
+ uint16_t nperio_tx_fifo_size;
+
+ uint8_t pti_enh_enable;
+
+ uint8_t multiproc_int_enable;
+
+ uint8_t en_multiple_tx_fifo;
+
+ hwcfg1_data_t hwcfg1;
+ hwcfg2_data_t hwcfg2;
+ hwcfg3_data_t hwcfg3;
+ hwcfg4_data_t hwcfg4;
+ fifosize_data_t hptxfsiz;
+ dcfg_data_t dcfg;
+
+ uint32_t otg_ver;
+
+};
+
+extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
+
+extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
+ uint32_t * _dest);
+extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
+ dwc_ep_t * _ep);
+extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
+ dwc_ep_t * _ep);
+extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
+ dwc_ep_t * _ep);
+extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
+ dwc_ep_t * _ep);
+extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
+ dwc_ep_t * _ep, int _dma);
+extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
+ dwc_ep_t * _ep);
+extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
+
+void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
+
+
+extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
+ uint8_t * dest, uint16_t bytes);
+
+extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
+extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
+extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
+
+#if 0
+/**
+ * This function returns the Core Interrupt register.
+ */
+static uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
+{
+ return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
+ DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
+}
+
+
+/**
+ * This function reads the Device All Endpoints Interrupt register and
+ * returns the IN endpoint interrupt bits.
+ */
+static uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
+ core_if)
+{
+
+ uint32_t v;
+ {
+ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
+ }
+ return (v & 0xffff);
+}
+
+/**
+ * This function reads the Device All Endpoints Interrupt register and
+ * returns the OUT endpoint interrupt bits.
+ */
+static uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
+ core_if)
+{
+ uint32_t v;
+
+ {
+ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
+ }
+
+ return ((v & 0xffff0000) >> 16);
+}
+
+/**
+ * This function returns the Device IN EP Interrupt register
+ */
+static uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
+ dwc_ep_t * ep)
+{
+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+ uint32_t v, msk, emp;
+
+ {
+ msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
+ emp = DWC_READ_REG32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
+ msk |= ((emp >> ep->num) & 0x1) << 7;
+ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
+ }
+
+ return v;
+}
+
+/**
+ * This function returns the Device OUT EP Interrupt register
+ */
+static uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if, dwc_ep_t * _ep)
+{
+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
+ uint32_t v;
+ doepmsk_data_t msk;
+ msk.d32 = 0;
+ {
+ msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
+ if (_core_if->pti_enh_enable)
+ {
+ msk.b.pktdrpsts = 1;
+ }
+ v = DWC_READ_REG32(&dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
+ }
+ return v;
+}
+
+static uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
+{
+ return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
+}
+#endif
+#endif
diff --git a/boot/common/src/uboot/include/usb/dwc_otg_core_if.h b/boot/common/src/uboot/include/usb/dwc_otg_core_if.h
new file mode 100644
index 0000000..099ae62
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/dwc_otg_core_if.h
@@ -0,0 +1,109 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
+ * $Revision: #13 $
+ * $Date: 2012/08/10 $
+ * $Change: 2047372 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#if !defined(__DWC_CORE_IF_H__)
+#define __DWC_CORE_IF_H__
+#include "common.h"
+struct dwc_otg_core_if;
+typedef struct dwc_otg_core_if dwc_otg_core_if_t;
+
+#define DWC_E_NOT_SUPPORTED 1004
+#define DWC_E_INVALID 1001
+#define DWC_E_NO_MEMORY 1002
+#define DWC_E_NO_DEVICE 1003
+#define DWC_E_SHUTDOWN 1010
+
+/** Maximum number of Periodic FIFOs */
+#define MAX_TX_FIFOS 15
+
+/** Maximum number of Endpoints/HostChannels */
+#define MAX_EPS_CHANNELS 3
+
+extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
+extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
+
+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
+#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
+#define dwc_param_opt_default 1
+#define dwc_param_dma_enable_default 1
+#define dwc_param_dma_desc_enable_default 1
+#define dwc_param_dma_burst_size_default 32
+#define dwc_param_speed_default 0
+#define DWC_SPEED_PARAM_HIGH 0
+#define DWC_SPEED_PARAM_FULL 1
+#define dwc_param_host_support_fs_ls_low_power_default 0
+#define dwc_param_host_ls_low_power_phy_clk_default 0
+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
+#define dwc_param_enable_dynamic_fifo_default 1
+#define dwc_param_data_fifo_size_default 8192
+#define dwc_param_dev_rx_fifo_size_default 1064
+#define dwc_param_dev_nperio_tx_fifo_size_default 1024
+#define dwc_param_dev_perio_tx_fifo_size_default 256
+#define dwc_param_host_rx_fifo_size_default 1024
+#define dwc_param_host_nperio_tx_fifo_size_default 1024
+#define dwc_param_host_perio_tx_fifo_size_default 1024
+#define dwc_param_max_transfer_size_default 65535
+#define dwc_param_max_packet_count_default 511
+#define dwc_param_host_channels_default 12
+#define dwc_param_dev_endpoints_default 6
+#define DWC_PHY_TYPE_PARAM_FS 0
+#define DWC_PHY_TYPE_PARAM_UTMI 1
+#define DWC_PHY_TYPE_PARAM_ULPI 2
+#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
+#define dwc_param_phy_utmi_width_default 16
+#define dwc_param_phy_ulpi_ddr_default 0
+#define DWC_PHY_ULPI_INTERNAL_VBUS 0
+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
+#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
+#define dwc_param_i2c_enable_default 0
+#define dwc_param_ulpi_fs_ls_default 0
+#define dwc_param_ts_dline_default 0
+#define dwc_param_en_multiple_tx_fifo_default 1
+#define dwc_param_dev_tx_fifo_size_default 768
+#define dwc_param_thr_ctl_default 0
+#define dwc_param_tx_thr_length_default 64
+#define dwc_param_rx_thr_length_default 64
+#define dwc_param_lpm_enable_default 1
+#define dwc_param_pti_enable_default 0
+#define dwc_param_mpi_enable_default 0
+#define dwc_param_adp_enable_default 0
+#define dwc_param_ic_usb_cap_default 0
+#define dwc_param_ahb_thr_ratio_default 0
+#define dwc_param_power_down_default 0
+#define dwc_param_reload_ctl_default 0
+#define dwc_param_dev_out_nak_default 0
+#define dwc_param_cont_on_bna_default 0
+#define dwc_param_ahb_single_default 0
+
+#endif /* __DWC_CORE_IF_H__ */
diff --git a/boot/common/src/uboot/include/usb/dwc_otg_driver.h b/boot/common/src/uboot/include/usb/dwc_otg_driver.h
new file mode 100644
index 0000000..85152fd
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/dwc_otg_driver.h
@@ -0,0 +1,81 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
+ * $Revision: #19 $
+ * $Date: 2010/11/15 $
+ * $Change: 1627671 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+#ifndef __DWC_OTG_DRIVER_H__
+#define __DWC_OTG_DRIVER_H__
+
+
+
+
+#define DWC_DEVICE_ONLY
+#define DEV_FIRST
+/** @file
+ * This file contains the interface to the Linux driver.
+ */
+
+#include "usb.h"
+#include "dwc_otg_core_if.h"
+#include "dwc_otg_pcd.h"
+
+
+/* Type declarations */
+struct dwc_otg_pcd;
+/**
+ * This structure is a wrapper that encapsulates the driver components used to
+ * manage a single DWC_otg controller.
+ */
+typedef struct dwc_otg_device
+{
+
+ /** Pointer to the core interface structure. */
+ dwc_otg_core_if_t *core_if;
+
+ /** Pointer to the PCD structure. */
+ struct dwc_otg_pcd *pcd;
+
+} dwc_otg_device_t;
+
+//add by 10136329 for charger or PC
+enum plug_in
+{
+ DEFAULT,
+ COMPUTER,
+ CHARGER
+};
+
+
+
+int dwc_otg_driver_probe(WORD32 USB_ADDR);
+
+
+#endif
diff --git a/boot/common/src/uboot/include/usb/dwc_otg_pcd.h b/boot/common/src/uboot/include/usb/dwc_otg_pcd.h
new file mode 100644
index 0000000..2e89567
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/dwc_otg_pcd.h
@@ -0,0 +1,189 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
+ * $Revision: #48 $
+ * $Date: 2012/08/10 $
+ * $Change: 2047372 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_HOST_ONLY
+#if !defined(__DWC_PCD_H__)
+#define __DWC_PCD_H__
+#include "usb.h"
+#include "dwc_otg_cil.h"
+#include "dwc_otg_pcd_if.h"
+#include "type.h"
+/**
+ * @file
+ *
+ * This file contains the structures, constants, and interfaces for
+ * the Perpherial Contoller Driver (PCD).
+ *
+ * The Peripheral Controller Driver (PCD) for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used. For
+ * the Mass Storage Function driver the File-backed USB Storage Gadget
+ * (FBS) driver will be used. The FBS driver supports the
+ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
+ * transports.
+ *
+ */
+
+/**
+ * Get the pointer to the core_if from the pcd pointer.
+ */
+#define GET_CORE_IF( _pcd ) (_pcd->core_if)
+
+/**
+ * States of EP0.
+ */
+typedef enum ep0_state
+{
+ EP0_DISCONNECT, /* no host */
+ EP0_IDLE,
+ EP0_IN_DATA_PHASE,
+ EP0_OUT_DATA_PHASE,
+ EP0_IN_STATUS_PHASE,
+ EP0_OUT_STATUS_PHASE,
+ EP0_STALL,
+} ep0state_e;
+
+/** Fordward declaration.*/
+struct dwc_otg_pcd;
+
+/** DWC_otg request structure.
+ * This structure is a list of requests.
+ */
+typedef struct dwc_otg_pcd_request
+{
+ void *priv;
+ void *buf;
+ uint32_t dma;
+ uint32_t length;
+ uint32_t actual;
+ unsigned sent_zlp:1;
+ /**
+ * Used instead of original buffer if
+ * it(physical address) is not dword-aligned.
+ **/
+ uint8_t *dw_align_buf;
+ uint32_t dw_align_buf_dma;
+} dwc_otg_pcd_request_t;
+
+/** PCD EP structure.
+ * This structure describes an EP, there is an array of EPs in the PCD
+ * structure.
+ */
+typedef struct dwc_otg_pcd_ep
+{
+ /** USB EP Descriptor */
+ const usb_endpoint_descriptor_t *desc;
+
+ /** queue of dwc_otg_pcd_requests. */
+ unsigned stopped:1;
+ unsigned disabling:1;
+ unsigned dma:1;
+ unsigned queue_sof:1;
+ dwc_ep_t dwc_ep;
+
+ /** Pointer to PCD */
+ struct dwc_otg_pcd *pcd;
+
+ void *priv;
+} dwc_otg_pcd_ep_t;
+
+/** DWC_otg PCD Structure.
+ * This structure encapsulates the data for the dwc_otg PCD.
+ */
+
+typedef union
+{
+ usb_device_request_t req;
+ uint32_t d32[2];
+}u_setup_pkt;
+
+struct dwc_otg_pcd
+{
+ /** The DWC otg device pointer */
+ struct dwc_otg_device *otg_dev;
+ /** Core Interface */
+ dwc_otg_core_if_t *core_if;
+ /** State of EP0 */
+ ep0state_e ep0state;
+ /** EP0 Request is pending */
+ unsigned ep0_pending;
+ /** Indicates when SET CONFIGURATION Request is in process */
+ unsigned request_config;
+ unsigned request_pending;
+
+ /** SETUP packet for EP0
+ * This structure is allocated as a DMA buffer on PCD initialization
+ * with enough space for up to 3 setup packets.
+ */
+ u_setup_pkt *setup_pkt;
+
+ uint32_t setup_pkt_dma_handle;
+ /* Additional buffer and flag for CTRL_WR premature case */
+ uint8_t *backup_buf;
+ unsigned data_terminated;
+
+ /** 2-byte dma buffer used to return status from GET_STATUS */
+ uint16_t *status_buf;
+ uint32_t status_buf_dma_handle;
+ /** EP0 */
+ dwc_otg_pcd_ep_t ep0;
+
+ /** Array of IN EPs. */
+ dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
+ /** Array of OUT EPs. */
+ dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
+
+#ifdef DWC_UTE_CFI
+ cfiobject_t *cfi;
+#endif
+
+};
+
+#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
+do { \
+ doepint_data_t doepint ; \
+ doepint.d32 = 0;\
+ doepint.b.__intr = 1; \
+ DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
+ doepint.d32); \
+} while (0)
+
+#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
+do { \
+ diepint_data_t diepint; \
+ diepint.d32 = 0;\
+ diepint.b.__intr = 1; \
+ DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
+ diepint.d32); \
+} while (0)
+
+#endif
+#endif /* DWC_HOST_ONLY */
diff --git a/boot/common/src/uboot/include/usb/dwc_otg_pcd_if.h b/boot/common/src/uboot/include/usb/dwc_otg_pcd_if.h
new file mode 100755
index 0000000..84bca4e
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/dwc_otg_pcd_if.h
@@ -0,0 +1,60 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
+ * $Revision: #11 $
+ * $Date: 2011/10/26 $
+ * $Change: 1873028 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_HOST_ONLY
+
+#if !defined(__DWC_PCD_IF_H__)
+#define __DWC_PCD_IF_H__
+#include "dwc_otg_core_if.h"
+#include "dwc_otg_pcd.h"
+#include <linux/types.h>
+/** @file
+ * This file defines DWC_OTG PCD Core API.
+ */
+
+typedef struct dwc_otg_pcd dwc_otg_pcd_t;
+
+/** Maxpacket size for EP0 */
+#define MAX_EP0_SIZE 64
+
+extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
+
+extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd);
+
+extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
+ const uint8_t * ep_desc, void *usb_ep);
+
+extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
+
+#endif /* __DWC_PCD_IF_H__ */
+
+#endif /* DWC_HOST_ONLY */
diff --git a/boot/common/src/uboot/include/usb/dwc_otg_regs.h b/boot/common/src/uboot/include/usb/dwc_otg_regs.h
new file mode 100644
index 0000000..5f1c0e5
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/dwc_otg_regs.h
@@ -0,0 +1,1593 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
+ * $Revision: #98 $
+ * $Date: 2012/08/10 $
+ * $Change: 2047372 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+#ifndef __DWC_OTG_REGS_H__
+#define __DWC_OTG_REGS_H__
+#include "dwc_otg_core_if.h"
+
+/**
+ * @file
+ *
+ * This file contains the data structures for accessing the DWC_otg core registers.
+ *
+ * The application interfaces with the HS OTG core by reading from and
+ * writing to the Control and Status Register (CSR) space through the
+ * AHB Slave interface. These registers are 32 bits wide, and the
+ * addresses are 32-bit-block aligned.
+ * CSRs are classified as follows:
+ * - Core Global Registers
+ * - Device Mode Registers
+ * - Device Global Registers
+ * - Device Endpoint Specific Registers
+ * - Host Mode Registers
+ * - Host Global Registers
+ * - Host Port CSRs
+ * - Host Channel Specific Registers
+ *
+ * Only the Core Global registers can be accessed in both Device and
+ * Host modes. When the HS OTG core is operating in one mode, either
+ * Device or Host, the application must not access registers from the
+ * other mode. When the core switches from one mode to another, the
+ * registers in the new mode of operation must be reprogrammed as they
+ * would be after a power-on reset.
+ */
+
+/****************************************************************************/
+/** DWC_otg Core registers .
+ * The dwc_otg_core_global_regs structure defines the size
+ * and relative field offsets for the Core Global registers.
+ */
+typedef struct dwc_otg_core_global_regs
+{
+ /** OTG Control and Status Register. <i>Offset: 000h</i> */
+ volatile uint32_t gotgctl;
+ /** OTG Interrupt Register. <i>Offset: 004h</i> */
+ volatile uint32_t gotgint;
+ /**Core AHB Configuration Register. <i>Offset: 008h</i> */
+ volatile uint32_t gahbcfg;
+ /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
+ volatile uint32_t gusbcfg;
+ /**Core Reset Register. <i>Offset: 010h</i> */
+ volatile uint32_t grstctl;
+ /**Core Interrupt Register. <i>Offset: 014h</i> */
+ volatile uint32_t gintsts;
+ /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
+ volatile uint32_t gintmsk;
+ /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
+ volatile uint32_t grxstsr;
+ /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
+ volatile uint32_t grxstsp;
+ /**Receive FIFO Size Register. <i>Offset: 024h</i> */
+ volatile uint32_t grxfsiz;
+ /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
+ volatile uint32_t gnptxfsiz;
+ /**Non Periodic Transmit FIFO/Queue Status Register (Read
+ * Only). <i>Offset: 02Ch</i> */
+ volatile uint32_t gnptxsts;
+ /**I2C Access Register. <i>Offset: 030h</i> */
+ volatile uint32_t gi2cctl;
+ /**PHY Vendor Control Register. <i>Offset: 034h</i> */
+ volatile uint32_t gpvndctl;
+ /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
+ volatile uint32_t ggpio;
+ /**User ID Register. <i>Offset: 03Ch</i> */
+ volatile uint32_t guid;
+ /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
+ volatile uint32_t gsnpsid;
+ /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
+ volatile uint32_t ghwcfg1;
+ /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
+ volatile uint32_t ghwcfg2;
+ /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
+ volatile uint32_t ghwcfg3;
+ /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
+ volatile uint32_t ghwcfg4;
+ /** Core LPM Configuration register <i>Offset: 054h</i>*/
+ volatile uint32_t glpmcfg;
+ /** Global PowerDn Register <i>Offset: 058h</i> */
+ volatile uint32_t gpwrdn;
+ /** Global DFIFO SW Config Register <i>Offset: 05Ch</i> */
+ volatile uint32_t gdfifocfg;
+ /** ADP Control Register <i>Offset: 060h</i> */
+ volatile uint32_t adpctl;
+} dwc_otg_core_global_regs_t;
+
+/**
+ * This union represents the bit fields of the Core OTG Control
+ * and Status Register (GOTGCTL). Set the bits using the bit
+ * fields then write the <i>d32</i> value to the register.
+ */
+typedef union gotgctl_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ unsigned sesreqscs:1;
+ unsigned sesreq:1;
+ unsigned vbvalidoven:1;
+ unsigned vbvalidovval:1;
+ unsigned avalidoven:1;
+ unsigned avalidovval:1;
+ unsigned bvalidoven:1;
+ unsigned bvalidovval:1;
+ unsigned hstnegscs:1;
+ unsigned hnpreq:1;
+ unsigned hstsethnpen:1;
+ unsigned devhnpen:1;
+ unsigned reserved12_15:4;
+ unsigned conidsts:1;
+ unsigned dbnctime:1;
+ unsigned asesvld:1;
+ unsigned bsesvld:1;
+ unsigned otgver:1;
+ unsigned reserved1:1;
+ unsigned multvalidbc:5;
+ unsigned chirpen:1;
+ unsigned reserved28_31:4;
+ } b;
+} gotgctl_data_t;
+/**
+ * This union represents the bit fields of the Core AHB Configuration
+ * Register (GAHBCFG). Set/clear the bits using the bit fields then
+ * write the <i>d32</i> value to the register.
+ */
+#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
+#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
+typedef union gahbcfg_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ unsigned glblintrmsk:1;
+ unsigned hburstlen:4;
+ unsigned dmaenable:1;
+ unsigned reserved:1;
+ unsigned nptxfemplvl_txfemplvl:1;
+ unsigned ptxfemplvl:1;
+ unsigned reserved9_20:12;
+ unsigned remmemsupp:1;
+ unsigned notialldmawrit:1;
+ unsigned ahbsingle:1;
+ unsigned reserved24_31:8;
+ } b;
+} gahbcfg_data_t;
+
+/**
+ * This union represents the bit fields of the Core USB Configuration
+ * Register (GUSBCFG). Set the bits using the bit fields then write
+ * the <i>d32</i> value to the register.
+ */
+typedef union gusbcfg_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ unsigned toutcal:3;
+ unsigned phyif:1;
+ unsigned ulpi_utmi_sel:1;
+ unsigned fsintf:1;
+ unsigned physel:1;
+ unsigned ddrsel:1;
+ unsigned srpcap:1;
+ unsigned hnpcap:1;
+ unsigned usbtrdtim:4;
+ unsigned reserved1:1;
+ unsigned phylpwrclksel:1;
+ unsigned otgutmifssel:1;
+ unsigned ulpi_fsls:1;
+ unsigned ulpi_auto_res:1;
+ unsigned ulpi_clk_sus_m:1;
+ unsigned ulpi_ext_vbus_drv:1;
+ unsigned ulpi_int_vbus_indicator:1;
+ unsigned term_sel_dl_pulse:1;
+ unsigned indicator_complement:1;
+ unsigned indicator_pass_through:1;
+ unsigned ulpi_int_prot_dis:1;
+ unsigned ic_usb_cap:1;
+ unsigned ic_traffic_pull_remove:1;
+ unsigned tx_end_delay:1;
+ unsigned force_host_mode:1;
+ unsigned force_dev_mode:1;
+ unsigned reserved31:1;
+ } b;
+} gusbcfg_data_t;
+
+/**
+ * This union represents the bit fields of the Core Reset Register
+ * (GRSTCTL). Set/clear the bits using the bit fields then write the
+ * <i>d32</i> value to the register.
+ */
+typedef union grstctl_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** Core Soft Reset (CSftRst) (Device and Host)
+ *
+ * The application can flush the control logic in the
+ * entire core using this bit. This bit resets the
+ * pipelines in the AHB Clock domain as well as the
+ * PHY Clock domain.
+ *
+ * The state machines are reset to an IDLE state, the
+ * control bits in the CSRs are cleared, all the
+ * transmit FIFOs and the receive FIFO are flushed.
+ *
+ * The status mask bits that control the generation of
+ * the interrupt, are cleared, to clear the
+ * interrupt. The interrupt status bits are not
+ * cleared, so the application can get the status of
+ * any events that occurred in the core after it has
+ * set this bit.
+ *
+ * Any transactions on the AHB are terminated as soon
+ * as possible following the protocol. Any
+ * transactions on the USB are terminated immediately.
+ *
+ * The configuration settings in the CSRs are
+ * unchanged, so the software doesn't have to
+ * reprogram these registers (Device
+ * Configuration/Host Configuration/Core System
+ * Configuration/Core PHY Configuration).
+ *
+ * The application can write to this bit, any time it
+ * wants to reset the core. This is a self clearing
+ * bit and the core clears this bit after all the
+ * necessary logic is reset in the core, which may
+ * take several clocks, depending on the current state
+ * of the core.
+ */
+ unsigned csftrst:1;
+ /** Hclk Soft Reset
+ *
+ * The application uses this bit to reset the control logic in
+ * the AHB clock domain. Only AHB clock domain pipelines are
+ * reset.
+ */
+ unsigned hsftrst:1;
+ /** Host Frame Counter Reset (Host Only)<br>
+ *
+ * The application can reset the (micro)frame number
+ * counter inside the core, using this bit. When the
+ * (micro)frame counter is reset, the subsequent SOF
+ * sent out by the core, will have a (micro)frame
+ * number of 0.
+ */
+ unsigned hstfrm:1;
+ /** In Token Sequence Learning Queue Flush
+ * (INTknQFlsh) (Device Only)
+ */
+ unsigned intknqflsh:1;
+ /** RxFIFO Flush (RxFFlsh) (Device and Host)
+ *
+ * The application can flush the entire Receive FIFO
+ * using this bit. The application must first
+ * ensure that the core is not in the middle of a
+ * transaction. The application should write into
+ * this bit, only after making sure that neither the
+ * DMA engine is reading from the RxFIFO nor the MAC
+ * is writing the data in to the FIFO. The
+ * application should wait until the bit is cleared
+ * before performing any other operations. This bit
+ * will takes 8 clocks (slowest of PHY or AHB clock)
+ * to clear.
+ */
+ unsigned rxfflsh:1;
+ /** TxFIFO Flush (TxFFlsh) (Device and Host).
+ *
+ * This bit is used to selectively flush a single or
+ * all transmit FIFOs. The application must first
+ * ensure that the core is not in the middle of a
+ * transaction. The application should write into
+ * this bit, only after making sure that neither the
+ * DMA engine is writing into the TxFIFO nor the MAC
+ * is reading the data out of the FIFO. The
+ * application should wait until the core clears this
+ * bit, before performing any operations. This bit
+ * will takes 8 clocks (slowest of PHY or AHB clock)
+ * to clear.
+ */
+ unsigned txfflsh:1;
+
+ /** TxFIFO Number (TxFNum) (Device and Host).
+ *
+ * This is the FIFO number which needs to be flushed,
+ * using the TxFIFO Flush bit. This field should not
+ * be changed until the TxFIFO Flush bit is cleared by
+ * the core.
+ * - 0x0 : Non Periodic TxFIFO Flush
+ * - 0x1 : Periodic TxFIFO #1 Flush in device mode
+ * or Periodic TxFIFO in host mode
+ * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
+ * - ...
+ * - 0xF : Periodic TxFIFO #15 Flush in device mode
+ * - 0x10: Flush all the Transmit NonPeriodic and
+ * Transmit Periodic FIFOs in the core
+ */
+ unsigned txfnum:5;
+ /** Reserved */
+ unsigned reserved11_29:19;
+ /** DMA Request Signal. Indicated DMA request is in
+ * probress. Used for debug purpose. */
+ unsigned dmareq:1;
+ /** AHB Master Idle. Indicates the AHB Master State
+ * Machine is in IDLE condition. */
+ unsigned ahbidle:1;
+ } b;
+} grstctl_t;
+
+/**
+ * This union represents the bit fields of the Core Interrupt Mask
+ * Register (GINTMSK). Set/clear the bits using the bit fields then
+ * write the <i>d32</i> value to the register.
+ */
+typedef union gintmsk_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ unsigned reserved0:1;
+ unsigned modemismatch:1;
+ unsigned otgintr:1;
+ unsigned sofintr:1;
+ unsigned rxstsqlvl:1;
+ unsigned nptxfempty:1;
+ unsigned ginnakeff:1;
+ unsigned goutnakeff:1;
+ unsigned ulpickint:1;
+ unsigned i2cintr:1;
+ unsigned erlysuspend:1;
+ unsigned usbsuspend:1;
+ unsigned usbreset:1;
+ unsigned enumdone:1;
+ unsigned isooutdrop:1;
+ unsigned eopframe:1;
+ unsigned restoredone:1;
+ unsigned epmismatch:1;
+ unsigned inepintr:1;
+ unsigned outepintr:1;
+ unsigned incomplisoin:1;
+ unsigned incomplisoout:1;
+ unsigned fetsusp:1;
+ unsigned resetdet:1;
+ unsigned portintr:1;
+ unsigned hcintr:1;
+ unsigned ptxfempty:1;
+ unsigned lpmtranrcvd:1;
+ unsigned conidstschng:1;
+ unsigned disconnect:1;
+ unsigned sessreqintr:1;
+ unsigned wkupintr:1;
+ } b;
+} gintmsk_data_t;
+/**
+ * This union represents the bit fields of the Core Interrupt Register
+ * (GINTSTS). Set/clear the bits using the bit fields then write the
+ * <i>d32</i> value to the register.
+ */
+#define DWC_SOF_INTR_MASK 0x0008
+#define DWC_HOST_MODE 1
+
+typedef union gintsts_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ unsigned curmode:1;
+ unsigned modemismatch:1;
+ unsigned otgintr:1;
+ unsigned sofintr:1;
+ unsigned rxstsqlvl:1;
+ unsigned nptxfempty:1;
+ unsigned ginnakeff:1;
+ unsigned goutnakeff:1;
+ unsigned ulpickint:1;
+ unsigned i2cintr:1;
+ unsigned erlysuspend:1;
+ unsigned usbsuspend:1;
+ unsigned usbreset:1;
+ unsigned enumdone:1;
+ unsigned isooutdrop:1;
+ unsigned eopframe:1;
+ unsigned restoredone:1;
+ unsigned epmismatch:1;
+ unsigned inepint:1;
+ unsigned outepintr:1;
+ unsigned incomplisoin:1;
+ unsigned incomplisoout:1;
+ unsigned fetsusp:1;
+ unsigned resetdet:1;
+ unsigned portintr:1;
+ unsigned hcintr:1;
+ unsigned ptxfempty:1;
+ unsigned lpmtranrcvd:1;
+ unsigned conidstschng:1;
+ unsigned disconnect:1;
+ unsigned sessreqintr:1;
+ unsigned wkupintr:1;
+ } b;
+} gintsts_data_t;
+
+/**
+ * This union represents the bit fields in the Device Receive Status Read and
+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
+ * element then read out the bits using the <i>b</i>it elements.
+ */
+
+#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
+#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
+#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
+#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
+#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
+
+typedef union device_grxsts_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ unsigned epnum:4;
+ unsigned bcnt:11;
+ unsigned dpid:2;
+ unsigned pktsts:4;
+ unsigned fn:4;
+ unsigned reserved25_31:7;
+ } b;
+} device_grxsts_data_t;
+/**
+ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
+ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
+ * then read out the bits using the <i>b</i>it elements.
+ */
+typedef union fifosize_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ unsigned startaddr:16;
+ unsigned depth:16;
+ } b;
+} fifosize_data_t;
+
+/**
+ * This union represents the bit fields in the Non-Periodic Transmit
+ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
+ * <i>d32</i> element then read out the bits using the <i>b</i>it
+ * elements.
+ */
+typedef union gnptxsts_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ unsigned nptxfspcavail:16;
+ unsigned nptxqspcavail:8;
+ /** Top of the Non-Periodic Transmit Request Queue
+ * - bit 24 - Terminate (Last entry for the selected
+ * channel/EP)
+ * - bits 26:25 - Token Type
+ * - 2'b00 - IN/OUT
+ * - 2'b01 - Zero Length OUT
+ * - 2'b10 - PING/Complete Split
+ * - 2'b11 - Channel Halt
+ * - bits 30:27 - Channel/EP Number
+ */
+ unsigned nptxqtop_terminate:1;
+ unsigned nptxqtop_token:2;
+ unsigned nptxqtop_chnep:4;
+ unsigned reserved:1;
+ } b;
+} gnptxsts_data_t;
+
+/**
+ * This union represents the bit fields in the Transmit
+ * FIFO Status Register (DTXFSTS). Read the register into the
+ * <i>d32</i> element then read out the bits using the <i>b</i>it
+ * elements.
+ */
+typedef union dtxfsts_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ unsigned txfspcavail:16;
+ unsigned reserved:16;
+ } b;
+} dtxfsts_data_t;
+/**
+ * This union represents the bit fields in the User HW Config1
+ * Register. Read the register into the <i>d32</i> element then read
+ * out the bits using the <i>b</i>it elements.
+ */
+typedef union hwcfg1_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ unsigned ep_dir0:2;
+ unsigned ep_dir1:2;
+ unsigned ep_dir2:2;
+ unsigned ep_dir3:2;
+ unsigned ep_dir4:2;
+ unsigned ep_dir5:2;
+ unsigned ep_dir6:2;
+ unsigned ep_dir7:2;
+ unsigned ep_dir8:2;
+ unsigned ep_dir9:2;
+ unsigned ep_dir10:2;
+ unsigned ep_dir11:2;
+ unsigned ep_dir12:2;
+ unsigned ep_dir13:2;
+ unsigned ep_dir14:2;
+ unsigned ep_dir15:2;
+ } b;
+} hwcfg1_data_t;
+
+/**
+ * This union represents the bit fields in the User HW Config2
+ * Register. Read the register into the <i>d32</i> element then read
+ * out the bits using the <i>b</i>it elements.
+ */
+#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
+#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
+#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
+#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
+
+typedef union hwcfg2_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /* GHWCFG2 */
+ unsigned op_mode:3;
+ unsigned architecture:2; //00 salve-only;01 external dma;10 internal dma;
+ unsigned point2point:1;
+ unsigned hs_phy_type:2;
+ unsigned fs_phy_type:2;
+ unsigned num_dev_ep:4;
+ unsigned num_host_chan:4;
+ unsigned perio_ep_supported:1;
+ unsigned dynamic_fifo:1;
+ unsigned multi_proc_int:1;
+ unsigned reserved21:1;
+ unsigned nonperio_tx_q_depth:2;
+ unsigned host_perio_tx_q_depth:2;
+ unsigned dev_token_q_depth:5;
+ unsigned otg_enable_ic_usb:1;
+ } b;
+} hwcfg2_data_t;
+
+/**
+ * This union represents the bit fields in the User HW Config3
+ * Register. Read the register into the <i>d32</i> element then read
+ * out the bits using the <i>b</i>it elements.
+ */
+typedef union hwcfg3_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /* GHWCFG3 */
+ unsigned xfer_size_cntr_width:4;
+ unsigned packet_size_cntr_width:3;
+ unsigned otg_func:1;
+ unsigned i2c:1;
+ unsigned vendor_ctrl_if:1;
+ unsigned optional_features:1;
+ unsigned synch_reset_type:1;
+ unsigned adp_supp:1;
+ unsigned otg_enable_hsic:1;
+ unsigned bc_support:1;
+ unsigned otg_lpm_en:1;
+ unsigned dfifo_depth:16;
+ } b;
+} hwcfg3_data_t;
+
+/**
+ * This union represents the bit fields in the User HW Config4
+ * Register. Read the register into the <i>d32</i> element then read
+ * out the bits using the <i>b</i>it elements.
+ */
+typedef union hwcfg4_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ unsigned num_dev_perio_in_ep:4;
+ unsigned power_optimiz:1;
+ unsigned min_ahb_freq:1;
+ unsigned hiber:1;
+ unsigned xhiber:1;
+ unsigned reserved:6;
+ unsigned utmi_phy_data_width:2;
+ unsigned num_dev_mode_ctrl_ep:4;
+ unsigned iddig_filt_en:1;
+ unsigned vbus_valid_filt_en:1;
+ unsigned a_valid_filt_en:1;
+ unsigned b_valid_filt_en:1;
+ unsigned session_end_filt_en:1;
+ unsigned ded_fifo_en:1;
+ unsigned num_in_eps:4;
+ unsigned desc_dma:1;
+ unsigned desc_dma_dyn:1;
+ } b;
+} hwcfg4_data_t;
+
+/**
+ * This union represents the bit fields of the Core LPM Configuration
+ * Register (GLPMCFG). Set the bits using bit fields then write
+ * the <i>d32</i> value to the register.
+ */
+typedef union glpmctl_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** LPM-Capable (LPMCap) (Device and Host)
+ * The application uses this bit to control
+ * the DWC_otg core LPM capabilities.
+ */
+ unsigned lpm_cap_en:1;
+ /** LPM response programmed by application (AppL1Res) (Device)
+ * Handshake response to LPM token pre-programmed
+ * by device application software.
+ */
+ unsigned appl_resp:1;
+ /** Host Initiated Resume Duration (HIRD) (Device and Host)
+ * In Host mode this field indicates the value of HIRD
+ * to be sent in an LPM transaction.
+ * In Device mode this field is updated with the
+ * Received LPM Token HIRD bmAttribute
+ * when an ACK/NYET/STALL response is sent
+ * to an LPM transaction.
+ */
+ unsigned hird:4;
+ /** RemoteWakeEnable (bRemoteWake) (Device and Host)
+ * In Host mode this bit indicates the value of remote
+ * wake up to be sent in wIndex field of LPM transaction.
+ * In Device mode this field is updated with the
+ * Received LPM Token bRemoteWake bmAttribute
+ * when an ACK/NYET/STALL response is sent
+ * to an LPM transaction.
+ */
+ unsigned rem_wkup_en:1;
+ /** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
+ * The application uses this bit to control
+ * the utmi_sleep_n assertion to the PHY when in L1 state.
+ */
+ unsigned en_utmi_sleep:1;
+ /** HIRD Threshold (HIRD_Thres) (Device and Host)
+ */
+ unsigned hird_thres:5;
+ /** LPM Response (CoreL1Res) (Device and Host)
+ * In Host mode this bit contains handsake response to
+ * LPM transaction.
+ * In Device mode the response of the core to
+ * LPM transaction received is reflected in these two bits.
+ - 0x0 : ERROR (No handshake response)
+ - 0x1 : STALL
+ - 0x2 : NYET
+ - 0x3 : ACK
+ */
+ unsigned lpm_resp:2;
+ /** Port Sleep Status (SlpSts) (Device and Host)
+ * This bit is set as long as a Sleep condition
+ * is present on the USB bus.
+ */
+ unsigned prt_sleep_sts:1;
+ /** Sleep State Resume OK (L1ResumeOK) (Device and Host)
+ * Indicates that the application or host
+ * can start resume from Sleep state.
+ */
+ unsigned sleep_state_resumeok:1;
+ /** LPM channel Index (LPM_Chnl_Indx) (Host)
+ * The channel number on which the LPM transaction
+ * has to be applied while sending
+ * an LPM transaction to the local device.
+ */
+ unsigned lpm_chan_index:4;
+ /** LPM Retry Count (LPM_Retry_Cnt) (Host)
+ * Number host retries that would be performed
+ * if the device response was not valid response.
+ */
+ unsigned retry_count:3;
+ /** Send LPM Transaction (SndLPM) (Host)
+ * When set by application software,
+ * an LPM transaction containing two tokens
+ * is sent.
+ */
+ unsigned send_lpm:1;
+ /** LPM Retry status (LPM_RetryCnt_Sts) (Host)
+ * Number of LPM Host Retries still remaining
+ * to be transmitted for the current LPM sequence
+ */
+ unsigned retry_count_sts:3;
+ unsigned reserved28_29:2;
+ /** In host mode once this bit is set, the host
+ * configures to drive the HSIC Idle state on the bus.
+ * It then waits for the device to initiate the Connect sequence.
+ * In device mode once this bit is set, the device waits for
+ * the HSIC Idle line state on the bus. Upon receving the Idle
+ * line state, it initiates the HSIC Connect sequence.
+ */
+ unsigned hsic_connect:1;
+ /** This bit overrides and functionally inverts
+ * the if_select_hsic input port signal.
+ */
+ unsigned inv_sel_hsic:1;
+ } b;
+} glpmcfg_data_t;
+// Device Registers
+/**
+ * Device Global Registers. <i>Offsets 800h-BFFh</i>
+ *
+ * The following structures define the size and relative field offsets
+ * for the Device Mode Registers.
+ *
+ * <i>These registers are visible only in Device mode and must not be
+ * accessed in Host mode, as the results are unknown.</i>
+ */
+typedef struct dwc_otg_dev_global_regs
+{
+ /** Device Configuration Register. <i>Offset 800h</i> */
+ volatile uint32_t dcfg;
+ /** Device Control Register. <i>Offset: 804h</i> */
+ volatile uint32_t dctl;
+ /** Device Status Register (Read Only). <i>Offset: 808h</i> */
+ volatile uint32_t dsts;
+ /** Reserved. <i>Offset: 80Ch</i> */
+ uint32_t unused;
+ /** Device IN Endpoint Common Interrupt Mask
+ * Register. <i>Offset: 810h</i> */
+ volatile uint32_t diepmsk;
+ /** Device OUT Endpoint Common Interrupt Mask
+ * Register. <i>Offset: 814h</i> */
+ volatile uint32_t doepmsk;
+ /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
+ volatile uint32_t daint;
+ /** Device All Endpoints Interrupt Mask Register. <i>Offset:
+ * 81Ch</i> */
+ volatile uint32_t daintmsk;
+ /** Device IN Token Queue Read Register-1 (Read Only).
+ * <i>Offset: 820h</i> */
+ volatile uint32_t dtknqr1;
+ /** Device IN Token Queue Read Register-2 (Read Only).
+ * <i>Offset: 824h</i> */
+ volatile uint32_t dtknqr2;
+ /** Device VBUS discharge Register. <i>Offset: 828h</i> */
+ volatile uint32_t dvbusdis;
+ /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
+ volatile uint32_t dvbuspulse;
+ /** Device IN Token Queue Read Register-3 (Read Only). /
+ * Device Thresholding control register (Read/Write)
+ * <i>Offset: 830h</i> */
+ volatile uint32_t dtknqr3_dthrctl;
+ /** Device IN Token Queue Read Register-4 (Read Only). /
+ * Device IN EPs empty Inr. Mask Register (Read/Write)
+ * <i>Offset: 834h</i> */
+ volatile uint32_t dtknqr4_fifoemptymsk;
+ /** Device Each Endpoint Interrupt Register (Read Only). /
+ * <i>Offset: 838h</i> */
+ volatile uint32_t deachint;
+ /** Device Each Endpoint Interrupt mask Register (Read/Write). /
+ * <i>Offset: 83Ch</i> */
+ volatile uint32_t deachintmsk;
+ /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
+ * <i>Offset: 840h</i> */
+ volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
+ /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
+ * <i>Offset: 880h</i> */
+ volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
+} dwc_otg_device_global_regs_t;
+
+/**
+ * This union represents the bit fields in the Device Configuration
+ * Register. Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements. Write the
+ * <i>d32</i> member to the dcfg register.
+ */
+#define DWC_DCFG_SEND_STALL 1
+#define DWC_DCFG_FRAME_INTERVAL_80 0
+#define DWC_DCFG_FRAME_INTERVAL_85 1
+#define DWC_DCFG_FRAME_INTERVAL_90 2
+#define DWC_DCFG_FRAME_INTERVAL_95 3
+
+typedef union dcfg_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** Device Speed */
+ unsigned devspd:2;
+ /** Non Zero Length Status OUT Handshake */
+ unsigned nzstsouthshk:1;
+ unsigned ena32khzs:1;
+ /** Device Addresses */
+ unsigned devaddr:7;
+ /** Periodic Frame Interval */
+ unsigned perfrint:2;
+ /** Enable Device OUT NAK for bulk in DDMA mode */
+ unsigned endevoutnak:1;
+ unsigned reserved14_17:4;
+ /** In Endpoint Mis-match count */
+ unsigned epmscnt:5;
+ /** Enable Descriptor DMA in Device mode */
+ unsigned descdma:1;
+ unsigned perschintvl:2;
+ unsigned resvalid:6;
+ } b;
+} dcfg_data_t;
+
+/**
+ * This union represents the bit fields in the Device Control
+ * Register. Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+typedef union dctl_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** Remote Wakeup */
+ unsigned rmtwkupsig:1;
+ /** Soft Disconnect */
+ unsigned sftdiscon:1;
+ /** Global Non-Periodic IN NAK Status */
+ unsigned gnpinnaksts:1;
+ /** Global OUT NAK Status */
+ unsigned goutnaksts:1;
+ /** Test Control */
+ unsigned tstctl:3;
+ /** Set Global Non-Periodic IN NAK */
+ unsigned sgnpinnak:1;
+ /** Clear Global Non-Periodic IN NAK */
+ unsigned cgnpinnak:1;
+ /** Set Global OUT NAK */
+ unsigned sgoutnak:1;
+ /** Clear Global OUT NAK */
+ unsigned cgoutnak:1;
+ /** Power-On Programming Done */
+ unsigned pwronprgdone:1;
+ /** Reserved */
+ unsigned reserved:1;
+ /** Global Multi Count */
+ unsigned gmc:2;
+ /** Ignore Frame Number for ISOC EPs */
+ unsigned ifrmnum:1;
+ /** NAK on Babble */
+ unsigned nakonbble:1;
+ /** Enable Continue on BNA */
+ unsigned encontonbna:1;
+
+ unsigned reserved18_31:14;
+ } b;
+} dctl_data_t;
+
+/**
+ * This union represents the bit fields in the Device Status
+ * Register. Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
+#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
+#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
+#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
+typedef union dsts_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** Suspend Status */
+ unsigned suspsts:1;
+ /** Enumerated Speed */
+ unsigned enumspd:2;
+ /** Erratic Error */
+ unsigned errticerr:1;
+ unsigned reserved4_7:4;
+ /** Frame or Microframe Number of the received SOF */
+ unsigned soffn:14;
+ unsigned reserved22_31:10;
+ } b;
+} dsts_data_t;
+
+/**
+ * This union represents the bit fields in the Device IN EP Interrupt
+ * Register and the Device IN EP Common Mask Register.
+ *
+ * - Read the register into the <i>d32</i> member then set/clear the
+ * bits using the <i>b</i>it elements.
+ */
+typedef union diepint_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** Transfer complete mask */
+ unsigned xfercompl:1;
+ /** Endpoint disable mask */
+ unsigned epdisabled:1;
+ /** AHB Error mask */
+ unsigned ahberr:1;
+ /** TimeOUT Handshake mask (non-ISOC EPs) */
+ unsigned timeout:1;
+ /** IN Token received with TxF Empty mask */
+ unsigned intktxfemp:1;
+ /** IN Token Received with EP mismatch mask */
+ unsigned intknepmis:1;
+ /** IN Endpoint NAK Effective mask */
+ unsigned inepnakeff:1;
+ /** Reserved */
+ unsigned emptyintr:1;
+
+ unsigned txfifoundrn:1;
+
+ /** BNA Interrupt mask */
+ unsigned bna:1;
+
+ unsigned reserved10_12:3;
+ /** BNA Interrupt mask */
+ unsigned nak:1;
+
+ unsigned reserved14_31:18;
+ } b;
+} diepint_data_t;
+
+/**
+ * This union represents the bit fields in the Device IN EP
+ * Common/Dedicated Interrupt Mask Register.
+ */
+typedef union diepint_data diepmsk_data_t;
+
+/**
+ * This union represents the bit fields in the Device OUT EP Interrupt
+ * Registerand Device OUT EP Common Interrupt Mask Register.
+ *
+ * - Read the register into the <i>d32</i> member then set/clear the
+ * bits using the <i>b</i>it elements.
+ */
+typedef union doepint_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** Transfer complete */
+ unsigned xfercompl:1;
+ /** Endpoint disable */
+ unsigned epdisabled:1;
+ /** AHB Error */
+ unsigned ahberr:1;
+ /** Setup Phase Done (contorl EPs) */
+ unsigned setup:1;
+ /** OUT Token Received when Endpoint Disabled */
+ unsigned outtknepdis:1;
+
+ unsigned stsphsercvd:1;
+ /** Back-to-Back SETUP Packets Received */
+ unsigned back2backsetup:1;
+
+ unsigned reserved7:1;
+ /** OUT packet Error */
+ unsigned outpkterr:1;
+ /** BNA Interrupt */
+ unsigned bna:1;
+
+ unsigned reserved10:1;
+ /** Packet Drop Status */
+ unsigned pktdrpsts:1;
+ /** Babble Interrupt */
+ unsigned babble:1;
+ /** NAK Interrupt */
+ unsigned nak:1;
+ /** NYET Interrupt */
+ unsigned nyet:1;
+ /** Bit indicating setup packet received */
+ unsigned sr:1;
+
+ unsigned reserved16_31:16;
+ } b;
+} doepint_data_t;
+
+/**
+ * This union represents the bit fields in the Device OUT EP
+ * Common/Dedicated Interrupt Mask Register.
+ */
+typedef union doepint_data doepmsk_data_t;
+
+/**
+ * This union represents the bit fields in the Device All EP Interrupt
+ * and Mask Registers.
+ * - Read the register into the <i>d32</i> member then set/clear the
+ * bits using the <i>b</i>it elements.
+ */
+typedef union daint_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** IN Endpoint bits */
+ unsigned in:16;
+ /** OUT Endpoint bits */
+ unsigned out:16;
+ } ep;
+ struct
+ {
+ /** IN Endpoint bits */
+ unsigned inep0:1;
+ unsigned inep1:1;
+ unsigned inep2:1;
+ unsigned inep3:1;
+ unsigned inep4:1;
+ unsigned inep5:1;
+ unsigned inep6:1;
+ unsigned inep7:1;
+ unsigned inep8:1;
+ unsigned inep9:1;
+ unsigned inep10:1;
+ unsigned inep11:1;
+ unsigned inep12:1;
+ unsigned inep13:1;
+ unsigned inep14:1;
+ unsigned inep15:1;
+ /** OUT Endpoint bits */
+ unsigned outep0:1;
+ unsigned outep1:1;
+ unsigned outep2:1;
+ unsigned outep3:1;
+ unsigned outep4:1;
+ unsigned outep5:1;
+ unsigned outep6:1;
+ unsigned outep7:1;
+ unsigned outep8:1;
+ unsigned outep9:1;
+ unsigned outep10:1;
+ unsigned outep11:1;
+ unsigned outep12:1;
+ unsigned outep13:1;
+ unsigned outep14:1;
+ unsigned outep15:1;
+ } b;
+} daint_data_t;
+
+/**
+ * This union represents the bit fields in the Device IN Token Queue
+ * Read Registers.
+ * - Read the register into the <i>d32</i> member.
+ * - READ-ONLY Register
+ */
+typedef union dtknq1_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** In Token Queue Write Pointer */
+ unsigned intknwptr:5;
+ /** Reserved */
+ unsigned reserved05_06:2;
+ /** write pointer has wrapped. */
+ unsigned wrap_bit:1;
+ /** EP Numbers of IN Tokens 0 ... 4 */
+ unsigned epnums0_5:24;
+ } b;
+} dtknq1_data_t;
+
+
+/**
+ * Device Logical IN Endpoint-Specific Registers. <i>Offsets
+ * 900h-AFCh</i>
+ *
+ * There will be one set of endpoint registers per logical endpoint
+ * implemented.
+ *
+ * <i>These registers are visible only in Device mode and must not be
+ * accessed in Host mode, as the results are unknown.</i>
+ */
+typedef struct dwc_otg_dev_in_ep_regs
+{
+ /** Device IN Endpoint Control Register. <i>Offset:900h +
+ * (ep_num * 20h) + 00h</i> */
+ volatile uint32_t diepctl;
+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
+ uint32_t reserved04;
+ /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
+ * (ep_num * 20h) + 08h</i> */
+ volatile uint32_t diepint;
+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
+ uint32_t reserved0C;
+ /** Device IN Endpoint Transfer Size
+ * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
+ volatile uint32_t dieptsiz;
+ /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
+ * (ep_num * 20h) + 14h</i> */
+ volatile uint32_t diepdma;
+ /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
+ * (ep_num * 20h) + 18h</i> */
+ volatile uint32_t dtxfsts;
+ /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
+ * (ep_num * 20h) + 1Ch</i> */
+ volatile uint32_t diepdmab;
+} dwc_otg_dev_in_ep_regs_t;
+
+/**
+ * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
+ * B00h-CFCh</i>
+ *
+ * There will be one set of endpoint registers per logical endpoint
+ * implemented.
+ *
+ * <i>These registers are visible only in Device mode and must not be
+ * accessed in Host mode, as the results are unknown.</i>
+ */
+typedef struct dwc_otg_dev_out_ep_regs
+{
+ /** Device OUT Endpoint Control Register. <i>Offset:B00h +
+ * (ep_num * 20h) + 00h</i> */
+ volatile uint32_t doepctl;
+ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
+ uint32_t reserved04;
+ /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
+ * (ep_num * 20h) + 08h</i> */
+ volatile uint32_t doepint;
+ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
+ uint32_t reserved0C;
+ /** Device OUT Endpoint Transfer Size Register. <i>Offset:
+ * B00h + (ep_num * 20h) + 10h</i> */
+ volatile uint32_t doeptsiz;
+ /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
+ * + (ep_num * 20h) + 14h</i> */
+ volatile uint32_t doepdma;
+ /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 18h</i> */
+ uint32_t unused;
+ /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
+ * + (ep_num * 20h) + 1Ch</i> */
+ uint32_t doepdmab;
+} dwc_otg_dev_out_ep_regs_t;
+
+/**
+ * This union represents the bit fields in the Device EP Control
+ * Register. Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+#define DWC_DEP0CTL_MPS_64 0
+#define DWC_DEP0CTL_MPS_32 1
+#define DWC_DEP0CTL_MPS_16 2
+#define DWC_DEP0CTL_MPS_8 3
+
+typedef union depctl_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** Maximum Packet Size
+ * IN/OUT EPn
+ * IN/OUT EP0 - 2 bits
+ * 2'b00: 64 Bytes
+ * 2'b01: 32
+ * 2'b10: 16
+ * 2'b11: 8 */
+ unsigned mps:11;
+ /** Next Endpoint
+ * IN EPn/IN EP0
+ * OUT EPn/OUT EP0 - reserved */
+ unsigned nextep:4;
+
+ /** USB Active Endpoint */
+ unsigned usbactep:1;
+
+ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
+ * This field contains the PID of the packet going to
+ * be received or transmitted on this endpoint. The
+ * application should program the PID of the first
+ * packet going to be received or transmitted on this
+ * endpoint , after the endpoint is
+ * activated. Application use the SetD1PID and
+ * SetD0PID fields of this register to program either
+ * D0 or D1 PID.
+ *
+ * The encoding for this field is
+ * - 0: D0
+ * - 1: D1
+ */
+ unsigned dpid:1;
+
+ /** NAK Status */
+ unsigned naksts:1;
+
+ /** Endpoint Type
+ * 2'b00: Control
+ * 2'b01: Isochronous
+ * 2'b10: Bulk
+ * 2'b11: Interrupt */
+ unsigned eptype:2;
+
+ /** Snoop Mode
+ * OUT EPn/OUT EP0
+ * IN EPn/IN EP0 - reserved */
+ unsigned snp:1;
+
+ /** Stall Handshake */
+ unsigned stall:1;
+
+ /** Tx Fifo Number
+ * IN EPn/IN EP0
+ * OUT EPn/OUT EP0 - reserved */
+ unsigned txfnum:4;
+
+ /** Clear NAK */
+ unsigned cnak:1;
+ /** Set NAK */
+ unsigned snak:1;
+ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
+ * Writing to this field sets the Endpoint DPID (DPID)
+ * field in this register to DATA0. Set Even
+ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
+ * Writing to this field sets the Even/Odd
+ * (micro)frame (EO_FrNum) field to even (micro)
+ * frame.
+ */
+ unsigned setd0pid:1;
+ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
+ * Writing to this field sets the Endpoint DPID (DPID)
+ * field in this register to DATA1 Set Odd
+ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
+ * Writing to this field sets the Even/Odd
+ * (micro)frame (EO_FrNum) field to odd (micro) frame.
+ */
+ unsigned setd1pid:1;
+
+ /** Endpoint Disable */
+ unsigned epdis:1;
+ /** Endpoint Enable */
+ unsigned epena:1;
+ } b;
+} depctl_data_t;
+
+/**
+ * This union represents the bit fields in the Device EP Transfer
+ * Size Register. Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+
+/** Max packet count for EP (pow(2,10)-1) */
+#define MAX_PKT_CNT 1023
+typedef union deptsiz_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** Transfer size */
+ unsigned xfersize:19;
+ /** Packet Count */
+ unsigned pktcnt:10;
+ /** Multi Count - Periodic IN endpoints */
+ unsigned mc:2;
+ unsigned reserved:1;
+ } b;
+} deptsiz_data_t;
+
+/**
+ * This union represents the bit fields in the Device EP 0 Transfer
+ * Size Register. Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+typedef union deptsiz0_data
+{
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** Transfer size */
+ unsigned xfersize:7;
+ /** Reserved */
+ unsigned reserved7_18:12;
+ /** Packet Count */
+ unsigned pktcnt:2;
+ /** Reserved */
+ unsigned reserved21_28:8;
+ /**Setup Packet Count (DOEPTSIZ0 Only) */
+ unsigned supcnt:2;
+ unsigned reserved31;
+ } b;
+} deptsiz0_data_t;
+
+/////////////////////////////////////////////////
+// DMA Descriptor Specific Structures
+//
+
+/** Buffer status definitions */
+
+#define BS_HOST_READY 0x0
+#define BS_DMA_BUSY 0x1
+#define BS_DMA_DONE 0x2
+#define BS_HOST_BUSY 0x3
+
+/** Receive/Transmit status definitions */
+
+#define RTS_SUCCESS 0x0
+#define RTS_BUFFLUSH 0x1
+#define RTS_RESERVED 0x2
+#define RTS_BUFERR 0x3
+
+
+/**
+ * The dwc_otg_dev_if structure contains information needed to manage
+ * the DWC_otg controller acting in device mode. It represents the
+ * programming view of the device-specific aspects of the controller.
+ */
+#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
+#define DWC_DEV_IN_EP_REG_OFFSET 0x900
+#define DWC_EP_REG_OFFSET 0x20
+#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
+
+typedef struct dwc_otg_dev_if
+{
+ /** Pointer to device Global registers.
+ * Device Global Registers starting at offset 800h
+ */
+ dwc_otg_device_global_regs_t *dev_global_regs;
+ /**
+ * Device Logical IN Endpoint-Specific Registers 900h-AFCh
+ */
+ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
+
+ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
+ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
+ /* Device configuration information */
+ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
+ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
+ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
+
+ /** Thresholding enable flags and length varaiables **/
+ uint16_t rx_thr_en;
+ //uint16_t iso_tx_thr_en;
+ uint16_t non_iso_tx_thr_en;
+
+ uint16_t rx_thr_length;
+ uint16_t tx_thr_length;
+
+ /**
+ * Pointers to the DMA Descriptors for EP0 Control
+ * transfers (virtual and physical)
+ */
+
+ /** Setup Packet Detected - if set clear NAK when queueing */
+ uint32_t spd;
+
+} dwc_otg_dev_if_t;
+
+/////////////////////////////////////////////////
+// Host Mode Register Structures
+//
+
+/**
+ * This union represents the bit fields in the Host Configuration Register.
+ * Read the register into the <i>d32</i> member then set/clear the bits using
+ * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
+ */
+#define DWC_HCFG_30_60_MHZ 0
+#define DWC_HCFG_48_MHZ 1
+#define DWC_HCFG_6_MHZ 2
+/**
+ * This union represents the bit fields in the Power and Clock Gating Control
+ * Register. Read the register into the <i>d32</i> member then set/clear the
+ * bits using the <i>b</i>it elements.
+ */
+typedef union pcgcctl_data
+{
+ /** raw register data */
+ uint32_t d32;
+
+ /** register bits */
+ struct
+ {
+ /** Stop Pclk */
+ unsigned stoppclk:1;
+ /** Gate Hclk */
+ unsigned gatehclk:1;
+ /** Power Clamp */
+ unsigned pwrclmp:1;
+ /** Reset Power Down Modules */
+ unsigned rstpdwnmodule:1;
+ /** Reserved */
+ unsigned reserved:1;
+ /** Enable Sleep Clock Gating (Enbl_L1Gating) */
+ unsigned enbl_sleep_gating:1;
+ /** PHY In Sleep (PhySleep) */
+ unsigned phy_in_sleep:1;
+ /** Deep Sleep*/
+ unsigned deep_sleep:1;
+ unsigned resetaftsusp:1;
+ unsigned restoremode:1;
+ unsigned enbl_extnd_hiber:1;
+ unsigned extnd_hiber_pwrclmp:1;
+ unsigned extnd_hiber_switch:1;
+ unsigned ess_reg_restored:1;
+ unsigned prt_clk_sel:2;
+ unsigned port_power:1;
+ unsigned max_xcvrselect:2;
+ unsigned max_termsel:1;
+ unsigned mac_dev_addr:7;
+ unsigned p2hd_dev_enum_spd:2;
+ unsigned p2hd_prt_spd:2;
+ unsigned if_dev_mode:1;
+ } b;
+} pcgcctl_data_t;
+
+/**
+ * This union represents the bit fields in the Global Data FIFO Software
+ * Configuration Register. Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+typedef union gdfifocfg_data
+{
+ /* raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** OTG Data FIFO depth */
+ unsigned gdfifocfg:16;
+ /** Start address of EP info controller */
+ unsigned epinfobase:16;
+ } b;
+} gdfifocfg_data_t;
+
+/**
+ * This union represents the bit fields in the Global Power Down Register
+ * Register. Read the register into the <i>d32</i> member then set/clear the
+ * bits using the <i>b</i>it elements.
+ */
+#define disconn_det disconn_det
+
+#define lnstschng lnstschng
+
+#define rst_det rst_det
+
+#define srp_det srp_det
+
+#define sts_chngint sts_chngint
+
+typedef union gpwrdn_data
+{
+ /* raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct
+ {
+ /** PMU Interrupt Select */
+ unsigned pmuintsel:1;
+ /** PMU Active */
+ unsigned pmuactv:1;
+ /** Restore */
+ unsigned restore:1;
+ /** Power Down Clamp */
+ unsigned pwrdnclmp:1;
+ /** Power Down Reset */
+ unsigned pwrdnrstn:1;
+ /** Power Down Switch */
+ unsigned pwrdnswtch:1;
+ /** Disable VBUS */
+ unsigned dis_vbus:1;
+ /** Line State Change */
+ unsigned lnstschng:1;
+ /** Line state change mask */
+ unsigned lnstchng_msk:1;
+ /** Reset Detected */
+ unsigned rst_det:1;
+ /** Reset Detect mask */
+ unsigned rst_det_msk:1;
+ /** Disconnect Detected */
+ unsigned disconn_det:1;
+ /** Disconnect Detect mask */
+ unsigned disconn_det_msk:1;
+ /** Connect Detected*/
+ unsigned connect_det:1;
+ /** Connect Detected Mask*/
+ unsigned connect_det_msk:1;
+ /** SRP Detected */
+ unsigned srp_det:1;
+ /** SRP Detect mask */
+ unsigned srp_det_msk:1;
+ /** Status Change Interrupt */
+ unsigned sts_chngint:1;
+ /** Status Change Interrupt Mask */
+ unsigned sts_chngint_msk:1;
+ /** Line State */
+ unsigned linestate:2;
+ /** Indicates current mode(status of IDDIG signal) */
+ unsigned idsts:1;
+ /** B Session Valid signal status*/
+ unsigned bsessvld:1;
+ /** ADP Event Detected */
+ unsigned adp_int:1;
+ /** Multi Valued ID pin */
+ unsigned mult_val_id_bc:5;
+ /** Reserved 24_31 */
+ unsigned reserved29_31:3;
+ } b;
+} gpwrdn_data_t;
+
+#endif
diff --git a/boot/common/src/uboot/include/usb/ehci-fsl.h b/boot/common/src/uboot/include/usb/ehci-fsl.h
new file mode 100644
index 0000000..67600ed
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/ehci-fsl.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
+ * Copyright (c) 2005 MontaVista Software
+ * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _EHCI_FSL_H
+#define _EHCI_FSL_H
+
+#include <asm/processor.h>
+
+/* Global offsets */
+#define FSL_SKIP_PCI 0x100
+
+/* offsets for the non-ehci registers in the FSL SOC USB controller */
+#define FSL_SOC_USB_ULPIVP 0x170
+#define FSL_SOC_USB_PORTSC1 0x184
+#define PORT_PTS_MSK (3 << 30)
+#define PORT_PTS_UTMI (0 << 30)
+#define PORT_PTS_ULPI (2 << 30)
+#define PORT_PTS_SERIAL (3 << 30)
+#define PORT_PTS_PTW (1 << 28)
+#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
+#define PORT_PTS_PHCD (1 << 23)
+#define PORT_PP (1 << 12)
+#define PORT_PR (1 << 8)
+
+/* USBMODE Register bits */
+#define CM_IDLE (0 << 0)
+#define CM_RESERVED (1 << 0)
+#define CM_DEVICE (2 << 0)
+#define CM_HOST (3 << 0)
+#define ES_BE (1 << 2) /* Big Endian Select, default is LE */
+#define USBMODE_RESERVED_2 (0 << 2)
+#define SLOM (1 << 3)
+#define SDIS (1 << 4)
+
+/* CONTROL Register bits */
+#define ULPI_INT_EN (1 << 0)
+#define WU_INT_EN (1 << 1)
+#define USB_EN (1 << 2)
+#define LSF_EN (1 << 3)
+#define KEEP_OTG_ON (1 << 4)
+#define OTG_PORT (1 << 5)
+#define REFSEL_12MHZ (0 << 6)
+#define REFSEL_16MHZ (1 << 6)
+#define REFSEL_48MHZ (2 << 6)
+#define PLL_RESET (1 << 8)
+#define UTMI_PHY_EN (1 << 9)
+#define PHY_CLK_SEL_UTMI (0 << 10)
+#define PHY_CLK_SEL_ULPI (1 << 10)
+#define CLKIN_SEL_USB_CLK (0 << 11)
+#define CLKIN_SEL_USB_CLK2 (1 << 11)
+#define CLKIN_SEL_SYS_CLK (2 << 11)
+#define CLKIN_SEL_SYS_CLK2 (3 << 11)
+#define RESERVED_18 (0 << 13)
+#define RESERVED_17 (0 << 14)
+#define RESERVED_16 (0 << 15)
+#define WU_INT (1 << 16)
+#define PHY_CLK_VALID (1 << 17)
+
+#define FSL_SOC_USB_PORTSC2 0x188
+
+/* OTG Status Control Register bits */
+#define FSL_SOC_USB_OTGSC 0x1a4
+#define CTRL_VBUS_DISCHARGE (0x1<<0)
+#define CTRL_VBUS_CHARGE (0x1<<1)
+#define CTRL_OTG_TERMINATION (0x1<<3)
+#define CTRL_DATA_PULSING (0x1<<4)
+#define CTRL_ID_PULL_EN (0x1<<5)
+#define HA_DATA_PULSE (0x1<<6)
+#define HA_BA (0x1<<7)
+#define STS_USB_ID (0x1<<8)
+#define STS_A_VBUS_VALID (0x1<<9)
+#define STS_A_SESSION_VALID (0x1<<10)
+#define STS_B_SESSION_VALID (0x1<<11)
+#define STS_B_SESSION_END (0x1<<12)
+#define STS_1MS_TOGGLE (0x1<<13)
+#define STS_DATA_PULSING (0x1<<14)
+#define INTSTS_USB_ID (0x1<<16)
+#define INTSTS_A_VBUS_VALID (0x1<<17)
+#define INTSTS_A_SESSION_VALID (0x1<<18)
+#define INTSTS_B_SESSION_VALID (0x1<<19)
+#define INTSTS_B_SESSION_END (0x1<<20)
+#define INTSTS_1MS (0x1<<21)
+#define INTSTS_DATA_PULSING (0x1<<22)
+#define INTR_USB_ID_EN (0x1<<24)
+#define INTR_A_VBUS_VALID_EN (0x1<<25)
+#define INTR_A_SESSION_VALID_EN (0x1<<26)
+#define INTR_B_SESSION_VALID_EN (0x1<<27)
+#define INTR_B_SESSION_END_EN (0x1<<28)
+#define INTR_1MS_TIMER_EN (0x1<<29)
+#define INTR_DATA_PULSING_EN (0x1<<30)
+#define INTSTS_MASK (0x00ff0000)
+
+/* USBCMD Bits of interest */
+#define EHCI_FSL_USBCMD_RST (1 << 1)
+#define EHCI_FSL_USBCMD_RS (1 << 0)
+
+#define INTERRUPT_ENABLE_BITS_MASK \
+ (INTR_USB_ID_EN | \
+ INTR_1MS_TIMER_EN | \
+ INTR_A_VBUS_VALID_EN | \
+ INTR_A_SESSION_VALID_EN | \
+ INTR_B_SESSION_VALID_EN | \
+ INTR_B_SESSION_END_EN | \
+ INTR_DATA_PULSING_EN)
+
+#define INTERRUPT_STATUS_BITS_MASK \
+ (INTSTS_USB_ID | \
+ INTR_1MS_TIMER_EN | \
+ INTSTS_A_VBUS_VALID | \
+ INTSTS_A_SESSION_VALID | \
+ INTSTS_B_SESSION_VALID | \
+ INTSTS_B_SESSION_END | \
+ INTSTS_DATA_PULSING)
+
+#define FSL_SOC_USB_USBMODE 0x1a8
+
+#define USBGENCTRL 0x200 /* NOTE: big endian */
+#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */
+#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/
+#define GC_PPP (1 << 3) /* Port Power Polarity */
+#define GC_PFP (1 << 2) /* Power Fault Polarity */
+#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */
+#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */
+
+#define ISIPHYCTRL 0x204 /* NOTE: big endian */
+#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
+#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
+#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */
+#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */
+#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
+
+#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
+#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
+#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
+#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
+#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
+#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
+#define SNOOP_SIZE_2GB 0x1e
+
+/* System Clock Control Register */
+#define MPC83XX_SCCR_USB_MASK 0x00f00000
+#define MPC83XX_SCCR_USB_DRCM_11 0x00300000
+#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
+#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
+
+#if defined(CONFIG_MPC83xx)
+#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
+#elif defined(CONFIG_MPC85xx)
+#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
+#elif defined(CONFIG_MPC512X)
+#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
+#endif
+
+/*
+ * USB Registers
+ */
+struct usb_ehci {
+ u32 id; /* 0x000 - Identification register */
+ u32 hwgeneral; /* 0x004 - General hardware parameters */
+ u32 hwhost; /* 0x008 - Host hardware parameters */
+ u32 hwdevice; /* 0x00C - Device hardware parameters */
+ u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
+ u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
+ u8 res1[0x68];
+ u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
+ u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
+ u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
+ u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
+ u32 sbuscfg; /* 0x090 - System Bus Interface Control */
+ u8 res2[0x6C];
+ u16 caplength; /* 0x100 - Capability Register Length */
+ u16 hciversion; /* 0x102 - Host Interface Version */
+ u32 hcsparams; /* 0x104 - Host Structural Parameters */
+ u32 hccparams; /* 0x108 - Host Capability Parameters */
+ u8 res3[0x14];
+ u32 dciversion; /* 0x120 - Device Interface Version */
+ u32 dciparams; /* 0x124 - Device Controller Params */
+ u8 res4[0x18];
+ u32 usbcmd; /* 0x140 - USB Command */
+ u32 usbsts; /* 0x144 - USB Status */
+ u32 usbintr; /* 0x148 - USB Interrupt Enable */
+ u32 frindex; /* 0x14C - USB Frame Index */
+ u8 res5[0x4];
+ u32 perlistbase; /* 0x154 - Periodic List Base
+ - USB Device Address */
+ u32 ep_list_addr; /* 0x158 - Next Asynchronous List
+ - End Point Address */
+ u8 res6[0x4];
+ u32 burstsize; /* 0x160 - Programmable Burst Size */
+#define FSL_EHCI_TXPBURST(X) ((X) << 8)
+#define FSL_EHCI_RXPBURST(X) (X)
+ u32 txfilltuning; /* 0x164 - Host TT Transmit
+ pre-buffer packet tuning */
+ u8 res7[0x8];
+ u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
+ u8 res8[0xc];
+ u32 config_flag; /* 0x180 - Configured Flag Register */
+ u32 portsc; /* 0x184 - Port status/control */
+ u8 res9[0x1C];
+ u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
+ u32 usbmode; /* 0x1a8 - USB Device Mode */
+ u32 epsetupstat; /* 0x1ac - End Point Setup Status */
+ u32 epprime; /* 0x1b0 - End Point Init Status */
+ u32 epflush; /* 0x1b4 - End Point De-initlialize */
+ u32 epstatus; /* 0x1b8 - End Point Status */
+ u32 epcomplete; /* 0x1bc - End Point Complete */
+ u32 epctrl0; /* 0x1c0 - End Point Control 0 */
+ u32 epctrl1; /* 0x1c4 - End Point Control 1 */
+ u32 epctrl2; /* 0x1c8 - End Point Control 2 */
+ u32 epctrl3; /* 0x1cc - End Point Control 3 */
+ u32 epctrl4; /* 0x1d0 - End Point Control 4 */
+ u32 epctrl5; /* 0x1d4 - End Point Control 5 */
+ u8 res10[0x28];
+ u32 usbgenctrl; /* 0x200 - USB General Control */
+ u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
+ u8 res11[0x1F8];
+ u32 snoop1; /* 0x400 - Snoop 1 */
+ u32 snoop2; /* 0x404 - Snoop 2 */
+ u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
+ u32 prictrl; /* 0x40c - Priority Control */
+ u32 sictrl; /* 0x410 - System Interface Control */
+ u8 res12[0xEC];
+ u32 control; /* 0x500 - Control */
+ u8 res13[0xafc];
+};
+
+#endif /* _EHCI_FSL_H */
diff --git a/boot/common/src/uboot/include/usb/global.h b/boot/common/src/uboot/include/usb/global.h
new file mode 100755
index 0000000..0848f70
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/global.h
@@ -0,0 +1,56 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ£º global.c
+* Îļþ±êʶ£º
+* ÄÚÈÝÕªÒª£º È«¾Ö±äÁ¿¼°³õʼ»¯
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº ÎÌÔÆ·å
+* Íê³ÉÈÕÆÚ£º
+*******************************************************************************/
+#ifndef __GLOBAL_H_
+#define __GLOBAL_H_
+#include "common.h"
+#include "usb_config.h"
+#include <linux/types.h>
+#include "dwc_otg_driver.h"
+
+
+struct g_data
+{
+ dwc_otg_device_t g_dwc_otg_dev_t;
+ u32 dwRxQuit;
+ u32 dwTxQuit;
+ u32 g_Connet;
+ u32 g_USB_MODE;
+ u32 g_USB_TIMEOUT;
+ u16 g_status_buf;
+ int g_State;
+ int g_bootfinish;
+ int g_bootaddr;
+ int g_bootsize;
+ int g_boot_save_size;
+ int g_boot_save_addr;
+
+ dwc_otg_core_if_t core_if_t;
+ dwc_otg_dev_if_t dev_if_t;
+ dwc_otg_core_params_t g_core_params;
+
+ u32 g_in_pPara[3];
+ u32 g_out_pPara[3];
+ u_setup_pkt g_u_setup_pkt[sizeof(u_setup_pkt)*5];
+ dwc_otg_pcd_t g_dwc_otg_pcd_tp;
+ u32 g_pll_cfg;
+ int g_enum;
+};
+
+
+extern struct g_data global;
+extern dwc_config_all_t g_config_desc;
+
+
+#endif
+extern void data_init(void);
+
+
diff --git a/boot/common/src/uboot/include/usb/musb_udc.h b/boot/common/src/uboot/include/usb/musb_udc.h
new file mode 100644
index 0000000..be808fd
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/musb_udc.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __MUSB_UDC_H__
+#define __MUSB_UDC_H__
+
+#include <usbdevice.h>
+
+/* UDC level routines */
+void udc_irq(void);
+void udc_set_nak(int ep_num);
+void udc_unset_nak(int ep_num);
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
+ struct usb_endpoint_instance *endpoint);
+void udc_connect(void);
+void udc_disconnect(void);
+void udc_enable(struct usb_device_instance *device);
+void udc_disable(void);
+void udc_startup_events(struct usb_device_instance *device);
+int udc_init(void);
+
+/* usbtty */
+#ifdef CONFIG_USB_TTY
+
+#define EP0_MAX_PACKET_SIZE 64 /* MUSB_EP0_FIFOSIZE */
+#define UDC_INT_ENDPOINT 1
+#define UDC_INT_PACKET_SIZE 64
+#define UDC_OUT_ENDPOINT 2
+#define UDC_OUT_PACKET_SIZE 64
+#define UDC_IN_ENDPOINT 3
+#define UDC_IN_PACKET_SIZE 64
+#define UDC_BULK_PACKET_SIZE 64
+
+#endif /* CONFIG_USB_TTY */
+
+#endif /* __MUSB_UDC_H__ */
diff --git a/boot/common/src/uboot/include/usb/spr_udc.h b/boot/common/src/uboot/include/usb/spr_udc.h
new file mode 100644
index 0000000..2c332d5
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/spr_udc.h
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPR_UDC_H
+#define __SPR_UDC_H
+
+/*
+ * Defines for USBD
+ *
+ * The udc_ahb controller has three AHB slaves:
+ *
+ * 1. THe UDC registers
+ * 2. The plug detect
+ * 3. The RX/TX FIFO
+ */
+
+#define MAX_ENDPOINTS 16
+
+struct udc_endp_regs {
+ u32 endp_cntl;
+ u32 endp_status;
+ u32 endp_bsorfn;
+ u32 endp_maxpacksize;
+ u32 reserved_1;
+ u32 endp_desc_point;
+ u32 reserved_2;
+ u32 write_done;
+};
+
+/* Endpoint Control Register definitions */
+
+#define ENDP_CNTL_STALL 0x00000001
+#define ENDP_CNTL_FLUSH 0x00000002
+#define ENDP_CNTL_SNOOP 0x00000004
+#define ENDP_CNTL_POLL 0x00000008
+#define ENDP_CNTL_CONTROL 0x00000000
+#define ENDP_CNTL_ISO 0x00000010
+#define ENDP_CNTL_BULK 0x00000020
+#define ENDP_CNTL_INT 0x00000030
+#define ENDP_CNTL_NAK 0x00000040
+#define ENDP_CNTL_SNAK 0x00000080
+#define ENDP_CNTL_CNAK 0x00000100
+#define ENDP_CNTL_RRDY 0x00000200
+
+/* Endpoint Satus Register definitions */
+
+#define ENDP_STATUS_PIDMSK 0x0000000f
+#define ENDP_STATUS_OUTMSK 0x00000030
+#define ENDP_STATUS_OUT_NONE 0x00000000
+#define ENDP_STATUS_OUT_DATA 0x00000010
+#define ENDP_STATUS_OUT_SETUP 0x00000020
+#define ENDP_STATUS_IN 0x00000040
+#define ENDP_STATUS_BUFFNAV 0x00000080
+#define ENDP_STATUS_FATERR 0x00000100
+#define ENDP_STATUS_HOSTBUSERR 0x00000200
+#define ENDP_STATUS_TDC 0x00000400
+#define ENDP_STATUS_RXPKTMSK 0x003ff800
+
+struct udc_regs {
+ struct udc_endp_regs in_regs[MAX_ENDPOINTS];
+ struct udc_endp_regs out_regs[MAX_ENDPOINTS];
+ u32 dev_conf;
+ u32 dev_cntl;
+ u32 dev_stat;
+ u32 dev_int;
+ u32 dev_int_mask;
+ u32 endp_int;
+ u32 endp_int_mask;
+ u32 reserved_3[0x39];
+ u32 reserved_4; /* offset 0x500 */
+ u32 udc_endp_reg[MAX_ENDPOINTS];
+};
+
+/* Device Configuration Register definitions */
+
+#define DEV_CONF_HS_SPEED 0x00000000
+#define DEV_CONF_LS_SPEED 0x00000002
+#define DEV_CONF_FS_SPEED 0x00000003
+#define DEV_CONF_REMWAKEUP 0x00000004
+#define DEV_CONF_SELFPOW 0x00000008
+#define DEV_CONF_SYNCFRAME 0x00000010
+#define DEV_CONF_PHYINT_8 0x00000020
+#define DEV_CONF_PHYINT_16 0x00000000
+#define DEV_CONF_UTMI_BIDIR 0x00000040
+#define DEV_CONF_STATUS_STALL 0x00000080
+
+/* Device Control Register definitions */
+
+#define DEV_CNTL_RESUME 0x00000001
+#define DEV_CNTL_TFFLUSH 0x00000002
+#define DEV_CNTL_RXDMAEN 0x00000004
+#define DEV_CNTL_TXDMAEN 0x00000008
+#define DEV_CNTL_DESCRUPD 0x00000010
+#define DEV_CNTL_BIGEND 0x00000020
+#define DEV_CNTL_BUFFILL 0x00000040
+#define DEV_CNTL_TSHLDEN 0x00000080
+#define DEV_CNTL_BURSTEN 0x00000100
+#define DEV_CNTL_DMAMODE 0x00000200
+#define DEV_CNTL_SOFTDISCONNECT 0x00000400
+#define DEV_CNTL_SCALEDOWN 0x00000800
+#define DEV_CNTL_BURSTLENU 0x00010000
+#define DEV_CNTL_BURSTLENMSK 0x00ff0000
+#define DEV_CNTL_TSHLDLENU 0x01000000
+#define DEV_CNTL_TSHLDLENMSK 0xff000000
+
+/* Device Status Register definitions */
+
+#define DEV_STAT_CFG 0x0000000f
+#define DEV_STAT_INTF 0x000000f0
+#define DEV_STAT_ALT 0x00000f00
+#define DEV_STAT_SUSP 0x00001000
+#define DEV_STAT_ENUM 0x00006000
+#define DEV_STAT_ENUM_SPEED_HS 0x00000000
+#define DEV_STAT_ENUM_SPEED_FS 0x00002000
+#define DEV_STAT_ENUM_SPEED_LS 0x00004000
+#define DEV_STAT_RXFIFO_EMPTY 0x00008000
+#define DEV_STAT_PHY_ERR 0x00010000
+#define DEV_STAT_TS 0xf0000000
+
+/* Device Interrupt Register definitions */
+
+#define DEV_INT_MSK 0x0000007f
+#define DEV_INT_SETCFG 0x00000001
+#define DEV_INT_SETINTF 0x00000002
+#define DEV_INT_INACTIVE 0x00000004
+#define DEV_INT_USBRESET 0x00000008
+#define DEV_INT_SUSPUSB 0x00000010
+#define DEV_INT_SOF 0x00000020
+#define DEV_INT_ENUM 0x00000040
+
+/* Endpoint Interrupt Register definitions */
+
+#define ENDP0_INT_CTRLIN 0x00000001
+#define ENDP1_INT_BULKIN 0x00000002
+#define ENDP_INT_NONISOIN_MSK 0x0000AAAA
+#define ENDP2_INT_BULKIN 0x00000004
+#define ENDP0_INT_CTRLOUT 0x00010000
+#define ENDP1_INT_BULKOUT 0x00020000
+#define ENDP2_INT_BULKOUT 0x00040000
+#define ENDP_INT_NONISOOUT_MSK 0x55540000
+
+/* Endpoint Register definitions */
+#define ENDP_EPDIR_OUT 0x00000000
+#define ENDP_EPDIR_IN 0x00000010
+#define ENDP_EPTYPE_CNTL 0x0
+#define ENDP_EPTYPE_ISO 0x1
+#define ENDP_EPTYPE_BULK 0x2
+#define ENDP_EPTYPE_INT 0x3
+
+/*
+ * Defines for Plug Detect
+ */
+
+struct plug_regs {
+ u32 plug_state;
+ u32 plug_pending;
+};
+
+/* Plug State Register definitions */
+#define PLUG_STATUS_EN 0x1
+#define PLUG_STATUS_ATTACHED 0x2
+#define PLUG_STATUS_PHY_RESET 0x4
+#define PLUG_STATUS_PHY_MODE 0x8
+
+/*
+ * Defines for UDC FIFO (Slave Mode)
+ */
+struct udcfifo_regs {
+ u32 *fifo_p;
+};
+
+/*
+ * USBTTY definitions
+ */
+#define EP0_MAX_PACKET_SIZE 64
+#define UDC_INT_ENDPOINT 1
+#define UDC_INT_PACKET_SIZE 64
+#define UDC_OUT_ENDPOINT 2
+#define UDC_BULK_PACKET_SIZE 64
+#define UDC_IN_ENDPOINT 3
+#define UDC_OUT_PACKET_SIZE 64
+#define UDC_IN_PACKET_SIZE 64
+
+/*
+ * UDC endpoint definitions
+ */
+#define UDC_EP0 0
+#define UDC_EP1 1
+#define UDC_EP2 2
+#define UDC_EP3 3
+
+/*
+ * Function declarations
+ */
+
+void udc_irq(void);
+
+void udc_set_nak(int epid);
+void udc_unset_nak(int epid);
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+int udc_init(void);
+void udc_enable(struct usb_device_instance *device);
+void udc_disable(void);
+void udc_connect(void);
+void udc_disconnect(void);
+void udc_startup_events(struct usb_device_instance *device);
+void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
+ struct usb_endpoint_instance *endpoint);
+
+#endif /* __SPR_UDC_H */
diff --git a/boot/common/src/uboot/include/usb/type.h b/boot/common/src/uboot/include/usb/type.h
new file mode 100755
index 0000000..f9c5f41
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/type.h
@@ -0,0 +1,59 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ£º types.h
+* ÄÚÈÝÕªÒª£º Êý¾ÝÀàÐͶ¨Òå
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº 177792
+* Íê³ÉÈÕÆÚ£º 2010-9-30
+*
+*
+*******************************************************************************/
+
+#ifndef __INCLUDE_TYPES_H
+#define __INCLUDE_TYPES_H
+#include <linux/types.h>
+#if 0
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+typedef unsigned long long u64;
+#endif
+
+typedef u8 BYTE;
+typedef u32 WORD32;
+typedef u16 WORD16;
+
+#if 0
+typedef int int32_t;
+typedef u32 uint32_t;
+typedef u16 uint16_t;
+typedef u8 uint8_t;
+#endif
+
+#define NULL (void *)0
+
+#define MIN(x,y) ((x) < (y) ? (x) : (y))
+#define MAX(x,y) ((x) > (y) ? (x) : (y))
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define REG(x) (*(volatile u32*)(x))
+#define REG8(x) (*(volatile u8*)(x))
+#define REG16(x) (*(volatile u16*)(x))
+#define REG32(x) (*(volatile u32*)(x))
+#define DWC_READ_REG32(a) (*(volatile u32 *)(a))
+#define DWC_WRITE_REG32(a,v) ((*(volatile u32 *)(a)) = v)
+
+// ÏÂÃæÊÇGCC±àÒëÑ¡ÏÒå
+#define __weak__ __attribute__((weak))
+#define __aligned(x) __attribute__((aligned(x)))
+#define __align(x) __attribute__((aligned(x)))
+
+
+#endif
+
diff --git a/boot/common/src/uboot/include/usb/usb.h b/boot/common/src/uboot/include/usb/usb.h
new file mode 100755
index 0000000..169e551
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/usb.h
@@ -0,0 +1,628 @@
+/*
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Lennart Augustsson (lennart@augustsson.net) at
+ * Carlstedt Research & Technology.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Modified by Synopsys, Inc, 12/12/2007 */
+
+
+#ifndef _USB_H_
+#define _USB_H_
+
+#include "common.h"
+#include <linux/types.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// T_LANGID_DESCRIPTOR
+#define LANGID_US_ENGLISH 0x0409
+
+// T_STRING_DESCRIPTOR
+#define MAX_STRING_LENGTH (0x20)//(0x100)
+
+
+typedef enum
+{
+
+ NEED_ENUM = 0,
+ DONOT_NEED_ENUM
+
+}T_USB_ENUM;
+
+/*usb´«ÊäÀàÐÍ*/
+typedef enum
+{
+ TRA_CTRL = 0,
+ TRA_BULK,
+ TRA_INTR,
+ TRA_ISO
+}T_USB_TRAN;
+
+/* USB¿ØÖÆ´«ÊäÃüÁî*/
+typedef struct
+{
+ BYTE bmRequestType;
+ BYTE bRequest;
+ WORD16 wValue;
+ WORD16 wIndex;
+ WORD16 wLength;
+}T_CTRL_COMMAND;
+
+
+// ¶ËµãÊý¾Ý°ü´óС
+typedef enum
+{
+ CONTROL_8 =8,
+ CONTROL_16 =16,
+ CONTROL_32 =32,
+ CONTROL_64 =64,
+
+ BULK_8 =8,
+ BULK_16 =16,
+ BULK_32 =32,
+ BULKL_64 =64
+}T_EP_PKT_SIZE;
+
+
+// CLEAR_FEATURE, SET_FEATURE
+#define FEATURE_DEVICE_REMOTE_WAKEUP (0x1)
+#define FEATURE_ENDPOINT_HALT (0x0)
+#define FEATURE_TEST_MODE (0x2)
+
+// ¸ù¾Ýʵ¼ÊÇé¿öÐÞ¸Ä
+#define USB_VENDOR_ID (0x19D2) // 2×Ö½Ú
+#define USB_PRODUCT_ID (0x0256) // 2×Ö½Ú
+#define PRODUCT_RELEASE_NUMBER (0x7520) // 2×Ö½Ú
+
+#define VERDOR_SPECIFIC (0xff)
+
+#define EP0_PACKET_SIZE CONTROL_64
+#define EP1_PACKET_SIZE 64
+#define EPX_PACKET_SIZE 64
+
+#define EP_FOR_IN 2
+#define EP_FOR_OUT 3
+
+
+/*usbÉ豸µÄÆ߸ö״̬*/
+typedef enum
+{
+ eUSB_ATTACHED = 0,
+ eUSB_POWERED,
+ eUSB_DEFAULT,
+ eUSB_SUSPEND,
+ eUSB_RUSUME,
+ eUSB_ADDRESS,
+ eUSB_CONFIG
+}E_USB_STATE;
+
+
+// ±ê×¼ÇëÇóÃüÁî
+typedef enum
+{
+ GET_STATUS =0x0,
+ CLEAR_FEATURE =0x1,
+ SET_FEATURE =0x3,
+ SET_ADDRESS =0x5,
+ GET_DESCRIPTOR =0x6,
+ SET_DESCRIPTOR =0x7,
+ GET_CONFIGURATION =0x8,
+ SET_CONFIGURATION =0x9,
+ GET_INTERFACE =0xa,
+ SET_INTERFACE =0xb,
+ SYNCH_FRAME =0xc
+}T_STANDARD_REQUST;
+
+
+// ÃèÊö·ûÀàÐÍ
+typedef enum
+{
+ DEVICE_DESCRIPTOR = 0x01,
+ CONFIG_DESCRIPTOR = 0x02,
+ STRING_DESCRIPTOR = 0x03,
+ INTERFACE_DESCRIPTOR= 0x04,
+ ENDPOINT_DESCRIPTOR = 0x05
+} T_DESCRIPTORS_TYPE;
+
+// USBÖ§³ÖµÄÌØÕ÷¶¨Òå
+typedef enum
+{
+ DEVICE_REMOTE_WAKEUP =1, // Device
+ ENDPOINT_HALT =0, // Endpoint
+ TEST_MODE =2 //Device
+}T_FEATURE;
+
+
+// bmAttributes
+#define ATTR_D7 (0x01 <<7) // ±ØÐëΪ1
+#define ATTR_SELF_POWERED (0x01 <<6) // ×Ô¹©µç
+#define ATTR_SUPPORT_REMOTE_WAKEUP (0x01 <<5) // Ô¶³Ì»½ÐÑ
+
+// bMaxPower
+#define POWER_MA(power) (power>>1) // µ¥Î»: 2mA
+
+#define EP_ADDRESS_DIRECTION_MASK (0x01 <<7) //Direction, ignored for control endpoints
+#define EP_ADDRESS_DIRECTION_IN (0x01 <<7)
+#define EP_ADDRESS_DIRECTION_OUT (0x0 <<7)
+
+
+//bmAttributes
+#define EP_ATTR_TRANSFER_TYPE_MASK (0x03 <<0)
+#define EP_ATTR_TRANSFER_TYPE_CONTROL (0 <<0)
+#define EP_ATTR_TRANSFER_TYPE_ISO (1 <<0)
+#define EP_ATTR_TRANSFER_TYPE_BULK (2 <<0)
+#define EP_ATTR_TRANSFER_TYPE_INTERRUPT (3 <<0)
+
+//ͬ²½´«Êä¶Ëµã, ×î´ó1023×Ö½Ú, ÂÖѯ¼ä¸ô---2^(bInterval -1)Ö¡
+#define MAX_ISO_PKT (256) //×î´ó1023×Ö½Ú
+#define MAX_ISO_R_INTERVAL (1) //ÂÖѯ¼ä¸ô---2^(bInterval -1)Ö¡
+#define MAX_ISO_T_INTERVAL (1) //ÂÖѯ¼ä¸ô---2^(bInterval -1)Ö¡
+
+//T_STRING_DESCRIPTOR, ascii to unicode---*2, length,type--+2
+#define STRING_DESCRIPTOR_SIZE(size) ((size*2)+2)
+//ת»»ascii×Ö·ûΪunicode×Ö·û
+#define UNICODE(ascii) ascii,0x00
+
+/**************************************************************************/
+typedef uint8_t uByte;
+typedef uint8_t uWord[2];
+typedef uint8_t uDWord[4];
+
+
+#define UT_GET_TYPE(a) ((a) & 0x60)
+#define UT_STANDARD 0x00
+#define UT_CLASS 0x20
+#define UT_VENDOR 0x40
+
+#define UT_GET_RECIPIENT(a) ((a) & 0x1f)
+#define UT_DEVICE 0x00
+#define UT_INTERFACE 0x01
+#define UT_ENDPOINT 0x02
+#define UT_OTHER 0x03
+/* Requests */
+#define UR_GET_STATUS 0x00
+#define USTAT_STANDARD_STATUS 0x00
+#define UR_CLEAR_FEATURE 0x01
+#define UR_SET_FEATURE 0x03
+#define UR_SET_ADDRESS 0x05
+#define UR_GET_DESCRIPTOR 0x06
+#define UR_SET_CONFIG 0x09
+/* Feature numbers */
+#define UF_ENDPOINT_HALT 0
+
+
+
+
+
+#define UE_GET_DIR(a) ((a) & 0x80)
+#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7))
+#define UE_DIR_IN 0x80
+#define UE_DIR_OUT 0x00
+#define UE_ADDR 0x0f
+#define UE_GET_ADDR(a) ((a) & UE_ADDR)
+
+
+#define USB_MAX_STRING_LEN 128
+#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */
+
+/* Hub specific request */
+#define UR_GET_BUS_STATE 0x02
+#define UR_CLEAR_TT_BUFFER 0x08
+#define UR_RESET_TT 0x09
+#define UR_GET_TT_STATE 0x0a
+#define UR_STOP_TT 0x0b
+
+/* Hub features */
+#define UHF_C_HUB_LOCAL_POWER 0
+#define UHF_C_HUB_OVER_CURRENT 1
+#define UHF_PORT_CONNECTION 0
+#define UHF_PORT_ENABLE 1
+#define UHF_PORT_SUSPEND 2
+#define UHF_PORT_OVER_CURRENT 3
+#define UHF_PORT_RESET 4
+#define UHF_PORT_L1 5
+#define UHF_PORT_POWER 8
+#define UHF_PORT_LOW_SPEED 9
+#define UHF_PORT_HIGH_SPEED 10
+#define UHF_C_PORT_CONNECTION 16
+#define UHF_C_PORT_ENABLE 17
+#define UHF_C_PORT_SUSPEND 18
+#define UHF_C_PORT_OVER_CURRENT 19
+#define UHF_C_PORT_RESET 20
+#define UHF_C_PORT_L1 23
+#define UHF_PORT_TEST 21
+#define UHF_PORT_INDICATOR 22
+
+#define UHD_PWR 0x0003
+#define UHD_PWR_GANGED 0x0000
+#define UHD_PWR_INDIVIDUAL 0x0001
+#define UHD_PWR_NO_SWITCH 0x0002
+#define UHD_COMPOUND 0x0004
+#define UHD_OC 0x0018
+#define UHD_OC_GLOBAL 0x0000
+#define UHD_OC_INDIVIDUAL 0x0008
+#define UHD_OC_NONE 0x0010
+#define UHD_TT_THINK 0x0060
+#define UHD_TT_THINK_8 0x0000
+#define UHD_TT_THINK_16 0x0020
+#define UHD_TT_THINK_24 0x0040
+#define UHD_TT_THINK_32 0x0060
+#define UHD_PORT_IND 0x0080
+#define UHD_PWRON_FACTOR 2
+#define UHD_NOT_REMOV(desc, i) (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1)
+
+#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */
+
+
+/* OTG feature selectors */
+#define UOTG_B_HNP_ENABLE 3
+#define UOTG_A_HNP_SUPPORT 4
+#define UOTG_A_ALT_HNP_SUPPORT 5
+
+/* Device status flags */
+#define UDS_SELF_POWERED 0x0001
+#define UDS_REMOTE_WAKEUP 0x0002
+/* Endpoint status flags */
+#define UES_HALT 0x0001
+
+
+
+#define UHS_LOCAL_POWER 0x0001
+#define UHS_OVER_CURRENT 0x0002
+
+
+
+#define UPS_CURRENT_CONNECT_STATUS 0x0001
+#define UPS_PORT_ENABLED 0x0002
+#define UPS_SUSPEND 0x0004
+#define UPS_OVERCURRENT_INDICATOR 0x0008
+#define UPS_RESET 0x0010
+#define UPS_PORT_POWER 0x0100
+#define UPS_LOW_SPEED 0x0200
+#define UPS_HIGH_SPEED 0x0400
+#define UPS_PORT_TEST 0x0800
+#define UPS_PORT_INDICATOR 0x1000
+#define UPS_C_CONNECT_STATUS 0x0001
+#define UPS_C_PORT_ENABLED 0x0002
+#define UPS_C_SUSPEND 0x0004
+#define UPS_C_OVERCURRENT_INDICATOR 0x0008
+#define UPS_C_PORT_RESET 0x0010
+
+
+/* Device class codes */
+#define UDCLASS_IN_INTERFACE 0x00
+#define UDCLASS_COMM 0x02
+#define UDCLASS_HUB 0x09
+#define UDSUBCLASS_HUB 0x00
+#define UDPROTO_FSHUB 0x00
+#define UDPROTO_HSHUBSTT 0x01
+#define UDPROTO_HSHUBMTT 0x02
+#define UDCLASS_DIAGNOSTIC 0xdc
+#define UDCLASS_WIRELESS 0xe0
+#define UDSUBCLASS_RF 0x01
+#define UDPROTO_BLUETOOTH 0x01
+#define UDCLASS_VENDOR 0xff
+
+/* Interface class codes */
+#define UICLASS_UNSPEC 0x00
+
+#define UICLASS_AUDIO 0x01
+#define UISUBCLASS_AUDIOCONTROL 1
+#define UISUBCLASS_AUDIOSTREAM 2
+#define UISUBCLASS_MIDISTREAM 3
+
+#define UICLASS_CDC 0x02 /* communication */
+#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1
+#define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2
+#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3
+#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4
+#define UISUBCLASS_CAPI_CONTROLMODEL 5
+#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6
+#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7
+#define UIPROTO_CDC_AT 1
+
+#define UICLASS_HID 0x03
+#define UISUBCLASS_BOOT 1
+#define UIPROTO_BOOT_KEYBOARD 1
+
+#define UICLASS_PHYSICAL 0x05
+
+#define UICLASS_IMAGE 0x06
+
+#define UICLASS_PRINTER 0x07
+#define UISUBCLASS_PRINTER 1
+#define UIPROTO_PRINTER_UNI 1
+#define UIPROTO_PRINTER_BI 2
+#define UIPROTO_PRINTER_1284 3
+
+#define UICLASS_MASS 0x08
+#define UISUBCLASS_RBC 1
+#define UISUBCLASS_SFF8020I 2
+#define UISUBCLASS_QIC157 3
+#define UISUBCLASS_UFI 4
+#define UISUBCLASS_SFF8070I 5
+#define UISUBCLASS_SCSI 6
+#define UIPROTO_MASS_CBI_I 0
+#define UIPROTO_MASS_CBI 1
+#define UIPROTO_MASS_BBB_OLD 2 /* Not in the spec anymore */
+#define UIPROTO_MASS_BBB 80 /* 'P' for the Iomega Zip drive */
+
+#define UICLASS_HUB 0x09
+#define UISUBCLASS_HUB 0
+#define UIPROTO_FSHUB 0
+#define UIPROTO_HSHUBSTT 0 /* Yes, same as previous */
+#define UIPROTO_HSHUBMTT 1
+
+#define UICLASS_CDC_DATA 0x0a
+#define UISUBCLASS_DATA 0
+#define UIPROTO_DATA_ISDNBRI 0x30 /* Physical iface */
+#define UIPROTO_DATA_HDLC 0x31 /* HDLC */
+#define UIPROTO_DATA_TRANSPARENT 0x32 /* Transparent */
+#define UIPROTO_DATA_Q921M 0x50 /* Management for Q921 */
+#define UIPROTO_DATA_Q921 0x51 /* Data for Q921 */
+#define UIPROTO_DATA_Q921TM 0x52 /* TEI multiplexer for Q921 */
+#define UIPROTO_DATA_V42BIS 0x90 /* Data compression */
+#define UIPROTO_DATA_Q931 0x91 /* Euro-ISDN */
+#define UIPROTO_DATA_V120 0x92 /* V.24 rate adaption */
+#define UIPROTO_DATA_CAPI 0x93 /* CAPI 2.0 commands */
+#define UIPROTO_DATA_HOST_BASED 0xfd /* Host based driver */
+#define UIPROTO_DATA_PUF 0xfe /* see Prot. Unit Func. Desc.*/
+#define UIPROTO_DATA_VENDOR 0xff /* Vendor specific */
+
+#define UICLASS_SMARTCARD 0x0b
+
+/*#define UICLASS_FIRM_UPD 0x0c*/
+
+#define UICLASS_SECURITY 0x0d
+
+#define UICLASS_DIAGNOSTIC 0xdc
+
+#define UICLASS_WIRELESS 0xe0
+#define UISUBCLASS_RF 0x01
+#define UIPROTO_BLUETOOTH 0x01
+
+#define UICLASS_APPL_SPEC 0xfe
+#define UISUBCLASS_FIRMWARE_DOWNLOAD 1
+#define UISUBCLASS_IRDA 2
+#define UIPROTO_IRDA 0
+
+#define UICLASS_VENDOR 0xff
+
+#define USB_HUB_MAX_DEPTH 5
+
+/*
+ * Minimum time a device needs to be powered down to go through
+ * a power cycle. XXX Are these time in the spec?
+ */
+#define USB_POWER_DOWN_TIME 200 /* ms */
+#define USB_PORT_POWER_DOWN_TIME 100 /* ms */
+
+
+/* Allow for marginal (i.e. non-conforming) devices. */
+#define USB_PORT_RESET_DELAY 50 /* ms */
+#define USB_PORT_ROOT_RESET_DELAY 250 /* ms */
+#define USB_PORT_RESET_RECOVERY 250 /* ms */
+#define USB_PORT_POWERUP_DELAY 300 /* ms */
+#define USB_SET_ADDRESS_SETTLE 10 /* ms */
+#define USB_RESUME_DELAY (50*5) /* ms */
+#define USB_RESUME_WAIT 50 /* ms */
+#define USB_RESUME_RECOVERY 50 /* ms */
+#define USB_EXTRA_POWER_UP_TIME 20 /* ms */
+
+
+#define USB_MIN_POWER 100 /* mA */
+#define USB_MAX_POWER 500 /* mA */
+
+#define USB_BUS_RESET_DELAY 100 /* ms XXX?*/
+
+#define USB_UNCONFIG_NO 0
+#define USB_UNCONFIG_INDEX (-1)
+
+typedef struct usb_device_request_t
+{
+ uint8_t bmRequestType;
+ uint8_t bRequest;
+ uint16_t wValue;
+ uint16_t wIndex;
+ uint16_t wLength;
+} __attribute__ ((__packed__)) usb_device_request_t;
+
+/*** ioctl() related stuff ***/
+
+#define USBD_SHORT_XFER_OK 0x04 /* allow short reads */
+#define USB_CURRENT_CONFIG_INDEX (-1)
+#define USB_CURRENT_ALT_INDEX (-1)
+
+
+
+typedef struct usb_endpoint_descriptor_t
+{
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bEndpointAddress;
+ uint8_t bmAttributes;
+ uint16_t wMaxPacketSize;
+ uint8_t bInterval;
+} __attribute__ ((__packed__)) usb_endpoint_descriptor_t;
+
+#define USB_MAX_DEVNAMES 4
+#define USB_MAX_DEVNAMELEN 16
+#define USB_SPEED_UNKNOWN 0
+#define USB_SPEED_LOW 1
+#define USB_SPEED_FULL 2
+#define USB_SPEED_HIGH 3
+/*
+ * USB directions
+ *
+ * This bit flag is used in endpoint descriptors' bEndpointAddress field.
+ * It's also one of three fields in control requests bRequestType.
+ */
+#define USB_DIR_OUT 0 /* to device */
+#define USB_DIR_IN 0x80 /* to host */
+
+#define USB_DT_DEVICE 0x01
+#define USB_DT_CONFIG 0x02
+#define USB_DT_STRING 0x03
+#define USB_DT_INTERFACE 0x04
+#define USB_DT_ENDPOINT 0x05
+#define USB_DT_DEVICE_QUALIFIER 0x06
+#define USB_DT_OTHER_SPEED_CONFIG 0x07
+#define USB_DT_INTERFACE_POWER 0x08
+
+/***************************************************/
+// ±ê×¼½Ó¿ÚÃèÊö·û
+typedef struct dwc_interface_descriptor_t
+{
+ BYTE bLength;
+ BYTE bDescriptorType;
+ BYTE bInterfaceNumber;
+ BYTE bAlternateSetting;
+ BYTE bNumEndpoints;
+ BYTE bInterfaceClass;
+ BYTE bInterfaceSubClass;
+ BYTE bInterfaceProtocol;
+ BYTE iInterface;
+}__attribute__ ((__packed__)) dwc_interface_descriptor_t;
+
+
+// ±ê×¼¶ËµãÃèÊö·û
+typedef struct dwc_ep_descriptor_t
+{
+ BYTE bLength;
+ BYTE bDescriptorType;
+ BYTE bEndpointAddress;
+ BYTE bmAttributes;
+ WORD16 wMaxPacketSize;
+ BYTE bInterval;
+}__attribute__ ((__packed__)) dwc_ep_descriptor_t;
+
+
+// ×Ö·û´®ÃèÊö·û
+typedef struct dwc_langid_descriptor_t
+{
+ BYTE bLength;
+ BYTE bDescriptorType;
+ WORD16 wLANGID0;
+
+}__attribute__ ((__packed__)) dwc_langid_descriptor_t;
+
+typedef struct dwc_string_descriptor_t
+{
+ BYTE bLength;
+ BYTE bDescriptorType;
+ BYTE bString[MAX_STRING_LENGTH];
+
+}__attribute__ ((__packed__)) dwc_string_descriptor_t;
+
+// É豸ÃèÊö·û
+typedef struct dwc_device_descriptor_t
+{
+ BYTE bLength;
+ BYTE bDescriptorType;
+ WORD16 bcdUSB;
+ BYTE bDeviceClass;
+ BYTE bDeviceSubClass;
+ BYTE bDeviceProtocol;
+ BYTE bMaxPacketSize0;
+ WORD16 idVendor;
+ WORD16 idProduct;
+ WORD16 bcdDevice;
+ BYTE iManufacturer;
+ BYTE iProduct;
+ BYTE iSerialNumber;
+ BYTE bNumConfigurations;
+}__attribute__ ((__packed__)) dwc_device_descriptor_t;
+
+//device qualifierÃèÊö·û
+typedef struct dwc_dev_qual_descriptor_t
+{
+ BYTE bLength;
+ BYTE bDescriptorType;
+ WORD16 bcdUSB;
+ BYTE bDeviceClass;
+ BYTE bDeviceSubClass;
+ BYTE bDeviceProtocol;
+ BYTE bMaxPacketSize0;
+ BYTE bNumConfigurations;
+ BYTE Reserved;
+}__attribute__ ((__packed__)) dwc_dev_qual_descriptor_t;
+
+
+// ±ê×¼ÅäÖÃÃèÊö·û
+typedef struct dwc_config_descriptor_t
+{
+ BYTE bLength;
+ BYTE bDescriptorType;
+ WORD16 wTotalLength;
+ BYTE bNumInterfaces;
+ BYTE bConfigurationValue;
+ BYTE iConfiguration;
+ BYTE bmAttributes;
+ BYTE bMaxPower;
+}__attribute__ ((__packed__)) dwc_config_descriptor_t;
+
+typedef struct dwc_product_descriptor_t
+{
+ BYTE bLength;
+ BYTE bDescriptorType;
+ char Prod_Desc[98];
+} __attribute__ ((__packed__)) dwc_product_descriptor_t;
+
+//#define MAX_EPS (0x8)
+#define MAX_EPS (0x2)
+typedef enum
+{
+ USB_MAX_PACKET_SIZE_NOT_SET = 0,
+ USB_FULLSPEED_BULK_MAXSIZE = 64,
+ USB_HIGHSPEED_BULK_MAXSIZE = 512,
+}T_USB_MAX_PACKET_SIZE;
+
+typedef struct dwc_config_all_t
+{
+ dwc_config_descriptor_t tConfig;
+ dwc_interface_descriptor_t tInterface;
+ dwc_ep_descriptor_t atTxEP[1]; //·¢ËͶ˵ã(²»°üÀ¨ep0)
+ dwc_ep_descriptor_t atRxEP[1]; //½ÓÊն˵ã(²»°üÀ¨ep0)
+ dwc_interface_descriptor_t tInterface1;
+ dwc_ep_descriptor_t atTxEP1[1]; //·¢ËͶ˵ã(²»°üÀ¨ep0)
+ dwc_ep_descriptor_t atRxEP1[1]; //½ÓÊն˵ã(²»°üÀ¨ep0)
+}__attribute__ ((__packed__)) dwc_config_all_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _USB_H_ */
diff --git a/boot/common/src/uboot/include/usb/usb_config.h b/boot/common/src/uboot/include/usb/usb_config.h
new file mode 100644
index 0000000..e5c1d3c
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/usb_config.h
@@ -0,0 +1,116 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ£º config.h
+* Îļþ±êʶ£º /include/config.h
+* ÄÚÈÝÕªÒª£º ÒýÈ뿪·¢°åµÄÅäÖÃÎļþ
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº ÎÌÔÆ·å
+* Íê³ÉÈÕÆÚ£º 2010-9-30
+*
+*
+*******************************************************************************/
+#ifndef __INCLUDE_USB_CONFIG_H_
+#define __INCLUDE_USB_CONFIG_H_
+/*********************************************************************************
+1:open 0:close
+* ¹¦ÄÜ SIM_EN USE_ASIC SYNC_USB_CTRL SYNC_USB_HSIC SYNC_SETADDRESS
+* FPGA 1 0 0 0 0
+* usb_ctrlÑéÖ¤ 0 1 1 1 1
+* usb_hsicÑéÖ¤ 0 1 1 1 1
+* usbtimeoutÑéÖ¤0 1 1 1 1
+* asic 1 1 0 0 0
+**********************************************************************************/
+#define SIM_EN 1
+#define USE_ASIC 1
+#define SYNC_USB_CTRL 0
+#define SYNC_USB_HSIC 0
+#define SYNC_SETADDRESS 0
+#define DMA_ENABLE 0
+#if DMA_ENABLE
+#define DWC_SLAVE_ONLY_ARCH 0
+#define DWC_EXT_DMA_ARCH 1
+#define DWC_INT_DMA_ARCH 2
+#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
+
+//#define DRV_BUF_BASE_ADDR 0x23000000
+#define DRV_BUF_BASE_ADDR 0x21000000
+#define FPGA_DDR_FOR_USB_DMA_ADDR DRV_BUF_BASE_ADDR
+#define USB_EP_BUF_ADDR FPGA_DDR_FOR_USB_DMA_ADDR
+#define USB_EP_BUF_LEN 0x500000 /* 5M byte*/
+
+#define USB_EP0_BUF_ADDR (DRV_BUF_BASE_ADDR + 0x500000)
+#define USB_EP0_BUF_LEN (0x100000-0x1000) /* 1M-4K byte*/
+#define USB_EP0_MAX_BUF_SIZE 256
+#define USB_EP_MAX_BUF_SIZE 8192
+#define USB_EP0_PKT_BUF_SIZE 5
+#endif
+
+#if !USE_ASIC ///0:fpga 1:asic
+// CPUʱÖÓƵÂÊ
+#define SYS_CPU_FREQ 50000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
+#define SYS_UART_CLK_CONFIG_PLL 25000000 // ʱÖÓƵÂÊ
+#else
+// CPUʱÖÓƵÂÊ
+#define SYS_CPU_FREQ 208000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK (26000000/6) // ʱÖÓƵÂÊ
+#define SYS_UART_CLK_CONFIG_PLL 104000000 // ʱÖÓƵÂÊ
+#endif
+// Æô¶¯Ä£Ê½Ñ¡Ôñ¼Ä´æÆ÷
+#define SYS_BOOTSEL_BASE 0x0010c03c // ¶¨ÒåBOOTSEL¼Ä´æÆ÷µØÖ·
+
+#define SOC_CRM_BASE (0x0010c000)
+#define BOOT_SEL (0x3c)
+#define NAND_CFG (0x34)
+#define SOC_MOD_CLKEN0 (0x0013b06c)
+#define SOC_MOD_CLKEN1 (0x0013b06c)
+#define SOC_MOD_RSTEN (0x0013b080)
+#define SOC_MOD_USBSTATECTRL (0x0010c05c)
+#define SOC_MOD_RSTEN1 (0x0010c064)
+
+#define CFG_STACK_TOP 0x0008AFE0 // ¶¨ÒåÁËÕ»¶¥
+
+// UART ²ÎÊý
+#define SYS_UART_BASE 0x00102000 // »ùµØÖ·
+//#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
+#define CFG_UART_BAUDRATE 115200 // ²¨ÌØÂÊ
+#define CFG_BUF_SIZE 64 // Êý¾Ý»º³åÇø´óС
+#if !USE_ASIC
+// USB ²ÎÊý
+#define SYS_USB_BASE 0x01500000 // »ùµØÖ·
+#define SYS_USB_HSIC_BASE 0x01600000 // »ùµØÖ·
+#else
+#define SYS_USB_BASE 0x01500000 // »ùµØÖ·
+#define SYS_USB_HSIC_BASE 0x01600000 // »ùµØÖ·
+#endif
+
+
+// NAND FLASH ²ÎÊý
+#define SYS_NAND_BASE 0x01207000 // ¼Ä´æÆ÷»ùµØÖ·
+#define SYS_NAND_DATA 0x01208000 // Êý¾Ý»ùµØÖ·
+
+// ͨÓòÎÊý
+#define CFG_LOAD_BASE 0x0008B000 // ¼ÓÔØ´úÂëµ½¸ÃµØÖ·,±ØÐë4K¶ÔÆë
+#define SYS_LOAD_LEN 0x1000 // ¼ÓÔس¤¶È
+#define CFG_PRINT_BUF_SIZE 256
+
+//#define POWER_DOMAIN_ISO (0x0010d200+0x41*4)
+//#define POWER_DOMAIN_POWERON (0x0010d200+0x42*4)
+//#define POWER_DOMAIN_RST (0x0010d200+0x40*4)
+
+//ÑéÖ¤ÐèÒª
+#if SYNC_USB_CTRL
+#define ARM_PORTA (0x102040)
+#endif
+
+#if SYNC_USB_HSIC
+#define REG_GPIO_OUT 0x01400014
+#define REG_GPIO_IN 0x01409020
+#endif
+#endif