[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/boot/common/src/uboot/include/usb/config.h b/boot/common/src/uboot/include/usb/config.h
new file mode 100644
index 0000000..7973739
--- /dev/null
+++ b/boot/common/src/uboot/include/usb/config.h
@@ -0,0 +1,226 @@
+
+#if 0
+
+/*******************************************************************************
+* °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ£º config.h
+* Îļþ±êʶ£º /include/config.h
+* ÄÚÈÝÕªÒª£º ÒýÈ뿪·¢°åµÄÅäÖÃÎļþ
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº ÎÌÔÆ·å
+* Íê³ÉÈÕÆÚ£º 2010-9-30
+*
+*
+
+*******************************************************************************/
+
+
+
+#ifndef __INCLUDE_CONFIG_H_
+#define __INCLUDE_CONFIG_H_
+/*********************************************************************************
+1:open 0:close
+* ¹¦ÄÜ SIM_EN USE_ASIC SYNC_USB_CTRL SYNC_USB_HSIC SYNC_SETADDRESS
+* FPGA 1 0 0 0 0
+* usb_ctrlÑéÖ¤ 0 1 1 1 1
+* usb_hsicÑéÖ¤ 0 1 1 1 1
+* usbtimeoutÑéÖ¤0 1 1 1 1
+* asic 1 1 0 0 0
+**********************************************************************************/
+#define SIM_EN 1
+#define USE_ASIC 0
+#define SYNC_USB_CTRL 0
+#define SYNC_USB_HSIC 0
+#define SYNC_SETADDRESS 0
+
+#if !USE_ASIC ///0:fpga 1:asic
+// CPUʱÖÓƵÂÊ
+#define SYS_CPU_FREQ 50000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
+#define SYS_UART_CLK_CONFIG_PLL 25000000 // ʱÖÓƵÂÊ
+#else
+// CPUʱÖÓƵÂÊ
+#define SYS_CPU_FREQ 208000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK (26000000/6) // ʱÖÓƵÂÊ
+#define SYS_UART_CLK_CONFIG_PLL 104000000 // ʱÖÓƵÂÊ
+#endif
+// Æô¶¯Ä£Ê½Ñ¡Ôñ¼Ä´æÆ÷
+#define SYS_BOOTSEL_BASE 0x0010c03c // ¶¨ÒåBOOTSEL¼Ä´æÆ÷µØÖ·
+
+#define SOC_CRM_BASE (0x0010c000)
+#define BOOT_SEL (0x3c)
+#define NAND_CFG (0x34)
+#define SOC_MOD_CLKEN0 (0x0010c00c)
+#define SOC_MOD_CLKEN1 (0x0010c010)
+#define SOC_MOD_RSTEN (0x0010c018)
+#define SOC_MOD_USBSTATECTRL (0x0010c05c)
+#define SOC_MOD_RSTEN1 (0x0010c064)
+
+#define CFG_STACK_TOP 0x0008AFE0 // ¶¨ÒåÁËÕ»¶¥
+
+// UART ²ÎÊý
+#define SYS_UART_BASE 0x00102000 // »ùµØÖ·
+//#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
+#define CFG_UART_BAUDRATE 115200 // ²¨ÌØÂÊ
+#define CFG_BUF_SIZE 64 // Êý¾Ý»º³åÇø´óС
+#if !USE_ASIC
+// USB ²ÎÊý
+#define SYS_USB_BASE 0x01240000 // »ùµØÖ·
+#define SYS_USB_HSIC_BASE 0x01280000 // »ùµØÖ·
+#else
+#define SYS_USB_BASE 0x01280000 // »ùµØÖ·
+#define SYS_USB_HSIC_BASE 0x01240000 // »ùµØÖ·
+#endif
+
+
+// NAND FLASH ²ÎÊý
+#define SYS_NAND_BASE 0x01207000 // ¼Ä´æÆ÷»ùµØÖ·
+#define SYS_NAND_DATA 0x01208000 // Êý¾Ý»ùµØÖ·
+
+// ͨÓòÎÊý
+#define CFG_LOAD_BASE 0x0008B000 // ¼ÓÔØ´úÂëµ½¸ÃµØÖ·,±ØÐë4K¶ÔÆë
+#define SYS_LOAD_LEN 0x1000 // ¼ÓÔس¤¶È
+#define CFG_PRINT_BUF_SIZE 256
+
+#define POWER_DOMAIN_ISO (0x0010d200+0x41*4)
+#define POWER_DOMAIN_POWERON (0x0010d200+0x42*4)
+#define POWER_DOMAIN_RST (0x0010d200+0x40*4)
+
+//ÑéÖ¤ÐèÒª
+#if SYNC_USB_CTRL
+#define ARM_PORTA (0x102040)
+#endif
+
+#if SYNC_USB_HSIC
+#define REG_GPIO_OUT 0x01400014
+#define REG_GPIO_IN 0x01409020
+#endif
+#define CFG_USB30_LOAD_BASE 0x62000000 //USB30 ÄÚ²¿DMAÊý¾ÝÏÂÔصØÖ·
+#endif
+#endif
+/******************************************************************************/
+/*******************************************************************************
+* °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ£º config.h
+* Îļþ±êʶ£º /include/config.h
+* ÄÚÈÝÕªÒª£º ÒýÈ뿪·¢°åµÄÅäÖÃÎļþ
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº
+* Íê³ÉÈÕÆÚ£º
+*
+*
+*******************************************************************************/
+#ifndef __INCLUDE_CONFIG_H_
+#define __INCLUDE_CONFIG_H_
+
+#define FPGA 0
+#define ASIC 1
+#define EMULATION 2
+#define ULPI 0
+#define UTMI 1
+
+/*ͨ¹ýºê¶¨ÒåÀ´Ñ¡Ôñ°æ±¾·½Ê½*/
+#define SIM_EN FPGA
+
+#define USB_PHY UTMI
+
+//IRAM0 0x62000000 IRAM2 0x80000 IRAM1 0x100000(δÓÃ)
+#define CFG_USB30_LOAD_BASE 0x62000000 //USB30 ÄÚ²¿DMAÊý¾ÝÏÂÔصØÖ·
+#define CFG_SDIO_LOAD_BASE 0x62000000 // SDIO DMA Êý¾Ý°áÔ˵ØÖ·
+#define CFG_LOAD_BASE 0x00087000 // ¼ÓÔØ´úÂëµ½¸ÃµØÖ·,±ØÐë4K¶ÔÆë
+#define SYS_LOAD_LEN 0x1000 // ¼ÓÔس¤¶È
+#define CFG_PRINT_BUF_SIZE 256
+#define CFG_STACK_TOP 0x86800
+
+#if ((SIM_EN == ASIC)||(SIM_EN == EMULATION))
+// CPUʱÖÓƵÂÊ,usb³¬Ê±»úÖƼÆʱ²ÉÓÃtick£¬Óëm0ͬƵ£¬ÇÒusb bootÐèpllʱÖÓÅäÖá£
+#define SYS_CPU_FREQ 208000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK 26000000 // ʱÖÓƵÂÊ
+#define PLL_8X(x) ((x)>>3) //pllδÅäÖÃÇ°£¬´æÔÚ8±¶µÄ¹Øϵ
+#elif (SIM_EN == FPGA)
+// CPUʱÖÓƵÂÊ
+#define SYS_CPU_FREQ 30000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
+#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
+#define PLL_8X(x) (x) //²»´æÔÚ±¶Êý²îÒì
+#endif
+
+// Æô¶¯Ä£Ê½Ñ¡Ôñ¼Ä´æÆ÷
+/*bootsel_info*/
+/*[0:3] bootsel0,bootsel1,bootsel2,bootsel3
+ [4:5] nand page size
+ [6] nand data width
+ [7] nand addr cycles*/
+/*
+#define SYS_BOOTSEL_INFO 0x0013b04c // ¶¨ÒåBOOTSEL¼Ä´æÆ÷µØÖ·
+#define SYS_STD_CRM_BASE 0x1307000
+#define SYS_LSP_CRM_BASE 0x01400000
+#define SYS_SOC_CRM_BASE 0x0013b000
+#define SYS_PAD_CTRL0_BASE 0x143000
+*/
+
+#define SOC_CRM_BASE (0x0013b000)
+#define BOOT_SEL (0x3c)
+#define NAND_CFG (0x34)
+#define SOC_MOD_CLKEN0 (0x0013b06c)
+#define SOC_MOD_CLKEN1 (0x0013b06c)
+#define SOC_MOD_RSTEN (0x0013b080)
+#define SOC_MOD_USBSTATECTRL (0x0010c05c)
+#define SOC_MOD_RSTEN1 (0x0010c064)
+
+
+
+
+
+/*UART ²ÎÊý*/
+#define SYS_UART_BASE 0x0138000 // UART0 »ùµØÖ· //
+
+#define CFG_UART_BAUDRATE 115200 // ²¨ÌØÂÊ
+#define CFG_BUF_SIZE 64 // Êý¾Ý»º³åÇø´óС
+
+/*USB BASE ADDRESS*/
+//#define SYS_USB_BASE 0x02000000 // 3.0»ùµØÖ·
+//#define SYS_USB_HSIC_BASE 0x01500000 // HSIC»ùµØÖ·
+
+#define SYS_USB_BASE 0x01500000 // 2.0»ùµØÖ·
+#define SYS_USB_HSIC_BASE 0x01600000 // HSIC»ùµØÖ·
+//ÒÔÉÏÊÇ7520V2оƬÖж¨ÒåµÄUSB»ùÖ·
+
+
+
+
+/* NAND FLASH ²ÎÊý*/
+#define SYS_NAND_BASE 0x01211000 // ¼Ä´æÆ÷»ùµØÖ·
+#define SYS_NAND_DATA 0x01212000 // Êý¾Ý»ùµØÖ·
+
+/*SPI_FLASH²ÎÊý*/
+#define SYS_SPI_FLASH_BASE 0x140c000
+
+/*SD/MMC ²ÎÊý*/
+#define SYS_EMMC_REGS_BASE 0x01210000 //SD0
+#define CFG_EMMC_CLK_REF 26000000
+#define CFG_EMMC_CLK_ENUM 400000
+#define CFG_EMMC_CLK_WORK 26000000
+
+/*SDIO SLAVE ²ÎÊý*/
+#define SYS_SDIO_REGS_BASE 0x01540000 //SD1
+
+
+#define POWER_DOMAIN_ISO (0x00140110)
+#define POWER_DOMAIN_POWERON (0x00140114)
+#define POWER_DOMAIN_RST (0x0014010c)
+
+
+//ÑéÖ¤ÐèÒª
+#if SIM_EN == EMULATION
+/*USB2.0*/
+#define ARM_PORTA (REG_GPIO_OUT)
+/*HSIC*/
+#define REG_GPIO_OUT 0x00145060 //7520
+#define REG_GPIO_IN 0x00145014
+#endif
+#endif
+