[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/cp/ps/driver/inc/cfg/drvs_cfg.h b/cp/ps/driver/inc/cfg/drvs_cfg.h
new file mode 100644
index 0000000..010e3aa
--- /dev/null
+++ b/cp/ps/driver/inc/cfg/drvs_cfg.h
@@ -0,0 +1,75 @@
+/*******************************************************************************
+ * Copyright (C) 2008, ZTE Corporation.
+ *
+ * File Name: drvs_cfg.h
+ * File Mark:
+ * Description: This file contains the
+ * Others:
+ * Version: V1.0
+ * Author: huji
+ * Date: 2008-11-18
+ * History 1:
+ * Date: 2008-12-31
+ * Version:
+ * Author: wangxia
+ * Modification: add flash address for zx2930,zx2960,zx2802
+ *********************************************************************************/
+
+#ifndef _DRV_CFG_H
+#define _DRV_CFG_H
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+/*for iram ddr*/
+#include "ram_config.h"
+/*for registers*/
+#include "drvs_chip_cfg.h"
+/*for dma regions*/
+#include "dma_cfg.h"
+#include "drvs_int.h"
+
+/****************************************************************************
+* type
+****************************************************************************/
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+//add for voice drv by xuxinqiang
+#define BASEADR_SM_INT (UINT16 *) 0xF6001000
+/****************************************************************************
+* i2S configuration
+****************************************************************************/
+#define ARM_TOP_REG_BASE 0x0010D000
+
+#define ARM_I2S_LOOP_CFG *((volatile UINT32 *)(0x00140060))
+
+#define ARM_FRAC_DIV_FREQ *((volatile UINT32 *)(0x0010D09C))
+#define ARM_CODEC_MCLK *((volatile UINT32 *)(0x0010D0a0))
+
+/*ARM I2S SEL & SET*/
+#define CRPM_CLKSEL *((volatile UINT32 *)(LSP_CRM_REG_BASE+0x00))
+#define I2S0_CLKDIV *((volatile UINT32 *)(LSP_CRM_REG_BASE+0x14))
+#define I2S1_CLKDIV *((volatile UINT32 *)(LSP_CRM_REG_BASE+0x18))
+
+
+/*xxxx config---------------------------------------------------------------*/
+#define DMA_SILLY_MODE_EN 0
+//zhouyuchao add for usb phy suspend
+#define NAND_USB_CTRL (0x00)
+
+/****************************************************************************
+* sd configuration
+****************************************************************************/
+#define SD_MAX_SLOT_NUM 1 //max slot numbers
+#if (defined _CHIP_ZX2975)||(defined _CHIP_ZX297520)||(defined _CHIP_ZX297520V2)
+#define IO_OUT_POWER_READ_REG ((volatile UINT32*)(0x60005098))
+#define IO_OUT_POWER_WRITE_REG ((volatile UINT32*)(0x60005098))
+#else
+#define IO_OUT_POWER_READ_REG ((volatile UINT32*)(0x60005068))
+#define IO_OUT_POWER_WRITE_REG ((volatile UINT32*)(0x60005098))
+#endif
+
+#endif/*_DRV_CFG_H*/
+
diff --git a/cp/ps/driver/inc/cfg/drvs_chip_cfg.h b/cp/ps/driver/inc/cfg/drvs_chip_cfg.h
new file mode 100644
index 0000000..425e621
--- /dev/null
+++ b/cp/ps/driver/inc/cfg/drvs_chip_cfg.h
@@ -0,0 +1,307 @@
+/*******************************************************************************
+ * Copyright (C) 2008, ZTE Corporation.
+ *
+ * File Name: drv_chip_cfg.h
+ * File Mark:
+ * Description: This file contains the
+ * Others:
+ * Version: V1.0
+ * Author: zhangdongdong
+ * Date: 2015-07-31
+ * History 1:
+ *
+ *********************************************************************************/
+
+#ifndef _DRV_CHIP_CFG_H
+#define _DRV_CHIP_CFG_H
+
+#include "drvs_bits.h"
+
+
+/****************************************************************************
+* type
+****************************************************************************/
+
+
+/****************************************************************************
+* MACRO
+****************************************************************************/
+
+#define TOP_MAIN_CLK_IN 26000000 /* 26MHz */
+
+/****************************************************************************
+* register map
+****************************************************************************/
+#ifdef _OS_TOS
+
+#include "drvs_regmap.inc"
+
+/*SYS*/
+#define TOP_SYS_REG_BASE ADDR_SOC_SYS
+#define SOC_SYS_REG_BASE ADDR_SOC_SYS
+#define A1_SYS_REG_BASE ADDR_SOC_SYS
+
+/*CRM*/
+#define SOC_CRM_REG_BASE ADDR_STD_CRM
+#define LSP_CRM_REG_BASE ADDR_LSP_CRM
+#define A1_CRM_REG_BASE ADDR_TOP_CRM
+#define PS_CRM_REG_BASE ADDR_MG_CRM
+
+/*PS*/
+#define PS_CFG_REG_BASE ADDR_MG_CFG
+
+#if defined (_CHIP_ZX297520V2)
+/*L2 CACHE*/
+#define L2CACHE_REG_BASE ADDR_MG_L2CACHE
+#endif
+
+/*PCU*/
+#define PCU_REG_BASE ADDR_PCU
+
+/*SCU*/
+#if defined (_CHIP_ZX297520V2)
+#define SCU_REG_BASE ADDR_MG_SCU /*only in 7520v2*/
+#endif
+
+/*GIC*/
+#define GICC_REG_BASE ADDR_MG_GICC
+#define GICD_REG_BASE ADDR_MG_GICD
+#if defined (_CHIP_ZX297520V3)
+#define GICR_REG_BASE ADDR_MG_GICR
+#endif
+
+/*TIMER*/
+#define TIMER0_REG_BASE ADDR_LSP_PS_TIMER0 /*ps tick*/
+#define TIMER1_REG_BASE ADDR_PS_TIMER1 /*psm wake timer*/
+#define TIMER2_REG_BASE ADDR_PS_TIMER2
+#define PSRM_TIMER_REG_BASE ADDR_LSP_PS_RM_TIMER /*uicc timer*/
+#define TIMER3_REG_BASE ADDR_RM_TIMER1 /*psm compensate timer*/
+
+/*WDT*/
+#define EXT_WDT_BASE ADDR_LSP_PS_WDT
+//#define PT_WDT_BASE ADDR_MG_PT_WDT
+
+/*I2C*/
+//#define I2C0_REG_BASE ADDR_APB_I2C0 /*V2¾«¼òµôÁËÒ»¸öI2C*/
+#define I2C1_REG_BASE ADDR_LSP_I2C1
+#define I2C_PMIC_REG_BASE ADDR_I2C_PMIC
+
+/*USB*/
+#define USB0_REG_BASE ADDR_HSIC
+#define USB1_REG_BASE ADDR_USB
+
+/*NAND*/
+#define NAND_REG_BASE ADDR_NAND_REG
+#define NAND_DATA_BASE ADDR_NAND_DATA
+
+/*DMA*/
+#define DMA0_REG_BASE ADDR_DMA_PS
+#define DMA1_REG_BASE ADDR_DMA_PHY
+
+/*SPI*/
+#define SPI0_REG_BASE ADDR_LSP_SSP0
+#define SPI1_REG_BASE ADDR_LSP_SSP1
+
+/*ICP*/
+#define ICP0_REG_BASE ADDR_ICP
+
+/*I2S*/
+#define I2S0_REG_BASE ADDR_LSP_I2S0
+#define I2S1_REG_BASE ADDR_LSP_I2S1
+
+/*SDMMC*/
+#define SDMMC0_REG_BASE ADDR_SD0
+#define SDMMC1_REG_BASE ADDR_SD1
+
+/*USIM*/
+#define USIM0_REG_BASE ADDR_GSM_USIM /*´ýÈ·ÈÏ£¬V2¾«¼òµôÁËÒ»¸öUSIM*/
+
+/*EDCP*/
+#define EDCP0_REG_BASE ADDR_EDCP
+
+/*CHECKSUM*/
+#define CHECKSUM0_REG_BASE 0
+
+/*UART*/
+#define UART0_REG_BASE ADDR_UART0
+#define UART1_REG_BASE ADDR_LSP_UART1
+#define UART2_REG_BASE ADDR_LSP_UART2
+
+/*PAD*/
+#define PAD_CTRL_REG_BASE ADDR_PAD_CTRL_A0
+
+/*GPIO*/
+#define GPIO0_REG_BASE ADDR_GPIO0
+#define GPIO1_REG_BASE ADDR_GPIO1
+
+/*PIN MUX*/
+#define GPIO_PINMUX_REG_BASE ADDR_PIN_MUX
+
+/*GSM_MODEM1*/
+#define GSM_MODEM1 ADDR_GSM_MODEM1
+
+/*GSM_MODEM2*/
+#define GSM_MODEM2 ADDR_GSM_MODEM2
+
+/*DDR*/
+#define DDR_CTRL_BASE ADDR_DDR_CTRL
+#define DDR_PHY_BASE ADDR_DDR_PHY
+#if defined (_CHIP_ZX297520V3)
+#define DDR_FFC_BASE ADDR_DDR_FFC
+#endif
+
+/*IRAM*/
+#define IRAM1_BASE ADDR_IRAM1 /*Ê¡µç½»»¥£¬²»µôµçIRAM*/
+#define IRAM2_BASE ADDR_IRAM2 /*ÔËÐÐM0Èí¼þ´úÂë*/
+
+/*LPM*/
+#define GSM_LPM_BASE ADDR_LPM_GSM
+#define LTE_LPM_BASE ADDR_LPM_LTE
+#define TD_LPM_BASE ADDR_LPM_TD
+#define W_LPM_BASE ADDR_LPM_W
+
+/*EFUSE*/
+#define EFUSE_BASE_ADDR ADDR_EFUSE
+
+#if defined (_CHIP_ZX297520V3)
+/*VOU*/
+#define VOU_CTRL_BASE ADDR_VOU_CFG
+#define VOU_CLK_CTRL_BASE ADDR_STD_CRM
+#endif
+#endif
+
+#ifdef _OS_LINUX
+#include <mach/iomap.h>
+
+/*SYS*/
+#define TOP_SYS_REG_BASE ((unsigned int)ZX_SOC_SYS_BASE)
+#define SOC_SYS_REG_BASE ((unsigned int)ZX_SOC_SYS_BASE)
+#define A1_SYS_REG_BASE ((unsigned int)ZX_SOC_SYS_BASE)
+
+/*CRM*/
+#define SOC_CRM_REG_BASE ((unsigned int)ZX_MATRIX_CRM_BASE)
+#define LSP_CRM_REG_BASE ((unsigned int)ZX_LSP_CRPM_BASE)
+#define A1_CRM_REG_BASE ((unsigned int)ZX_TOP_CRM_BASE)
+#define PS_CRM_REG_BASE ((unsigned int)ZX_AP_PERIPHERAL_BASE)
+
+/*PS*/
+//#define PS_CFG_REG_BASE ZX297520V3_MG_CFG
+
+/*L2 CACHE*/
+//#define L2CACHE_REG_BASE ZX297520V3_MG_L2CACHE
+
+/*PCU*/
+#define PCU_REG_BASE ((unsigned int)ZX_PCU_BASE)
+
+/*GIC*/
+#define GICC_REG_BASE ((unsigned int)ZX_GICC_BASE)
+#define GICD_REG_BASE ((unsigned int)ZX_GIC_BASE)
+#define GICR_REG_BASE ((unsigned int)GIC_REDIST_BASE)
+
+
+/*TIMER*/
+#define TIMER0_REG_BASE ((unsigned int)ZX_PS_TIMER0_BASE) /*ps tick*/
+#define TIMER1_REG_BASE ((unsigned int)ZX_PS_TIMER1_BASE) /*psm wake timer*/
+#define TIMER2_REG_BASE ((unsigned int)ZX_PS_TIMER2_BASE) /*psm compensate timer*/
+#define PSRM_TIMER_REG_BASE ((unsigned int)ZX_PS_RM_TIMER_BASE) /*uicc timer*/
+#define TIMER3_REG_BASE ((unsigned int)ZX_RM_TIMER1_BASE) /*rm timer1*/
+
+/*WDT*/
+#define EXT_WDT_BASE ((unsigned int)ZX_PS_WDT_BASE)
+//#define PT_WDT_BASE ZX297520V3_MG_PT_WDT
+
+/*I2C*/
+//#define I2C0_REG_BASE ZX297520V3_APB_I2C0 /*V2¾«¼òµôÁËÒ»¸öI2C*/
+#define I2C1_REG_BASE ((unsigned int)ZX_I2C1_BASE)
+#define I2C_PMIC_REG_BASE ((unsigned int)ZX_PMIC_I2C_BASE)
+
+/*USB*/
+#define USB0_REG_BASE ((unsigned int)ZX_HSIC_BASE)
+#define USB1_REG_BASE ((unsigned int)ZX_USB_BASE)
+
+/*NAND*/
+#define NAND_REG_BASE ((unsigned int)ZX_NAND_REG_BASE)
+#define NAND_DATA_BASE ((unsigned int)ZX_NAND_DATA_BASE)
+
+/*DMA*/
+#define DMA0_REG_BASE ((unsigned int)ZX_DMA_PS_BASE)
+#define DMA1_REG_BASE ((unsigned int)ZX_DMA_PHY_BASE)
+
+/*SPI*/
+#define SPI0_REG_BASE ((unsigned int)ZX_SSP0_BASE)
+#define SPI1_REG_BASE ((unsigned int)ZX_SSP1_BASE)
+
+/*ICP*/
+#define ICP0_REG_BASE ((unsigned int)ZX_ICP_BASE)
+
+/*I2S*/
+#define I2S0_REG_BASE ((unsigned int)ZX_I2S0_BASE)
+#define I2S1_REG_BASE ((unsigned int)ZX_I2S1_BASE)
+
+/*TDM*/
+#define TDM_REG_BASE ((unsigned int)ZX_TDM_BASE)
+
+/*SDMMC*/
+#define SDMMC0_REG_BASE ((unsigned int)ZX_SD0_BASE)
+#define SDMMC1_REG_BASE ((unsigned int)ZX_SD1_BASE)
+
+/*USIM*/
+//#define USIM0_REG_BASE ZX297520V3_GSM_USIM /*´ýÈ·ÈÏ£¬V2¾«¼òµôÁËÒ»¸öUSIM*/
+#define USIM1_REG_BASE ((unsigned int)ZX_USIM1_BASE)
+
+/*EDCP*/
+#define EDCP0_REG_BASE ((unsigned int)ZX_EDCP_BASE)
+
+/*CHECKSUM*/
+#define CHECKSUM0_REG_BASE 0
+
+/*UART*/
+#define UART0_REG_BASE ((unsigned int)ZX_UART0_BASE)
+#define UART1_REG_BASE ((unsigned int)ZX_UART1_BASE)
+#define UART2_REG_BASE ((unsigned int)ZX_UART2_BASE)
+
+/*PAD*/
+#define PAD_CTRL_REG_BASE ((unsigned int)ZX_PAD_CTRL_BASE)
+
+/*GPIO*/
+#define GPIO0_REG_BASE ((unsigned int)ZX_GPIO0_BASE)
+#define GPIO1_REG_BASE ((unsigned int)ZX_GPIO1_BASE)
+
+/*PIN MUX*/
+#define GPIO_PINMUX_REG_BASE ((unsigned int)ZX_PIN_MUX_BASE)
+
+/*GSM_CFG*/
+#define GSM_CFG_BASE ((unsigned int)ZX_GSM_CFG_BASE)
+
+/*GSM_MODEM1*/
+#define GSM_MODEM1 ((unsigned int)ZX_GSM_MODEM_BASE)
+
+/*GSM_MODEM2*/
+#define GSM_MODEM2 ((unsigned int)(ZX_GSM_MODEM_BASE+0x2000000))
+
+/*DDR*/
+#define DDR_CTRL_BASE ((unsigned int)ZX_DDR_CTRL_BASE)
+#define DDR_PHY_BASE ((unsigned int)ZX_DDR_PHY_BASE)
+#define DDR_FFC_BASE ((unsigned int)ZX_DDR_FFC_BASE)
+/**/
+#define SYS_CTRL_BASE ((unsigned int)ZX_SOC_SYS_BASE)
+
+/*IRAM*/
+#define IRAM1_BASE ((unsigned int)ZX_IRAM1_BASE) /*Ê¡µç½»»¥£¬²»µôµçIRAM*/
+#define IRAM2_BASE_ADDR ((unsigned int)ZX_IRAM2_BASE) /*ÔËÐÐM0Èí¼þ´úÂë*/
+
+/*LPM*/
+#define GSM_LPM_BASE ((unsigned int)ZX_LPM_GSM_BASE)
+#define LTE_LPM_BASE ((unsigned int)ZX_LPM_LTE_BASE)
+#define TD_LPM_BASE ((unsigned int)ZX_LPM_TD_BASE)
+#define W_LPM_BASE ((unsigned int)ZX_LPM_W_BASE)
+
+/*EFUSE*/
+#define EFUSE_BASE_ADDR ((unsigned int)ZX_EFUSE_BASE)
+/*VOU*/
+#define VOU_CTRL_BASE ((unsigned int)ZX_VOU_CFG_BASE)
+#define VOU_CLK_CTRL_BASE ((unsigned int)ZX_MATRIX_CRM_BASE)
+#endif
+
+#endif/*_DRV_CFG_H*/
+
diff --git a/cp/ps/driver/inc/cfg/drvs_debug.h b/cp/ps/driver/inc/cfg/drvs_debug.h
new file mode 100644
index 0000000..93f5cda
--- /dev/null
+++ b/cp/ps/driver/inc/cfg/drvs_debug.h
@@ -0,0 +1,77 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: 1.0
+ * Author: geanfeng
+ * Date: 2013-09-25
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_DEBUG_H_
+#define _DRVS_DEBUG_H_
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "drvs_general.h"
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+/****************************************************************************
+* Types
+****************************************************************************/
+typedef enum _T_DRV_DEBUG_PRINT_CHANNEL
+{
+ DRV_DEBUG_PRINT_ZOSS,
+ DRV_DEBUG_PRINT_DCC
+}T_DRV_DEBUG_PRINT_CHANNEL;
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+extern volatile T_DRV_DEBUG_PRINT_CHANNEL g_debugPrintChnSel;
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+SINT32 debug_Print(const VOID *pFormat, ... );
+/*******************************************************************************
+* Function:zDrvDebug_Printf
+* Description: log´òÓ¡
+* Parameters:
+* pFormat:¸ñʽ»¯×Ö·û´®
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+#define zDrvDebug_Printf(s...) \
+{ \
+ if (g_debugPrintChnSel == DRV_DEBUG_PRINT_ZOSS)\
+ {\
+ zOss_Printf(SUBMDL_HAL, PRINT_LEVEL_NORMAL, s);\
+ }\
+ else \
+ {\
+ debug_Print(s);\
+ }\
+}
+
+#endif/*_DRVS_IO_H_*/
+
diff --git a/cp/ps/driver/inc/cfg/drvs_int_internal.h b/cp/ps/driver/inc/cfg/drvs_int_internal.h
new file mode 100644
index 0000000..bcc9e14
--- /dev/null
+++ b/cp/ps/driver/inc/cfg/drvs_int_internal.h
@@ -0,0 +1,143 @@
+/*******************************************************************************
+ * Copyright (C) 2014, ZTE Corporation.
+ *
+ * File Name: hal_int_internal.h
+ * File Mark:
+ * Description: describe functions and related macros and types used by
+ * other driver modules
+ * Others:
+ * Version: 1.0
+ * Author: xuzhiguo
+ * Date: 2014-05-05
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_INT_INTERNAL_H
+#define _DRVS_INT_INTERNAL_H
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "drvs_general.h"
+#include "drvs_int.h"
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+/****************************************************************************
+* Types
+****************************************************************************/
+typedef enum _T_Int_State
+{
+ INT_UNINSTALL,
+ INT_PENDING,
+ INT_ACTIVE,
+} T_Int_State;
+
+/*
+* this struct presents the operation method
+* and state of interrupt controller chip
+*/
+typedef struct _T_Int_Chip
+{
+ VOID (*pMaskIrq)( UINT32 line );
+ VOID (*pUnmaskIrq)( UINT32 line );
+ VOID (*pSetLineLevel)(UINT32 line, T_zDrvIntLineLevel level);
+ VOID (*pSetLinePri)(UINT32 line, UINT32 pri);
+} T_Int_Chip;
+
+typedef VOID (*IsrFunc)(VOID);
+
+/**************************************************************************
+ * Global Variable
+ **************************************************************************/
+
+/**************************************************************************
+ * Function Prototypes
+ **************************************************************************/
+ /*******************************************************************************
+ * Function: zDrvInt_SetMaskRam
+ * Description: an inline function to set g_IntDev.MaskRegInRam
+ * Parameters:
+ * Input:
+ * index: which member in array MaskRegInRam
+ * value: be writen
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvInt_SetMaskRam(UINT32 index, UINT32 value);
+
+/*******************************************************************************
+ * Function: zDrvInt_GetMaskRam
+ * Description: an inline function to get g_IntDev.MaskRegInRam
+ * Parameters:
+ * Input:
+ * index: which member in array MaskRegInRam
+ *
+ * Output:
+ *
+ * Returns:
+ * member's value in array MaskRegInRam
+ *
+ * Others:
+ ********************************************************************************/
+ UINT32 zDrvInt_GetMaskRam(UINT32 index);
+
+/*******************************************************************************
+ * Function: zDrvInt_GetExtraIsr
+ * Description: get a isr according to ex8in1 int and gpio int
+ * Parameters:
+ * Input:
+ * line: interrupt line
+ *
+ * Output:
+ *
+ * Returns:
+ * isr for ex8in1 int and gpio int
+ * Others:
+ ********************************************************************************/
+ VOID* zDrvInt_GetExtraIsr(UINT32 line);
+
+/*******************************************************************************
+ * Function: zDrvInt_GetIntState
+ * Description: an inline function to get g_IntDev.IntState
+ * Parameters:
+ * Input:
+ * line: interrupt line to be disabled 0--INT_LINES_NUM
+ *
+ * Output:
+ *
+ * Returns:
+ * member's value in array IntState
+ *
+ * Others:
+ ********************************************************************************/
+ T_Int_State zDrvInt_GetIntState(UINT32 line);
+
+/*******************************************************************************
+ * Function: zDrvInt_SetChipHandler
+ * Description:
+ * Parameters:
+ * Input:
+ * line: which member in array IntChipHandler, according to interrupt line
+ * pChip: point to struct T_Int_Chip to be set
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvInt_SetChipHandler(UINT32 line, T_Int_Chip *pChip);
+
+ #endif
diff --git a/cp/ps/driver/inc/cfg/drvs_zx297510_regmap.inc b/cp/ps/driver/inc/cfg/drvs_zx297510_regmap.inc
new file mode 100644
index 0000000..849d18e
--- /dev/null
+++ b/cp/ps/driver/inc/cfg/drvs_zx297510_regmap.inc
@@ -0,0 +1,80 @@
+/*******************************************************************************
+ * Copyright (C) 2013, ZTE Corporation.
+ *
+ * File Name: drvs_zx297510_regmap.inc
+ * File Mark:
+ * Description: This file contains the register map of zx297510.
+ * Others:
+ * Version: V1.0
+ * Author: geanfeng
+ * Date: 2013-04-07
+ * History 1:
+ *
+ *********************************************************************************/
+#ifndef _DRVS_ZX297510_REGMAP_H
+#define _DRVS_ZX297510_REGMAP_H
+
+#define ZX297510_A1_SYS 0x00100000
+#define ZX297510_A1_CRM 0x00101000
+#define ZX297510_A1_UART0 0x00102000
+#define ZX297510_A1_UART1 0x00103000
+#define ZX297510_A1_SPI0 0x00104000
+#define ZX297510_A1_I2C0 0x00106000
+#define ZX297510_A1_TIMER0 0x00108000
+#define ZX297510_A1_TIMER1 0x00109000
+#define ZX297510_A1_RTC 0x0010B000
+
+#define ZX297510_SOC_CRM 0x0010C000
+#define ZX297510_TOP_SYS 0x0010D000
+#define ZX297510_APB_TIMER 0x00123000
+#define ZX297510_APB_WATCHDOG 0x00124000
+
+#define ZX297510_MG_ICU 0x00800000
+#define ZX297510_MG_TIMER 0x00801000
+#define ZX297510_MG_WATCHDOG 0x00802000
+#define ZX297510_MG_CRPM 0x00803000
+#define ZX297510_MG_INST_AS_CFG 0x00810000
+#define ZX297510_MG_DATA_AS_CFG 0x00811000
+#define ZX297510_MG_L2CACHE 0x00C00000
+
+#define ZX297510_DDR_CFG 0x01203000
+#define ZX297510_NAND_REG 0x01207000
+#define ZX297510_NAND_DATA 0x01208000
+#define ZX297510_EDCP 0x01210000
+#define ZX297510_CHECKSUM 0x01220000
+#define ZX297510_USB0_CFG 0x01240000
+#define ZX297510_USB1_CFG 0x01280000
+#define ZX297510_A2_DMA_INT_MUX 0x01300000
+#define ZX297510_DMA0_CFG 0x01301000
+#define ZX297510_DMA1_CFG 0x01302000
+#define ZX297510_SOC_SYS 0x01303000
+#define ZX297510_USIM 0x01304000
+#define ZX297510_SSC 0x01305000
+#define ZX297510_MG_LSP_CRPM 0x01400000
+#define ZX297510_MG_LSP_I2S0 0x01406000
+#define ZX297510_MG_LSP_I2S1 0x01407000
+#define ZX297510_MG_LSP_SDMMC0 0x01408000
+#define ZX297510_MG_LSP_I2C0 0x01409000
+#define ZX297510_MG_LSP_BLG 0x0140C000
+#define ZX297510_MG_LSP_TIMER0 0x0140E000
+#define ZX297510_MG_LSP_TIMER1 0x0140F000
+#define ZX297510_MG_LSP_SDMMC1 0x01415000
+#define ZX297510_IRAM1_IRAM3 0x10000000
+#define ZX297510_NIC301_GPV 0x10400000
+
+#define ZX297510_DDR_BASE 0x20000000
+
+#define ZX297510_ICP0 0x60000000
+#define ZX297510_ICP1 0x60001000
+#define ZX297510_ZSP_CFG 0x70000000
+
+#define ZX297510_IRAM0_IRAM2 0x90000000
+#define ZX297510_IRAM6 0x90020000
+#define ZX297510_TD_MODEM2 0xA0000000
+#define ZX297510_LTE_MODEM2 0xA0800000
+#define ZX297510_LTE_MODEM1 0xF0000000
+#define ZX297510_TD_MODEM1 0xF2000000
+#define ZX297510_GSM_MODEM1 0xF4000000
+#define ZX297510_GSM_MODEM2 0xF6000000
+
+#endif
diff --git a/cp/ps/driver/inc/cfg/drvs_zx297520_regmap.inc b/cp/ps/driver/inc/cfg/drvs_zx297520_regmap.inc
new file mode 100644
index 0000000..e710b26
--- /dev/null
+++ b/cp/ps/driver/inc/cfg/drvs_zx297520_regmap.inc
@@ -0,0 +1,107 @@
+/*******************************************************************************
+ * Copyright (C) 2014, ZTE Corporation.
+ *
+ * File Name: drvs_zx297520_regmap.inc
+ * File Mark:
+ * Description: This file contains the register map of zx297520.
+ * Others:
+ * Version: V1.0
+ * Author: xuzhiguo
+ * Date: 2014-01-06
+ * History 1:
+ *
+ *********************************************************************************/
+#ifndef _DRVS_ZX297520_REGMAP_H
+#define _DRVS_ZX297520_REGMAP_H
+
+/* AHB0 -- A1 */
+#define ZX297520_A1_SPI0 0x00130000
+#define ZX297520_A1_I2C_PMIC 0x00131000
+#define ZX297520_A1_TIMER0 0x00132000
+#define ZX297520_A1_TIMER1 0x00133000
+#define ZX297520_A1_TIMER2 0x00134000
+#define ZX297520_A1_TIMER3 0x00135000
+#define ZX297520_A1_TIMER4 0x00136000
+#define ZX297520_A1_TIMER5 0x00137000
+#define ZX297520_A1_UART0 0x00138000
+#define ZX297520_A1_RTC 0x00139000
+#define ZX297520_A1_WDT 0x0013A000
+#define ZX297520_A1_CRM 0x0013B000
+#define ZX297520_A1_PCU 0x0013C000
+#define ZX297520_A1_KEY 0x0013D000
+#define ZX297520_A1_GSM_CFG 0x0013E000
+#define ZX297520_A1_LPM 0x0013F000
+#define ZX297520_A1_PAD_CTRL0 0x00143000
+#define ZX297520_A1_GPIO0 0x00144000
+#define ZX297520_A1_GPIO1 0x00145000
+#define ZX297520_A1_SOC_SYS 0x00146000
+#define ZX297520_A1_TS_CTRL 0x00148000
+#define ZX297520_A1_USIM 0x00149000
+
+/* AHB0 */
+#define ZX297520_EDCP 0x01200000
+#define ZX297520_SD0 0x01210000
+#define ZX297520_NAND_REG 0x01211000
+#define ZX297520_NAND_DATA 0x01212000
+
+/* R7 MG */
+#define ZX297520_MG_CRM 0x00800000
+#define ZX297520_MG_CFG 0x00801000
+#define ZX297520_MG_AACFG 0x00802000
+#define ZX297520_MG_L2APB 0x00803000
+#define ZX297520_MG_L2CACHE 0x00804000
+
+#define ZX297520_MG_SCU 0xEF000000
+#define ZX297520_MG_GICC 0xEF000100
+#define ZX297520_MG_GICD 0xEF001000
+#define ZX297520_MG_GT 0xEF000200
+#define ZX297520_MG_PT_WDT 0xEF000600
+
+/* APB */
+#define ZX297520_DMA0_CFG 0x01300000
+#define ZX297520_DMA1_CFG 0x01301000
+#define ZX297520_ICP 0x01302000
+#define ZX297520_DDR_CRTL 0x01303000
+#define ZX297520_DDR_PHY 0x01304000
+#define ZX297520_SSC 0x01305000
+#define ZX297520_STD_CRM 0x01307000
+
+#define ZX297520_APB_CRM 0x01400000
+#define ZX297520_APB_UART0 0x01401000
+#define ZX297520_APB_UART1 0x01402000
+#define ZX297520_APB_I2S0 0x01403000
+#define ZX297520_APB_I2S1 0x01404000
+#define ZX297520_APB_I2C0 0x01405000
+#define ZX297520_APB_I2C1 0x01406000
+#define ZX297520_APB_SSP1 0x01407000
+#define ZX297520_APB_TIMER6 0x01408000
+#define ZX297520_APB_TIMER7 0x01409000
+#define ZX297520_MCU_LCD 0x0140A000
+#define ZX297520_APB_BLG 0x0140B000
+#define ZX297520_APB_SPIFC 0x0140C000
+
+/* AHB1 */
+#define ZX297520_USBHSIC 0x01500000
+#define ZX297520_SD1 0x01540000
+
+/* AXI */
+#define ZX297520_USB 0x02000000
+
+#define ZX297520_NIC400_CFG 0x10400000
+
+/* AXI */
+#define ZX297520_DDR_BASE 0x20000000
+
+/* MODEM */
+#define ZX297520_TD_MODEM_D 0xA0000000
+#define ZX297520_LTE_MODEM_D 0xA2000000
+#define ZX297520_WD_MODEM_D 0xA4000000
+
+#define ZX297520_TD_MODEM_C 0xC0000000
+#define ZX297520_LTE_MODEM_C 0xC2000000
+#define ZX297520_WD_MODEM_C 0xC4000000
+
+#define ZX297520_GSM_MODEM1 0xF4000000
+#define ZX297520_GSM_MODEM2 0xF6000000
+
+#endif
diff --git a/cp/ps/driver/inc/cfg/drvs_zx297520v2_regmap.inc b/cp/ps/driver/inc/cfg/drvs_zx297520v2_regmap.inc
new file mode 100644
index 0000000..8b61176
--- /dev/null
+++ b/cp/ps/driver/inc/cfg/drvs_zx297520v2_regmap.inc
@@ -0,0 +1,121 @@
+/*******************************************************************************
+ * Copyright (C) 2014, ZTE Corporation.
+ *
+ * File Name: drvs_zx297520_regmap.inc
+ * File Mark:
+ * Description: This file contains the register map of zx297520V2.
+ * Others:
+ * Version: V1.0
+ * Author: zhangdongdong
+ * Date: 2015-07-31
+ * History 1:
+ *
+ *********************************************************************************/
+#ifndef _DRVS_ZX297520V2_REGMAP_H
+#define _DRVS_ZX297520V2_REGMAP_H
+
+/* M0 -- A1 CFG */
+#define ZX297520V2_A1_IROM 0x00000000
+#define ZX297520V2_A1_IRAM2 0x00080000
+#define ZX297520V2_A1_IRAM1 0x00100000
+#define ZX297520V2_A1_KEY 0x00130000
+#define ZX297520V2_A1_UART0 0x00131000
+#define ZX297520V2_A1_I2C_PMIC 0x00132000
+#define ZX297520V2_A1_RTC 0x00133000
+#define ZX297520V2_A1_LPM_GSM 0x00134000
+#define ZX297520V2_A1_LPM_LTE 0x00134200
+#define ZX297520V2_A1_LPM_TD 0x00134400
+#define ZX297520V2_A1_LPM_W 0x00134600
+#define ZX297520V2_A1_PS_TIMER1 0x00138000
+#define ZX297520V2_A1_PS_TIMER2 0x00139000
+#define ZX297520V2_A1_PCU 0x0013A000
+#define ZX297520V2_A1_CRM 0x0013B000
+#define ZX297520V2_A1_PAD_CTRL0 0x0013C000
+#define ZX297520V2_A1_GPIO0 0x0013D000
+#define ZX297520V2_A1_GPIO1 0x0013E000
+#define ZX297520V2_A1_GSM_CFG 0x0013F000
+#define ZX297520V2_A1_SOC_SYS 0x00140000
+#define ZX297520V2_A1_RM_TIMER0 0x00142000
+#define ZX297520V2_A1_AP_TIMER1 0x00143000
+#define ZX297520V2_A1_AP_TIMER2 0x00144000
+#define ZX297520V2_A1_RM_TIMER1 0x00145000
+#define ZX297520V2_A1_AP_TIMER3 0x00146000
+#define ZX297520V2_A1_PHY_TIMER1 0x00147000
+#define ZX297520V2_A1_RM_WDT 0x00148000
+#define ZX297520V2_A1_RM2MATRIX 0x00200000
+
+#define ZX297520V2_NIC400_CFG 0x10400000
+
+/* M1 -- AHB CFG0 */
+#define ZX297520V2_EDCP 0x01200000
+#define ZX297520V2_SD0 0x01210000
+#define ZX297520V2_SD1 0x01211000
+#define ZX297520V2_NAND_REG 0x01214000
+#define ZX297520V2_NAND_DATA 0x01215000
+#define ZX297520V2_DDR_CTRL 0x01216000
+#define ZX297520V2_DDR_PHY 0x0121A000
+#define ZX297520V2_EFUSE 0x0121B000
+#define ZX297520V2_USB 0x01500000
+#define ZX297520V2_HSIC 0x01600000
+
+/* M1 -- APB CFG */
+#define ZX297520V2_DMA_PHY_CFG 0x01300000
+#define ZX297520V2_DMA_PS_CFG 0x01301000
+#define ZX297520V2_ICP 0x01302000
+#define ZX297520V2_PIN_MUX 0x01303000
+#define ZX297520V2_SSC 0x01304000
+#define ZX297520V2_STD_CRM 0x01306000
+#define ZX297520V2_GMAC 0x01307000
+
+/* M1 -- LSP */
+#define ZX297520V2_LSP_CRM 0x01400000
+#define ZX297520V2_LSP_PS_TIMER0 0x01401000
+#define ZX297520V2_LSP_PHY_WDT 0x01402000
+#define ZX297520V2_LSP_PS_WDT 0x01403000
+#define ZX297520V2_LSP_RM_WDT 0x01404000
+#define ZX297520V2_LSP_I2S0 0x01405000
+#define ZX297520V2_LSP_I2S1 0x01406000
+#define ZX297520V2_LSP_SPIFC0 0x01407000
+#define ZX297520V2_LSP_UART1 0x01408000
+#define ZX297520V2_LSP_I2C1 0x01409000
+#define ZX297520V2_LSP_SSP0 0x0140A000
+#define ZX297520V2_LSP_PS_RM_TIMER 0x0140B000
+#define ZX297520V2_LSP_PHY_TIMER0 0x0140C000
+#define ZX297520V2_LSP_UART2 0x0140D000
+#define ZX297520V2_LSP_AP_WDT 0x0140E000
+#define ZX297520V2_LSP_AP_TIMER0 0x0140F000
+#define ZX297520V2_LSP_SSP1 0x01410000
+#define ZX297520V2_LSP_AP_TIMER4 0x01411000
+#define ZX297520V2_LSP_TDM 0x01412000
+
+/* PS MG */
+
+#define ZX297520V2_MG_CRM 0x00800000
+#define ZX297520V2_MG_CFG 0x00801000
+#define ZX297520V2_MG_AACFG 0x00802000
+#define ZX297520V2_MG_L2APB 0x00803000
+#define ZX297520V2_MG_L2CACHE 0x00804000
+
+#define ZX297520V2_MG_SCU 0xEF000000
+#define ZX297520V2_MG_GICC 0xEF000100
+#define ZX297520V2_MG_GICD 0xEF001000
+#define ZX297520V2_MG_GT 0xEF000200
+#define ZX297520V2_MG_PT_WDT 0xEF000600
+
+/* M0 -- DDR */
+#define ZX297520V2_DDR_BASE 0x20000000
+
+/* MODEM */
+#define ZX297520V2_TD_MODEM_D 0xA0000000
+#define ZX297520V2_LTE_MODEM_D 0xA2000000
+#define ZX297520V2_WD_MODEM_D 0xA4000000
+
+#define ZX297520V2_TD_MODEM_C 0xC0000000
+#define ZX297520V2_LTE_MODEM_C 0xC2000000
+#define ZX297520V2_WD_MODEM_C 0xC4000000
+
+#define ZX297520V2_GSM_MODEM1 0xF4000000
+#define ZX297520V2_GSM_MODEM2 0xF6000000
+#define ZX297520V2_GSM_USIM 0xF6100000
+
+#endif