[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/cp/ps/driver/inc/misc/NvParam_tsc.h b/cp/ps/driver/inc/misc/NvParam_tsc.h
new file mode 100644
index 0000000..93a0197
--- /dev/null
+++ b/cp/ps/driver/inc/misc/NvParam_tsc.h
@@ -0,0 +1,79 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: nvparam_tsc.h
+* File Mark:
+* Description:
+* Others:
+* Version:
+* Author:
+* Date:
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+* History 2:
+**********************************************************************/
+
+#ifndef NVPARAM_TSC_H
+#define NVPARAM_TSC_H
+
+/**************************************************************************
+ * Include files *
+ **************************************************************************/
+#include "RWNvConfig.h"
+/**************************************************************************
+ * Macro *
+ **************************************************************************/
+/****************************************************************************
+* Types
+****************************************************************************/
+
+/******************************************************
+* TSC NV
+******************************************************/
+#define PROBE_MAX_NUM (6)
+
+typedef struct
+{
+ UINT8 THROSHOLD_0; /*fail_th0*/
+ UINT8 THROSHOLD_1; /*rise_t0*/
+ UINT8 THROSHOLD_2; /*fail_t1*/
+ UINT8 THROSHOLD_3; /*rise_t1*/
+ UINT8 THROSHOLD_4; /*fail_t2*/
+ UINT8 THROSHOLD_5; /*rise_t2*/
+ UINT8 THROSHOLD_6; /*fail_t3*/
+ UINT8 THROSHOLD_7; /*rise_t3*/
+ UINT8 THROSHOLD_8; /*fail_t4*/
+ UINT8 THROSHOLD_9; /*rise_t4*/
+ UINT8 THROSHOLD_10; /*rise_t5*/
+ }
+T_SYS_NV_TSC_THRESHOLD;
+
+typedef struct
+{
+ T_SYS_NV_TSC_THRESHOLD Threshods[PROBE_MAX_NUM]; /*ÓëÔÚdrvs_tscÖж¨ÒåµÄPROBE_MAX±£³ÖÒ»ÖÂ*/
+ UINT8 reserved1[22];
+ UINT8 DetectEn; /*οØ×Ü¿ª¹Ø£¬0xB2±íʾοشò¿ª,ÆäËûÖµ²»¿ª*/
+ UINT8 Wifi_TxBackOff_En; /*ÏÞÖÆWIFI×î´ó¹¦ÂÊ¿ª¹Ø,0xB2±íʾÏÞÖÆÏÞÖÆWIFI×î´ó¹¦ÂÊ´ò¿ª,ÆäËûÖµ²»¿ª*/
+ UINT8 Wifi_RateLmite_En; /*ÏÞÖÆWIFI¹¦ÂÊ¿ª¹Ø£¬0xB2±íʾÏÞÖÆWIFI¹¦ÂÊ´ò¿ª,ÆäËûÖµ²»¿ª*/
+ UINT8 Wifi_IntervalTime;/*wifi½µËÙʱ¼ä¼ä¸ô£¬Ä¬ÈÏ0ʱΪĬÈÏʱ³¤1min£¬ÆäÓàÖµÉèÖöàÉÙ¼ä¸ôΪ¶àÉÙ*/
+ UINT8 Aprate_En; /*AP²àËÙÂÊ¿ØÖÆ¿ª¹Ø£¬0xB2±íʾAP²àËÙÂÊ¿ØÖÆ´ò¿ª,ÆäËûÖµ²»¿ª*/
+ UINT8 Modemrate_En; /*modem ²àËÙÂÊ¿ØÖÆ¿ª¹Ø£¬0xB2±íʾmodem²àËÙÂÊ¿ØÖÆ´ò¿ª,ÆäËûÖµ²»¿ª*/
+ UINT8 Dfs_En; /*ps ²àDFS¿ØÖÆ¿ª¹Ø£¬0xB2±íʾps ²àDFS¿ØÖÆ´ò¿ª,ÆäËûÖµ²»¿ª*/
+ UINT8 TansmitPower_En; /* modem²à½µ·¢É书ÂÊ¿ØÖÆ¿ª¹Ø, 0xB2±íʾmodem²à½µ·¢É书ÂÊ¿ØÖÆ´ò¿ª,ÆäËûÖµ²»¿ª*/
+ UINT8 User_En; /*Óû§²ßÂÔ¿ØÖÆ¿ª¹Ø0xB2±íʾ¿ª,ÆäËûÖµ²»¿ª*/
+ UINT8 reserved2[3];
+}T_SYS_NV_TSC_CONFIG;
+
+/******************************************************
+* Drv NV Config
+******************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+
+#endif /* NVPARAM_TSC_H */
diff --git a/cp/ps/driver/inc/misc/aud_drv.h b/cp/ps/driver/inc/misc/aud_drv.h
new file mode 100644
index 0000000..0fde9db
--- /dev/null
+++ b/cp/ps/driver/inc/misc/aud_drv.h
@@ -0,0 +1,1603 @@
+/**
+ * Copyright (C) Infineon Technologies Denmark A/S. All rights reserved.
+ *
+ * This document contains proprietary information belonging to Infineon
+ * Technologies Denmark A/S. Passing on and copying of this document, use
+ * and communication of its contents is not permitted without prior written
+ * authorisation.
+ *
+ * Description:
+ * Interface header file for the audio driver
+ *
+ * Revision Information:
+ * File name: \dwddrvif\inc\aud_drv.h
+ * Version: \main\34
+ * Date: 2007-10-03 09:23:08
+ * Responsible: soerenek
+ * Comment:
+ * added HW available for I2S1
+ */
+
+#if !defined (_AUD_INTERFACES)
+#define _AUD_INTERFACES
+
+#if !defined (_WIN32) /* QQQQ Problem with including bastypes.h in the test suite - fix this later */
+#include "bastypes.h"
+//#include "scttypes.h" /* QQQQ For including SDL_Pid - scttypes.h ought to be included in the file that includes aud_drv.h */
+#include "base_api.h"
+#endif /* QQQQ */
+
+/*changed by wangjun for NV change.[20090214]*/
+#include "aud_nv.h" //#include "eep.h"
+
+/* Temporarily inserted to protect the old I2S interface until it is no longer used */
+#define aud_old_I2S_interface
+
+/******************************************************************************
+*
+* Feature defines
+*
+******************************************************************************/
+#if defined(AUD_EXTERNAL_RINGER) && !defined(AUD_EXTERNAL_RINGER_MA2)
+ #define AUD_EXTERNAL_RINGER_MA3
+#endif
+
+/******************************************************************************
+*
+* Type defines
+*
+******************************************************************************/
+/* QQQQ UINT8, UINT16, UINT32, SINT8, SINT16, and SINT32 should not be used *
+ * - remove the defines when they are not used any longer */
+ #if 0 //huojishan 200801.01
+#if !defined (UNITEST) /* UINT8 and UINT16 are already defined in Microsoft Visual Studio which is used for Unitest UMAC test environment build */
+ #if !defined (UINT8)
+ typedef unsigned char UINT8;
+ #endif
+
+ #if !defined (UINT16)
+ typedef unsigned short UINT16;
+ #endif
+#endif /* UNITEST */
+
+#if !defined (UINT32)
+ #if defined (_WIN32)
+ typedef unsigned int UINT32;
+ #else
+ typedef unsigned long UINT32;
+ #endif
+#endif /* UINT32 */
+
+#if !defined (SINT8)
+ typedef signed char SINT8;
+#endif
+
+#if !defined (SINT16)
+ typedef signed short SINT16;
+#endif
+
+#if !defined (SINT32)
+ #if !defined (_WIN32)
+ typedef signed long SINT32;
+ #else
+ typedef signed int SINT32;
+ #endif
+#endif /* SINT32 */
+
+#if defined (_WIN32) /* QQQQ Problem with including bastypes.h in the test suite - fix this later */
+ #if !defined (U8)
+ typedef unsigned char U8;
+ #endif
+ #if !defined (U16)
+ typedef unsigned short U16;
+ #endif
+ #if !defined (U32)
+ typedef unsigned int U32;
+ #endif
+ #if !defined (S8)
+ typedef signed char S8;
+ #endif
+ #if !defined (S16)
+ typedef signed short S16;
+ #endif
+ #if !defined (S32)
+ typedef signed int S32;
+ #endif
+#endif /* QQQQ _WIN32 */
+#endif
+
+/* Defines/includes for PC/target builds */
+#if defined (_WIN32)
+#define SDL_Pid U8
+#define SDL_boolean BOOL
+#endif /* _WIN32 */
+
+#define DWD_HUGE
+#define DWD_AUDIO_FAR
+
+/* Return codes */
+#define aud_rc_ok 0
+#define aud_rc_resource_in_use -1
+#define aud_rc_resource_conflict -2
+#define aud_rc_handle_not_used -3
+#define aud_rc_no_hw_support -4
+#define aud_rc_sharing_violation -5
+#define aud_rc_parameter_out_of_range -6
+#define aud_rc_audio_driver_disabled -7
+#define aud_rc_missing_dsp_resources -8
+#define aud_rc_format_not_supported -10
+#define aud_rc_no_playback -11
+#define aud_rc_unknown_position -12
+#define aud_rc_request_error -13
+#define aud_rc_syntax_error -14
+#define aud_rc_tone_error -15
+#define aud_rc_storage_problems -16
+#define aud_rc_performance_problems -17
+#define aud_rc_ram_buffer_used -18
+#define aud_rc_suspend_resume_error -19
+#define aud_rc_info -20
+#define aud_rc_playback_finish -21
+#define aud_rc_playback_started -22
+#define aud_rc_playback_stopped -23
+#define aud_rc_playback_suspended -24
+#define aud_rc_playback_loop -25
+#define aud_rc_recording_finish -26
+#define aud_rc_recording_started -27
+#define aud_rc_user_event -28
+#define aud_rc_elapsed_time -29
+#define aud_rc_total_playtime -30
+#define aud_rc_not_supported -31
+#define aud_rc_mapi -32
+#define aud_rc_current_frame -33
+#define aud_rc_backwardforward_info -34
+#define aud_rc_path_removal_success -35
+#define aud_rc_path_addition_success -36
+#define aud_rc_path_addition_conflict -37
+#define aud_rc_path_removal_error -38
+#define aud_rc_user_message -39
+#define aud_rc_encoding_started -40
+#define aud_rc_encoding_stopped -41
+#define aud_rc_encoder_suspended -42
+#define aud_rc_I2S_started -43
+#define aud_rc_I2S_stopped -44
+#define aud_rc_I2S_setup_error -45
+#define aud_rc_path_in_use -46
+/* !!! Please inform the MobileAnalyzer decoding maintainer (HHE) when adding new return codes */
+
+/* Used for defining which HW is present in the system in question - must be updated when aud_resource_enum is updated */
+#define AUD_HW_AVAILABLE_SPEECH 0x00000001
+#define AUD_HW_AVAILABLE_TONE_GENERATOR 0x00000002
+#define AUD_HW_AVAILABLE_RINGER 0x00000004
+#define AUD_HW_AVAILABLE_EXTERNAL_VIBRATOR 0x00000008
+#define AUD_HW_AVAILABLE_EXTERNAL_AMPLIFIER 0x00000010
+#define AUD_HW_AVAILABLE_FM_RADIO 0x00000020
+#define AUD_HW_AVAILABLE_RECORDING_VM 0x00000040
+#define AUD_HW_AVAILABLE_PLAYBACK_VM 0x00000080
+#define AUD_HW_AVAILABLE_PLAYBACK_MP3 0x00000100
+#define AUD_HW_AVAILABLE_I2S_PCM 0x00000200
+#define AUD_HW_AVAILABLE_INTERNAL_MIDI 0x00000400
+#define AUD_HW_AVAILABLE_TTY 0x00000800
+#define AUD_HW_AVAILABLE_PLAYBACK_PCM 0x00001000
+#define AUD_HW_AVAILABLE_RECORD_PCM 0x00002000
+#define AUD_HW_AVAILABLE_MAPI 0x00004000
+#define AUD_HW_AVAILABLE_INBAND 0x00008000
+#define AUD_HW_ABAILABLE_SMPOWER_BACKSPEAKER 0x00010000
+#define AUD_HW_AVAILABLE_SBC_ENCODER 0x00020000
+#define AUD_HW_AVAILABLE_I2S2_RX 0x00040000
+#define AUD_HW_AVAILABLE_I2S2_TX 0x00080000
+
+#define AUD_HW_AVAILABLE_I2S1_RX 0x00000000
+#define AUD_HW_AVAILABLE_I2S1_TX 0x00000000
+#define AUD_HW_AVAILABLE_I2S1_BLUETOOTH 0x00400000
+/* Test handles - update this list when the list above is updated */
+#define AUD_TEST_HANDLE 0xFF
+#define AUD_SPEECH_TEST_HANDLE 0xFE
+#define AUD_TONE_GENERATOR_TEST_HANDLE 0xFD
+#define AUD_AMPLIFIER_TEST_HANDLE 0xFC
+#define AUD_RINGER_TEST_HANDLE 0xFB
+#define AUD_FM_RADIO_TEST_HANDLE 0xFA
+#define AUD_RECORDING_VM_TEST_HANDLE 0xF9
+#define AUD_PLAYBACK_VM_TEST_HANDLE 0xF8
+#define AUD_PLAYBACK_MP3_TEST_HANDLE 0xF7
+#define AUD_TTY_TEST_HANDLE 0xF6
+#define AUD_VIBRATOR_TEST_HANDLE 0xF5
+#define AUD_MIDI_PLAYER_TEST_HANDLE 0xF4
+#define AUD_PCM_CHANNEL_TEST_HANDLE 0xF3
+#define AUD_PLAYBACK_PCM_TEST_HANDLE 0xF2
+#define AUD_RECORD_PCM_TEST_HANDLE 0xF1
+#define AUD_MAPI_TEST_HANDLE 0xF0
+#define AUD_INBAND_TEST_HANDLE 0xEF
+#define AUD_SMPOWER_BACKSPEAKER_TEST_HANDLE 0xEE
+#define AUD_SBC_ENCODER_TEST_HANDLE 0xED
+#define AUD_I2S2_RX_TEST_HANDLE 0xEC
+#define AUD_I2S2_TX_TEST_HANDLE 0xEB
+
+/* For compatility reasons with atcptst */
+#define AUD_MIC 1
+#define AUD_EARPIECE 2
+
+/******************************************************************************
+*
+* External enumerations and structures
+*
+******************************************************************************/
+
+/* Resources */
+typedef enum {
+ aud_resource_speech, /* 0 */
+ aud_resource_tone_generator,
+ aud_resource_ringer, /* This Does NOT include the vibrator */
+ aud_resource_vibrator,
+ aud_resource_amplifier, /* External amplifier for speaker phone */
+ aud_resource_radio, /* 5 */
+ aud_resource_record_vm,
+ aud_resource_playback_vm,
+ aud_resource_playback_mp3,
+ aud_resource_PCM_channel, /* Replaced by I2S2_Rx and I2S2_Tx (05-12-2006) */
+ aud_resource_midi_player, /* 10 */
+ aud_resource_tty,
+ aud_resource_playback_pcm,
+ aud_resource_record_pcm,
+ aud_resource_mapi,
+ aud_resource_inband, /* 15 */ /* Virtual resource used to indicate whether non-baseband audio is active. */
+ aud_resource_smpower_backspeaker, /* SM power only if other devices input audio through SP power gain. */
+ aud_resource_sbc_encoder, /*SBC Encoder */
+ aud_resource_I2S2_Rx,
+ aud_resource_I2S2_Tx,
+ aud_resource_end
+} aud_resource_enum; /* When adding more resources, also add them to the defines at the top of this file, and notify PhoneTool group */
+
+/* Priorities for resource allocation */
+typedef enum {
+ aud_priority_normal,
+ aud_priority_high,
+ aud_priority_end
+} aud_priority_enum;
+
+/* Mute-related enumerations */
+typedef enum {
+ aud_mute_enable,
+ aud_mute_disable,
+ aud_mute_end
+} aud_mute_enum;
+
+typedef enum {
+ aud_mute_left_channel_dac,
+ aud_mute_right_channel_dac,
+ aud_mute_dac_end
+} aud_mute_dac_enum;
+
+typedef enum {
+ aud_direction_uplink, /* 0 */
+ aud_direction_downlink,
+ aud_direction_updownlink,
+ aud_direction_downlink_left,
+ aud_direction_downlink_right,
+ aud_direction_uplink_speech, /* 5 */
+ aud_direction_downlink_speech,
+ aud_direction_updownlink_speech,
+ aud_direction_end
+} aud_direction_enum;
+
+typedef enum {
+ aud_direction_resource_uplink,
+ aud_direction_resource_downlink,
+ aud_direction_resource_updownlink,
+ aud_direction_resource_end
+} aud_ul_dl_direction_enum;
+
+/* Path-related enumerations */
+typedef enum {
+ aud_disable_path,
+ aud_enable_path,
+ aud_audio_path_end
+} aud_audio_path_enum;
+
+typedef enum {
+ aud_handset_mic, /* 0 */
+ aud_headset_mic,
+ aud_I2S1_rx, /*Now used for any kind of bluetooth device connection*/
+ aud_tty_uplink,
+ aud_hfcarkit_mic,
+ aud_I2S1_inband_rx, /* 5 */
+ aud_handset_mic_42dB,
+ aud_handset_dthf_uplink,
+ aud_mic_mute,
+ aud_handset_mic_slidedown,
+ aud_handset_mic_loopback, /* 10 */
+ aud_I2S1_rx_loopback,
+ aud_media_to_uplink,
+ aud_media_to_uplink_hifi,
+ aud_stereo_mic,
+ aud_scheduler_8kHz, /* 15 */
+ aud_scheduler_16kHz,
+ aud_scheduler_48kHz,
+ aud_external_stereo_input,
+ aud_headset_mic_42dB,
+ aud_uplink_source_end
+} aud_uplink_source_enum; /* When adding more paths, remember to notify the PhoneTool group */
+
+typedef enum {
+ aud_normal_earpiece, /* 0 */
+ aud_mono_headset,
+ aud_stereo_headset,
+ aud_backspeaker,
+ aud_I2S1_tx,
+ aud_tty_downlink, /* 5 */
+ aud_mono_headset_external_ringer,
+ aud_stereo_headset_external_ringer,
+ aud_backspeaker_path_downlink,
+ aud_earpiece_path_downlink,
+ aud_backspeaker_external_ringer, /* 10 */
+ aud_hfcarkit_speaker,
+ aud_I2S1_inband_tx, /*Special path used for routing inband audio (like ringtones) to the bt headset*/
+ aud_backspeaker_stereo,
+ aud_fmradio_backspeaker,
+ aud_fmradio_headset, /* 15 */
+ aud_companion_mono_headset,
+ aud_companion_stereo_headset,
+ aud_companion_mono_backspeaker,
+ aud_companion_stereo_backspeaker,
+ aud_smpower_backspeaker, /* 20 */ /*Special path to backspeaker for non baseband audio*/
+ aud_normal_earpiece_loopback,
+ aud_I2S1_tx_loopback,
+ aud_media_to_downlink_mute,
+ aud_sidetone_loopback,
+ aud_I2S2_external, /* 25 */
+ aud_tmp_downlink_path, /* To be replaced when a new path is added. Preserved for PhoneTool compatibility. */
+ aud_downlink_source_end
+} aud_downlink_source_enum; /* When adding more paths, remember to notify the PhoneTool group */
+
+/* Enable/disable enumerations */
+typedef enum {
+ aud_enable,
+ aud_disable,
+ aud_enable_disable_end
+} aud_enable_disable_enum;
+
+/* Volume enumerations */
+typedef enum {
+ aud_ringer_volume_off,
+ aud_ringer_volume_1,
+ aud_ringer_volume_2,
+ aud_ringer_volume_3,
+ aud_ringer_volume_4,
+ aud_ringer_volume_5,
+ aud_ringer_volume_in_call,
+ aud_ringer_volume_init, /* Only for internal use in audio driver */
+ aud_ringer_volume_end
+} aud_ringer_volume_enum;
+
+typedef enum {
+ aud_speech_volume_1,
+ aud_speech_volume_2,
+ aud_speech_volume_3,
+ aud_speech_volume_4,
+ aud_speech_volume_5,
+ aud_speech_volume_6,
+ aud_speech_volume_7,
+ aud_speech_volume_8,
+ aud_speech_volume_9,
+ aud_speech_volume_10,
+ aud_speech_volume_special, /* For test purpose only */
+ aud_speech_volume_end
+} aud_speech_volume_enum;
+
+typedef enum {
+ aud_volume_0=0,
+ aud_volume_1=1,
+ aud_volume_2,
+ aud_volume_3,
+ aud_volume_4,
+ aud_volume_5,
+ aud_volume_6,
+ aud_volume_7,
+ aud_volume_8,
+ aud_volume_9,
+ aud_volume_10,
+ aud_volume_11,
+ aud_volume_12,
+ aud_volume_13,
+ aud_volume_14,
+ aud_volume_15,
+ aud_volume_16,
+ aud_volume_17,
+ aud_volume_18,
+ aud_volume_19,
+ aud_volume_20,
+ aud_volume_21,
+ aud_volume_22,
+ aud_volume_23,
+ aud_volume_24,
+ aud_volume_25,
+ aud_volume_26,
+ aud_volume_27,
+ aud_volume_28,
+ aud_volume_29,
+ aud_volume_30,
+ aud_volume_31,
+ aud_volume_32,
+ aud_volume_33,
+ aud_volume_34,
+ aud_volume_35,
+ aud_volume_36,
+ aud_volume_37,
+ aud_volume_38,
+ aud_volume_39,
+ aud_volume_40,
+ aud_volume_41,
+ aud_volume_42,
+ aud_volume_43,
+ aud_volume_44,
+ aud_volume_45,
+ aud_volume_46,
+ aud_volume_47,
+ aud_volume_48,
+ aud_volume_49,
+ aud_volume_50,
+ aud_volume_51,
+ aud_volume_52,
+ aud_volume_53,
+ aud_volume_54,
+ aud_volume_55,
+ aud_volume_56,
+ aud_volume_57,
+ aud_volume_58,
+ aud_volume_59,
+ aud_volume_60,
+ aud_volume_61,
+ aud_volume_62,
+ aud_volume_63,
+ aud_volume_64,
+ aud_volume_65,
+ aud_volume_66,
+ aud_volume_67,
+ aud_volume_68,
+ aud_volume_69,
+ aud_volume_70,
+ aud_volume_71,
+ aud_volume_72,
+ aud_volume_73,
+ aud_volume_74,
+ aud_volume_75,
+ aud_volume_76,
+ aud_volume_77,
+ aud_volume_78,
+ aud_volume_79,
+ aud_volume_80,
+ aud_volume_81,
+ aud_volume_82,
+ aud_volume_83,
+ aud_volume_84,
+ aud_volume_85,
+ aud_volume_86,
+ aud_volume_87,
+ aud_volume_88,
+ aud_volume_89,
+ aud_volume_90,
+ aud_volume_91,
+ aud_volume_92,
+ aud_volume_93,
+ aud_volume_94,
+ aud_volume_95,
+ aud_volume_96,
+ aud_volume_97,
+ aud_volume_98,
+ aud_volume_99,
+ aud_volume_100,
+ aud_volume_special, /* For test purpose only */
+ aud_volume_end
+} aud_volume_enum;
+
+/* Tone enumerations */
+typedef enum {
+ aud_tone_DTMF_0, /* 0 */
+ aud_tone_DTMF_1,
+ aud_tone_DTMF_2,
+ aud_tone_DTMF_3,
+ aud_tone_DTMF_4,
+ aud_tone_DTMF_5, /* 5 */
+ aud_tone_DTMF_6,
+ aud_tone_DTMF_7,
+ aud_tone_DTMF_8,
+ aud_tone_DTMF_9,
+ aud_tone_DTMF_hash, /* 10 */
+ aud_tone_DTMF_asterix,
+ aud_tone_key_tone_1, // Not in use.
+ aud_tone_key_tone_2, // Not in use.
+ aud_tone_key_tone_3, // Not in use.
+ aud_tone_key_tone_4, /* 15 */ /* Not in use. */
+ aud_tone_key_tone_5, // Not in use.
+ aud_tone_sv_subscriber_busy,
+ aud_tone_sv_congestion,
+ aud_tone_sv_radio_path_ack,
+ aud_tone_sv_radio_path_not_avail, /* 20 */
+ aud_tone_sv_error_info,
+ aud_tone_sv_call_waiting,
+ aud_tone_info_free_tone,
+ aud_tone_info_connection,
+ aud_tone_info_disconnect, /* 25 */
+ aud_tone_info_device_in,
+ aud_tone_info_device_out,
+ aud_tone_info_msg_full,
+ aud_tone_info_ussd,
+ aud_tone_info_minutte_minder, /* 30 */
+ aud_tone_info_error_1,
+ aud_tone_info_error_2,
+ aud_tone_info_sms_in_call,
+ aud_tone_info_broadcast_in_call,
+ aud_tone_info_alarm_in_call, /* 35 */
+ aud_tone_info_low_bat_in_call,
+ aud_tone_info_power_off,
+ aud_tone_info_power_on,
+ aud_tone_info_single_beep,
+ aud_tone_info_positive_acknowledgement, /* 40 */
+ aud_tone_info_negative_acknowledgement,
+ aud_tone_info_auto_redial,
+ aud_tone_info_network_attention,
+ aud_tone_info_dial_tone,
+ aud_tone_info_low_bat, /* 45 */
+ aud_tone_id_end
+} aud_tone_id_enum;
+
+typedef enum {
+ aud_single_user_tone,
+ aud_dual_user_tone,
+ aud_triple_user_tone,
+ aud_tone_type_end
+} aud_tone_type_enum;
+
+/* Tone generator structures */
+typedef struct {
+ U16 freq1;
+ S16 amp1;
+ U16 duration;
+} aud_single_user_tone_type;
+
+typedef struct {
+ U16 freq1;
+ S16 amp1;
+ U16 freq2;
+ S16 amp2;
+ U16 duration;
+} aud_dual_user_tone_type;
+
+typedef struct {
+ U16 freq1;
+ S16 amp1;
+ U16 freq2;
+ S16 amp2;
+ U16 freq3;
+ S16 amp3;
+ U16 duration;
+} aud_triple_user_tone_type;
+
+/* Ringer enumerations */
+typedef enum {
+ aud_ringer_info_power_off, /* 0 */
+ aud_ringer_info_power_on,
+ aud_ringer_info_low_bat,
+ aud_ringer_info_connection,
+ aud_ringer_info_error_1,
+ aud_ringer_info_error_2, /* 5 */
+ aud_ringer_info_device_in,
+ aud_ringer_info_device_out,
+ aud_ringer_info_msg_full,
+ aud_ringer_message_1,
+ aud_ringer_message_2, /* 10 */
+ aud_ringer_message_3,
+ aud_ringer_message_4,
+ aud_ringer_message_5,
+ aud_ringer_message_6,
+ aud_ringer_message_7, /* 15 */
+ aud_ringer_message_8,
+ aud_ringer_message_9,
+ aud_ringer_message_10,
+ aud_ringer_broadcast_1,
+ aud_ringer_broadcast_2, /* 20 */
+ aud_ringer_broadcast_3,
+ aud_ringer_broadcast_4,
+ aud_ringer_broadcast_5,
+ aud_ringer_broadcast_6,
+ aud_ringer_broadcast_7, /* 25 */
+ aud_ringer_broadcast_8,
+ aud_ringer_broadcast_9,
+ aud_ringer_broadcast_10,
+ aud_ringer_alarm_1,
+ aud_ringer_alarm_2, /* 30 */
+ aud_ringer_alarm_3,
+ aud_ringer_alarm_4,
+ aud_ringer_alarm_5,
+ aud_ringer_alarm_6,
+ aud_ringer_alarm_7, /* 35 */
+ aud_ringer_alarm_8,
+ aud_ringer_alarm_9,
+ aud_ringer_alarm_10,
+ aud_ringer_1,
+ aud_ringer_2, /* 40 */
+ aud_ringer_3,
+ aud_ringer_4,
+ aud_ringer_5,
+ aud_ringer_6,
+ aud_ringer_7, /* 45 */
+ aud_ringer_8,
+ aud_ringer_9,
+ aud_ringer_10,
+ aud_ringer_11,
+ aud_ringer_12, /* 50 */
+ aud_ringer_13,
+ aud_ringer_14,
+ aud_ringer_15,
+ aud_ringer_16,
+ aud_ringer_17, /* 55 */
+ aud_ringer_18,
+ aud_ringer_19,
+ aud_ringer_20,
+ aud_ringer_21,
+ aud_ringer_22, /* 60 */
+ aud_ringer_23,
+ aud_ringer_24,
+ aud_ringer_25,
+ aud_ringer_26,
+ aud_ringer_27, /* 65 */
+ aud_ringer_28,
+ aud_ringer_29,
+ aud_ringer_30,
+ aud_ringer_31,
+ aud_ringer_32, /* 70 */
+ aud_ringer_33,
+ aud_ringer_34,
+ aud_ringer_35,
+ aud_ringer_36,
+ aud_ringer_37, /* 75 */
+ aud_ringer_38,
+ aud_ringer_39,
+ aud_ringer_40,
+ aud_ringer_41,
+ aud_ringer_42, /* 80 */
+ aud_ringer_43,
+ aud_ringer_44,
+ aud_ringer_45,
+ aud_ringer_46,
+ aud_ringer_47, /* 85 */
+ aud_ringer_48,
+ aud_ringer_49,
+ aud_ringer_50,
+ aud_ringer_game_1,
+ aud_ringer_game_2, /* 90 */
+ aud_ringer_game_3,
+ aud_ringer_game_4,
+ aud_ringer_game_5,
+ aud_ringer_game_6,
+ aud_ringer_game_7, /* 95 */
+ aud_ringer_game_8,
+ aud_ringer_game_9,
+ aud_ringer_game_10,
+ aud_ringer_camera_1,
+ aud_ringer_prod_test_1, /* 100 */
+ aud_ringer_prod_test_2,
+ aud_ringer_prod_test_3,
+ aud_ringer_prod_test_4,
+ ringer_test_01,
+ ringer_test_02, /* 105 */
+ ringer_test_03,
+ ringer_test_04,
+ ringer_test_05,
+ ringer_test_06,
+ ringer_test_07, /* 110 */
+ ringer_test_08,
+ ringer_test_09,
+ ringer_test_10,
+ ringer_test_11,
+ ringer_test_12, /* 115 */
+ ringer_test_13,
+ ringer_test_14,
+ ringer_test_15,
+ ringer_test_16,
+ ringer_test_17, /* 120 */
+ ringer_test_18,
+ ringer_test_19,
+ ringer_test_20,
+ ringer_test_21,
+ ringer_test_22, /* 125 */
+ ringer_test_23,
+ ringer_test_24,
+ ringer_test_25,
+ ringer_test_26,
+ ringer_test_rambuff,
+
+ aud_ringer_tone_id_end
+} aud_ringer_tone_id_enum;
+
+typedef enum {
+ aud_ringer_device_sound,
+ aud_ringer_device_vibrator, /* Not used anymore (the functions for starting/stopping vibrator should be used) */
+ aud_ringer_device_sound_and_vibrator, /* Not used anymore (the functions for starting/stopping vibrator should be used) */
+ aud_ringer_device_end
+} aud_ringer_device_enum;
+
+typedef enum {
+ aud_format_smaf, /* MA2/MA3 NB: SMAF is not just SMAF. With the MA3 came extentions
+ to the SMAF, which cannot be played on a MA2 */
+ aud_format_midi, /* MA2/MA3 NB: Be aware that MIDI is many different formats,
+ only following formats are supported: SP-MIDI, SMF format 0 and 1 */
+ aud_format_smaf_phrase_l1, /* MA3/MA2 */
+ aud_format_rmd, /* MA3 */
+ aud_format_imelody, /* MA2/MA3 */
+ aud_format_buzzer, /* Buzzer */
+ aud_format_wav, /* wav */
+ aud_format_mp3, /* mp3 */
+ aud_format_smafaudio, /* pcm data in smaf header container*/
+ aud_format_end
+} aud_format_enum;
+
+/* Vibrator enumerations */
+typedef enum {
+ Aud_vibrator_mode_async_1,
+ Aud_vibrator_mode_async_2,
+ Aud_vibrator_mode_sync_1,
+ Aud_vibrator_mode_sync_2,
+ aud_vibmode_end
+} aud_vibrator_mode_enum;
+
+typedef enum {
+ aud_vibrator_on, /* 0 */
+ aud_vibrator_async_blinking1,
+ aud_vibrator_async_blinking2,
+ aud_vibrator_async_blinking3,
+ aud_vibrator_async_blinking4,
+ aud_vibrator_async_blinking5, /* 5 */
+ aud_vibrator_async_blinking6,
+ aud_vibrator_async_blinking7,
+ aud_vibrator_async_blinking8,
+ aud_vibrator_async_blinking9,
+ aud_vibrator_async_blinking10, /* 10 */
+ aud_vibrator_async_blinking11,
+ aud_vibrator_async_blinking12,
+ aud_vibrator_async_blinking13,
+ aud_vibrator_async_blinking14,
+ aud_vibrator_async_blinking15, /* 15 */
+ aud_vibrator_async_blinking16,
+ aud_vibrator_sync1,
+ aud_vibrator_sync2,
+ aud_vibrator_sync3,
+ aud_vibrator_sync4, /* 20 */
+ aud_vib_mode_end
+} aud_vib_mode;
+
+typedef enum {
+ Aud_vibrator_on_200ms,
+ Aud_vibrator_on_300ms,
+ Aud_vibrator_on_400ms,
+ Aud_vibrator_on_600ms,
+ Aud_vibrator_on_800ms,
+ Aud_vibrator_on_1000ms,
+ Aud_vibrator_on,
+ Aud_vibrator_on_end
+} aud_vibrator_on_enum;
+
+typedef enum {
+ Aud_vibrator_off_200ms,
+ Aud_vibrator_off_300ms,
+ Aud_vibrator_off_400ms,
+ Aud_vibrator_off_600ms,
+ Aud_vibrator_off,
+ Aud_vibrator_off_end
+} aud_vibrator_off_enum;
+
+/* FM radio enumerations */
+typedef enum {
+ aud_fm_radio_rssi_0,
+ aud_fm_radio_rssi_1,
+ aud_fm_radio_rssi_2,
+ aud_fm_radio_rssi_3,
+ aud_fm_radio_rssi_4,
+ aud_fm_radio_rssi_5,
+ aud_fm_radio_rssi_6,
+ aud_fm_radio_rssi_7,
+ aud_fm_radio_rssi_8,
+ aud_fm_radio_rssi_9,
+ aud_fm_radio_rssi_enum_end
+} aud_fm_radio_rssi_enum;
+
+typedef enum {
+ aud_fm_radio_seek_off, /* Station preset */
+ aud_fm_radio_seek_up, /* Auto seek up */
+ aud_fm_radio_seek_down, /* Auto seek down */
+ aud_fm_radio_seek_enum_end
+} aud_fm_radio_seek_mode_enum;
+
+typedef enum {
+ aud_fm_radio_rssi_info, /* SDL message contains RSSI level */
+ aud_fm_radio_seek_info, /* SDL message contains station seek result */
+ aud_fm_radio_rds_info, /* SDL message contains RDS data - only used for module testing */
+ aud_fm_radio_freq_info, /* SDL message contains frequency returned during seeking */
+ aud_fm_radio_sdl_opcodes_end
+} aud_fm_radio_sdl_opcodes_enum;
+
+/* Voice memo enumerations */
+typedef enum {
+ aud_vm_mode_standby,
+ aud_vm_mode_tch,
+ aud_vm_mode_end
+} aud_vm_mode_enum;
+
+typedef enum {
+ aud_dsp_format_fr,
+ aud_dsp_format_amr,
+ aud_dsp_format_pcm,
+ aud_dsp_format_amr_if2,
+ aud_dsp_format_end
+} aud_dsp_format_enum;
+
+typedef enum {
+ aud_media_ffs,
+ aud_media_mmc,
+ aud_media_ram,
+ aud_media_test_ram,
+ aud_media_I2S,
+ aud_media_mmf, /* Support for Multimedia framework */
+ aud_media_mmf_test, /* Support for Multimedia framework */
+ aud_media_vr,
+ aud_media_fs_cdrive, /*FS_FTL_DEVICE1 RW mode*/
+ aud_media_fs_edrive, /*FS_FTL_DEVICE2, RO only */
+ aud_media_fs_fdrive, /*FS_FTL_DEVICE1 RW mode*/
+ aud_media_end
+} aud_media_enum;
+
+typedef enum {
+ aud_amr_475, /* 0 */
+ aud_amr_515,
+ aud_amr_590,
+ aud_amr_670,
+ aud_amr_740,
+ aud_amr_795, /* 5 */
+ aud_amr_102,
+ aud_amr_122,
+ aud_amr_end
+} aud_amr_bitrate;
+
+
+/* PCM player/recorder enumerations */
+typedef enum {
+ aud_pcm_mode_mono,
+ aud_pcm_mode_dual_mono,
+ aud_pcm_mode_stereo,
+ aud_pcm_mode_end
+} aud_pcm_mode_enum;
+
+typedef enum {
+ aud_pcm_rate_1,
+ aud_pcm_rate_2,
+ aud_pcm_rate_3,
+ aud_pcm_rate_4,
+ aud_pcm_rate_5,
+ aud_pcm_rate_6,
+ aud_pcm_rate_7,
+ aud_pcm_rate_8,
+ aud_pcm_rate_9,
+ aud_pcm_rate_end
+} aud_pcm_sample_rate_enum;
+
+typedef enum {
+ aud_pcm_format_pcm,
+ aud_pcm_format_adpcm,
+ aud_pcm_format_wave,
+ aud_pcm_format_end
+} aud_pcm_format_enum;
+
+/* Yamaha Music API (mapi) enumerations */
+typedef enum {
+ aud_mapi_getmode, /* 0 */
+ aud_mapi_setmode,
+ aud_mapi_resetmode,
+ aud_mapi_initialize,
+ aud_mapi_terminate,
+ aud_mapi_checkload, /* 5 */
+ aud_mapi_checkunload,
+ aud_mapi_getcontentsdata,
+ aud_mapi_getphraselist,
+ aud_mapi_realtime_midiopen,
+ aud_mapi_realtime_midisendchmessage, /* 10 */
+ aud_mapi_realtime_starttimer,
+ aud_mapi_realtime_stoptimer,
+ aud_mapi_realtime_midiclose,
+ aud_mapi_realtime_midisendsysexmessage,
+ aud_mapi_realtime_midisetapivolume, /* 15 */
+ aud_mapi_realtime_midigetchvolume,
+ aud_mapi_phrase_audioload,
+ aud_mapi_phrase_audioopen,
+ aud_mapi_phrase_audiostandby,
+ aud_mapi_phrase_audiocontrol, /* 20 */
+ aud_mapi_phrase_audiostart,
+ aud_mapi_phrase_audiostop,
+ aud_mapi_phrase_audioclose,
+ aud_mapi_phrase_audiounload,
+ aud_mapi_phrase_getposition, /* 25 */
+ aud_mapi_phrase_setevhandler,
+ aud_mapi_phrase_getlink,
+ aud_mapi_phrase_setlink,
+ aud_mapi_phrase_kill,
+ aud_mapi_phrase_setdata, /* 30 */
+ aud_mapi_phrase_seek,
+ aud_mapi_phrase_getlength,
+ aud_mapi_phrase_setvolume,
+ aud_mapi_phrase_setpanpot,
+ aud_mapi_phrase_play, /* 35 */
+ aud_mapi_phrase_stop,
+ aud_mapi_phrase_removedata,
+ aud_mapi_phrase_getstatus,
+ aud_mapi_phrase_pause,
+ aud_mapi_phrase_restart, /* 40 */
+ aud_mapi_melody_control,
+ aud_mapi_melody_openarginit,
+ aud_mapi_melody_open,
+ aud_mapi_melody_standby,
+ aud_mapi_melody_waitready, /* 45 */
+ aud_mapi_melody_start,
+ aud_mapi_melody_stop,
+ aud_mapi_melody_seek,
+ aud_mapi_melody_close,
+ aud_mapi_melody_load, /* 50 */
+ aud_mapi_melody_unload,
+ aud_mapi_devicecontrol,
+ aud_mapi_melody_end
+} aud_mapi_if_enum;
+
+/* SBC Encoder enumerations */
+typedef enum {
+ aud_sbc_mono,
+ aud_sbc_dual_channel,
+ aud_sbc_stereo,
+ aud_sbc_joint_stereo,
+ aud_sbc_channel_mode_end
+} aud_sbc_encoder_channel_mode_enum;
+
+typedef enum {
+ aud_sbc_sample_rate_16_khz,
+ aud_sbc_sample_rate_32_khz,
+ aud_sbc_sample_rate_44_1_khz,
+ aud_sbc_sample_rate_48_khz,
+ aud_sbc_sample_rate_end
+} aud_sbc_encoder_sample_rate_enum;
+
+typedef enum {
+ aud_sbc_number_of_blocks_4,
+ aud_sbc_number_of_blocks_8,
+ aud_sbc_number_of_blocks_12,
+ aud_sbc_number_of_blocks_16,
+ aud_sbc_number_of_blocks_end
+} aud_sbc_encoder_number_of_blocks_enum;
+
+typedef enum {
+ aud_sbc_internal_data_encoding_mode,
+ aud_sbc_external_data_encoding_mode,
+ aud_sbc_data_mode_end
+} aud_sbc_encoder_data_mode_enum;
+
+/* I2S enumerations */
+typedef enum {
+ aud_dai_mode_normal,
+ aud_dai_mode_codec_test,
+ aud_dai_mode_acoustic_test,
+ aud_dai_mode_loopback,
+ aud_dai_mode_end
+} aud_dai_mode_enum;
+
+#if defined (aud_old_I2S_interface)
+typedef enum {
+ aud_I2Sx_mode1, /* Mode 1: 16 bit 8 kHz Master, Burst Mode, Mono */
+ aud_I2Sx_mode2, /* Mode 2: 16 bit 8 kHz Slave, Burst Mode, Mono */
+ aud_I2Sx_mode3, /* Mode 3: 16 bit 8 kHz Master, Normal Mode, Mono */
+ aud_I2Sx_mode4, /* Mode 4: 16 bit 8 kHz Slave, Normal Mode, Mono */
+ aud_I2Sx_mode5, /* Mode 5: 16 bit 16 kHz Master, Normal Mode, Mono */
+ aud_I2Sx_mode6, /* Mode 6: 16 bit 16 kHz Slave, Normal Mode, Mono */
+ aud_I2Sx_mode7, /* Mode 7: 16 bit 32 kHz Master, Normal Mode, Mono */
+ aud_I2Sx_mode8, /* Mode 8: 16 bit 32 kHz Master, Normal Mode, Stereo */
+ aud_I2Sx_mode9, /* Mode 9: 16 bit 32 kHz Slave, Normal Mode, Mono*/
+ aud_I2Sx_mode10, /* Mode 10: 16 bit 44.1 kHz Master, Normal Mode, Mono */
+ aud_I2Sx_mode11, /* Mode 11: 16 bit 44.1 kHz Master, Normal Mode, Stereo */
+ aud_I2Sx_mode12, /* Mode 12: 16 bit 44.1 kHz Slave, Normal Mode, Mono */
+ aud_I2Sx_mode13, /* Mode 13: 16 bit 48 kHz Master, Normal Mode, Mono */
+ aud_I2Sx_mode14, /* Mode 14: 16 bit 48 kHz Master, Normal Mode, Stereo */
+ aud_I2Sx_mode15, /* Mode 15: 16 bit 48 kHz Slave, Normal Mode, Mono */
+ aud_I2S2_mode_dai, /* set up the I2S2 to dai mode*/
+ aud_I2Sx_mode16, /* Mode 16: 16bit 8 kHz, Slave, Normal mode, Stereo*/
+ aud_I2Sx_mode17, /* Mode 17: 16bit 11.025 kHz, Slave, Normal mode, Stereo*/
+ aud_I2Sx_mode18, /* Mode 18: 16bit 12 kHz, Slave, Normal mode, Stereo*/
+ aud_I2Sx_mode19, /* Mode 19: 16bit 16 kHz, Slave, Normal mode, Stereo*/
+ aud_I2Sx_mode20, /* Mode 20: 16bit 22.05 kHz, Slave, Normal mode, Stereo*/
+ aud_I2Sx_mode21, /* Mode 21: 16bit 24 kHz, Slave, Normal mode, Stereo*/
+ aud_I2Sx_mode22, /* Mode 22: 16bit 32 kHz, Slave, Normal mode, Stereo*/
+ aud_I2Sx_mode23, /* Mode 23: 16bit 44.1 kHz, Slave, Normal mode, Stereo*/
+ aud_I2Sx_mode24, /* Mode 24: 16bit 48k Hz, Slave, Normal mode, Stereo*/
+ aud_I2Sx_mode25, /* Mode 25: 16bit 8kHz, Master, Normal mode, DualMono*/
+ aud_I2Sx_mode_end
+} aud_I2Sx_mode_enum;
+#endif /* aud_old_I2S_interface */
+
+typedef enum {
+ aud_I2S2_clk0,
+ aud_I2S2_clk1,
+ aud_I2S_clk_end
+} aud_I2S_clk_enum;
+
+typedef enum { /* Changes in this enum will change the validation matrix */
+ aud_I2S_master,
+ aud_I2S_slave,
+ aud_I2S_Master_Slave_end
+} aud_I2S_Master_Slave_enum;
+
+typedef enum { /* Changes in this enum will change the validation matrix */
+ aud_I2S_samplerate_08000,
+ aud_I2S_samplerate_11025,
+ aud_I2S_samplerate_12000,
+ aud_I2S_samplerate_16000,
+ aud_I2S_samplerate_22050,
+ aud_I2S_samplerate_24000,
+ aud_I2S_samplerate_32000,
+ aud_I2S_samplerate_44100,
+ aud_I2S_samplerate_48000,
+ aud_I2S_samplerate_end
+} aud_I2S_samplerate_enum;
+
+typedef enum {
+ aud_I2S_sample_width_16,
+ aud_I2S_sample_width_18,
+ aud_I2S_sample_width_20,
+ aud_I2S_sample_width_24,
+ aud_I2S_sample_width_32,
+ aud_I2S_sample_width_end
+} aud_I2S_sample_width_enum;
+
+typedef enum { /* Changes in this enum will change the validation matrix */
+ aud_I2S_transmission_mode_PCM,
+ aud_I2S_transmission_mode_normal, /* Normal I2S */
+ aud_I2S_transmission_mode_end
+} aud_I2S_transmission_mode_emum;
+
+typedef enum {
+ aud_I2S_setting_normal,
+ aud_I2S_setting_special_case1,
+ aud_I2S_setting_special_case2,
+ aud_I2S_setting_end
+} aud_I2S_setting_enum;
+
+typedef enum { /* Changes in this enum will change the validation matrix */
+ aud_I2S_mode_mono,
+ aud_I2S_mode_dual_mono,
+ aud_I2S_mode_stereo,
+ aud_I2S_mode_end
+} aud_I2S_mode_enum;
+
+typedef enum { /* Changes in this enum will change the validation matrix */
+ aud_I2S_entry_point_MMS,
+ aud_I2S_entry_point_MMS_FB, /* located at the frame-based part of the voiceband processing system */
+ aud_I2S_entry_point_External,
+ aud_I2S_entry_point_DAI,
+ aud_I2S_entry_point_end
+} aud_I2S_entry_point_enum;
+
+typedef enum {
+ aud_8_KHz,
+ aud_16_KHz,
+ aud_sample_rate_end
+}aud_sample_rate_enum;
+
+#if defined (aud_old_I2S_interface)
+typedef enum {
+ aud_disable_pcm_channel,
+ aud_enable_pcm_channel,
+ aud_enable_pcm_channel_and_Dai,
+ aud_enable_pcm_channel_externalmode,
+ aud_audio_pcm_end
+} aud_audio_pcm_enum;
+
+typedef enum {
+ aud_pcm_direction_rx,
+ aud_pcm_direction_tx,
+ aud_pcm_direction_rx_tx,
+ aud_pcm_direction_end
+} aud_pcm_direction_enum;
+#endif /* aud_old_I2S_interface */
+
+/* smaf enumerations */
+typedef enum {
+ aud_smaf_err_ok, /* 0 */
+ aud_smf_err_initialize_failed,
+ aud_smf_err_create_failed,
+ aud_smf_err_load_failed,
+ aud_smf_err_open_failed,
+ aud_smf_err_evhand_failed, /* 5 */
+ aud_smf_err_standby_failed,
+ aud_smf_err_seek_failed,
+ aud_smf_err_control_failed,
+ aud_smf_err_start_failed,
+ aud_smf_err_stop_failed, /* 10 */
+ aud_smf_err_close_failed,
+ aud_smf_err_unload_failed,
+ aud_smf_err_delete_failed,
+ aud_smf_err_invalid_parameters,
+ aud_smf_err_wrong_state /* 15 */
+} aud_smaf_error_enum;
+
+/* DSP info */
+typedef enum {
+ aud_dsp_tch_mode,
+ aud_dsp_pdch_mode,
+ aud_dsp_idle_mode,
+ aud_dsp_bb_off_mode,
+ aud_dsp_bb_off_tch_26_mode,
+ aud_dsp_mode_end
+} aud_dsp_info_enum;
+
+/* Accessory enumeration (deprecated) */
+typedef enum {
+ aud_accessory_normal, /* 0 */
+ aud_accessory_headset,
+ aud_accessory_back_speaker_normal_mic,
+ aud_accessory_midi_louder_speaker,
+ aud_accessory_bt_headset,
+ aud_accessory_stereo_phones, /* 5 */
+ aud_accessory_car_kit,
+ aud_accessory_end
+} aud_accessory_enum;
+
+/* Layer 1 info (deprecated) */
+typedef enum {
+ aud_layer1_tch_mode,
+ aud_layer1_pdch_mode,
+ aud_layer1_idle_mode,
+ aud_layer1_bb_off_mode,
+ aud_layer1_bb_off_tch_26_mode,
+ aud_layer1_mode_end
+} aud_layer1_info_enum;
+
+/* Resource capability enumerations (deprecated) */
+typedef enum {
+ uplink_paths_supported, //deprecated
+ downlink_paths_supported, //deprecated
+ resource_conflict, //deprecated
+ features_supported //deprecated
+} aud_resource_capability_enum; //this enum is only used by deprecated function AUD_get_resource_capability
+
+/* Test ram buffer enumerations */
+typedef enum {
+ aud_testrambufferstatus_free, /* ram buffer is free to allocate */
+ aud_testrambufferstatus_busy, /* ram buffer is used by players */
+ aud_testrambufferstatus_copy, /* copying is ongoing */
+ aud_testrambufferstatus_idle, /* ram buffer is allocated and copied but not used */
+ aud_testrambufferstatus_end
+} aud_testrambuffer_status_enum;
+
+/* Callback function type definitions */
+typedef int (*ptr_GetAudioBufferFunction)(
+ /* audiobuffer */ U8 **,
+ /* size */ U16 *,
+ /* user_data */ void *user_data);
+typedef void (*ptr_SetVbOnStatusFunction)(
+ /* Status */ U8);
+typedef void (*ptr_FmRadioRdsCallbackFunction)(
+ /* rds_buffer */ U8 *,
+ /* num_bytes */ U16);
+
+/* Structures for acoustic test */
+#define AUD_MAX_MIC_FREQ_NUM 3
+typedef struct {
+ U16 freq_mid;
+ U16 UpperLimit;
+ U16 LowerLimit;
+} InputMicVal_Type;
+
+typedef struct {
+ U16 actest_no_of_freq;
+ U16 actest_no_of_freq_outoflim;
+ U16 actest_scal;
+ U16 actest_ppeak;
+ U16 actest_npeak;
+ U16 actest_level_f1;
+ U16 actest_level_f2;
+ U16 actest_level_f3;
+ U16 actest_level_f4;
+ U16 actest_level_f5;
+ U16 actest_level_f6;
+} T_DSP_CMD_ACOUSTIC_TEST_RESULT_PAR;
+
+/******************************************************************************
+*
+* Global variables
+*
+******************************************************************************/
+extern U8 aud_mon_gaim_setting[2];
+
+#if defined (VMS_PRESENT)
+extern ptr_GetAudioBufferFunction getAudioBuffer;
+#endif
+
+#if defined (MP3_PRESENT)
+extern ptr_GetAudioBufferFunction mp3_getAudioBuffer;
+#endif
+
+#define AUD_GLOBAL_TONE_DUR_INTER_DEFAULT_VALUE 10
+extern U16 aud_global_tone_dur_inter;
+
+
+#ifdef _OS_WIN
+#define DISABLE_CLOCK
+#define ENABLE_CLOCK
+
+#define ATOMIC_BEGIN
+#define ATOMIC_END
+#else
+#define DISABLE_CLOCK ZOSS_DISABLE_IRQ();
+#define ENABLE_CLOCK ZOSS_ENABLE_IRQ();
+
+#define ATOMIC_BEGIN ZOSS_DISABLE_IRQ();
+#define ATOMIC_END ZOSS_ENABLE_IRQ();
+#endif
+
+#ifndef MAX
+#define MAX(A,B) ( (A) > (B) ? (A) : (B) )
+#endif
+
+/******************************************************************************
+*
+* Prototypes for interface functions
+*
+******************************************************************************/
+
+/* Resource allocation */
+S8 AUD_allocate_resource(U16 id, aud_resource_enum resource, aud_priority_enum priority);
+S8 AUD_release_resource(U8 handle);
+
+/* Path control */
+U32 AUD_get_downlnk_parallel_path_configuration(aud_downlink_source_enum path);
+U32 AUD_get_uplink_parallel_path_configuration(aud_uplink_source_enum path);
+S8 AUD_add_uplinkpath(aud_uplink_source_enum path);
+S8 AUD_remove_uplinkpath(aud_uplink_source_enum path);
+S8 AUD_add_downlinkpath(aud_downlink_source_enum path);
+S8 AUD_remove_downlinkpath(aud_downlink_source_enum path);
+S8 AUD_Pathupdate_Enable(void);
+S8 AUD_Pathupdate_Disable(void);
+S8 AUD_set_eq_vol_threshold(aud_downlink_source_enum path, aud_volume_enum eq_volume_threshold);
+
+/* Volume control */
+S8 AUD_set_resource_volume(U8 handle, aud_volume_enum volume);
+S8 AUD_set_master_volume(aud_volume_enum volume);
+S8 AUD_mute_resource(U8 handle, aud_mute_enum enable_disable,
+ aud_ul_dl_direction_enum direction);
+S8 AUD_mute_master(aud_mute_enum enable_disable);
+
+/* Speech */
+S8 AUD_speech_enable(U8 handle);
+S8 AUD_speech_disable(U8 handle);
+S8 AUD_set_EC_NR(U8 EC_on, U8 NR_on);
+
+/* Tone generator */
+S8 AUD_tone_start(U8 handle, aud_tone_id_enum tone_id,
+ U16 nof_repeats, S16 mix_factor);
+S8 AUD_tone_start_user_tone(U8 handle, void *tone_data, aud_tone_type_enum type,
+ U32 nof_tones, U16 nof_repeats, S16 mix_factor);
+S8 AUD_tone_stop(U8 handle);
+S8 AUD_tone_suspend(U8 handle, U8 slot_id);
+S8 AUD_tone_resume(U8 handle, U8 slot_id);
+S8 AUD_tone_get_total_playtime(U8 handle, aud_tone_id_enum tone_id, void *tone_data,
+ U32 nof_tones, aud_tone_type_enum type);
+S8 AUD_tone_get_play_position(U8 handle);
+S8 AUD_tone_set_play_position(U8 handle, U32 pos);
+
+/* Ringer */
+S8 AUD_ringer_start(U8 handle, aud_ringer_tone_id_enum tone_id,
+ U16 nof_repeats, aud_ringer_device_enum device);
+S8 AUD_ringer_start_user_tone(U8 handle, U8 DWD_HUGE *ringer_data,
+ U32 size, aud_format_enum format, U16 nof_repeats,
+ aud_ringer_device_enum device, U8 channel, U8 channel_volume);
+S8 AUD_ringer_stop(U8 handle, U8 channel);
+S8 AUD_ringer_set_channel_volume(U8 handle, U8 channel_volume, U8 channel);
+S8 AUD_ringer_suspend(U8 handle, U8 SlotID, U8 channel);
+S8 AUD_ringer_resume(U8 handle, U8 SlotID, U8 channel);
+S8 AUD_ringer_stop_suspend(U8 handle, U8 SlotID, U8 channel);
+S8 AUD_ringer_get_total_playtime(U8 handle, U8 DWD_HUGE *data, U32 data_size,
+ aud_format_enum format, aud_ringer_tone_id_enum tone_id);
+S8 AUD_ringer_get_playposition(U8 handle);
+S8 AUD_ringer_set_playposition(U8 handle, U8 channel, U32 offset);
+
+/* Vibrator */
+void AUD_vibrator_enable(aud_vib_mode mode, U8 channel);
+void AUD_vibrator_pause(void);
+void AUD_vibrator_disable(void);
+
+/* FM Radio */
+S8 AUD_radio_enable(U8 handle);
+S8 AUD_radio_disable(U8 handle);
+S8 AUD_radio_rssi_subscribe(U8 handle, aud_fm_radio_rssi_enum lower_threshold,
+ aud_fm_radio_rssi_enum upper_threshold);
+S8 AUD_radio_rds_subscribe(U8 handle, ptr_FmRadioRdsCallbackFunction pCbFunc);
+S8 AUD_radio_set_station(U8 handle, aud_fm_radio_seek_mode_enum seekmode,
+ U32 frequency, aud_fm_radio_rssi_enum detect_level, U8 force_mono);
+S8 AUD_radio_get_frequency(U8 handle);
+
+/* Voice memo */
+S8 AUD_vm_start_recording(
+ U8 handle,
+ aud_vm_mode_enum vm_mode,
+ aud_media_enum media_type,
+ aud_dsp_format_enum format,
+ U8 rate,
+ U16 DWD_HUGE *file_handle,
+ U32 buffer_size,
+ U32 offset);
+S8 AUD_vm_stop_recording(U8 handle);
+S8 AUD_vm_start_playback(
+ U8 handle,
+ aud_vm_mode_enum vm_mode,
+ aud_media_enum media_type,
+ aud_dsp_format_enum format,
+ U16 DWD_HUGE *file_handle,
+ U32 buffer_size,
+ U16 nof_repeats,
+ U32 offset);
+S8 AUD_vm_stop_playback(U8 handle);
+void Aud_vms_set_getbuffer_function(U8 handle, ptr_GetAudioBufferFunction func,
+ void * user_data);
+S8 AUD_vm_suspend(U8 handle, U8 slot_id);
+S8 AUD_vm_resume(U8 handle, U8 slot_id);
+S8 AUD_vm_get_total_playtime(
+ U8 handle,
+ aud_media_enum media_type,
+ aud_dsp_format_enum format,
+ U16 DWD_HUGE *file_handle,
+ U32 buffer_size,
+ U32 offset);
+S8 AUD_vm_get_play_position(U8 handle);
+S8 AUD_vm_set_play_position(
+ U8 handle,
+ U32 pos,
+ U16 DWD_HUGE *file_handle,
+ U32 buffer_size);
+S8 AUD_vm_stop_suspend(U8 handle, U8 slot_id);
+
+/* MP3 Player */
+S8 AUD_mp3_start(U8 handle, aud_media_enum media_type, U16 DWD_HUGE *file_handle,
+ U32 buffer_size, U32 id_offset, U32 start_frame, U16 nof_repeats);
+S8 AUD_mp3_stop(U8 handle);
+S8 AUD_mp3_suspend(U8 handle, U16 slot_id);
+S8 AUD_mp3_resume(U8 handle, U16 slot_id);
+S8 AUD_mp3_fastforward(U8 handle, U32 frame, U16 slot_id);
+S8 AUD_mp3_backward(U8 handle, U32 frame, U16 slot_id);
+void Aud_mp3_set_getbuffer_function(U8 handle, ptr_GetAudioBufferFunction func,
+ void * user_data);
+S8 Aud_mp3_get_current_frame(U8 handle, U16 slot_id);
+S8 AUD_mp3_get_total_playtime(U8 handle, aud_media_enum media_type,
+ U16 DWD_HUGE *file_handle, U32 buffer_size,
+ U32 id_offset );
+S8 AUD_mp3_get_play_position(U8 handle);
+S8 AUD_mp3_set_play_position(U8 handle, U32 pos, U16 DWD_HUGE *file_handle,
+ U32 buffer_size);
+S8 AUD_mp3_stop_suspend(U8 handle, U8 SlotID);
+
+/* TTY */
+S8 AUD_tty_enable(U8 handle);
+S8 AUD_tty_disable(U8 handle);
+S8 AUD_tty_set_negotiation(U8 handle,U8 on_off);
+
+/* PCM player/recorder */
+S8 AUD_pcm_intern_start_playback(
+ U8 handle,
+ aud_pcm_mode_enum mode,
+ aud_pcm_sample_rate_enum sample_rate,
+ U8 bit_rate,
+ aud_media_enum media_type,
+ aud_pcm_format_enum format,
+ U16 DWD_HUGE *file_handle,
+ U32 buffer_size,
+ U16 nof_repeats,
+ U32 start_offset);
+S8 AUD_pcm_intern_stop_playback(U8 handle);
+S8 AUD_pcm_intern_start_recording(
+ U8 handle,
+ aud_pcm_sample_rate_enum sample_rate,
+ aud_media_enum media_type,
+ aud_pcm_format_enum format,
+ U16 DWD_HUGE *file_handle,
+ U32 buffer_size,
+ U32 start_offset);
+S8 AUD_pcm_intern_stop_recording(U8 handle);
+S8 AUD_pcm_intern_getbuffer_function(U8 handle, ptr_GetAudioBufferFunction func,
+ void * user_data);
+S8 AUD_pcm_intern_suspend(U8 handle, U8 slot_id);
+S8 AUD_pcm_intern_resume(U8 handle, U8 slot_id);
+S8 AUD_pcm_intern_stop_suspend(U8 handle, U8 slot_id);
+S8 AUD_pcm_intern_get_total_playtime(U8 handle, aud_media_enum media_type,
+ aud_pcm_format_enum format, aud_pcm_sample_rate_enum sample_rate,
+ aud_pcm_mode_enum mode, U8 bit_rate,
+ U16 DWD_HUGE *file_handle, U32 buffer_size, U32 offset);
+S8 AUD_pcm_intern_get_play_position(U8 handle);
+S8 AUD_pcm_intern_set_play_position(U8 handle, U32 pos,
+ U16 DWD_HUGE *file_handle, U32 buffer_size);
+
+/* Yamaha Music API (mapi) */
+S8 AUD_mapi(U8 handle, aud_mapi_if_enum func_id, U32 parm1, U32 parm2,
+ U32 parm3, U32 parm4, U32 parm5, U32 parm6, U32 parm7);
+
+/* Inband resource, used for non-baseband audio */
+/**
+ * AUD_non_baseband_resource_start
+ *
+ * This function activates the inband virtual resource, used for non-baseband audio.
+ * Only use this when aud_resource_inband is allocated. The resource is virtual,
+ * so the usecase is non-baseband audio output on whatever paths are enabled.
+ *
+ * @param handle (generated by AUD_allocate_resource)
+ * @see AUD_allocate_resource
+ * @return signed 8bit integer (error code)
+ */
+S8 AUD_non_baseband_resource_start(U8 handle);
+
+/**
+ * AUD_non_baseband_resource_stop
+ *
+ * This function deactivates the inband virtual resource, used for non-baseband audio.
+ * Only use this when aud_resource_inband is allocated. The resource is virtual,
+ * so the usecase is non-baseband audio output on whatever paths are enabled.
+ *
+ * @param handle (generated by AUD_allocate_resource)
+ * @see AUD_allocate_resource
+ * @return signed 8bit integer (error code)
+ */
+S8 AUD_non_baseband_resource_stop(U8 handle);
+
+/* SM Power */
+/**
+ * AUD_SMPower_enable
+ *
+ * This function is to trigger the power-on of the SM Power Gain Amplifier
+ * Only use this when allocating the aud_resource_smpower. The resource is virtual,
+ * so the usecase is an external device outputting through SM power.
+ *
+ * @param handle (generated by AUD_allocate_resource)
+ * @see AUD_allocate_resource
+ * @return signed 8bit integer (error code)
+ */
+S8 AUD_SMPower_enable(U8 handle);
+/**
+ * AUD_SMPower_disable
+ *
+ * This function is to trigger the power-off of the SM Power Gain Amplifier
+ * Only use this when allocating the aud_resource_smpower. The resource is virtual,
+ * so the usecase is an external device outputting through SM power.
+ *
+ * @param handle (generated by AUD_allocate_resource)
+ * @see AUD_allocate_resource
+ * @return signed 8bit integer (error code)
+ */
+S8 AUD_SMPower_disable(U8 handle);
+
+/* SBC Encoder */
+S8 AUD_sbc_encoder_start (U8 handle,
+ aud_sbc_encoder_data_mode_enum data_mode,
+ aud_sbc_encoder_channel_mode_enum channel_mode,
+ aud_sbc_encoder_sample_rate_enum sample_rate,
+ aud_sbc_encoder_number_of_blocks_enum no_of_blocks,
+ U8 bitpool);
+S8 AUD_sbc_encoder_stop(U8 handle);
+S8 AUD_sbc_encoder_suspend(U8 handle, U8 slot_id);
+S8 AUD_sbc_encoder_resume (U8 handle, U8 slot_id);
+S8 AUD_sbc_encoder_set_getinputbuffer_function(U8 handle,
+ ptr_GetAudioBufferFunction input_buffer_function,
+ void * user_data);
+S8 AUD_sbc_encoder_set_getoutputbuffer_function(U8 handle,
+ ptr_GetAudioBufferFunction output_buffer_function,
+ void * user_data);
+
+/* I2S2 Rx and Tx*/
+#if defined (aud_old_I2S_interface)
+S8 AUD_configure_pcm_channel(U8 handle, aud_I2Sx_mode_enum mode);
+S8 AUD_pcm_channel_routing(U8 handle, U8 input_to_uplink, U8 input_to_downlink,
+ U8 output_from_uplink, U8 output_from_downlink);
+S8 AUD_pcm_channel_enable(U8 handle, aud_pcm_direction_enum direction);
+S8 AUD_pcm_channel_disable(U8 handle);
+#endif /* aud_old_I2S_interface */
+S8 AUD_I2S_enable_resource(U8 handle);
+S8 AUD_I2S_disable_resource (U8 handle);
+S8 AUD_I2S_setup_clock(aud_I2S_clk_enum clock,
+ aud_I2S_Master_Slave_enum Master_Slave,
+ aud_I2S_samplerate_enum samplerate,
+ aud_I2S_sample_width_enum sample_width,
+ aud_I2S_transmission_mode_emum transmission_mode,
+ aud_I2S_setting_enum settings,
+ aud_I2S_mode_enum I2S_mode);
+S8 AUD_I2S_setup_resource(U8 handle,
+ aud_I2S_clk_enum clock,
+ aud_I2S_entry_point_enum entry_point);
+
+/* I2S1 */
+S8 AUD_configure_bluetooth(U8 handle, aud_I2Sx_mode_enum mode);
+
+/* 3D stereo */
+S8 AUD_3D_mode_enable(void);
+S8 AUD_3D_mode_disable(void);
+
+/* Interrupts */
+void AUD_tone_handle_int(void);
+void AUD_TONE_int_handler(int vector);
+void AUD_poak_int2_handle_int(void);
+void AUD_POAK_INT2_int_handler(int vector);
+void AUD_TEAK_INT5_int_handler(int vector);
+void AUD_teak_int5_handle_int(void);
+void AUD_TEAK_INT4_int_handler(int vector);
+void AUD_teak_int4_handle_int(void);
+void AUD_TEAK_INT6_int_handler(int vector);
+void AUD_teak_int6_handle_int(void);
+void AUD_TEAK_INT7_int_handler(int vector);
+void AUD_teak_int7_handle_int(void);
+void AUD_hal_fm_radio_lisr_int_handler(int vector); /* LISR for FM Radio interrupt */
+
+/* Misc functions */
+U32 AUD_info_hw_available(void);
+void AUD_misc_dsp_info(aud_dsp_info_enum dsp_info); /* Only to be used on interface between DSP and AUD */
+S8 Aud_set_vb_on_status_function(ptr_SetVbOnStatusFunction func);
+
+/* Misc functions */
+void aud_drv_check_timeout(void);
+void aud_dai_mode(aud_dai_mode_enum dai_mode);
+void aud_drv_restart_hf(void);
+
+/* Test functions */
+U16 AUD_ptest_generic_func(void *func_req_ptr); /* generic ATCP test interface */
+U16 AUD_ptest_generic_func_memaligned(void *func_req_ptr);
+
+/* FFT analysis */
+S8 AUD_FFT_Start(U16 NoOfFrames, U16 AverageExponent, U16 RefLevel, U16 QFormat,
+ InputMicVal_Type *pMicVal);
+S8 AUD_FFT_GetResult(T_DSP_CMD_ACOUSTIC_TEST_RESULT_PAR **pFFT_Result);
+
+/* Audio Dispatcher - should only be used in aud_intf.c and aud_op.c */
+void AudioDispatcher(
+ SDL_Pid sender,
+ U8 event,
+ U16 caller_id,
+ U32 parm1,
+ U32 parm2,
+ U32 parm3,
+ U32 parm4,
+ U32 parm5,
+ U32 parm6,
+ U32 parm7,
+ U32 parm8,
+ U8 *ptr1,
+ U8 *ptr2);
+
+/******************************************************************************
+*
+* Deprecated functions
+*
+******************************************************************************/
+/* Do not remove the following functions here - file is shared between EGold, SGold and other systems */
+/* This is old stuff that has to be removed when Apoxi has cleaned out their inclusion of old files - depending on this */
+
+S8 AUD_media_to_uplink(U8 enable_disable); /* deprecated - use new path aud_media_to_uplink instead */
+S8 AUD_media_to_downlink(U8 enable_disable); /* deprecated - use new path aud_media_to_downlink_mute instead */
+U32 AUD_get_resource_capability(aud_resource_enum resource, aud_resource_capability_enum capability);
+S8 AUD_key_tone(aud_tone_id_enum key_tone, S16 mix_factor);
+S8 AUD_amp_enable(U8 handle);
+S8 AUD_amp_disable(U8 handle);
+S8 AUD_vibrator_start(U8 handle, aud_vibrator_mode_enum mode,
+ aud_vibrator_on_enum on, aud_vibrator_off_enum off);
+S8 AUD_vibrator_stop(U8 handle);
+void AUD_misc_set_accessory(aud_accessory_enum accessory);
+void AUD_misc_set_vmic(U8 status);
+S8 AUD_set_volume(U8 handle, aud_volume_enum volume);
+S8 AUD_speech_set_volume(U8 handle, aud_speech_volume_enum volume);
+S8 AUD_ringer_set_volume(U8 handle,aud_ringer_volume_enum volume);
+void AUD_init(void);
+S8 AUD_radio_init(U8 handle);
+S8 AUD_radio_config(U8 handle, void * aud_radio_config_data);
+S8 AUD_radio_read_current_status(U8 handle);
+S8 AUD_radio_mute(U8 handle,U8 mute);
+S8 AUD_speech_mute(U8 handle,aud_mute_enum status,aud_direction_enum direction);
+#ifdef USE_VOICE_SUPPORT
+void AUD_misc_layer1_info(aud_layer1_info_enum layer1_info); /* Only to be used on interface between AUD and Layer1 */
+#endif
+#endif /* _AUD_INTERFACES */
+/* End of file. */
diff --git a/cp/ps/driver/inc/misc/aud_nv.h b/cp/ps/driver/inc/misc/aud_nv.h
new file mode 100644
index 0000000..3d171b3
--- /dev/null
+++ b/cp/ps/driver/inc/misc/aud_nv.h
@@ -0,0 +1,1232 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: aud_nv.h
+* File Mark:
+* Description: Provide audio NV function prototype declaration and type declaration. The audio NV type declaration is moved from eep.h.
+* Others:
+* Version: v0.5
+* Author: Wangjun
+* Date: 2009-02-14
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+* History 2:
+**********************************************************************/
+
+#ifndef _AUD_NV_H
+#define _AUD_NV_H
+
+
+
+/**************************************************************************
+ * Include files *
+ **************************************************************************/
+
+
+
+/**************************************************************************
+ * Macro *
+ **************************************************************************/
+#ifndef int16
+#define int16 short int
+#endif
+#ifndef int32
+#define int32 long
+#endif
+
+/* Defines to determine array sizes */
+#if 0
+#define EEP_AUD_BIQUAD_FILTERS_UL 30
+#define EEP_AUD_BIQUAD_FILTERS_DL 20
+#define EEP_AUD_BIQUAD_FILTERS_CBUF 10
+#endif
+#if 0
+#define EEP_AUD_FIR_FILTERS_UL 5
+#define EEP_AUD_FIR_FILTERS_DL 5
+#define EEP_AUD_FIR_FILTERS_CBUF 5
+#endif
+#if 0
+#define EEP_AUD_HF 8
+#endif
+#if 0
+#define EEP_AUD_ASP_UL 5
+#define EEP_AUD_DL_NR 5
+#endif
+#define EEP_AUD_UPLINK_PATHS 22
+#define EEP_AUD_DOWNLINK_PATHS 29
+
+#define AUDIO_PATHS 10 /*defined multiple places -also in aud_data.h*/
+
+/*[Begin] [lvwenhua-2010/9/16]*/
+#define EEP_CODEC_UPLINK_PATHS 3 //MAX_CODEC_INPUT_PATH
+#define EEP_CODEC_DOWNLINK_PATHS 5 //MAX_CODEC_OUTPUT_PATH
+#define EEP_VOICE_OUTPUT_VOL_LEVELS 12 /* MAX_VOICE_OUTPUT_VOL_LEVEL */
+#define EEP_MIDI_OUTPUT_VOL_LEVELS 12 /* MAX_MIDI_OUTPUT_VOL_LEVEL */
+#define EEP_TONE_OUTPUT_VOL_LEVELS 12 /* MAX_TONE_OUTPUT_VOL_LEVEL */
+#define EEP_PCM_OUTPUT_VOL_LEVELS 12 /* MAX_AUDIO_OUTPUT_VOL_LEVEL */
+/*[End] [lvwenhua-2010/9/16]*/
+
+#define EEP_AUD_CEPT 0
+#define EEP_AUD_ANSI 1
+#define EEP_AUD_JAPAN 2
+#define EEP_AUD_REGION_END 3
+
+typedef struct
+{
+ UINT16 gain_out; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÏÂÐеÄgain_outÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x1FFF£»
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,23,25,26,27,28ʱ:
+ aud_audio_downlink_parms[n].downlink_gain_cells.gain_out = 8192;
+ µ±n =20,21,22,24ʱ:
+ aud_audio_downlink_parms[n].downlink_gain_cells.gain_out = 0;
+ *********************************************************************************/
+
+ UINT16 gain_out_use; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÏÂÐеÄgain_outÔöÒæÊÇ·ñÊÇÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,21,22,25,26,27,28ʱ:
+ aud_audio_downlink_parms[n].downlink_gain_cells.gain_out_use=1;
+ µ±n =20,23,24ʱ:
+ aud_audio_downlink_parms[n].downlink_gain_cells.gain_out_use=0;
+ *********************************************************************************/
+
+ UINT16 kappa0; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÏÂÐеÄkappa0ÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x7FFF£»
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,23,25,26,27,28ʱ:
+ aud_audio_downlink_parms[n].downlink_gain_cells.kappa0=32767;
+ µ±n =21,22,24ʱ:
+ aud_audio_downlink_parms[0].downlink_gain_cells.kappa0=0;
+ *********************************************************************************/
+
+ UINT16 kappa0_use; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÏÂÐеÄkappa0ÔöÒæÊÇ·ñÊÇÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,25,26,27,28ʱ:
+ aud_audio_downlink_parms[n].downlink_gain_cells.kappa0_use = 1;
+ µ±n =20,21,22,23,24ʱ:
+ aud_audio_downlink_parms[n].downlink_gain_cells.kappa0_use = 0;
+ *********************************************************************************/
+
+ UINT16 mix_afe; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÏÂÐеĻìºÏµ½AFEµÄmix_afeÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x3FFF£»
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,24,25,26,27,28ʱ:
+ aud_audio_downlink_parms[n].downlink_gain_cells.mix_afe=1;
+ µ±n =21,22,23ʱ:
+ aud_audio_downlink_parms[n].downlink_gain_cells.mix_afe=0;
+ *********************************************************************************/
+
+ UINT16 mix_afe_use; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÏÂÐеĻìºÏµ½AFEµÄmix_afeÔöÒæÊÇ·ñÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,24,25,26,27,28ʱ:
+ aud_audio_downlink_parms[n].downlink_gain_cells.mix_afe_use=0;
+ µ±n =21,22,23ʱ:
+ aud_audio_downlink_parms[n].downlink_gain_cells.mix_afe_use=1;
+ *********************************************************************************/
+}
+eep_aud_downlink_gain_cells_type;
+
+typedef struct
+{
+ SINT16 hf_algorithm_init; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄhandsfreeµÄµÚÒ»´ÎÆô¶¯£»
+ È¡Öµ·¶Î§£º0µ½0xFF
+
+ ³ö³§Öµ£º
+ ÔÚÊý×éÖУ¬aud_hf[3].hf_algorithm_init=0£¬ÆäÓ඼Ϊ397¡£
+ *********************************************************************************/
+
+ SINT16 hf_algorithm_restart; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄhandsfreeµÄÖØÐÂÆô¶¯£»
+ È¡Öµ·¶Î§£º0µ½0xFF
+
+ ³ö³§Öµ£º
+ ÔÚÊý×éÖУ¬aud_hf[3].hf_algorithm_restart=0£¬ÆäÓ඼Ϊ270¡£
+ *********************************************************************************/
+
+ UINT16 step_width; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄhandsfreeµÄLMSµ÷½ÚµÄ²½³¤£»
+ È¡Öµ·¶Î§£º0µ½32767
+
+ ³ö³§Öµ£º
+ 2200
+ *********************************************************************************/
+
+ UINT16 lms_length; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄLMSÂ˲¨Æ÷ϵÊý¸öÊý£»
+ È¡Öµ·¶Î§£º2µ½400
+
+ ³ö³§Öµ£º
+ 250
+ *********************************************************************************/
+
+ UINT16 lms_offset; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄLMSÂ˲¨Æ÷ϵÊý¸öÊýµÄÆ«ÒÆ£»
+ È¡Öµ·¶Î§£º0µ½400
+
+ ³ö³§Öµ£º
+ 8
+ *********************************************************************************/
+
+ UINT16 block_length; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄLMS¿é¸üÐÂÏòÁ¿³¤¶È£»
+ È¡Öµ·¶Î§£º2£¬4£¬5£¬8
+
+ ³ö³§Öµ£º
+ 5
+ *********************************************************************************/
+
+ SINT16 rxtx_relation; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakÊäÈëÊä³ö¼ûµÄ¹Øϵ£»
+ È¡Öµ·¶Î§£º-960µ½960
+
+ ³ö³§Öµ£º
+ ÔÚÊý×éÖÐ:
+ aud_hf[0].rxtx_relation=-200£»
+ aud_hf[1].rxtx_relation=150£»
+ ÆäÓ඼Ϊ-400¡£
+
+ *********************************************************************************/
+
+ UINT16 add_atten; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄ×Ô¶¯ÔöÒæÄ£¿éµÄË¥¼õ£»
+ È¡Öµ·¶Î§£º0µ½960
+
+ ³ö³§Öµ£º
+ 0
+ *********************************************************************************/
+
+ UINT16 min_atten; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄ×Ô¶¯ÔöÒæÄ£¿éµÄ×îС˥¼õ£»
+ È¡Öµ·¶Î§£º0µ½960
+
+ ³ö³§Öµ£º
+ 0
+ *********************************************************************************/
+
+ UINT16 max_atten; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄ×Ô¶¯ÔöÒæÄ£¿éµÄ×î´óË¥¼õ£»
+ È¡Öµ·¶Î§£º0µ½960
+
+ ³ö³§Öµ£º
+ 500
+ *********************************************************************************/
+
+ UINT16 nr_sw_2; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄÔëÒôÒÖÖÆÄ£¿éµÄ×î´óË¥¼õ£»
+ È¡Öµ·¶Î§£º0µ½32767
+
+ ³ö³§Öµ£º
+ 16384
+ *********************************************************************************/
+
+ UINT16 nr_u_fak_0; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄÔëÒôÒÖÖÆÄ£¿éµÄ´ø¿í0µÄ½µÔëÒòËØ£»
+ È¡Öµ·¶Î§£º0µ½16384
+
+ ³ö³§Öµ£º
+ 16384
+ *********************************************************************************/
+
+ UINT16 nr_u_fak; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄÔëÒôÒÖÖÆÄ£¿éµÄ´ø¿í1µ½7µÄ½µÔëÒòËØ£»
+ È¡Öµ·¶Î§£º0µ½16384
+
+ ³ö³§Öµ£º
+ 16384
+ *********************************************************************************/
+}
+eep_aud_hf_type;
+
+typedef struct
+{
+ UINT16 coeffi; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄbiquadÂ˲¨Æ÷ÊÇÉÏÐÐÂ˲¨»¹ÊÇÏÂÐÐÂ˲¨£»
+ È¡Öµ·¶Î§£º0: ÉÏÐÐ
+ 1: ÏÂÐÐ
+ 2: CBuf
+
+ ³ö³§Öµ£º
+ ÉÏÐеÄÂ˲¨Æ÷(aud_uplink_biquad_filters)Ϊ: 0
+ ÏÂÐеÄÂ˲¨Æ÷(aud_downlink_biquad_filters)Ϊ: 1
+ CBuf Â˲¨Æ÷ Ϊ: 2
+ *********************************************************************************/
+
+ UINT16 a1_1; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º0µ½0xFFFF
+
+ ³ö³§Öµ£º
+ ÉÏÐÐÂ˲¨Æ÷µÄaud_uplink_biquad_filters[0].a1_1=14878£¬ÆäÓ඼Ϊ0£»
+ ÏÂÐÐÂ˲¨Æ÷µÄaud_downlink_biquad_filters[0].a1_1=35445£¬ÆäÓ඼Ϊ0£»
+ CBuf Â˲¨Æ÷µÄaud_cbuf_biquad_filters[0].a1_1=57878; ÆäÓ඼Ϊ0¡£
+ *********************************************************************************/
+
+ UINT16 b1_1; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º0µ½0xFFFF
+
+ ³ö³§Öµ£º
+ ÉÏÐÐÂ˲¨Æ÷µÄaud_uplink_biquad_filters[0].b1_1=13372£¬ÆäÓ඼Ϊ0£»
+ ÏÂÐÐÂ˲¨Æ÷µÄaud_downlink_biquad_filters[0].b1_1=35572£¬ÆäÓ඼Ϊ0£»
+ CBuf Â˲¨Æ÷µÄaud_cbuf_biquad_filters[0].b1_1=45294£¬ÆäÓ඼Ϊ0¡£
+ *********************************************************************************/
+
+ UINT16 a2_1; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º0µ½0xFFFF
+
+ ³ö³§Öµ£º
+ ÉÏÐÐÂ˲¨Æ÷µÄa2_1¶¼Îª0£»
+ ÏÂÐÐÂ˲¨Æ÷µÄaud_downlink_biquad_filters[0].a2_1=30091£¬ÆäÓ඼Ϊ0£»
+ CBuf Â˲¨Æ÷µÄaud_cbuf_biquad_filters[0].a2_1=5321£¬ÆäÓ඼Ϊ0¡£
+ *********************************************************************************/
+
+ UINT16 b2_1; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º0µ½0xFFFF
+
+ ³ö³§Öµ£º
+ ÉÏÐÐÂ˲¨Æ÷µÄb2_1¶¼Îª0£»
+ ÏÂÐÐÂ˲¨Æ÷µÄaud_downlink_biquad_filters[0].b2_1=27668£¬ÆäÓ඼Ϊ0£»
+ CBuf Â˲¨Æ÷µÄaud_cbuf_biquad_filters[0].b2_1=14049£¬ÆäÓ඼Ϊ0¡£
+ *********************************************************************************/
+
+ UINT16 a0_1; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º0µ½0xFFFF
+
+ ³ö³§Öµ£º
+ ÉÏÐÐÂ˲¨Æ÷µÄaud_uplink_biquad_filters[0].a0_1=29756£¬ÆäÓ඼Ϊ32767£»
+ ÏÂÐÐÂ˲¨Æ÷µÄaud_downlink_biquad_filters[0].a0_1=30091£¬ÆäÓ඼Ϊ32767£»
+ CBuf Â˲¨Æ÷µÄaud_cbuf_biquad_filters[0].a0_1=14315£¬ÆäÓ඼Ϊ32767¡£
+ *********************************************************************************/
+
+ UINT16 a1_2; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º0µ½0xFFFF
+
+ ³ö³§Öµ£º
+ ÉÏÐÐÂ˲¨Æ÷µÄaud_uplink_biquad_filters[0].a1_2=39151£¬ÆäÓ඼Ϊ0£»
+ ÏÂÐÐÂ˲¨Æ÷µÄaud_downlink_biquad_filters[0].a1_2=26488£¬ÆäÓ඼Ϊ0£»
+ CBuf Â˲¨Æ÷µÄa1_2¶¼Îª0¡£
+ *********************************************************************************/
+
+ UINT16 b1_2; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º0µ½0xFFFF
+
+ ³ö³§Öµ£º
+ ÉÏÐÐÂ˲¨Æ÷µÄaud_uplink_biquad_filters[0].b1_2=36192£¬ÆäÓ඼Ϊ0£»
+ ÏÂÐÐÂ˲¨Æ÷µÄaud_downlink_biquad_filters[0].b1_2=24996£¬ÆäÓ඼Ϊ0£»
+ CBuf Â˲¨Æ÷µÄb1_2¶¼Îª0¡£
+ *********************************************************************************/
+
+ UINT16 a2_2; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º0µ½0xFFFF
+
+ ³ö³§Öµ£º
+ ÉÏÐÐÂ˲¨Æ÷µÄaud_uplink_biquad_filters[0].a2_2=26385£¬ÆäÓ඼Ϊ0£»
+ ÏÂÐÐÂ˲¨Æ÷µÄaud_downlink_biquad_filters[0].a2_2=26488£¬ÆäÓ඼Ϊ0£»
+ CBuf Â˲¨Æ÷µÄa2_2¶¼Îª0¡£
+ *********************************************************************************/
+
+ UINT16 b2_2; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º0µ½0xFFFF
+
+ ³ö³§Öµ£º
+ ÉÏÐÐÂ˲¨Æ÷µÄaud_uplink_biquad_filters[0].b2_2=26962£¬ÆäÓ඼Ϊ0£»
+ ÏÂÐÐÂ˲¨Æ÷µÄaud_downlink_biquad_filters[0].b2_2=23168£¬ÆäÓ඼Ϊ0£»
+ CBuf Â˲¨Æ÷µÄb2_2¶¼Îª0¡£
+ *********************************************************************************/
+
+ UINT16 a0_2; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º0µ½0xFFFF
+
+ ³ö³§Öµ£º
+ ÉÏÐÐÂ˲¨Æ÷µÄaud_uplink_biquad_filters[0].a0_2=26385£¬ÆäÓ඼Ϊ32767£»
+ ÏÂÐÐÂ˲¨Æ÷µÄaud_downlink_biquad_filters[0].a0_2=26488£¬ÆäÓ඼Ϊ32767£»
+ CBuf Â˲¨Æ÷µÄa0_2¶¼Îª32767¡£
+ *********************************************************************************/
+}
+eep_aud_biquad_filters_type;
+
+
+typedef struct
+{
+ eep_aud_downlink_gain_cells_type downlink_gain_cells; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÏÂÐеÄÔöÒ棻
+ È¡Öµ·¶Î§£º¼ûeep_aud_downlink_gain_cells_type½á¹¹Ìå
+
+ ³ö³§Öµ£º
+ ¼ûeep_aud_downlink_gain_cells_type½á¹¹Ìå
+ *********************************************************************************/
+
+ #if 0
+ int16 biquad_filter_dl_index_8kHz; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃÏÂÐÐ8KHZ biquad_filterµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½20
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,6,7,10,11,12,13,14,15,16,17,18,19,20,23,24,25,26,27,28ʱ:
+ aud_audio_downlink_parms[n].biquad_filter_dl_index_8kHz=0;
+ µ±n =5,8,9,21,22,ʱ:
+ aud_audio_downlink_parms[n].biquad_filter_dl_index_8kHz=1;
+ *********************************************************************************/
+ #endif
+ eep_aud_biquad_filters_type biquad_filter_dl_8kHz;
+
+ #if 0
+ int16 biquad_filter_dl_index_16kHz; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃÏÂÐÐ16KHZ biquad_filterµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½20
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,6,7,10,11,12,13,14,15,16,17,18,19,20,23,24,25,26,27,28ʱ:
+ aud_audio_downlink_parms[n].biquad_filter_dl_index_16kHz=0;
+ µ±n =5,8,9,21,22,ʱ:
+ aud_audio_downlink_parms[n].biquad_filter_dl_index_16kHz=1;
+ *********************************************************************************/
+ #endif
+ eep_aud_biquad_filters_type biquad_filter_dl_16kHz;
+
+ #if 0
+ int16 biquad_filter_cbuf_index; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃCBUF biquad_filterµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½10
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28ʱ:
+ aud_audio_downlink_parms[n].biquad_filter_cbuf_index=0;
+ µ±n =5ʱ:
+ aud_audio_downlink_parms[n].biquad_filter_cbuf_index=1;
+ *********************************************************************************/
+ #endif
+ eep_aud_biquad_filters_type biquad_filter_cbuf;
+
+ #if 0
+ int16 fir_filter_dl_index; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖà teakÏÂÐеÄfir_filterµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½5
+
+ ³ö³§Öµ£º
+ 0
+ *********************************************************************************/
+
+ int16 fir_filter_cbuf_index; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖà teakµÄCBUFµÄ fir_filterµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½5
+
+ ³ö³§Öµ£º
+ 0
+ *********************************************************************************/
+
+ int16 dl_nr_index; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖà teakµÄÏÂÐеÄÔëÒôÒÖÖƵÄͨµÀµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½5
+
+ ³ö³§Öµ£º
+ 0
+ *********************************************************************************/
+
+ #endif
+ UINT16 side_tone_fact; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖà teakµÄside_toneµÄÖµ£»
+ È¡Öµ·¶Î§£º0µ½0x7FFF
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,4,6,7,8,9,10,11,12,13,16,17,18,19,24,25,26,27,28ʱ:
+ aud_audio_downlink_parms[n].side_tone_fact=500;
+ µ±n =3,5,14,15,20,23,ʱ:
+ aud_audio_downlink_parms[n].side_tone_fact=0;
+ µ±n =21,22,ʱ:
+ aud_audio_downlink_parms[n].side_tone_fact=5787;
+ *********************************************************************************/
+
+ UINT16 side_tone_fact_use; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄside_toneµÄÖµÊÇ·ñÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,5,6,7,8,9,10,11,12,13,16,17,18,19,20,21,22,24,25,26,27,28ʱ:
+ aud_audio_downlink_parms[n].side_tone_fact_use=1;
+ µ±n =14,15,23ʱ:
+ aud_audio_downlink_parms[n].side_tone_fact_use=0;
+ *********************************************************************************/
+}
+eep_audio_downlink_parms_type; /* 14*2 bytes */
+
+typedef struct
+{
+ UINT16 scal_mic; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄscal_micÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x1FFF£»
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n = 0,1,4,6,7,9,13,18,19,20,21ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.scal_mic=6143;
+ µ±n = 2,3,5,12,14ʱ:
+ aud_audio_uplink_parms[2].uplink_gain_cells.scal_mic=8192;
+ µ±n = 10,11ʱ:
+ aud_audio_uplink_parms[2].uplink_gain_cells.scal_mic=8191;
+ µ±n = 8,15,16,17ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.scal_mic=0;
+ *********************************************************************************/
+
+ UINT16 scal_mic_use; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄscal_micÔöÒæÊÇ·ñÊÇÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,6,7,8,9,10,11,13,14,18,19,20,21ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.scal_mic_use=1;
+ µ±n =5,12,15,16,17ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.scal_mic_use=0;
+ *********************************************************************************/
+
+ UINT16 lambda0; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄlambda0ÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x7FFF£»
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,5,6,7,9,12,13,14,19,20,21ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.lambda0=32767;
+ µ±n =8,10,11,15,16,17,18ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.lambda0=0;
+ *********************************************************************************/
+
+ UINT16 lambda0_use; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄlambda0ÔöÒæÊÇ·ñÊÇÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,6,7,8,9,13,19,20,21ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.lambda0_use=1;
+ µ±n =5,10,11,12,14,15,16,17,18ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.lambda0_use=0;
+ *********************************************************************************/
+
+ UINT16 gamma0; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄgamma0ÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x7FFF£»
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,5,6,7,8,9,12,13,14,19,20,21ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.gamma0=32767;
+ µ±n =10,11,15,16,17,18ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.gamma0=0;
+ *********************************************************************************/
+
+ UINT16 gamma0_use; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄgamma0ÔöÒæÊÇ·ñÊÇÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =5,8,10,11,12,14,15,16,17,18ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.gamma0_use=0
+ µ±n =0,1,2,3,4,6,7,9,13,19,20,21ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.gamma0_use=1
+ *********************************************************************************/
+
+ UINT16 scal_afe; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄscal_afeÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x1FFF£»
+ ³ö³§Öµ£º
+ Êý×éÖУ¬³ýÁËaud_audio_uplink_parms[5].uplink_gain_cells.scal_afe=8192,
+ ÆäÓ඼Ϊ0.
+ *********************************************************************************/
+
+ UINT16 scal_afe_use; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄscal_afeÔöÒæÊÇ·ñÊÇÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ Êý×éÖУ¬³ýÁËaud_audio_uplink_parms[5].uplink_gain_cells.scal_afe_use=1,
+ ÆäÓàaud_audio_uplink_parms[n].uplink_gain_cells.scal_afe_use=0.
+ *********************************************************************************/
+
+ UINT16 scal_mic2; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄscal_mic2ÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x1FFF£»
+ ³ö³§Öµ£º
+ Êý×éÖÐ,aud_audio_uplink_parms[5].uplink_gain_cells.scal_mic2=8192;
+ ÆäÓ඼Ϊ0.
+ *********************************************************************************/
+
+ UINT16 scal_mic2_use; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄscal_mic2ÔöÒæÊÇ·ñÊÇÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,3,4,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.scal_mic2_use=0;
+ µ±n =5ʱ:
+ aud_audio_uplink_parms[n].uplink_gain_cells.scal_mic2_use=1;
+ *********************************************************************************/
+
+ UINT16 afe_tone; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄafe_toneÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x3FFF£»
+ ³ö³§Öµ£º
+ Êý×éÖÐ,aud_audio_uplink_parms[5].uplink_gain_cells.afe_tone=16384;
+ ÆäÓ඼Ϊ0.
+ *********************************************************************************/
+
+ UINT16 afe_tone_use; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄafe_toneÔöÒæÊÇ·ñÊÇÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,aud_audio_uplink_parms[5].uplink_gain_cells.afe_tone_use=1;
+ ÆäÓ඼Ϊ0.
+ *********************************************************************************/
+
+ UINT16 mix_pcmrec; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеĻìºÏPCMÒôÀÖµÄmix_pcmrecÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x3FFF£»
+ ³ö³§Öµ£º
+ Êý×éÖÐ,aud_audio_uplink_parms[12].uplink_gain_cells.mix_pcmrec=1;
+ ÆäÓ඼Ϊ0.
+ *********************************************************************************/
+}
+eep_aud_uplink_gain_cells_type;
+
+
+typedef struct
+{
+ eep_aud_uplink_gain_cells_type uplink_gain_cells; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄÔöÒ棻
+ È¡Öµ·¶Î§£º¼ûeep_aud_uplink_gain_cells_type½á¹¹Ìå
+
+ ³ö³§Öµ£º
+ ¼ûeep_aud_uplink_gain_cells_type½á¹¹Ìå
+ *********************************************************************************/
+
+ #if 0
+ int16 biquad_filter_ul_index_8kHz; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃÉÏÐÐ8KHZ biquad_filterµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½30
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,4,5,6,7,8,9,12,13,14,15,16,17,18,19,20,21ʱ:
+ aud_audio_uplink_parms[n].biquad_filter_ul_index_8kHz=0;
+ µ±n =3,10,11ʱ:
+ aud_audio_uplink_parms[n].biquad_filter_ul_index_8kHz=1;
+ *********************************************************************************/
+ #endif
+ eep_aud_biquad_filters_type biquad_filter_ul_8kHz;
+
+ #if 0
+ int16 biquad_filter_ul_index_16kHz; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃÉÏÐÐ16KHZ biquad_filterµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½30
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,4,5,6,7,8,9,12,13,14,15,16,17,18,19,20,21ʱ:
+ aud_audio_uplink_parms[n].biquad_filter_ul_index_16kHz=0;
+ µ±n =3,10,11ʱ:
+ aud_audio_uplink_parms[n].biquad_filter_ul_index_16kHz=1;
+ *********************************************************************************/
+ #endif
+ eep_aud_biquad_filters_type biquad_filter_ul_16kHz;
+
+ #if 0
+ int16 biquad_filter_ul_index_48kHz; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃÉÏÐÐ48KHZ biquad_filterµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½30
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,4,5,6,7,8,9,12,13,14,15,16,17,18,19,20,21ʱ:
+ aud_audio_uplink_parms[n].biquad_filter_ul_index_48kHz=0;
+ µ±n =3,10,11ʱ:
+ aud_audio_uplink_parms[n].biquad_filter_ul_index_48kHz=1;
+ *********************************************************************************/
+ #endif
+ eep_aud_biquad_filters_type biquad_filter_ul_48kHz;
+
+ #if 0
+ int16 fir_filter_ul_index; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖà teakÉÏÐеÄfir_filterµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½5
+
+ ³ö³§Öµ£º
+ 0
+ *********************************************************************************/
+ #endif
+
+ #if 0
+ int16 hf_index; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖà teakµÄhandsfreeµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½8
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,6,8,9,20,21ʱ:
+ aud_audio_uplink_parms[n].hf_index=0;
+ µ±n =1,2,4,5,10,11,12,13,14,15,16,17,18,19ʱ:
+ aud_audio_uplink_parms[n].hf_index=1;
+ µ±n =7ʱ:
+ aud_audio_uplink_parms[n].hf_index=2;
+ µ±n =3ʱ:
+ aud_audio_uplink_parms[n].hf_index=3;
+ *********************************************************************************/
+ #endif
+ eep_aud_hf_type hf;
+
+ #if 0
+ int16 asp_ul_index; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖà teakµÄÉÏÐеÄASPµÄË÷ÒýÖµ£»
+ È¡Öµ·¶Î§£º0µ½5
+
+ ³ö³§Öµ£º
+ 0
+ *********************************************************************************/
+ #endif
+
+ UINT16 mic_gain; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖà teakµÄÉÏÐеÄmic_gainÔöÒ棻
+ È¡Öµ·¶Î§£º0x0µ½0x10
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,4,7,12,13,14,18,20,21ʱ:
+ aud_audio_uplink_parms[n].mic_gain=10;
+ µ±n =2,3,ʱ:
+ aud_audio_uplink_parms[n].mic_gain=6;
+ µ±n =5,ʱ:
+ aud_audio_uplink_parms[n].mic_gain=2;
+ µ±n =6,19ʱ:
+ aud_audio_uplink_parms[n].mic_gain=14;
+ µ±n =8,9,ʱ:
+ aud_audio_uplink_parms[n].mic_gain=5;
+ µ±n =10,11,15,16,17,ʱ:
+ aud_audio_uplink_parms[n].mic_gain=0;
+ *********************************************************************************/
+
+ UINT16 mic_gain_use; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÏÂÐеÄmic_gainÔöÒæÊÇ·ñÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ Êý×éÖÐ,µ±n =0,1,2,4,5,6,7,9,10,11,13,14,18,19,20,21ʱ:
+ aud_audio_uplink_parms[n].mic_gain_use=1;
+ µ±n =8,12,15,16,17ʱ:
+ aud_audio_uplink_parms[n].mic_gain_use=0;
+ *********************************************************************************/
+
+ #if 0
+ UINT16 tx_dither; /********************************************************************************
+ ¹¦ÄÜ£º AFEµÄÏà¹ØÉèÖã»
+ È¡Öµ·¶Î§£ºnot used
+
+
+ ³ö³§Öµ£º
+ 0
+ *********************************************************************************/
+
+ UINT16 tx_dither_use; /********************************************************************************
+ ¹¦ÄÜ£º AFEµÄÏà¹ØÉèÖÃÊÇ·ñÓÉNV²ÎÊýÉèÖã»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ÓÃ
+ 1: ʹÓÃNV²ÎÊý
+
+ ³ö³§Öµ£º
+ 0
+ *********************************************************************************/
+ #endif
+}
+eep_audio_uplink_parms_type; /* 23*2 bytes */
+
+typedef struct
+{
+ unsigned char audio_parms_from_eep_used; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÊÇ·ñʹÓÃNV²ÎÊýµÄÖµ£»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ ÓÃ(false)
+ 1: ʹÓã»(true)
+ ³ö³§Öµ£º
+ 1
+ *********************************************************************************/
+
+ #if 0
+ unsigned char aud_use_filters_ul; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÊÇ·ñʹÓÃÓïÒôͨ·µÄÉÏÐÐÂ˲¨Æ÷£»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ ÓÃ(none)
+ 1: ʹÓÃfirÂ˲¨Æ÷ (fir)
+ 4: ʹÓÃbiquadÂ˲¨Æ÷ (biquad)
+ 5: ʹÓÃfir+biquadÂ˲¨Æ÷(fir+biquad)
+ ³ö³§Öµ£º
+ 1
+ *********************************************************************************/
+
+
+ unsigned char aud_use_filters_dl; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÊÇ·ñʹÓÃÓïÒôͨ·µÄÏÂÐÐÂ˲¨Æ÷£»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ ÓÃ(none)
+ 1: ʹÓÃfirÂ˲¨Æ÷ (fir)
+ 4: ʹÓÃbiquadÂ˲¨Æ÷ (biquad)
+ 5: ʹÓÃfir+biquadÂ˲¨Æ÷(fir+biquad)
+ ³ö³§Öµ£º
+ 1
+ *********************************************************************************/
+
+ unsigned char aud_use_filters_cbuf; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÊÇ·ñʹÓÃcircular buffer 48KHZͨ·ÉϵÄÂ˲¨Æ÷£»
+ È¡Öµ·¶Î§£º0: ²»Ê¹ ÓÃ(none)
+ 1: ʹÓÃfirÂ˲¨Æ÷ (fir)
+ 4: ʹÓÃbiquadÂ˲¨Æ÷ (biquad)
+ 5: ʹÓÃfir+biquadÂ˲¨Æ÷(fir+biquad)
+ ³ö³§Öµ£º
+ 1
+ *********************************************************************************/
+
+ #endif
+ #if 0
+ eep_aud_biquad_filters_type aud_uplink_biquad_filters[EEP_AUD_BIQUAD_FILTERS_UL]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º
+ ¼ûeep_aud_biquad_filters_type½á¹¹Ì壻
+ ³ö³§Öµ£º
+ ¼ûeep_aud_biquad_filters_type½á¹¹Ì壻
+ *********************************************************************************/
+
+
+ eep_aud_biquad_filters_type aud_downlink_biquad_filters[EEP_AUD_BIQUAD_FILTERS_DL]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÏÂÐеÄbiquadÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º
+ ¼ûeep_aud_biquad_filters_type½á¹¹Ì壻
+ ³ö³§Öµ£º
+ ¼ûeep_aud_biquad_filters_type½á¹¹Ì壻
+ *********************************************************************************/
+
+ eep_aud_biquad_filters_type aud_cbuf_biquad_filters[EEP_AUD_BIQUAD_FILTERS_CBUF]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak µÄcircular buffer 48KHZͨ·ÉϵÄÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º
+ ¼ûeep_aud_biquad_filters_type½á¹¹Ì壻
+ ³ö³§Öµ£º
+ ¼ûeep_aud_biquad_filters_type½á¹¹Ì壻
+ *********************************************************************************/
+
+ #endif
+ #if 0
+ eep_aud_fir_filter_type aud_uplink_fir_filters[EEP_AUD_FIR_FILTERS_UL]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÉÏÐеÄfirÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º
+ ¼ûeep_aud_fir_filter_type½á¹¹Ì壻
+ ³ö³§Öµ£º
+ ¼ûeep_aud_fir_filter_type½á¹¹Ì壻
+ *********************************************************************************/
+
+ eep_aud_fir_filter_type aud_downlink_fir_filters[EEP_AUD_FIR_FILTERS_DL]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÏÂÐеÄfirÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º
+ ¼ûeep_aud_fir_filter_type½á¹¹Ì壻
+ ³ö³§Öµ£º
+ ¼ûeep_aud_fir_filter_type½á¹¹Ì壻
+ *********************************************************************************/
+
+
+ eep_aud_fir_filter_type aud_cbuf_fir_filters[EEP_AUD_FIR_FILTERS_CBUF]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄcircular buffer 48KHZͨ·ÉϵÄÂ˲¨Æ÷²ÎÊý£»
+ È¡Öµ·¶Î§£º
+ ¼ûeep_aud_fir_filter_type½á¹¹Ì壻
+ ³ö³§Öµ£º
+ ¼ûeep_aud_fir_filter_type½á¹¹Ì壻
+ *********************************************************************************/
+
+ eep_aud_hf_type aud_hf[EEP_AUD_HF]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄhandsfreeµÄ²ÎÊý£»
+ È¡Öµ·¶Î§£º
+ ¼ûeep_aud_hf_type½á¹¹Ì壻
+ ³ö³§Öµ£º
+ ¼ûeep_aud_hf_type½á¹¹Ì壻
+ *********************************************************************************/
+
+ #endif
+ #if 0
+ eep_aud_asp_ul_type aud_asp_ul[EEP_AUD_ASP_UL]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄÉÏÐÐͨµÀÉÏÕðµ´±£»¤µÄ²ÎÊý£»
+ È¡Öµ·¶Î§£º
+ ¼ûeep_aud_asp_ul_type½á¹¹Ì壻
+ ³ö³§Öµ£º
+ ¼ûeep_aud_asp_ul_type½á¹¹Ì壻
+ *********************************************************************************/
+
+ eep_aud_dl_nr_type aud_dl_nr[EEP_AUD_DL_NR]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄÏÂÐÐͨµÀÉϽµµÍÔëÒôµÄ²ÎÊý£»
+ È¡Öµ·¶Î§£º
+ ¼ûeep_aud_dl_nr_type½á¹¹Ì壻
+ ³ö³§Öµ£º
+ ¼ûeep_aud_dl_nr_type½á¹¹Ì壻
+ *********************************************************************************/
+
+ #endif
+ eep_audio_uplink_parms_type aud_audio_uplink_parms[EEP_AUD_UPLINK_PATHS]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄÉÏÐÐÓïÒôͨ·ÉϵIJÎÊý£»
+ È¡Öµ·¶Î§£º
+ ¼ûeep_audio_uplink_parms_type½á¹¹Ì壻
+ ³ö³§Öµ£º
+ ¼ûeep_audio_uplink_parms_type½á¹¹Ì壻
+ *********************************************************************************/
+
+ eep_audio_downlink_parms_type aud_audio_downlink_parms[EEP_AUD_DOWNLINK_PATHS]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄÏÂÐÐÓïÒôͨ·ÉϵIJÎÊý£»
+ È¡Öµ·¶Î§£º
+ ¼ûeep_audio_downlink_parms_type½á¹¹Ì壻
+ ³ö³§Öµ£º
+ ¼ûeep_audio_downlink_parms_type½á¹¹Ì壻
+ *********************************************************************************/
+
+ #if 0
+ unsigned char fill[2]; /********************************************************************************
+ ¹¦ÄÜ£º Ìî³äλ£»
+ È¡Öµ·¶Î§£º0 µ½ 255
+
+ ³ö³§Öµ£º
+ 255
+ *********************************************************************************/
+ #endif
+}
+eep_aud_path_data_type;
+
+typedef struct
+{
+ SINT16 mix_afe; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖûìºÏµ½AFEµÄÒôƵ×ÊÔ´ÔöÒæÖµ£»
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x3FFF£»
+ ³ö³§Öµ£º
+ aud_cbuf_mix_parms[5].mix_afe=0,ÆäÓ඼Ϊ32767¡£
+ *********************************************************************************/
+
+ SINT16 mix_i2s1; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖûìºÏµ½I2S1µÄÒôƵ×ÊÔ´ÔöÒæÖµ£»
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x3FFF£»
+ ³ö³§Öµ£º
+ aud_cbuf_mix_parms[5].mix_i2s1=0£¬ÆäÓ඼Ϊ32767¡£
+ *********************************************************************************/
+}
+eepaud_static_cbuf_mix_parms_type;
+
+typedef SINT16 eep_aud_region_type;
+
+/********************************************************************************
+¹¦ÄÜ£º ÉèÖÃteakµÄÉÏÐÐÓïÒôͨµÀµÄÔöÒ棻
+È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x1FFF£»
+
+³ö³§Öµ£º
+ ÔÚ³ÌÐòÖÐΪһ¸ö32λµÄÊý×é
+ ÔÚÊý×é[0] µ½ [31] ÖУ¬³ýÁË[3]Ϊ0x5000£¬ÆäÓ඼Ϊ0x2000
+*********************************************************************************/
+typedef struct
+{
+ SINT16 scal_in;
+}
+eepaud_static_scal_in_parms_type;
+
+/********************************************************************************
+¹¦ÄÜ£º ÉèÖÃteakµÄÏÂÐÐÓïÒôͨµÀµÄÔöÒ棻
+È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x1FFF£»
+
+³ö³§Öµ£º
+ 0x2000
+*********************************************************************************/
+typedef struct
+{
+ SINT16 scal_out;
+}
+eepaud_static_scal_out_parms_type;
+
+/*[Begin] [lvwenhua-2010/9/16]*/
+typedef struct
+{
+ SINT16 scal_i2s1;
+}
+eepaud_static_scal_i2s1_parms_type;
+
+typedef struct
+{
+ SINT16 scal_rec;
+}
+eepaud_static_scal_rec_parms_type;
+/*[End] [lvwenhua-2010/9/16]*/
+
+typedef struct
+{
+ UINT16 gain[EEP_VOICE_OUTPUT_VOL_LEVELS];
+} eep_voice_volume_config_type;
+
+typedef struct
+{
+ UINT16 gain[EEP_MIDI_OUTPUT_VOL_LEVELS];
+} eep_midi_volume_config_type;
+
+typedef struct
+{
+ UINT16 gain[EEP_TONE_OUTPUT_VOL_LEVELS];
+} eep_tone_volume_config_type;
+
+#ifdef _USE_CODEC_TLV3212
+typedef enum
+{
+ PMIC_MIC_GAIN_MINUS_12DB = 0,
+ PMIC_MIC_GAIN_MINUS_9DB,
+ PMIC_MIC_GAIN_MINUS_6DB,
+ PMIC_MIC_GAIN_MINUS_3DB,
+ PMIC_MIC_GAIN_0DB,
+ PMIC_MIC_GAIN_PLUS_3DB,
+ PMIC_MIC_GAIN_PLUS_6DB,
+ PMIC_MIC_GAIN_PLUS_9DB,
+ PMIC_MIC_GAIN_PLUS_12DB,
+ PMIC_MIC_GAIN_PLUS_15DB,
+ PMIC_MIC_GAIN_PLUS_18DB,
+ PMIC_MIC_GAIN_MAX
+
+} EEP_PMIC_AUDIO_MIC_GAIN;
+
+typedef enum
+{
+ PMIC_OUTPGA_GAIN_PLUS_24DB = 0,
+ PMIC_OUTPGA_GAIN_PLUS_21DB,
+ PMIC_OUTPGA_GAIN_PLUS_18DB,
+ PMIC_OUTPGA_GAIN_PLUS_15DB,
+ PMIC_OUTPGA_GAIN_PLUS_12DB,
+ PMIC_OUTPGA_GAIN_PLUS_9DB,
+ PMIC_OUTPGA_GAIN_PLUS_6DB,
+ PMIC_OUTPGA_GAIN_PLUS_3DB,
+ PMIC_OUTPGA_GAIN_0DB,
+ PMIC_OUTPGA_GAIN_MINUS_3DB,
+ PMIC_OUTPGA_GAIN_MINUS_6DB,
+ PMIC_OUTPGA_GAIN_MINUS_9DB,
+ PMIC_OUTPGA_GAIN_MINUS_12DB,
+ PMIC_OUTPGA_GAIN_MINUS_15DB,
+ PMIC_OUTPGA_GAIN_MINUS_18DB,
+ PMIC_OUTPGA_GAIN_MINUS_21DB,
+ PMIC_OUTPGA_GAIN_MINUS_24DB,
+ PMIC_OUTPGA_GAIN_MINUS_27DB,
+ PMIC_OUTPGA_GAIN_MINUS_30DB,
+ PMIC_OUTPGA_GAIN_MINUS_33DB,
+ PMIC_OUTPGA_GAIN_MINUS_36DB,
+ PMIC_OUTPGA_GAIN_MINUS_39DB,
+ PMIC_OUTPGA_GAIN_MINUS_42DB,
+ PMIC_OUTPGA_GAIN_MINUS_45DB,
+ PMIC_OUTPGA_GAIN_MINUS_48DB,
+ PMIC_OUTPGA_GAIN_MINUS_51DB,
+ PMIC_OUTPGA_GAIN_MINUS_54DB,
+ PMIC_OUTPGA_GAIN_MINUS_57DB,
+ PMIC_OUTPGA_GAIN_MINUS_60DB,
+ PMIC_OUTPGA_GAIN_MINUS_63DB,
+ PMIC_OUTPGA_GAIN_MAX
+
+} EEP_PMIC_AUDIO_OUTPUT_PGA_GAIN;
+/*added by miaolin 20130805*/
+
+#else
+
+typedef enum
+{
+ PMIC_MIC_GAIN_MINUS_12DB = 0,
+ PMIC_MIC_GAIN_MINUS_9DB,
+ PMIC_MIC_GAIN_MINUS_6DB,
+ PMIC_MIC_GAIN_MINUS_3DB,
+ PMIC_MIC_GAIN_0DB,
+ PMIC_MIC_GAIN_PLUS_3DB,
+ PMIC_MIC_GAIN_PLUS_6DB,
+ PMIC_MIC_GAIN_PLUS_9DB,
+ PMIC_MIC_GAIN_PLUS_12DB,
+ PMIC_MIC_GAIN_PLUS_15DB,
+ PMIC_MIC_GAIN_PLUS_18DB,
+ PMIC_MIC_GAIN_MAX
+
+} EEP_PMIC_AUDIO_MIC_GAIN;
+
+typedef enum
+{
+ PMIC_OUTPGA_GAIN_PLUS_24DB = 0,
+ PMIC_OUTPGA_GAIN_PLUS_21DB,
+ PMIC_OUTPGA_GAIN_PLUS_18DB,
+ PMIC_OUTPGA_GAIN_PLUS_15DB,
+ PMIC_OUTPGA_GAIN_PLUS_12DB,
+ PMIC_OUTPGA_GAIN_PLUS_9DB,
+ PMIC_OUTPGA_GAIN_PLUS_6DB,
+ PMIC_OUTPGA_GAIN_PLUS_3DB,
+ PMIC_OUTPGA_GAIN_0DB,
+ PMIC_OUTPGA_GAIN_MINUS_3DB,
+ PMIC_OUTPGA_GAIN_MINUS_6DB,
+ PMIC_OUTPGA_GAIN_MINUS_9DB,
+ PMIC_OUTPGA_GAIN_MINUS_12DB,
+ PMIC_OUTPGA_GAIN_MINUS_15DB,
+ PMIC_OUTPGA_GAIN_MINUS_18DB,
+ PMIC_OUTPGA_GAIN_MINUS_21DB,
+ PMIC_OUTPGA_GAIN_MINUS_24DB,
+ PMIC_OUTPGA_GAIN_MINUS_27DB,
+ PMIC_OUTPGA_GAIN_MINUS_30DB,
+ PMIC_OUTPGA_GAIN_MINUS_33DB,
+ PMIC_OUTPGA_GAIN_MINUS_36DB,
+ PMIC_OUTPGA_GAIN_MINUS_39DB,
+ PMIC_OUTPGA_GAIN_MINUS_42DB,
+ PMIC_OUTPGA_GAIN_MINUS_45DB,
+ PMIC_OUTPGA_GAIN_MINUS_48DB,
+ PMIC_OUTPGA_GAIN_MINUS_51DB,
+ PMIC_OUTPGA_GAIN_MINUS_54DB,
+ PMIC_OUTPGA_GAIN_MINUS_57DB,
+ PMIC_OUTPGA_GAIN_MINUS_60DB,
+ PMIC_OUTPGA_GAIN_MINUS_63DB,
+ PMIC_OUTPGA_GAIN_MAX
+
+} EEP_PMIC_AUDIO_OUTPUT_PGA_GAIN;
+#endif
+
+#ifndef _USE_DATACARD
+typedef struct
+{
+ EEP_PMIC_AUDIO_OUTPUT_PGA_GAIN gain[EEP_PCM_OUTPUT_VOL_LEVELS];
+} eep_pcm_volume_config_type;
+#endif
+
+
+typedef struct
+{
+ eep_voice_volume_config_type voice_vol_gain_config[EEP_CODEC_DOWNLINK_PATHS];
+ eep_midi_volume_config_type midi_vol_gain_config[EEP_CODEC_DOWNLINK_PATHS];
+ eep_tone_volume_config_type tone_vol_gain_config[EEP_CODEC_DOWNLINK_PATHS];
+#ifndef _USE_DATACARD
+ eep_pcm_volume_config_type pcm_vol_gain_config[EEP_CODEC_DOWNLINK_PATHS];
+#endif
+}aud_eep_volume_config_type;
+
+
+#ifndef _USE_DATACARD
+typedef struct
+{
+ EEP_PMIC_AUDIO_MIC_GAIN pga_tx;
+}aud_pmic_eep_pga_tx_type;
+
+typedef struct
+{
+ EEP_PMIC_AUDIO_OUTPUT_PGA_GAIN pga_rx;
+}aud_pmic_eep_pga_rx_type;
+/*[End] [lvwenhua-2010/9/16]*/
+#endif
+
+typedef volatile struct _aud_eep_static_type
+{
+ eep_aud_path_data_type aud_path_data; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÓïÒôÉÏÏÂÐÐͨ·ÉϵÄÔöÒæÂ˲¨²ÎÊýµÈ£»
+ È¡Öµ·¶Î§£º¸Ã½á¹¹ÌåµÄÈ¡Öµ·¶Î§¼ûeep_aud_path_data_type½á¹¹Ì壻
+
+ ³ö³§Öµ£º
+ ¼ûeep_aud_path_data_type½á¹¹Ì壻
+ *********************************************************************************/
+
+ #if 0
+ eep_external_audio_type external_audio; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteak ÊÇ·ñʹÓÃÍⲿÒôƵÉ豸£»
+ È¡Öµ·¶Î§£º0: ʹÄÜ
+ 1: ²»Ê¹ÄÜ£»
+ ³ö³§Öµ£º
+ 0
+ *********************************************************************************/
+ #endif
+
+ eepaud_static_cbuf_mix_parms_type aud_cbuf_mix_parms[AUDIO_PATHS]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖûìºÏµ½I2S1ºÍAFEµÄÒôƵ×ÊÔ´ÔöÒæÖµ£»
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x3FFF£»
+ ³ö³§Öµ£º
+ ¼ûeepaud_static_cbuf_mix_parms_type½á¹¹Ì壻
+ *********************************************************************************/
+
+
+ #if 0
+ eep_aud_fm_radio_type aud_fm_radio; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄÊÕÒô»úµÄÉèÖ㬷½°¸ÖÐûÓÐʹÓøù¦ÄÜ£¬
+ Õâ¸ö²ÎÊýÔڽṹÌåÖпÉÒÔÈ¥µô£»
+ È¡Öµ·¶Î§£º¸Ã½á¹¹ÌåµÄÈ¡Öµ·¶Î§¼ûeep_aud_fm_radio_type½á¹¹Ìå¡£
+
+ ³ö³§Öµ£º
+ ¼ûeep_aud_fm_radio_type½á¹¹Ìå¡£
+ *********************************************************************************/
+ #endif
+
+ eep_aud_region_type aud_region; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄʹÓÃÇøÓò£»
+ È¡Öµ·¶Î§£º0: EEP_AUD_CEPT
+ 1: EEP_AUD_ANSI
+ 2: EEP_AUD_JAPAN£»
+ ³ö³§Öµ£º
+ 0
+ *********************************************************************************/
+
+ eepaud_static_scal_in_parms_type aud_scal_in_parms[EEP_AUD_UPLINK_PATHS]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄÉÏÐÐÓïÒôͨµÀµÄÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ0x1FFF£»
+
+ ³ö³§Öµ£º
+ ¼ûeepaud_static_scal_in_parms_type½á¹¹Ìå¡£
+ *********************************************************************************/
+
+ eepaud_static_scal_out_parms_type aud_scal_out_parms[EEP_AUD_DOWNLINK_PATHS]; /********************************************************************************
+ ¹¦ÄÜ£º ÉèÖÃteakµÄÏÂÐÐÓïÒôͨµÀµÄÔöÒ棻
+ È¡Öµ·¶Î§£º0 µ½0x7FFF,
+ 0 db ֵΪ 0x1FFF£»
+
+ ³ö³§Öµ£º
+ ¼ûeepaud_static_scal_out_parms_type½á¹¹Ìå¡£
+ *********************************************************************************/
+ /*[Begin] [lvwenhua-2010/9/16]*/
+ eepaud_static_scal_i2s1_parms_type aud_scal_i2s1_parms[EEP_AUD_DOWNLINK_PATHS];
+ eepaud_static_scal_rec_parms_type aud_scal_rec_parms[EEP_AUD_DOWNLINK_PATHS];
+ /*[End] [lvwenhua-2010/9/16]*/
+
+#ifndef _USE_DATACARD
+ /*[Begin] [lvwenhua-2010/9/16]*/
+ aud_pmic_eep_pga_tx_type pmic_pga_tx_parms[EEP_AUD_UPLINK_PATHS];
+ aud_pmic_eep_pga_rx_type pmic_pga_rx_parms[EEP_AUD_DOWNLINK_PATHS];
+#endif
+
+ aud_eep_volume_config_type aud_volume_config;
+ /*[End] [lvwenhua-2010/9/16]*/
+}
+aud_eep_static_type;
+
+#endif /* _AUD_NV_H */
+
+
diff --git a/cp/ps/driver/inc/misc/drvs_audiomanager.h b/cp/ps/driver/inc/misc/drvs_audiomanager.h
new file mode 100644
index 0000000..3180831
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_audiomanager.h
@@ -0,0 +1,64 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: drvs_audiomanager.h
+* File Mark:
+* Description: audio manager interface declaration.
+* Others:
+* Version: v1.0
+* Author: lvwenhua
+* Date: 2016-07-07
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+
+* History 2:
+**********************************************************************/
+#ifndef _DRVS_AUDIOM_H
+#define _DRVS_AUDIOM_H
+
+
+/*************************************************************************
+ * Include files *
+ *************************************************************************/
+#include "drvs_general.h"
+
+/*************************************************************************
+ * Macro *
+ *************************************************************************/
+
+
+/**************************************************************************
+ * Types *
+ **************************************************************************/
+
+typedef enum {
+ AUDIO_MANAGER_RESOURCE_VOICE=0, /* 0 */
+ AUDIO_MANAGER_RESOURCE_VOLTE, /* 1*/
+ AUDIO_MANAGER_RESOURCE_TONE_IN_SPEECH, /* 2 */
+ AUDIO_MANAGER_RESOURCE_AUDIO, /* 3*/
+ AUDIO_MANAGER_RESOURCE_FM, /* 4 */
+
+ MAX_AUDIO_MANAGER_RESOURCE
+} T_ZDrvAudioM_Resource;
+
+
+
+
+
+
+/**************************************************************************
+ * Global Variable *
+ **************************************************************************/
+
+
+
+extern SINT32 zDrvAudioM_GetResource(T_ZDrvAudioM_Resource res);
+extern SINT32 zDrvAudioM_FreeResource(T_ZDrvAudioM_Resource res);
+
+
+#endif /* _DRVS_AUDIOM_H */
+
diff --git a/cp/ps/driver/inc/misc/drvs_backlight.h b/cp/ps/driver/inc/misc/drvs_backlight.h
new file mode 100644
index 0000000..2f4e549
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_backlight.h
@@ -0,0 +1,62 @@
+/*********************************************************************
+ Copyright 2007 by ZTE Corporation.
+ *
+ * FileName:: drvs_backlight.h
+ * File Mark:
+* Description: This file contains the hardware interface for lcd blg driver
+* Others:
+* Version: v0.5
+* Author: zhangyingjun
+* Date: 2009-06-25
+
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+* History 2:
+**********************************************************************/
+
+#ifndef _DRVS_BLG_H
+#define _DRVS_BLG_H
+
+
+/**************************************************************************
+* Function: BlgEvb_Init
+* Description: initiate the battery device
+* Parameters:
+* Input:
+* None
+* Outpu: None
+* Returns:
+* DRV_SUCCESS
+* Others: None
+**************************************************************************/
+ SINT32 BlgEvb_Open(void);
+/**************************************************************************
+* Function: BlgEvb_LcdEnable
+* Description: open the LCD backlight
+* Parameters:
+* Input:
+* bl: TRUE or FALSE value,TRUE open the blg,FALSE close theblg
+* Outpu: None
+* Returns:
+* DRV_SUCCESS
+* Others: None
+**************************************************************************/
+SINT32 BlgEvb_LcdEnable(BOOL bl);
+/**************************************************************************
+* Function: halBlg_LcdSetBrightness
+* Description: set the LCD brightness
+* Parameters:
+* Input:
+* val_brightness the value of lcd brightness
+*
+* Outpu: None
+* Returns:
+* DRV_SUCCESS
+* Others: None
+**************************************************************************/
+SINT32 BlgEvb_LcdSetBrightness(UINT32 val_brightness );
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_cam.h b/cp/ps/driver/inc/misc/drvs_cam.h
new file mode 100644
index 0000000..5c533a9
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_cam.h
@@ -0,0 +1,351 @@
+/*******************************************************************************
+ * Copyright by ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: V1.0
+ * Author: wuhui
+ * Date: 2016-9-6
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_CAM_H
+#define _DRVS_CAM_H
+
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "drvs_general.h"
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+//#define ZDRV_DEV_CAMERA "camera" /* device name of camera */
+
+typedef UINT32 PhyAddr;
+typedef UINT8 * T_HalCam_Buff_Addr;
+
+/****************************************************************************
+* Types
+****************************************************************************/
+typedef enum
+{
+ HAL_CAM_BUF_FREE= 0, /* Buffer isn't full filled */
+ HAL_CAM_BUF_READY= 1,
+ HAL_CAM_BUF_BUSY= 2,
+ MAX_HAL_CAM_BUF_FLAG =3
+}T_HalCam_EBufFlag;
+#if defined(_USE_RAW_BUFFER)
+typedef struct
+{
+ T_HalCam_Buff_Addr bufaddr;
+ T_HalCam_EBufFlag bufflag;
+} T_HalSensor_Buff;
+#endif
+/* sensors */
+typedef enum
+{
+ SENSOR_MAIN, /* main sensor */
+ SENSOR_SUB, /* sub sensor */
+ MAX_SENSOR_ID
+} T_ZDrv_SensorId;
+typedef enum
+{
+ //SENSOR_OV9656,
+ //SENSOR_OV7670,
+ //SENSOR_MT9D113,
+ //SENSOR_MT9V113,
+ //SENSOR_HI704,
+ #if defined(_USE_TYPE_GC6133)
+ SENSOR_GC6133,
+ #endif
+ #if defined(_USE_TYPE_BF3A01CS)
+ SENSOR_BF3A01CS,
+ #endif
+ MAX_SENSOR_DEV_TYPE
+} T_ZDrv_Sensor_DevType;
+
+/* sensor info */
+typedef struct
+{
+ T_ZDrv_Sensor_DevType tDevType; /* the sensor now using*/
+ T_ZDrv_SensorId tActivedSensor; /* the sensor now using*/
+ UINT16 uiWidth; /* max pixel width of the actived sensor */
+ UINT16 uiHeight; /* max pixel height of the actived sensor */
+ UINT16 pixelBytes;
+ BOOL fucSetZoom; /*whether to support set_zoom function */
+ BOOL fucSetImgSize; /*whether to support set_img_Size function */
+ BOOL fucSetEffect; /*whether to support set_effect function */
+ BOOL fucSetMirrorFlip; /*whether to support set MirrorFlip function */
+ BOOL fucSetBrightness; /*whether to support set Brightness function */
+ BOOL fucSetContrast; /*whether to support SetContrast function */
+ BOOL fucSetSaturation; /*whether to support SetSaturation function */
+ BOOL fucSetWhiteBalance; /*whether to support SetWhiteBalance function */
+ BOOL fucSetLightMode; /*whether to support SetLightMode function */
+ BOOL fucSetNightMode; /*whether to support SetNightMode function */
+ BOOL fucSetFrameRate; /*whether to support SetFrameRate function */
+
+ //BOOL funcSetExposureCompensation; /*whether to support ExposureCompensation function */
+ BOOL funcSetAntiFlicker;
+
+} T_ZDrv_SensorInfo;
+/* camera frame rate*/
+typedef enum
+{
+ Fps714 = 0,
+ Fps75 ,
+ Fps143 ,
+ Fps15 ,
+ Fps25 ,
+ Fps30 ,
+
+ MAX_FPS_SIZE
+} T_ZDrv_CamFps;
+
+/* output size */
+typedef enum
+{
+ OUTPUT_IMG_SXGA =0,
+ OUTPUT_IMG_VGA,
+ OUTPUT_IMG_QVGA,
+ OUTPUT_IMG_QQVGA,
+ OUTPUT_IMG_CIF ,
+ OUTPUT_IMG_QCIF,
+ OUTPUT_IMG_QQCIF ,
+ OUTPUT_IMG_USVGA,
+
+ MAX_OUTPUT_IMG_SIZE
+} T_ZDrv_CamOutputSize;
+
+/* night mode */
+typedef enum
+{
+ NIGHT_MODE_0, /* level 0*/
+ NIGHT_MODE_1, /* level 1 */
+ NIGHT_MODE_2, /* level 2 */
+
+ MAX_NIGHT_MODE
+} T_ZDrv_CamNightMode;
+
+/* zomm level */
+typedef enum
+{
+ ZOOM_LEVEL_0, /* level 0 */
+ ZOOM_LEVEL_1, /* level 1 */
+ ZOOM_LEVEL_2, /* level 2 */
+ ZOOM_LEVEL_3, /* level 3 */
+ ZOOM_LEVEL_4, /* level 4 */
+
+ MAX_ZOOM_LEVEL
+} T_ZDrv_CamZoom;
+
+/* brightness level */
+typedef enum
+{
+ BRI_LEVEL_0 = 0, /* level 0 (darkest) */
+ BRI_LEVEL_1, /* level 1 */
+ BRI_LEVEL_2, /* level 2 */
+ BRI_LEVEL_3, /* level 3 */
+ BRI_LEVEL_4, /* level 4 */
+ BRI_LEVEL_5, /* level 5 */
+ BRI_LEVEL_6, /* level 6 */
+
+ MAX_BRI_LEVEL
+} T_ZDrv_CamBrightness;
+
+/* contrast level*/
+typedef enum
+{
+ CON_LEVEL_0 = 0, /* level 0 (thinnest) */
+ CON_LEVEL_1, /* level 1 */
+ CON_LEVEL_2, /* level 2 */
+ CON_LEVEL_3, /* level 3 */
+ CON_LEVEL_4, /* level 4 */
+ CON_LEVEL_5, /* level 5 */
+ CON_LEVEL_6, /* level 6 (sharpest) */
+
+ MAX_CON_LEVEL
+} T_ZDrv_CamContrast;
+
+/* saturation level */
+typedef enum
+{
+ SAT_LEVEL_0,
+ SAT_LEVEL_1,
+ SAT_LEVEL_2,
+ SAT_LEVEL_3,
+ SAT_LEVEL_4,
+
+ MAX_SAT_LEVEL
+} T_ZDrv_CamSaturation;
+
+/* camera effect */
+typedef enum
+{
+ EFF_NORMAL = 0,
+ EFF_ANTIQUE,
+ EFF_BLUISH,
+ EFF_GREENISH,
+ EFF_REDISH,
+ EFF_YELLOW,
+ EFF_NEGATIVE,
+ EFF_BLACK_AND_WHITE,
+ EFF_BW_NEGATIVE,
+ EFF_SEPIA_GREEN,
+
+ MAX_EFF_TYPE
+} T_ZDrv_CamEffect;
+
+/* camera whiteblance */
+typedef enum
+{
+ WB_AUTO = 0,
+ WB_INSCANDSENCE,
+ WB_FLUORESCENT,//CWF
+ // WB_FLUORECWF, //cool white FLUORESCENT
+ WB_TUNGSTEN,
+ WB_SUNNY,
+ WB_CLOUDY,
+
+ MAX_WB_MODE
+} T_ZDrv_CamWhiteBalance;
+
+/* camera light mode */
+typedef enum
+{
+ LIGTH_AUTO, /* auto */
+ LIGTH_SUNNY, /* sunny */
+ LIGTH_CLOUDY, /* cloudy */
+ LIGTH_OFFICE, /* office */
+ LIGTH_HOME, /* home */
+ LIGTH_NIGHT, /* night */
+
+ MAX_LIGTH_MODE
+} T_ZDrv_CamLightMode;
+
+/* exposure compesation level */
+typedef enum
+{
+ EV_NEG_4_3 = 0, /* EV -2 */
+ EV_NEG_3_3, /* EV -1.5 */
+ EV_NEG_2_3, /* EV -1 */
+ EV_NEG_1_3, /* EV -0.5 */
+ EV_ZERO, /* EV 0 */
+ EV_POS_1_3, /* EV +0.5 */
+ EV_POS_2_3, /* EV +1 */
+ EV_POS_3_3, /* EV +1.5 */
+ EV_POS_4_3, /* EV +2 */
+
+ MAX_EV_LEVEL
+} T_ZDrv_CamExpCom;
+
+typedef enum
+{
+ HAL_CAM_WORD_MODE_YUV,
+ HAL_CAM_WORD_MODE_RGB,
+
+ MAX_HAL_CAM_WORD_MODE
+}T_HalCam_EWorkMode;
+
+typedef struct
+{
+ PhyAddr *Y;
+ PhyAddr *Cb;
+ PhyAddr *Cr;
+}T_ZDrv_YuvBuf;
+
+/* Image data buffer */
+typedef union
+{
+ T_ZDrv_YuvBuf YuvBuf;
+ PhyAddr *streamDataBuf;
+ PhyAddr*ARGBdataBuf;
+} T_ZDrv_ImageDataBuf;
+/* Pixel format. */
+typedef enum
+{
+ PIXEL_YCbCr400,
+ PIXEL_YCbCr420,
+ PIXEL_YUYV,
+// PIXEL_YCbCr422 = PIXEL_YUYV,
+// PIXEL_YCbCr422H = PIXEL_YUYV,
+// PIXEL_YCbCr422V = PIXEL_YUYV,
+ PIXEL_YCbCr444,
+ PIXEL_RGB_PLANAR,
+ PIXEL_RGB555,
+ PIXEL_RGB565,
+ PIXEL_RGB666,
+ PIXEL_RGB888,
+ PIXEL_ARGB888,
+
+ MAX_PIXEL_FORMAT
+} T_ZDrv_PixelFmt;
+
+/* camera data info */
+typedef struct
+{
+ T_ZDrv_ImageDataBuf dataBuf; /* image data buffer */
+ UINT32 Width; /* image width */
+ UINT32 Height; /* image height */
+ T_ZDrv_PixelFmt pixeFmt; /* pixel format */
+} T_ZDrv_CamDataInfo;
+
+typedef struct
+{
+ UINT32 ySize;
+ UINT32 uSize;
+ UINT32 vSize;
+
+} T_ZDrv_YuvBufSize;
+
+/* Image buffer size */
+typedef union
+{
+ T_ZDrv_YuvBufSize YuvBufSize;
+ UINT32 streamBufSize;
+ UINT32 ARGBBufSize;
+} T_ZDrv_ImageBufSzie;
+
+/* mirror type */
+typedef enum
+{
+ MIR_NONE,
+ MIR_V,
+ MIR_H,
+ MIR_V_H,
+
+ MAX_MIR_TYPE
+} T_ZDrv_MirrorType;
+
+typedef enum
+{
+ FLICKER_50HZ,
+ FLICKER_60HZ,
+
+ MAX_FLICKER_TYPE
+} T_ZDrv_AntiFlicker;
+
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+
+
+#endif/*_FILENAME_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_cipher.h b/cp/ps/driver/inc/misc/drvs_cipher.h
new file mode 100644
index 0000000..f6a9cc5
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_cipher.h
@@ -0,0 +1,223 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: drvs_cipher.h
+* File Mark:
+* Description: Provide cipher module Function prototype declaration
+* and type declaration.
+* Others:
+* Version: v0.5
+* Author: Wangxia
+* Date: 2008-07-06
+*
+* History 1:
+* History 2:
+**********************************************************************/
+#ifndef _DRVS_CIPHER_H
+#define _DRVS_CIPHER_H
+/**************************************************************************
+ * Include files *
+ **************************************************************************/
+
+
+
+
+/**************************************************************************
+ * Macro
+ *
+ **************************************************************************/
+ #define ZDRV_DEV_CIPHER "cipher"
+
+
+ /**************************************************************************
+ * Types *
+ **************************************************************************/
+
+/* param of cipher interface function */
+typedef struct
+{
+ UINT32 uiDirection; /* direction param*/
+ UINT32 uiCount; /* count param for encrypt and integrity check */
+ UINT8 pcKey[16]; /* key param */
+ union
+ {
+ UINT32 uiBearer; /* bearer param for encrypt */
+ UINT32 uiFresh; /* fresh param for integrity check */
+ }uOthers;
+} T_ZDrvCipher_Param;
+
+
+typedef UINT8 aCiphKey[4][16];
+
+/*GPRS cipher struct, GPRS uses GEA1/2,GEA3 algorithm*/
+ typedef struct
+{
+ UINT8 *headerStart_ptr;
+ UINT16 headerLength;
+ UINT8 *payloadStart_ptr;
+ UINT16 payloadLength;
+ UINT16 crcLength;
+ UINT8 *destination_ptr;
+ UINT8 cipherOn;
+ UINT8 *kc_ptr;
+ UINT32 cipherInput;
+} T_ZDrvCipher_GEACipherData;
+
+
+ typedef struct
+{
+ SINT32 Direction_CK_index;
+ UINT32 Count;
+ UINT32 Bearer;
+ UINT32 Length;
+ UINT32 Fresh;
+ UINT32 *Message;
+ UINT32 Direction;
+ SINT32 IK_index;
+ UINT32 MAC_I;
+}T_ZDrvCipher_RequestListType;
+
+typedef struct
+{
+ SINT32 CiphContext;
+ SINT32 CallerId;
+ SINT32 NoRequests;
+ aCiphKey *IK;
+ aCiphKey *CK;
+ T_ZDrvCipher_RequestListType RequestList[2];
+}T_ZDrvCipher_SCiphF8;
+
+typedef T_ZDrvCipher_SCiphF8 T_ZDrvCipher_SCiphF9;
+
+/**************************************************************************
+ * Global Variables *
+ **************************************************************************/
+
+
+
+
+/**************************************************************************
+ * Function Prototypes *
+ **************************************************************************/
+/**************************************************************************
+* Functin: zDrvCipher_Encrypt
+* Description: This function is used to encrypt the input data.
+* Parameters:
+* (IN)
+* pBufferInOut: Data buffer for input and output, and its size must be a multiple of 32
+* uiBitLenInOut: Data length of input and output, 1-20000bit.
+* pPara: Stuct T_ZDrvCipher_PARA
+* (OUT)
+* pBufferInOut: Data buffer for input and output, and its size must be a multiple of 32
+* Returns:
+* T_ZDrv_ErrCode
+* Others:
+* 1. Param pBufferInOut is both for input and output.
+* 2. The data length of input and output is the same.
+ **************************************************************************/
+SINT32 zDrvCipher_Encrypt( CHAR *pBufferInOut, UINT32 uiBitLenInOut, T_ZDrvCipher_Param *pParam );
+
+
+/**************************************************************************
+* Functin: zDrvCipher_Integrity
+* Description: This function is used to chech the integrity.
+* Parameters:
+* (IN)
+* pBufferInOut: Data buffer for input and output, and its size must be a multiple of 32
+* uiBitLenInOut: Data length of input and output.
+* pPara: Stuct T_ZDrvCipher_PARA
+* (OUT)
+* pBufferInOut: Data buffer for input and output, and its size must be a multiple of 32
+* Returns:
+* T_ZDrv_ErrCode
+* Others:
+* 1. Param pBufferInOut is both for input and output.
+* 2. The data length of output is 32bit.
+ **************************************************************************/
+SINT32 zDrvCipher_Integrity( CHAR *pBufferInOut, UINT32 uiBitLenIn, T_ZDrvCipher_Param *pParam );
+
+/***************************************************************************************
+* Function: zDrvCipher_GprsUintInitialise
+* Description: This function is used to initialize ciphering semaphoreme,olny using for GPRS communication
+* Parameters:
+* Input:
+* None
+* Output:
+* None
+* Returns:
+* None
+***************************************************************************************/
+VOID zDrvCipher_GprsUnitInitialise (VOID);
+
+
+/***************************************************************************************
+* Function: zDrvCipher_GprsUnitEncode
+* Description: This function is used to encode data of uplink,olny using for GPRS communication
+* Parameters:
+* Input:
+* pointer of T_ZDrvCipher_GEACipherData struct
+* Output:
+* None
+* Returns:
+* None
+***************************************************************************************/
+VOID zDrvCipher_GprsUnitEncode(T_ZDrvCipher_GEACipherData * ciData_ptr);
+
+/***************************************************************************************
+* Function: zDrvCipher_GgprsUnitEncode
+* Description: This function is used to encode data of uplink,olny using for GPRS communication
+* Parameters:
+* Input:
+* pointer of T_ZDrvCipher_GEACipherData struct
+* Output:
+* None
+* Returns:
+* None
+***************************************************************************************/
+VOID zDrvCipher_GgprsUnitEncode(T_ZDrvCipher_GEACipherData * ciData_ptr);
+
+
+/***************************************************************************************
+* Function: zDrvCipher_GprsUnitDecode
+* Description: This function is used to encode data of downlink,olny using for GPRS communication
+* Parameters:
+* Input:
+* pointer of T_ZDrvCipher_GEACipherData struct
+* Output:
+* None
+* Returns:
+* None
+***************************************************************************************/
+BOOL zDrvCipher_GprsUnitDecode(T_ZDrvCipher_GEACipherData * ciData_ptr);
+
+/****************************************************************************************
+* Function: zDrvCipher_F8
+* Description: This function is used to cipher data using f8 algorithm which be used in UMTS communication
+* Parameters:
+* Input:
+* pointer of T_ZDrvCipher_SCiphF8 struct
+* Output:
+* None
+* Returns:
+* 1: faild
+* 0:success
+****************************************************************************************/
+BOOL zDrvCipher_F8(T_ZDrvCipher_SCiphF8 *f8_ctrl);
+
+
+/***************************************************************************************
+* Function: zDrvCipher_F9
+* Description: This function is used to cipher data using f9 algorithm which be used in UMTS communication
+* Parameters:
+* Input:
+* pointer of T_ZDrvCipher_GEACipherData struct
+* Output:
+* None
+* Returns:
+* None
+***************************************************************************************/
+VOID zDrvCipher_F9(T_ZDrvCipher_SCiphF9 *f9_ctrl);
+
+
+#endif /* _CIPHER_API_H */
+
diff --git a/cp/ps/driver/inc/misc/drvs_codec.h b/cp/ps/driver/inc/misc/drvs_codec.h
new file mode 100644
index 0000000..b93e577
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_codec.h
@@ -0,0 +1,581 @@
+/**
+ * @file drvs_codec.h
+ * @brief Public APIs of Codec drivers
+ *
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * @author Xinqiang Xu <xu.xinqiang@sanechips.com.cn>
+ * @ingroup si_cp_drv_id
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _DRV_CODEC_TLV3100_H
+#define _DRV_CODEC_TLV3100_H
+
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "drvs_i2s.h"
+#include "drvs_voiceprocess.h"
+
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Type definitions *
+ ******************************************************************************/
+typedef unsigned long T_ZDrvCodec_Handle;
+
+typedef enum {
+ VOICE_SOURCE,
+ AUDIO_SOURCE,
+ EXTERN_AUDIO,
+
+ SOURCE_MAX
+} T_ZDrvCodec_SourceType;
+
+typedef enum {
+ AUDIO_I2S_NONE,
+ AUDIO_I2S0,
+ AUDIO_I2S1,
+
+ AUDIO_I2S_MAX
+} T_ZDrvCodec_AudioI2SChannel;
+
+typedef enum {
+ I2S_MASTER_MODE,
+ I2S_SLAVE_MODE,
+
+ I2S_MODE_MAX
+} T_ZDrvCodec_AudioI2SMode;
+
+typedef enum {
+ AUDIO_SAMPLE_8K,
+ AUDIO_SAMPLE_11_025_KHZ, /* Use 11.025 kHz sampling rate. */
+ AUDIO_SAMPLE_12_KHZ, /* Use 12 kHz sampling rate. */
+ AUDIO_SAMPLE_16K,
+ AUDIO_SAMPLE_22_050_KHZ, /* Use 22.050 kHz sampling rate. */
+ AUDIO_SAMPLE_24_KHZ, /* Use 24 kHz sampling rate. */
+ AUDIO_SAMPLE_32K,
+ AUDIO_SAMPLE_44_1K,
+ AUDIO_SAMPLE_48K,
+ AUDIO_SAMPLE_64_KHZ, /* Use 64 kHz sampling rate */
+ AUDIO_SAMPLE_96_KHZ, /* Use 96 kHz sampling rate. */
+
+ AUDIO_SAMPLE_MAX
+} T_ZDrvCodec_AudioSample;
+
+typedef enum {
+ AUDIO_INPUT_HANDSET,
+ AUDIO_INPUT_SPEAKER,
+ AUDIO_INPUT_HEADSET,
+ AUDIO_INPUT_BLUETOOTH,
+ AUDIO_INPUT_FM_ANATODIG,
+ AUDIO_INPUT_FM_ANATOANA,
+
+ AUDIO_INPUT_MAX
+} T_ZDrvCodec_InDevice;
+
+typedef enum {
+ AUDIO_OUTPUT_RECEIVER,
+ AUDIO_OUTPUT_SPEAKER,
+ AUDIO_OUTPUT_HEADSET,
+ AUDIO_OUTPUT_BLUETOOTH,
+ AUDIO_OUTPUT_HEADSET_SPEAKER,
+ AUDIO_OUTPUT_FM_ANATODIG_HEADSET,
+ AUDIO_OUTPUT_FM_ANATODIG_SPEAKER,
+ AUDIO_OUTPUT_FM_ANATOANA_HEADSET,
+ AUDIO_OUTPUT_FM_ANATOANA_SPEAKER,
+
+ AUDIO_OUTPUT_MAX
+} T_ZDrvCodec_OutDevice;
+
+typedef enum {
+ CLSD_GAIN_PLUS_6DB,
+ CLSD_GAIN_PLUS_12DB,
+ CLSD_GAIN_PLUS_18DB,
+ CLSD_GAIN_PLUS_24DB,
+
+ CLSD_GAIN_MAX
+} T_ZDrvCodec_ClsD_Vol;
+
+typedef enum {
+ CLSAB_GAIN_PLUS_0DB,
+ CLSAB_GAIN_PLUS_1DB,
+ CLSAB_GAIN_PLUS_2DB,
+ CLSAB_GAIN_PLUS_3DB,
+ CLSAB_GAIN_PLUS_4DB,
+ CLSAB_GAIN_PLUS_5DB,
+ CLSAB_GAIN_PLUS_6DB,
+ CLSAB_GAIN_PLUS_7DB,
+ CLSAB_GAIN_PLUS_8DB,
+ CLSAB_GAIN_PLUS_9DB,
+
+ CLSAB_GAIN_MAX
+} T_ZDrvCodec_ClsAB_Vol;
+
+typedef enum {
+ CODEC_INPATH_DIG_GAIN_MINUS_12DB = 0,
+ CODEC_INPATH_DIG_GAIN_MINUS_11DB,
+ CODEC_INPATH_DIG_GAIN_MINUS_10DB,
+ CODEC_INPATH_DIG_GAIN_MINUS_9DB,
+ CODEC_INPATH_DIG_GAIN_MINUS_8DB,
+ CODEC_INPATH_DIG_GAIN_MINUS_7DB,
+ CODEC_INPATH_DIG_GAIN_MINUS_6DB,
+ CODEC_INPATH_DIG_GAIN_MINUS_5DB,
+ CODEC_INPATH_DIG_GAIN_MINUS_4DB,
+ CODEC_INPATH_DIG_GAIN_MINUS_3DB,
+ CODEC_INPATH_DIG_GAIN_MINUS_2DB,
+ CODEC_INPATH_DIG_GAIN_MINUS_1DB,
+ CODEC_INPATH_DIG_GAIN_0DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_1DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_2DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_3DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_4DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_5DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_6DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_7DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_8DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_9DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_10DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_11DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_12DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_13DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_14DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_15DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_16DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_17DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_18DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_19DB,
+ CODEC_INPATH_DIG_GAIN_PLUS_20DB,
+
+ CODEC_INPATH_DIG_GAIN_MAX
+} T_ZDrvCodec_InPath_Digital_Gain;
+
+typedef enum {
+ CODEC_OUTPATH_DIG_GAIN_PLUS_24DB = 0,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_23DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_22DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_21DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_20DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_19DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_18DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_17DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_16DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_15DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_14DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_13DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_12DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_11DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_10DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_9DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_8DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_7DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_6DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_5DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_4DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_3DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_2DB,
+ CODEC_OUTPATH_DIG_GAIN_PLUS_1DB,
+ CODEC_OUTPATH_DIG_GAIN_0DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_1DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_2DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_3DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_4DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_5DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_6DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_7DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_8DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_9DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_10DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_11DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_12DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_13DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_14DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_15DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_16DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_17DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_18DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_19DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_20DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_21DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_22DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_23DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_24DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_25DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_26DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_27DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_28DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_29DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_30DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_31DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_32DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_33DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_34DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_35DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_36DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_37DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_38DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_39DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_40DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_41DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_42DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_43DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_44DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_45DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_46DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_47DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_48DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_49DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_50DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_51DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_52DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_53DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_54DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_55DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_56DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_57DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_58DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_59DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_60DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_61DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_62DB,
+ CODEC_OUTPATH_DIG_GAIN_MINUS_63DB,
+
+ CODEC_OUTPATH_DIG_GAIN_MAX
+} T_ZDrvCodec_OutPath_Digital_Gain;
+
+typedef enum {
+ MICBIAS_OUT_POWERDOWN = 0,
+ MICBIAS_OUT_2V,
+ MICBIAS_OUT_2_5V,
+ MICBIAS_OUT_AVDD,
+
+ MICBIAS_OUT_MAX
+} T_ZDrvMicBias_Ctrl;
+
+/**
+ * @brief describe the codec agc Parameter
+ * @param onOff agc function enable
+ * @param targetLevel the Level of target
+ * @param attackTime attack Time
+ * @param decayTime decay Time
+ * @param noiseDebounce noise Debounce
+ * @param signalDebounce signal Debounce
+ * @param noiseThreshold the Threshold of the noise
+ * @param maxgain the max gain
+ */
+typedef struct _T_AudCodec_AGC_Parameter {
+ SINT8 onOff;
+ SINT8 targetLevel;
+ SINT8 attackTime;
+ SINT8 decayTime;
+ SINT8 noiseDebounce;
+ SINT8 signalDebounce;
+ SINT8 noiseThreshold;
+
+ SINT8 maxgain;
+} T_ZDrvAudCodec_AGC_Parameter;
+
+/**
+ * @brief describe the codec drc Parameter
+ * @param onOff drc function enable
+ * @param threshold threshold value
+ * @param hysteresis hysteresis value
+ * @param holdTime hold Time
+ * @param attackRate attack Rate
+ * @param decayRate decay Rate
+ */
+typedef struct _T_AudCodec_DRC_Parameter {
+ SINT8 onOff;
+ SINT8 threshold;
+ SINT8 hysteresis;
+ SINT8 holdTime;
+ SINT8 attackRate;
+ SINT8 decayRate;
+} T_ZDrvAudCodec_DRC_Parameter;
+
+typedef enum {
+ CODEC_DATA_LEGTH_8BIT = 0,
+ CODEC_DATA_LEGTH_16BIT,
+ CODEC_DATA_LEGTH_20BIT,
+ CODEC_DATA_LEGTH_24BIT,
+ CODEC_DATA_LEGTH_32BIT,
+
+ CODEC_DATA_LEGTH_MAX
+} T_ZDrvCodec_DataLength;
+
+typedef enum {
+ CODEC_DATA_TRACK_DOUBLE = 0,
+ CODEC_DATA_TRACK_LEFT,
+ CODEC_DATA_TRACK_RIGHT,
+
+ CODEC_DATA_TRACK_MAX
+} T_ZDrvCodec_DataTrack;
+
+typedef enum {
+ CODEC_BUS_I2S,
+ CODEC_BUS_RJF, /* Right-Justified Mode */
+ CODEC_BUS_LJF, /* Left-Justified Mode */
+ CODEC_BUS_DSP,
+ CODEC_BUS_TDM,
+ CODEC_BUS_MAX
+} T_AudCodec_BusMode;
+
+#define T_ZDrvCodec_BusMode T_AudCodec_BusMode
+
+/**
+ * @brief describe the i2s transfer protocol
+ * @param audI2SChannel Audio I2S Channel
+ * @param masterSlave Audio I2S Mode;
+ * @param busMode bus mode
+ * @param dataLength Codec Data Length
+ * @param dataTrack codec data type
+ */
+typedef struct _T_Codec_UseProtocol {
+ T_ZDrvCodec_AudioI2SChannel audI2SChannel;
+ T_ZDrvCodec_AudioI2SMode masterSlave;
+ T_ZDrvCodec_BusMode busMode;
+ T_ZDrvCodec_DataLength dataLength;
+ T_ZDrvCodec_DataTrack dataTrack;
+} T_ZDrvCodec_UseProtocol;
+
+/*******************************************************************************
+ * Global variable declarations *
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Global function declarations *
+ ******************************************************************************/
+/**
+ * @brief Open codec,set parameters.
+ *
+ * @param handle Pointer to T_ZDrvCodec_Handle.
+ * @param srcType Pointer to T_ZDrvCodec_SourceType
+ *
+ * @return 0-DRV_SUCCESS, other-error
+ */
+SINT32 zDrvCodec_Open(T_ZDrvCodec_Handle *handle, T_ZDrvCodec_SourceType srcType);
+
+/**
+* @brief close codec, power off.
+*
+* @param handle T_ZDrvCodec_Handle
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_Close(T_ZDrvCodec_Handle *handle);
+
+/**
+* @brief Set i2s protocol.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param channel T_ZDrvCodec_AudioI2SChannel
+* @param masterSlave T_ZDrvCodec_AudioI2SMode
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_SetProtocal(T_ZDrvCodec_Handle handle, T_ZDrvCodec_AudioI2SChannel channel, T_ZDrvCodec_AudioI2SMode masterSlave);
+
+/**
+* @brief Set i2s clock.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param sample T_ZDrvCodec_AudioSample
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_SetClock(T_ZDrvCodec_Handle handle, T_ZDrvCodec_AudioSample sample);
+
+/**
+* @brief reset codec.
+*
+* @param handle T_ZDrvCodec_Handle
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_Reset(T_ZDrvCodec_Handle handle);
+
+/**
+* @brief Set the input path of the codec.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param dev T_ZDrvCodec_InDevice
+* @param onoff BOOL
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_SetInPath(T_ZDrvCodec_Handle handle, T_ZDrvCodec_InDevice dev, BOOL onoff);
+
+/**
+* @brief Set the output path of the codec.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param dev T_ZDrvCodec_InDevice
+* @param onoff BOOL
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_SetOutPath(T_ZDrvCodec_Handle handle, T_ZDrvCodec_OutDevice dev, BOOL onoff);
+
+/**
+* @brief Enable the audio path.
+*
+* @param handle T_ZDrvCodec_Handle
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_AudioEnable(T_ZDrvCodec_Handle handle);
+
+/**
+* @brief Disable the audio path.
+*
+* @param handle T_ZDrvCodec_Handle
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_AudioDisable(T_ZDrvCodec_Handle handle);
+
+/**
+* @brief Set the ClsD volume.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param vol T_ZDrvCodec_ClsD_Vol
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_Set_ClsD_Vol(T_ZDrvCodec_Handle handle, T_ZDrvCodec_ClsD_Vol vol);
+
+/**
+* @brief Set the ClsAB volume.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param vol UINT8
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_Set_ClsAB_Vol(T_ZDrvCodec_Handle handle, UINT8 vol);
+
+/**
+* @brief Set the output Analog volume of the Output path.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param vol SINT8
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_Set_Outpath_Ana_Vol(T_ZDrvCodec_Handle handle, SINT8 vol);
+
+/**
+* @brief Set the Analog volume of the Input path.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param vol SINT8
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_Set_Inpath_Ana_Vol(T_ZDrvCodec_Handle handle, SINT8 vol);
+
+/**
+* @brief Set the Digital volume of the Input path.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param invol T_ZDrvCodec_InPath_Digital_Gain
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_Set_Inpath_Dig_Vol(T_ZDrvCodec_Handle handle, T_ZDrv_VpVol vol);
+
+/**
+* @brief Set the Digital volume of the Output path.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param invol T_ZDrv_VpVol
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_Set_Outpath_Dig_Vol(T_ZDrvCodec_Handle handle, T_ZDrv_VpVol vol);
+
+/**
+* @brief Set the Side Tone.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param onoff BOOL
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_SetSideTone(T_ZDrvCodec_Handle handle, BOOL onoff);
+
+/**
+* @brief Set the Mic Bias.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param micBiasCtrl T_ZDrvMicBias_Ctrl
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_SetMicBias(T_ZDrvCodec_Handle handle, T_ZDrvMicBias_Ctrl micBiasCtrl);
+
+/**
+* @brief Set the Input Agc.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param AGCPara Poiter to T_ZDrvAudCodec_AGC_Parameter
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_SetInputAgc(T_ZDrvCodec_Handle handle, T_ZDrvAudCodec_AGC_Parameter *AGCPara);
+
+/**
+* @brief Set the Output Agc.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param DRCPara Poiter to T_ZDrvAudCodec_DRC_Parameter
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_SetOutputDrc(T_ZDrvCodec_Handle handle, T_ZDrvAudCodec_DRC_Parameter *DRCPara);
+
+/**
+* @brief Set the Loop Back.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param onoff BOOL
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_SetLoopBack(T_ZDrvCodec_Handle handle, BOOL onoff);
+
+/**
+* @brief Set the mute function in the input path.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param onoff BOOL
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_SetInpathMute(T_ZDrvCodec_Handle handle, BOOL onoff);
+
+/**
+* @brief Set the mute function in the output path.
+*
+* @param handle T_ZDrvCodec_Handle
+* @param onoff BOOL
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvCodec_SetOutpathMute(T_ZDrvCodec_Handle handle, BOOL onoff);
+
+/**
+* @brief read data to codec
+*
+* @param regPage the page number of the register
+* @param regAddress register address
+* @param regValue register value
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+//SINT32 codec_I2CRead(UINT8 regPage, UINT8 regAddress, UINT8 *regValue);
+
+#endif/*#ifndef _DRV_CODEC_TLV3100_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_comm.h b/cp/ps/driver/inc/misc/drvs_comm.h
new file mode 100644
index 0000000..dc9fde7
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_comm.h
@@ -0,0 +1,143 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: drvs_comm.h
+* File Mark:
+* Description: comm hal interface declaration.
+* Others:
+* Version: v1.0
+* Author: zhangyingjun
+* Date: 2009-05-26
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+
+* History 2:
+**********************************************************************/
+
+#ifndef _DRVS_COMM_H_
+#define _DRVS_COMM_H_
+
+/**************************************************************************
+ * Include files *
+ **************************************************************************/
+
+
+
+
+
+ /**************************************************************************
+ * Macro *
+ **************************************************************************/
+
+
+
+/**************************************************************************
+ * Types *
+ **************************************************************************/
+/*the diffrent reset info*/
+typedef enum
+{
+ RESET_TO_NORMAL, /*reset to idle*/
+ RESET_TO_CHARGER, /*reset to charger*/
+ RESET_TO_ALRAM, /*reset to alarm*/
+ RESET_TO_EXCEPTRESET,
+ MAX_RESET_TYPE,
+} T_ZDrvSys_RESET_TYPE;
+
+/*the power on info*/
+typedef enum
+{
+ POWER_ON_NORMAL = 0,
+ POWER_ON_FOTA,
+ POWER_ON_CHARGING,
+ POWER_ON_RTC,
+ POWER_ON_RESET,
+ POWER_ON_HDT_TEST,
+ POWER_ON_EXCEPTRESET,
+ POWER_ON_LOCALUPDATE,
+ POWER_ON_BOOST_IN,
+ POWER_ON_AMT,
+ POWER_ON_PRODUCTION,
+ POWER_ON_INVALID,
+}T_ZDrvSys_PowerOn_Type;
+
+typedef struct _HAL_COMM_OPT_
+{
+ SINT32 (*halComm_ShutDown)(VOID); /*system powerdown Device Initialize Handler*/
+ SINT32 (*halComm_Soft_Reset)(T_ZDrvSys_RESET_TYPE reset_type); /*system reset Handler*/
+ T_ZDrvSys_PowerOn_Type (*halComm_Get_PowerOnStat)(VOID);
+}HAL_COMM_OPT, *HAL_COMM_OPT_PTR;
+
+
+/**************************************************************************
+ * Global Variable *
+ **************************************************************************/
+
+
+
+/**************************************************************************
+ * Function Prototypes *
+ **************************************************************************/
+
+/*******************************************************************************
+ * Function: zDrv_ShutDown
+ * Description: shut down the mobile
+ * Parameters:
+ * Input: None
+ * Output: None
+ *
+ * Returns:
+* DRV_SUCCESS:success to init
+* DRV_ERROR:fail to init
+ * Others: None
+ ********************************************************************************/
+SINT32 zDrv_ShutDown(VOID);
+
+
+/*******************************************************************************
+ * Function: zDrv_Soft_Reset
+ * Description: reset the mobile
+ * Parameters:
+ * Input: None
+ * Output: None
+ *
+ * Returns:
+* DRV_SUCCESS:success to reset
+* DRV_ERROR:fail to shutdown
+* others: others error code. for detailed information, please refer to the header file of hal layer
+ * Others: None
+ ********************************************************************************/
+SINT32 zDrv_Soft_Reset(T_ZDrvSys_RESET_TYPE reset_type);
+
+/**************************************************************************
+* Function: halChg_SetInstance
+* Description: this function used for put semp
+* Parameters:
+* Input:
+* None
+* Outpu: None
+* Returns:
+* None
+* Others: None
+**************************************************************************/
+VOID zDrvComm_SetOperations(HAL_COMM_OPT_PTR CommObjPtr);
+
+/**************************************************************************
+* Function: zDrvComm_GetPowerOnState
+* Description: get the systerm power on reason.
+* Parameters:
+* Input:
+* None
+* Outpu: None
+* Returns:
+* T_ZDrvSys_PowerOn_Type
+* Others: None
+**************************************************************************/
+T_ZDrvSys_PowerOn_Type zDrvComm_GetPowerOnState(VOID);
+
+#endif /* HAL_COMM_H */
+/*last line of file ends with a newline*/
diff --git a/cp/ps/driver/inc/misc/drvs_ddrnet.h b/cp/ps/driver/inc/misc/drvs_ddrnet.h
new file mode 100644
index 0000000..f292526
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_ddrnet.h
@@ -0,0 +1,6 @@
+#ifndef _DDRNET_PUB_H
+#define _DDRNET_PUB_H
+
+SINT32 zDrvDdrNet_Initiate(void);
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_disk.h b/cp/ps/driver/inc/misc/drvs_disk.h
new file mode 100644
index 0000000..8a89304
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_disk.h
@@ -0,0 +1,94 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: 1.0
+ * Author: geanfeng
+ * Date: 2013-09-25
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef _DRVS_DISK_H
+#define _DRVS_DISK_H
+
+#include "drvs_list.h"
+#include "drvs_io.h"
+#include "drvs_io_dev.h"
+
+
+typedef struct _T_ZDrvDisk_PartDevice T_ZDrvDisk_PartDevice;
+
+typedef struct _T_ZDrvDisk_DevDesc {
+ char dev_name[32]; /* device name */
+ unsigned char part_type; /* partition type */
+ unsigned char target; /* target SCSI ID */
+ unsigned char type; /* device type */
+ unsigned char removable; /* removable device */
+ unsigned long lba; /* number of blocks */
+ unsigned long blksz; /* block size */
+ char vendor [40+1]; /* IDE model, SCSI Vendor */
+ char product[20+1]; /* IDE Serial no, SCSI product */
+ char revision[8+1]; /* firmware revision */
+
+ T_ZDrvDisk_PartDevice *partition;
+
+ SINT32 (*block_read)(VOID *priv_data,
+ UINT32 start,
+ UINT32 blkcnt,
+ VOID *buffer);
+ SINT32 (*block_write)(VOID *priv_data,
+ UINT32 start,
+ UINT32 blkcnt,
+ const VOID *buffer);
+ SINT32 (*block_erase)(VOID *priv_data,
+ UINT32 start,
+ UINT32 blkcnt);
+ VOID *priv_data; /* device private data */
+}T_ZDrvDisk_DevDesc;
+
+
+/* Part types */
+#define PART_TYPE_UNKNOWN 0x00
+#define PART_TYPE_MAC 0x01
+#define PART_TYPE_DOS 0x02
+#define PART_TYPE_ISO 0x03
+#define PART_TYPE_AMIGA 0x04
+#define PART_TYPE_EFI 0x05
+#define PART_TYPE_TSP 0x06
+
+
+/* device types */
+#define DEV_TYPE_UNKNOWN 0xff /* not connected */
+#define DEV_TYPE_HARDDISK 0x00 /* harddisk */
+#define DEV_TYPE_TAPE 0x01 /* Tape */
+#define DEV_TYPE_CDROM 0x05 /* CD-ROM */
+#define DEV_TYPE_OPDISK 0x07 /* optical disk */
+
+typedef struct _T_ZDrvDisk_Partition {
+ unsigned long start; /* # of first block in partition */
+ unsigned long size; /* number of blocks in partition */
+ unsigned long blksz; /* block size in bytes */
+ unsigned char name[48]; /* partition name */
+ unsigned char type[32]; /* string type description */
+} T_ZDrvDisk_Partition;
+
+typedef struct _T_ZDrvDisk_PartDevice
+{
+ struct list_head node;
+ T_ZDrvDisk_Partition part_info;
+ T_ZDrvDisk_DevDesc *blk_dev;
+ T_ZDrvIODev_Handle *io_dev;
+}
+T_ZDrvDisk_PartDevice;
+
+SINT32 zDrvDisk_Register(T_ZDrvDisk_DevDesc *dev_desc);
+VOID zDrvDisk_Unregister(T_ZDrvDisk_DevDesc *dev_desc);
+
+#endif /* _DRVS_DISK_H */
diff --git a/cp/ps/driver/inc/misc/drvs_dma.h b/cp/ps/driver/inc/misc/drvs_dma.h
new file mode 100644
index 0000000..93d0892
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_dma.h
@@ -0,0 +1,494 @@
+/*******************************************************************************
+ * Copyright (C) 2014, ZTE Corporation.
+ *
+ * File Name: drvs_dma.h
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: v0.1
+ * Author: limeifeng
+ * Date: 2014-03-03
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_DMA_H
+#define _DRVS_DMA_H
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+#if defined (_CHIP_ZX297520V3)
+#define DMAC0_CH_NUM 23 /*dmac0¿ØÖÆÆ÷µÄͨµÀÊý*/
+#elif defined (_CHIP_ZX297520V2)
+#define DMAC0_CH_NUM 19 /*dmac0¿ØÖÆÆ÷µÄͨµÀÊý*/
+#endif
+
+//#define DMAC1_CH_NUM 9 /*dmac1¿ØÖÆÆ÷µÄͨµÀÊý*/
+#define DMAC_CH_MAX DMAC0_CH_NUM
+/****************************************************************************
+* Type
+****************************************************************************/
+typedef enum _T_ZDrv_DmaId
+{
+ DMAC0=0,
+ DMAC_NUM
+}T_ZDrv_DmaId;
+
+/*ÊÇ·ñΪ×èÈû·½Ê½´«Êä*/
+typedef enum _T_ZDrvDma_IsBlock
+{
+ DMA_NOT_BLOCK=0,
+ DMA_BLOCK=1,
+}T_ZDrvDma_IsBlock;
+
+#if defined (_CHIP_ZX297520V3)
+typedef enum
+{
+/*DMAC0ͨµÀºÅ¶¨Òå*/
+ DMAC0_CH_UART0_TX = 0,
+ DMAC0_CH_UART0_RX,
+ DMAC0_CH_UART1_TX,
+ DMAC0_CH_UART1_RX, /* or DMAC0_CH_HASH_RX*/
+ DMAC0_CH_SSP0_TX,
+ DMAC0_CH_SSP0_RX,
+ DMAC0_CH_GPRS0,
+ DMAC0_CH_GPRS1,
+ DMAC0_CH_USIM,
+ DMAC0_CH_I2S0_TX, /*or DMAC0_CH_TDM_TX*/
+ DMAC0_CH_I2S0_RX0, /*or DMAC0_CH_TDM_RX*/
+ DMAC0_CH_I2S1_TX, /*or DMAC0_CH_TDM_TX*/
+ DMAC0_CH_I2S1_RX0, /*or DMAC0_CH_TDM_RX*/
+ DMAC0_CH_SPIFC0_TX,
+ DMAC0_CH_SPIFC0_RX,
+ DMAC0_CH_SSP1_TX,
+ DMAC0_CH_SSP1_RX,
+ DMAC0_CH_UART2_TX, /*or DMAC0_CH_I2S0_RX1*/
+ DMAC0_CH_UART2_RX, /*or DMAC0_CH_I2S1_RX1*/
+ DMAC0_CH_EMBMS,
+ DMAC0_CH_USIM1,
+ DMAC0_CH_M2M_TX,
+ DMAC0_CH_M2M_RX,
+ DMAC0_CH_MEMORY, /*ÓÃÓÚÉêÇëDMAC0ÉϵĿÕÏÐͨµÀ*/
+}T_Dma_Peripheral_Id;
+#elif defined (_CHIP_ZX297520V2)
+typedef enum
+{
+/*DMAC0ͨµÀºÅ¶¨Òå*/
+ DMAC0_CH_UART0_TX = 0,
+ DMAC0_CH_UART0_RX,
+ DMAC0_CH_UART1_TX,
+ DMAC0_CH_UART1_RX,
+ DMAC0_CH_SSP0_TX,
+ DMAC0_CH_SSP0_RX,
+ DMAC0_CH_GPRS0,
+ DMAC0_CH_GPRS1,
+ DMAC0_CH_USIM,
+ DMAC0_CH_I2S0_TX,
+ DMAC0_CH_I2S0_RX,
+ DMAC0_CH_I2S1_TX,
+ DMAC0_CH_I2S1_RX,
+ DMAC0_CH_SPIFC0_TX,
+ DMAC0_CH_SPIFC0_RX,
+ DMAC0_CH_SSP1_TX,
+ DMAC0_CH_SSP1_RX,
+ DMAC0_CH_UART2_TX,
+ DMAC0_CH_UART2_RX,
+ DMAC0_CH_MEMORY, /*ÓÃÓÚÉêÇëDMAC0ÉϵĿÕÏÐͨµÀ*/
+}T_Dma_Peripheral_Id;
+#endif
+
+/*----DMA Transfer Control Set------*/
+typedef enum
+{
+ DMA_DISABLE = 0, /*disable DMA transmission*/
+ DMA_ENABLE = 1, /*enable DMA transmission*/
+
+ DMA_ENABLE_ALL
+}T_DMA_ENABLE;
+
+
+/*----DMA Request mode set------*/
+typedef enum
+{
+ DMA_PERIPHERAL_REQ = 0, /*peripheral request*/
+ DMA_SOFT_REQ = 1, /*soft request for single transfer*/
+ DMA_REQ_MOD_ALL
+}T_DMA_REQ_MOD;
+
+/*----DMA Source or Dest address mode------*/
+typedef enum
+{
+ DMA_ADDRMOD_RAM = 0, /*RAM mode, address will increase when transmission*/
+ DMA_ADDRMOD_FIFO = 1, /*FIFO mode, address will not change during transmission*/
+
+ DMA_ADDRMOD_ALL
+}T_DMA_ADDR_MOD;
+
+/*----DMA IRQ Mode------*/
+typedef enum
+{
+ DMA_ALL_IRQ_DISABLE = 0, /*½ûÄÜËùÓÐÖжÏ*/
+ DMA_TC_IRQ_ENABLE = 1, /*Íê³ÉÖжÏʹÄÜ*/
+ DMA_ERR_IRQ_ENABLE =2, /*´«ÊäºÍÅäÖôíÎóÖжÏʹÄÜ*/
+ DMA_ALL_IRQ_ENABLE = 3, /*ʹÄÜËùÓÐÖжÏ*/
+
+ DMA_IRQMOD_ALL
+}T_DMA_IRQ_MOD;
+
+/*----DMA Burst Size------*/
+typedef enum
+{
+ DMA_BURST_SIZE_8BIT = 0,
+ DMA_BURST_SIZE_16BIT = 1,
+ DMA_BURST_SIZE_32BIT = 2,
+ DMA_BURST_SIZE_64BIT = 3,
+ DMA_BURST_SIZE_128BIT = 4,
+ DMA_BURST_SIZE_ALL
+}
+T_DMA_BURST_SIZE;
+
+
+/*----DMA Burst Len------*/
+typedef enum
+{
+ DMA_BURST_LEN_1 = 0, /* 1 tranfer in each burst*/
+ DMA_BURST_LEN_2 , /* 2 tranfers in each burst*/
+ DMA_BURST_LEN_3 , /* 3 tranfers in each burst*/
+ DMA_BURST_LEN_4 , /* 4 tranfers in each burst*/
+ DMA_BURST_LEN_5 , /* 5 tranfers in each burst*/
+ DMA_BURST_LEN_6 , /* 6 tranfers in each burst*/
+ DMA_BURST_LEN_7 , /* 7 tranfers in each burst*/
+ DMA_BURST_LEN_8 , /* 8 tranfers in each burst*/
+ DMA_BURST_LEN_9 , /* 9 tranfers in each burst*/
+ DMA_BURST_LEN_10, /* 10 tranfers in each burst*/
+ DMA_BURST_LEN_11 , /* 11 tranfers in each burst*/
+ DMA_BURST_LEN_12 , /* 12 tranfers in each burst*/
+ DMA_BURST_LEN_13 , /* 13 tranfers in each burst*/
+ DMA_BURST_LEN_14 , /* 14 tranfers in each burst*/
+ DMA_BURST_LEN_15 , /* 15 tranfers in each burst*/
+ DMA_BURST_LEN_16 , /* 16 tranfers in each burst*/
+
+ DMA_BURST_LEN_ALL
+}
+T_DMA_BURST_LEN;
+
+/*----DMA Int Select------*/
+typedef enum
+{
+ DMA_INT_TO_PS,
+ DMA_INT_TO_PHY,
+ DMA_INT_TO_M0,
+ DMA_INT_SEL_ALL
+}T_DMA_INT_SEL;
+typedef enum
+{
+ DMA_INT_ERR, /*transmission error*/
+ DMA_INT_END, /*transmission done*/
+
+ MAX_DMA_INT
+} T_ZDrvDma_IntStatus; /*T_HalDma_IntStatus;*/
+
+/*----DMA Control reg para------*/
+typedef struct _T_DMA_CONTROL
+{
+ T_DMA_REQ_MOD BurstReqMod; /*DMA Request mode*/
+ T_DMA_ADDR_MOD SrcMod; /*DMA Source address mode*/
+ T_DMA_ADDR_MOD DestMod; /*DMA Destination address mode*/
+ T_DMA_IRQ_MOD IrqMod;
+ T_DMA_BURST_SIZE SrcBurstSize; /*DMA burst size£¬ÍâÉèÄÚ´æ¼ä´«ÊäʱҪÂú×ãCountÊÇ
+ max(SrcBurstSize,DestBurstSize)µÄÕûÊý±¶*/
+ T_DMA_BURST_LEN SrcBurstLen;
+ T_DMA_BURST_SIZE DestBurstSize; /*DMA burst size£¬ÍâÉèÄÚ´æ¼ä´«ÊäʱҪÂú×ãCountÊÇ
+ max(SrcBurstSize,DestBurstSize)µÄÕûÊý±¶*/
+ T_DMA_INT_SEL IntSel; /* select witch core will deal with the dma int*/
+} T_DMA_CONTROL;
+
+/*----DMA channel para ------*/
+typedef struct
+{
+ UINT32 SrcAddr; /*DMA source address*/
+ UINT32 DestAddr; /*DMA Destination address*/
+ UINT16 Count; /*һά´«Êäʱ´«ÊäµÄÊý¾Ý×Ü×Ö½ÚÊý*/
+ UINT16 YCount; /*һά´«ÊäʱΪ0*/
+ UINT16 ZCount; /*һά´«ÊäʱΪ0*/
+ UINT16 SrcYstep; /*һά´«ÊäʱΪ0*/
+ UINT16 SrcZstep; /*һά´«ÊäʱΪ0*/
+ UINT16 DestYstep; /*һά´«ÊäʱΪ0*/
+ UINT16 DestZstep; /*һά´«ÊäʱΪ0*/
+ UINT32 LLI; /*Á´±íµØÖ·£¬²»ÊÇÁ´±í´«Êäʱһ¶¨ÒªÉèΪ0*/
+ T_DMA_CONTROL CONTROL;
+}T_ZDrvDma_ChannelDef;
+
+typedef struct
+{
+ UINT32 SrcAddr; /*DMA source address*/
+ UINT32 DestAddr; /*DMA Destination address*/
+ UINT16 Count; /*һά´«Êäʱ´«ÊäµÄÊý¾Ý×Ü×Ö½ÚÊý*/
+}T_ZDrvDma_EmbmsChannelDef;
+
+/*----DMA Group------*/
+typedef enum
+{
+ DMA_GROUP_1234_5678 = 0,
+ DMA_GROUP_2341_5678 ,
+ DMA_GROUP_3412_5678 ,
+ DMA_GROUP_4123_5678 ,
+ DMA_GROUP_1234_6785 ,
+ DMA_GROUP_2341_6785 ,
+ DMA_GROUP_3412_6785 ,
+ DMA_GROUP_4123_6785 ,
+ DMA_GROUP_1234_7856 ,
+ DMA_GROUP_2341_7856 ,
+ DMA_GROUP_3412_7856 ,
+ DMA_GROUP_4123_7856 ,
+ DMA_GROUP_1234_8567 ,
+ DMA_GROUP_2341_8567 ,
+ DMA_GROUP_3412_8567 ,
+ DMA_GROUP_4123_8567 ,
+ DMA_GROUP_5678_1234 ,
+ DMA_GROUP_5678_2341 ,
+ DMA_GROUP_5678_3412 ,
+ DMA_GROUP_5678_4123 ,
+ DMA_GROUP_6785_1234 ,
+ DMA_GROUP_6785_2341 ,
+ DMA_GROUP_6785_3412 ,
+ DMA_GROUP_6785_4123 ,
+ DMA_GROUP_7856_1234 ,
+ DMA_GROUP_7856_2341 ,
+ DMA_GROUP_7856_3412 ,
+ DMA_GROUP_7856_4123 ,
+ DMA_GROUP_8567_1234 ,
+ DMA_GROUP_8567_2341 ,
+ DMA_GROUP_8567_3412 ,
+ DMA_GROUP_8567_4123 ,
+ DMA_GROUP_ALL
+}
+T_DMA_GROUP_ORDER;
+
+/*----DMA Group Arbi Mode------*/
+typedef enum
+{
+ DMA_MODE_RR = 0, /*ÂÖѯ·½Ê½,DMA·Ö×éÎÞЧ*/
+ DMA_MODE_8PRI, /*ÿËĸöͨµÀÒ»×飬°´ÇëÇóÏß´ÓµÍλµ½¸ßλ·Ö³É8×é
+ Àý:1234_5678,1>2>3>4>5>6>7>8*/
+ DMA_MODE_4PRI, /*Àý:1234_5678,1>2>3>4,5>6>7>8,1234Óë5678×é¼äͬÓÅÏȼ¶*/
+ DMA_MODE_2PRI, /*Àý:1234_5678,1234>5678*/
+ DMA_MODE_ALL
+}
+T_DMA_GROUP_MODE;
+
+/*----T_DMA_STATUS------*/
+typedef enum
+{
+ DMA_TRANSFER_DONE = 0,
+ DMA_CFG_ERROR,
+ DMA_NOT_DONE,
+
+ DMA_STATUS_ALL
+}
+T_DMA_STATUS;
+
+typedef VOID (*zDrvDma_CallbackFunc)(T_ZDrvDma_IntStatus);
+
+/****************************************************************************
+* Global Function Prototypes
+****************************************************************************/
+/*******************************************************************************
+* Function: zDrvDma_SetPriority
+* Description:
+* Parameters:dmacID :DMAC0¡¢DMAC1
+* groupOrder:ÓÅÏȼ¶·Ö×é˳Ðò1 2 3 4 5 6 7 8 ÿËĸöͨµÀÒ»×飬°´ÇëÇóÏߴӵ͵½¸ß
+ ·ÖΪ8×é¡£
+ groupMode:ÓÅÏȼ¶·Ö×éģʽ£¬ DMA_MODE_RR : ÂÖѯ·½Ê½£¬²»·Ö×飬ÎÞÓÅÏȼ¶²î±ð
+ DMA_MODE_8PRI:ÿËĸöͨµÀÒ»×飬°´ÇëÇóÏß´ÓµÍλµ½¸ßλ·Ö³É8×é
+ Àý:1234_5678,1>2>3>4>5>6>7>8
+ DMA_MODE_4PRI: Àý:1234_5678,1>2>3>4,5>6>7>8,1234Óë5678×é¼äͬÓÅÏȼ¶
+ DMA_MODE_2PRI: Àý:1234_5678,1234>5678
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvDma_SetPriority(T_ZDrv_DmaId dmacID, T_DMA_GROUP_ORDER groupOrder, T_DMA_GROUP_MODE groupMode);
+
+/*******************************************************************************
+* Function: zDrvDma_Initiate
+* Description: reset dma controller,the reset line will hold 2ms
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvDma_Initiate(VOID);
+
+
+/*******************************************************************************
+* Function: zDrvDma_AllocChannel
+* Description:
+ for users, they don't konw with channel chould be used to do the transfer.
+ so they should first call this function to get a free channel id;
+
+ afer dma transfer is over , zDrvDma_DeAllocChannel should be called to release the
+ channedl resoure
+* Parameters:
+* Input:
+* peripheralID: peripheral request line defined by structure T_Dma_Peripheral_Id
+
+* Output:
+*
+* Returns:
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvDma_AllocChannel(T_Dma_Peripheral_Id peripheralID);
+
+
+/**************************************************************************
+* Function: zDrvDma_ConfigChannel
+* Description:
+* Parameters:
+* Input:
+* channelID: the return value from zDrvDma_AllocChannel
+* tChanPar:parameter of channel
+* CallBack:when dma transfer is over, isr will call cbk
+
+* Output: None
+* Returns:
+* T_ZDrvDma_Ret
+* Others:
+* 1. ÔÚÔ´»òÄ¿µÄµØÖ·Ö»ÒªÓÐÒ»¶ËÓй̶¨µØÖ·£¬¼´T_DMA_ADDR_MODΪ
+* DMA_ADDRMOD_FIFOʱ£¬tChanPar µÄCount ±ØÐëÊǽϴóburstsize
+* µÄÕûÊý±¶!!!
+* 2.ÔÚ BurstReqMod = DMA_PERIPHERAL_REQʱ£¬ÐèÒªÌرð×¢Òâ:Èç¹û¶ÔÓ¦ÍâÉèÖ»ÄܲúÉú
+* burstÇëÇó¶øûÓÐsingleÇëÇóÊä³ö¹¦ÄÜ£¬ÄÇôtChanPar µÄCount ±ØÐëÊÇburstsize*burstlen
+* µÄÕûÊý±¶!!!
+* 3.SrcAddrºÍDestAddrÒªÇóΪburstsizeµÄÕûÊý±¶£¬¼´ÒÔburstsizeΪµ¥Î»µØÖ·¶ÔÆë¡£
+* 4.tChanPar µÄ²ÎÊýCount µÄȡֵҪСÓÚµÈÓÚ64K-1×Ö½Ú£¬Countµ¥Î»Îª×Ö½Ú!!
+**************************************************************************/
+SINT32 zDrvDma_ConfigChannel(UINT32 channelID,T_ZDrvDma_ChannelDef tChanPar);
+
+/**************************************************************************
+* Function: zDrvDma_StartChannel
+* Description:
+* Parameters:
+* Input:
+* channelID: the return value from zDrvDma_AllocChannel
+* CallBack:if not null, when dma transfer is over, 'callback' will be called in the dma isr
+ isBlock: if set true, the process will be suspended until the dma transfer is done
+* Output: None
+* Returns:
+* T_ZDrvDma_Ret
+* Others: None
+**************************************************************************/
+SINT32 zDrvDma_StartChannel(UINT32 channelID, zDrvDma_CallbackFunc CallBack, T_ZDrvDma_IsBlock isBlock);
+
+
+/*******************************************************************************
+* Function: zDrvDma_DeAllocChannel
+* Description:ÊÍ·ÅÒѾÉêÇë³É¹¦µÄDMA ͨµÀ£¬ÈçûÓÐÉêÇë³É¹¦Ôò²»ÄÜÊÍ·Å
+* Ò»°ãÔÚ¸ÃDMAͨµÀÅäÖ÷µ»Ø´íÎóÐÅÏ¢»òʹÓÃÕß²»ÔÙʹÓøÃDMAͨµÀ
+* ʱµ÷Óô˺¯Êý¡£
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+* Others:ÈôΪ×èÈû´«Êä(zDrvDma_StartChannelµÄisBlock²ÎÊýΪTRUE)
+* ÏàͬͨµÀµÄzDrvDma_DeAllocChannel±ØÐëÔÚºÍzDrvDma_StartChannelͬһ¸öÏ̱߳»µ÷ÓÃ
+* ·ñÔò¿ÉÄܻᵼÖµ÷ÓÃzDrvDma_StartChannelµÄÏß³ÌÒòdmaδÀ´Íê³ÉÖж϶øÓÀÔ¶ÏÝËÀ
+********************************************************************************/
+SINT32 zDrvDma_DeAllocChannel(UINT32 channelID);
+/**************************************************************************
+* Function: zDrvDma_GetTransferNumber
+* Description:»ñÈ¡ucChannel ´ú±íµÄͨµÀµÄÊý¾ÝµÄ´«ÊäÊ£Óà´óС
+* Parameters:
+* Input: zDrvDma_AllocChannel µÄ·µ»ØÖµ:¸ß16λ:dma¿ØÖÆÆ÷µÍ16λ:ͨµÀºÅ(0~15)
+* Output: None
+* Output: None
+* Returns:
+* None
+* Others: None
+**************************************************************************/
+UINT32 zDrvDma_GetTransferNumber(UINT32 ucChannel);
+
+/**************************************************************************
+* Function: zDrvDma_DisableChannel
+* Description: Ç¿ÖÆÍ£Ö¹ucChannelËùָͨµÀºÅµÄ´«Êä¡£
+* Í£Ö¹ºóÈôÏëÖØÐÂÆô¶¯´«Ê䣬ÐèÖØÐÂÅäÖòÎÊý¡£
+* Parameters:
+* Input:
+* ucChannel: zDrvDma_AllocChannelµÄ·µ»ØÖµ¡£
+* Output: None
+* Returns:
+*
+* Others: ´Ëº¯ÊýÍ£Ö¹DMA´«Ê䣬²»ÊÇÔÝÍ£¡£
+**************************************************************************/
+SINT32 zDrvDma_DisableChannel(UINT32 ucChannel);
+
+/**************************************************************************
+* Function: zDrvDma_GetStatus
+* Description:Ê¡µçרÓýӿڣ¬ÓÃÓÚ²»²úÉúÖжϵÄDMA´«Êä
+* Parameters:
+* Input: zDrvDma_AllocChannel µÄ·µ»ØÖµ:¸ß16λ:dma¿ØÖÆÆ÷µÍ16λ:ͨµÀºÅ(0~15)
+* Output: None
+* Returns:
+* DMA_TRANSFER_DONE: channelID 's dma transfer has done.
+* DMA_CFG_ERROR:something wrong with channelID's dma configuration
+* DMA_NOT_DONE: if dma not done and dma config has no problem,return this value.
+*
+* Others: None
+**************************************************************************/
+T_DMA_STATUS zDrvDma_GetStatus(UINT32 channelID);
+
+/**************************************************************************
+* Function: zDrvDma_ConfigLLI
+* Description:Ê¡µçרÓýӿڣ¬ÓÃÓÚ²»²úÉúÖжϵÄDMA´«Êä
+* Parameters:
+* Input: channelID:zDrvDma_AllocChannel µÄ·µ»ØÖµ:¸ß16λ:dma¿ØÖÆÆ÷µÍ16λ:ͨµÀºÅ(0~15)
+ channelaPara:DMA²ÎÊýÊý×é
+ LLIParaCnt:Êý×éÔªËظöÊý:×î´óΪ32
+ isLoop:TRUE--Ñ»·´«ËÍ FALSE--normal
+* Output: None
+* Returns:
+*
+* Others: None
+**************************************************************************/
+SINT32 zDrvDma_ConfigLLI(UINT32 channelID,T_ZDrvDma_ChannelDef channelaPara[], UINT32 LLIParaCnt, BOOL isLoop);
+
+/*******************************************************************************
+* Function: zDrvDma_Mem2MemForEmbms
+* Description:
+ this function implement a mem to mem dma transfer function,
+ note: the memery involved must be set to non-cacheable
+* Parameters:
+* Input:
+* embmsChannel:
+ LLIParaCnt:number of embmsChannel[]
+ CallBack: callback func
+* Output:
+*
+* Returns:
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvDma_Mem2MemForEmbms(T_ZDrvDma_EmbmsChannelDef embmsChannel[], UINT32 LLIParaCnt, zDrvDma_CallbackFunc CallBack);
+
+#endif/*_DRVS_DMA_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_dpram.h b/cp/ps/driver/inc/misc/drvs_dpram.h
new file mode 100644
index 0000000..05e33f4
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_dpram.h
@@ -0,0 +1,696 @@
+/*******************************************************************************
+ * Copyright by ZTE Corporation.
+ *
+ * File Name: drvs_dpram.h
+ * File Mark:
+ * Description: dpram interface declaration(W&TD).
+ * Others:
+ * Version: v0.1
+ * Author: shideyou
+ * Date: 2013-6-19
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_DPRAM_H
+#define _DRVS_DPRAM_H
+
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+//#include "ps_ephy_interface.h"
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+/****************************************************************************
+* Types
+****************************************************************************/
+typedef enum
+{
+ DPRAM_RAT_W,
+ DPRAM_RAT_TD,
+ DPRAM_RAT_LTE,
+
+ MAX_DPRAM_RAT
+}
+T_ZDrvDpram_Rat;
+
+/* error code define */
+typedef enum
+{
+ DPRAM_RET_SUCCESS = 0, /* successed */
+ DPRAM_RET_ERROR = 1, /* error occured */
+ DPRAM_RET_ERR_INVALID_PARAM = 2, /* the input parameter is invalid */
+ DPRAM_RET_ERR_NO_MEMORY = 3, /* no enough memory in dpram to store data of the required length */
+ DPRAM_RET_ERR_NO_DATA = 4, /* no data in ring */
+ DPRAM_RET_ERR_NOT_INITIALIZED = 5, /* not initialized yet */
+
+ MAX_DPRAM_ERR_CODE
+} T_ZDrvDpram_RetCode;
+
+typedef enum
+{
+ DPRAM_DATA_UL_PHY,
+ DPRAM_DATA_HSUPA,
+ DPRAM_DATA_BCH,
+ DPRAM_DATA_DL_PHY,
+ DPRAM_DATA_HSDPA,
+ DPRAM_DATA_EAGCH,
+
+ MAX_DPRAM_DATA_ID
+} T_ZDrvDpram_DataId; //used for TD
+
+/* will be invoked when command has been received
+ uiCmdId: command id
+ pData: command data
+ uiLen: length of command data. unit: byte
+ */
+
+typedef enum
+{
+ DPRAM_MSG_CFNSFN = 0xFF,
+ DPRAM_MSG_EXCEPT = 0xFE,
+
+ MAX_DPRAM_OTHER_MSG
+} T_ZDrvDpram_OtherMsg;
+
+
+typedef struct
+{
+ UINT32 uiCfn;
+ UINT32 uiSubfn;
+ UINT32 uiSfn;
+ UINT32 uiRtCfn;
+ UINT32 uiRtSfn;
+} T_ZDrvDpram_CfnSfnForW;
+
+typedef struct
+{
+ UINT32 uiMemBaseAddr; /* base address of dpram memory */
+ //UINT32 uiRegBaseAddr; /* base address of doram register */
+ UINT32 uiMemSize; /* memroy size of dpram */
+ BOOL bBigEndian; /* big-endian if true, else little-endian */
+} T_ZDrvDpram_Info; //used for TD
+
+#if 0
+typedef enum
+{
+ DPRAM_UPA_ADDR_1 ,
+ DPRAM_UPA_ADDR_2 ,
+
+ MAX_DPRAM_UPAAddr_ID
+} T_ZDrvDpram_UPAAddrSel;
+#endif
+
+/*used by td*/
+typedef enum
+{
+ ARMTOZSP_INT1 =0, /*in order to let sleep time tell zsp ,ÖеÚ0bitÓ÷¨ÊÇ֪ͨÎïÀí²ãϵͳ˯Ãßʱ¼ä */
+ ARMTOZSP_INT2 =1, /*ÆäÖеÚ1bitÓ÷¨ÊÇ֪ͨÎïÀí²ãϵͳ˯Ãßʱ¼ä,ÓÐÐÒéÕ»ÏûÏ¢£¬sendcmd ·¢mailboxÖжϻ½ÐÑzsp*/
+ ARMTOZSP_INT3 = 2,/*used in HSUPA*/
+ ARMTOZSP_INT4 = 3, //ps wakeup phy
+ MAX_ARMTOZSPINT = 100
+
+}T_ZDrvIcp_IntType; //used for TD
+
+
+typedef struct
+{
+ UINT32 uiCfn;
+ UINT32 uiSfn;
+} T_ZDrvDpram_CfnSfn; //used for TD
+
+typedef UINT32 (*ZDRV_DPRAM_CMD_RECVFUNC)(UINT16 uiCmdId, VOID *pData, UINT16 uiLen);
+
+typedef struct
+{
+ ZDRV_DPRAM_CMD_RECVFUNC fCmdRecv;
+} T_ZDrvDpram_CallbackFuncs;
+
+typedef VOID (*ZDRV_DPRAM_ISR_CALLBACK)( VOID );
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+
+/**************************************************************************
+* Functin: zDrvWDpram_RegCallback
+* Description: This function is used to register the interrupt callback function.
+* Parameters:
+* (IN)
+* ptCallbackStruct: callback functions struct pointer.
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERROR: failed.
+* Others:
+* None.
+**************************************************************************/
+extern SINT32 zDrvWDpram_RegCallback(T_ZDrvDpram_CallbackFuncs *ptCallbackStruct );
+/**************************************************************************
+* Functin: zDrvDpram_SendCmdForW
+* Description: This function is used to send command.
+* Parameters:
+* (IN)
+* uiCmdId: cmd id.
+* pData: cmd data pointer
+* uiLen: cmd data length. uint: byte. must be multiples of 4. maybe 0 for null command
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* DPRAM_RET_ERR_NO_MEMORY: no enough space to send this command.
+* Others:
+* None.
+**************************************************************************/
+//extern UINT32 zDrvDpram_SendCmdForW( UINT16 uiCmdId, VOID *pData, UINT16 uiLen );
+/**************************************************************************
+* Functin: zDrvWDpram_FrameInfoGet
+* Description: This function is used to get the frameinfo block.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* ppBlockAddr: pointer to store address of databuf in block.
+* puiBlockLen: pointer to store length of databuf in block. uint: byte
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERROR: unknow error
+* DPRAM_RET_ERR_NO_DATA: no data.
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvWDpram_FrameInfoGet(VOID **ppBlockAddr, UINT32 *puiRealLen);
+/**************************************************************************
+* Functin: zDrvWDpram_FrameInfoFree
+* Description: This function is used to free the frameinfo block.
+* Parameters:
+* (IN)
+* pBlockAddr: pointer to store address of databuf in block.
+* (OUT)
+* None
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvWDpram_FrameInfoFree(VOID *pBlockAddr);/*ΪÁ˱ÜÃâÎïÀí²ãƵ·±Ð´Ö¡ÖжÏÐÅÏ¢£¨Õë¶Ô10msʱ²»ÊÇÿ¸ö×ÓÖ¡µÄÖ¡ÖжÏÐÅÏ¢¶¼ÓÐЧ£©£¬Òò´Ë£¬ÐÒéÕ»ÔÚ¶ÁÍêÖ¡ÖжÏÐÅÏ¢ºó×îºÃÇå³ýÖ¡ÖжÏÐÅÏ¢¡£Çå³ý¶¯×÷Ôڴ˺¯ÊýÖд¦Àí*/
+/**************************************************************************
+* Functin: zDrvWDpram_UlDataGet
+* Description: This function is used to get the free block of UL data.
+* Parameters:
+* (IN)
+* None
+* (OUT)
+* pBlockAddr: pointer to store address of databuf in block.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERROR: unknow error
+* DPRAM_RET_ERR_NO_MEMORY: no free block.
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvWDpram_UlDataGet(VOID **pBlockAddr);
+/**************************************************************************
+* Functin: zDrvWDpram_UlDataSend
+* Description: This function is used to send ul data.
+* Parameters:
+* (IN)
+* pBlockAddr: ul data pointer.
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvWDpram_UlDataSend(VOID *pBlockAddr);
+/**************************************************************************
+* Functin: zDrvDpram_GetDlDataForW
+* Description: This function is used to get dl data.
+* Parameters:
+* (IN)
+* Ret: DPRAM_RET_W.
+* (OUT)
+* ppBlockAddr: pointer to store address of databuf in block.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* DPRAM_RET_ERR_NO_DATA: no data.
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvDpram_GetDlDataForW(VOID **ppBlockAddr, T_ZDrvDpram_Rat Rat);
+/**************************************************************************
+* Functin: zDrvWDpram_PsDlDataFree
+* Description: This function is used to free the DL data block.
+* Parameters:
+* (IN)
+* Ret: DPRAM_RET_W.
+* ppBlockAddr: pointer to store address of databuf in block.
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvWDpram_PsDlDataFree(VOID *pBlockAddr, T_ZDrvDpram_Rat Rat);
+/**************************************************************************
+* Functin: zDrvWDpram_UpaDataGet
+* Description: This function is used to get the free block of upadata.
+* Parameters:
+* (IN)
+* uiHARQId
+* (OUT)
+* ppBlockAddr: pointer to store address of upadata in block.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* DPRAM_RET_ERR_NO_MEMORY: no free block.
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvWDpram_UpaDataGet(UINT8 uiHARQId, VOID **ppBlockAddr);
+/**************************************************************************
+* Functin: zDrvWDpram_UpaDataSend
+* Description: This function is used to send upa data.
+* Parameters:
+* (IN)
+* uiHARQId: harq id of upa data.
+* pBlockAddr:upa data pointer
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvWDpram_UpaDataSend(UINT8 uiHARQId, VOID *pBlockAddr);
+
+#if 0
+/**************************************************************************
+* Functin: zDrvDpram_GetUpaPhyBufAddrForW
+* Description: This function is used to get UPA buffer data of phy.
+* Parameters:
+* (IN)
+* uiHARQId: harq id of upa data.
+* cho: 0 or 1
+* (OUT)
+* ppBlockAddr: pointer to store address of phy databuf .
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvDpram_GetUpaPhyBufAddrForW(UINT8 uiHARQId, VOID **ppBlockAddr, T_ZDrvDpram_UPAAddrSel addsel);
+
+#endif
+/**************************************************************************
+* Functin: zDrvWDpram_GrantMonitorReqSend
+* Description: This function is used to send GrantMonitor request.
+* Parameters:
+* (IN)
+* pBlockAddr: address of GrantMonitor request.
+* uiLen:length of data
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_ERR_NO_MEMORY: PHY is processing
+* DPRAM_RET_SUCCESS: successed.
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvWDpram_GrantMonitorReqSend(VOID *pBlockAddr, UINT16 uiLen);
+
+/**************************************************************************
+* Functin: zDrvWDpram_UlDataFree
+* Description: This function is used to get free data of UL.
+* Parameters:
+* (IN)
+* pBlockAddr: address of UL.
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_ERR_NO_DATA: no data in this buf
+* DPRAM_RET_SUCCESS: successed.
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvWDpram_UlDataFree(VOID *pBlockAddr);
+
+/**************************************************************************
+* Functin: zDrvWDpram_PsDlDataGet
+* Description: This function is used to get free data of DL.
+* Parameters:
+* (IN)
+* uiLen:length of data
+* (OUT)
+* ppBlockAddr: address of DL free data.
+* Returns:
+* DPRAM_RET_ERR_NO_MEMORY: no free memory
+* DPRAM_RET_SUCCESS: successed.
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvWDpram_PsDlDataGet(VOID **ppBlockAddr, UINT16 uiLen);
+
+/**************************************************************************
+* Functin: zDrvWDpram_UpaDataFree
+* Description: This function is used to send GrantMonitor request.
+* Parameters:
+* (IN)
+* pBlockAddr: address of GrantMonitor request.
+* uiHARQId: id of harq
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_ERR_NO_DATA: no data in this buf
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+extern UINT32 zDrvWDpram_UpaDataFree(UINT8 uiHARQId, VOID *pBlockAddr);
+
+/*-------------------------used for TD---------------------------*/
+/**************************************************************************
+* Functin: zDrvTDpram_Initiate
+* Description: This function is used to initialize dpram.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERROR: error
+* DRV_ERR_NOT_SUPPORTED: this device don't support open operation.
+* others: others error code. for detailed information, please refer to the header file of hal layer
+* Others:
+* None.
+**************************************************************************/
+SINT32 zDrvTDpram_Initiate( VOID );
+
+/**************************************************************************
+* Functin: zDrvTDpram_RegCallback
+* Description: This function is used to register the interrupt callback function.
+* Parameters:
+* (IN)
+* ptCallbackStruct: callback functions struct pointer.
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERROR: failed.
+* Others:
+* None.
+**************************************************************************/
+UINT32 zDrvTDpram_RegCallback( T_ZDrvDpram_CallbackFuncs *ptCallbackStruct );
+
+
+/**************************************************************************
+* Functin: zDrvDpram_SendCmd
+* Description: This function is used to send command.
+* Parameters:
+* (IN)
+* uiCmdId: cmd id.
+* pData: cmd data pointer
+* uiLen: cmd data length. uint: byte. must be multiples of 4. maybe 0 for null command
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* DPRAM_RET_ERR_NO_MEMORY: no enough space to send this command.
+* Others:
+* None.
+**************************************************************************/
+//UINT32 zDrvDpram_SendCmd( UINT16 uiCmdId, VOID *pData, UINT16 uiLen );
+
+
+/**************************************************************************
+* Functin: zDrvDpram_GetFreeData
+* Description: This function is used to get the free block.
+* Parameters:
+* (IN)
+* uiDataId: T_ZDrvDpram_DataId.
+* (OUT)
+* ppBlockAddr: pointer to store address of databuf in block.
+* puiBlockLen: pointer to store length of databuf in block. uint: byte
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* DPRAM_RET_ERR_NO_MEMORY: no free data space.
+* Others:
+* None.
+**************************************************************************/
+//UINT32 zDrvDpram_GetFreeData ( UINT8 uiDataId, VOID **ppBlockAddr, UINT16 *puiBlockLen );
+
+
+/**************************************************************************
+* Functin: zDrvDpram_SendData
+* Description: This function is used to send data.
+* Parameters:
+* (IN)
+* uiDataId: T_ZDrvDpram_DataId.
+* ppBlockAddr: base address of databuf in block.
+* uiDataLen: data length. uint: byte
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* DPRAM_RET_ERR_NO_MEMORY: no enough space to send this data.
+* Others:
+* None.
+**************************************************************************/
+//UINT32 zDrvDpram_SendData( UINT8 uiDataId, VOID *ppBlockAddr, UINT16 uiDataLen );
+
+
+/**************************************************************************
+* Functin: zDrvDpram_DataExist
+* Description: This function is used to check if there is data.
+* Parameters:
+* (IN)
+* uiDataId: T_ZDrvDpram_DataId.
+* (OUT)
+* None.
+* Returns:
+* TRUE: have data; FALSE: no data.
+* Others:
+* None.
+**************************************************************************/
+//BOOL zDrvDpram_DataExist( UINT8 uiDataId ); /*zyj,20110330*/
+
+/**************************************************************************
+* Functin: zDrvDpram_GetData
+* Description: This function is used to get data.
+* Parameters:
+* (IN)
+* puiDataId: pointer to stord data id. T_ZDrvDpram_DataId.
+* (OUT)
+* ppBlockAddr: pointer to store address of databuf in block.
+* puiRealLen: pointer to store data length. uint: byte
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* DPRAM_RET_ERR_NO_DATA: no data.
+* Others:
+* None.
+**************************************************************************/
+//UINT32 zDrvDpram_GetData( UINT8 uiDataId, VOID **ppBlockAddr, UINT16 *puiRealLen );
+
+/**************************************************************************
+* Functin: zDrvDpram_FreeData
+* Description: This function is used to free the data block.
+* Parameters:
+* (IN)
+* uiDataId: T_ZDrvDpram_DataId.
+* pBlockAddr: base address of databuf in block.
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+//UINT32 zDrvDpram_FreeData( UINT8 uiDataId, VOID *pBlockAddr );
+
+
+/**************************************************************************
+* Functin: zDrvTDpram_GetInfo
+* Description: This function is used to get the dpram information, such as base address.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* ptInfo: information pointer.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+UINT32 zDrvTDpram_GetInfo( T_ZDrvDpram_Info *ptInfo );
+
+#if ((defined ( _CHIP_ZX297502)||defined ( _CHIP_ZX2975)||defined ( _CHIP_ZX2960_02B)||defined ( _CHIP_ZX2804)) && defined (_USE_DPRAM_ADDR_NEWSW))
+/**************************************************************************
+* Functin: zDrvTDpram_GetUPHValue
+* Description: This function is used to get the UPH value in Dpram.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* None.
+* Returns:
+* UINT16: 2 bytes UPH Value.
+* Others:
+* None.
+**************************************************************************/
+UINT16 zDrvTDpram_GetUPHValue( VOID );
+
+
+/**************************************************************************
+* Functin: zDrvTDpram_GetSNPLValue
+* Description: This function is used to get the SNPL value in Dpram.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* None.
+* Returns:
+* UINT16: 2 bytes SNPL Value.
+* Others:
+* None.
+**************************************************************************/
+UINT16 zDrvTDpram_GetSNPLValue( VOID );
+#endif
+/**************************************************************************
+* Functin: zDrvDpram_IntGen
+* Description: This function is used to send mailbox int to zsp
+* Parameters:
+* (IN)
+* inttype
+* (OUT)
+* no
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+//SINT32 zDrvDpram_IntGen(UINT32 inttype);
+
+#ifdef _USE_PSM
+
+/**************************************************************************
+* Functin: zDrvDpram_WakeUpUphy
+* Description: This function is used to wakeup phy for ps
+* Parameters:
+* (IN)
+* no
+* (OUT)
+* no
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+//extern VOID zDrvDpram_WakeUpUphy(VOID);//ps»½ÐÑphy
+
+#endif
+
+
+/**************************************************************************
+* Functin: zDrvDpram_L1tqueueFlag
+* Description: ÅжÏzspÊÇ·ñΪ¿ÕÏУ¬Èç¹û¿ÕÏз¢maiblox»½ÐÑzsp£¬²¢ÇÒÖ±dpramΪ0xa
+* Parameters:
+* (IN)
+* no
+* (OUT)
+* no
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+
+
+//VOID zDrvDpram_L1tqueueFlag(VOID); /*ÅжÏ2963 l1t·ÅÏûÏ¢¶ÓÁÐÖÐÊÇ·ñÓÐÏûÏ¢*/
+/**************************************************************************
+* Functin: zDrvDpram_ClerrL1tqueueFlag
+* Description: This function is used to clear drx flag
+* Parameters:
+* (IN)
+* no
+* (OUT)
+* no
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+//VOID zDrvDpram_ClearL1tqueueFlag(VOID); /*Çå³ýl1tÏûÏ¢¶ÓÁÐÊÇ·ñÓбê־λ*/
+
+/**************************************************************************
+* Functin: zDrvDpram_MsgExist
+* Description: This function is used to check PS <-->TD buffer has msg.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* None.
+* Returns:
+* TRUE:PS <-->TD has msg
+* FALSE:PS <-->TD no msg
+* Others:
+* none
+**************************************************************************/
+//BOOL zDrvDpram_MsgExist(VOID);
+
+/**************************************************************************
+* Functin: zDrvDpram_MsgExistForW
+* Description: This function is used to check WPS ->WPHY cmd ring buffer has msg.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* None.
+* Returns:
+* TRUE:WPS ->WPHY has msg
+* FALSE:WPS <-->WPHY has no msg
+* Others:
+* none
+**************************************************************************/
+//BOOL zDrvDpram_MsgExistForW(VOID);
+
+
+
+#endif/*_FILENAME_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_dpram_td.h b/cp/ps/driver/inc/misc/drvs_dpram_td.h
new file mode 100644
index 0000000..a4ca393
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_dpram_td.h
@@ -0,0 +1,522 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: drvs_dpram_td.h
+* File Mark:
+* Description: dpram interface declaration.
+* Others:
+* Version: v1.0
+* Author: yan junhua
+* Date: 2007-10-19
+* History 1:
+* Date: 2007-12-26
+* Version: 1.1v
+* Author: yan junhua
+* Modification: modify macro defines according to IC's modification
+* different address define for different project
+* change parameter in macros sucn as IsSet_H2UINTSTAL from bit number to bitmap
+*
+*
+* History 2:
+* Date: 2008-05-07
+* Version: 1.2v
+* Author: yan junhua
+* Modification: remove macro defines
+* return base address by functions
+*
+* History 3:
+* Date: 2010-04-26
+* Version: 1.4.9
+* Author: wangxia
+* Modification: add function for HSPUA in CHIP ZX2963
+**********************************************************************/
+#ifndef _DRVS_DPRAM_TD_H
+#define _DRVS_DPRAM_TD_H
+
+
+/*************************************************************************
+ * Include files *
+ *************************************************************************/
+
+#include "drvs_dpram.h"
+/*************************************************************************
+ * Macro *
+ *************************************************************************/
+
+ /**************************************************************************
+ * Types *
+ **************************************************************************/
+
+/**************************************************************************
+ * Function Prototypes *
+ **************************************************************************/
+
+/*******************************************************************************
+* Function: zDrvTDpram_GetTdSfn
+* Description: get td sfn from dpram
+* Parameters:
+* Input:
+*
+* Output:td sfn
+*
+* Returns:
+*
+*
+*
+*
+* Others:
+********************************************************************************/
+UINT32 zDrvTDpram_GetTdSfn(void);
+
+#if 0
+/* error code define */
+typedef enum
+{
+ DPRAM_RET_SUCCESS = 0, /* successed */
+ DPRAM_RET_ERROR = 1, /* error occured */
+ DPRAM_RET_ERR_INVALID_PARAM = 2, /* the input parameter is invalid */
+ DPRAM_RET_ERR_NO_MEMORY = 3, /* no enough memory in dpram to store data of the required length */
+ DPRAM_RET_ERR_NO_DATA = 4, /* no data in ring */
+ DPRAM_RET_ERR_NOT_INITIALIZED = 5, /* not initialized yet */
+
+ MAX_DPRAM_ERR_CODE
+} T_ZDrvDpram_RetCode;
+
+typedef enum
+{
+#if (((defined ( _CHIP_ZX297502)||defined ( _CHIP_ZX2975)||defined ( _CHIP_ZX2960_02B)) && defined (_USE_DPRAM_ADDR_NEWSW))||defined ( _CHIP_ZX2804))
+ DPRAM_DATA_UL_PHY,
+ DPRAM_DATA_HSUPA,
+ DPRAM_DATA_BCH,
+ DPRAM_DATA_DL_PHY,
+ DPRAM_DATA_HSDPA,
+ DPRAM_DATA_EAGCH,
+#else
+ DPRAM_DATA_UL_PHY,
+ DPRAM_DATA_BCH,
+ DPRAM_DATA_DL_PHY,
+ DPRAM_DATA_HSDPA,
+
+#endif
+
+ MAX_DPRAM_DATA_ID
+} T_ZDrvDpram_DataId;
+
+/* will be invoked when command has been received
+ uiCmdId: command id
+ pData: command data
+ uiLen: length of command data. unit: byte
+ */
+typedef UINT32 (*ZDRV_DPRAM_CMD_RECVFUNC)( UINT16 uiCmdId, VOID *pData, UINT16 uiLen );
+typedef VOID (*ZDRV_DPRAM_ISR_CALLBACK)( VOID ); //for TD-DPRAM
+
+typedef struct
+{
+ ZDRV_DPRAM_CMD_RECVFUNC fCmdRecv;
+} T_ZDrvDpram_CallbackFuncs;
+
+typedef enum
+{
+ DPRAM_MSG_CFNSFN = 0xFF,
+ DPRAM_MSG_EXCEPT = 0xFE,
+
+ MAX_DPRAM_OTHER_MSG
+} T_ZDrvDpram_OtherMsg;
+
+typedef struct
+{
+ UINT32 uiCfn;
+ UINT32 uiSfn;
+} T_ZDrvDpram_CfnSfn;
+
+typedef struct
+{
+ UINT32 uiMemBaseAddr; /* base address of dpram memory */
+ UINT32 uiRegBaseAddr; /* base address of doram register */
+ UINT32 uiMemSize; /* memroy size of dpram */
+ BOOL bBigEndian; /* big-endian if true, else little-endian */
+} T_ZDrvDpram_Info;
+
+
+
+typedef enum
+{
+ ARMTOZSP_INT1 =0, /*in order to let sleep time tell zsp ,ÖеÚ0bitÓ÷¨ÊÇ֪ͨÎïÀí²ãϵͳ˯Ãßʱ¼ä */
+ ARMTOZSP_INT2 =1, /*ÆäÖеÚ1bitÓ÷¨ÊÇ֪ͨÎïÀí²ãϵͳ˯Ãßʱ¼ä,ÓÐÐÒéÕ»ÏûÏ¢£¬sendcmd ·¢mailboxÖжϻ½ÐÑzsp*/
+ ARMTOZSP_INT3 = 2,/*used in HSUPA*/
+ ARMTOZSP_INT4 = 3, //ps wakeup phy
+ MAX_ARMTOZSPINT = 100
+
+}T_ZDrvIcp_IntType;
+#ifdef _USE_PSM
+
+#define DPRAM_BASE_ADDR 0x19800
+#define DPRAM_TDL1SLEEP_FLAG (DPRAM_BASE_ADDR + 0x63CE)
+#define DPRAM_TDL1SLEEP_FC_ADDR (DPRAM_BASE_ADDR + 0x63D0)
+#define DPRAM_TDL1SLEEP_CC_ADDR (DPRAM_BASE_ADDR + 0x63D2)
+#define DPRAM_TDL1SLEEP_LEN_ADDR (DPRAM_BASE_ADDR + 0x63D4)
+#define DPRAM_TDL1SLEEP_FC1_ADDR (DPRAM_BASE_ADDR + 0x63D6)
+#define DPRAM_TDL1SLEEP_CC1_ADDR (DPRAM_BASE_ADDR + 0x63D8)
+#define DPRAM_DRX_ADDR (DPRAM_BASE_ADDR + 0x63DA)
+#define DPRAM_TDSLEEP_FORCE_GSM_WAKEUP_ADRR (DPRAM_BASE_ADDR + 0x63DC)
+#define DPRAM_TD_CAMPON_ADDR (DPRAM_BASE_ADDR + 0x63DE)
+#define DPRAM_L1G_WAKEUPOK_FLAG_ADDR (DPRAM_BASE_ADDR + 0x63E0)
+#define DPRAM_L1T_QUEUE_FLAG_ADDR (DPRAM_BASE_ADDR + 0x63E2)
+#define DPRAM_ZSP_CHANGE_FREQ_FLAG_ADDR (DPRAM_BASE_ADDR + 0x63E8)
+#define DPRAM_ZSP_TDT1_FLAG_ADDR (DPRAM_BASE_ADDR + 0x63EA)
+#endif
+/**************************************************************************
+ * Function Prototypes *
+ **************************************************************************/
+/**************************************************************************
+* Functin: zDrvDpram_Init
+* Description: This function is used to initialize dpram.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERROR: error
+* DRV_ERR_NOT_SUPPORTED: this device don't support open operation.
+* others: others error code. for detailed information, please refer to the header file of hal layer
+* Others:
+* None.
+**************************************************************************/
+SINT32 zDrvDpram_Init( VOID );
+
+/**************************************************************************
+* Functin: zDrvDpram_RegISRCallback
+* Description: This function is used to get the isr function. It just be used by TD Ret
+* Parameters:
+* (IN)
+* fISRCallback: isr function pointer.
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERROR: failed.
+* Others:
+* None.
+**************************************************************************/
+UINT32 zDrvDpram_RegISRCallback( ZDRV_DPRAM_ISR_CALLBACK fISRCallback ); //for TD-DPRAM
+
+/**************************************************************************
+* Functin: zDrvDpram_Exit
+* Description: This function is used to uninitialize dpram.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERROR: error
+* DRV_ERR_NOT_SUPPORTED: this device don't support open operation.
+* others: others error code. for detailed information, please refer to the header file of hal layer
+* Others:
+* None.
+**************************************************************************/
+SINT32 zDrvDpram_Exit( VOID );
+
+
+/**************************************************************************
+* Functin: zDrvTDpram_RegCallback
+* Description: This function is used to register the interrupt callback function.
+* Parameters:
+* (IN)
+* ptCallbackStruct: callback functions struct pointer.
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERROR: failed.
+* Others:
+* None.
+**************************************************************************/
+UINT32 zDrvTDpram_RegCallback( T_ZDrvDpram_CallbackFuncs *ptCallbackStruct );
+
+
+/**************************************************************************
+* Functin: zDrvDpram_SendCmd
+* Description: This function is used to send command.
+* Parameters:
+* (IN)
+* uiCmdId: cmd id.
+* pData: cmd data pointer
+* uiLen: cmd data length. uint: byte. must be multiples of 4. maybe 0 for null command
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* DPRAM_RET_ERR_NO_MEMORY: no enough space to send this command.
+* Others:
+* None.
+**************************************************************************/
+UINT32 zDrvDpram_SendCmd( UINT16 uiCmdId, VOID *pData, UINT16 uiLen );
+
+
+/**************************************************************************
+* Functin: zDrvDpram_GetFreeData
+* Description: This function is used to get the free block.
+* Parameters:
+* (IN)
+* uiDataId: T_ZDrvDpram_DataId.
+* (OUT)
+* ppBlockAddr: pointer to store address of databuf in block.
+* puiBlockLen: pointer to store length of databuf in block. uint: byte
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* DPRAM_RET_ERR_NO_MEMORY: no free data space.
+* Others:
+* None.
+**************************************************************************/
+UINT32 zDrvDpram_GetFreeData ( UINT8 uiDataId, VOID **ppBlockAddr, UINT16 *puiBlockLen );
+
+
+/**************************************************************************
+* Functin: zDrvDpram_SendData
+* Description: This function is used to send data.
+* Parameters:
+* (IN)
+* uiDataId: T_ZDrvDpram_DataId.
+* ppBlockAddr: base address of databuf in block.
+* uiDataLen: data length. uint: byte
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* DPRAM_RET_ERR_NO_MEMORY: no enough space to send this data.
+* Others:
+* None.
+**************************************************************************/
+UINT32 zDrvDpram_SendData( UINT8 uiDataId, VOID *ppBlockAddr, UINT16 uiDataLen );
+
+
+/**************************************************************************
+* Functin: zDrvDpram_DataExist
+* Description: This function is used to check if there is data.
+* Parameters:
+* (IN)
+* uiDataId: T_ZDrvDpram_DataId.
+* (OUT)
+* None.
+* Returns:
+* TRUE: have data; FALSE: no data.
+* Others:
+* None.
+**************************************************************************/
+#if 0
+#ifdef _USE_EVB2963
+BOOL zDrvDpram_DataExist( UINT8 uiDataId );
+#else
+BOOL zDrvDpram_DataExist( VOID );
+#endif
+#endif
+
+
+BOOL zDrvDpram_DataExist( UINT8 uiDataId ); /*zyj,20110330*/
+
+/**************************************************************************
+* Functin: zDrvDpram_GetData
+* Description: This function is used to get data.
+* Parameters:
+* (IN)
+* puiDataId: pointer to stord data id. T_ZDrvDpram_DataId.
+* (OUT)
+* ppBlockAddr: pointer to store address of databuf in block.
+* puiRealLen: pointer to store data length. uint: byte
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* DPRAM_RET_ERR_NO_DATA: no data.
+* Others:
+* None.
+**************************************************************************/
+#if (((defined ( _CHIP_ZX297502)||defined ( _CHIP_ZX2975)||defined ( _CHIP_ZX2960_02B)) && defined (_USE_DPRAM_ADDR_NEWSW))||defined ( _CHIP_ZX2804))
+UINT32 zDrvDpram_GetData( UINT8 uiDataId, VOID **ppBlockAddr, UINT16 *puiRealLen );
+#else
+UINT32 zDrvDpram_GetData( UINT8 *puiDataId, VOID **ppBlockAddr, UINT16 *puiRealLen );
+#endif
+
+/**************************************************************************
+* Functin: zDrvDpram_FreeData
+* Description: This function is used to free the data block.
+* Parameters:
+* (IN)
+* uiDataId: T_ZDrvDpram_DataId.
+* pBlockAddr: base address of databuf in block.
+* (OUT)
+* None.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+UINT32 zDrvDpram_FreeData( UINT8 uiDataId, VOID *pBlockAddr );
+
+
+/**************************************************************************
+* Functin: zDrvTDpram_GetInfo
+* Description: This function is used to get the dpram information, such as base address.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* ptInfo: information pointer.
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+UINT32 zDrvTDpram_GetInfo( T_ZDrvDpram_Info *ptInfo );
+
+
+
+#if ((defined ( _CHIP_ZX297502)||defined ( _CHIP_ZX2975)||defined ( _CHIP_ZX2960_02B)||defined ( _CHIP_ZX2804)) && defined (_USE_DPRAM_ADDR_NEWSW))
+/**************************************************************************
+* Functin: zDrvTDpram_GetUPHValue
+* Description: This function is used to get the UPH value in Dpram.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* None.
+* Returns:
+* UINT16: 2 bytes UPH Value.
+* Others:
+* None.
+**************************************************************************/
+UINT16 zDrvTDpram_GetUPHValue( VOID );
+
+
+/**************************************************************************
+* Functin: zDrvTDpram_GetSNPLValue
+* Description: This function is used to get the SNPL value in Dpram.
+* Parameters:
+* (IN)
+* None.
+* (OUT)
+* None.
+* Returns:
+* UINT16: 2 bytes SNPL Value.
+* Others:
+* None.
+**************************************************************************/
+UINT16 zDrvTDpram_GetSNPLValue( VOID );
+#endif
+/**************************************************************************
+* Functin: zDrvDpram_IntGen
+* Description: This function is used to send mailbox int to zsp
+* Parameters:
+* (IN)
+* inttype
+* (OUT)
+* no
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+SINT32 zDrvDpram_IntGen(T_ZDrvIcp_IntType inttype);
+
+#ifdef _USE_PSM
+/**************************************************************************
+* Functin: zDrvDpram_GetDRXFlag
+* Description: This function is used to get drx flag
+* Parameters:
+* (IN)
+* pFlag :
+* (OUT)
+* no
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+
+SINT32 zDrvDpram_GetDRXFlag (UINT16 *pFlag);
+/**************************************************************************
+* Functin: zDrvDpram_ClearDRXFlag
+* Description: This function is used to clear drx flag
+* Parameters:
+* (IN)
+* no
+* (OUT)
+* no
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+
+SINT32 zDrvDpram_ClearDRXFlag (VOID );
+
+
+/**************************************************************************
+* Functin: zDrvDpram_WakeUpUphy
+* Description: This function is used to wakeup phy for ps
+* Parameters:
+* (IN)
+* no
+* (OUT)
+* no
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+extern VOID zDrvDpram_WakeUpUphy(VOID);//ps»½ÐÑphy
+
+#endif
+
+
+/**************************************************************************
+* Functin: zDrvDpram_L1tqueueFlag
+* Description: ÅжÏzspÊÇ·ñΪ¿ÕÏУ¬Èç¹û¿ÕÏз¢maiblox»½ÐÑzsp£¬²¢ÇÒÖ±dpramΪ0xa
+* Parameters:
+* (IN)
+* no
+* (OUT)
+* no
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+
+
+VOID zDrvDpram_L1tqueueFlag(VOID); /*ÅжÏ2963 l1t·ÅÏûÏ¢¶ÓÁÐÖÐÊÇ·ñÓÐÏûÏ¢*/
+/**************************************************************************
+* Functin: zDrvDpram_ClerrL1tqueueFlag
+* Description: This function is used to clear drx flag
+* Parameters:
+* (IN)
+* no
+* (OUT)
+* no
+* Returns:
+* DPRAM_RET_SUCCESS: successed.
+* DPRAM_RET_ERR_INVALID_PARAM: the input parameters are invalid
+* Others:
+* None.
+**************************************************************************/
+
+
+VOID zDrvDpram_ClearL1tqueueFlag(VOID); /*Çå³ýl1tÏûÏ¢¶ÓÁÐÊÇ·ñÓбê־λ*/
+
+#endif
+
+#endif /* _DRVSDPRAM_H */
+
diff --git a/cp/ps/driver/inc/misc/drvs_dsp.h b/cp/ps/driver/inc/misc/drvs_dsp.h
new file mode 100644
index 0000000..a3f95a4
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_dsp.h
@@ -0,0 +1,83 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: hal_dsp.h
+* File Mark:
+* Description: tu hal interface declaration.
+* Others:
+* Version: v1.0
+* Author: wangxia
+* Date: 2008-08-28
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+
+* History 2:
+**********************************************************************/
+
+#ifndef HAL_DSP_H
+#define HAL_DSP_H
+
+
+/*************************************************************************
+ * Include files *
+ *************************************************************************/
+
+
+/*************************************************************************
+ * Macro *
+ *************************************************************************/
+
+
+/**************************************************************************
+ * Types *
+ **************************************************************************/
+typedef enum
+{
+ GSM_DSP_INT0 ,/*90*/
+ GSM_DSP_INT1,/*91*/
+ GSM_DSP_INT2,/*92*/
+ GSM_DSP_INT3,/*93*/
+ GSM_DSP_INT4,/*94*/
+ GSM_DSP_INT5,/*95*/
+ GSM_DSP_INT6,/*96*/
+ GSM_DSP_INT7,/*97*/
+
+ MAX_DSP_INT
+} T_ZDrvDsp_IntId;
+
+/**************************************************************************
+ * Global Variable *
+ **************************************************************************/
+
+
+/**************************************************************************
+ * Function Prototypes *
+ **************************************************************************/
+/**************************************************************************
+* Functin: zDrvDsp_IntRegister
+* Description: This function is used to regist isr callback for l1g.
+* Parameters:
+* (IN)
+* intNumber: T_ZDrvDsp_IntId.
+* cb: isr callback.
+* intPrio:prio of interrupt
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERR_NOT_SUPPORTED: this device don't support ioctrl operation.
+* DRV_ERR_INVALID_PARAM: the input parameters are invalid
+* DRV_ERROR: error
+* others: others programmer defined error code. for detailed information, please contact with the programmer
+* Others:
+* others error code should be a negative number, and not equal to the value that already be defined in T_ZDrv_ErrCode in drv_pub.h.
+**************************************************************************/
+SINT32 zDrvDsp_IntRegister(T_ZDrvDsp_IntId intNumber,VOID (*cb)(VOID),UINT32 intPrio);
+
+
+#endif /* HAL_DSP_H */
+
diff --git a/cp/ps/driver/inc/misc/drvs_edcp.h b/cp/ps/driver/inc/misc/drvs_edcp.h
new file mode 100644
index 0000000..9058dbb
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_edcp.h
@@ -0,0 +1,693 @@
+/*******************************************************************************
+* Copyright (C) 2007, ZTE Corporation.
+*
+* File Name: drvs_edcp.h
+* File Mark:
+* Description:
+* Others:
+* Version: 0.5
+* Author: yangjupei
+* Date: 2013-8-25
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+* History 2:
+********************************************************************************/
+#ifndef _DRVS_EDCP_H
+#define _DRVS_EDCP_H
+
+/*************************************************************************
+* Include files *
+*************************************************************************/
+#include "drvs_general.h"
+
+/*************************************************************************
+* Macro *
+*************************************************************************/
+
+#define Z_W_MAX_UL_EDCP_PDU_NUM (WORD)2
+#define Z_W_MAX_UL_EDCP_CFG_NUM (WORD)256 /*EDCP1ÖÐÿ¸öPDU¶ÔÓ¦¶¯Ì¬ÅäÖÃÊý×éµÄ¸öÊý*/
+#define Z_W_MAX_DL_EDCP_CFG_NUM (WORD)512 /*EDCP2ÖжÔÓ¦¶¯Ì¬ÅäÖÃÊý×éµÄ¸öÊý*/
+#define Z_W_MAX_PDCP_EDCP_CFG_NUM (WORD)512 /*EDCP3ÖжÔÓ¦¶¯Ì¬ÅäÖÃÊý×éµÄ¸öÊý*/
+#define Z_W_MAX_EDCP_CK_NUM (WORD)16
+#define Z_EDCP_CK_LEN (WORD)16
+
+/*EDCP INT type*/
+#define EDCP_INT_UL_ASYN (UINT32)0x1
+#define EDCP_INT_EMAC (UINT32)0x2
+#define EDCP_INT_DL (UINT32)0x4
+
+/*¼ÓÃÜ·½Ê½ºÍÍê±£Ëã·¨*/
+#define EDCP_NOCIPHER (WORD)0 /*²»¼ÓÃÜ*/
+#define EDCP_SNOW3G (WORD)1 /*SNOW3G*/
+#define EDCP_AES (WORD)2 /*AES*/
+#define EDCP_ZUC (WORD)3 /*ZUC*/
+#define EDCP_KASUMI (WORD)4 /*KSAUMI*/
+
+/**************************************************************************
+* Types *
+**************************************************************************/
+
+typedef struct T_ZDrvEdcp_StaticConfigInfo
+{
+ UINT8 CtrlPaneCk[16]; /*EDPCP_CK_I¼Ä´æÆ÷4*4bytes*/
+ UINT8 UserPaneCk[16]; /*EDPCP_CK_C¼Ä´æÆ÷4*4bytes*/
+ UINT8 Ik[16]; /*EDPCP_IK_I¼Ä´æÆ÷4*4bytes*/
+ UINT8 Direct; /*ÉÏÐÐ0£¬ÏÂÐÐ1*/
+ UINT8 CipherType; /*¼ÓÃÜָʾ: 0²»¼ÓÃÜ£¬1 snow3g£¬ 2 aes£¬ 3 zuc*/
+ UINT8 IntegType; /*ÍêÕûÐÔָʾ: 0ÎÞÍê±££¬1 snow3g£¬ 2 aes£¬ 3 zuc*/
+} T_ZDrvEdcp_StaticConfigInfo;
+
+
+typedef struct T_ZDrvEdcp_ULDynamicCtrlInfo
+{
+ UINT8 CPInd; /*¼ÓÃÜָʾ: 0 ²»¼ÓÃÜ£¬1 ¼ÓÃÜ*/
+ UINT8 IPInd; /*ÍêÕûÐÔָʾ: 0 ÎÞÍê±££¬1 Íê±£*/
+ UINT8 DataSourceType; /*Êý¾ÝÔ´ÀàÐÍ 0 Óû§Ã棬1 ¿ØÖÆÃæ*/
+ UINT8 BearerId; /*¼ÓÃܲÎÊý*/
+ UINT8 *pDataSrc; /*Êý¾ÝÔ´µØÖ·*/
+ UINT16 DateLen; /*Êý¾ÝÔ´³¤¶È*/
+ UINT16 CompHeaderLen; /*ѹËõÍ·³¤¶È*/
+ UINT8 *pDataCompHeaderSrc; /*ѹËõÍ·µØÖ·*/
+ UINT8 *pDataDest; /*Ä¿±êµØÖ·*/
+ UINT32 Count; /*¼ÓÃܲÎÊý*/
+} T_ZDrvEdcp_ULDynamicCtrlInfo;
+
+
+/*EMAC ͬ²½´¦ÀíË÷ÒýRAM*/
+typedef struct T_ZDrvEdcp_BusCopyCtrlInfo
+{
+ UINT8 *pDataSrc;
+ UINT16 DataLen;
+ UINT8 *pDataDest;
+} T_ZDrvEdcp_BusCopyCtrlInfo;
+
+/*ÏÂÐд¦Àí¿ØÖÆË÷ÒýRAM*/
+typedef struct T_ZDrvEdcp_DLDynamicCtrlInfo
+{
+ UINT8 CPInd; /*¼ÓÃÜָʾ: 0 ²»¼ÓÃÜ£¬1 ¼ÓÃÜ*/
+ UINT8 IPInd; /*ÍêÕûÐÔָʾ: 0 ÎÞÍê±££¬1 ÓÐÍê±£*/
+ UINT8 DataSourceType; /*Êý¾ÝÔ´ÀàÐÍ 0 Óû§Ã棬1 ¿ØÖÆÃæ*/
+ UINT8 *pDataSrc; /*Êý¾ÝÔ´µØÖ·*/
+ UINT16 DateLen; /*Êý¾ÝÔ´³¤¶È*/
+ UINT8 *pDataDest; /*Ä¿±êµØÖ·*/
+ UINT8 BearerId; /*¼ÓÃܲÎÊý*/
+ UINT32 Count; /*¼ÓÃܲÎÊý*/
+ UINT16 DecipherLen; /*¼ÓÃܳ¤¶È²ÎÊý*/
+ UINT8 SegmentNum; /*·Ö¶Î×ÜÊý*/
+} T_ZDrvEdcp_DLDynamicCtrlInfo;
+
+/*UMTSÉÏÐÐ Òì²½´¦Àí¿ØÖÆË÷ÒýRAM*/
+typedef struct T_ZDrvEdcp_ULDynamicCtrlInfo_umts
+{
+ UINT8 bUea;//CPInd; /*ÊÇ·ñ¼ÓÃÜ bit0*/
+ UINT8 *pDataSrc; /*Êý¾ÝÔ´µØÖ·*/
+ UINT16 wDataLen; /*Êý¾ÝÔ´³¤¶È bitµ¥Î» bit15-0*/
+ UINT8 bSegNum; /*·Ö¶Î¸öÊý bit15-8*/
+ UINT8 BearerId; /*¼ÓÃܲÎÊý bit20-16*/
+ UINT8 CkIndex; /*Ñ¡ÔñÄÇ×éÃÜÔ¿ bit7-4*/
+ UINT32 Count; /*¼ÓÃܲÎÊý*/
+} T_ZDrvEdcp_ULDynamicCtrlInfo_umts;
+
+
+/*UMTSÏÂÐÐ Òì²½´¦Àí¿ØÖÆË÷ÒýRAM*/
+typedef struct T_ZDrvEdcp_DLDynamicCtrlInfo_umts
+{
+ UINT8 bUea;//CPInd; /*ÊÇ·ñ½âÃÜ bit0*/
+ UINT8 *pDataSrc; /*Êý¾ÝÔ´µØÖ·*/
+ UINT16 wDataLen; /*Êý¾ÝÔ´³¤¶È bitµ¥Î» bit15-0*/
+ UINT8 bDataOffset; /*Ñ¡ÔñÄÇ×éÃÜÔ¿ bit10-8*/
+ UINT8 *pDataDes; /*Ä¿±êµØÖ·*/
+ UINT8 BearerId; /*¼ÓÃܲÎÊý bit20-16*/
+ UINT8 CkIndex; /*Ñ¡ÔñÄÇ×éÃÜÔ¿ bit7-4*/
+ UINT32 Count; /*¼ÓÃܲÎÊý*/
+} T_ZDrvEdcp_DLDynamicCtrlInfo_umts;
+
+/*UMTS ÃÜÔ¿Ë÷ÒýRAM*/
+typedef struct T_ZDrvEdcp_KeyIndexInfo_umts
+{
+ UINT32 CK0; /*¼ÓÃÜÃÜÔ¿*/
+ UINT32 CK1;
+ UINT32 CK2;
+ UINT32 CK3;
+} T_ZDrvEdcp_KeyIndexInfo_umts;
+
+
+typedef VOID (*ZDRV_EDCP_CMD_RECVFUNC)(UINT32 intType);
+
+typedef struct
+{
+ ZDRV_EDCP_CMD_RECVFUNC fCmdRecv;
+} T_ZDrvEdcp_CallbackFuncs;
+
+typedef VOID (*ZDRV_PDCP_EDCP_ISR_CALLBACK)( VOID );
+
+typedef struct
+{
+ ZDRV_PDCP_EDCP_ISR_CALLBACK fCmdRecv;
+} T_ZDrvEdcp_CallbackFuncs_ForW;
+
+typedef struct
+{
+UINT32 DataSourceType:
+ 1; //Êý¾Ý¿éÀàÐÍ
+UINT32 IPInd:
+ 1; //ÍêÕûÐÔ±£»¤
+UINT32 CPInd:
+ 1; //ÊÇ·ñ¼ÓÃÜ
+UINT32 Reserve0:
+ 1;
+UINT32 MultiSegFlag:
+ 1;
+UINT32 Reserve1:
+ 11;
+UINT32 Total_DateLen:
+ 14;
+UINT32 Reserve2:
+ 2;
+}
+Edcp_Conf;//lte
+
+//define Uplink/ downlink lte control structure
+typedef struct
+{
+UINT32 DataLen:
+ 14;
+UINT32 Reserve0:
+ 2;
+UINT32 Bearer:
+ 5;
+UINT32 Reserve1:
+ 11;
+}
+Edcp_Length_Bearer;//lte
+
+//define Uplink/ downlink control structure
+typedef struct
+{
+ Edcp_Conf conf;
+ UINT32 datain_addr;
+ Edcp_Length_Bearer length_bearer;
+ UINT32 dataout_addr;
+ UINT32 count;
+}
+T_ZDrvEdcp_Ctrl_Index;
+
+
+/*==============================================================================
+ÔÓT_zDrvEdcp_UlCfg
+˵Ã÷: EDCP ULÅäÖòÎÊý
+==============================================================================*/
+typedef struct {
+ UINT8 bUea;//CPInd;
+ UINT8 *pDataSrc;
+ UINT16 wDataLen;
+ UINT8 bSegNum;
+ UINT8 BearerId;
+ UINT8 CkIndex;
+ UINT32 Count;
+}T_zDrvEdcp_UlDynamicCtrlInfo;
+
+
+typedef struct {
+ UINT16 wCfgNum;
+ UINT16 wTotalLen;
+ UINT8 *pDataDes;
+ UINT16 wTruncatedDataLen;
+ UINT8 *pTruncatedDataSrc;
+ UINT8 *pTruncatedDataDes;
+ T_zDrvEdcp_UlDynamicCtrlInfo tUlDynamicCtrlInfo[Z_W_MAX_UL_EDCP_CFG_NUM];
+}T_zDrvEdcp_PduCfg;
+
+
+typedef struct {
+ T_zDrvEdcp_PduCfg tPduCfg[Z_W_MAX_UL_EDCP_PDU_NUM];
+}T_zDrvEdcp_UlCfg;
+
+
+/*==============================================================================
+ÔÓT_zDrvEdcp_DlCfg
+˵Ã÷: EDCP DLÅäÖòÎÊý
+==============================================================================*/
+typedef struct {
+ UINT8 bUea; //CPInd;//7510 UMTS½öÖ§³ÖUEA1Ò»ÖÖ¼ÓÃÜ·½Ê½£¬CPIndΪ1ʱĬÈÏΪUEA1¼ÓÃÜ¡£
+ UINT8 *pDataSrc;
+ UINT16 wDataLen;
+ UINT8 bDataOffset;
+ UINT8 *pDataDes;
+ UINT8 BearerId;
+ UINT8 CkIndex;
+ UINT32 Count;
+}T_zDrvEdcp_DlDynamicCtrlInfo;
+
+
+typedef struct {
+ UINT16 wCfgNum;
+ T_zDrvEdcp_DlDynamicCtrlInfo tDlDynamicCtrlInfo[Z_W_MAX_DL_EDCP_CFG_NUM];
+}T_zDrvEdcp_DlCfg;
+
+/*==============================================================================
+T_zDrvEdcp_PdcpCfg
+˵Ã÷: PDCP EDCPÅäÖòÎÊý
+==============================================================================*/
+typedef struct{
+ UINT8 *pDataSrc;
+ UINT8 *pDataDes;
+ UINT16 wDataLen;
+}T_zDrvEdcp_PdcpDynamicCtrlInfo;
+
+typedef struct{
+ UINT16 wCfgNum;
+ T_zDrvEdcp_PdcpDynamicCtrlInfo tPdcpDynamicCtrlInfo[Z_W_MAX_PDCP_EDCP_CFG_NUM];
+}T_zDrvEdcp_PdcpCfg;
+
+/*==============================================================================
+ÔÓT_zDrvEdcp_StaticCfgInfo
+˵Ã÷: static EDCPÅäÖòÎÊý
+==============================================================================*/
+typedef struct{
+// UINT8 Uea;
+ UINT8 CK[Z_W_MAX_EDCP_CK_NUM][Z_EDCP_CK_LEN];
+}T_zDrvEdcp_StaticCfgInfo;
+
+/* error code define */
+typedef enum
+{
+ EDCP_RET_SUCCESS = 0, /* successed */
+ EDCP_RET_BUSY = 1, /* busy */
+ EDCP_RET_ERR_INVALID_PARAM = 2, /* the input parameter is invalid */
+
+ MAX_EDCP_ERR_CODE
+} T_ZDrvEdcp_RetCode;
+
+typedef enum
+{
+ EDCP_UL_MODULE,
+ EDCP_DL_MODULE,
+ EDCP_EMAC_MODULE
+}T_ZDrvEdcp_ModuleSel;
+
+//define Uplink syn ctrl index structure
+typedef struct
+{
+ UINT32 datain_addr;
+ UINT32 length_valid;
+ UINT32 dataout_addr;
+}
+T_ZDrvEdcp_Emac_Index;
+
+/**************************************************************************
+* Function Prototypes *
+**************************************************************************/
+/*******************************************************************************
+* Function: zDrvEDCP_Initiate
+* Description: initialize edcp module and globle Variables
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEDCP_Initiate(VOID);
+
+/*******************************************************************************
+* Function: zDrvEdcp_StartHWOp
+* Description: start lte EDCP hardware
+* Parameters:
+* Input:
+* HWSource 0: UL_ASYN
+* 1: DL
+* 2: UL_SYN
+* EnableInt 1:enable interrupt
+* 0:disable interrupt
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEdcp_StartHWOp(UINT8 HWSource, UINT8 EnableInt);
+
+/*******************************************************************************
+* Function: zDrvEdcp_InitULStaticPara
+* Description: configure static parameters for up link
+* Parameters:
+* Input:
+* StaticConfigInfo :CK_I,CK_C,IK,direct
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+VOID zDrvEdcp_InitULStaticPara(T_ZDrvEdcp_StaticConfigInfo StaticConfigInfo);
+
+/*******************************************************************************
+* Function: zDrvEdcp_WriteULIndexRam
+* Description: configure index for up link
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEdcp_WriteULIndexRam(T_ZDrvEdcp_ULDynamicCtrlInfo ULDynamicCtrlInfo);
+
+
+/*******************************************************************************
+* Function: zDrvEdcp_WriteEmacIndexRam
+* Description: configure EMAC index for EMAC channel
+* Parameters:
+* Input:
+* BusCopyCtrlInfo:data source's address,data length,data des'address
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEdcp_WriteEmacIndexRam(T_ZDrvEdcp_Emac_Index *BusCopyCtrlInfo, WORD dwNum);
+
+/*******************************************************************************
+* Function: zDrvEdcp_InitDLStaticPara
+* Description: configure static parameters for down link
+* Parameters:
+* Input: StaticConfigInfo :CK_I,CK_C,IK,direct
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+VOID zDrvEdcp_InitDLStaticPara(T_ZDrvEdcp_StaticConfigInfo StaticConfigInfo);
+
+/*******************************************************************************
+* Function: zDrvEdcp_WriteDLIndexRam
+* Description: configure index for down link
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEdcp_WriteDLIndexRam(T_ZDrvEdcp_Ctrl_Index *DLDynamicCtrlInfo, DWORD dwNum);
+
+/*******************************************************************************
+* Function: zDrvEdcp_RegCallback
+* Description: enable EDCP interrupt,register EDCP ISR callback function
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEdcp_RegCallback( T_ZDrvEdcp_CallbackFuncs *ptCallbackStruct );
+
+/*******************************************************************************
+* Function: zDrvEdcp_UnRegCallback
+* Description: disable EDCP interrupt,release callback thread's source
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+VOID zDrvEdcp_UnRegCallback(VOID);
+
+/*******************************************************************************
+* Function: zDrvEdcp_GetFreeDlIndexRamNum
+* Description: Get Free Dl Index Ram Num
+* Parameters:
+* Input:
+*
+* Output: the remain Num
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEdcp_GetFreeDlIndexRamNum(VOID);
+
+/*******************************************************************************
+* Function: zDrvEdcp_IsBusy
+* Description: judge edcp hardware busy or idle
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+UINT8 zDrvEdcp_IsBusy(T_ZDrvEdcp_ModuleSel EdcpNum);
+
+/*******************************************************************************
+* Function: zDrvEdcp_Reset
+* Description: Reset Edcp
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEdcp_Reset( VOID);
+
+/*******************************************************************************
+* Function: zDrvEdcp_CleanEmacIndexCount
+* Description:
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEdcp_ClrUlSynEmacIndexCnt(VOID);
+
+/*******************************************************************************
+* Function: zDrvEdcp_UpDateEmacIndex
+* Description:
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEdcp_UpDateEmacIndexRam(UINT8 IndexNo,T_ZDrvEdcp_BusCopyCtrlInfo BusCopyCtrlInfo);
+
+/*******************************************************************************
+* Function: zDrvEdcp_EmacTotalIndex
+* Description:
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+UINT8 zDrvEdcp_EmacTotalIndex(VOID);
+
+/*******************************************************************************
+*For Wcdma
+*
+********************************************************************************/
+/*******************************************************************************
+* Function: zDrvEdcp_CKCfgForW
+* Description: EDCP½âÃÜÃÜÔ¿ÅäÖÃ
+* Parameters:
+* Input:T_zDrvEdcp_StaticCfgInfo
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+UINT32 zDrvEdcp_CKCfgForW(T_zDrvEdcp_StaticCfgInfo *ptCK,T_ZDrvEdcp_ModuleSel EdcpNum);
+
+/*******************************************************************************
+* Function: zDrvEdcp_IsBusyForW
+* Description:
+* Parameters:
+* Input:EdcpNum
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+UINT8 zDrvEdcp_IsBusyForW(UINT8 EdcpNum);
+
+/*******************************************************************************
+* Function: zDrvEdcp_ResetForW
+* Description: Reset Edcp for W
+* Parameters:
+* Input:EdcpNum
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+VOID zDrvEdcp_ResetForW(T_ZDrvEdcp_ModuleSel EdcpNum);
+
+/*******************************************************************************
+* Function: zDrvEdcp_UlCfgForW
+* Description: ÉÏÐÐÄ£¿éÅäÖò¢Æô¶¯
+* Parameters:
+* Input:T_zDrvEdcp_UlCfg
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+UINT32 zDrvEdcp_UlCfgForW(T_zDrvEdcp_UlCfg *ptUlCfg);
+
+/*******************************************************************************
+* Function: zDrvEdcp_DlCfgForW
+* Description: ÏÂÐÐÄ£¿éÅäÖò¢Æô¶¯
+* Parameters:
+* Input:T_zDrvEdcp_DlCfg
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+UINT32 zDrvEdcp_DlCfgForW(T_zDrvEdcp_DlCfg *ptDlCfg);
+
+/*******************************************************************************
+* Function: zDrvEdcp_PdcpCfgForW
+* Description: edcpÏÂÐÐpdcp sdu°áÔËÄ£¿éÅäÖò¢Æô¶¯
+* Parameters:
+* Input:T_zDrvEdcp_PdcpCfg
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+UINT32 zDrvEdcp_PdcpCfgForW(T_zDrvEdcp_PdcpCfg *ptPdcpCfg);
+
+/*******************************************************************************
+* Function: zDrvEdcp_RegCallback_ForW
+* Description: register edcp isr callback function for wcdma
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+UINT32 zDrvEdcp_RegCallback_ForW(T_ZDrvEdcp_CallbackFuncs_ForW *ptCallbackStruct);
+
+/*******************************************************************************
+* Function: zDrvEdcp_UlCfgNormForW
+* Description: Normal UL data
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+UINT32 zDrvEdcp_UlCfgNormForW(T_zDrvEdcp_UlCfg *ptUlCfg);
+
+#ifdef _USE_PSM
+/*******************************************************************************
+* Function: zDrvEdcp_SaveConfiguration
+* Description: Ê¡µçÄ£¿é¶ÏµçÇ°±£´æÏÖ³¡
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEdcp_SaveConfiguration(VOID);
+
+/*******************************************************************************
+* Function: zDrvEdcp_RestoreConfiguration
+* Description: Ê¡µçÄ£¿é»Ö¸´¹©µçʱ»Ö¸´ÏÖ³¡
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvEdcp_RestoreConfiguration(VOID);
+#endif
+
+#endif/*_DRVS_EDCP_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_efuse.h b/cp/ps/driver/inc/misc/drvs_efuse.h
new file mode 100644
index 0000000..2cca866
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_efuse.h
@@ -0,0 +1,110 @@
+/*******************************************************************************
+ * Copyright (C) 2014, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: 1.0
+ * Author:
+ * Date:
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_EFUSE_H
+#define _DRVS_EFUSE_H
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#ifndef _OS_LINUX
+#include "oss_api.h"
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+
+/****************************************************************************
+* Types
+****************************************************************************/
+typedef struct
+{
+ UINT32 pubKeyRsaE[32];
+ UINT32 pubKeyRsaN[32];
+ UINT32 secureFlag;
+ UINT32 pubKeyHash[4];
+ UINT32 secureDevId[3];
+}T_ZDrvEfuse_Secure;
+
+typedef enum
+{
+ SECURE_EN,
+ PUB_KEY_HASH,
+ DEVICE_ID,
+ MAX_ENUM
+}E_ZDrvEfuse_SecureMsg;
+#endif
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+
+/*******************************************************************************
+* Function: zDrvEfuse_IsSpe
+* Description:
+* Parameters:
+* Input:
+* None
+* Output:
+* None
+* Returns:
+* Others:
+*******************************************************************************/
+UINT32 zDrvEfuse_IsSpe(VOID);
+
+#ifndef _OS_LINUX
+
+/*******************************************************************************
+ * Function: zDrvEfuse_GetSecureMsg
+ * Description:¸Ãº¯ÊýÓÃÓÚ»ñÈ¡¹«Ô¿¶Ô¡¢°²È«¿ªÆô±ê¼Ç¡¢¹«Ô¿hashÖµ¡¢É豸ID¡£
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ * Others:
+ ********************************************************************************/
+VOID zDrvEfuse_GetSecureMsg(T_ZDrvEfuse_Secure *secure);
+
+/*******************************************************************************
+* Function: zDrvEfuse_SetSecureMsg
+* Description:¸Ãº¯ÊýÓÃÓÚÉèÖð²È«¿ªÆô±ê¼Ç¡¢¹«Ô¿hashÖµ¡¢É豸ID¡£
+* Parameters:
+* Input:
+* None
+* Output:
+* None
+* Returns:
+* None
+* Others:
+*******************************************************************************/
+SINT32 zDrvEfuse_SetSecureMsg(E_ZDrvEfuse_SecureMsg secure_msg, UINT32 *secure_buf);
+#endif
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_gpio.h b/cp/ps/driver/inc/misc/drvs_gpio.h
new file mode 100644
index 0000000..96ebc53
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_gpio.h
@@ -0,0 +1,1137 @@
+/**
+* @file drvs_gpio.h
+* @brief Public APIs of gpio drivers
+*
+* Copyright (C) 2017 Sanechips Technology Co., Ltd.
+* @author Dongdong Zhang <Zhang.Dongdong@sanechips.com.cn>
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+*/
+#ifndef _DRVS_GPIO_H
+#define _DRVS_GPIO_H
+
+#ifdef _OS_LINUX
+#include <linux/gpio.h>
+#else
+/*******************************************************************************
+* Include header files *
+******************************************************************************/
+
+/*******************************************************************************
+* Macro definitions *
+******************************************************************************/
+#define GPIO0 0
+#define GPIO1 1
+#define GPIO2 2
+#define GPIO3 3
+#define GPIO4 4
+#define GPIO5 5
+#define GPIO6 6
+#define GPIO7 7
+#define GPIO8 8
+#define GPIO9 9
+#define GPIO10 10
+#define GPIO11 11
+#define GPIO12 12
+#define GPIO13 13
+#define GPIO14 14
+#define GPIO15 15
+#define GPIO16 16
+#define GPIO17 17
+#define GPIO18 18
+#define GPIO19 19
+#define GPIO20 20
+#define GPIO21 21
+#define GPIO22 22
+#define GPIO23 23
+#define GPIO24 24
+#define GPIO25 25
+#define GPIO26 26
+#define GPIO27 27
+#define GPIO28 28
+#define GPIO29 29
+#define GPIO30 30
+#define GPIO31 31
+#define GPIO32 32
+#define GPIO33 33
+#define GPIO34 34
+#define GPIO35 35
+#define GPIO36 36
+#define GPIO37 37
+#define GPIO38 38
+#define GPIO39 39
+#define GPIO40 40
+#define GPIO41 41
+#define GPIO42 42
+#define GPIO43 43
+#define GPIO44 44
+#define GPIO45 45
+#define GPIO46 46
+#define GPIO47 47
+#define GPIO48 48
+#define GPIO49 49
+#define GPIO50 50
+#define GPIO51 51
+#define GPIO52 52
+#define GPIO53 53
+#define GPIO54 54
+#define GPIO55 55
+#define GPIO56 56
+#define GPIO57 57
+#define GPIO58 58
+#define GPIO59 59
+#define GPIO60 60
+#define GPIO61 61
+#define GPIO62 62
+#define GPIO63 63
+#define GPIO64 64
+#define GPIO65 65
+#define GPIO66 66
+#define GPIO67 67
+#define GPIO68 68
+#define GPIO69 69
+#define GPIO70 70
+#define GPIO71 71
+#define GPIO72 72
+#define GPIO73 73
+#define GPIO74 74
+#define GPIO75 75
+#define GPIO76 76
+#define GPIO77 77
+#define GPIO78 78
+#define GPIO79 79
+#define GPIO80 80
+#define GPIO81 81
+#define GPIO82 82
+#define GPIO83 83
+#define GPIO84 84
+#define GPIO85 85
+#define GPIO86 86
+#define GPIO87 87
+#define GPIO88 88
+#define GPIO89 89
+#define GPIO90 90
+#define GPIO91 91
+#define GPIO92 92
+#define GPIO93 93
+#define GPIO94 94
+#define GPIO95 95
+#define GPIO96 96
+#define GPIO97 97
+#define GPIO98 98
+#define GPIO99 99
+#define GPIO100 100
+#define GPIO101 101
+#define GPIO102 102
+#define GPIO103 103
+#define GPIO104 104
+#define GPIO105 105
+#define GPIO106 106
+#define GPIO107 107
+#define GPIO108 108
+#define GPIO109 109
+#define GPIO110 110
+#define GPIO111 111
+#define GPIO112 112
+#define GPIO113 113
+#define GPIO114 114
+#define GPIO115 115
+#define GPIO116 116
+#define GPIO117 117
+#define GPIO118 118
+#define GPIO119 119
+#define GPIO120 120
+#define GPIO121 121
+#define GPIO122 122
+#define GPIO123 123
+#define GPIO124 124
+#define GPIO125 125
+#define GPIO126 126
+#define GPIO127 127
+#define GPIO128 128
+#define GPIO129 129
+#define GPIO130 130
+#define GPIO131 131
+#define GPIO132 132
+#define GPIO133 133
+#define GPIO134 134
+#define GPIO135 135
+#define GPIO136 136
+#define GPIO137 137
+#define GPIO138 138
+#define GPIO139 139
+#define GPIO140 140
+#define GPIO141 141
+#define GPIO142 142
+#define GPIO143 143
+#define GPIO144 144
+#define GPIO145 145
+#define GPIO146 146
+#define GPIO147 147
+#define GPIO148 148
+#define GPIO149 149
+#define GPIO150 150
+#define GPIO151 151
+#define GPIO152 152
+#define GPIO153 153
+#define GPIO154 154
+#define GPIO155 155
+
+#if defined (_CHIP_ZX297520V3)
+#define MAX_GPIO_NUM GPIO135
+#elif defined (_CHIP_ZX297520V2)
+#define MAX_GPIO_NUM GPIO155
+#endif
+
+#define INVLID_GPIO 0xffff
+
+/*******************************************************************************
+* Type definitions *
+******************************************************************************/
+typedef enum{
+ GPIO_IN = 101,
+ GPIO_OUT = 102,
+}T_ZDrvGpio_IoDirection;
+
+typedef enum{
+ GPIO_LOW = 201,
+ GPIO_HIGH = 202,
+}T_ZDrvGpio_IoVal;
+
+typedef enum{
+ GPIO_PULL_DOWN = 0x1,
+ GPIO_NO_ACTION = 0x2,
+ GPIO_PULL_UP = 0x3,
+}T_ZDrvGpio_PullUp;
+
+#if defined (_CHIP_ZX297520V3)
+typedef enum
+{
+ /*[31:24]:gpio_id [23:12]:level1_sel [11:0]:level2_sel*/
+ GPIO0_GPIO0 = 0x00000000,
+ GPIO0_NAND_WE = 0x00001000,
+ GPIO0_LCD_OE_N = 0x00001001,
+ GPIO1_GPIO1 = 0x01000000,
+ GPIO1_NAND_CS0 = 0x01001000,
+ GPIO1_LCD_CS_N = 0x01001001,
+ GPIO2_GPIO2 = 0x02000000,
+ GPIO2_NAND_READY = 0x02001000,
+ GPIO2_LCD_RS = 0x02001001,
+ GPIO3_GPIO3 = 0x03000000,
+ GPIO3_NAND_CLE = 0x03001000,
+ GPIO3_LCD_RESET_N = 0x03001001,
+ GPIO4_GPIO4 = 0x04000000,
+ GPIO4_NAND_ALE = 0x04001000,
+ GPIO4_LCD_WE_N = 0x04001001,
+ GPIO5_GPIO5 = 0x05000000,
+ GPIO5_NAND_RE = 0x05001000,
+ GPIO5_LCD_TE = 0x05001001,
+ GPIO6_GPIO6 = 0x06000000,
+ GPIO6_NAND_WRITE_PROTECT = 0x06001000,
+ GPIO6_LCD_D0 = 0x06001001,
+ GPIO7_GPIO7 = 0x07000000,
+ GPIO7_NAND_DATA0 = 0x07001000,
+ GPIO7_LCD_D1 = 0x07001001,
+ GPIO8_GPIO8 = 0x08000000,
+ GPIO8_NAND_DATA1 = 0x08001000,
+ GPIO8_LCD_D2 = 0x08001001,
+ GPIO9_GPIO9 = 0x09000000,
+ GPIO9_NAND_DATA2 = 0x09001000,
+ GPIO9_LCD_D3 = 0x09001001,
+ GPIO10_GPIO10 = 0x0A000000,
+ GPIO10_NAND_DATA3 = 0x0A001000,
+ GPIO10_LCD_D4 = 0x0A001001,
+ GPIO11_GPIO11 = 0x0B000000,
+ GPIO11_NAND_DATA4 = 0x0B001000,
+ GPIO11_LCD_D5 = 0x0B001001,
+ GPIO12_GPIO12 = 0x0C000000,
+ GPIO12_NAND_DATA5 = 0x0C001000,
+ GPIO12_LCD_D6 = 0x0C001001,
+ GPIO13_GPIO13 = 0x0D000000,
+ GPIO13_NAND_DATA6 = 0x0D001000,
+ GPIO13_LCD_D7 = 0x0D001001,
+ GPIO14_GPIO14 = 0x0E000000,
+ GPIO14_NAND_DATA7 = 0x0E001000,
+ GPIO14_LCD_D8 = 0x0E001001,
+ GPIO15_CLK_OUT0 = 0x0F000000,
+ GPIO15_GPIO15 = 0x0F000001,
+ GPIO16_GPIO16 = 0x10000000,
+ GPIO16_CLK_OUT1 = 0x10000001,
+ GPIO17_GPIO17 = 0x11000000,
+ GPIO17_CLK_OUT2 = 0x11000001,
+ GPIO17_TEST_CLK_OUT = 0x11000002,
+ GPIO17_TDM_MCLK_OUT = 0x11001000,
+ GPIO17_I2S0_MCLK_OUT = 0x11001001,
+ GPIO17_I2S1_MCLK_OUT = 0x11001002,
+ GPIO18_GPIO18 = 0x12000000,
+ GPIO18_CLK_32K_OUT = 0x12000001,
+ GPIO19_GPIO19 = 0x13000000,
+ GPIO19_RMII_CLK_I = 0x13001000,
+ GPIO20_GPIO20 = 0x14000000,
+ GPIO20_RMII_CLK_O = 0x14001000,
+ GPIO21_CLK_REQ0 = 0x15000000,
+ GPIO21_GPIO21 = 0x15000001,
+ GPIO22_CLK_REQ1 = 0x16000000,
+ GPIO22_GPIO22 = 0x16000001,
+ GPIO23_PWRCTRL = 0x17000000,
+ GPIO23_GPIO23 = 0x17000001,
+ GPIO24_GPIO24 = 0x18000000,
+ GPIO25_GPIO25 = 0x19000000,
+ GPIO25_SSP0_CS = 0x19001000,
+ GPIO26_GPIO26 = 0x1A000000,
+ GPIO26_SSP0_CLK = 0x1A001000,
+ GPIO27_GPIO27 = 0x1B000000,
+ GPIO27_SSP0_RXD = 0x1B001000,
+ GPIO28_GPIO28 = 0x1C000000,
+ GPIO28_SSP0_TXD = 0x1C001000,
+ GPIO29_UART0_RXD = 0x1D000000,
+ GPIO29_GPIO29 = 0x1D000001,
+ GPIO29_UART0_TXD = 0x1D000002,
+ GPIO29_FRAME_SYNC = 0x1D001000,
+ GPIO29_TEST_PIN10 = 0x1D001001,
+ GPIO30_UART0_TXD = 0x1E000000,
+ GPIO30_GPIO30 = 0x1E000001,
+ GPIO30_UART0_RXD = 0x1E000002,
+ GPIO30_LTE_PRE_TX = 0x1E001000,
+ GPIO30_TEST_PIN11 = 0x1E001001,
+ GPIO31_UART0_CTS = 0x1F000000,
+ GPIO31_GPIO31 = 0x1F000001,
+ GPIO31_LTE_TPU_OUT3 = 0x1F001000,
+ GPIO31_UART1_TXD = 0x1F001001,
+ GPIO31_TEST_PIN12 = 0x1F001002,
+ GPIO32_UART0_RTS = 0x20000000,
+ GPIO32_GPIO32 = 0x20000001,
+ GPIO32_LTE_TPU_OUT4 = 0x20001000,
+ GPIO32_UART1_RXD = 0x20001001,
+ GPIO33_GPIO33 = 0x21000000,
+ GPIO33_UART1_RXD = 0x21001000,
+ GPIO33_UART2_TXD = 0x21001001,
+ GPIO33_UART2_RXD = 0x21001002,
+ GPIO34_GPIO34 = 0x22000000,
+ GPIO34_UART1_TXD = 0x22001000,
+ GPIO34_UART2_RXD = 0x22001001,
+ GPIO34_UART2_TXD = 0x22001002,
+ GPIO35_GPIO35 = 0x23000000,
+ GPIO35_I2S0_WS = 0x23001000,
+ GPIO35_TEST_PIN0 = 0x23001001,
+ GPIO35_TDM_FS = 0x23001002,
+ GPIO36_GPIO36 = 0x24000000,
+ GPIO36_I2S0_CLK = 0x24001000,
+ GPIO36_TEST_PIN1 = 0x24001001,
+ GPIO36_TDM_CLK = 0x24001002,
+ GPIO37_GPIO37 = 0x25000000,
+ GPIO37_I2S0_DIN = 0x25001000,
+ GPIO37_TEST_PIN2 = 0x25001001,
+ GPIO37_TDM_DATA_IN = 0x25001002,
+ GPIO38_GPIO38 = 0x26000000,
+ GPIO38_I2S0_DOUT = 0x26001000,
+ GPIO38_TEST_PIN3 = 0x26001001,
+ GPIO38_TDM_DATA_OUT = 0x26001002,
+ GPIO39_GPIO39 = 0x27000000,
+ GPIO39_I2S1_WS = 0x27001000,
+ GPIO39_TEST_PIN4 = 0x27001001,
+ GPIO39_TDM_FS = 0x27001002,
+ GPIO39_PWM0 = 0x27001003,
+ GPIO40_GPIO40 = 0x28000000,
+ GPIO40_I2S1_CLK = 0x28001000,
+ GPIO40_TEST_PIN5 = 0x28001001,
+ GPIO40_TDM_CLK = 0x28001002,
+ GPIO40_PWM1 = 0x28001003,
+ GPIO41_GPIO41 = 0x29000000,
+ GPIO41_I2S1_DIN = 0x29001000,
+ GPIO41_TEST_PIN6 = 0x29001001,
+ GPIO41_TDM_DATA_IN = 0x29001002,
+ GPIO42_GPIO42 = 0x2A000000,
+ GPIO42_I2S1_DOUT = 0x2A001000,
+ GPIO42_TEST_PIN7 = 0x2A001001,
+ GPIO42_TDM_DATA_OUT = 0x2A001002,
+ GPIO43_SCL0 = 0x2B000000,
+ GPIO43_GPIO43 = 0x2B000001,
+ GPIO44_SDA0 = 0x2C000000,
+ GPIO44_GPIO44 = 0x2C000001,
+ GPIO45_GPIO45 = 0x2D000000,
+ GPIO45_SCL1 = 0x2D001000,
+ GPIO46_GPIO46 = 0x2E000000,
+ GPIO46_SDA1 = 0x2E001000,
+ GPIO47_GPIO47 = 0x2F000000,
+ GPIO47_EXT_INT0 = 0x2F000001,
+ GPIO48_GPIO48 = 0x30000000,
+ GPIO48_EXT_INT1 = 0x30000001,
+ GPIO49_GPIO49 = 0x31000000,
+ GPIO49_EXT_INT2 = 0x31000001,
+ GPIO50_GPIO50 = 0x32000000,
+ GPIO50_EXT_INT3 = 0x32000001,
+ GPIO50_TEST_PIN8 = 0x32001000,
+ GPIO51_GPIO51 = 0x33000000,
+ GPIO51_EXT_INT4 = 0x33000001,
+ GPIO51_TEST_PIN9 = 0x33001000,
+ GPIO52_GPIO52 = 0x34000000,
+ GPIO52_EXT_INT5 = 0x34000001,
+ GPIO52_TEST_PIN13 = 0x34001000,
+ GPIO53_GPIO53 = 0x35000000,
+ GPIO53_EXT_INT6 = 0x35000001,
+ GPIO53_TEST_PIN14 = 0x35001000,
+ GPIO54_GPIO54 = 0x36000000,
+ GPIO54_EXT_INT7 = 0x36000001,
+ GPIO54_TEST_PIN15 = 0x36001000,
+ GPIO55_GPIO55 = 0x37000000,
+ GPIO55_RMII_TXEN = 0x37001000,
+ GPIO56_GPIO56 = 0x38000000,
+ GPIO56_RMII_RXEN = 0x38001000,
+ GPIO57_GPIO57 = 0x39000000,
+ GPIO57_RMII_RXD0 = 0x39001000,
+ GPIO58_GPIO58 = 0x3A000000,
+ GPIO58_RMII_RXD1 = 0x3A001000,
+ GPIO59_GPIO59 = 0x3B000000,
+ GPIO59_RMII_TXD0 = 0x3B001000,
+ GPIO60_GPIO60 = 0x3C000000,
+ GPIO60_RMII_TXD1 = 0x3C001000,
+ GPIO61_GPIO61 = 0x3D000000,
+ GPIO61_MDC_SCLK = 0x3D001000,
+ GPIO62_GPIO62 = 0x3E000000,
+ GPIO62_MDC_SDIO = 0x3E001000,
+ GPIO63_GPIO63 = 0x3F000000,
+ GPIO63_PHY_RST = 0x3F001000,
+ GPIO64_GPIO64 = 0x40000000,
+ GPIO64_PHY_INT = 0x40001000,
+ GPIO65_GPIO65 = 0x41000000,
+ GPIO66_GPIO66 = 0x42000000,
+ GPIO66_KEY_COL2 = 0x42000001,
+ GPIO66_EMMC_CLK = 0x42001000,
+ GPIO67_GPIO67 = 0x43000000,
+ GPIO67_KEY_COL3 = 0x43000001,
+ GPIO67_EMMC_CMD = 0x43001000,
+ GPIO68_GPIO68 = 0x44000000,
+ GPIO68_KEY_COL4 = 0x44000001,
+ GPIO68_EMMC_DATA0 = 0x44001000,
+ GPIO69_GPIO69 = 0x45000000,
+ GPIO69_KEY_ROW2 = 0x45000001,
+ GPIO69_EMMC_DATA1 = 0x45001000,
+ GPIO70_GPIO70 = 0x46000000,
+ GPIO70_KEY_ROW3 = 0x46000001,
+ GPIO70_EMMC_DATA2 = 0x46001000,
+
+ GPIO71_GPIO71 = 0x47000000,
+ GPIO71_KEY_ROW4 = 0x47000001,
+ GPIO71_EMMC_DATA3 = 0x47001000,
+ GPIO72_GPIO72 = 0x48000000,
+ GPIO72_SD1_HOST_SDCLK = 0x48001000,
+ GPIO73_GPIO73 = 0x49000000,
+ GPIO73_M_JTAG_TDO = 0x49000001,
+ GPIO73_SD1_CMD = 0x49001000,
+ GPIO73_PS_JTAG_TDO = 0x49001001,
+ GPIO73_PHY_JTAG_TDO = 0x49001002,
+ GPIO73_AP_JTAG_TDO = 0x49001003,
+ GPIO74_GPIO74 = 0x4A000000,
+ GPIO74_M_JTAG_TCK = 0x4A000001,
+ GPIO74_SD1_DATA0 = 0x4A001000,
+ GPIO74_PS_JTAG_TCK = 0x4A001001,
+ GPIO74_PHY_JTAG_TCK = 0x4A001002,
+ GPIO74_AP_JTAG_TCK = 0x4A001003,
+ GPIO75_GPIO75 = 0x4B000000,
+ GPIO75_M_JTAG_TRST = 0x4B000001,
+ GPIO75_SD1_DATA1 = 0x4B001000,
+ GPIO75_PS_JTAG_TRST = 0x4B001001,
+ GPIO75_PHY_JTAG_TRST = 0x4B001002,
+ GPIO75_AP_JTAG_TRST = 0x4B001003,
+ GPIO76_GPIO76 = 0x4C000000,
+ GPIO76_M_JTAG_TMS = 0x4C000001,
+ GPIO76_SD1_DATA2 = 0x4C001000,
+ GPIO76_PS_JTAG_TMS = 0x4C001001,
+ GPIO76_PHY_JTAG_TMS = 0x4C001002,
+ GPIO76_AP_JTAG_TMS = 0x4C001003,
+ GPIO77_GPIO77 = 0x4D000000,
+ GPIO77_M_JTAG_TDI = 0x4D000001,
+ GPIO77_SD1_DATA3 = 0x4D001000,
+ GPIO77_PS_JTAG_TDI = 0x4D001001,
+ GPIO77_PHY_JTAG_TDI = 0x4D001002,
+ GPIO77_AP_JTAG_TDI = 0x4D001003,
+ GPIO78_M_JTAG_TCK = 0x4E000000,
+ GPIO78_GPIO78 = 0x4E000001,
+ GPIO78_PS_JTAG_TCK = 0x4E001000,
+ GPIO78_PHY_JTAG_TCK = 0x4E001001,
+ GPIO78_AP_JTAG_TCK = 0x4E001002,
+ GPIO79_M_JTAG_TDI = 0x4F000000,
+ GPIO79_GPIO79 = 0x4F000001,
+ GPIO79_PS_JTAG_TDI = 0x4F001000,
+ GPIO79_PHY_JTAG_TDI = 0x4F001001,
+ GPIO79_AP_JTAG_TDI = 0x4F001002,
+ GPIO80_M_JTAG_TDO = 0x50000000,
+ GPIO80_GPIO80 = 0x50000001,
+ GPIO80_PS_JTAG_TDO = 0x50001000,
+ GPIO80_PHY_JTAG_TDO = 0x50001001,
+ GPIO80_AP_JTAG_TDO = 0x50001002,
+ GPIO81_M_JTAG_TMS = 0x51000000,
+ GPIO81_GPIO81 = 0x51000001,
+ GPIO81_PS_JTAG_TMS = 0x51001000,
+ GPIO81_PHY_JTAG_TMS = 0x51001001,
+ GPIO81_AP_JTAG_TMS = 0x51001002,
+ GPIO82_M_JTAG_TRST = 0x52000000,
+ GPIO82_GPIO82 = 0x52000001,
+ GPIO82_PS_JTAG_TRST = 0x52001000,
+ GPIO82_PHY_JTAG_TRST = 0x52001001,
+ GPIO82_AP_JTAG_TRST = 0x52001002,
+ GPIO83_KEY_COL0 = 0x53000000,
+ GPIO83_GPIO83 = 0x53000001,
+ GPIO84_KEY_COL1 = 0x54000000,
+ GPIO84_GPIO84 = 0x54000001,
+ GPIO85_KEY_ROW0 = 0x55000000,
+ GPIO85_GPIO85 = 0x55000001,
+ GPIO86_KEY_ROW1 = 0x56000000,
+ GPIO86_GPIO86 = 0x56000001,
+ GPIO87_GPIO87 = 0x57000000,
+ GPIO87_CAM_SPI_CS = 0x57001000,
+ GPIO88_GPIO88 = 0x58000000,
+ GPIO88_CAM_SPI_CLK = 0x58001000,
+ GPIO89_GPIO89 = 0x59000000,
+ GPIO89_CAM_SPI_DATA0 = 0x59001000,
+ GPIO90_GPIO90 = 0x5A000000,
+ GPIO90_CAM_SPI_DATA1 = 0x5A001000,
+ GPIO90_CAM_SPI_TXD = 0x5A001001,
+ GPIO91_GPIO91 = 0x5B000000,
+ GPIO91_CAM_SPI_DATA2 = 0x5B001000,
+ GPIO92_GPIO92 = 0x5C000000,
+ GPIO92_CAM_SPI_DATA3 = 0x5C001000,
+ GPIO93_GPIO93 = 0x5D000000,
+ GPIO93_SPIFC_CS = 0x5D001000,
+ GPIO94_GPIO94 = 0x5E000000,
+ GPIO94_SPIFC_CLK = 0x5E001000,
+ GPIO95_GPIO95 = 0x5F000000,
+ GPIO95_SPIFC_DATA0 = 0x5F001000,
+ GPIO96_GPIO96 = 0x60000000,
+ GPIO96_SPIFC_DATA1 = 0x60001000,
+ GPIO97_GPIO97 = 0x61000000,
+ GPIO97_SPIFC_DATA2 = 0x61001000,
+ GPIO98_GPIO98 = 0x62000000,
+ GPIO98_SPIFC_DATA3 = 0x62001000,
+ GPIO99_GPIO99 = 0x63000000,
+ GPIO100_GPIO100 = 0x64000000,
+ GPIO100_RF_SPI_STR = 0x64001000,
+ GPIO101_GPIO101 = 0x65000000,
+ GPIO101_RF_SPI_CLK = 0x65001000,
+ GPIO102_GPIO102 = 0x66000000,
+ GPIO102_RF_SPI_DATA = 0x66001000,
+ GPIO103_GPIO103 = 0x67000000,
+ GPIO104_GPIO104 = 0x68000000,
+ GPIO104_TD_G0_GPIO2 = 0x68001081,
+ GPIO104_LTE_TPU_OUT0_5 = 0x68001009,
+ GPIO104_W_G0_GPIO2 = 0x68001011,
+ GPIO104_GSM_T_OUT_O_0 = 0x68001021,
+ GPIO105_GPIO105 = 0x69000000,
+ GPIO105_TD_G0_GPIO3 = 0x69001081,
+ GPIO105_LTE_TPU_OUT0_6 = 0x69001009,
+ GPIO105_W_G0_GPIO3 = 0x69001011,
+ GPIO105_GSM_T_OUT_O_1 = 0x69001021,
+ GPIO106_GPIO106 = 0x6A000000,
+ GPIO106_TD_G0_GPIO4 = 0x6A001081,
+ GPIO106_LTE_TPU_OUT0_7 = 0x6A001009,
+ GPIO106_W_G0_GPIO4 = 0x6A001011,
+ GPIO106_GSM_T_OUT_O_2 = 0x6A001021,
+ GPIO107_GPIO107 = 0x6B000000,
+ GPIO107_TD_G0_GPIO5 = 0x6B001081,
+ GPIO107_LTE_TPU_OUT0_8 = 0x6B001009,
+ GPIO107_W_G0_GPIO5 = 0x6B001011,
+ GPIO107_GSM_T_OUT_O_3 = 0x6B001021,
+ GPIO108_GPIO108 = 0x6C000000,
+ GPIO108_TD_G0_GPIO6 = 0x6C001081,
+ GPIO108_LTE_TPU_OUT0_9 = 0x6C001009,
+ GPIO108_W_G0_GPIO6 = 0x6C001011,
+ GPIO108_GSM_T_OUT_O_4 = 0x6C001021,
+ GPIO109_GPIO109 = 0x6D000000,
+ GPIO109_TD_G0_GPIO7 = 0x6D001081,
+ GPIO109_LTE_TPU_OUT0_10 = 0x6D001009,
+ GPIO109_W_G0_GPIO7 = 0x6D001011,
+ GPIO109_GSM_T_OUT_O_5 = 0x6D001021,
+ GPIO110_GPIO110 = 0x6E000000,
+ GPIO110_TD_G0_GPIO8 = 0x6E001081,
+ GPIO110_LTE_TPU_OUT0_11 = 0x6E001009,
+ GPIO110_W_G0_GPIO8 = 0x6E001011,
+ GPIO110_GSM_T_OUT_O_6 = 0x6E001021,
+ GPIO111_GPIO111 = 0x6F000000,
+ GPIO111_TD_G0_GPIO9 = 0x6F001081,
+ GPIO111_LTE_TPU_OUT0_12 = 0x6F001009,
+ GPIO111_W_G0_GPIO9 = 0x6F001011,
+ GPIO111_GSM_T_OUT_O_7 = 0x6F001021,
+ GPIO112_GPIO112 = 0x70000000,
+ GPIO112_MIPI_RFFE_CLK0 = 0x70001006,
+ GPIO112_TD_G0_GPIO10 = 0x70001081,
+ GPIO112_LTE_TPU_OUT0_13 = 0x70001009,
+ GPIO112_W_G0_GPIO10 = 0x70001011,
+ GPIO112_GSM_T_OUT_O_8 = 0x70001021,
+ GPIO113_GPIO113 = 0x71000000,
+ GPIO113_MIPI_RFFE_DATA0 = 0x71001006,
+ GPIO113_TD_G0_GPIO11 = 0x71001081,
+ GPIO113_LTE_TPU_OUT0_14 = 0x71001009,
+ GPIO113_W_G0_GPIO11 = 0x71001011,
+ GPIO113_GSM_T_OUT_O_9 = 0x71001021,
+ GPIO114_GPIO114 = 0x72000000,
+ GPIO114_MIPI_RFFE_CLK1 = 0x72001006,
+ GPIO114_ABB_I2C_SEL_PINMUX = 0x72000001,
+ GPIO114_TD_G0_GPIO12 = 0x72001081,
+ GPIO114_LTE_TPU_OUT0_15 = 0x72001009,
+ GPIO114_W_G0_GPIO12 = 0x72001011,
+ GPIO114_GSM_T_OUT_O_10 = 0x72001021,
+ GPIO115_GPIO115 = 0x73000000,
+ GPIO115_ABB_I2C_SDA_PINMUX = 0x73000001,
+ GPIO115_MIPI_RFFE_DATA1 = 0x73001006,
+ GPIO115_TD_G1_GPIO0 = 0x73001081,
+ GPIO115_LTE_TPU_OUT1_0 = 0x73001009,
+ GPIO115_W_G1_GPIO0 = 0x73001011,
+ GPIO115_GSM_T_OUT_O_11 = 0x73001021,
+
+ GPIO133_GPIO133 = 0x85000000,
+ GPIO133_SIM1_RST = 0x85000001,
+ GPIO133_TD_G1_GPIO1 = 0x85001081,
+ GPIO133_LTE_TPU_OUT1_1 = 0x85001009,
+ GPIO133_W_G1_GPIO1 = 0x85001011,
+ GPIO133_GSM_T_OUT_O_12 = 0x85001021,
+ GPIO134_GPIO134 = 0x86000000,
+ GPIO134_SIM1_CLK = 0x86000001,
+ GPIO134_TD_G1_GPIO2 = 0x86001081,
+ GPIO134_LTE_TPU_OUT1_2 = 0x86001009,
+ GPIO134_W_G1_GPIO2 = 0x86001011,
+ GPIO134_GSM_T_OUT_O_13 = 0x86001021,
+ GPIO135_GPIO135 = 0x87000000,
+ GPIO135_SIM1_DATA = 0x87000001,
+ GPIO135_TD_G1_GPIO3 = 0x87001081,
+ GPIO135_LTE_TPU_OUT1_3 = 0x87001009,
+ GPIO135_W_G1_GPIO3 = 0x87001011,
+ GPIO135_GSM_T_OUT_O_14 = 0x87001021,
+
+ GPIO116_SIM_RST = 0x74000000,
+ GPIO116_GPIO116 = 0x74000001,
+ GPIO117_SIM_CLK = 0x75000000,
+ GPIO117_GPIO117 = 0x75000001,
+ GPIO118_SIM_DATA = 0x76000000,
+ GPIO118_GPIO118 = 0x76000001,
+ GPIO119_GPIO119 = 0x77000000,
+ GPIO119_EXT_INT8 = 0x77000001,
+ GPIO119_M_JTAG_TDO = 0x77000002,
+ GPIO119_URAT0_RTS = 0x77000003,
+ GPIO119_PSJTAG_TDO = 0x77001000,
+ GPIO119_PHYJTAG_TDO = 0x77001001,
+ GPIO119_APJTAG_TDO = 0x77001002,
+ GPIO119_PWM0 = 0x77001003,
+ GPIO120_GPIO120 = 0x78000000,
+ GPIO120_EXT_INT9 = 0x78000001,
+ GPIO120_M_JTAG_TCK = 0x78000002,
+ GPIO120_UART0_CTS = 0x78000003,
+ GPIO120_PSJTAG_TCK = 0x78001000,
+ GPIO120_PHYJTAG_TCK = 0x78001001,
+ GPIO120_APJTAG_TCK = 0x78001002,
+ GPIO120_PWM1 = 0x78001003,
+ GPIO121_GPIO121 = 0x79000000,
+ GPIO121_EXT_INT10 = 0x79000001,
+ GPIO121_M_JTAG_TRST = 0x79000002,
+ GPIO121_PSJTAG_TRST = 0x79001000,
+ GPIO121_PHYJTAG_TRST = 0x79001001,
+ GPIO121_APJTAG_TRST = 0x79001002,
+ GPIO121_UART2_RXD = 0x79001003,
+ GPIO122_GPIO122 = 0x7A000000,
+ GPIO122_EXT_INT11 = 0x7A000001,
+ GPIO122_M_JTAG_TMS = 0x7A000002,
+ GPIO122_PSJTAG_TMS = 0x7A001000,
+ GPIO122_PHYJTAG_TMS = 0x7A001001,
+ GPIO122_APJTAG_TMS = 0x7A001002,
+ GPIO122_UART2_TXD = 0x7A001003,
+ GPIO123_GPIO123 = 0x7B000000,
+ GPIO123_EXT_INT12 = 0x7B000001,
+ GPIO123_M_JTAG_TDI = 0x7B000002,
+ GPIO123_PSJTAG_TDI = 0x7B001000,
+ GPIO123_PHYJTAG_TDI = 0x7B001001,
+ GPIO123_APJTAG_TDI = 0x7B001002,
+ GPIO123_UART2_RTS = 0x7B001003,
+ GPIO124_GPIO124 = 0x7C000000,
+ GPIO124_EXT_INT13 = 0x7C000001,
+ GPIO124_UART2_CTS = 0x7C001000,
+ GPIO125_GPIO125 = 0x7D000000,
+ GPIO125_EXT_INT14 = 0x7D000001,
+ GPIO125_UART1_RTS = 0x7D001000,
+ GPIO126_GPIO126 = 0x7E000000,
+ GPIO126_EXT_INT15 = 0x7E000001,
+ GPIO126_KEY_COL2 = 0x7E000002,
+ GPIO126_UART1_CTS = 0x7E001000,
+ GPIO127_GPIO127 = 0x7F000000,
+ GPIO127_EXT_INT8 = 0x7F000001,
+ GPIO127_KEY_COL3 = 0x7F000002,
+ GPIO128_GPIO128 = 0x80000000,
+ GPIO128_EXT_INT9 = 0x80000001,
+ GPIO128_KEY_COL4 = 0x80000002,
+ GPIO129_GPIO129 = 0x81000000,
+ GPIO129_EXT_INT10 = 0x81000001,
+ GPIO129_KEY_COL5 = 0x81000002,
+ GPIO130_GPIO130 = 0x82000000,
+ GPIO130_EXT_INT11 = 0x82000001,
+ GPIO130_KEY_ROW2 = 0x82000002,
+ GPIO131_GPIO131 = 0x83000000,
+ GPIO131_EXT_INT12 = 0x83000001,
+ GPIO131_KEY_ROW3 = 0x83000002,
+ GPIO132_GPIO132 = 0x84000000,
+ GPIO132_EXT_INT13 = 0x84000001,
+ GPIO132_KEY_ROW4 = 0x84000002,
+
+
+}T_ZDrvGpio_FuncSel;
+#elif defined (_CHIP_ZX297520V2)
+typedef enum
+{
+ /*[31:24]:gpio_id [23:12]:level1_sel [11:0]:level2_sel*/
+ GPIO0_GPIO0 = 0x00000000,
+ GPIO0_NAND_WE = 0x00001000,
+ GPIO1_GPIO1 = 0x01000000,
+ GPIO1_NAND_CS0 = 0x01001000,
+ GPIO2_GPIO2 = 0x02000000,
+ GPIO2_NAND_READY = 0x02001000,
+ GPIO3_GPIO3 = 0x03000000,
+ GPIO3_NAND_CLE = 0x03001000,
+ GPIO3_SPIFC0_SCLK = 0x03001001,
+ GPIO4_GPIO4 = 0x04000000,
+ GPIO4_NAND_ALE = 0x04001000,
+ GPIO5_GPIO5 = 0x05000000,
+ GPIO5_NAND_RE = 0x05001000,
+ GPIO5_SPIFC0_CS = 0x05001001,
+ GPIO6_GPIO6 = 0x06000000,
+ GPIO6_NAND_WRITE_PROTECT = 0x06001000,
+ GPIO7_GPIO7 = 0x07000000,
+ GPIO7_NAND_DATA0 = 0x07001000,
+ GPIO7_SSP1_CS = 0x07001001,
+ GPIO8_GPIO8 = 0x08000000,
+ GPIO8_NAND_DATA1 = 0x08001000,
+ GPIO8_SSP1_CLK = 0x08001001,
+ GPIO9_GPIO9 = 0x09000000,
+ GPIO9_NAND_DATA2 = 0x09001000,
+ GPIO9_SPIFC0_DATA0 = 0x09001001,
+ GPIO10_GPIO10 = 0x0A000000,
+ GPIO10_NAND_DATA3 = 0x0A001000,
+ GPIO10_SPIFC0_DATA1 = 0x0A001001,
+ GPIO11_GPIO11 = 0x0B000000,
+ GPIO11_NAND_DATA4 = 0x0B001000,
+ GPIO11_SPIFC0_DATA2 = 0x0B001001,
+ GPIO12_GPIO12 = 0x0C000000,
+ GPIO12_NAND_DATA5 = 0x0C001000,
+ GPIO12_SPIFC0_DATA3 = 0x0C001001,
+ GPIO13_GPIO13 = 0x0D000000,
+ GPIO13_NAND_DATA6 = 0x0D001000,
+ GPIO13_SSP1_RXD = 0x0D001001,
+ GPIO14_GPIO14 = 0x0E000000,
+ GPIO14_NAND_DATA7 = 0x0E001000,
+ GPIO14_SSP1_TXD = 0x0E001001,
+ GPIO23_CLK_OUT0 = 0x17000000,
+ GPIO23_GPIO23 = 0x17000001,
+ GPIO24_GPIO24 = 0x18000000,
+ GPIO24_CLK_OUT1 = 0x18000001,
+ GPIO25_GPIO25 = 0x19000000,
+ GPIO25_CLK_OUT2 = 0x19000001,
+ GPIO25_TEST_CLK_OUT = 0x19000002,
+ GPIO26_GPIO26 = 0x1A000000,
+ GPIO26_CLK_32K_OUT = 0x1A000001,
+ GPIO27_CLK_REQ0 = 0x1B000000,
+ GPIO27_GPIO27 = 0x1B000001,
+ GPIO29_PWRCTRL1 = 0x1D000000,
+ GPIO29_GPIO29 = 0x1D000001,
+ GPIO30_GPIO30 = 0x1E000000,
+ GPIO30_SSP0_CS = 0x1E001000,
+ GPIO31_GPIO31 = 0x1F000000,
+ GPIO31_SSP0_CLK = 0x1F001000,
+ GPIO32_GPIO32 = 0x20000000,
+ GPIO32_SSP0_RXD = 0x20001000,
+ GPIO33_GPIO33 = 0x21000000,
+ GPIO33_SSP0_TXD = 0x21001000,
+ GPIO34_UART0_RXD = 0x22000000,
+ GPIO34_GPIO34 = 0x22000001,
+ GPIO34_UART0_TXD = 0x22000002,
+ GPIO34_FRAME_SYNC = 0x22001000,
+ GPIO34_TEST_PIN10 = 0x22001001,
+ GPIO35_UART0_TXD = 0x23000000,
+ GPIO35_GPIO35 = 0x23000001,
+ GPIO35_UART0_RXD = 0x23000002,
+ GPIO35_LTE_PRE_TX = 0x23001000,
+ GPIO35_TEST_PIN11 = 0x23001001,
+ GPIO36_UART0_CTS = 0x24000000,
+ GPIO36_GPIO36 = 0x24000001,
+ GPIO36_UART1_RXD = 0x24001000,
+ GPIO36_LTE_TPU_OUT3 = 0x24001001,
+ GPIO36_TEST_PIN12 = 0x24001002,
+ GPIO36_UART1_TXD = 0x24001003,
+ GPIO37_UART0_RTS = 0x25000000,
+ GPIO37_GPIO37 = 0x25000001,
+ GPIO37_UART1_TXD = 0x25001000,
+ GPIO37_LTE_TPU_OUT4 = 0x25001001,
+ GPIO37_UART1_RXD = 0x25001002,
+ GPIO38_GPIO38 = 0x26000000,
+ GPIO38_I2S0_WS = 0x26001000,
+ GPIO38_TEST_PIN0 = 0x26001001,
+ GPIO38_LTE_DATA_DONGLE_CLK = 0x26001002,
+ GPIO38_TDM_FS = 0x26001003,
+ GPIO39_GPIO39 = 0x27000000,
+ GPIO39_I2S0_CLK = 0x27001000,
+ GPIO39_TEST_PIN1 = 0x27001001,
+ GPIO39_LTE_DATA_DONGLE_CMD = 0x27001002,
+ GPIO39_TDM_CLK = 0x27001003,
+ GPIO40_GPIO40 = 0x28000000,
+ GPIO40_I2S0_DIN = 0x28001000,
+ GPIO40_TEST_PIN2 = 0x28001001,
+ GPIO40_LTE_DATA_DONGLE0 = 0x28001002,
+ GPIO40_TDM_DATA_IN = 0x28001003,
+ GPIO41_GPIO41 = 0x29000000,
+ GPIO41_I2S0_DOUT = 0x29001000,
+ GPIO41_TEST_PIN3 = 0x29001001,
+ GPIO41_LTE_DATA_DONGLE1 = 0x29001002,
+ GPIO41_TDM_DATA_OUT = 0x29001003,
+ GPIO42_GPIO42 = 0x2A000000,
+ GPIO42_I2S1_WS = 0x2A001000,
+ GPIO42_TEST_PIN4 = 0x2A001001,
+ GPIO42_LTE_DATA_DONGLE2 = 0x2A001002,
+ GPIO42_TDM_FS = 0x2A001003,
+ GPIO43_GPIO43 = 0x2B000000,
+ GPIO43_I2S1_CLK = 0x2B001000,
+ GPIO43_TEST_PIN5 = 0x2B001001,
+ GPIO43_LTE_DATA_DONGLE3 = 0x2B001002,
+ GPIO43_TDM_CLK = 0x2B001003,
+ GPIO44_GPIO44 = 0x2C000000,
+ GPIO44_I2S1_DIN = 0x2C001000,
+ GPIO44_TEST_PIN6 = 0x2C001001,
+ GPIO44_TDM_DATA_IN = 0x2C001002,
+ GPIO45_GPIO45 = 0x2D000000,
+ GPIO45_I2S1_DOUT = 0x2D001000,
+ GPIO45_TEST_PIN7 = 0x2D001001,
+ GPIO45_TDM_DATA_OUT = 0x2D001002,
+ GPIO46_SCL0 = 0x2E000000,
+ GPIO46_GPIO46 = 0x2E000001,
+ GPIO47_SDA0 = 0x2F000000,
+ GPIO47_GPIO47 = 0x2F000001,
+ GPIO48_GPIO48 = 0x30000000,
+ GPIO48_SCL1 = 0x30001000,
+ GPIO49_GPIO49 = 0x31000000,
+ GPIO49_SDA1 = 0x31001000,
+ GPIO50_GPIO50 = 0x32000000,
+ GPIO50_EXT_INT0 = 0x32000001,
+ GPIO51_GPIO51 = 0x33000000,
+ GPIO51_EXT_INT1 = 0x33000001,
+ GPIO52_GPIO52 = 0x34000000,
+ GPIO52_EXT_INT2 = 0x34000001,
+ GPIO53_GPIO53 = 0x35000000,
+ GPIO53_EXT_INT3 = 0x35000001,
+ GPIO53_TEST_PIN8 = 0x35001000,
+ GPIO54_GPIO54 = 0x36000000,
+ GPIO54_EXT_INT4 = 0x36000001,
+ GPIO54_TEST_PIN9 = 0x36001000,
+ GPIO55_GPIO55 = 0x37000000,
+ GPIO55_EXT_INT5 = 0x37000001,
+ GPIO55_TEST_PIN13 = 0x37001000,
+ GPIO56_GPIO56 = 0x38000000,
+ GPIO56_EXT_INT6 = 0x38000001,
+ GPIO56_CLK_REQ1 = 0x38000002,
+ GPIO56_TEST_PIN14 = 0x38001000,
+ GPIO57_GPIO57 = 0x39000000,
+ GPIO57_EXT_INT7 = 0x39000001,
+ GPIO57_TEST_PIN15 = 0x39001000,
+ GPIO58_GPIO58 = 0x3A000000,
+ GPIO58_SD1_HOST_SDCLK = 0x3A001000,
+ GPIO59_GPIO59 = 0x3B000000,
+ GPIO59_M_JTAG_TDO = 0x3B000001,
+ GPIO59_SD1_CMD = 0x3B001000,
+ GPIO59_PS_JTAG_TDO = 0x3B001001,
+ GPIO59_PHY_JTAG_TDO = 0x3B001002,
+ GPIO59_AP_JTAG_TDO = 0x3B001003,
+ GPIO60_GPIO60 = 0x3C000000,
+ GPIO60_M_JTAG_TCK = 0x3C000001,
+ GPIO60_SD1_DATA0 = 0x3C001000,
+ GPIO60_PS_JTAG_TCK = 0x3C001001,
+ GPIO60_PHY_JTAG_TCK = 0x3C001002,
+ GPIO60_AP_JTAG_TCK = 0x3C001003,
+ GPIO61_GPIO61 = 0x3D000000,
+ GPIO61_M_JTAG_TRST = 0x3D000001,
+ GPIO61_SD1_DATA1 = 0x3D001000,
+ GPIO61_PS_JTAG_TRST = 0x3D001001,
+ GPIO61_PHY_JTAG_TRST = 0x3D001002,
+ GPIO61_AP_JTAG_TRST = 0x3D001003,
+ GPIO62_GPIO62 = 0x3E000000,
+ GPIO62_M_JTAG_TMS = 0x3E000001,
+ GPIO62_SD1_DATA2 = 0x3E001000,
+ GPIO62_PS_JTAG_TMS = 0x3E001001,
+ GPIO62_PHY_JTAG_TMS = 0x3E001002,
+ GPIO62_AP_JTAG_TMS = 0x3E001003,
+ GPIO63_GPIO63 = 0x3F000000,
+ GPIO63_M_JTAG_TDI = 0x3F000001,
+ GPIO63_SD1_DATA3 = 0x3F001000,
+ GPIO63_PS_JTAG_TDI = 0x3F001001,
+ GPIO63_PHY_JTAG_TDI = 0x3F001002,
+ GPIO63_AP_JTAG_TDI = 0x3F001003,
+ GPIO64_M_JTAG_TCK = 0x40000000,
+ GPIO64_GPIO64 = 0x40000001,
+ GPIO64_PS_JTAG_TCK = 0x40001000,
+ GPIO64_PHY_JTAG_TCK = 0x40001001,
+ GPIO64_AP_JTAG_TCK = 0x40001002,
+ GPIO66_M_JTAG_TDI = 0x42000000,
+ GPIO66_GPIO66 = 0x42000001,
+ GPIO66_PS_JTAG_TDI = 0x42001000,
+ GPIO66_PHY_JTAG_TDI = 0x42001001,
+ GPIO66_AP_JTAG_TDI = 0x42001002,
+ GPIO67_M_JTAG_TDO = 0x43000000,
+ GPIO67_GPIO67 = 0x43000001,
+ GPIO67_PS_JTAG_TDO = 0x43001000,
+ GPIO67_PHY_JTAG_TDO = 0x43001001,
+ GPIO67_AP_JTAG_TDO = 0x43001002,
+ GPIO68_M_JTAG_TMS = 0x44000000,
+ GPIO68_GPIO68 = 0x44000001,
+ GPIO68_PS_JTAG_TMS = 0x44001000,
+ GPIO68_PHY_JTAG_TMS = 0x44001001,
+ GPIO68_AP_JTAG_TMS = 0x44001002,
+ GPIO69_M_JTAG_TRST = 0x45000000,
+ GPIO69_GPIO69 = 0x45000001,
+ GPIO69_PS_JTAG_TRST = 0x45001000,
+ GPIO69_PHY_JTAG_TRST = 0x45001001,
+ GPIO69_AP_JTAG_TRST = 0x45001002,
+ GPIO70_KEY_COL0 = 0x46000000,
+ GPIO70_GPIO70 = 0x46000001,
+ GPIO70_EXT_INT8 = 0x46000002,
+ GPIO70_M_JTAG_TDO = 0x46000003,
+ GPIO70_PS_JTAG_TDO = 0x46001000,
+ GPIO70_PHY_JTAG_TDO = 0x46001001,
+ GPIO70_AP_JTAG_TDO = 0x46001002,
+ GPIO70_LTE_DATA_DONGLE4 = 0x46001003,
+ GPIO71_KEY_COL1 = 0x47000000,
+ GPIO71_GPIO71 = 0x47000001,
+ GPIO71_EXT_INT9 = 0x47000002,
+ GPIO71_LTE_DATA_DONGLE5 = 0x47001000,
+ GPIO72_KEY_COL2 = 0x48000000,
+ GPIO72_GPIO72 = 0x48000001,
+ GPIO72_EXT_INT10 = 0x48000002,
+ GPIO72_M_JTAG_TCK = 0x48000003,
+ GPIO72_PS_JTAG_TCK = 0x48001000,
+ GPIO72_PHY_JTAG_TCK = 0x48001001,
+ GPIO72_AP_JTAG_TCK = 0x48001002,
+ GPIO72_LTE_DATA_DONGLE6 = 0x48001003,
+ GPIO73_KEY_COL3 = 0x49000000,
+ GPIO73_GPIO73 = 0x49000001,
+ GPIO73_EXT_INT11 = 0x49000002,
+ GPIO73_LTE_DATA_DONGLE7 = 0x49001000,
+ GPIO74_KEY_ROW0 = 0x4A000000,
+ GPIO74_GPIO74 = 0x4A000001,
+ GPIO74_EXT_INT12 = 0x4A000002,
+ GPIO74_M_JTAG_TRST = 0x4A000003,
+ GPIO74_PS_JTAG_TRST = 0x4A001000,
+ GPIO74_PHY_JTAG_TRST = 0x4A001001,
+ GPIO74_AP_JTAG_TRST = 0x4A001002,
+ GPIO74_LTE_DATA_DONGLE8 = 0x4A001003,
+ GPIO75_KEY_ROW1 = 0x4B000000,
+ GPIO75_GPIO75 = 0x4B000001,
+ GPIO75_EXT_INT13 = 0x4B000002,
+ GPIO75_M_JTAG_TMS = 0x4B000003,
+ GPIO75_PS_JTAG_TMS = 0x4B001000,
+ GPIO75_PHY_JTAG_TMS = 0x4B001001,
+ GPIO75_AP_JTAG_TMS = 0x4B001002,
+ GPIO75_LTE_DATA_DONGLE9 = 0x4B001003,
+ GPIO76_KEY_ROW2 = 0x4C000000,
+ GPIO76_GPIO76 = 0x4C000001,
+ GPIO76_EXT_INT14 = 0x4C000002,
+ GPIO76_M_JTAG_TDI = 0x4C000003,
+ GPIO76_PS_JTAG_TDI = 0x4C001000,
+ GPIO76_PHY_JTAG_TDI = 0x4C001001,
+ GPIO76_AP_JTAG_TDI = 0x4C001002,
+ GPIO76_UART2_RXD = 0x4C001003,
+ GPIO77_KEY_ROW3 = 0x4D000000,
+ GPIO77_GPIO77 = 0x4D000001,
+ GPIO77_EXT_INT15 = 0x4D000002,
+ GPIO77_UART2_TXD = 0x4D001000,
+ GPIO78_GPIO78 = 0x4E000000,
+ GPIO78_MODEM_TXRX_DATA0 = 0x4E001000,
+ GPIO79_GPIO79 = 0x4F000000,
+ GPIO79_MODEM_TXRX_DATA1 = 0x4F001000,
+ GPIO80_GPIO80 = 0x50000000,
+ GPIO80_MODEM_TXRX_DATA2 = 0x50001000,
+ GPIO81_GPIO81 = 0x51000000,
+ GPIO81_MODEM_TXRX_DATA3 = 0x51001000,
+ GPIO82_GPIO82 = 0x52000000,
+ GPIO82_MODEM_TXRX_DATA4 = 0x52001000,
+ GPIO83_GPIO83 = 0x53000000,
+ GPIO83_MODEM_TXRX_DATA5 = 0x53001000,
+ GPIO84_GPIO84 = 0x54000000,
+ GPIO84_MODEM_TXRX_DATA6 = 0x54001000,
+ GPIO85_GPIO85 = 0x55000000,
+ GPIO85_MODEM_TXRX_DATA7 = 0x55001000,
+ GPIO86_GPIO86 = 0x56000000,
+ GPIO86_MODEM_TXRX_DATA8 = 0x56001000,
+ GPIO87_GPIO87 = 0x57000000,
+ GPIO87_MODEM_TXRX_DATA9 = 0x57001000,
+ GPIO88_GPIO88 = 0x58000000,
+ GPIO88_MODEM_TXRX_DATA10 = 0x58001000,
+ GPIO89_GPIO89 = 0x59000000,
+ GPIO89_MODEM_TXRX_DATA11 = 0x59001000,
+ GPIO90_GPIO90 = 0x5A000000,
+ GPIO90_MODEM_RX_DATA0 = 0x5A001000,
+ GPIO91_GPIO91 = 0x5B000000,
+ GPIO91_MODEM_RX_DATA1 = 0x5B001000,
+ GPIO92_GPIO92 = 0x5C000000,
+ GPIO92_MODEM_RX_DATA2 = 0x5C001000,
+ GPIO93_GPIO93 = 0x5D000000,
+ GPIO93_MODEM_RX_DATA3 = 0x5D001000,
+ GPIO94_GPIO94 = 0x5E000000,
+ GPIO94_MODEM_RX_DATA4 = 0x5E001000,
+ GPIO95_GPIO95 = 0x5F000000,
+ GPIO95_MODEM_RX_DATA5 = 0x5F001000,
+ GPIO96_GPIO96 = 0x60000000,
+ GPIO96_MODEM_RX_DATA6 = 0x60001000,
+ GPIO97_GPIO97 = 0x61000000,
+ GPIO97_MODEM_RX_DATA7 = 0x61001000,
+ GPIO98_GPIO98 = 0x62000000,
+ GPIO98_MODEM_RX_DATA8 = 0x62001000,
+ GPIO99_GPIO99 = 0x63000000,
+ GPIO99_MODEM_RX_DATA9 = 0x63001000,
+ GPIO100_GPIO100 = 0x64000000,
+ GPIO100_MODEM_RX_DATA10 = 0x64001000,
+ GPIO101_GPIO101 = 0x65000000,
+ GPIO101_MODEM_RX_DATA11 = 0x65001000,
+ GPIO102_GPIO102 = 0x66000000,
+ GPIO102_MODEM_FCLK_O = 0x66001000,
+ GPIO103_GPIO103 = 0x67000000,
+ GPIO103_MODEM_FRAME_TX_O = 0x67001000,
+ GPIO104_GPIO104 = 0x68000000,
+ GPIO104_MODEM_FRAME_RX_I = 0x68001000,
+ GPIO105_GPIO105 = 0x69000000,
+ GPIO105_MODEM_MCLK_I = 0x69001000,
+ GPIO106_GPIO106 = 0x6A000000,
+ GPIO106_LTE_REF_CLK = 0x6A001000,
+ /*GPIO107 GPIO108*/
+ GPIO109_GPIO109 = 0x6D000000,
+ GPIO110_GPIO110 = 0x6E000000,
+ GPIO110_GSM_OUT_OLD_O_12 = 0x6E000001,
+ GPIO111_PWRCTRL2 = 0x6F000000,
+ GPIO111_GPIO111 = 0x6F000001,
+ GPIO112_GPIO112 = 0x70000000,
+ GPIO112_RF_SPI0_STR0 = 0x70001000,
+ GPIO113_GPIO113 = 0x71000000,
+ GPIO113_RF_SPI0_STR1 = 0x71001000,
+ GPIO114_GPIO114 = 0x72000000,
+ GPIO114_RF_SPI0_CLK = 0x72001000,
+ GPIO115_GPIO115 = 0x73000000,
+ GPIO115_RF_SPI0_DIN = 0x73001000,
+ GPIO116_GPIO116 = 0x74000000,
+ GPIO116_RF_SPI0_DATA = 0x74001000,
+ GPIO117_GPIO117 = 0x75000000,
+ GPIO117_RF_SPI1_STR0 = 0x75001000,
+ GPIO118_GPIO118 = 0x76000000,
+ GPIO118_RF_SPI1_CLK = 0x76001000,
+ GPIO119_GPIO119 = 0x77000000,
+ GPIO119_RF_SPI1_DIN = 0x77001000,
+ GPIO120_GPIO120 = 0x78000000,
+ GPIO120_RF_SPI1_DATA = 0x78001000,
+ /*GPIO121 --GPIO144*/
+ GPIO145_GPIO145 = 0x91000000,
+ GPIO145_RMII_TXEN = 0x91001000,
+ GPIO146_GPIO146 = 0x92000000,
+ GPIO146_RMII_RXEN = 0x92001000,
+ GPIO147_GPIO147 = 0x93000000,
+ GPIO147_RMII_RXD0 = 0x93001000,
+ GPIO148_GPIO148 = 0x94000000,
+ GPIO148_RMII_RXD1 = 0x94001000,
+ GPIO149_GPIO149 = 0x95000000,
+ GPIO149_RMII_TXD0 = 0x95001000,
+ GPIO150_GPIO150 = 0x96000000,
+ GPIO150_RMII_TXD1 = 0x96001000,
+ GPIO151_GPIO151 = 0x97000000,
+ GPIO151_MDC_SCLK = 0x97001000,
+ GPIO152_GPIO152 = 0x98000000,
+ GPIO152_MDC_SDIO = 0x98001000,
+ GPIO153_GPIO153 = 0x99000000,
+ GPIO153_PHY_RST = 0x99001000,
+ GPIO154_GPIO154 = 0x9A000000,
+ GPIO154_RMII_CLK_O = 0x9A001000,
+ GPIO155_GPIO155 = 0x9B000000,
+ GPIO155_RMII_CLK_I = 0x9B001000,
+
+}T_ZDrvGpio_FuncSel;
+#endif
+/*******************************************************************************
+ * Global function declarations *
+ ******************************************************************************/
+/**
+*@brief This function is used to get descriptor of pin.
+*@param name the name used to distinguish gpio, must added in g_GpioConfig[](in gpio_ref.c)
+*
+*@return pointer of gpio descriptor if success, errcode otherwise
+*/
+UINT32 zDrvGpio_Request(CHAR *name);
+
+/**
+ *@brief This function is used to free this gpio, so others can request it
+ *@param gpio_id pointer of gpio descriptor
+ *
+ *@return 0 if success, errcode otherwise.
+ */
+SINT32 zDrvGpio_Free(UINT32 gpio_id);
+
+/**
+ *@brief This function is used to set the pin use ,used as GPIO or other function
+ *@param gpio_id gpio id
+ *@param func_sel gpio function sel
+ *
+ *@return 0 if success, errcode otherwise.
+ */
+SINT32 zDrvGpio_SetFunc(UINT32 gpio_id, T_ZDrvGpio_FuncSel func_sel);
+
+/**
+ *@brief This function is used to set gpio internal pull up or pull down or none
+ *@param gpio_id gpio id
+ *@param val pull function sel
+ *
+ *@return 0 if success, errcode otherwise.
+ */
+SINT32 zDrvGpio_PullUpDown(UINT32 gpio_id, T_ZDrvGpio_PullUp val);
+
+/**
+ *@brief This function is used to set direction of gpio, in or out
+ *@param gpio_id gpio id
+ *@param value gpio direction sel
+ *
+ *@return none.
+ */
+VOID zDrvGpio_SetDirection(UINT32 gpio_id, T_ZDrvGpio_IoDirection value);
+
+/**
+ *@brief This function is used to get direction of gpio
+ *@param gpio_id gpio id
+ *
+ *@return gpio direction.
+ */
+T_ZDrvGpio_IoDirection zDrvGpio_GetDirection(UINT32 gpio_id);
+
+/**
+ *@brief This function is used to set output value
+ *@param gpio_id gpio id
+ *@param value gpio output val sel
+ *
+ *@return none.
+ */
+VOID zDrvGpio_SetOutputValue(UINT32 gpio_id, T_ZDrvGpio_IoVal value);
+
+/**
+ *@brief This function is used to get output value
+ *@param gpio_id gpio id
+ *
+ *@return output value(high or low).
+ */
+T_ZDrvGpio_IoVal zDrvGpio_GetOutputValue(UINT32 gpio_id);
+
+/**
+ *@brief This function is used to get input value
+ *@param gpio_id gpio id
+ *
+ *@return input value(high or low).
+ */
+T_ZDrvGpio_IoVal zDrvGpio_GetInputValue(UINT32 gpio_id);
+
+/**
+ *@brief This function is used to set gpio pin for jtag
+ *@param jtagNum jtag id 0/1/2
+ *@param function sel jtag connect to which core(0:m0jtag, 1:psjtag, 2:phyjtag, 3:apjtag)
+ *
+ *@return none.
+ */
+VOID zDrvGpio_JtagConfig(UINT32 jtagNum, UINT32 function);
+#endif
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_headsetkey.h b/cp/ps/driver/inc/misc/drvs_headsetkey.h
new file mode 100644
index 0000000..3c496e7
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_headsetkey.h
@@ -0,0 +1,39 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: drvs_headsetkey.h
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: V0.5
+ * Author: zhangyingjun
+ * Date: 2010-02-12
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_HEADSETKEY_H
+#define _DRVS_HEADSETKEY_H
+
+
+
+typedef enum
+{
+ HEADSET_TAKEOFF, /*ÌýͲÄÃÆð */
+ HEADSET_PUTDOWN, /* ÌýͲ¹ÒÉÏ*/
+
+ MAX_HEADSET_EVENT_INT
+} T_ZDrvHeadset_EventInt;
+
+typedef VOID (*zDrvHeadset_CallbackFunc)(T_ZDrvHeadset_EventInt);
+
+
+SINT32 zDrvHeadsetkey_RegisterCallback(zDrvHeadset_CallbackFunc headset_callback);
+
+SINT32 zDrvHeadsetkey_UnregisterCallback(VOID);
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_i2c.h b/cp/ps/driver/inc/misc/drvs_i2c.h
new file mode 100644
index 0000000..8a70f1e
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_i2c.h
@@ -0,0 +1,283 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: V0.5
+ * Author: Zhenghong
+ * Date: 2008-01-10
+ * History 1:
+ * Date: 2012-07-16
+ * Version: V1.0
+ * Author: zhouqi
+ * Modification: 1. Ôö¼Ó T_ZDrvI2c_BusFreq ö¾ÙÖÐ 300KHZ ¶¨Òå
+ 2. ÐÞ¸Ä T_ZDrvI2c_DevFlagType ÖеÚÒ»¸ö I2C_DFLT_ADDR_DEV Ϊ I2C_10BIT_SLAVE_ADDR
+ 3. ÔÚ T_ZDrvI2c_DevFlagType Ôö¼Ó I2C_USE_INT ¶¨Òå
+ 4. Ôö¼Ó²¿·Ö×¢ÊÍÓë˵Ã÷
+ * History 2:
+ ******************************************************************************/
+#ifndef _DRVS_I2C_H
+#define _DRVS_I2C_H
+
+
+
+/**********************************************************/
+/** @defgroup T_ZDrvI2c_BusNum 7520ÓÐ 3 ¸öI2C½Ó¿Ú, 7520V2 È¥µôÒ»¸öI2C
+ */
+typedef enum
+{
+ //I2C_BUS_0 = 0,
+ I2C_BUS_1 = 1,
+ I2C_BUS_2 = 2, /* pmic i2c */
+ MAX_I2C_BUS_NUM
+}T_ZDrvI2c_BusNum;
+
+
+/**********************************************************/
+/** @defgroup T_ZDrvI2c_BusFreq
+ */
+typedef enum{
+ I2C_FREQ_ONE_HUNDRED_KILO_HZ = 100*1000,
+ I2C_FREQ_THREE_HUNDRED_KILO_HZ = 300*1000,
+ I2C_FREQ_FOUR_HUNDRED_KILO_HZ = 400*1000,
+ MAX_I2C_BUS_FREQ
+}T_ZDrvI2c_BusFreq;
+
+
+/**********************************************************/
+/** @defgroup T_ZDrvI2c_DevFlagType
+ */
+typedef enum {
+ I2C_10BIT_SLAVE_ADDR = 0x0001 << 0, /* ±êʶʹÓà --10λ´Ó»úµØÖ·-- */
+ /* ĬÈϲ»Ê¹ÓÃλ 7λ´Ó»úµØÖ· */
+
+ I2C_MEM_DEV = 0x0001 << 1, /* ±êʶʹÓà --16λ¼Ä´æÆ÷µØÖ·-- */
+ I2C_REG_DEV = 0x0001 << 2, /* ±êʶʹÓà --8λ¼Ä´æÆ÷µØÖ·-- */
+
+ I2C_NACK_LAST_BYTE = 0x0001 << 3, /* NACK last byte read from slave */
+ I2C_NOP_LAST_BYTE = 0x0001 << 4, /* Let slave release SDA after last */
+ I2C_M_COMBINE = 0x0001 << 5, /* ¾µäµÄ×éºÏ¶Áģʽ */
+ I2C_STOP_START_BEFORE_READ = 0x0001 << 6, /* During a read transaction, gen. */
+ /* a STOP & START after writing */
+ /* the slave addr(just before read) */
+ I2C_CLK_START_BEFORE_RW = 0x0001 << 7, /* Generate a clock and a START */
+ /* before every I/O operation. */
+ I2C_USE_INT = 0x0001 << 8 /* ʹÓÃÖжÏģʽ´«ÊäÊý¾Ý */
+ /* Çø±ðΪ START ºó£¬»ñÈ¡ÐźÅÁ¿£¬Ï̹߳ÒÆð*/
+ /* ½¨ÒéÔÚ´«ËͶà×Ö½ÚʱʹÓà */
+} T_ZDrvI2c_DevFlagType;
+
+/**********************************************************************/
+/* ˵Ã÷:
+
+ 1. ÔÚĬÈÏÇé¿öÏ£¬Ê¹Óà 7λ ´Ó»úµØÖ·£¬
+ 8λ ¼Ä´æÆ÷µØÖ·
+ ±ê׼ʱÐòµÄ ¼òµ¥Ð´¡¢ ¼òµ¥¶Á¡¢ ×éºÏ¶Áģʽ--
+ ²»Ê¹ÓÃÖжÏ
+
+ 2. ÒÔÇ°ÅäÖÃµÄ ÒÔϲÎÊýÏÖÔÚ²»ÔÙʹÓã¬ÏÈÇ°ÅäÖõÄÒ²²»Óøü¸Ä£¬µ«¶¼Ä¬ÈÏΪ --±ê×¼×éºÏ¶ÁʱÐò--
+ Èç¹ûÓÐÌØÊâʱÐò£¬Çë¸æÖª
+
+ I2C_NACK_LAST_BYTE ÔÚU207ûÓз¢ÏÖʹÓÃ
+ I2C_NOP_LAST_BYTE ÔÚU207ûÓз¢ÏÖʹÓÃ
+ I2C_M_COMBINE RDA5802\mt9d113ʹÓÃ
+ I2C_STOP_START_BEFORE_READ PMIC\OV7670\0V9656ʹÓÃ
+ I2C_CLK_START_BEFORE_RW ÔÚU207ûÓз¢ÏÖʹÓÃ
+
+ 3. ÏÖÔڿɸù¾ÝÒ»ÏÂÁÐ×ÓÅäÖÃ:
+
+ static T_ZDrvI2c_Device s_mt9d113I2cDev =
+ {
+ I2C_BUS_0,
+ EXAMPLE_SLAVE_ADDRESS,
+ I2C_FREQ_THREE_HUNDRED_KILO_HZ,
+ 100,
+ 1,
+ -----------------------------------------------------------
+ I2C_10BIT_SLAVE_ADDR | I2C_REG_DEV | I2C_USE_INT,
+ // ʹÓÃ10´Ó»úµØÖ· 8λ¼Ä´æÆ÷µØÖ· ʹÓÃÖжϷ½Ê½
+
+ I2C_MEM_DEV,
+ // 16λ¼Ä´æÆ÷µØÖ·, 8´Ó»úµØÖ· ²»Ê¹ÓÃÖжÏ
+ ----------------------------------------------------------
+ NULL,
+ };
+*********************************************************************/
+/**********************************************************/
+/** @defgroup T_ZDrvI2c_Device
+ */
+typedef struct _T_ZDrvI2c_Device
+{
+
+ T_ZDrvI2c_BusNum bus_num; /* indicate which i2c bus the device belongs to */
+ UINT16 slv_addr; /* device addr on the i2c bus, 10bits for memory device and 7bits for registers */
+ T_ZDrvI2c_BusFreq bus_freq; /* the i2c bus transfer freq according to the device require*/
+ UINT32 timeout; /* time threshold waiting for bus idle */
+ UINT8 retries; /* times we'll try again if the bus is busy */
+ T_ZDrvI2c_DevFlagType flags; /* indicate the operation features */
+
+ VOID *privData;
+}T_ZDrvI2c_Device;
+
+
+/*******************************************************************************
+* Function Prototypes *
+*******************************************************************************/
+
+
+/*******************************************************************************
+ * Function: zDrvI2c_DevRead
+ * Description: I2C×ÜÏß¼òµ¥¶Á
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others: 1. ×ñÑI2C×ÜÏß ×éºÏ¶Á ±êÏßÐÒé¡£
+ 2. ×î´óÒ»´Î¶ÁÈ¡ --32-- ¸ö×Ö½ÚÊý¾Ý¡£
+ ********************************************************************************/
+SINT32 zDrvI2c_DevRead( T_ZDrvI2c_Device *i2c_dev, UINT16 regAddr, UINT8 *readBuf, UINT32 readNum );
+
+
+
+/*******************************************************************************
+ * Function: zDrvI2c_DevWrite
+ * Description: I2C×ÜÏß¼òµ¥Ð´
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others: 1. ×ñÑI2C×ÜÏß ¼òµ¥Ð´ ±êÏßÐÒé¡£
+ 2. ×î´óÒ»´ÎдÈë --30-- ¸ö×Ö½ÚÊý¾Ý¡£
+ ********************************************************************************/
+SINT32 zDrvI2c_DevWrite( T_ZDrvI2c_Device *i2c_dev, UINT16 regAddr, UINT8 *writeBuf, UINT32 writeNum );
+
+
+
+/*******************************************************************************
+ * Function: zDrvI2c_DevLock_BeforePSM
+ * Description: ÔÚ¹ØÖжϲ¢µ÷Óà PSM ½Ó¿ÚÇ°£¬»ñÈ¡ I2C É豸Ëø¡£
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others: 1. ¹ØÖжϲ¢µ÷Óà PSM ½Ó¿Úʱ£¬I2C ¿ÉÄÜÕýÔÚ±»ÆäËûÏß³ÌʹÓá£
+ * ʹÓô˽ӿڵȴýÆäËûÏß³ÌʹÓÃÍê±ÏºóÍ˳ö¡£
+ ********************************************************************************/
+SINT32 zDrvI2c_DevLock_BeforePSM( T_ZDrvI2c_BusNum busNum);
+
+
+
+/*******************************************************************************
+ * Function: zDrvI2c_DevUnlock_AfterPSM
+ * Description: ²»ÔÙʹÓà PSM ½Ó¿Úʱ£¬ÊÍ·Å I2C É豸Ëø¡£
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others: 1. ÓëzDrvI2c_DevLock_BeforePSM½á¶ÔʹÓá£
+ ********************************************************************************/
+SINT32 zDrvI2c_DevUnlock_AfterPSM( T_ZDrvI2c_BusNum busNum);
+
+
+
+/*******************************************************************************
+ * Function: zDrvI2c_DevRead
+ * Description: I2C×ÜÏß¼òµ¥¶Á£¬Ê¹ÓÃÊ¡µçģʽ
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others: 1. ×ñÑI2C×ÜÏß ×éºÏ¶Á ±êÏßÐÒé¡£
+ 2. ×î´óÒ»´Î¶ÁÈ¡ --32-- ¸ö×Ö½ÚÊý¾Ý¡£
+ 3. Ö÷ÒªÊÇÔÚ²Ù×÷ÖÐ --²»»ñÈ¡»¥³âÁ¿--£¬ Á½µÄÏ̲߳»ÄÜͬʱµ÷ÓÃ
+ ********************************************************************************/
+SINT32 zDrvI2c_DevRead_PSM( T_ZDrvI2c_Device *i2c_dev, UINT16 regAddr, UINT8 *readBuf, UINT32 readNum );
+
+
+
+
+/*******************************************************************************
+ * Function: zDrvI2c_DevWrite
+ * Description: I2C×ÜÏß¼òµ¥Ð´£¬Ê¹ÓÃÊ¡µçģʽ
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others: 1. ×ñÑI2C×ÜÏß ¼òµ¥Ð´ ±êÏßÐÒé¡£
+ 2. ×î´óÒ»´ÎдÈë --30-- ¸ö×Ö½ÚÊý¾Ý¡£
+ 3. Ö÷ÒªÊÇÔÚ²Ù×÷ÖÐ --²»»ñÈ¡»¥³âÁ¿--£¬ Á½µÄÏ̲߳»ÄÜͬʱµ÷ÓÃ
+ ********************************************************************************/
+SINT32 zDrvI2c_DevWrite_PSM( T_ZDrvI2c_Device *i2c_dev, UINT16 regAddr, UINT8 *writeBuf, UINT32 writeNum );
+
+
+
+/*******************************************************************************
+ * Function: zDrvI2c_DevRead_ByteStream
+ * Description: I2C×ÜÏß×Ö½ÚÁ÷¶Á
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others: 1. ×ñÑI2C×ÜÏß ¼òµ¥¶Á ±êÏßÐÒé¡£
+ 2. ֻд I2C Æ÷¼þµØÖ·£¬----------²»Ê¹ÓüĴæÆ÷µØÖ·-----¡£
+ 2. ×î´óÒ»´Î¶ÁÈ¡ 32 ¸ö×Ö½ÚÊý¾Ý¡£
+ ********************************************************************************/
+SINT32 zDrvI2c_DevRead_ByteStream( T_ZDrvI2c_Device *i2c_dev, UINT8 *readBuf, UINT32 readNum );
+
+
+
+
+/*******************************************************************************
+ * Function: zDrvI2c_DevWrite_ByteStream
+ * Description: I2C×ÜÏß×Ö½ÚÁ÷д
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others: 1. ×ñÑI2C×ÜÏß ¼òµ¥Ð´ ±êÏßÐÒé¡£
+ 2. ֻд I2C Æ÷¼þµØÖ·£¬----------²»Ê¹ÓüĴæÆ÷µØÖ·-----¡£
+ 2. ×î´óÒ»´ÎдÈë 30 ¸ö×Ö½ÚÊý¾Ý¡£
+ ********************************************************************************/
+SINT32 zDrvI2c_DevWrite_ByteStream( T_ZDrvI2c_Device *i2c_dev, UINT8 *writeBuf, UINT32 writeNum );
+
+
+
+
+
+#endif /* _DRVS_I2C_H */
+
+
diff --git a/cp/ps/driver/inc/misc/drvs_i2s.h b/cp/ps/driver/inc/misc/drvs_i2s.h
new file mode 100644
index 0000000..2f19362
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_i2s.h
@@ -0,0 +1,489 @@
+/**
+ * @file drvs_i2s.h
+ * @brief Public APIs of i2s drivers
+ *
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * @author Xinqiang Xu <xu.xinqiang@sanechips.com.cn>
+ * @ingroup si_cp_drv_id
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _HAL_I2S_H
+#define _HAL_I2S_H
+
+/*******************************************************************************
+ * Include header files *
+ ******************************************************************************/
+#include "drvs_general.h"
+#include "drvs_io_voice.h"
+
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Type definitions *
+ ******************************************************************************/
+/* i2s index */
+typedef enum {
+ I2S_1 = 0,
+ I2S_2 = 1,
+
+ MAX_I2S_ID
+} T_ZDrvI2S_Id;
+
+typedef enum {
+ I2S_TX = 0,
+ I2S_RX = 1
+} T_ZDrvI2S_TransDirection;
+
+typedef enum {
+ I2S_NORMAL_MODE,
+ I2S_LOOPBACK_MODE,
+
+ MAX_TEST_MODE
+} T_ZDrvI2S_TestMode;
+
+typedef enum {
+ PCM_NORMAL_MODE,
+ PCM_TEAK_MODE,
+
+ MAX_PCM_MODE
+} T_ZDrvI2S_PcmMode;
+
+typedef enum {
+ PCM_LSB_FIRST,
+ PCM_MSB_FIRST,
+
+ MAX_PCM_FIRSTBIT
+} T_ZDrvI2S_PcmFirstBitSel;
+
+typedef enum {
+ PCM_1TIME_SLOT = 0x00,
+ PCM_2TIME_SLOT = 0x01,
+ PCM_4TIME_SLOT = 0x03,
+ PCM_8TIME_SLOT = 0x07,
+ PCM_16TIME_SLOT = 0x0f,
+
+ MAX_PCM_SLOTNUM
+} T_ZDrvI2S_PcmSlotNum;
+
+/* i2s operation mode */
+typedef enum {
+ I2S_DATA_16BIT = 0x0f,
+ I2S_DATA_17BIT = 0x10,
+ I2S_DATA_18BIT = 0x11,
+ I2S_DATA_19BIT = 0x12,
+ I2S_DATA_20BIT = 0x13,
+ I2S_DATA_21BIT = 0x14,
+ I2S_DATA_22BIT = 0x15,
+ I2S_DATA_23BIT = 0x16,
+ I2S_DATA_24BIT = 0x17,
+ I2S_DATA_25BIT = 0x18,
+ I2S_DATA_26BIT = 0x19,
+ I2S_DATA_27BIT = 0x1a,
+ I2S_DATA_28BIT = 0x1b,
+ I2S_DATA_29BIT = 0x1c,
+ I2S_DATA_30BIT = 0x1d,
+ I2S_DATA_31BIT = 0x1e,
+ I2S_DATA_32BIT = 0x1f,
+
+ MAX_I2S_DATA_FMT
+} T_ZDrvI2S_DataFmt;
+
+typedef enum {
+ I2S_TS_16CYCLE = 0x0f,
+ I2S_TS_17CYCLE = 0x10,
+ I2S_TS_18CYCLE = 0x11,
+ I2S_TS_19CYCLE = 0x12,
+ I2S_TS_20CYCLE = 0x13,
+ I2S_TS_21CYCLE = 0x14,
+ I2S_TS_22CYCLE = 0x15,
+ I2S_TS_23CYCLE = 0x16,
+ I2S_TS_24CYCLE = 0x17,
+ I2S_TS_25CYCLE = 0x18,
+ I2S_TS_26CYCLE = 0x19,
+ I2S_TS_27CYCLE = 0x1a,
+ I2S_TS_28CYCLE = 0x1b,
+ I2S_TS_29CYCLE = 0x1c,
+ I2S_TS_30CYCLE = 0x1d,
+ I2S_TS_31CYCLE = 0x1e,
+ I2S_TS_32CYCLE = 0x1f,
+
+ MAX_I2S_TS_WIDTH
+} T_ZDrvI2S_TsWidth;
+
+#if 1//defined _USE_EVB2963
+/*i2s track select*/
+typedef enum {
+ DOUBLE_TRACK = 0x00,
+ LEFT_TRACK = 0x01,
+ RIGHT_TRACK = 0x02,
+
+ MAX_I2S_TRACK_FMT
+} T_ZDrvI2S_TrackFmt;
+
+/*i2s clock source in master mode*/
+typedef enum {
+ PCLK_DIVIDE = 0x00,
+ I2S_SCLK_DIVIDE = 0x01,
+ EQUAL_TO_SCLK = 0x02,
+
+ MAX_I2S_CLK_SOURCE
+} T_ZDrvI2S_ClkSource;
+
+/*i2s clock mode*/
+typedef enum {
+ TRANS_POSITIVE_NEGATIVE = 0,
+ TRANS_NEGATIVE_POSITIVE ,
+
+ MAX_EDGE_SELECT
+} T_ZDrvI2S_ClkEdgeSel;
+
+#endif
+
+typedef VOID (*T_ZDrvI2S_AUD_PLAY_CB)(VOID);
+
+/* i2s configuration */
+
+/*i2s clock mode*/
+typedef enum {
+ I2S_TIME_MODE = 0,
+ PCM_TIME_MODE ,
+
+ MAX_I2S_TIME_MODE
+} T_ZDrvI2S_ClkMode;
+
+typedef enum {
+ PCM_FSYNC_LENGTH_1CLK,
+ PCM_FSYNC_LENGTH_2CLK,
+ PCM_FSYNC_LENGTH_3CLK,
+ PCM_FSYNC_LENGTH_4CLK,
+ PCM_FSYNC_LENGTH_5CLK,
+ PCM_FSYNC_LENGTH_6CLK,
+ PCM_FSYNC_LENGTH_7CLK,
+ PCM_FSYNC_LENGTH_8CLK,
+
+ MAX_PCM_FSYNC
+} T_ZDrvI2S_PcmFsyncLen;
+
+typedef enum {
+ FIRST_DATA_ALIGN_TO_FIRST_CYCLE,
+ FIRST_DATA_ALIGN_TO_SECOND_CYCLE,
+
+ MAX_7510_DATA_ALIGN_MODE
+} T_ZDrvI2S_DataAlignMode;
+
+typedef enum {
+ TIMING_I2S_MONO_RIGHT = 0,
+ TIMING_I2S_MONO_LEFT,
+ TIMING_I2S_ST_2CHN_1LANE,
+ TIMING_I2S_ST_4CHN_2LANE,
+ TIMING_I2S_ST_6CHN_3LANE,
+ TIMING_I2S_ST_8CHN_4LANE,
+ TIMING_TDM_1CHN_1LANE_1TS,
+ TIMING_TDM_2CHN_1LANE_2TS,
+
+ MAX_TMING_SELECT
+} T_ZDrvI2S_TimingType;
+
+/**
+ * @brief describe the i2s device timing config info
+ * @param tTimingTp tTimingTp
+ * @param tTimingSel tTimingSel
+ * @param tChnNum tChnNum
+ * @param tLaneNum tLaneNum
+ * @param tTsCfg tTsCfg
+ */
+typedef struct {
+ T_ZDrvI2S_TimingType tTimingTp;
+ T_ZDrvI2S_ClkMode tTimingSel;
+ UINT8 tChnNum;
+ UINT8 tLaneNum;
+ UINT8 tTsCfg;
+
+} T_ZDrvI2S_TimingCfg;
+
+typedef enum {
+ PCM_LONG_FSYNC,
+ PCM_SHORT_FSYNC,
+ MAX_PCM_LS_FSYNC
+} T_ZDrvI2S_PcmFsync;
+
+typedef enum {
+ TDM_TEAK_EXTRA_CYCLE,
+ TDM_NO_EXTRA_CYCLE,
+ MAX_TDM_EXTRA_CYCLE
+} T_ZDrvI2S_TdmExtCycle;
+
+typedef enum {
+ DATA_ALIGN_STD_I2S,
+ DATA_ALIGN_MSB_JUSTIF,
+ DATA_ALIGN_LSB_JUSTIF,
+ DATA_ALIGN_NORMAL,
+ MAX_DATA_ALIGN_MODE
+} T_ZDrvI2S_TransMode;
+
+typedef enum {
+ REF_CLK26M,
+ REF_CLK104M,
+ REF_CLK122M88,
+
+ REF_CLK_MAX
+} T_I2s_RefClkForI2s;
+
+/**
+ * @brief describe the i2s device config info
+ * @param bMaster TRUE: master mode; FALSE: slave mode
+ * @param tDataFmt T_ZDrvI2S_DataFmt
+ * @param tTsWidth T_ZDrvI2S_TsWidth
+ * @param sample_rate sample rate of auido file
+ * @param tClkMode the clk mode of i2s
+ * @param tTansmit_edge the clk edge select
+ * @param tTrackFmt tTrackFmt
+ * @param tTestMode tTestMode
+ * @param tDataAlignMode tDataAlignMode
+ * @param tPcmMode; tPcmMode
+ * @param tPcmFirstBit tPcmFirstBit
+ * @param tPcmFsynLen tPcmFsynLen
+ * @param tPcmSlotNum tPcmSlotNum
+ * @param tTimingType tTimingType
+ * @param tPcmFsync tPcmFsync
+ * @param tTdmExtCycle only exit in the 7520
+ * @param tTransMode tTransMode
+ * @param refclk refclk
+ */
+typedef struct {
+ BOOL bMaster;
+ T_ZDrvI2S_DataFmt tDataFmt;
+ T_ZDrvI2S_TsWidth tTsWidth;
+ UINT32 sample_rate;
+ T_ZDrvI2S_ClkMode tClkMode;
+ T_ZDrvI2S_ClkEdgeSel tTansmit_edge;
+ T_ZDrvI2S_TrackFmt tTrackFmt;
+ T_ZDrvI2S_TestMode tTestMode;
+ T_ZDrvI2S_DataAlignMode tDataAlignMode;
+ T_ZDrvI2S_PcmMode tPcmMode;
+ T_ZDrvI2S_PcmFirstBitSel tPcmFirstBit;
+ T_ZDrvI2S_PcmFsyncLen tPcmFsynLen;
+ T_ZDrvI2S_PcmSlotNum tPcmSlotNum;
+
+ T_ZDrvI2S_TimingType tTimingType;
+ T_ZDrvI2S_PcmFsync tPcmFsync;
+ T_ZDrvI2S_TdmExtCycle tTdmExtCycle;
+ T_ZDrvI2S_TransMode tTransMode;
+ T_I2s_RefClkForI2s refclk;
+
+} T_ZDrvI2S_Cfg;
+
+typedef enum {
+ I2S_IDLE,
+ I2S_OPEN,
+ I2S_PLAY_INUSE,
+ I2S_RECORD_INUSE,
+ I2S_BOTH_INUSE,
+
+ MAX_I2S_STATUS
+}T_I2s_Status;
+
+/**
+ * @brief describe the codec agc Parameter
+ * @param channel audio channel
+ * @param buffersize buffer size
+ * @param p_cb the callback of audio play
+ */
+typedef struct {
+ T_ZDrvAudio_Channel channel;
+ UINT32 buffersize;
+ T_ZDrvI2S_AUD_PLAY_CB p_cb;
+} T_ZDrvI2s_Params;
+
+typedef enum {
+ TRANS_CPU_MODE,
+ TRANS_INT_MODE,
+ TRANS_DMA_MODE,
+
+ MAX_TRANS_FUNC
+}T_ZDrvI2s_TransMode;
+
+/*******************************************************************************
+ * Global variable declarations *
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Global function declarations *
+ ******************************************************************************/
+
+/**
+* @brief open i2s device.
+*
+* @param tId i2s selete struct
+* @param i2sTransMode T_ZDrvI2s_TransMode
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_Open(T_ZDrvI2S_Id tId, T_ZDrvI2s_TransMode i2sTransMode);
+
+/**
+* @brief reset i2s device.
+*
+* @param tId i2s select i2s0 or i2s1
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_Reset(T_ZDrvI2S_Id tId);
+
+/**
+* @brief close i2s device.
+*
+* @param tId i2s selete struct
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_Close(T_ZDrvI2S_Id tId);
+
+/**
+* @brief i2s write stop ,use to stop playing or recording.
+*
+* @param tId i2s index select i2s0 or i2s1
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_Write_Stop(T_ZDrvI2S_Id tId);
+
+/**
+* @brief i2s read stop ,use to stop playing or recording.
+*
+* @param tId i2s select i2s0 or i2s1
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_Read_Stop(T_ZDrvI2S_Id tId);
+
+/**
+* @brief This function is used to read data by i2s.
+*
+* @param tId i2s select i2s0 or i2s1
+* @param pBuf one buffer is how many bytes
+* @param uiLen buffer length
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_Read(T_ZDrvI2S_Id tId, UINT8 **pBuf, UINT32 *uiLen);
+
+/**
+* @brief i2s trans data to fifo from ram while playing.
+*
+* @param tId i2s selete struct
+* @param pBuf one buffer is how many bytes
+* @param uiLen buffer length
+*
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_Write(T_ZDrvI2S_Id tId, const UINT8 *pBuf, UINT32 uiLen);
+
+/**
+* @brief i2s write start .
+*
+* @param tId i2s selete struct
+* @param params pointer to struct T_ZDrvI2s_Params
+* @param ptCfg pointer to struct T_ZDrvI2S_Cfg
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_Write_Start(T_ZDrvI2S_Id tId, T_ZDrvI2s_Params *params, T_ZDrvI2S_Cfg *ptCfg);
+
+/**
+* @brief i2s read start.
+*
+* @param tId i2s selete struct
+* @param params pointer to T_ZDrvI2s_Params
+* @param ptCfg pointer to T_ZDrvI2S_Cfg
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_Read_Start(T_ZDrvI2S_Id tId, T_ZDrvI2s_Params *params, T_ZDrvI2S_Cfg *ptCfg);
+
+/**
+* @brief start to trans data,use in playing.
+*
+* @param tId i2s selete struct
+* @param params T_ZDrvI2s_Params
+* @param ptCfg config param
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_Vousb_Start(T_ZDrvI2S_Id tId, T_ZDrvI2s_Params *params, T_ZDrvI2S_Cfg *ptCfg);
+
+/**
+* @brief i2s get buffer ,get buffer to write playing data.
+*
+* @param tId i2s select i2s0 or i2s1
+* @param pBuf playing data buffer
+* @param uiLen buffer length
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_GetBuf(T_ZDrvI2S_Id tId, UINT8 **pBuf, UINT32 *uiLen);
+
+/**
+* @brief i2s free buffer ,get buffer to write playing data.
+*
+* @param tId i2s select i2s0 or i2s1
+* @param pBuf data buffer
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_GetRemained(T_ZDrvI2S_Id tId, UINT32 *len);
+
+/**
+* @brief i2s free buffer ,get buffer to write playing data.
+*
+* @param tId i2s select i2s0 or i2s1
+* @param pBuf data buffer
+* @return 0-DRV_SUCCESS, other-error
+*/
+SINT32 zDrvI2S_FreeBuf(T_ZDrvI2S_Id tId, UINT8 *pBuf);
+
+/**
+* @brief pause while playing.
+*
+* @param tId i2s select i2s0 or i2s1
+* @return 0-DRV_SUCCESS, other-error
+*/
+VOID zDrvI2S_Pause(T_ZDrvI2S_Id tId);
+
+/**
+* @brief resume playing if pause.
+*
+* @param tId i2s select i2s0 or i2s1
+* @return 0-DRV_SUCCESS, other-error
+*/
+VOID zDrvI2S_Resume(T_ZDrvI2S_Id tId);
+
+/**
+* @brief Release the rx semaphore before stop.
+*
+* @param tId i2s select i2s0 or i2s1
+* @return 0-DRV_SUCCESS, other-error
+*/
+VOID zDrvI2s_RxRlsSemaBeforeStop(T_ZDrvI2S_Id tId);
+
+/**
+* @brief Release the tx semaphore before stop.
+*
+* @param tId i2s select i2s0 or i2s1
+* @return 0-DRV_SUCCESS, other-error
+*/
+VOID zDrvI2s_TxRlsSemaBeforeStop(T_ZDrvI2S_Id tId);
+
+/**
+* @brief get i2s status.
+*
+* @param tId i2s select i2s0 or i2s1
+* @return 0-DRV_SUCCESS, other-error
+*/
+T_I2s_Status zDrvI2s_GetI2sStatus(T_ZDrvI2S_Id tId);
+
+#endif /* #ifndef _HAL_I2S_H */
+
diff --git a/cp/ps/driver/inc/misc/drvs_icp.h b/cp/ps/driver/inc/misc/drvs_icp.h
new file mode 100644
index 0000000..e39edba
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_icp.h
@@ -0,0 +1,232 @@
+/*******************************************************************************
+ * Copyright by ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: 0.1
+ * Author: shideyou
+ * Date: 2013-7-8
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_ICP_H
+#define _DRVS_ICP_H
+
+#include "ram_config.h"
+#include "drvs_rpmsg.h"
+/*******************************************************************************
+* Macro *
+*******************************************************************************/
+
+/*******************************************************************************
+* Types *
+*******************************************************************************/
+#if 0
+typedef enum _T_HalIcp_MsgActor
+{
+ ICP_MSG_ACTOR_M0,
+ ICP_MSG_ACTOR_PHY,
+ ICP_MSG_ACTOR_ARM = ICP_MSG_ACTOR_PHY,
+ MAX_ICP_MSG_ACTOR
+} T_HalIcp_MsgActor;
+
+typedef enum _T_HalIcp_ModuleId
+{
+ ICP_ARM0_MODULE_ID_BASE, // 0
+ ICP_ARM0_MODULE_ID_DRV = ICP_ARM0_MODULE_ID_BASE,
+ ICP_ARM0_MODULE_ID_PSM, // 1
+ ICP_ARM0_MODULE_ID_OS, // 2
+ ICP_ARM0_MODULE_ID_LTEPS, // 3
+ ICP_ARM0_MODULE_ID_TDPS, // 4
+ ICP_ARM0_MODULE_ID_WPS, // 5
+ ICP_ARM0_MODULE_ID_LTEPSM, // 6
+ ICP_ARM0_MODULE_ID_TDPSM, // 7
+ ICP_ARM0_MODULE_ID_WPSM, // 8
+ MAX_ICP_ARM0_MODULE_ID = ICP_ARM0_MODULE_ID_WPSM,
+
+ ICP_ARM1_MODULE_ID_BASE, // 9
+ ICP_ARM1_MODULE_ID_DRV = ICP_ARM1_MODULE_ID_BASE,
+ ICP_ARM1_MODULE_ID_PSM, // 10
+ ICP_ARM1_MODULE_ID_OS, // 11
+ ICP_ARM1_MODULE_ID_LTEPHY, // 12
+ ICP_ARM1_MODULE_ID_TDPHY, // 13
+ ICP_ARM1_MODULE_ID_WPHY, // 14
+ ICP_ARM1_MODULE_ID_LTEPSM, // 15
+ ICP_ARM1_MODULE_ID_TDPSM, // 16
+ ICP_ARM1_MODULE_ID_WPSM, // 17
+ MAX_ICP_ARM1_MODULE_ID = ICP_ARM1_MODULE_ID_WPSM,
+
+ ICP_M0_MODULE_ID_BASE, // 18
+ ICP_M0_MODULE_ID_DRV = ICP_M0_MODULE_ID_BASE,
+ ICP_M0_MODULE_ID_PSM, // 19
+ ICP_M0_MODULE_ID_OS, // 20
+ MAX_ICP_M0_MODULE_ID = ICP_M0_MODULE_ID_OS,
+
+ MAX_ICP_MODULE_ID // 21
+} T_HalIcp_ModuleId;
+
+typedef enum _T_HalIcp_CallbackType
+{
+ ICP_ISR_CALLBACK,
+ ICP_HISR_CALLBACK,
+
+ MAX_ICP_CALLBACK_TYPE
+}T_HalIcp_CallbackType;
+#endif
+typedef struct _T_HalIcp_Dword
+{
+ UINT32 low_word;
+ UINT32 high_word;
+} T_HalIcp_Dword;
+
+typedef struct _T_HalIcp_Msg
+{
+ UINT32 SrcModId;
+ UINT32 desModId;
+ T_HalIcp_Dword IntInfo;
+ UINT32 sfn;
+ VOID *pBuf;
+ UINT32 len;
+} T_HalIcp_Msg;
+#if 0
+typedef VOID (*T_HalIcp_CallbackFunction)(const T_HalIcp_Msg *pMsg);
+
+
+/*******************************************************************************
+* Function Prototypes *
+*******************************************************************************/
+/*******************************************************************************
+* Function: zDrvIcp_RegCallback
+* Description: This function is used for registing callback functions;
+* Parameters:
+* Input:
+* me: which module regists callback function.
+* from: which is this function for.
+* callback: the callback function.
+* callbackType: where is this function, isr or hisr.
+*
+* Output:None
+*
+* Returns:
+* DRV_SUCCESS
+* DRV_ERROR
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvIcp_RegCallback(UINT32 me,
+ UINT32 from,
+ T_HalIcp_CallbackFunction callback,
+ T_HalIcp_CallbackType callbackType);
+
+/*******************************************************************************
+* Function: zDrvIcp_SendMsg
+* Description: This function is used for sending ICP MSG;
+* Parameters:
+* Input:
+* pMsg: the msg which will be sent
+* Output:None
+*
+* Returns:
+* DRV_SUCCESS: successfully send msg.
+* DRV_ERROR: fail to send msg.
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvIcp_SendMsg(const T_HalIcp_Msg *pMsg);
+
+/*******************************************************************************
+* Function: zDrvIcp_SendMsg_Psm
+* Description: This function is used for sending ICP MSG during interrupt disabled;
+* Parameters:
+* Input:
+* pMsg: the msg which will be sent
+* Output:None
+*
+* Returns:
+* DRV_SUCCESS: successfully send msg.
+* DRV_ERROR: fail to send msg.
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvIcp_SendMsg_Psm(const T_HalIcp_Msg *pMsg);
+
+
+/*******************************************************************************
+* Function: zDrvIcp_Mask
+* Description: This function is used for mask ICP interrupt from another core;
+* Parameters:
+* Input:
+* actor: which core.
+* bit_map: which interrupts will be masked.
+* Output:None
+*
+* Returns:
+* None
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvIcp_Mask(T_HalIcp_MsgActor actor, T_HalIcp_Dword bit_map);
+
+ /*******************************************************************************
+ * Function: zDrvIcp_Unmask
+ * Description: This function is used for unmask ICP interrupt from another core;
+ * Parameters:
+ * Input:
+ * actor: which core.
+ * bit_map: which interrupts will be unmasked.
+ * Output:None
+ *
+ * Returns:
+ * None
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ SINT32 zDrvIcp_Unmask(T_HalIcp_MsgActor actor, T_HalIcp_Dword bit_map);
+
+ /*******************************************************************************
+* Function: zDrvIcp_GetState
+* Description: This function is used for getting state;
+* Parameters:
+* Input:
+* actor: which core.
+* Output:None
+* pState: the current state.
+*
+* Returns:
+* DRV_ERR_INVALID_PARAM
+* DRV_SUCCESS
+*
+* Others:
+********************************************************************************/
+ SINT32 zDrvIcp_GetState(T_HalIcp_MsgActor actor, T_HalIcp_Dword *pState);
+
+ /*******************************************************************************
+* Function: zDrvIcp_ClearState
+* Description: This function is used for clear state;
+* Parameters:
+* Input:
+* actor: which core.
+* bit_map: which bits' state will be clear, 0-not clear, 1-clear.
+* Output:None
+*
+* Returns:
+* None
+*
+*
+* Others:
+********************************************************************************/
+ SINT32 zDrvIcp_ClearState(T_HalIcp_MsgActor actor, T_HalIcp_Dword bit_map);
+#endif
+#endif /* _DRVS_ICP_H */
+
diff --git a/cp/ps/driver/inc/misc/drvs_int.h b/cp/ps/driver/inc/misc/drvs_int.h
new file mode 100644
index 0000000..9b378f5
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_int.h
@@ -0,0 +1,416 @@
+/**
+* @file drvs_int.h
+* @brief Public APIs of int drivers
+*
+* Copyright (C) 2017 Sanechips Technology Co., Ltd.
+* @author Dongdong Zhang <Zhang.Dongdong@sanechips.com.cn>
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+*/
+#ifndef _DRVS_INT_H
+#define _DRVS_INT_H
+
+/*******************************************************************************
+ * Include header files *
+ ******************************************************************************/
+#include "drvs_general.h"
+
+#ifdef _OS_LINUX
+#include <linux/irq.h>
+#endif
+
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+#define INT_PRI_NUM 15 /* 0-highest, 15-lowest, but 15 is always be masked in gic*/
+ /*so in fact, only 0-14 can generate interrupt*/
+
+#define MAX_NEST_NUM 32 /* maximum number of nested interrupt */
+
+
+#define INT_TABLE_END 0xFFFF
+#define INT_VECTOR_DEFAULT 0xFFFF
+#define INT_PRIORITY_DEFAULT 14
+#define INT_INVALID_INTLINE 0xFFFFFFFF
+
+#if 1//modify by xxx ndef _OS_LINUX
+
+/*
+ * 0-15: SGI (software generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+: SPI (shared peripheral interrupts)
+ */
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define RESERVED_INT 0xffff
+
+/*
+ * software generated interrupts
+ */
+#define SGI0_INT (0)
+#define SGI1_INT (1)
+#define SGI2_INT (2)
+#define SGI3_INT (3)
+#define SGI4_INT (4)
+#define SGI5_INT (5)
+#define SGI6_INT (6)
+#define SGI7_INT (7)
+#define SGI8_INT (8)
+#define SGI9_INT (9)
+#define SGI10_INT (10)
+#define SGI11_INT (11)
+#define SGI12_INT (12)
+#define SGI13_INT (13)
+#define SGI14_INT (14)
+#define SGI15_INT (15)
+
+/*
+ * private peripheral interrupts
+ */
+#define GLOBAL_TIMER_INT (27)
+#define LEGACY_FIQ_INT (28)
+#define PRIVATE_TIMER_INT (29)
+#define PRIVATE_WDT_INT (30)
+#define LEGACY_IRQ_INT (31)
+
+/*
+ * shared peripheral interrupts
+ */
+#define UART0_INT (GIC_SPI_START+0)
+#define UART1_INT (GIC_SPI_START+1)
+#define UART2_INT (GIC_SPI_START+2)
+#define SSP0_INT (GIC_SPI_START+3)
+#define PS_SYS_COUNTER (GIC_SPI_START+4)
+#define RTC_ALARM_INT (GIC_SPI_START+5)
+#define RTC_TIMER_INT (GIC_SPI_START+6)
+#define I2S0_INT (GIC_SPI_START+7)
+#define I2S1_INT (GIC_SPI_START+8)
+#define USIM1_INT (GIC_SPI_START+9)
+#define I2C1_INT (GIC_SPI_START+10)
+#define PMIC_I2C_INT (GIC_SPI_START+11)
+#define KEYPAD_INT (GIC_SPI_START+12)
+#define SD1_INT (GIC_SPI_START+13)
+#define WLAN_PRIORITY_POS_INT (GIC_SPI_START+14)
+#define WLAN_PRIORITY_NEG_INT (GIC_SPI_START+15)
+#define SD0_INT (GIC_SPI_START+16)
+#define ICP_PHY_INT (GIC_SPI_START+17)
+#define ICP_M0_INT (GIC_SPI_START+18)
+#define TIMER0_INT (GIC_SPI_START+19) /*ps timer0*/
+#define TIMER1_INT (GIC_SPI_START+20) /*ps timer1*/
+#define PS_RM_TIMER_INT (GIC_SPI_START+21) /*ps rm timer*/
+#define GSMIF_RFSSCR_INT (GIC_SPI_START+22)
+#define GSMIF_RFSSCT_INT (GIC_SPI_START+23)
+#define GSMIF_GP0_INT (GIC_SPI_START+24)
+#define GSMIF_T_INT (GIC_SPI_START+25)
+#define GSMIF_TL_INT (GIC_SPI_START+26)
+#define GPRS_INT0 (GIC_SPI_START+27)
+#define GPRS_INT1 (GIC_SPI_START+28)
+#define DSP_INT0 (GIC_SPI_START+29)
+#define DSP_INT1 (GIC_SPI_START+30)
+#define DSP_INT2 (GIC_SPI_START+31)
+#define DSP_INT3 (GIC_SPI_START+32)
+#define DSP_INT4 (GIC_SPI_START+33)
+#define DSP_INT6 (GIC_SPI_START+34)
+#define DSP_INT7 (GIC_SPI_START+35)
+#define GSM_LPM_INT0 (GIC_SPI_START+36)
+#define RCOUT1_INT (GIC_SPI_START+37)
+#define DMAC0_INT (GIC_SPI_START+38) /*ps dma int1 to ps*/
+#define DMAC1_INT (GIC_SPI_START+39) /*phy dma int1 to ps*/
+#define NAND_INT (GIC_SPI_START+40)
+#define USB_INT (GIC_SPI_START+41)
+#define USB_POWERDWN_UP_INT (GIC_SPI_START+42)
+#define USB_POWERDWN_DOWN_INT (GIC_SPI_START+43)
+#define HSIC_INT (GIC_SPI_START+44)
+#define HSIC_POWERDWN_UP_INT (GIC_SPI_START+45)
+#define HSIC_POWERDWN_DOWN_INT (GIC_SPI_START+46)
+
+#define GSM_USIM_INT (GIC_SPI_START+48)
+
+#define EX8IN1_INT (GIC_SPI_START+51) /*only used by int driver*/
+#define EX0_INT (GIC_SPI_START+52)
+#define EX1_INT (GIC_SPI_START+53)
+#define EX2_INT (GIC_SPI_START+54)
+#define EX3_INT (GIC_SPI_START+55)
+#define EX4_INT (GIC_SPI_START+56)
+#define EX5_INT (GIC_SPI_START+57)
+#define EX6_INT (GIC_SPI_START+58)
+#define EX7_INT (GIC_SPI_START+59)
+#define SSC0_CONFLICT_INT (GIC_SPI_START+60)
+#define TD_LPM4_INT (GIC_SPI_START+61)
+#define TD_FRM_INT (GIC_SPI_START+62)
+#define TD_FRM32K_INT (GIC_SPI_START+63)
+#define LTE_LPM2_INT (GIC_SPI_START+64)
+#define LTE_LPM4_INT (GIC_SPI_START+65)
+#define LTE_LPM5_INT (GIC_SPI_START+66)
+#define GSM_LPM_INT1 (GIC_SPI_START+67)
+#define LTE_TPU_INT (GIC_SPI_START+68)
+#define WD_LPM4_INT (GIC_SPI_START+69)
+#define WD_FRM_INT (GIC_SPI_START+70)
+#define EDCP_INT (GIC_SPI_START+71)
+#define SD1_DATA1_INT (GIC_SPI_START+72)
+
+#if defined (_CHIP_ZX297520V3)
+#define UART0_RXD_INT (GIC_SPI_START+73)
+#elif defined (_CHIP_ZX297520V2)
+#define UART0_CTS_INT (GIC_SPI_START+73)
+#endif
+
+#define SPIFC0_INT (GIC_SPI_START+74)
+#define TIMER2_INT (GIC_SPI_START+75) /*ps timer2*/
+#define PS_WDT_INT (GIC_SPI_START+76)
+#define ICP_AP_INT (GIC_SPI_START+77)
+#define SSP1_INT (GIC_SPI_START+78)
+#define SD0_DATA1_INT (GIC_SPI_START+79)
+#define TDM_INT (GIC_SPI_START+80)
+#define PHY_TIMER0_INT (GIC_SPI_START+81)
+#define PHY_TIMER1_INT (GIC_SPI_START+82)
+#define TD_MODEM_INT0 (GIC_SPI_START+83)
+#define TD_MODEM_INT1 (GIC_SPI_START+84)
+#define TD_MODEM_INT2 (GIC_SPI_START+85)
+#define LTE_MODEM_INT0 (GIC_SPI_START+86)
+#define LTE_MODEM_INT1 (GIC_SPI_START+87)
+#define LTE_MODEM_INT2 (GIC_SPI_START+88)
+#define WD_MODEM_INT0 (GIC_SPI_START+89)
+#define WD_MODEM_INT1 (GIC_SPI_START+90)
+#define WD_MODEM_INT2 (GIC_SPI_START+91)
+#define TD_LPM_ZSP_EXT_INT (GIC_SPI_START+92)
+#define LTE_LPM1_INT (GIC_SPI_START+93)
+#define WD_LPM3_INT (GIC_SPI_START+94)
+#define EDCP_PHY_INT (GIC_SPI_START+95)
+
+#define GIC_INT_NUM (EDCP_PHY_INT+1)
+
+/*virtual external 8in1 interrupts*/
+#define EX8_INT (GIC_SPI_START+96)
+#define EX9_INT (GIC_SPI_START+97)
+#define EX10_INT (GIC_SPI_START+98)
+#define EX11_INT (GIC_SPI_START+99)
+#define EX12_INT (GIC_SPI_START+100)
+#define EX13_INT (GIC_SPI_START+101)
+#define EX14_INT (GIC_SPI_START+102)
+#define EX15_INT (GIC_SPI_START+103)
+
+#define EX8IN1_INT_NUM (8)
+
+#define INT_LINES_NUM (EX15_INT+1)
+
+#if 0 /*7520V2 reserved*/
+/*
+ *virtual gpio interrupts
+ *interrupt number should be defined by user
+ *example:
+ * #define GPIO23_INT (GPIO_INT0_START+23)
+ * #define GPIO130_INT (GPIO_INT1_START+3) or (GPIO_INT0_START+130)
+ */
+
+/*
+ *gpio0 --- GPIO_INT0_START
+ *gpio127 --- GPIO_INT0_END
+ */
+#define GPIO_INT0_START (EX15_INT+1)
+#define GPIO_INT0_END (GPIO_INT0_START+127)
+
+/*
+ *gpio128 --- GPIO_INT1_START
+ *gpio255 --- GPIO_INT1_END
+ */
+#define GPIO_INT1_START (GPIO_INT0_END+1)
+#define GPIO_INT1_END (GPIO_INT1_START+127)
+
+
+#define INT_LINES_NUM (GPIO_INT1_END + 1) /*ÖжϸöÊý*/
+#endif
+
+#endif
+
+/*******************************************************************************
+* Type definitions *
+******************************************************************************/
+typedef struct _T_zDrvIntTable
+{
+ UINT32 uIntLine; /*the intline of the dev*/
+ UINT32 uIntPri; /*hardware priority*/
+ UINT32 vector; /*OSE vector,should be convert to type OSVECTOR */
+ UINT32 level; /*CPU trigger level*/
+}
+T_zDrvIntTable;
+
+#ifdef _OS_TOS
+typedef enum _T_zDrvIntLineLevel
+{
+ INT_HIGHLEVEL = 0x00, /* 00: high level */
+ INT_LOWLEVEL = 0x01, /* 01: low level */
+ INT_POSEDGE = 0x02, /* 10: raise edge */
+ INT_NEGEDGE = 0x03, /* 11: fall edge */
+ INT_DEFAULT_LEVEL,
+}
+T_zDrvIntLineLevel;
+#endif
+
+#ifdef _OS_LINUX
+typedef enum _T_zDrvIntLineLevel
+{
+ INT_HIGHLEVEL = IRQ_TYPE_LEVEL_HIGH, /* 0x4: high level */
+ INT_LOWLEVEL = IRQ_TYPE_LEVEL_LOW, /* 0x8: low level */
+ INT_POSEDGE = IRQ_TYPE_EDGE_RISING, /* 0x1: raise edge */
+ INT_NEGEDGE = IRQ_TYPE_EDGE_FALLING, /* 0x2: fall edge */
+ INT_DUALEDGE = IRQ_TYPE_EDGE_BOTH, /* 0x3: fall and raise edge, it can only be applyed to GPIO int */
+ INT_DEFAULT_LEVEL = 0xf,
+}
+T_zDrvIntLineLevel;
+#endif
+
+/*******************************************************************************
+ * Global function declarations *
+ ******************************************************************************/
+
+/**
+ *@brief This function is used to install isr into tos
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *@param pEntry the point to isr entry
+ *@param pName isr name
+ *@param level int line trigger level
+ *
+ *@note the level is source trigger level. if you don't know the int trigger level, you can set the level:INT_DEFAULT_LEVEL.
+ *
+ *@return id of interrupt handler process if successed, errcode otherwise.
+ */
+SINT32 zDrvInt_InstallIsr(UINT32 line, VOID *pEntry, const CHAR * pName,
+ T_zDrvIntLineLevel level);
+
+/**
+ *@brief This function is used to uninstall isr
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *
+ *@return 0 if successed, errcode otherwise.
+ */
+SINT32 zDrvInt_UninstallIsr(UINT32 line);
+
+/**
+ *@brief This function is used to mask irq
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *
+ *@return 0 if successed, errcode otherwise.
+ */
+VOID zDrvInt_MaskIrq(UINT32 line);
+
+/**
+ *@brief This function is used to unmask irq
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *
+ *@return 0 if successed, errcode otherwise.
+ */
+VOID zDrvInt_UnmaskIrq(UINT32 line);
+
+/**
+ *@brief This function is used to set int trigger level
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *@param level int line trigger level
+ *
+ *@return 0 if successed, errcode otherwise.
+ */
+SINT32 zDrvInt_SetLineLevel(UINT32 line, T_zDrvIntLineLevel level);
+
+/**
+ *@brief This function is used to clear int status
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *
+ *@return 0 if successed, errcode otherwise.
+ */
+SINT32 zDrvInt_ClearInt(UINT32 line);
+
+/**
+ *@brief This function is used to set int priority
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *@param pri priority number
+ *
+ *@return 0 if successed, errcode otherwise.
+ */
+VOID zDrvInt_SetLinePri(UINT32 line, UINT32 pri);
+
+#ifdef _OS_LINUX
+/**
+ *@brief This function is used to install isr into linux
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *@param pEntry the point to isr entry
+ *@param pName isr name
+ *@param level int line trigger level
+ *
+ *@note the level is source trigger level. if you don't know the int trigger level, you can set the level:INT_DEFAULT_LEVEL.
+ *
+ *@return id of interrupt handler process if successed, errcode otherwise.
+ */
+SINT32 zDrvInt_InstallFastIsr( UINT32 uiLine, VOID *pEntry, const CHAR * pName,
+ T_zDrvIntLineLevel level);
+
+/**
+ *@brief This function is used to install nested isr for interrupt line uiLine.
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *@param pEntry the point to isr entry
+ *@param pName isr name
+ *
+ *@return id of interrupt handler process if successed, errcode otherwise.
+ */
+SINT32 zDrvInt_InstallNestedIsr( UINT32 uiLine, VOID *pEntry, const CHAR * pName);
+
+#endif
+
+#ifdef _OS_TOS
+/**
+ *@brief This function is used to install isr into tos
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *@param pEntry the point to isr entry
+ *@param pName isr name
+ *@param level int line trigger level
+ *
+ *@note the level is source trigger level. if you don't know the int trigger level, you can set the level:INT_DEFAULT_LEVEL.
+ *
+ *@return id of interrupt handler process if successed, errcode otherwise.
+ */
+SINT32 zDrvInt_InstallIsrDsr(UINT32 line, VOID *pIsrEntry,
+ VOID *pDsrEntry, T_zDrvIntLineLevel level);
+
+/**
+ *@brief This function is used to distinguish whether this interrupt need to delay umask or not
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *
+ *@note invoked by os.
+ *
+ *@return 0 if need to delay umask; 1 otherwise.
+ */
+SINT32 zDrvInt_DelayUnmask(UINT32 intLine);
+
+/**
+ *@brief This function is used to initiate interrupt controller, can only be used when system bringing up
+ *
+ *@param none.
+ *
+ *@return none.
+ */
+VOID zDrvInt_Initiate(VOID);
+
+/**
+ *@brief This function is used to delay unmask an interrupt when isr is completed.
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *
+ *@note it must be used before installing irq, and you should unmask this int manually after isr is completed.
+ *
+ *@return none.
+ */
+VOID zDrvInt_DelayUnmaskAdd(UINT32 intLine);
+
+/**
+ *@brief This function is used to remove the delay unmask function for an interrupt.
+ *@param line interrupt line(0--INT_LINES_NUM)
+ *
+ *@return none.
+ */
+VOID zDrvInt_DelayUnmaskRemove(UINT32 intLine);
+
+#endif
+
+#endif /* DRVS_INT_H */
diff --git a/cp/ps/driver/inc/misc/drvs_kpdbacklight.h b/cp/ps/driver/inc/misc/drvs_kpdbacklight.h
new file mode 100644
index 0000000..d0285b0
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_kpdbacklight.h
@@ -0,0 +1,79 @@
+/*********************************************************************
+ Copyright 2007 by ZTE Corporation.
+ *
+ * FileName:: drvs_backlight.h
+ * File Mark:
+* Description: This file contains the hardware interface for lcd blg driver
+* Others:
+* Version: v0.5
+* Author: zhangyingjun
+* Date: 2009-06-25
+
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+* History 2:
+**********************************************************************/
+
+#ifndef _DRVS_KPDBLG_H
+#define _DRVS_KPDBLG_H
+
+
+/**************************************************************************
+* Function: KpdBlgEvb_Init
+* Description: initiate the battery device
+* Parameters:
+* Input:
+* None
+* Outpu: None
+* Returns:
+* DRV_SUCCESS
+* Others: None
+**************************************************************************/
+SINT32 KpdBlgEvb_Init(void);
+/**************************************************************************
+* Function: halBlg_LEDEnable
+* Description: open the LED
+* Parameters:
+* Input:
+* chan_1 LED channel
+* bl: TRUE or FALSE value,TRUE open the blg,FALSE close theblg
+* Outpu: None
+* Returns:
+* DRV_SUCCESS
+* Others: None
+**************************************************************************/
+SINT32 BlgEvb_LEDEnable(T_ZDrvBlg_LEDCHAN chan_1,BOOL bl) ;
+/**************************************************************************
+* Function: BlgEvb_LEDOn
+* Description: set the LED light frequence
+* Parameters:
+* Input:
+* channel LED channel
+* Freq the value of LED light frequence
+*
+* Outpu: None
+* Returns:
+* DRV_SUCCESS
+* Others: None
+**************************************************************************/
+SINT32 BlgEvb_LEDOn(T_ZDrvBlg_LEDCHAN channel,UINT32 period ,UINT32 Freq);
+/**************************************************************************
+* Function: BlgEVB_LEDOff
+* Description: set the LED light frequence
+* Parameters:
+* Input:
+* channel LED channel
+* Freq the value of LED light frequence
+*
+* Outpu: None
+* Returns:
+* DRV_SUCCESS
+* Others: None
+**************************************************************************/
+
+SINT32 BlgEVB_LEDOff(T_ZDrvBlg_LEDCHAN channel );
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_l2cache.h b/cp/ps/driver/inc/misc/drvs_l2cache.h
new file mode 100644
index 0000000..7cfa8b2
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_l2cache.h
@@ -0,0 +1,195 @@
+/*******************************************************************************
+ * Copyright (C) 2013, ZTE Corporation.
+ *
+ * File Name: drvs_l2cache.h
+ * File Mark:
+ * Description: This file contains the interface to operate L2 cache
+ * controller(L2C310) on zx297510 platform .
+ * Others:
+ * Version: V1.0
+ * Author: xuzhiguo
+ * Date: 2013-11-11
+ * History 1:
+ *
+ *********************************************************************************/
+#ifndef _DRVS_L2CACHE_H
+#define _DRVS_L2CACHE_H
+
+
+/*********************************************************************************
+* Include files
+**********************************************************************************/
+
+/*********************************************************************************
+* Macros
+**********************************************************************************/
+
+/*********************************************************************************
+* Type
+**********************************************************************************/
+
+/*********************************************************************************
+ * Global Variable *
+ *********************************************************************************/
+
+
+/*********************************************************************************
+* Global Function Prototypes
+**********************************************************************************/
+
+/*******************************************************************************
+* Function: zDrvL2x0_Sync
+* Description: Drain the STB. Operation complete when all buffers, LRB, LFB, STB,
+* and EB, are empty,
+* Parameters:
+* Input:
+* None
+* Outpu:
+* None
+* Returns:
+* None
+* Others: this fucntion can not be used when l2 cache is not initialized.
+* if you use it, nothing would be done.
+*******************************************************************************/
+void zDrvL2x0_Sync(void);
+
+/*******************************************************************************
+* Function: zDrvL2x0_Flush_All
+* Description: clean and invalidate entire L2 cache by way
+* Parameters:
+* Input:
+* None
+* Outpu:
+* None
+* Returns:
+* None
+* Others: this fucntion can not be used when l2 cache is not initialized.
+* if you use it, nothing would be done.
+*******************************************************************************/
+void zDrvL2x0_Flush_All(void);
+
+/*******************************************************************************
+* Function: zDrvL2x0_Clean_All
+* Description: clean entire L2 cache by way
+* Parameters:
+* Input:
+* None
+* Outpu:
+* None
+* Returns:
+* None
+* Others: this fucntion can not be used when l2 cache is not initialized.
+* if you use it, nothing would be done.
+*******************************************************************************/
+void zDrvL2x0_Clean_All(void);
+
+/*******************************************************************************
+* Function: zDrvL2x0_Inv_All
+* Description: invalidate entire L2 cache by way
+* Parameters:
+* Input:
+* None
+* Outpu:
+* None
+* Returns:
+* None
+* Others: this fucntion can not be used when l2 cache is not initialized.
+* if you use it, nothing would be done.
+*******************************************************************************/
+void zDrvL2x0_Inv_All(void);
+
+/*******************************************************************************
+* Function: zDrvL2x0_Flush_Range
+* Description: clean and invalidate L2 cache by line
+* Parameters:
+* Input:
+* base: base physical address of space needs to be flushed
+* size: size of space needs to be flushed
+* Outpu:
+* None
+* Returns:
+* None
+* Others: this fucntion can not be used when l2 cache is not initialized.
+* if you use it, nothing would be done.
+*******************************************************************************/
+void zDrvL2x0_Flush_Range(unsigned long base, unsigned long size);
+
+/*******************************************************************************
+* Function: zDrvL2x0_Clean_Range
+* Description: clean L2 cache by line
+* Parameters:
+* Input:
+* base: base physical address of space needs to be cleaned
+* size: size of space needs to be cleaned
+* Outpu:
+* None
+* Returns:
+* None
+* Others: this fucntion can not be used when l2 cache is not initialized.
+* if you use it, nothing would be done.
+*******************************************************************************/
+void zDrvL2x0_Clean_Range(unsigned long base, unsigned long size);
+
+/*******************************************************************************
+* Function: zDrvL2x0_Inv_Range
+* Description: invalidate L2 cache by line
+* Parameters:
+* Input:
+* base: base physical address of space needs to be invalidated
+* size: size of space needs to be invalidated
+* Outpu:
+* None
+* Returns:
+* None
+* Others: this fucntion can not be used when l2 cache is not initialized.
+* if you use it, nothing would be done.
+*******************************************************************************/
+void zDrvL2x0_Inv_Range(unsigned long base, unsigned long size);
+
+/*******************************************************************************
+* Function: zDrvL2x0_Enable
+* Description: enable l2 cache simply
+* Parameters:
+* Input:
+* None
+* Outpu:
+* None
+* Returns:
+* None
+* Others: this fucntion can not be used when l2 cache is not initialized.
+* if you use it, nothing would be done.
+*******************************************************************************/
+void zDrvL2x0_Enable(void);
+
+/*******************************************************************************
+* Function: zDrvL2x0_Disable
+* Description: disable l2 cache simply
+* Parameters:
+* Input:
+* None
+* Outpu:
+* None
+* Returns:
+* None
+* Others: this fucntion can not be used when l2 cache is not initialized.
+* if you use it, nothing would be done.
+* this function can not be used in complex case of operating L1 cache,
+* L2 cache and mmu.
+*******************************************************************************/
+void zDrvL2x0_Disable(void);
+
+/*******************************************************************************
+* Function: zDrvL2x0_Initiate
+* Description: Initiate l2 cache controller
+* Parameters:
+* Input:
+* None
+* Outpu:
+* None
+* Returns:
+* None
+* Others: None
+*******************************************************************************/
+void zDrvL2x0_Initiate(void);
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_led.h b/cp/ps/driver/inc/misc/drvs_led.h
new file mode 100644
index 0000000..0134203
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_led.h
@@ -0,0 +1,153 @@
+/*******************************************************************************
+ * Copyright (C) 2010, ZTE Corporation.
+ *
+ * File Name: drvs_led.h
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: V1.0
+ * Author: yuxiang
+ * Date: 2014-07-07
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_LED_H
+#define _DRVS_LED_H
+
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+/* */
+#define SN3216_REG_MODE_CONFIG 0x00 /* D7=SSD, D6:D5=MODE, D4=AE */
+#define SN3216_REG_OUT_STATUS1 0x01 /* out16:out9 led on/off, default all on */
+#define SN3216_REG_OUT_STATUS2 0x02 /* out8:out1 led on/off, default all off */
+
+#define SN3216_REG_CURRENT 0x03 /* D7=CM, D6:D4=CS, D3=AGCE, D2:D0=AGS */
+#define SN3216_REG_GPIO_CONFIG 0x04 /* */
+#define SN3216_REG_GPIO_DIRECT 0x05 /* */
+#define SN3216_REG_GPIO_VALUE 0x06 /* */
+
+#define SN3216_REG_OUT16_PWM 0x10 /* out16~out1 pwm level 10h~1fh */
+
+#define SN3216_REG_UPDATE_PWM 0xB0 /* update pwm regs */
+
+/*00h*/
+#define SN3216_REG_MODE_CONFIG_AE_LSH (4)
+#define SN3216_REG_MODE_CONFIG_MODE_LSH (5)
+#define SN3216_REG_MODE_CONFIG_SSD_LSH (7)
+
+/*03h*/
+#define SN3216_REG_CURRENT_CS_LSH (4)
+
+
+#define SN3216_BITFVAL(var, lsh) ( (var) << (lsh) )
+#define SN3216_BITFMASK(wid, lsh) ( ((1U << (wid)) - 1) << (lsh) )
+#define SN3216_BITFEXT(var, wid, lsh) ((var & SN3216_BITFMASK(wid, lsh)) >> (lsh))
+/****************************************************************************
+* Types
+****************************************************************************/
+#if 1
+typedef enum sn3216_channel {
+ SN3216_LED1 =0x0,
+ SN3216_LED2,
+ SN3216_LED3,
+ SN3216_LED4,
+ SN3216_LED5,
+ SN3216_LED6,
+ SN3216_LED7,
+ SN3216_LED8,
+
+ SN3216_LED9,
+ SN3216_LED10,
+ SN3216_LED11,
+ SN3216_LED12,
+ SN3216_LED13,
+ SN3216_LED14,
+ SN3216_LED15,
+ SN3216_LED16,
+
+ SN3216_LED_MAX
+}sn3216_channel;
+#else
+
+typedef enum sn3216_channel {
+
+ SN3216_LED16 = 0x0,
+ SN3216_LED15,
+ SN3216_LED14,
+ SN3216_LED13,
+ SN3216_LED12,
+ SN3216_LED11,
+ SN3216_LED10,
+ SN3216_LED9,
+
+ SN3216_LED8,
+ SN3216_LED7,
+ SN3216_LED6,
+ SN3216_LED5,
+ SN3216_LED4,
+ SN3216_LED3,
+ SN3216_LED2,
+ SN3216_LED1,
+
+ SN3216_LED_MAX
+}sn3216_channel;
+#endif
+typedef enum sn3216_current {
+ SN3216_CURRENT_20 =0x0,
+ SN3216_CURRENT_15,
+ SN3216_CURRENT_10,
+ SN3216_CURRENT_5,
+ SN3216_CURRENT_40,
+ SN3216_CURRENT_35,
+ SN3216_CURRENT_30,
+ SN3216_CURRENT_25,
+
+ SN3216_CURRENT_MAX
+}sn3216_current;
+
+typedef enum sn3216_status {
+ SN3216_LED_STATUS_OFF = 0x0,
+ SN3216_LED_STATUS_ON = 0x1,
+
+ SN3216_LED_STATUS_MAX,
+}sn3216_status;
+
+typedef enum sn3216_sleep {
+ SN3216_SLEEP_OFF = 0x0,
+ SN3216_SLEEP_ON = 0x1,
+ SN3216_SLEEP_MAX,
+}sn3216_sleep;
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+SINT32 sn3216_I2cRead(UINT8 reg_addr, UINT8 *reg_val);
+SINT32 sn3216_I2cRead(UINT8 reg_addr, UINT8 *reg_val);
+SINT32 sn3216_GetRegister(UINT8 addr, UINT8* data);
+SINT32 sn3216_SetRegister(UINT8 addr, UINT8 data, UINT8 mask);
+SINT32 sn3216_SetStatus(sn3216_channel channel, sn3216_status status);
+SINT32 sn3216_SetBlink(sn3216_channel channel, UINT32 delay_on, UINT32 delay_off);
+SINT32 sn3216_SetCurrent(sn3216_current sn_current);
+SINT32 sn3216_SetPwm(sn3216_channel channel, UINT16 level);
+SINT32 sn3216_SetSleep(sn3216_sleep sleep);
+#endif/*_DRVS_LED_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_lpm.h b/cp/ps/driver/inc/misc/drvs_lpm.h
new file mode 100644
index 0000000..8ae3555
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_lpm.h
@@ -0,0 +1,206 @@
+/*******************************************************************************
+ * Copyright by ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: v0.1
+ * Author: shideyou
+ * Date: 2013-6-29
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_LPM_H
+#define _DRVS_LPM_H
+
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+//#include "drvs_general.h"
+#include "drvs_dpram.h"
+
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+/****************************************************************************
+* Types
+****************************************************************************/
+ typedef enum
+{
+ LPM_RAT_TD,
+ LPM_RAT_LTE,
+ LPM_RAT_W,
+ LPM_T4_RAT_TD,
+ LPM_T4_RAT_W,
+ LPM_T2_RAT_LTE,
+
+ MAX_LPM_RAT
+} T_ZDrvLpm_RAT;
+
+typedef struct
+{
+ UINT16 wWFrmCnt; /*0~4095 Fn*/
+ UINT16 wWSlotCnt; /*0~14 slot*/
+ UINT16 wWSymbolCnt; /*0~9 symbol*/
+ UINT16 wWChipCnt; /*0~255 chip*/
+}T_WLpmTime;
+
+typedef struct
+{
+ UINT16 wTdFrmCnt; /*0~8191 Fn*/
+ UINT16 wTdChipCnt; /*0~6400 chip*/
+}T_TdLpmTime;
+
+typedef struct
+{
+ UINT16 wLteSuperFrmCnt;
+ UINT16 wLteFrmCnt;
+ UINT16 wLteSubFrmCnt;
+}T_LteLpmTime;
+
+
+typedef VOID (*T_ZDrvLpm_CallbackFunction)(VOID); //used for LTE
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+/*******************************************************************************
+ * Function: zDrvLpm_RegCallbackForLTE
+ * Description: regist callback function for LTE_lpm interrupt
+ * Parameters:
+ * Input:
+ * callback: function be register
+ * Output:
+ * None
+ * Returns:
+ * DRV_ERROR:interrupt install failed
+ * Drv_SUCCESS:successful!
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvLpm_RegCallbackForLTE(T_ZDrvLpm_CallbackFunction callback);
+
+/*******************************************************************************
+ * Function: zDrvLpm_RegCallbackForTD
+ * Description: regist callback function for TD_lpm interrupt
+ * Parameters:
+ * Input:
+ * callback: function be register
+ * Output:
+ * None
+ * Returns:
+ * DRV_ERROR:interrupt install failed
+ * Drv_SUCCESS:successful!
+ *
+ * Others:
+ ********************************************************************************/
+ SINT32 zDrvLpm_RegCallbackForTD(T_ZDrvLpm_CallbackFunction callback);
+
+ /*******************************************************************************
+ * Function: zDrvLpm_RegCallbackForW
+ * Description: regist callback function for W_lpm interrupt
+ * Parameters:
+ * Input:
+ * callback: function be register
+ * Output:
+ * None
+ * Returns:
+ * DRV_ERROR:interrupt install failed
+ * Drv_SUCCESS:successful!
+ *
+ * Others:
+ ********************************************************************************/
+ SINT32 zDrvLpm_RegCallbackForW(T_ZDrvLpm_CallbackFunction callback);
+/*******************************************************************************
+ * Function: zDrvLpm_IrqEnable
+ * Description: enable interrupt of lpm
+ * Parameters:
+ * Input:
+ * rat: TD/W/LTE
+ * Output:
+ * None
+ * Returns:
+ * None
+ *
+ * Others:
+ ********************************************************************************/
+VOID zDrvLpm_IrqEnable(T_ZDrvLpm_RAT rat);
+
+/*******************************************************************************
+ * Function: zDrvLpm_IrqDisable
+ * Description: disable interrupt of lpm
+ * Parameters:
+ * Input:
+ * rat: TD/W/LTE
+ * Output:
+ * None
+ * Returns:
+ * None
+ *
+ * Others:
+ ********************************************************************************/
+VOID zDrvLpm_IrqDisable(T_ZDrvLpm_RAT rat);
+
+/**************************************************************************
+* º¯ÊýÃû³Æ£º lpm_WDpramSfnIsValid
+* ¹¦ÄÜÃèÊö£º »ñÈ¡WDpramÄÚÖ¡ºÅÐÅÏ¢ÊÇ·ñÓÐЧ
+* ²ÎÊý˵Ã÷£º
+* ·µ »Ø Öµ £ºTRUE ÓÐЧ£» FALSE ÎÞЧ
+* ÆäËü˵Ã÷£º
+**************************************************************************/
+BOOL zDrvLpm_WDpramSfnIsValid(void);
+
+/**************************************************************************
+* º¯ÊýÃû³Æ£º Lpm_GetWCfnSfn
+* ¹¦ÄÜÃèÊö£º PS»ñÈ¡WÖ¡ºÅµ÷¶ÈÐÅÏ¢
+* ²ÎÊý˵Ã÷£º
+* ·µ »Ø Öµ £º
+* ÆäËü˵Ã÷£º
+**************************************************************************/
+VOID zDrvLpm_GetWCfnSfn(T_ZDrvDpram_CfnSfnForW* ptCfnSfn);
+/**************************************************************************
+* º¯ÊýÃû³Æ£º zDrvLpm_GetSfn_Lte
+* ¹¦ÄÜÃèÊö£º PS»ñÈ¡LTEÖ¡ºÅÐÅÏ¢
+* ²ÎÊý˵Ã÷£º
+* ·µ »Ø Öµ £º
+* ÆäËü˵Ã÷£º
+**************************************************************************/
+UINT32 zDrvLpm_GetSfn_Lte(VOID);
+
+/**************************************************************************
+* º¯ÊýÃû³Æ£º zDrvLpm_TdDpramSfnIsValid
+* ¹¦ÄÜÃèÊö£º »ñÈ¡TdDpramÄÚÖ¡ºÅÐÅÏ¢ÊÇ·ñÓÐЧ
+* ²ÎÊý˵Ã÷£º
+* ·µ »Ø Öµ £ºTRUE ÓÐЧ£» FALSE ÎÞЧ
+* ÆäËü˵Ã÷£º
+**************************************************************************/
+BOOL zDrvLpm_TdDpramSfnIsValid(void);
+
+/**************************************************************************
+* º¯ÊýÃû³Æ£º zDrvLpm_GetTdCfnSfn
+* ¹¦ÄÜÃèÊö£º PS»ñÈ¡TDÖ¡ºÅµ÷¶ÈÐÅÏ¢
+* ²ÎÊý˵Ã÷£º
+* ·µ »Ø Öµ £ºTD NT ×ÓÖ¡ºÅ\Cfn
+* ÆäËü˵Ã÷£º
+**************************************************************************/
+VOID zDrvLpm_GetTdCfnSfn(T_ZDrvDpram_CfnSfn* ptTdCfnSfn);
+
+#endif/*_FILENAME_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_nand.h b/cp/ps/driver/inc/misc/drvs_nand.h
new file mode 100644
index 0000000..daa6ad1
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_nand.h
@@ -0,0 +1,438 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: drvs_nand.h
+* File Mark:
+* Description: tu hal interface declaration.
+* Others:
+* Version: v1.0
+* Author: wangxia
+* Date: 2008-08-28
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+
+* History 2:
+**********************************************************************/
+
+#ifndef HAL_NAND_H
+#define HAL_NAND_H
+
+#ifdef _OS_TOS
+#include <cyg/fs/tos_yaffs_nand.h>
+#endif
+#include "drvs_io.h"
+/*************************************************************************
+ * Include files *
+ *************************************************************************/
+
+
+/*************************************************************************
+ * Macro *
+ *************************************************************************/
+#define ZDRV_NAND_PART_NVRO "nvr"
+#define ZDRV_NAND_PART_NVRW "nvrw"
+#define ZDRV_NAND_PART_YAFFS "cpfs"
+/**************************************************************************
+ * Types *
+ **************************************************************************/
+typedef struct{
+ UINT8 pbyManu; /* ÖÆÔìÉÌid */
+ UINT8 pbyDevice; /* оƬid */
+ UINT8 pbyID3; /* ¸½¼Óid */
+ UINT8 pbyID4; /* ¸½¼Óid */
+ UINT8 pbyID5; /* ¸½¼Óid */
+}T_ZDrvNand_DeviceID;
+
+typedef struct{
+ UINT32 nvBase; /* NVÆðʼµØÖ·*/
+ UINT32 nvSize; /* NV´óС */
+}T_ZDrvNand_NVParam;
+
+/**
+ * NAND Flash part information
+*/
+typedef struct _T_Nand_Part_Info
+{
+
+ UINT32 PageSize;
+ UINT32 PageSpareSize;
+ UINT32 BlockSize;
+ UINT32 PartOffset;
+ UINT32 PartSize;
+ UINT32 TotalSize;
+ UINT8 *PartName;
+ T_ZDrvIO_Handle pIoHnd;
+}T_Nand_Part_Info;
+
+typedef enum {
+
+ ZFTL_PART_NVRO_NVRW=0,
+ ZFTL_PART_NVFAC,
+ ZFTL_PART_SMS,
+ ZFTL_PART_SIMNV,
+ ZFTL_PART_SIMNVFAC,
+ ZFTL_PART_MAX
+
+} T_ZFTL_PART_NO;
+
+
+/**************************************************************************
+ * Global Variable *
+ **************************************************************************/
+
+
+/**************************************************************************
+ * Function Prototypes *
+ **************************************************************************/
+/**************************************************************************
+* Function: zDrvNand_Initiate
+* Description:initialize nand for hal_init.c
+* Parameters:
+* Input:None
+* Output: None
+* Returns:None
+**************************************************************************/
+SINT32 zDrvNand_Initiate(VOID);
+
+/**************************************************************************
+* Function: zDrvNand_PartRead
+* Description:read nand base partition.
+* Parameters:
+* Input:None
+* Output: None
+* Returns:None
+**************************************************************************/
+SINT32 zDrvNand_PartRead(char* part_name,UINT32 offset,UINT32 size,UINT8* buffer);
+/**************************************************************************
+* Function: zDrvNand_PartGetSize
+* Description:get nand partition size.
+* Parameters:
+* Input:None
+* Output: None
+* Returns:None
+**************************************************************************/
+UINT32 zDrvNand_PartGetSize(char* part_name);
+
+
+/*******************************************************************************
+ * Function: zDrvNand_ReadBootflag
+ * Description: read the bootflag of zx297510
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns: 0: open dl usb
+ * 1: close dl usb
+ *
+ * Others: 0xffffffff_ffffffff: USB DL;
+ * "ZTE7510\0" : NO USB DL
+ ********************************************************************************/
+UINT32 zDrvNand_ReadBootflag( void );
+
+/*******************************************************************************
+ * Function: zDrvNand_WriteBootflag
+ * Description: write the bootflag of zx297510
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:0 success
+ * 1 fail
+ *
+ *
+ * Others: 0xffffffff_ffffffff: USB DL;
+ * "ZTE7510\0" : NO USB DL
+ ********************************************************************************/
+UINT32 zDrvNand_WriteBootflag( UINT32 flag );
+
+/*******************************************************************************
+ * Function: zDrvNand_ReadUsbtimeout
+ * Description: read the usbtimeout flag of zx297510
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns: flag:usb time out (1~10)
+ *
+ *
+ * Others:
+ ********************************************************************************/
+UINT32 zDrvNand_ReadUsbtimeout( void );
+
+/*******************************************************************************
+ * Function: zDrvNand_WriteUsbtimeout
+ * Description: write the usbtimeout flag of zx297510
+ * Parameters:
+ * Input:flag (1~10)
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+UINT32 zDrvNand_WriteUsbtimeout( UINT32 flag );
+
+
+/**************************************************************************
+* º¯ÊýÃû³Æ£º zDrvNand_GetNVParam
+* ¹¦ÄÜÃèÊö£º This function is used to get nv param
+
+* ²ÎÊý˵Ã÷£º (IN)
+ none.
+ (OUT)
+ nvParam: nvÆðʼµØÖ·´óС.
+
+* ·µ »Ø Öµ£º 0: ³É¹¦
+* !=0: ʧ°Ü
+
+* ÆäËü˵Ã÷£º none.
+**************************************************************************/
+extern SINT32 zDrvNand_GetNVParam(T_ZDrvNand_NVParam *nvParam);
+
+/**************************************************************************
+* º¯ÊýÃû³Æ£º zDrvNand_ReadID
+* ¹¦ÄÜÃèÊö£º This function is used to identify the nand chip
+
+* ²ÎÊý˵Ã÷£º (IN)
+ none.
+ (OUT)
+ pbyDevice: ³§ÉÌid,оƬid,¸½¼Óid,¸½¼Óid.
+
+* ·µ »Ø Öµ£º 0: ³É¹¦
+* !=0: ʧ°Ü
+
+* ÆäËü˵Ã÷£º none.
+**************************************************************************/
+extern SINT32 zDrvNand_ReadID(T_ZDrvNand_DeviceID *pbyDevice);
+
+
+/**************************************************************************
+* º¯ÊýÃû³Æ£º zDrvNand_Initialize
+* ¹¦ÄÜÃèÊö£º This function is used to initialize the nand chip
+
+* ²ÎÊý˵Ã÷£º (IN)
+ none.
+ (OUT)
+ none.
+
+* ·µ »Ø Öµ£º none.
+
+* ÆäËü˵Ã÷£º none.
+***************************************************************************/
+extern SINT32 zDrvNand_Initialize(void);
+
+/**************************************************************************
+* º¯ÊýÃû³Æ£º zDrvNand_Erase
+* ¹¦ÄÜÃèÊö£º This function is used to erase the nand blocks spcified by
+ dwStart and dwEnd.
+
+* ²ÎÊý˵Ã÷£º (IN)
+ dwStart: start address to erase
+ dwEnd: end address to erase
+ µØÖ··¶Î§£º( NAND_BASE ~ NAND_BASE + BYTES_IN_NAND )
+ (OUT)
+ none.
+
+* ·µ »Ø Öµ£º 0: ³É¹¦
+* !=0: ʧ°Ü
+
+* ÆäËü˵Ã÷£º ¸Ã¹¦ÄܽöÔÚÕû¿é²Á³ýºÍ¸ñʽ»¯Ê±Ê¹Óá£
+ дµÄʱºòÎÞÐè²Á³ý±»Ð´ÇøÓò.
+ ²Á³ýʱdwStart¡¢dwEndËù¿çµÄ¿é£¨Ã¿¿é16K byte£©½«±»È«²¿²Á³ý¡£
+**************************************************************************/
+extern SINT32 zDrvNand_Erase(UINT32 dwStart, UINT32 dwEnd);
+
+extern SINT32 zDrvNand_Program_1(T_ZFTL_PART_NO partNo, UINT32 offset, UINT32 len, UINT8* from);
+extern SINT32 zDrvNand_Read_1(T_ZFTL_PART_NO partNo, UINT32 offset, UINT32 len, UINT8* to);
+
+#ifdef _OS_TOS
+/**************************************************************************
+* Function: zDrvNand_PartOpen
+* Description:get nand parameters for ecos fs.
+* Parameters:
+* Input: part_name:partition name
+* Output: pNandPartInfo:part information
+* Returns:0: success
+* other: error
+**************************************************************************/
+SINT32 zDrvNand_PartOpen(UINT8* part_name, T_zYaffs_PartInfo *pNandPartInfo);
+
+/*******************************************************************************
+ * Function: zDrvNand_PartReadMain
+ * Description: yaffs read nand main
+ * Parameters:
+ * Input:pNandPartInfo:yaffs information;
+ * dwAddr:start addr;
+ * dwLen:read length;
+ * pbyBuf:read buffer;
+ * Output:
+ *
+ * Returns: 0:success;
+ * others:fail
+ *
+ *
+ * Others:
+ ********************************************************************************/
+
+SINT32 zDrvNand_PartReadMain(T_zYaffs_PartInfo *pNandPartInfo, UINT32 dwAddr, UINT32 dwLen, UINT8 *pbyBuf);
+
+/**************************************************************************
+* Function: zDrvNand_PartReadSpare
+* Description: read data from flash
+* Parameters:
+* Input: pNandPartInfo:yaffs information;
+* dwAddr: address
+* dwLen: length to read
+* Output: None
+* Returns:
+* 0: success
+* other: error
+* Others: Éϲãµ÷ÓÃzDrvNand_PartReadSpare()µÄº¯Êý dwLen ¶ÁÈ¡µÄ³¤¶È¶¼Îª Õû¸öOOB
+ dwAddr ¶ÁÈ¡µØÖ·¶¼Îª Ò³µØÖ·¶ÔÆë
+
+**************************************************************************/
+SINT32 zDrvNand_PartReadSpare(T_zYaffs_PartInfo *pNandPartInfo,UINT32 dwAddr, UINT32 dwLen, UINT8 *pbyBuf);
+
+/**************************************************************************
+* Function: zDrvNand_PartWriteMain
+* Description: write data to flash of main area
+* Parameters:
+* Input: pNandPartInfo:yaffs information;
+* dwAddr: address
+* dwLen: length to read
+* pMBuf: buffer in which data is stored
+* Output: None
+* Returns:
+* 0: success
+* other: error
+* Others: Éϲãµ÷ÓÃzDrvNand_PartWriteMain()µÄº¯Êý dwLen дÈëµÄ³¤¶È1 page,
+ dwAddr дÈëµØÖ·¶¼Îª Ò³µØÖ·¶ÔÆë
+
+**************************************************************************/
+SINT32 zDrvNand_PartWriteMain(T_zYaffs_PartInfo *pNandPartInfo, UINT32 dwAddr, UINT32 dwLen, UINT8 *pbyBuf);
+
+/**************************************************************************
+* Function: zDrvNand_PartWriteSpare
+* Description: write data to flash of spare area
+* Parameters:
+* Input: pNandPartInfo:yaffs information;
+* dwAddr: address
+* dwLen: length to read
+* pbyBuf: buffer in which data is stored
+* Output: None
+* Returns:
+* 0: success
+* other: error
+* Others: Éϲãµ÷ÓÃzDrvNand_PartWriteSpare()µÄº¯Êý dwLen дÈëµÄ³¤¶È¶¼ÎªÕû¸öOOB
+ dwAddr дÈëµØÖ·¶¼Îª Ò³µØÖ·¶ÔÆë
+
+**************************************************************************/
+SINT32 zDrvNand_PartWriteSpare(T_zYaffs_PartInfo *pNandPartInfo, UINT32 dwAddr, UINT32 dwLen, UINT8 *pbyBuf);
+
+/**************************************************************************
+* Function: zDrvNand_PartErase
+* Description: erase a block
+* Parameters:
+* Input: pNandPartInfo:yaffs information;
+* dwAddr: address,block aliagn
+* Output: None
+* Returns:
+* 0: success
+* other: error
+* Others:
+**************************************************************************/
+SINT32 zDrvNand_PartErase(T_zYaffs_PartInfo *pNandPartInfo, UINT32 dwAddr);
+
+/**************************************************************************
+* Function: zDrvNand_PartCheckBadBlock
+* Description:check badblock for ecos fs.
+* Parameters:
+* Input: pNandPartInfo:part information
+* dwAddr:start addrress
+* Output: None
+* Returns:DRV_SUCCESS: good block
+* DRV_ERROR: bad block
+**************************************************************************/
+
+SINT32 zDrvNand_PartCheckBadBlock(T_zYaffs_PartInfo *pNandPartInfo,UINT32 dwAddr);
+
+/**************************************************************************
+* Function: zDrvNand_PartMarkBadBlock
+* Description:mark badblock for ecos fs.
+* Parameters:
+* Input: pNandPartInfo:part information
+* dwAddr:start addrress
+* Output: None
+* Returns:DRV_SUCCESS: mark bad success
+* DRV_ERROR: mark bad fail
+**************************************************************************/
+
+SINT32 zDrvNand_PartMarkBadBlock(T_zYaffs_PartInfo *pNandPartInfo,UINT32 dwAddr);
+#endif
+
+/**************************************************************************
+* Function: zDrvNand_PartMtdOpen
+* Description:get nand parameters for FOTA.
+* Parameters:
+* Input:None
+* Output: None
+* Returns:None
+**************************************************************************/
+SINT32 zDrvNand_PartMtdOpen(UINT8* part_name, T_Nand_Part_Info *pNandPartInfo);
+
+/**************************************************************************
+* Function: zDrvNand_PartMtdRead
+* Description:read data for FOTA.
+* Parameters:
+* Input:None
+* Output: None
+* Returns:None
+**************************************************************************/
+SINT32 zDrvNand_PartMtdRead(T_Nand_Part_Info *pNandPartInfo,UINT32 dwAddr, UINT32 dwLen, UINT8 *pbyBuf);
+/**************************************************************************
+* Function: zDrvNand_PartMtdWrite
+* Description:read data for FOTA.
+* Parameters:
+* Input:None
+* Output: None
+* Returns:None
+**************************************************************************/
+SINT32 zDrvNand_PartMtdWrite(T_Nand_Part_Info *pNandPartInfo,UINT32 dwAddr, UINT32 dwLen, UINT8 *pbyBuf);
+/**************************************************************************
+* Function: zDrvNand_PartMtdErase
+* Description:erase data for FOTA.
+* Parameters:
+* Input:None
+* Output: None
+* Returns:None
+**************************************************************************/
+SINT32 zDrvNand_PartMtdErase(T_Nand_Part_Info *pNandPartInfo,UINT32 dwAddr);
+
+/**************************************************************************
+* Function: zDrvNand_NvRwEccMake
+* Description:
+* Parameters:
+* Input:
+*
+* Output: None
+* Returns: 0: ÕýÈ·
+ ÆäËû: ´íÎó
+*
+*
+* Others:
+**************************************************************************/
+SINT32 zDrvNand_NvRwEccMake(UINT32 dwStart, UINT32 dwLen);
+
+
+
+#endif /* HAL_NAND_H */
+
diff --git a/cp/ps/driver/inc/misc/drvs_nand_ids.h b/cp/ps/driver/inc/misc/drvs_nand_ids.h
new file mode 100644
index 0000000..b8a1318
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_nand_ids.h
@@ -0,0 +1,166 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: drvs_nand.h
+* File Mark:
+* Description: tu hal interface declaration.
+* Others:
+* Version: v1.0
+* Author: wangxia
+* Date: 2008-08-28
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+
+* History 2:
+**********************************************************************/
+
+#ifndef DRV_NAND_IDS_H
+#define DRV_NAND_IDS_H
+
+/*************************************************************************
+ * Include files *
+ *************************************************************************/
+
+
+/*************************************************************************
+ * Macro *
+ *************************************************************************/
+
+
+/**************************************************************************
+ * Types *
+ **************************************************************************/
+#if 1
+/*
+* nand_flash_timing
+*/
+struct nand_flash_timing
+{
+ unsigned char Twhr; /*reg offset 0x100*/ /*spi nand: rd delay*/
+ unsigned char Trr1; /*spi nand: cs setup*/
+ unsigned char Tadl; /*reg offset 0x110*/ /*spi nand: cs hold*/
+ unsigned char Trr2; /*spi nand: cs desel*/
+ unsigned char Trhw; /*reg offset 0x120*/
+ unsigned char Trea; /*reg offset 0x130*/
+ unsigned char Trp; /*reg offset 0x1f0, or Twp*/
+ unsigned char Treh; /*reg offset 0x200, or Tweh*/
+ unsigned char Tcs; /*reg offset 0x220*/
+ unsigned char Trhz; /*reg offset 0x290*/
+};
+
+
+struct nand_ecc
+{
+ unsigned int strength; /*ECC ¾À´íÄÜÁ¦*/
+ unsigned int sector_size; /*ECC ¾À´íµÄÊý¾Ý¿é´óС*/
+};
+
+
+/*nand É豸ÃèÊö½á¹¹Ìå*/
+struct nand_flash_device_para
+{
+ unsigned char manuf_id; /* ³§¼ÒID */
+ unsigned char device_id; /* É豸ID */
+ unsigned char res_id; /* Æ÷¼þID */
+ unsigned char bus_num; /* 0:8λ 1:16λ */
+ unsigned int page_size; /* ÿҳmainÇøÓò´óС */
+ unsigned int oob_size; /* ÿҳspareÇøÓò´óС */
+ unsigned int column_addr_num; /* ÁеØÖ·Ñ°Ö·ÖÜÆÚÊý */
+ unsigned int row_addr_num; /* ÐеØÖ·Ñ°Ö·ÖÜÆÚÊý */
+ unsigned int block_size; /* ÿ¿éµÄ´óС */
+ unsigned int pages_per_block; /* ÿ¿éµÄÒ³Êý */
+ unsigned int block_num; /* ¿éÊý */
+ unsigned int die_num;
+ unsigned int bad_block_markpos; /* »µ¿é±ê־λλÖÃ,´Ó0¿ªÊ¼ */
+ struct nand_flash_timing nand_timeing;
+
+ struct nand_ecc ecc;
+};
+#endif
+
+
+/**
+ * struct nand_flash_dev - NAND Flash Device ID Structure
+ * @name: Identify the device type
+ * @id: device ID code
+ * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
+ * If the pagesize is 0, then the real pagesize
+ * and the eraseize are determined from the
+ * extended id bytes in the chip
+ * @erasesize: Size of an erase block in the flash device.
+ * @chipsize: Total chipsize in Mega Bytes
+ * @options: Bitfield to store chip relevant options
+ */
+struct nand_flash_dev {
+ char *name;
+ int id;
+ unsigned long pagesize;
+ unsigned long chipsize;
+ unsigned long erasesize;
+ unsigned long options;
+};
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @name: Manufacturer name
+ * @id: manufacturer ID code of device.
+*/
+struct nand_manufacturers {
+ int id;
+ char * name;
+};
+
+
+
+
+/* Option constants for bizarre disfunctionality and real
+* features
+*/
+/* Chip can not auto increment pages */
+#define NAND_NO_AUTOINCR 0x00000001
+/* Buswitdh is 16 bit */
+#define NAND_BUSWIDTH_16 0x00000002
+/* Device supports partial programming without padding */
+#define NAND_NO_PADDING 0x00000004
+/* Chip has cache program function */
+#define NAND_CACHEPRG 0x00000008
+/* Chip has copy back function */
+#define NAND_COPYBACK 0x00000010
+/* AND Chip which has 4 banks and a confusing page / block
+ * assignment. See Renesas datasheet for further information */
+#define NAND_IS_AND 0x00000020
+/* Chip has a array of 4 pages which can be read without
+ * additional ready /busy waits */
+#define NAND_4PAGE_ARRAY 0x00000040
+/* Chip requires that BBT is periodically rewritten to prevent
+ * bits from adjacent blocks from 'leaking' in altering data.
+ * This happens with the Renesas AG-AND chips, possibly others. */
+#define BBT_AUTO_REFRESH 0x00000080
+/* Chip does not require ready check on read. True
+ * for all large page devices, as they do not support
+ * autoincrement.*/
+#define NAND_NO_READRDY 0x00000100
+/* Chip does not allow subpage writes */
+#define NAND_NO_SUBPAGE_WRITE 0x00000200
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA 0x98
+#define NAND_MFR_SAMSUNG 0xec
+#define NAND_MFR_FUJITSU 0x04
+#define NAND_MFR_NATIONAL 0x8f
+#define NAND_MFR_RENESAS 0x07
+#define NAND_MFR_STMICRO 0x20
+#define NAND_MFR_HYNIX 0xad
+#define NAND_MFR_MICRON 0x2c
+#define NAND_MFR_AMD 0x01
+#define NAND_MFR_GIGADEVICE 0xC8
+
+
+#endif /* DRV_NAND_IDS_H */
+
diff --git a/cp/ps/driver/inc/misc/drvs_nv.h b/cp/ps/driver/inc/misc/drvs_nv.h
new file mode 100644
index 0000000..3ea5b57
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_nv.h
@@ -0,0 +1,59 @@
+/***********************************************************************
+* Copyright (C) 2013, ZTE Corporation.
+*
+* File Name: drvs_nv.h
+* File Mark:
+* Description: Provide audio NV function prototype declaration and type declaration. The audio NV type declaration is moved from eep.h.
+* Others:
+* Version: v0.5
+* Author: zhouqi
+* Date: 2013-05-8
+*
+* History 1:
+* Date:2013-07-23
+* Version:
+* Author:geanfeng
+* Modification:add NV macro
+* History 2:
+**********************************************************************/
+
+#ifndef _DRVS_NV_H
+#define _DRVS_NV_H
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "drvs_general.h"
+/****************************************************************************
+* Macros
+****************************************************************************/
+/****************************************************************************
+* Types
+****************************************************************************/
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+/**************************************************************************
+* Function: zDrvNand_ChangeNvrAttr
+* Description: ÉèÖÃNV_R·ÖÇøµÄ¶ÁдÊôÐÔ£¬Ä¬ÈÏΪֻ¶Á
+* Parameters:
+* Input:
+*
+* Output: None
+* Returns:
+*
+*
+* Others: ĬÈÏֵΪ 0x0 Ö»¶Á
+ 0x1 ¶Áд
+**************************************************************************/
+SINT32 zDrvNand_ChangeNvrAttr( UINT32 rw );
+
+#endif /* _DRVS_NV_H */
+
diff --git a/cp/ps/driver/inc/misc/drvs_p_sio_mux_ata.h b/cp/ps/driver/inc/misc/drvs_p_sio_mux_ata.h
new file mode 100644
index 0000000..22be837
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_p_sio_mux_ata.h
@@ -0,0 +1,227 @@
+/* ==========================================================================
+** Copyright (C) 1999 - 2007 COMNEON GmbH. All rights reserved.
+** ==========================================================================
+**
+** ==========================================================================
+**
+** This document contains proprietary information belonging to COMNEON.
+** Passing on and copying of this document, use and communication of its
+** contents is not permitted without prior written authorisation.
+**
+** ==========================================================================
+** Revision Information :
+** File name: sio_scc.h
+** Version: /main/sio_main/66
+** Date: 2007-05-09 15:43:50
+**
+** ==========================================================================
+** Project: Mobile Station (MS)
+** Block: -
+** Process: -
+**
+** ==========================================================================
+** Contents: DTE-AT adapter to receive at commands from the DTE
+**
+** ==========================================================================
+** History:
+**
+** Date Author Comment
+** --------------------------------------------------------------------------
+** 04.11.03 ges Added ata_control.
+** 13.05.03 wein Added TCP/IP over serial mode.
+** 19.03.03 wein Removed USB from ata_op1.c.
+** 23.01.03 hwe Merge: Added ata_linestate().
+** 02.10.02 hwe Added WAP DS.
+** 04.12.01 ges added ata_set_pec_size().
+** 06.11.01 ges added ATA_OFFLINE_PTEST and ATA_OFFLINE_END_PTEST
+** (production test modes).
+** 26.07.01 rha added ata_free_tx_buf().
+** 13.09.99 ges created.
+**
+** ==========================================================================
+*/
+
+#ifndef SIO_MUX_ATA_H
+#define SIO_MUX_ATA_H
+
+/*
+** =========================================================================
+** GLOBAL DEFINES
+** =========================================================================
+*/
+/* mux dev define begin */
+#define ZDRV_DEV_SIO_MUX_1 "/mux/1"
+#define ZDRV_DEV_SIO_MUX_2 "/mux/2"
+#define ZDRV_DEV_SIO_MUX_3 "/mux/3"
+#define ZDRV_DEV_SIO_MUX_4 "/mux/4"
+#define ZDRV_DEV_SIO_MUX_5 "/mux/5"
+#define ZDRV_DEV_SIO_MUX_6 "/mux/6"
+#define ZDRV_DEV_SIO_MUX_7 "/mux/7"
+#define ZDRV_DEV_SIO_MUX_8 "/mux/8"
+#define ZDRV_DEV_SIO_MUX_9 "/mux/9"
+#define ZDRV_DEV_SIO_MUX_10 "/mux/10"
+#define ZDRV_DEV_SIO_MUX_11 "/mux/11"
+#define ZDRV_DEV_SIO_MUX_12 "/mux/12"
+#define ZDRV_DEV_SIO_MUX_13 "/mux/13"
+#define ZDRV_DEV_SIO_MUX_14 "/mux/14"
+#define ZDRV_DEV_SIO_MUX_15 "/mux/15"
+/* mux dev define end */
+#define SIO_USE_SOCKET_CONCEPT 0
+#define SIO_FBUS_AVAILABLE 0
+/*
+** =========================================================================
+** GLOBAL TYPES
+** =========================================================================
+*/
+
+
+/*
+** =========================================================================
+** GLOBAL FUNCTIONS
+** =========================================================================
+*/
+/****************************************************************************
+* Type: cmux_cmd_par_t
+*----------------------------------------------------------------------------
+* Purpose: the parameters of the at command AT+CMUX.
+*
+* Parameters: None.
+*
+* Returns: None - on error the function exits.
+****************************************************************************/
+typedef struct
+{
+ unsigned char mode;
+ unsigned char subset;
+ unsigned int port_speed;
+ unsigned int n1;
+ unsigned char t1;
+ unsigned char n2;
+ unsigned char t2;
+ unsigned char t3;
+ unsigned char k;
+
+} cmux_cmd_par_t;
+
+typedef enum ata_mode_e
+{
+ /*
+ ** AT command mode
+ */
+ ATA_OFFLINE_CMD = 0, /* Single line mode */
+ ATA_OFFLINE_SMS_TEXT = 3, /* Multi line mode */
+ ATA_OFFLINE_SMS_PDU = 7, /* Multi line mode */
+ ATA_OFFLINE_CHAR = 1, /* AT break-off mode */
+
+ ATA_ONLINE = 2, /* No AT line mode, DS data transfer mode */
+ ATA_ONLINE_CMD = 4, /* Interrupted DS mode, AT line mode */
+
+ ATA_OFFLINE_BUSY = 5, /* AT command in progress */
+ ATA_ONLINE_BUSY = 6, /* AT command in progress */
+
+ ATA_ONLINE_PTP = 10, /* Point to Point Protocol mode. */
+
+ ATA_OFFLINE_PTEST = 12, /* AT is ready to process productions
+ * test commands.
+ */
+ ATA_OFFLINE_END_PTEST = 13, /* AT processing a production test command.
+ */
+ ATA_ONLINE_PTEST, /* AT is in production test transfer mode.
+ */
+ ATA_MUX, /* multiplexing mode */
+ ATA_ONLINE_AP_AT, /* application over AT/serial mode */
+ ATA_ONLINE_AP_DS, /* application over DS mode */
+ ATA_ONLINE_TRACE, /* FD is connected to the trace device. */
+ ATA_ONLINE_TRACE_CHANGE, /* The trace device change is ongoing. */
+
+#if SIO_USE_SOCKET_CONCEPT > 0
+ ATA_ONLINE_SOCKET, /* Give the port control to another
+ * application. */
+#endif
+ ATA_ONLINE_DS_SYNC, /* DS data transfer mode - waiting for sync. */
+ ATA_ONLINE_DS, /* DS data transfer mode */
+
+ ATA_SMS_CHAR_MODE, /* SMS char mode - SMS PDU or SMS Text mode.
+ * SMS is sent as ascii coded text PDU or hex coded binary PDU.
+ */
+#if SIO_FBUS_AVAILABLE == 1
+ ATA_ONLINE_FBUS_BUSY, /* An FBUS frame is processed. */
+ ATA_ONLINE_FBUS_IDLE, /* Enter the idle mode of the FBUS protocol. */
+ ATA_ONLINE_FBUS_INIT, /* Start the FBUS protocol. */
+#endif
+
+ ATA_NO_MODE
+
+} ata_mode_t;
+
+/****************************************************************************
+* Type: cmux_test_par_t
+*----------------------------------------------------------------------------
+* Purpose: the parameters of the at test command AT+CMUX=?.
+*
+* Parameters: None.
+*
+* Returns: None - on error the function exits.
+****************************************************************************/
+
+typedef struct {
+ char buf[64];
+} cmux_test_par_t;
+
+/**B**************************************************************************
+* Function: ata_mux_test
+*-----------------------------------------------------------------------------
+* Usage: None
+*
+* Remarks: None
+***E*************************************************************************/
+int ata_mux_test (int tid, cmux_test_par_t *cmux_test_rsp_p);
+
+/**B**************************************************************************
+* Function: ata_mux_read
+*-----------------------------------------------------------------------------
+* Usage: None
+*
+* Remarks: None
+***E*************************************************************************/
+int ata_mux_read (int tid, cmux_cmd_par_t *cmux_cmd_par_p);
+
+/**B**************************************************************************
+* Function: ata_mux_cmd
+*-----------------------------------------------------------------------------
+* Usage: cmux_cmd_par_t ÖеÄn1×î´óÖ§³Ö2047
+*
+* Remarks: None
+***E*************************************************************************/
+int ata_mux_cmd (int tid, cmux_cmd_par_t *cmux_cmd_par);
+
+/**B**************************************************************************
+* Function: ata_mux_release
+*-----------------------------------------------------------------------------
+* Usage: None
+*
+* Remarks: None
+***E*************************************************************************/
+int ata_mux_release (int tid);
+
+#if 0 /* ͳһʹÓÃDD_SIOµÄCTRLÃüÁî */
+typedef enum
+{
+ IOCTL_SIO_MUX_SET_DATA, /*set data config command,set baudrate.param:T_ZDrvSio_DataConfig*/
+ IOCTL_SIO_MUX_SET_BUFFER, /*set data buffer command,param:T_ZDrvSio_SetConfig */
+ IOCTL_SIO_MUX_SET_BLOCKTIME, /*set sio block read*/
+ IOCTL_SIO_MUX_SET_BLOCK,
+ IOCTL_SIO_MUX_CLEAN_BLOCK, /*clean the sio block read*/
+ IOCTL_SIO_MUX_CALLBACK, /*set sio non block callback function.param:T_ZDrvSio_Read_CallBack*/
+ #if 0 /* 617001655333 MUXÓÅ»¯ºó²»ÐèÒªÒÔÏÂIOCTLÖ¸Áî */
+ IOCTL_SIO_MUX_ACTIVE_MUX, /*active mux mode add by zqs*/
+ IOCTL_SIO_MUX_DEACTIVE_MUX, /*deactive mux mode,back to normal add by zqs*/
+ IOCTL_SIO_MUX_GET_TX_FINISH, /*get tx state for check send over zqs*/
+ #endif
+ IOCTL_SIO_MUX_CMD_MAX
+} T_ZDrvSio_MUX_IOCTL; /*sio mux ioctl command*/
+#endif
+
+#endif /* SIO_MUX_ATA_H */
+
+/* drvs_sio_mux_ata.h ends here. */
diff --git a/cp/ps/driver/inc/misc/drvs_pcu.h b/cp/ps/driver/inc/misc/drvs_pcu.h
new file mode 100644
index 0000000..0144172
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_pcu.h
@@ -0,0 +1,120 @@
+/***********************************************************************
+* Copyright (C) 2014, ZTE Corporation.
+*
+* File Name: drvs_pcu.h
+* File Mark:
+* Description: pcu control interface declaration.
+* Others:
+* Version: v1.0
+* Author: limeifeng
+* Date: 2014-01-22
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+
+**********************************************************************/
+#ifndef DRVS_PCU_H
+#define DRVS_PCU_H
+
+/*************************************************************************
+ * Include files *
+ *************************************************************************/
+#include "drvs_general.h"
+/****************************************************************************
+* macro
+****************************************************************************/
+
+/****************************************************************************
+* Type
+****************************************************************************/
+/**************************************************************************
+ * Global Variable *
+ **************************************************************************/
+
+/**************************************************************************
+ * Function Prototypes *
+ **************************************************************************/
+/*******************************************************************************
+ * Function: zDrvPcu_InitIntType
+ * Description:ÉèÖþ¹ýPCUµÄÖжÏÔ´Í·ÀàÐͲ¢ÇåÖжϣ¬GPIOĬÈÏΪµçƽ´¥·¢¡£
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ * Others:´Ëº¯ÊýÖ»¹©ÖжÏÄ£¿éµ÷Óã¬ÆäËüÄ£¿éÇ벻ҪʹÓÃ!
+ ********************************************************************************/
+VOID zDrvPcu_InitIntType(VOID);
+
+/*******************************************************************************
+ * Function: zDrvPcu_SetWakeInt
+ * Description:
+ * ÉèÖÃij¸öÖжÏÊÇ·ñΪ»½ÐÑÖжÏ
+ * Parameters:
+ * Input:
+ * intLine: ÖжϺÅ
+ * isWakeInt: ÊÇ·ñΪ»½ÐÑÖжϣ¬0 »½ÐÑÖÐ¶Ï 1 ·Ç»½ÐÑÖжÏ
+ * Output:
+ *
+ * Returns: ³É¹¦·µ»ØDRV_SUCCESS£¬Ê§°Ü·µ»ØDRV_ERROR¡£
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvPcu_SetWakeInt(UINT32 intLine, BOOL isWakeInt);
+
+/*******************************************************************************
+ * Function: zDrvPcu_ClrInt
+ * Description:Çå³ýÖжÏÔÚPCUµÄÖжÏ״̬¡£
+ * Èç¹û¶ÔÓ¦ÖжϾ¹ýPCUÇÒÖжÏÔ´Í·ÀàÐÍΪ±ßÑØ´¥·¢£¬
+ * ÔòÐèÒªÔÚÖжϻص÷º¯ÊýISRÀïµ÷Óô˺¯ÊýÇå³ýÖжÏ״̬¡£
+ * Parameters:
+ * Input:
+ * intSel: T_PCUINT_SELö¾ÙÀàÐÍ,ÒªÇå³ýµÄÖжϡ£
+ * Output:
+ *
+ * Returns: ³É¹¦·µ»ØDRV_SUCCESS£¬Ê§°Ü·µ»ØDRV_ERROR¡£
+ *
+ * Others:
+ ********************************************************************************/
+//SINT32 zDrvPcu_ClearInt(UINT32 intLine);
+
+
+/*******************************************************************************
+ * Function: zDrvPcu_SetIntLevel
+ * Description:
+ * 1.¶ÔÓÚPCU²à¹Ì¶¨´¥·¢·½Ê½µÄÖжϲ»ÐèÒªµ÷Óô˺¯Êý
+ * ÒÑÔÚÖжÏÄ£¿é³õʼ»¯Ê±ÅäÖá£
+ * 2.´Ëº¯ÊýÖ÷Òª¸øÍⲿÖжÏÀàÐÍ¿ÉÉèÖõÄGPIO_EX_INTºÍEX_INT¸ù¾Ý
+ * ʵ¼Ê´¥·¢·½Ê½½øÐÐÅäÖá£
+ * Parameters:
+ * Input:
+ * intSel: T_IntPCURegö¾ÙÀàÐÍ
+ * level: PCU²àµÄÖжϴ¥·¢·½Ê½
+ * Output:
+ *
+ * Returns: ³É¹¦·µ»ØDRV_SUCCESS£¬Ê§°Ü·µ»ØDRV_ERROR¡£
+ *
+ * Others:
+ ********************************************************************************/
+//SINT32 zDrvPcu_SetIntLevel(UINT32 intLine,T_zDrvIntLineLevel level);
+
+/*******************************************************************************
+ * Function: zDrvPcu_Clear8in1Int
+ * Description:EX8IN1_INT0_PCU~EX8IN1_INT7_PCUÐèÒª¶îÍâµ÷Óô˺¯ÊýÇå³ýÖжÏ
+ * Parameters:
+ * Input:
+ * intSel: T_PCUINT_SELö¾ÙÀàÐÍ,ÒªÇå³ýµÄÖжϡ£
+ * Output:
+ *
+ * Returns: ³É¹¦·µ»ØDRV_SUCCESS£¬Ê§°Ü·µ»ØDRV_ERR_INVALID_PARAM¡£
+ *
+ * Others:
+ ********************************************************************************/
+//SINT32 zDrvPcu_Clear8in1Int(VOID);
+
+#endif /* DRVS_PCU_H */
diff --git a/cp/ps/driver/inc/misc/drvs_pmic.h b/cp/ps/driver/inc/misc/drvs_pmic.h
new file mode 100644
index 0000000..608cee8
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_pmic.h
@@ -0,0 +1,34 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: drvs_pmic.h
+ * File Mark:
+ * Description: Provide pmic interface for other module' use.(mc13783 and lp3917)
+ * Others:
+ * Version: V0.5
+ * Author: zhangyingjun
+ * Date: 2009-06-17
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_PMIC_H
+#define _DRVS_PMIC_H
+
+#include "drvs_pm.h"
+#include "drvs_pmic_bus.h"
+#include "drvs_pmic_int.h"
+#include "drvs_pmic_adc.h"
+#include "drvs_pmic_addr.h"
+#include "drvs_pmic_rtc.h"
+#include "drvs_pmic_regulator.h"
+#include "drvs_pmic_wrapper.h"
+#endif
+
+
+
+
diff --git a/cp/ps/driver/inc/misc/drvs_pmic_adc.h b/cp/ps/driver/inc/misc/drvs_pmic_adc.h
new file mode 100644
index 0000000..4cfe089
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_pmic_adc.h
@@ -0,0 +1,52 @@
+/*******************************************************************************
+ * Copyright (C) 2016, ZTE Corporation.
+ *
+ * File Name: hal_pmic_adc.h
+ * File Mark:
+ * Description: pmic adc interface.
+ * Others:
+ * Version: V1.0
+ * Author: yuxiang
+ * Date: 2016-01-27
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef __DRVS_PMIC_ADC_H_
+#define __DRVS_PMIC_ADC_H_
+
+#if defined(_USE_PMIC_ZX234290)
+typedef enum _T_ZDrvPmic_AdcChannel
+{
+ ADC_CHANNEL_VBAT_ADC = 0,
+ ADC_CHANNEL_VADC2 = 1, /* 01 */
+ ADC_CHANNEL_VADC1 = 2, /* 10 */
+
+ MAX_ADC_CHANNEL
+}T_ZDrvPmic_AdcChannel;
+
+/* ADC */
+#define ZX234290_ADC_ADC_START_LSH (5)
+#define ZX234290_ADC_ADC1_EN_LSH (4)
+#define ZX234290_ADC_ADC2_EN_LSH (3)
+
+#define ZX234290_ADC_ADC_START_WID (1)
+#define ZX234290_ADC_ADC1_EN_WID (1)
+#define ZX234290_ADC_ADC2_EN_WID (1)
+
+/* CODE 12BIT */
+#define ZX234290_ADC_DATAMSB_LSH (0) /* DATA0 - DATA11 */
+#define ZX234290_ADC_DATALSB_LSH (4) /* */
+#define ZX234290_ADC_DATAMSB_WID (8) /* DATA0 - DATA11 */
+#define ZX234290_ADC_DATALSB_WID (4) /* */
+
+SINT32 zDrvPmic_AdcInit(VOID);
+SINT32 zDrvPmic_AdcExit(VOID);
+SINT32 zDrvPmic_AdcSingleAdcRead(T_ZDrvPmic_AdcChannel channel, SINT32 *value);
+SINT32 zDrvPmic_AdcAvgAdcRead(T_ZDrvPmic_AdcChannel channel, SINT32 *avgValue);
+#endif
+#endif
+
diff --git a/cp/ps/driver/inc/misc/drvs_pmic_addr.h b/cp/ps/driver/inc/misc/drvs_pmic_addr.h
new file mode 100644
index 0000000..9b96da7
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_pmic_addr.h
@@ -0,0 +1,132 @@
+/*******************************************************************************
+ * Copyright (C) 2016, ZTE Corporation.
+ *
+ * File Name: drvs_pmic_addr.h
+ * File Mark: register addresses of pmic
+ * Description:
+ * Others:
+ * Version: V1.0
+ * Author: yuxiang
+ * Date: 2016-01-27
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef _DRVS_PMIC_ADDR_H
+#define _DRVS_PMIC_ADDR_H
+
+#if defined(_USE_PMIC_ZX234290)
+
+/////////////////////////////////////////////////
+/*slave address 0x12*/
+/////////////////////////////////////////////////
+#define ZX234290_I2C_SLAVE_ADDR0 (0x12)
+
+/* interrupt and mask */
+#define ZX234290_REG_ADDR_INTA 0x00 /* INTERRUPT */
+#define ZX234290_REG_ADDR_INTB 0x01
+#define ZX234290_REG_ADDR_INTA_MASK 0x02
+#define ZX234290_REG_ADDR_INTB_MASK 0x03
+
+/* interrupt status */
+#define ZX234290_REG_ADDR_STSA 0x04
+#define ZX234290_REG_ADDR_STSB 0x05
+#define ZX234290_REG_ADDR_STS_STARTUP 0x06
+
+/* adc & softon select */
+#define ZX234290_REG_ADDR_SYS_CTRL 0x07 /*0x8 0x9Ìø¹ý*/
+
+/* bucks normal voltage and sleep voltage */
+#define ZX234290_REG_ADDR_BUCK1_VOL 0x0A /*[00xx xxxx]0xB 0xC Ìø¹ý*/
+#define ZX234290_REG_ADDR_BUCK1_SLPVOL 0x0D
+
+/* bucks mode */
+#define ZX234290_REG_ADDR_BUCK1_MODE 0x0E /* [xx] NRM [xx] SLP [00 00]*/
+#define ZX234290_REG_ADDR_BUCK23_MODE 0x0F /*[xx]BUCK3 NRM [xx]BUCK3 SLP [xx]BUCK2 NRM [xx]BUCK2 SLP*/
+#define ZX234290_REG_ADDR_BUCK4_MODE 0x11 /* [00 00] [xx] NRM [xx] SLP 0X10Ìø¹ý */
+
+/* ldo normal voltage */
+#define ZX234290_REG_ADDR_LDO12_VOL 0x12 /* [xxxx xxxx] */
+#define ZX234290_REG_ADDR_LDO34_VOL 0x13
+#define ZX234290_REG_ADDR_LDO56_VOL 0x14
+#define ZX234290_REG_ADDR_LDO78_VOL 0x15
+#define ZX234290_REG_ADDR_LDO9_VOL 0x16 /* [xxxx 0000] */
+#define ZX234290_REG_ADDR_LDO10_RTCLDO_VOL 0x17 /* [00 xx]VORTC [xx xx]LDO10*/
+
+
+#define ZX234290_REG_ADDR_BUCK2_VOL 0x1A /* BUCK2 VLOT */
+
+/* ldo sleep voltage */
+#define ZX234290_REG_ADDR_LDO12_SLPVOL 0x18 /* [xx xx]ldo2 [xx xx]ldo1*/
+#define ZX234290_REG_ADDR_LDO3_SLPVOL 0x19 /* [00 00] [xx xx] */
+#define ZX234290_REG_ADDR_LDO78_SLPVOL 0x1B /* [xx xx]ldo8 [xx xx]ldo7*/
+#define ZX234290_REG_ADDR_LDO9_SLPVOL 0x1C /* [xx xx] [00 00] */
+#define ZX234290_REG_ADDR_LDO10_SLPVOL 0x1D /* [00 00] [xx xx] */
+
+/* ldo mode */
+#define ZX234290_REG_ADDR_LDO1234_MODE 0x1E /* [xx][xx][xx][xx]*/
+#define ZX234290_REG_ADDR_LDO5678_MODE 0x1F
+#define ZX234290_REG_ADDR_LDO910_MODE 0x20 /* [00] [xx] [xx] [00] */
+
+/* ldo enable */
+#define ZX234290_REG_ADDR_LDO_EN1 0x21 /* LDO8-1 */
+#define ZX234290_REG_ADDR_LDO_EN2 0x22 /* [xx xx]BUCK4-1, [0xx0]LDO10-9*/
+
+/* adc code */
+#define ZX234290_REG_ADDR_VBATADC_MSB 0x23 /*[xxxx xxxx]*/
+#define ZX234290_REG_ADDR_VBATADC_LSB 0x24 /*[xxxx 0000]*/
+#define ZX234290_REG_ADDR_ADC1_MSB 0x25
+#define ZX234290_REG_ADDR_ADC1_LSB 0x26
+#define ZX234290_REG_ADDR_ADC2_MSB 0x27
+#define ZX234290_REG_ADDR_ADC2_LSB 0x28
+
+/* rtc */
+#define ZX234290_REG_ADDR_RTC_CTRL1 0x30
+#define ZX234290_REG_ADDR_RTC_CTRL2 0x31
+
+/* date and time */
+#define ZX234290_REG_ADDR_SECONDS 0x32
+#define ZX234290_REG_ADDR_MINUTES 0x33
+#define ZX234290_REG_ADDR_HOURS 0x34
+#define ZX234290_REG_ADDR_DAY 0x35
+#define ZX234290_REG_ADDR_WEEK 0x36
+#define ZX234290_REG_ADDR_MONTH 0x37
+#define ZX234290_REG_ADDR_YEAR 0x38
+
+/* alarm */
+#define ZX234290_REG_ADDR_ALARM_MINUTE 0x39
+#define ZX234290_REG_ADDR_ALARM_HOUR 0x3A
+#define ZX234290_REG_ADDR_ALARM_DAY 0x3B
+#define ZX234290_REG_ADDR_ALARM_WEEK 0x3C
+#define ZX234290_REG_ADDR_ALARM_SECOND 0x3D
+
+#define ZX234290_REG_ADDR_TIMER_CTRL 0x3E
+#define ZX234290_REG_ADDR_TIMER_CNT 0x3F
+
+/* enable ldo output discharge resistance */
+#define ZX234290_REG_ADDR_EN_DISCH1 0x40
+#define ZX234290_REG_ADDR_EN_DISCH2 0x41
+
+/* power key control */
+#define ZX234290_REG_ADDR_PWRKEY_CONTROL1 0x42
+#define ZX234290_REG_ADDR_PWRKEY_CONTROL2 0x43
+
+#define ZX234290_REG_ADDR_VERSION 0x44
+
+/*fault status*/
+#define ZX234290_REG_ADDR_BUCK_FAULT_STATUS 0x45
+#define ZX234290_REG_ADDR_LDO_FAULT_STATUS 0x46
+
+#define ZX234290_REG_ADDR_BUCK_INT_MASK 0x47
+#define ZX234290_REG_ADDR_LDO_INT_MASK 0x48
+
+#define ZX234290_REG_ADDR_USER_RESERVED 0x50
+
+#define ZX234290_REG_ADDR_GMT_TESTING 0xf1
+
+#endif
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_pmic_bus.h b/cp/ps/driver/inc/misc/drvs_pmic_bus.h
new file mode 100644
index 0000000..f93ed2b
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_pmic_bus.h
@@ -0,0 +1,33 @@
+/*******************************************************************************
+ * Copyright (C) 2016, ZTE Corporation.
+ *
+ * File Name: drvs_pmic_bus.h
+ * File Mark:
+ * Description: pmic i2c interface
+ * Others:
+ * Version: V1.0
+ * Author: yuxiang
+ * Date: 2016-01-27
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef __DRVS_PMIC_BUS_H_
+#define __DRVS_PMIC_BUS_H_
+
+extern SINT32 zDrvPmic_I2cRead(UINT8 slv_addr, UINT8 reg_addr, UINT8 *reg_val);
+extern SINT32 zDrvPmic_I2cWrite(UINT8 slv_addr, UINT8 reg_addr, UINT8 *reg_val);
+
+extern SINT32 zDrvPmic_I2cInit(VOID);
+extern SINT32 zDrvPmic_GetRegister(UINT8 slv_addr, UINT8 addr, UINT8* data);
+extern SINT32 zDrvPmic_SetRegister(UINT8 slv_addr, UINT8 addr, UINT8 data, UINT8 mask);
+
+extern SINT32 zDrvPmic_I2cInit_PSM(VOID);
+extern SINT32 zDrvPmic_I2cRead_PSM(UINT8 slv_addr, UINT8 reg_addr, UINT8 *reg_val);
+extern SINT32 zDrvPmic_I2cWrite_PSM(UINT8 slv_addr, UINT8 reg_addr, UINT8 *reg_val);
+extern SINT32 zDrvPmic_SetRegister_PSM(UINT8 slv_addr, UINT8 addr, UINT8 data, UINT8 mask);
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_pmic_int.h b/cp/ps/driver/inc/misc/drvs_pmic_int.h
new file mode 100644
index 0000000..8e8eb16
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_pmic_int.h
@@ -0,0 +1,56 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: drvs_pmic_int.h
+ * File Mark:
+ * Description: pmic int interface
+ * Others:
+ * Version: V1.0
+ * Author: yuxiang
+ * Date: 2016-01-27
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef _DRVS_PMIC_INT_H
+#define _DRVS_PMIC_INT_H
+
+/* pmic */
+typedef enum _T_ZDrvPmic_IntId {
+ /* 0x00 */
+ ZX234290_INT_INVALID0 = 0,
+ ZX234290_INT_INVALID1,
+ ZX234290_INT_EOADC, /* xxxx x100 */
+ ZX234290_INT_PWRON_SHORT,
+ ZX234290_INT_PWRON_LONG,
+ ZX234290_INT_PWRON,
+ ZX234290_INT_INVALID2,
+ ZX234290_INT_INVALID3,
+ /* 0x01 */
+ ZX234290_INT_RTC_ALRM = 8,
+ ZX234290_INT_INVALID4,
+ ZX234290_INT_INVALID8,
+ ZX234290_INT_RTC_MIN,
+ ZX234290_INT_RTC_HOUR,
+ ZX234290_INT_INVALID5,
+ ZX234290_INT_INVALID6,
+ ZX234290_INT_INVALID7,
+
+ PMIC_INT_MAX_ID
+} T_ZDrvPmic_IntId;
+
+typedef VOID(*T_PMIC_CALLBACK)(UINT8 reg_val);
+
+SINT32 zDrvPmic_IsrMask(UINT8 nInt);
+SINT32 zDrvPmic_IsrUnMask(UINT8 nInt);
+SINT32 zDrvPmic_IntInit(VOID);
+SINT32 zDrvPmic_RegisterCallback(T_ZDrvPmic_IntId nIntId, T_PMIC_CALLBACK callback);
+SINT32 zDrvPmic_UnRegisterCallback(T_ZDrvPmic_IntId nIntId);
+SINT32 zDrvPmic_CleanIrq(UINT8 slv_addr, UINT8 reg_addr);
+SINT32 zDrvPmic_UnMaskIrq(T_ZDrvPmic_IntId nIntId);
+SINT32 zDrvPmic_MaskIrq(T_ZDrvPmic_IntId nIntId);
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_pmic_regulator.h b/cp/ps/driver/inc/misc/drvs_pmic_regulator.h
new file mode 100644
index 0000000..ce7f009
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_pmic_regulator.h
@@ -0,0 +1,630 @@
+/*******************************************************************************
+ * Copyright (C) 2016, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: V1.0
+ * Author: yuxiang
+ * Date: 2016-01-27
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_PMIC_REGULATOR_H
+#define _DRVS_PMIC_REGULATOR_H
+
+#if defined(_USE_PMIC_ZX234290)
+/* ========================== ¼Ä´æÆ÷ÒÆλ²¿·Ö ======================== */
+#if 1
+/* 0x06 STATUS REG -- STARTUP */
+#define ZX234290_SYSPOR_STATUS_PWRON_STARTUP (0x1 << 0) /* PWR ON button */
+#define ZX234290_SYSPOR_STATUS_RTC_ALARM_STARTUP (0x1 << 1)
+#define ZX234290_SYSPOR_STATUS_PSHOLD_STARTUP (0x1 << 2)
+#define ZX234290_SYSPOR_STATUS_PWRONLLP_STARTUP (0x1 << 3)
+
+
+/* discharger */
+#define ZX234290_DISCHG1_LSB_LSH (0)
+#define ZX234290_DISCHG1_LSB_WID (4)
+
+#define ZX234290_DISCHG1_MSB_LSH (5)
+#define ZX234290_DISCHG1_MSB_WID (2)
+
+#define ZX234290_DISCHG2_LSH (0)
+#define ZX234290_DISCHG2_WID (8)
+
+
+/* BUCK VOLTAGE */
+#define ZX234290_BUCK01_VSEL_LSH (0)
+#define ZX234290_BUCK01_VSEL_WID (6)
+
+/* BUCK SLEEP VOLTAGE */
+#define ZX234290_BUCK01_SLEEP_VSEL_LSH (0)
+#define ZX234290_BUCK01_SLEEP_VSEL_WID (6)
+
+/* BUCKS MODE CTROL */
+#define ZX234290_REGULATOR_MODE_WID (2)
+
+#define ZX234290_BUCK0_SLPMODE_LSH (0)
+#define ZX234290_BUCK0_NRMMODE_LSH (2)
+#define ZX234290_BUCK1_SLPMODE_LSH (4)
+#define ZX234290_BUCK1_NRMMODE_LSH (6) /*[7:6]*/
+#define ZX234290_BUCK2_SLPMODE_LSH (0)
+#define ZX234290_BUCK2_NRMMODE_LSH (2)
+#define ZX234290_BUCK3_SLPMODE_LSH (4)
+#define ZX234290_BUCK3_NRMMODE_LSH (6)
+#define ZX234290_BUCK4_SLPMODE_LSH (0)
+#define ZX234290_BUCK4_NRMMODE_LSH (2)
+
+/* LDO MODE, ONLY SLEEP MODE */
+#define ZX234290_LDO1_SLPMODE_LSH (0)
+#define ZX234290_LDO2_SLPMODE_LSH (2)
+#define ZX234290_LDO3_SLPMODE_LSH (4)
+#define ZX234290_LDO4_SLPMODE_LSH (6)
+#define ZX234290_LDO5_SLPMODE_LSH (0)
+#define ZX234290_LDO6_SLPMODE_LSH (2)
+#define ZX234290_LDO7_SLPMODE_LSH (4)
+#define ZX234290_LDO8_SLPMODE_LSH (6)
+#define ZX234290_LDO9_SLPMODE_LSH (2)
+#define ZX234290_LDO10_SLPMODE_LSH (4)
+//#define ZX234290_LDO11_SLPMODE_LSH (6)
+
+/* LDO VOLTAGE SELECT */
+#define ZX234290_LDO_VSEL_WID (4)
+
+#define ZX234290_LDO1_VSEL_LSH (0) /* [3:0] */
+#define ZX234290_LDO2_VSEL_LSH (4) /* [7:4] */
+#define ZX234290_LDO3_VSEL_LSH (0)
+#define ZX234290_LDO4_VSEL_LSH (4)
+#define ZX234290_LDO5_VSEL_LSH (0)
+#define ZX234290_LDO6_VSEL_LSH (4)
+#define ZX234290_LDO7_VSEL_LSH (0)
+#define ZX234290_LDO8_VSEL_LSH (4)
+#define ZX234290_LDO9_VSEL_LSH (4)
+#define ZX234290_LDO10_VSEL_LSH (0)
+#define ZX234290_LDO11_VSEL_LSH (0) /* [3:0] */
+
+#define ZX234290_VORTC_VSEL_WID (2)
+#define ZX234290_VORTC_VSEL_LSH (4) /* [5][4] */
+#define ZX234290_LDO5_VSEL_WID (2) /* [1][0]*/
+
+
+/* LDO SLEEP VOLTAGE */
+#define ZX234290_BUCK2_VSEL_WID (5)
+
+#define ZX234290_BUCK2_VSEL_LSH (0)
+
+#define ZX234290_LDO1_SLP_VSEL_LSH (0) /* [3:0] */
+#define ZX234290_LDO2_SLP_VSEL_LSH (4) /* [7:4] */
+#define ZX234290_LDO3_SLP_VSEL_LSH (0)
+#define ZX234290_LDO7_SLP_VSEL_LSH (0)
+#define ZX234290_LDO8_SLP_VSEL_LSH (0)
+#define ZX234290_LDO11_SLP_VSEL_LSH (0) /* [3:0] */
+
+/* ENABLE 0x21-0x22 */
+#define ZX234290_LDOS_ON_WID (1)
+
+#define ZX234290_LDO1_ON_LSH (0)
+#define ZX234290_LDO2_ON_LSH (1)
+#define ZX234290_LDO3_ON_LSH (2)
+#define ZX234290_LDO4_ON_LSH (3)
+#define ZX234290_LDO5_ON_LSH (4)
+#define ZX234290_LDO6_ON_LSH (5)
+#define ZX234290_LDO7_ON_LSH (6)
+#define ZX234290_LDO8_ON_LSH (7)
+
+#define ZX234290_LDO9_ON_LSH (1)
+#define ZX234290_LDO10_ON_LSH (2)
+#define ZX234290_BUCK1_ON_LSH (4)
+#define ZX234290_BUCK2_ON_LSH (5)
+#define ZX234290_BUCK3_ON_LSH (6)
+#define ZX234290_BUCK4_ON_LSH (7)
+
+/* LONG PRESSED TIME */
+#define ZX234290_PWRON_TIME_LSH (0)
+#define ZX234290_PWRON_TIME_WID (2)
+#define ZX234290_PWRON_LONGPRESS_EN_LSH (2)
+#define ZX234290_PWRON_LONGPRESS_EN_WID (1)
+#define ZX234290_PWRON_LLP_TODO_LSH (3) /* LLP long long pressed */
+#define ZX234290_PWRON_LLP_TODO_WID (1)
+
+/* sys ctrol 0x07 */
+#define ZX234290_SINK1_EN_LSH (0)
+#define ZX234290_SINK1_EN_WID (1)
+#define ZX234290_SINK2_EN_LSH (1)
+#define ZX234290_SINK2_EN_WID (1)
+#define ZX234290_ADC1_EN_LSH (4)
+#define ZX234290_ADC1_EN_WID (1)
+#define ZX234290_ADC2_EN_LSH (3)
+#define ZX234290_ADC2_EN_WID (1)
+#define ZX234290_ADC_START_LSH (5)
+#define ZX234290_ADC_START_WID (1)
+
+/* 0x08 */
+#define ZX234290_SINK2_CURSEL_LSH (0)
+#define ZX234290_SINK2_CURSEL_WID (4)
+/* 0x09 */
+#define ZX234290_SINK1_CURSEL_LSH (0)
+#define ZX234290_SINK1_CURSEL_WID (4)
+
+#define ZX234290_LDO_RSTERR_LSH (0)
+#define ZX234290_LDO_RSTERR_WID (1)
+
+#endif /* end of ZX234290 */
+
+#define ZX234290_BITFVAL(var, lsh) ( (var) << (lsh) )
+#define ZX234290_BITFMASK(wid, lsh) ( ((1U << (wid)) - 1) << (lsh) )
+#define ZX234290_BITFEXT(var, wid, lsh) ((var & ZX234290_BITFMASK(wid, lsh)) >> (lsh))
+
+/* =========================== ¸÷½á¹¹ÌåµÄ¶¨Òå ========================== */
+
+/* VBA - BUCK1 6bit */
+typedef enum _T_ZDrvZx234290_VbuckA
+{
+ VBUCKA_0_675 = 0x00,
+ VBUCKA_0_700 = 0x02,
+ VBUCKA_0_750 = 0x06,
+ VBUCKA_0_800 = 0x0a,
+ VBUCKA_0_850 = 0x0e,
+ VBUCKA_0_900 = 0x12,/*default*/
+ VBUCKA_0_950 = 0x16,
+ VBUCKA_1_000 = 0x1a,
+ VBUCKA_1_050 = 0x1e,
+ VBUCKA_1_100 = 0x22,
+ VBUCKA_1_150 = 0x26,
+ VBUCKA_1_200 = 0x2a,
+ VBUCKA_1_250 = 0x2e,
+
+ VBUCKA_MAX
+
+}T_ZDrvZx234290_VbuckA;
+
+/* VBC - BUCK2 */
+typedef enum _T_ZDrvZx234290_VbuckC
+{
+ VBUCKC_0_850 = 0x00,
+ VBUCKC_0_900 = 0x02,
+ VBUCKC_0_950 = 0x04,
+ VBUCKC_1_000 = 0x06,
+ VBUCKC_1_050 = 0x08,
+ VBUCKC_1_100 = 0x0a,
+ VBUCKC_1_150 = 0x0c,
+ VBUCKC_1_200 = 0x0e,/*default*/
+ VBUCKC_1_250 = 0x10,
+ VBUCKC_1_300 = 0x12,
+ VBUCKC_1_350 = 0x14,
+ VBUCKC_1_400 = 0x16,
+ VBUCKC_1_450 = 0x18,
+ VBUCKC_1_500 = 0x1a,
+ VBUCKC_1_550 = 0x1c,
+ VBUCKC_1_600 = 0x1e,
+
+ VBUCKC_MAX
+
+}T_ZDrvZx234290_VbuckC;
+
+/* VLA - ldo1/9/10 */
+typedef enum _T_ZDrvZx234290_VldoA
+{
+ VLDOA_0_725 = 0,
+ VLDOA_0_750 = 1,
+ VLDOA_0_775 = 2,
+ VLDOA_0_800 = 3,
+ VLDOA_0_825 = 4,
+ VLDOA_0_850 = 5,
+ VLDOA_0_875 = 6,
+ VLDOA_0_900 = 7,
+ VLDOA_0_925 = 8,
+ VLDOA_0_950 = 9,
+ VLDOA_0_975 = 10,
+ VLDOA_1_000 = 11,
+ VLDOA_1_025 = 12,
+ VLDOA_1_050 = 13,
+ VLDOA_1_075 = 14,
+ VLDOA_1_100 = 15,
+
+ VLDOA_MAX
+
+}T_ZDrvZx234290_VldoA;
+
+/* VLB - ldo5 2bit */
+typedef enum _T_ZDrvZx234290_VldoB
+{
+ VLDOB_3_300 = 0,
+ VLDOB_3_150 = 1,
+ VLDOB_3_000 = 2,
+ VLDOB_1_800 = 3, /* 11 */
+
+ VLDOB_MAX
+
+}T_ZDrvZx234290_VldoB;
+
+/* VLC - ldo2/ldo3 */
+typedef enum _T_ZDrvZx234290_VldoC
+{
+ VLDOC_0_750 = 0,
+ VLDOC_0_800 = 1,
+ VLDOC_0_850 = 2,
+ VLDOC_0_900 = 3,
+ VLDOC_0_950 = 4,
+ VLDOC_1_000 = 5,
+ VLDOC_1_050 = 6,
+ VLDOC_1_100 = 7,
+ VLDOC_1_200 = 8,
+ VLDOC_1_500 = 9,
+ VLDOC_1_800 = 10,
+ VLDOC_2_000 = 11,
+ VLDOC_2_500 = 12,
+ VLDOC_2_800 = 13,
+ VLDOC_3_000 = 14,
+ VLDOC_3_300 = 15,
+
+ VLDOC_MAX
+
+}T_ZDrvZx234290_VldoC;
+
+/* VLD - ldo4/6/7/8 */
+typedef enum _T_ZDrvZx234290_VldoD
+{
+ VLDOD_1_400 = 0,
+ VLDOD_1_500 = 1,
+ VLDOD_1_600 = 2,
+ VLDOD_1_800 = 3,
+ VLDOD_1_850 = 4,
+ VLDOD_2_000 = 5,
+ VLDOD_2_050 = 6,
+ VLDOD_2_500 = 7,
+ VLDOD_2_550 = 8,
+ VLDOD_2_700 = 9,
+ VLDOD_2_750 = 10,
+ VLDOD_2_800 = 11,
+ VLDOD_2_850 = 12,
+ VLDOD_2_900 = 13,
+ VLDOD_2_950 = 14,
+ VLDOD_3_000 = 15,
+
+ VLDOD_MAX
+
+}T_ZDrvZx234290_VldoD;
+
+/* VORTC 2bit */
+typedef enum _T_ZDrvZx234290_VldoE
+{
+ VLDOE_1_800 = 0,
+ VLDOE_2_500 = 1,
+ VLDOE_3_000 = 2,
+ VLDOE_3_300 = 3, /* 11 */
+
+ VLDOE_MAX
+
+}T_ZDrvZx234290_VldoE;
+
+
+/* BUCK3/4 EXTERNAL ADJUSTABLE */
+
+typedef enum _T_ZDrvZx234290_LDO_ENABLE
+{
+ LDO_ENABLE_OFF = 0, /* 00 */
+ LDO_ENABLE_ON = 1, /* 10 */
+
+ LDO_AVTICE_MAX
+}T_ZDrvZx234290_LDO_ENABLE;
+
+typedef enum _T_ZDrvZx234290_LLP_ENABLE
+{
+ LLP_DISBALE = 0, /* 00 */
+ LLP_ENABLE = 1, /* 10 */
+
+ LLP_ENABLE_MAX
+}T_ZDrvZx234290_LLP_ENABLE;
+
+typedef enum _T_ZDrvZx234290_LLP_TODO
+{
+ LLP_SHUTDOWN = 0, /* 00 */
+ LLP_RESTART = 1, /* 10 */
+
+ LLP_TODO_MAX
+}T_ZDrvZx234290_LLP_TODO;
+
+typedef enum _T_ZDrvZx234290_LP_TIME
+{
+ LP_TIME_1S = 0,
+ LP_TIME_2S ,
+ LP_TIME_3S ,
+ LP_TIME_4S ,
+
+ LP_TIME_MAX
+}T_ZDrvZx234290_LP_TIME;
+typedef enum _T_ZDrvZx234290_TIME_IT
+{
+ LLP_DLY_128MS = 0,
+ LLP_DLY_500MS ,
+ LLP_DLY_1000MS ,
+ LLP_DLY_1500MS ,
+
+ LLP_DLY_MAX
+}T_ZDrvZx234290_TIME_IT;
+
+typedef enum _T_ZDrvZx234290_LLP_TIME
+{
+ LLP_TIME_6S = 0,
+ LLP_TIME_7S ,
+ LLP_TIME_8S ,
+ LLP_TIME_10S ,
+
+ LLP_TIME_MAX
+}T_ZDrvZx234290_LLP_TIME;
+
+
+/*
+ ¹ØÓÚ BUCKSµÄģʽ£¬·ÖΪÕý³£Ä£Ê½Óë˯Ãßģʽ£¬ Õý³£Ä£Ê½Ö»¹Ø×¢PFM/PWM£¬²»¹Ø×¢¿ª¹Ø¡£
+ ˯Ãßģʽ¹Ø×¢PFM/PWM/ECO/OFF/NRM£¬Ó¦¸Ã½âÊÍΪ ˯ÃßģʽµÄ״̬²»½ö¹Ø×¢PWM/PFM£¬
+ ¶øÇÒ¹Ø×¢´ò¿ª¹Ø±Õ£¬³ýÁËOFF£¬ÆäËû¶¼ÊÇÔÚ¿ª×ŵÄÇé¿öϵÄģʽ£»¶øĬÈÏ¿ªµÄÇé¿öÔòÊÇ
+ NRMMODE£¬µçѹÓÃ˯Ãßµçѹ£»
+ ¶øLDOSµÄ˯Ãßģʽ£¬Ò»ÑùÓëÕý³£Ä£Ê½²»Ïà¸É¡£ÆäÒ²ÓÐNRM/ECO/OFFÕ⼸ÖÖ״̬
+*/
+
+/* BUCK1/2/3/4 NORMAL MODE */
+typedef enum _T_ZDrvZx234290_BUCK_NRMMODE
+{
+ BUCK_NRM_AUTO_WITH_ECO = 0, /* 00/01 AUTO PWM/PSM ECO */
+ BUCK_NRM_FORCE_PWM = 2, /* 10 FORCE PWM */
+ BUCK_NRM_AUTO_WITHOUT_ECO = 3, /* 00/01 AUTO PWM/PSM ECO */
+ BUCK_NRMMODE_MAX
+}T_ZDrvZx234290_BUCK_NRMMODE;
+
+/* BUCK1 SLPMODE */
+typedef enum _T_ZDrvZx234290_BUCK1_SLPMODE
+{
+ BUCK1_SLP_AUTO_WITHOUT_ECO = 0, /* 00/11 AUTO PWM/PFM */
+ BUCK1_SLP_AUTO_ECO = 1, /*BUCK1_SLP_AUTO_ECO_VOLT output voltage configred by FBDC1[5:0]*/
+ BUCK1_SLP_AUTO_ECO_SLP = 2, /* output voltage configred by FBDC1_SLP[5:0]*/
+ BUCK1_SLP_SHUTDOWN = 3, /* 11 OFF */
+ BUCK1_SLPMODE_MAX
+}T_ZDrvZx234290_BUCK1_SLPMODE;
+
+/* BUCK2/3/4 SLPMODE */
+typedef enum _T_ZDrvZx234290_BUCK234_SLPMODE
+{
+ BUCK234_SLP_AUTO_WITHOUT_ECO = 0, /* 00 AUTO PWM/PFM without eco*/
+ BUCK234_SLP_ECO_WITH_ECO = 1, /* 01Óë10¾ùÊÇ ECO */
+ BUCK234_SLP_SHUTDOWN = 3, /* 11 OFF */
+
+ BUCK234_SLPMODE_MAX
+}T_ZDrvZx234290_BUCK234_SLPMODE;
+
+/* LDO1/2/3/7/8/9/10 SLPMODE */
+typedef enum _T_ZDrvZx234290_LDOA_SLPMODE
+{
+ LDOA_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */
+ LDOA_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */
+ LDOA_SLP_ECO_VOLT_SLP = 2, /* VOLDOx_SLP[3:0] */
+ LDOA_SLP_SHUTDOWN = 3, /* 11 OFF */
+ LDOA_SLPMODE_MAX
+}T_ZDrvZx234290_LDOA_SLPMODE;
+
+/* LDO4/5/6/ SLPMODE */
+typedef enum _T_ZDrvZx234290_LDOB_SLPMODE
+{
+ LDOB_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */
+ LDOB_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */
+ LDOB_SLP_NRM_MODE_VOLT = 2, /* VOLDOx[3:0] */
+ LDOB_SLP_SHUTDOWN = 3, /* 11 OFF */
+ LDOB_SLPMODE_MAX
+}T_ZDrvZx234290_LDOB_SLPMODE;
+
+#endif
+
+typedef enum _T_ZDrvZx234290_LdoDischarger
+{
+ DISCHARGER_LDO_9 = 0,
+ DISCHARGER_LDO_10,
+ DISCHARGER_LDO_X, /*not support*/
+ DISCHARGER_BUCK_4,
+ DISCHARGER_BUCK_3,
+ DISCHARGER_BUCK_2,
+ DISCHARGER_BUCK_1,
+ DISCHARGER_BUCK_X, /*not support*/
+
+ DISCHARGER_LDO_1,
+ DISCHARGER_LDO_2,
+ DISCHARGER_LDO_3,
+ DISCHARGER_LDO_4,
+ DISCHARGER_LDO_5,
+ DISCHARGER_LDO_6,
+ DISCHARGER_LDO_7,
+ DISCHARGER_LDO_8,
+
+ DISCHARGER_MAX
+}T_ZDrvZx234290_LdoDischarger;
+
+typedef enum _T_ZDrvZx234290_DISCHARGER_ENABLE
+{
+ DISCHARGER_DISBALE = 0, /* 00 */
+ DISCHARGER_ENABLE = 1, /* 10 */
+
+ DISCHARGER_ENABLE_MAX
+}T_ZDrvZx234290_DISCHARGER_ENABLE;
+
+typedef enum _T_ZDrvZx234290_LdoList
+{
+ LDOLIST_BUCK_1 = 0,
+ LDOLIST_BUCK_2,
+ LDOLIST_BUCK_3,
+ LDOLIST_BUCK_4,
+ LDOLIST_LDO_1,
+ LDOLIST_LDO_2,
+ LDOLIST_LDO_3,
+
+ LDOLIST_LDO_4,
+ LDOLIST_LDO_5,
+ LDOLIST_LDO_6,//default off
+ LDOLIST_LDO_7,
+ LDOLIST_LDO_8,
+ LDOLIST_LDO_9,//default off
+ LDOLIST_LDO_10,
+ LDOLIST_LDO_RTC,
+
+ LDOLIST_MAX
+}T_ZDrvZx234290_LdoList;
+
+
+typedef enum _T_ZDrvZx234290_ResetType
+{
+#if 0
+ ZX234290_USER_RST_UNDEFINE = 0,
+ ZX234290_USER_RST_TO_NORMAL = 1,
+ ZX234290_USER_RST_TO_CHARGER = 2,
+ ZX234290_USER_RST_TO_ALARM = 3,
+ ZX234290_USER_RST_TO_EXCEPT = 4,
+#else
+ ZX234290_USER_RST_TO_NORMAL = 0,
+ ZX234290_USER_RST_TO_CHARGER = 1,
+ ZX234290_USER_RST_TO_ALARM = 2,
+ ZX234290_USER_RST_UNDEFINE = 3,
+ /* ZX234290_USER_RST_TO_EXCEPT = 4, */
+#endif
+
+ ZX234290_USER_RST_MAX
+}T_ZDrvZx234290_ResetType;
+
+
+/* ----------------------- º¯Êý¶¨Òå -------------------------------- */
+#if defined(_USE_PMIC_ZX234290)
+SINT32 Zx234290_SetTllpToDo(T_ZDrvZx234290_LLP_TODO enable);
+SINT32 Zx234290_SetLlpEnable(T_ZDrvZx234290_LLP_ENABLE enable);
+SINT32 Zx234290_SetLpTime(T_ZDrvZx234290_LP_TIME time);
+SINT32 Zx234290_SetRestartDly(T_ZDrvZx234290_TIME_IT time);
+SINT32 Zx234290_SetLlpTime(T_ZDrvZx234290_LLP_TIME time);
+int Zx234290_SetUserReg_PSM(UINT8 data);
+
+
+SINT32 Zx234290_SetDischarger(T_ZDrvZx234290_LdoDischarger ldo, T_ZDrvZx234290_DISCHARGER_ENABLE enable);
+SINT32 Zx234290_PrintLdoOnoff(T_ZDrvZx234290_LdoList LdoId, UINT8 status);
+SINT32 Zx234290_PrintLdoVol(T_ZDrvZx234290_LdoList LdoId, UINT8 vol);
+SINT32 Zx234290_PrintLdoSleep(T_ZDrvZx234290_LdoList LdoId, UINT8 status);
+
+
+/* regulator */
+SINT32 Zx234290_SetVbuck1Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVbuck1Onoff(VOID);
+SINT32 Zx234290_SetVbuck1(T_ZDrvZx234290_VbuckA vol);
+T_ZDrvZx234290_VbuckA Zx234290_GetVbuck1(VOID);
+SINT32 Zx234290_SetBUCK1SleepMode(T_ZDrvZx234290_BUCK1_SLPMODE status);
+T_ZDrvZx234290_BUCK1_SLPMODE Zx234290_GetBUCK1SleepMode(VOID);
+SINT32 Zx234290_SetVbuck1SLPV(T_ZDrvZx234290_VbuckA vol);
+
+SINT32 Zx234290_SetVbuck2Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVbuck2Onoff(VOID);
+SINT32 Zx234290_SetVbuck2(T_ZDrvZx234290_VbuckC vol);
+T_ZDrvZx234290_VbuckC Zx234290_GetVbuck2(VOID);
+SINT32 Zx234290_SetBUCK2SleepMode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+T_ZDrvZx234290_BUCK234_SLPMODE Zx234290_GetBUCK2SleepMode(VOID);
+
+SINT32 Zx234290_SetVbuck3Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVbuck3Onoff(VOID);
+SINT32 Zx234290_SetVbuck3ActiveMode(T_ZDrvZx234290_BUCK_NRMMODE status);
+SINT32 Zx234290_SetBUCK3SleepMode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+T_ZDrvZx234290_BUCK234_SLPMODE Zx234290_GetBUCK3SleepMode(VOID);
+
+SINT32 Zx234290_SetVbuck4Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVbuck4Onoff(VOID);
+SINT32 Zx234290_SetVbuck4ActiveMode(T_ZDrvZx234290_BUCK_NRMMODE status);
+SINT32 Zx234290_SetBUCK4SleepMode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+T_ZDrvZx234290_BUCK234_SLPMODE Zx234290_GetBUCK4SleepMode(VOID);
+
+SINT32 Zx234290_SetVldo1Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVldo1Onoff(VOID);
+SINT32 Zx234290_SetVldo1(T_ZDrvZx234290_VldoA vol);
+T_ZDrvZx234290_VldoA Zx234290_GetVldo1(VOID);
+SINT32 Zx234290_SetLDO1SleepMode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE Zx234290_GetLDO1SleepMode(VOID);
+
+SINT32 Zx234290_SetVldo2Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVldo2Onoff(VOID);
+SINT32 Zx234290_SetVldo2(T_ZDrvZx234290_VldoC vol);
+T_ZDrvZx234290_VldoC Zx234290_GetVldo2(VOID);
+SINT32 Zx234290_SetLDO2SleepMode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE Zx234290_GetLDO2SleepMode(VOID);
+
+SINT32 Zx234290_SetVldo3Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVldo3Onoff(VOID);
+SINT32 Zx234290_SetVldo3(T_ZDrvZx234290_VldoC vol);
+T_ZDrvZx234290_VldoC Zx234290_GetVldo3(VOID);
+SINT32 Zx234290_SetLDO3SleepMode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE Zx234290_GetLDO3SleepMode(VOID);
+
+SINT32 Zx234290_SetVldo4Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVldo4Onoff(VOID);
+SINT32 Zx234290_SetVldo4(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD Zx234290_GetVldo4(VOID);
+SINT32 Zx234290_SetLDO4SleepMode(T_ZDrvZx234290_LDOB_SLPMODE status);
+T_ZDrvZx234290_LDOB_SLPMODE Zx234290_GetLDO4SleepMode(VOID);
+SINT32 Zx234290_SetLDO4SleepMode_PSM(T_ZDrvZx234290_LDOB_SLPMODE status);
+
+SINT32 Zx234290_SetVldo5Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVldo5Onoff(VOID);
+SINT32 Zx234290_SetVldo5(T_ZDrvZx234290_VldoB vol);
+T_ZDrvZx234290_VldoB Zx234290_GetVldo5(VOID);
+extern SINT32 Zx234290_SetLDO5SleepMode(T_ZDrvZx234290_LDOB_SLPMODE status);
+extern T_ZDrvZx234290_LDOB_SLPMODE Zx234290_GetLDO5SleepMode(VOID);
+
+SINT32 Zx234290_SetVldo6Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVldo6Onoff(VOID);
+SINT32 Zx234290_SetVldo6(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD Zx234290_GetVldo6(VOID);
+SINT32 Zx234290_SetLDO6SleepMode(T_ZDrvZx234290_LDOB_SLPMODE status);
+T_ZDrvZx234290_LDOB_SLPMODE Zx234290_GetLDO6SleepMode(VOID);
+
+SINT32 Zx234290_SetVldo7Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVldo7Onoff(VOID);
+SINT32 Zx234290_SetVldo7(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD Zx234290_GetVldo7(VOID);
+SINT32 Zx234290_SetLDO7SleepMode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE Zx234290_GetLDO7SleepMode(VOID);
+
+SINT32 Zx234290_SetVldo8Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVldo8Onoff(VOID);
+SINT32 Zx234290_SetVldo8(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD Zx234290_GetVldo8(VOID);
+SINT32 Zx234290_SetLDO8SleepMode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE Zx234290_GetLDO8SleepMode(VOID);
+
+SINT32 Zx234290_SetVldo9Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVldo9Onoff(VOID);
+SINT32 Zx234290_SetVldo9(T_ZDrvZx234290_VldoA vol);
+T_ZDrvZx234290_VldoA Zx234290_GetVldo9(VOID);
+SINT32 Zx234290_SetLDO9SleepMode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE Zx234290_GetLDO9SleepMode(VOID);
+
+SINT32 Zx234290_SetVldo10Onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE Zx234290_GetVldo10Onoff(VOID);
+SINT32 Zx234290_SetVldo10(T_ZDrvZx234290_VldoA vol);
+T_ZDrvZx234290_VldoA Zx234290_GetVldo10(VOID);
+extern SINT32 Zx234290_SetLDO10SleepMode(T_ZDrvZx234290_LDOA_SLPMODE status);
+extern T_ZDrvZx234290_LDOA_SLPMODE Zx234290_GetLDO10SleepMode(VOID);
+
+SINT32 Zx234290_SetVortc(T_ZDrvZx234290_VldoE vol);
+T_ZDrvZx234290_VldoE Zx234290_GetVortc(VOID);
+
+SINT32 Zx234290_SetVldo1Onoff_Psm(T_ZDrvZx234290_LDO_ENABLE status);
+SINT32 Zx234290_SetVldo5Onoff_Psm(T_ZDrvZx234290_LDO_ENABLE status);
+SINT32 Zx234290_SetLDO1SleepMode_Psm(T_ZDrvZx234290_LDOA_SLPMODE status);
+SINT32 Zx234290_SetLDO5SleepMode_Psm(T_ZDrvZx234290_LDOB_SLPMODE status);
+int Zx234290_SetResetFalg(T_ZDrvZx234290_ResetType rsttype);
+int Zx234290_SetResetFlag_Psm(T_ZDrvZx234290_ResetType rsttype);
+SINT32 zDrvZx234290_LdoRstErr(VOID);
+SINT32 Zx234290_getPoweronStatus(void);
+SINT32 Zx234290_getPoweronStatus_PSM(void);
+SINT32 Zx234290_setSoftOn(bool SoftOn);
+SINT32 Zx234290_setSoftOn_PSM(bool SoftOn);
+#endif
+
+#endif /*_DRVS_PMIC_REGULATOR_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_pmic_rtc.h b/cp/ps/driver/inc/misc/drvs_pmic_rtc.h
new file mode 100644
index 0000000..65f620b
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_pmic_rtc.h
@@ -0,0 +1,203 @@
+/*******************************************************************************
+ * Copyright (C) 2010, ZTE Corporation.
+ *
+ * File Name: drvs_pmic_rtc.h
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: V1.0
+ * Author: yuxiang
+ * Date: 2016-01-27
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_PMIC_RTC_H
+#define _DRVS_PMIC_RTC_H
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "drvs_io_rtc.h"
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+#if defined(_USE_PMIC_ZX234290)
+
+#define ZX234290_RTC_ALARM_INT_EN_LSH (1)
+#define ZX234290_RTC_ALARM_INT_EN_WID (1)
+
+#define ZX234290_RTC_TIMER_INT_EN_LSH (0)
+#define ZX234290_RTC_TIMER_INT_EN_WID (1)
+
+
+ /*RTC TIME SECONDS MIN HOU DAY MON YEAR WEEKDAY*/
+#define ZX234290_RTC_TIME_SECONDS_LSH (0)
+#define ZX234290_RTC_TIME_SECONDS_WID (7)
+
+#define ZX234290_RTC_TIME_MINUTES_LSH (0)
+#define ZX234290_RTC_TIME_MINUTES_WID (7)
+
+#define ZX234290_RTC_TIME_HOURS_LSH (0)
+#define ZX234290_RTC_TIME_HOURS_WID (6)
+
+#define ZX234290_RTC_TIME_DAYS_LSH (0)
+#define ZX234290_RTC_TIME_DAYS_WID (6)
+
+#define ZX234290_RTC_TIME_MONTHS_LSH (0)
+#define ZX234290_RTC_TIME_MONTHS_WID (5)
+#define ZX234290_RTC_TIME_CENTURY_LSH (7)
+#define ZX234290_RTC_TIME_CENTURY_WID (1)
+
+#define ZX234290_RTC_TIME_YEAR_LSH (0)
+#define ZX234290_RTC_TIME_YEAR_WID (7)
+
+#define ZX234290_RTC_TIME_WEEKDAY_LSH (0)
+#define ZX234290_RTC_TIME_WEEKDAY_WID (3)
+
+ /*RTC ALARM MIN HOU DAY WEEKDAY*/
+#define ZX234290_RTC_AlARM_MINUTES_LSH (0)
+#define ZX234290_RTC_AlARM_MINUTES_WID (7)
+
+#define ZX234290_RTC_AlARM_HOURS_LSH (0)
+#define ZX234290_RTC_AlARM_HOURS_WID (6)
+
+#define ZX234290_RTC_AlARM_DAYS_LSH (0)
+#define ZX234290_RTC_AlARM_DAYS_WID (6)
+
+#define ZX234290_RTC_AlARM_WEEKDAY_LSH (0)
+#define ZX234290_RTC_AlARM_WEEKDAY_WID (3)
+
+#define ZX234290_RTC_AlARM_SECOND_LSH (0)
+#define ZX234290_RTC_AlARM_SECOND_WID (7)
+ /*RTC ALARM Enable*/
+#define ZX234290_RTC_AlARM_ACTIVATED_LSH (7)
+#define ZX234290_RTC_AlARM_ACTIVATED_WID (1)
+
+ /* RTC TIMER ENABLE */
+#define ZX234290_RTC_TIMER_EN_LSH (7)
+#define ZX234290_RTC_TIMER_EN_WID (1)
+
+#define ZX234290_RTC_TIMER_TD_LSH (0)
+#define ZX234290_RTC_TIMER_TD_WID (2)
+
+#define ZX234290_RTC_TIMER_CNT_LSH (0)
+#define ZX234290_RTC_TIMER_CNT_WID (8)
+
+ /*RTC MASK IRQ */
+#define ZX234290_RTC_MASK_ALARM_LSH (0)
+#define ZX234290_RTC_MASK_ALARM_WID (1)
+
+#define ZX234290_RTC_MASK_HOUR_LSH (4)
+#define ZX234290_RTC_MASK_HOUR_WID (1)
+
+#define ZX234290_RTC_MASK_MIN_LSH (3)
+#define ZX234290_RTC_MASK_MIN_WID (1)
+ /*AF/TF alarm flag/timer flag*/
+#define ZX234290_RTC_AF_LSH (3)
+#define ZX234290_RTC_AF_WID (1)
+
+#define ZX234290_RTC_TF_LSH (2)
+#define ZX234290_RTC_TF_WID (1)
+
+#define ZX234290_BCD2DEC(var) ((((var&0xF0)>>4)*10)+(var&0x0F))
+#define ZX234290_DEC2BCD(var) (((var/10)<<4)+(var%10))
+
+
+typedef enum _T_ZDrvZx234290_TimerCount
+{
+ TIMER_COUNT_4096 = 0,
+ TIMER_COUNT_64 = 1, /* 64 DEFAULT */
+ TIMER_COUNT_1 = 2, /* 1 */
+ TIMER_COUNT_1_60 = 3, /* 1/60 */
+
+ TIMER_COUNT_MAX
+}T_ZDrvZx234290_TimerCount;
+
+
+/**************************************************************************
+ * Types *
+ **************************************************************************/
+
+typedef struct
+{
+ UINT8 mday; /* day of the month - [1,31] */
+ UINT8 mon; /* months - [01,12] */
+ UINT8 wday; /*days in a week - [1,7] NULL when input*/
+ UINT16 year; /* years - [0000,9999] */
+}T_ZDrvRtc_Date;
+
+typedef struct
+{
+ BOOL PM_flag; /* if 12 hour flag = TRUE TRUE->PM ; FALSE->AM */
+ BOOL mode_12_hour; /* TRUE->12 hour mode ; FALSE-> 24 hour mode */ /*20080227*/
+ UINT8 sec; /* seconds after the minute - [0,59] */
+ UINT8 min; /* minutes after the hour - [0,59] */
+ UINT8 hour; /* hours after the midnight - [0,23] */
+}T_ZDrvRtc_Time;
+
+typedef enum
+{
+ MON = 1,
+ TUES,
+ WED,
+ THURS,
+ FRI,
+ SAT,
+ SUN,
+
+ MAX_RTC_WEEKDAY
+} T_ZDrvRtc_WeekDay;
+
+typedef enum _T_ZDrvRtc_TimerUnit
+{
+ RTC_TIMER_COUNT_4096 = 0, /* 1/4096 s*/
+ RTC_TIMER_COUNT_64 = 1, /* 64 DEFAULT ,1/64 s*/
+ RTC_TIMER_COUNT_1 = 2, /* 1 ,s*/
+ RTC_TIMER_COUNT_1_60 = 3, /* 1/60 ,min*/
+
+ RTC_TIMER_COUNT_MAX
+}T_ZDrvRtc_TimerUnit;
+
+typedef struct _T_ZDrvRtc_Timer
+{
+ UINT8 iCount;
+ T_ZDrvRtc_TimerUnit unit;
+}T_ZDrvRtc_Timer;
+
+
+/*for appstart.c*/
+
+typedef enum
+{
+ RTC_12_HOUR_MODE,
+ RTC_24_HOUR_MODE,
+
+ MAX_RTC_HOUR_MODE
+} T_ZDrvRtc_HourMode;
+
+#endif
+
+/****************************************************************************
+* Types
+****************************************************************************/
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+
+#endif/*_DRVS_PMIC_RTC_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_pmmanager.h b/cp/ps/driver/inc/misc/drvs_pmmanager.h
new file mode 100644
index 0000000..9b7e410
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_pmmanager.h
@@ -0,0 +1,71 @@
+/*********************************************************************
+ Copyright 2007 by ZTE Corporation.
+ *
+ * FileName:: hal_pmmanager.c
+ * File Mark:
+* Description: This file contains the hardware interface for rtc driver
+* Others:
+* Version: v0.5
+* Author: zhangyingjun
+* Date: 2009-02-23
+
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+* History 2:
+**********************************************************************/
+
+/**************************************************************************
+ * Include files *
+ **************************************************************************/
+
+#ifndef _HAL_POWERON_DEF_H
+#define _HAL_POWERON_DEF_H
+
+#define OS_FLASH_KPD_POWERON_FLAG 0x163FFFFC
+#define OS_FLASH_ALARM_POWERON_FLAG 0x163FFFFD
+#define OS_FLASH_CHARGER_POWERON_FLAG 0x163FFFFE
+#define OS_FLASH_SOFTRESET_FLAG 0x163FFFFF /*use check softreset power on */
+
+#define DPRAM_TRACE_LOADING_FLAG 0x40000000 + 0x1400
+#define TRACE_LOADING_FLAG_VALUE 0xAABB
+
+#define SOFTRESET_POWRON_FLAG_VALUE 0xAA
+#define KPD_POWER_FLAG_VALUE 0xBB
+#define ALARM_POWER_FLAG_VALUE 0xCC
+#define CHARGER_POWER_FLAG_VALUE 0xDD
+typedef enum
+{
+ POWER_ON_STATE_NORMAL = 0,
+ POWER_ON_STATE_CLOCK = 1,
+ POWER_ON_STATE_CHARGING = 2,
+ POWER_ON_STATE_SOFTRESET = 3,
+ POWER_ON_STATE_INVALID = 4,
+ POWER_ON_STATE_INIT = 5
+}T_POWER_ON_State;
+
+typedef enum
+{
+ POWER_ON_EVENT_NORMAL = 0,
+ POWER_ON_EVENT_CLOCK = 1,
+ POWER_ON_EVENT_CHARGING = 2,
+ POWER_ON_EVENT_SOFTRESET =3,
+ POWER_ON_EVENT_INVALID = 4,
+ POWER_ON_EVENT_INIT = 5
+}T_POWER_ON_EVENT;
+
+typedef struct
+{
+ T_POWER_ON_State normal_Power_on_CurrentState;
+ T_POWER_ON_State rtc_Power_on_CurrentState;
+ T_POWER_ON_State charger_Power_on_CurrentState;
+ T_POWER_ON_State softreset_Power_on_CurrentState;
+}
+T_POWER_ON_CURRENT_STATE;
+
+SINT32 zDrvPmmanager_Initiate(VOID);
+//T_POWER_ON_CURRENT_STATE hal_sysm_power_on_state_get(VOID);
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_pow.h b/cp/ps/driver/inc/misc/drvs_pow.h
new file mode 100644
index 0000000..0263efd
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_pow.h
@@ -0,0 +1,458 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: drvs_pow.h
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: 1.3.0
+ * Author: wangxia
+ * Date: 2009-6-10
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_POW_H
+#define _DRVS_POW_H
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+/****************************************************************************
+* macro define
+****************************************************************************/
+//#define _USE_PSM
+//#define _USE_PSM_DEBUG
+
+#ifdef _OS_LINUX
+#define PSM_CPU_CP 0
+#else
+#define PSM_CPU_CP 1
+#endif
+
+#ifdef _CPU_DFS_ON
+#define PSM_CPU_DFS 1
+#else
+#define PSM_CPU_DFS 0
+#endif
+
+#ifdef _AXI_DFS_ON
+#define PSM_AXI_DFS 1
+#else
+#define PSM_AXI_DFS 0
+#endif
+
+#ifdef _AXI_DFS_ON_HW
+#define PSM_AXI_DFS_HW 1 //axi change by hw
+#else
+#define PSM_AXI_DFS_HW 0
+#endif
+
+#ifdef _DDR_DFS_ON
+#define PSM_DDR_DFS 1
+ #if PSM_DDR_DFS
+ #define PSM_DDR_DFS_HW 1 //ddr change by hw
+ #endif
+#else
+#define PSM_DDR_DFS 0
+#define PSM_DDR_DFS_HW 0
+#endif
+
+#ifdef _VCORE_DVS_ON
+#define PSM_VCORE_DVS 1
+#else
+#define PSM_VCORE_DVS 0
+#endif
+
+
+#define POW_IDLE_TIMEOUT_MS (1)
+#define POW_IDLE_TIMEOUT_TCPIP (5*1000*POW_IDLE_TIMEOUT_MS)
+
+#define ICP2M0_PSM_AT_CMD_VALID 0x49435001
+#define ICP2M0_PSM_AXI_DFS 0x49435002
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+
+/****************************************************************************
+* Types
+****************************************************************************/
+typedef enum
+{
+/*PS wake int dis reg1 begin*/
+ PS_RM_INT_DIS=1,
+ UART0_RXD_INT_DIS=2,
+ SD0_DATA1_INT_DIS=3,
+ PS_TIMER1_INT_DIS,
+ PS_TIMER2_INT_DIS,
+ ICP_AP2PS_INT_DIS,
+ USB2_POWERDWN_UP_INT_DIS,
+ USB2_POWERDWN_DOWN_INT_DIS,
+ HSIC_POWERDWN_UP_INT_DIS,
+ HSIC_POWERDWN_DOWN_INT_DIS,
+ ICP_PHY2PS_INT_DIS,
+ ICP_M02PS_INT_DIS,
+ RM_RTC_ALARM_INT_DIS,
+ RM_RTC_TIMER_INT_DIS,
+ RM_KEYPAD_INT_DIS,
+ SD1_DATA1_INT_DIS,
+ UART0_CTS_INT_DIS,
+ SPCU_PW_INT_DIS,
+ GSM_LPM_INT_DIS,
+ TD_LPM_TIMER_IND3_DIS=24,
+ TD_LPM_TIMER_IND4_DIS,
+ LTE_LPM_TIMER_IND2_DIS,
+ LTE_LPM_TIMER_IND4_DIS,
+ LTE_LPM_TIMER_IND5_DIS,
+ WD_LPM_TIMER_IND3_DIS,
+ WD_LPM_TIMER_IND4_DIS,
+ FRM_INT_ARM_32K_DIS=31,
+/*PS wake int dis reg1 end*/
+/*PS wake int dis reg2 begin*/
+ EXTERNAL_INT0_DIS=34,
+ EXTERNAL_INT1_DIS,
+ EXTERNAL_INT2_DIS,
+ EXTERNAL_INT3_DIS,
+ EXTERNAL_INT4_DIS,
+ EXTERNAL_INT5_DIS,
+ EXTERNAL_INT6_DIS,
+ EXTERNAL_INT7_DIS,
+ EXTERNAL_8IN1_INT0_DIS,
+ EXTERNAL_8IN1_INT1_DIS,
+ EXTERNAL_8IN1_INT2_DIS,
+ EXTERNAL_8IN1_INT3_DIS,
+ EXTERNAL_8IN1_INT4_DIS,
+ EXTERNAL_8IN1_INT5_DIS,
+ EXTERNAL_8IN1_INT6_DIS,
+ EXTERNAL_8IN1_INT7_DIS=49,
+
+ INVALID_WAKE_DIS_BIT
+/*PS wake int dis reg2 end*/
+}T_ZDrvPow_PsIntWakeDis;
+
+typedef enum
+{
+ PS_WAKE_INT,
+ PS_DIS_WAKE_INT,
+
+ INVALID_PS_WAKE_EN
+}T_ZDrvPow_PsWakeIntDis;
+
+
+typedef enum
+{
+ IDLE_FLAG_UICC =0,
+ IDLE_FLAG_USBENUM =1,
+ IDLE_FLAG_VOICE =2,
+ IDLE_FLAG_I2S=3,
+ IDLE_FLAG_AP2CP=4,
+ IDLE_FLAG_SLEEP=5,
+ IDLE_FLAG_WIFI=6,
+ IDLE_FLAG_KPD=7,
+ IDLE_FLAG_TCPIP=8,
+ IDLE_FLAG_NAND=9,
+ IDLE_FLAG_CHARGER=10,
+ IDLE_FLAG_LCD=11,
+ IDLE_FLAG_LED=12,
+ IDLE_FLAG_WIFI_IOCTRL=13,
+ IDLE_FLAG_WIFI_XMIT=14,
+ IDLE_FLAG_LAN=15,
+ IDLE_FLAG_HOSTENUM=16,
+ IDLE_FLAG_BLG=17,
+ IDLE_FLAG_UART=18,
+ IDLE_FLAG_TD_ICP=19,/*·ÀֹʹÄÜ×ÓÖ¡ÖжÏÓë×ÓÖ¡Öжϵ½À´ÆÚ¼ä½øÈëÐÝÃß*/
+ IDLE_FLAG_W_ICP=20,
+ IDLE_FLAG_LTE_ICP=21,
+ IDLE_FLAG_CAMERA=22,
+ IDLE_FLAG_SD=23,
+ IDLE_FLAG_PMIC=24,
+ IDLE_FLAG_I2C=25,
+ IDLE_FLAG_VSIM = 26,
+ IDLE_FLAG_EDCP=27,
+ IDLE_FLAG_TDM,
+ IDLE_FLAG_MAX
+
+}T_ZDrvPow_IdleFlag;
+
+/*plat begin*/
+typedef enum
+{
+ TD_PHY =0,
+ WD_PHY =1,
+ LTE_PHY =2,
+ PHY_ID_MAX
+
+}T_ZDrvPow_PhyId;
+
+typedef enum
+{
+ POW_BOOT_DEFAULT, /* Æô¶¯³õʼֵ */
+ POW_SYSINIT_FINISH, /* ϵͳ³õʼ»¯Íê³É,ÈçÐͺŻúÍê³ÉSysEntry */
+ POW_BOOT_FINISH /* ¿ª»úÍê³É£¬ÈçÐͺŻú³öÏÖ´ý»ú½çÃæ */
+}T_ZDrvPow_BootStage; /* Æô¶¯½×¶Î */
+/*plat begin*/
+
+/*sleep begin*/
+typedef struct _T_ZDrvPow_Opt
+{
+ VOID (*pow_RefBeforeSleep)(VOID);
+ VOID (*pow_RefAfterSleep)(VOID);
+}T_ZDrvPow_Opt;
+
+typedef enum
+{
+ KERNEL_SLEEP_MODE,
+ BOOT_SLEEP_MODE,
+ LOSSCOVERAGE_SLEEP_MODE,
+ AIRPLANE_SLEEP_MODE,
+ DEEP_SLEEP_MODE,
+ MAX_SLEEP_MODE
+}T_ZDrvPow_SleepMode;
+
+typedef enum
+{
+ FPI_CLK_32K = 0,
+ FPI_CLK_52M = 1,
+ FPI_INVALID_CLK
+}T_ZDrvPow_FpiClk;
+
+typedef enum
+{
+ ARM_PS_WAKE = 0,
+ ARM_PS_SLEEP = 1,
+ ARM_PS_INVALID_FLAG
+}T_ZDrvPow_PsSleepFlag;
+
+ /*sleep end*/
+
+ /*freq begin*/
+typedef enum
+{
+#if defined (_CHIP_ZX297520V2)
+ MAIN_CLK=0,
+ AON_MPLL_624M,
+ AON_DPLL_491M52,
+ MATRIX_MPLL_312M,
+ AON_MPLL_208M,
+ MATRIX_MPLL_104M,
+ MATRIX_MPLL_78M,
+ MATRIX_MPLL_52M=7,
+#else
+ MAIN_CLK=0,
+ AON_MPLL_624M,
+ MATRIX_MPLL_312M,
+ MATRIX_MPLL_156M,
+#endif
+ CORE_INVALID_FREQ
+}T_ZDrvPow_CoreFreq;
+
+typedef enum
+{
+#if defined (_CHIP_ZX297520V2)
+ AXI_26M,
+ AXI_39M,
+ AXI_52M,
+ AXI_78M,
+ AXI_104M,
+ AXI_122M88,
+ AXI_156M,
+#else
+ AXI_6M5=0,
+ AXI_26M,
+ AXI_39M,
+ AXI_52M,
+ AXI_78M,
+ AXI_104M,
+ AXI_124M8,
+ AXI_156M=7,
+#endif
+
+ AXI_INVALID_FREQ
+}T_ZDrvPow_AxiFreq;
+typedef enum
+{
+ VCORE_0V800,
+ VCORE_0V825,
+ VCORE_0V850,
+ VCORE_0V875,
+ VCORE_0V900,
+ VCORE_INVALID_VOL
+}T_ZDrvPow_Vcore;
+
+typedef enum
+{
+ CLK26M=26000000,
+ CLK624M=624000000,
+#if defined (_CHIP_ZX297520V2)
+#else
+ CLK156M=156000000,
+#endif
+ CLK312M=312000000,
+ CLK208M=208000000,
+ CLK78M=78000000,
+
+ CLK_INVALID_FREQ
+}T_ZDrvPow_PsFreqConst;
+
+#define DOWN_CPUFREQ CLK156M
+#define UP_CPUFREQ CLK312M
+#define PULL_CPUFREQ CLK624M
+#if PSM_DDR_DFS_HW
+ typedef enum
+ {
+ DDR_156M = 0, //ÐèÒªÖØп¼ÂÇƵÂʵµ£¬×îÖÕƵÂÊÇëÇóΪ¸÷ºËÇëÇóµþ¼ÓºÍ
+ DDR_208M = 0x4f,
+ DDR_312M = 0x9d,
+ DDR_400M = 0xc8,
+ DDR_CLKEND
+ }T_zDrvPow_DDRCLK;
+#else
+typedef enum
+{
+#if defined (_CHIP_ZX297520V2)
+ DDR_13M = 0,
+ DDR_52M = 1,
+ DDR_100M = 2,
+ DDR_104M = 3,
+ DDR_156M = 4,
+ DDR_208M = 5,
+ DDR_312M = 6,
+ DDR_400M = 7,
+ DDR_416M = 8,
+
+#else
+ DDR_156M ,
+ DDR_208M ,
+ DDR_312M ,
+ DDR_400M ,
+#endif
+ DDR_CLKEND
+}T_zDrvPow_DDRCLK;
+#endif
+
+ /*freq end*/
+
+/*gate begin*/
+typedef enum
+{
+ /*ps power domain*/
+ GSM_RAM_PWR = 0,
+ GSM_DSP_PWR = 1,
+ EDCP_PWR = 4,
+ /*3/4bits reserved*/
+ USB_CTRL_PWR = 8,
+ USB_HSIC_PWR = 9,
+
+ PS_ALL_PWR = 10,
+
+ MAX_PWR = 11
+
+}T_ZDrvPow_PwrId;
+
+typedef enum
+{
+ POW_ENABLE = 0,
+ POW_DISABLE = 1,
+
+ POW_ENABLE_ALL
+}T_ZDrvPow_PwrEn;
+/*gate end*/
+
+#ifdef _USE_WAKELOCK
+/*wakelock begin*/
+typedef struct _T_ZDrvWakeLock_Entry
+{
+ struct list_head node; /* node*/
+ char name[32];
+ BOOL active:1;
+ UINT32 active_count;
+ UINT32 relax_count;
+}T_ZDrvWakeLock_Entry;
+
+typedef struct _T_zDrvWakeLock_TAB
+{
+ struct list_head devList;
+ ZOSS_SEMAPHORE_ID opMutex;
+ UINT32 devListCount;
+}T_zDrvWakeLock_TAB;
+
+typedef void * T_ZDrvWakeLock_Handle;
+/*wakelock end*/
+#endif
+
+/****************************************************************************
+* function
+****************************************************************************/
+#ifdef _USE_WAKELOCK
+/*wakelock begin*/
+T_ZDrvWakeLock_Handle zDrvWakeLock_Register(const char *name);
+VOID zDrvWakeLock_Lock(T_ZDrvWakeLock_Handle handle);
+VOID zDrvWakeLock_Unlock(T_ZDrvWakeLock_Handle handle);
+BOOL zDrvWakeLock_DevStatue(VOID);
+/*wakelock end*/
+#endif
+
+typedef VOID (*psm_uartWakeExtApHook)(VOID); /*uart wake ext ap hook */
+typedef VOID (*psm_usbWakeExtApHook)(VOID); /*usb wake ext ap hook */
+
+typedef SINT32 (*pm_callback_fn)(void);
+
+extern SINT32 zx_pm_register_callback(pm_callback_fn enter_cb, pm_callback_fn exit_cb);
+
+VOID zDrvPow_SetWakeExtApHookOpt(psm_uartWakeExtApHook uartWakeExtApHook, psm_usbWakeExtApHook usbWakeExtApHook);
+
+
+/*plat begin*/
+SINT32 zDrvPow_GetLteSleepFlag(VOID);/*ÐÒéÕ»ÐèÇó£¬Óë7510±£³ÖÒ»ÖÂ*/
+VOID zDrvPow_ClearPhySleepFlag(VOID);
+SINT32 zDrvPow_GetPhySleepFlag(T_ZDrvPow_PhyId phyId);
+BOOL zDrvPow_PsmGetCampon(VOID);
+VOID zDrvPow_SetBootStage(T_ZDrvPow_BootStage stage);
+BOOL zDrvPow_PsmIdleFlag(VOID);
+VOID zDrvPow_DpramSendCmdWakePhy(T_ZDrvPow_PhyId phyId);
+VOID zDrvPow_Icp2ZspDebugInfo(T_ZDrvPow_PhyId phyId,SINT32 dwIcp);
+BOOL zDrvPow_UmtsSleep(VOID);
+VOID zDrvPow_ChangeRRCFreForGSM(VOID);
+UINT32 zDrvPow_Sleep_Func(T_ZDrvPow_SleepMode sleep_mode, UINT32 sleep_time);
+SINT32 zDrvPow_SetDevActive(T_ZDrvPow_IdleFlag devId);
+SINT32 zDrvPow_SetDevIdle(T_ZDrvPow_IdleFlag devId);
+UINT32 zDrvPow_PsmIdleFlagGet(VOID);
+UINT32 zDrvPow_PsmDeepSleepCnt(VOID);
+
+/*plat end*/
+
+ /*sleep begin*/
+SINT32 zDrvPow_SetOpt(T_ZDrvPow_Opt* pPowOpt);
+UINT32 zDrvPow_PsmDeepSleep(UINT32 ps_sleep_time);
+UINT32 zDrvPow_ChargerSleep(UINT32 sleep_time);
+VOID zDrvPow_KernelSleep(VOID);
+UINT32 zDrvPow_BootSleep(UINT32 sleep_time);
+VOID zDrvPow_ActiveSleep(UINT32 ms);
+SINT32 zDrvPow_SetPcuWakeInt(T_ZDrvPow_PsIntWakeDis intId,T_ZDrvPow_PsWakeIntDis intDis);
+SINT32 zDrvPow_PSM_Init(VOID);
+VOID zDrvPow_ChargerOnSleepInit(VOID);
+VOID zDrvPow_ChargerOnSleepOperation(VOID);
+ /*sleep end*/
+
+/*freq begin*/
+UINT32 zDrvPow_GetPsCoreFreq(VOID);
+
+SINT32 zDrvPow_SetArmPsCoreFreq(T_ZDrvPow_PsFreqConst workFreq);
+SINT32 zDrvPow_SetPsDdrFreq(T_zDrvPow_DDRCLK freq);
+/*freq end*/
+
+SINT32 zDrvPow_GetTdSfnFlag(VOID);
+VOID zDrvPow_PcuSetWakeSource(UINT32 *wake_source);
+VOID zDrvPow_PsmLed(BOOL onOff);
+/*power partition control*/
+SINT32 zDrvpow_SetPwrGate(T_ZDrvPow_PwrId partId, T_ZDrvPow_PwrEn ena);
+
+#endif/*_DRVS_POW_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_pwr.h b/cp/ps/driver/inc/misc/drvs_pwr.h
new file mode 100644
index 0000000..a86e87a
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_pwr.h
@@ -0,0 +1,25 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: vx.x.
+ * Author: ZhengHong
+ * Date: 2009-6-29
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ******************************************************************************/
+
+#ifndef _DRVS_PWR_H_
+#define _DRVS_PWR_H_
+
+#include "drvs_pow.h"
+
+#endif
+
diff --git a/cp/ps/driver/inc/misc/drvs_rf.h b/cp/ps/driver/inc/misc/drvs_rf.h
new file mode 100644
index 0000000..bcfe48b
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_rf.h
@@ -0,0 +1,171 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: drvs_rf.h
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: v1.2.1
+ * Author: wangxia
+ * Date: 2009-4-17
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_RF_H
+#define _DRVS_RF_H
+
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+
+/****************************************************************************
+* Types
+****************************************************************************/
+typedef struct
+{
+ UINT32 i2s2_wa_sel:1;
+ UINT32 i2s2_clk_sel:1;
+ UINT32 i2s1_wa_sel:1;
+ UINT32 i2s1_clk_sel:1;
+ UINT32 gpio_clkout3_sel:1;
+ UINT32 gpio_clkout2_sel:1;
+ UINT32 gpio_clkout1_sel:1;
+ UINT32 gpio_clkout0_sel:1;
+ UINT32 td_spi_sel:1;
+ UINT32 reserved9_15:7;
+ UINT32 td_time2_ind_en:1;
+ UINT32 td_time1_ind_en:1;
+ UINT32 rc_out1_en:1;
+ UINT32 rc_out0_en:1;
+ UINT32 clkout3_en:1;
+ UINT32 clkout2_en:1;
+ UINT32 clkout0_en:1;
+ UINT32 clkout1_en:1;
+ UINT32 reserved24_31:8;
+}T_ZDrvRf_I2s_ClkOut;
+
+
+typedef struct
+{
+ UINT32 spi_gpio_oen:14;
+ UINT32 reserved14_15:2;
+ UINT32 spi_gpio_in:14;
+ UINT32 reserved30_31:2;
+}T_ZDrvRf_SpiEn;
+
+
+typedef struct
+{
+ UINT32 spi_gpio_out:14;
+ UINT32 reserved14_15:2;
+ UINT32 spi_gpio_sel:14;
+ UINT32 reserved30_31:2;
+}T_ZDrvRf_SpiSel;
+
+
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+
+/*******************************************************************************
+ * Function: zDrvRf_GsmSelect
+ * Description: select GSM rf through GPIO
+ * Parameters:
+ * Input:gsmgpio 0~7
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvRf_GsmSelect(UINT32 gsmgpio);
+
+
+/*******************************************************************************
+ * Function: zDrvRf_TdSelect
+ * Description: select TD rf through GPIO
+ * Parameters:
+ * Input:tdgpio 0~8
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvRf_TdSelect(UINT32 tdgpio);
+
+/*******************************************************************************
+ * Function: zDrvRf_I2sClkOutSel
+ * Description: select I2S & Clk Out
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+VOID zDrvRf_I2sClkOutSel(T_ZDrvRf_I2s_ClkOut i2s_clkout);
+
+/*******************************************************************************
+ * Function: zDrvRf_SpiGpioOen
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+VOID zDrvRf_SpiGpioOen(T_ZDrvRf_SpiEn spioen);
+
+/*******************************************************************************
+ * Function: zDrvRf_SpiGpioSel
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+VOID zDrvRf_SpiGpioSel(T_ZDrvRf_SpiSel spisel);
+
+
+
+
+#endif/*_DRVS_RF_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_rpmsg.h b/cp/ps/driver/inc/misc/drvs_rpmsg.h
new file mode 100755
index 0000000..7690bf8
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_rpmsg.h
@@ -0,0 +1,538 @@
+/*******************************************************************************
+ * Copyright by ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: 0.1
+ * Author: zhangdongdong
+ * Date: 2015-10-21
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_RPMSG_H
+#define _DRVS_RPMSG_H
+
+/*******************************************************************************
+* Include files *
+*******************************************************************************/
+#include "ram_config.h"
+
+/*******************************************************************************
+* Macro *
+*******************************************************************************/
+#define RPMSG_WRITE_INT (0x1)
+#define RPMSG_READ_POLL (0x1<<1)
+
+#define CHANNEL_FLAG 0x1
+
+#define M0AP_CHANNEL_MAXID 10
+/*******************************************************************************
+* Types *
+*******************************************************************************/
+
+/*-----------------------[Begin] [used by normal]-----------------------------*/
+/*channels definition*/
+#define DRIVER channel_0
+#define PSM channel_1
+#define USB_ADB channel_2
+
+
+#define WAN1 channel_3
+#define WAN2 channel_4
+#define WAN3 channel_5
+#define WAN4 channel_6
+
+#define DTMF channel_7
+#define DEV_BUFFREE channel_8
+
+#define AMT channel_9
+#define RAMDUMP channel_10
+
+#define VSIM channel_11
+#define ISMS channel_12
+
+#define IPSEC1 channel_13
+#define IPSEC2 channel_14
+#define IPSEC3 channel_15
+#define IPSEC4 channel_16
+
+
+typedef enum _T_ZDrvRpMsg_MsgActor
+{
+#ifdef _OS_TOS
+ ICP_MSG_ACTOR_A9,
+#endif
+ ICP_MSG_ACTOR_ZSP,
+ ICP_RPMSG_ACTOR_M0,
+ MAX_RPMSG_ACTOR
+} T_ZDrvRpMsg_MsgActor;
+
+typedef enum _T_ZDrvRpMsg_ChID
+{
+ CHANNEL_BASEID,
+
+ channel_0 = CHANNEL_BASEID, //driver just for AP<->PS
+ channel_1, //PSM
+ channel_2, //USB_DETCT
+ channel_3, //USB_ADB
+ channel_4, //WAN
+ channel_5, //LAN1
+ channel_6, //LAN2
+ channel_7, //DEV_BUFMALLOC
+ channel_8, //DEV_BUFFREE
+ channel_9, //AT
+ CHANNEL_PS2M0_MAXID,
+
+ channel_10 = CHANNEL_PS2M0_MAXID, //AMT
+ channel_11, //LOG
+ channel_12, //FOTA
+
+ channel_13,
+ channel_14,
+ channel_15,
+ channel_16,
+ channel_17,
+ channel_18,
+ channel_19,
+ channel_20,
+ channel_21,
+ channel_22,
+ channel_23,
+ channel_24,
+ channel_25,
+ channel_26,
+ channel_27,
+ channel_28,
+ channel_29,
+ channel_30,
+ channel_31,
+ channel_32,
+ channel_33,
+ channel_34,
+ channel_35,
+ channel_36,
+ channel_37,
+ channel_38,
+ channel_39,
+ channel_40,
+ channel_41,
+ channel_42,
+ channel_43,
+ channel_44,
+ channel_45,
+ channel_46,
+ channel_47,
+ channel_48,
+ channel_49,
+ channel_50,
+ channel_51,
+ channel_52,
+ channel_53,
+ channel_54,
+ channel_55,
+ channel_56,
+ channel_57,
+ channel_58,
+ channel_59,
+ channel_60,
+ channel_61,
+ channel_62,
+ channel_63,
+
+ PSAP_CHANNEL_MAXID
+}T_ZDrvRpMsg_ChID;
+
+typedef struct _T_ZDrvRpMsg_Msg
+{
+ T_ZDrvRpMsg_MsgActor actorID;
+ T_ZDrvRpMsg_ChID chID;
+ UINT32 flag; /*bit0:is need send icp int 1:y; 0:n*/
+ /*bit1: read mode 1:poll; 0:semaphore*/
+ VOID *buf;
+ UINT32 len;
+} T_ZDrvRpMsg_Msg;
+
+typedef enum _T_ZDrvRpMsg_ErrCode
+{
+ RPMSG_INVALID_PARAMETER = -101, //²ÎÊý²»ÕýÈ·
+ RPMSG_SPACE_NOT_ENOUGH = -102, //¿Õ¼ä²»×ã¹»
+ RPMSG_CHANNEL_ALREADY_EXIST = -103, //ͨµÀÒѾ´æÔÚ
+ RPMSG_CHANNEL_INEXISTANCE = -104, //ͨµÀ²»´æÔÚ
+ RPMSG_CHANNEL_MSG_ERR = -105, //ͨµÀÖÐÏûÏ¢´íÎó
+ RPMSG_CHANNEL_NOMSG = -107, //ͨµÀÖÐûÓÐÏûÏ¢
+}
+T_ZDrvRpMsg_ErrCode;
+
+typedef VOID (*T_ZDrvRpMsg_CallbackFunction)(VOID *buf, UINT32 len);/*for normal*/
+
+/*******************************************************************************
+* Function Prototypes *
+*******************************************************************************/
+
+/*******************************************************************************
+* Function: zDrvRpMsg_CreateChannel
+* Description: This function is used for create channel to send message;
+* Parameters:
+* Input:
+* actorID:remote cpu
+* chID: ID of channel
+* size: size of channel
+* Output:None
+*
+* Returns:
+* DRV_SUCCESS: successfully .
+* DRV_ERROR: fail .
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_CreateChannel (T_ZDrvRpMsg_MsgActor actorID, T_ZDrvRpMsg_ChID chID, UINT32 size);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_RegCallBack
+* Description: This function is used for registing callback functions;
+* Parameters:
+* Input:
+* actor: core id.
+* chID : channel id
+* callback: callback function
+* Output:None
+*
+* Returns:
+* DRV_SUCCESS: successfully .
+* other: fail .
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_RegCallBack(T_ZDrvRpMsg_MsgActor actorID, T_ZDrvRpMsg_ChID chID, T_ZDrvRpMsg_CallbackFunction callback);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_MaskInt
+* Description: This function is used for mask ICP interrupt from another core;
+* Parameters:
+* Input:
+* actor: which core.
+* bit_map: which interrupts will be masked.
+* Output:None
+*
+* Returns:
+* None
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_MaskInt(T_ZDrvRpMsg_MsgActor actorID, T_ZDrvRpMsg_ChID chID);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_UnmaskInt
+* Description: This function is used for unmask ICP interrupt from another core;
+* Parameters:
+* Input:
+* actor: which core.
+* bit_map: which interrupts will be unmasked.
+* Output:None
+*
+* Returns:
+* None
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_UnmaskInt(T_ZDrvRpMsg_MsgActor actorID, T_ZDrvRpMsg_ChID chID);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_Write
+* Description: This function is used for sending message to remote cpu, mutex;
+* Parameters:
+* Input:
+* pMsg: the msg which will be sent
+* Output:None
+*
+* Returns:
+* DRV_SUCCESS: successfully send msg.
+* other: fail to send msg.
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_Write(const T_ZDrvRpMsg_Msg *pMsg);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_WriteWithId
+* Description: This function is used for ps&phy to send msg to remote cpu.
+* Parameters:
+* Input:
+* msgId:msg id that ps will put into the ring buffer
+* pMsg: the msg which will be sent
+* Output:None
+*
+* Returns:
+* DRV_SUCCESS: successfully send msg.
+* other: fail to send msg.
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_WriteWithId(UINT32 msgId, const T_ZDrvRpMsg_Msg *pMsg);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_WriteLockIrq
+* Description: This function is used for sending message to remote cpu, no mutex;
+* Parameters:
+* Input:
+* pMsg: the msg which will be sent
+* Output:None
+*
+* Returns:
+* DRV_SUCCESS: successfully send msg.
+* other: fail to send msg.
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_WriteLockIrq(const T_ZDrvRpMsg_Msg *pMsg);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_Read
+* Description: This function is used for reading message;
+* Parameters:
+* Input:
+* pMsg:message which will be read
+* Output:
+* pMsg
+*
+* Returns:
+* DRV_SUCCESS: successfully .
+* other: fail .
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_Read(const T_ZDrvRpMsg_Msg *pMsg);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_ReadWithId
+* Description: This function is used for ps&phy to read message from remote cpu;
+* Parameters:
+* Input:
+* pMsgId:msg id that ps will get from the ring buffer
+* pMsg:message which will be read
+* Output:
+* pMsg
+*
+* Returns:
+* DRV_SUCCESS: successfully .
+* other: fail .
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_ReadWithId(UINT32 *pMsgId, const T_ZDrvRpMsg_Msg *pMsg);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_ReadWithIdLockIrq
+* Description: This function is used for reading message;
+* Parameters:
+* Input:
+* pMsgId:msg id that ps will get from the ring buffer
+* pMsg:message which will be read
+* Output:
+* pMsg
+*
+* Returns:
+* DRV_SUCCESS: successfully .
+* other: fail .
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_ReadWithIdLockIrq(UINT32 *pMsgId, const T_ZDrvRpMsg_Msg *pMsg);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_ReadLockIrq
+* Description: This function is used for reading message;
+* Parameters:
+* Input:
+* pMsg:message which will be read
+* Output:
+* pMsg
+*
+* Returns:
+* DRV_SUCCESS: successfully .
+* other: fail .
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_ReadLockIrq(const T_ZDrvRpMsg_Msg *pMsg);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_ChIsEmpty
+* Description: This function is used for checking the channel used to receive message is empty or not;
+* Parameters:
+* Input:
+* actorID:remote cpu
+* chID:channel id
+* Output:None
+*
+* Returns:
+* TRUE: channel is empty .
+* FALSE: channel is not empty .
+*
+* Others:
+********************************************************************************/
+BOOL zDrvRpMsg_ChIsEmpty(T_ZDrvRpMsg_MsgActor actorID, T_ZDrvRpMsg_ChID chID);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_WriteChIsEmpty
+* Description: This function is used for checking the channel used to send message is empty or not;
+* Parameters:
+* Input:
+* actorID:remote cpu
+* chID:channel id
+* Output:None
+*
+* Returns:
+* TRUE: channel is empty .
+* FALSE: channel is not empty .
+*
+* Others:
+********************************************************************************/
+BOOL zDrvRpMsg_WriteChIsEmpty(T_ZDrvRpMsg_MsgActor actorID, T_ZDrvRpMsg_ChID chID);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_CreateBlock
+* Description: This function is used for create block channel to send message;
+* Parameters:
+* Input:
+* actorID:remote cpu
+* chID: ID of channel
+* blkSize: size of block, 4 bytes reserve at leaset
+* blkNums: numbers of block
+* memtype: 0:iram 1:ddr
+* Output:None
+*
+* Returns:
+* DRV_SUCCESS: successfully .
+* DRV_ERROR: fail .
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_CreateBlock(T_ZDrvRpMsg_MsgActor actorID, T_ZDrvRpMsg_ChID chID, UINT32 blkSize, UINT32 blkNums, UINT32 memType);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_GetWriteAddr
+* Description: This function is used for getting write addr;
+* Parameters:
+* Input:
+* actorID:remote processor id
+* chID:channel id
+* Output:
+* wrAddr:addr for write
+*
+* Returns:
+* positive: success
+* negative: fail .
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_GetWriteAddr(T_ZDrvRpMsg_MsgActor actorID, T_ZDrvRpMsg_ChID chID, VOID **wrAddr);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_WriteUpdate
+* Description: This function is used for reading message;
+* Parameters:
+* Input:
+* actorID:remote processor id
+* chID:channel id
+* addr:addr for update
+* len:update len
+* intFlag: 0:without icp int 1:with icp int
+* Output:
+* NULL
+*
+* Returns:
+* positive: len
+* negative: fail .
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_WriteUpdate(T_ZDrvRpMsg_MsgActor actorID, T_ZDrvRpMsg_ChID chID, UINT32 addr, UINT32 len, BOOL intFlag);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_GetReadAddr
+* Description: This function is used for getting read addr;
+* Parameters:
+* Input:
+* actorID:remote processor id
+* chID:channel id
+* Output:
+* rdAddr:addr for read
+*
+* Returns:
+* positive: len
+* negative: fail .
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_GetReadAddr(T_ZDrvRpMsg_MsgActor actorID, T_ZDrvRpMsg_ChID chID, VOID **rdAddr);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_ReadUpdate
+* Description: This function is used for reading message;
+* Parameters:
+* Input:
+* actorID:remote processor id
+* chID:channel id
+* addr:update addr
+* Output:
+* NULL
+*
+* Returns:
+* positive: len
+* negative: fail .
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_ReadUpdate(T_ZDrvRpMsg_MsgActor actorID, T_ZDrvRpMsg_ChID chID, UINT32 addr);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_Initiate
+* Description: This function is used to init rpmsg module;
+* Parameters:
+* Input:
+* null
+*
+* Output:None
+*
+* Returns:
+* DRV_SUCCESS: successfully .
+* other: fail .
+*
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvRpMsg_Initiate (VOID);
+
+/*******************************************************************************
+* Function: zDrvRpMsg_ReadExit
+* Description: This function is used to exit from the block read func,for ctrm;
+* Parameters:
+* Input:
+* null
+*
+* Output:None
+*
+* Returns:
+* null .
+*
+*
+*
+* Others:
+********************************************************************************/
+VOID zDrvRpMsg_ReadExit(T_ZDrvRpMsg_MsgActor actor, T_ZDrvRpMsg_ChID chID);
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_rtt.h b/cp/ps/driver/inc/misc/drvs_rtt.h
new file mode 100644
index 0000000..f9d53b1
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_rtt.h
@@ -0,0 +1,179 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: drvs_rtt.h
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: 1.0
+ * Author: wangxia
+ * Date: 2010-4-29
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_RTT_H
+#define _DRVS_RTT_H
+
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "os_ose.h"
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+#define RTT_INT_LEVEL_USER_0 0x5
+#define RTT_INT_LEVEL_USER_1 0x5
+#define RTT_INT_LEVEL_USER_2 0x5
+#define RTT_INT_LEVEL_USER_3 0x5
+#define RTT_INT_LEVEL_USER_4 0x5
+#define RTT_INT_LEVEL_USER_COMMON 0x7
+
+/*The RTT Clock resolution on creation. RTT Clock is available only for predefined users.
+ The resolution can be modified at runtime using RTT_set_clock_resolution
+ */
+#define RTT_DEFAULT_CLOCK_RESOLUTION rtt_clock_100_microseconds
+
+/****************************************************************************
+* Types
+****************************************************************************/
+ typedef enum
+ {
+ rtt_uicc, /* Reserved timer : GPT0T1 */
+ rtt_free1, /* Reserved timer : GPT0T0 */
+ rtt_meas, /* Reserved timer : GPT1T0 */
+ rtt_mmci, /* Reserved timer : GPT1T1 */
+ rtt_free2, /* Reserved timer : GPT1T2 */
+ rtt_common = 5, /* Reserved timer : GPT0T2 */
+ rtt_with_clock = 15, /* !!! use MSB special exception for turning of powersave !!!*/
+ rtt_max_nof_timers = 40
+ } rtt_timer_user_id_enum;
+
+ typedef enum
+ {
+ rtt_one_shot,
+ rtt_repetitive,
+ rtt_one_shot_timer_with_clock,
+ rtt_repetitive_timer_with_clock
+ } rtt_timer_mode_enum;
+
+ typedef enum
+ {
+ rtt_clock_1_microsecond,
+ rtt_clock_10_microseconds,
+ rtt_clock_100_microseconds,
+ rtt_clock_5_milliseconds,
+ rtt_clock_10_milliseconds,
+ rtt_clock_100_milliseconds
+ }rtt_clock_resolution_type;
+
+ /*---------------------------------------------*/
+ /* Typedefinition . */
+ /*---------------------------------------------*/
+ typedef struct
+ {
+ VOID (*timeout_func)(VOID ); /* Callback function on timeout */
+ VOID *arg; /* Argument list to the above callback function */
+ rtt_timer_user_id_enum user_id;
+ rtt_timer_mode_enum timer_mode;
+ UINT32 created;
+ UINT32 started;
+ UINT32 duration;
+ UINT32 restart_duration;
+ UINT32 hw_timer_id;
+ UINT32 process_id;
+ } rtt_timer_list_type;
+ /* end of UICC_Driver_2007_11_2_dcm */
+
+ typedef struct
+ {
+ unsigned int creation_time[2]; //64 bit creation timestamp
+ unsigned int scaled_creation_time; //scaled to current resolution
+ unsigned long resolution;
+ }rtt_clock_data_type;
+
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+
+/*******************************************************************************
+ * Function: RTT_create_timer
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+extern rtt_timer_list_type *RTT_create_timer(VOID (*timeout_func)(VOID ),
+ VOID *arg,
+ rtt_timer_user_id_enum user_id,
+ rtt_timer_mode_enum timer_mode);
+
+/*******************************************************************************
+ * Function: RTT_remove_timer
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+extern SINT32 RTT_remove_timer(rtt_timer_list_type *timer);
+
+
+/*******************************************************************************
+ * Function: RTT_start_timer
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+extern SINT32 RTT_start_timer(rtt_timer_list_type *timer, UINT32 duration);
+
+
+/*******************************************************************************
+ * Function: RTT_stop_timer
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+extern SINT32 RTT_stop_timer(volatile rtt_timer_list_type * volatile timer);
+#endif/*_DRVS_RTT_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_spcu.h b/cp/ps/driver/inc/misc/drvs_spcu.h
new file mode 100644
index 0000000..27dbfaf
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_spcu.h
@@ -0,0 +1,68 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: drvs_spcu.h
+* File Mark:
+* Description: spcu hal interface declaration.
+* Others:
+* Version: v1.0
+* Author: wangxia
+* Date: 2010-01-26
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+
+* History 2:
+**********************************************************************/
+
+#ifndef DRVS_SPCU_H
+#define DRVS_SPCU_H
+
+
+/*************************************************************************
+ * Include files *
+ *************************************************************************/
+
+
+/*************************************************************************
+ * Macro *
+ *************************************************************************/
+
+
+/**************************************************************************
+ * Types *
+ **************************************************************************/
+typedef VOID (*T_ZDRVSPCU_CALLBACK)(VOID);
+
+/**************************************************************************
+ * Global Variable *
+ **************************************************************************/
+
+/**************************************************************************
+ * Function Prototypes *
+ **************************************************************************/
+/**************************************************************************
+* Functin: zDrvSpcu_IntRegister
+* Description: This function is used to regist isr callback for l1g.
+* Parameters:
+* (IN)
+* fCallback: isr callback.
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERR_NOT_SUPPORTED: this device don't support ioctrl operation.
+* DRV_ERR_INVALID_PARAM: the input parameters are invalid
+* DRV_ERROR: error
+* others: others programmer defined error code. for detailed information, please contact with the programmer
+* Others:
+* others error code should be a negative number, and not equal to the value that already be defined in T_ZDrv_ErrCode in drv_pub.h.
+**************************************************************************/
+extern SINT32 zDrvSpcu_IntRegister(T_ZDRVSPCU_CALLBACK fCallback,UINT32 intPrio);
+
+#endif/*DRVS_SPCU_H */
+
+
diff --git a/cp/ps/driver/inc/misc/drvs_spinlock.h b/cp/ps/driver/inc/misc/drvs_spinlock.h
new file mode 100644
index 0000000..13066d1
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_spinlock.h
@@ -0,0 +1,231 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description: all function defines provided by sys module
+ * Others:
+ * Version: 1.0
+ * Author: chenjianguo
+ * Date: 2013-5-31
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_SPINLOCK_H
+#define _DRVS_SPINLOCK_H
+
+#include "drvs_general.h"
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+/****************************************************************************
+* Types
+****************************************************************************/
+typedef enum
+{
+ CORE_ID_PS=210,
+ CORE_ID_PHY=211,
+ CORE_ID_ZSP=212,
+ CORE_ID_M0=213,
+ CORE_ID_AP=214,
+ CORE_ID_NUM = 215
+} T_ZDrvSpinlock_CpuId;
+/* ±êʶӲ¼þËø*/
+typedef enum
+{
+ PCU_HWLOCK = 0,/*PCU*/
+ CLK_HWLOCK = 1,/*Clock*/
+ REGLOCK_HWLOCK = 2,/*Reg*/
+ SOFTLOCK_HWLOCK = 3,/*Software*/
+ HWLOCK_NUM
+} T_ZDrvSpinlock_HwLockId;
+
+/* ±êʶÈí¼þËø*/
+typedef enum
+{
+ I2C0_SFLOCK = 0,/*i2c0*/
+ I2C1_SFLOCK = 1,/*i2c1*/
+ I2C2_SFLOCK = 2,/*pmic-i2c*/
+ NAND_SFLOCK = 3,/*NAND*/
+ SD0_SFLOCK,
+ SD1_SFLOCK,
+ ADC_SFLOCK, /*pmic adc*/
+ UART_SFLOCK,
+ SFLOCK_ID8,
+ SFLOCK_ID9,
+ SFLOCK_ID10,
+ SFLOCK_ID11,
+ SFLOCK_ID12,
+ SFLOCK_ID13,
+ SFLOCK_ID14,
+ SFLOCK_ID15,
+ SFLOCK_ID16,
+ SFLOCK_ID17,
+ SFLOCK_ID18,
+ SFLOCK_ID19,
+ SFLOCK_ID20,
+ SFLOCK_ID21,
+ SFLOCK_ID22,
+ SFLOCK_ID23,
+ SFLOCK_ID24,
+ SFLOCK_ID25,
+ SFLOCK_ID26,
+ SFLOCK_ID27,
+ SFLOCK_ID28,
+ SFLOCK_ID29,
+ SFLOCK_ID30,
+ REG_SFLOCK = 31,/*reg*/
+ SFLOCK_NUM
+} T_ZDrvSpinlock_SfLockId;
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+/*******************************************************************************
+ * Function: zDrvSysSpinlock_HwLock
+ * Description:»ñÈ¡Ó²¼þËø£¬id 0~1£¬
+ * id 4±£Áô¸øÈí¼þËøʹÓã¬ÍⲿÇý¶¯²»¿ÉÓá£
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvSysSpinlock_HwLock(T_ZDrvSpinlock_HwLockId hwid);
+/*******************************************************************************
+ * Function: zDrvSysSpinlock_HwUnlock
+ * Description:Çý¶¯ÊÍ·ÅÓ²¼þËø£¬id 0~1
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvSysSpinlock_HwUnlock(T_ZDrvSpinlock_HwLockId hwid);
+/*******************************************************************************
+ * Function: zDrvSysSpinlock_SoftLock
+ * Description:Çý¶¯»ñµÃÈí¼þËø½Ó¿Ú
+ * Parameters:
+ * Input: sfid: Èí¼þËøid¡£
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvSysSpinlock_SoftLock(T_ZDrvSpinlock_SfLockId sfid);
+/*******************************************************************************
+ * Function: zDrvSysSpinlock_soft_unlock
+ * Description:ÓëzDrvSysSpinlock_SoftLock¶ÔÓ¦µÄÊÍ·ÅÈí¼þËø½Ó¿Ú¡£
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvSysSpinlock_SoftUnlock(T_ZDrvSpinlock_SfLockId sfid);
+/*******************************************************************************
+ * Function: zDrvSysSpinlock_SoftLockPsm
+ * Description:Çý¶¯»ñµÃÈí¼þËø½Ó¿Ú(Ê¡µçרÓÃ)
+ * Parameters:
+ * Input: sfid: Èí¼þËøid¡£
+ * coreid: ±£³ÖidºÅΪsfidÈí¼þËøµÄcpuid¡£
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvSysSpinlock_SoftLockPsm(T_ZDrvSpinlock_SfLockId sfid);
+
+/*******************************************************************************
+ * Function: zDrvSysSpinlock_SoftUnlockPsm
+ * Description:ÓëzDrvSysSpinlock_SoftLockPsm¶ÔÓ¦µÄÊÍ·ÅÈí¼þËø½Ó¿Ú¡£
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvSysSpinlock_SoftUnlockPsm(T_ZDrvSpinlock_SfLockId sfid);
+
+/*******************************************************************************
+ * Function: zDrvSysSpinlock_RegLock
+ * Description:Çý¶¯»ñµÃÈí¼þËø½Ó¿Ú
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvSysSpinlock_RegLock(VOID);
+/*******************************************************************************
+ * Function: zDrvSysSpinlock_reg_unlock
+ * Description:ÓëzDrvSysSpinlock_RegLock¶ÔÓ¦µÄÊÍ·ÅÈí¼þËø½Ó¿Ú¡£
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvSysSpinlock_RegUnlock(VOID);
+/*******************************************************************************
+ * Function: zDrvSysSpinlock_Initiate
+ * Description:Èí¼þËø³õʼ»¯¡£
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvSysSpinlock_Initiate(VOID);
+#endif/*_DRVS_SYS_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_ssp.h b/cp/ps/driver/inc/misc/drvs_ssp.h
new file mode 100644
index 0000000..1b64c00
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_ssp.h
@@ -0,0 +1,255 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: 1.0
+ * Author: weizhigang
+ * Date: 2010-8-6
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_SSP_H
+#define _DRVS_SSP_H
+
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "drvs_dma.h"
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+//#define SSP_INT_ENABLE 0
+//#define SSP_DMA_ENABLE 1
+
+#define SSP_ASSERT() zOss_ASSERT(0)
+
+#define SSP_ERROR(format,args...) do {SSP_ASSERT();zOss_Printf(1,1,format,##args);} while(0)
+
+#define SSP_DEBUG_RAMLOG
+
+#ifdef SSP_DEBUG_RAMLOG
+#define zDrvSsp_RamLog(s...) zDrvRamlog_PRINTF(RAMLOG_MOD_SPI,s)
+#else
+#define zDrvSsp_RamLog(s...)
+#endif
+
+#define SPI_PRINTF(cond, format, args...) do { if(cond) zOss_Printf(SUBMDL_TEST, PRINT_LEVEL_NORMAL, format, ##args);}while(0)
+/****************************************************************************
+* Types
+****************************************************************************/
+
+
+//define ssp num --zhangpei add
+typedef enum _T_SspDevNum
+{
+ SSP_DEV_0 = 0,
+ SSP_DEV_1 = 1,
+ SSP_DEV_NUM
+}
+T_SspDevNum;
+typedef enum _T_SspMSMode
+{
+ SSP_MS_MASTER = 0x0,
+ SSP_MS_SLAVE = 0x1,
+}
+T_SspMSMode;
+//define ssp mode
+typedef enum _T_SspMode
+{
+ SSP_AS_SPI = 0x0,
+ SSP_AS_TISS = 0x1,
+}
+T_SspMode;
+
+//define ssp mode
+typedef enum _T_SspXferWidth
+{
+ SSP_8_BIT = 7,
+ SSP_9_BIT = 8,
+ SSP_16_BIT = 15,
+ SSP_32_BIT = 31
+}
+T_SspXferWidth;
+
+//define ssp mode
+typedef enum _T_SspPolarity
+{
+ SPH_SPO_00 = 0x0,
+ SPH_SPO_01 = 0x1,
+ SPH_SPO_10 = 0x2,
+ SPH_SPO_11 = 0x3
+}
+T_SspPolarity;
+
+
+//defined for ssp frequency changing
+typedef enum _T_SspFrequency
+{
+ SSP_FREQ_52M,
+ SSP_FREQ_39M,
+ SSP_FREQ_26M,
+ SSP_FREQ_13M,
+ SSP_FREQ_6M5,
+ SSP_FREQ_3M2,
+ SSP_FREQ_1M6,
+ SSP_FREQ_812K5,
+ SSP_FREQ_NUM,
+}
+T_SspFrequency;
+
+typedef enum _T_SspCamMode
+{
+ SSP_NORMAL_MODE = 0x0,
+ SSP_CAMERA_MODE = 0x1,
+}
+T_SspCamMode;
+
+
+//define ssp cs level
+typedef enum _T_SspCsLevel
+{
+ SSP_CS_LOW = 0,
+ SSP_CS_HIGH = 1
+}
+T_SspCsLevel;
+
+
+//define the status
+#define RXFIFOFULL 1
+#define RXFIFONOTFULL 0
+#define RXFIFOEMPT 0
+#define RXFIFONOTEMPT 1
+#define TXFIFOFULL 0
+#define TXFIFONOTFULL 1
+#define TXFIFOEMPTY 1
+#define TXFIFONOTEMPTY 0
+
+//define register bit field segment
+typedef volatile struct
+{
+ /*0x00*/
+ UINT32 SSP_VER_REG;
+ /*0x04*/
+ UINT32 SSP_COM_CTRL;
+ /*0x08*/
+ UINT32 SSP_FMT_CTRL;
+ /*0x0c*/
+ UINT32 SSP_DR;
+ /*0x10*/
+ UINT32 SSP_FIFO_CTRL;
+ /*0x14*/
+ UINT32 SSP_FIFO_SR;
+ /*0x18*/
+ UINT32 SSP_INTR_EN;
+ //0x1c
+ UINT32 SSP_ISR_OR_ICR;
+ //0x20
+ UINT32 SSP_TIMING;
+
+}
+T_SspReg;
+
+
+typedef enum _T_SspStatus
+{
+ SSP_STA_INIT = 0,
+ SSP_STA_OPENED,
+ SSP_STA_XFER,
+ SSP_STA_DMA_ERR,
+ SSP_STA_DONE,
+}
+T_SspStatus;
+
+typedef struct _T_SspDmaInfo
+{
+ UINT32 rxDmaChl; // ssp rx Dma channel number
+ UINT32 txDmaChl;
+ T_ZDrvDma_ChannelDef rxDmaChlDef;
+ T_ZDrvDma_ChannelDef txDmaChlDef;
+ zDrvDma_CallbackFunc rxDmaCbFunc; // ssp rx callback function
+ zDrvDma_CallbackFunc txDmaCbFunc;
+ ZOSS_SEMAPHORE_ID TxDmaSema;
+ ZOSS_SEMAPHORE_ID RxDmaSema;
+} T_SspDmaInfo;
+
+
+typedef union _T_SspData
+{
+ UINT8 *Buf_8;
+ UINT16 *Buf_16;
+ UINT32 *Buf_32;
+ VOID *Buf;
+} T_SspData;
+
+
+typedef struct
+{
+ T_SspDevNum devNum; //indicate the ssp device num
+ T_SspReg* regPtr;
+ T_SspDmaInfo SspDmaInfo;
+ T_SspStatus status;
+ T_SspMSMode msMode;
+ T_SspMode mode;
+ T_SspPolarity polarity;
+ T_SspXferWidth xferWidth;
+
+ //NT32 SspWorkClock; //the wanted freq
+ //NT32 RealSspWorkClock; //the actral freq
+ UINT32 SspWorkClock; //the wanted freq
+
+ UINT32 tx_thres;
+ UINT32 rx_thres;
+
+ UINT32 Len_tx_remin;
+ VOID* txBuf;
+ UINT32 Len_rx_remin;
+ VOID* rxBuf;
+
+ UINT32 bPrint;
+
+ //ZOSS_SEMAPHORE_ID txSem;
+ // ZOSS_SEMAPHORE_ID rxSem;
+
+}
+T_SspDevHnd;
+
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+SINT32 zDrvSsp_Transfer(VOID* hnd, VOID* txBuf ,VOID* rxBuf,UINT32 Len);
+//VOID* zDrvSsp_Open(T_SspDevNum devNum, T_SspMSMode msMode);
+VOID* zDrvSsp_Open(T_SspDevNum devNum);
+//VOID zDrvSsp_Reset(T_SspDevNum devNum);
+SINT32 zDrvSsp_Set_XferWidth(VOID* hnd,T_SspXferWidth length);
+
+SINT32 zDrvSsp_Xfer(VOID* hnd, VOID* txBuf ,VOID* rxBuf,UINT32 Len);
+
+SINT32 zDrvSsp_DmaXfer(VOID* hnd, VOID* txBuf ,VOID* rxBuf,UINT32 Len);
+//SINT32 zDrvSsp_DmaEnable(T_SspDevNum devNum);
+//SINT32 zDrvSsp_DmaDisable(T_SspDevNum devNum);
+//NT32 zDrvSsp_ChangeFreq(VOID *hnd, T_SspFrequency Freq);
+SINT32 zDrvSsp_SetMSMode(VOID *hnd, T_SspMSMode msMode);
+SINT32 zDrvSsp_Initiate(VOID);
+SINT32 zDrvSsp_Ioctl(VOID *hnd, T_DRVIO_CTRL_KEY function, VOID *arg);
+
+#endif/*_FILENAME_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_sys.h b/cp/ps/driver/inc/misc/drvs_sys.h
new file mode 100644
index 0000000..3f7dcbf
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_sys.h
@@ -0,0 +1,868 @@
+/*******************************************************************************
+ * Copyright (C) 2014, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description: definition of clock name and frequency for zx297520
+ * Others:
+ * Version: v1.0
+ * Author: xuzhiguo
+ * Date: 2014-07-01
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_SYS_H
+#define _DRVS_SYS_H
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+/****************************************************************************
+* Types
+****************************************************************************/
+#if 0//modify by xxx def _OS_LINUX
+
+#define DRV_USE_MODEM_TYPE
+
+#include <mach/clk.h> /*use linux define*/
+
+#else
+
+#if defined (_CHIP_ZX297520V3)
+/*
+* ACLK: AXI BUS CLOCK
+* HCLK: AHB BUS CLOCK
+* PCLK: APB BUS CLOCK
+*/
+typedef enum
+{
+ /*
+ * PS mg input clock
+ */
+ CLK_PS_CORE,
+ CLK_PS_CORE_IDLE,
+ CLK_TODDR_ACLK,
+ CLK_TOMATIRX_ACLK,
+ CLK_FROMMATIRX_PCLK,
+ CLK_PSMATIRX_AXI,
+
+
+ #if 0
+ CLK_R7INT,
+ CLK_R7CRM_PCLK,
+ CLK_AXI2AXI_APB_AS_FOR_TCM,
+ CLK_AXI2AXI_AS_M1,
+ CLK_AXI2AXI_APB_AS,
+ CLK_R7CFG_APBMUX_PCLK,
+ #endif
+ /*
+ * lsp mg input clock
+ */
+ CLK_LSP32K,
+ CLK_LSP26M,
+ CLK_LSP52M,
+ CLK_LSP78M,
+ CLK_LSP124M8,
+ CLK_LSP156M,
+ CLK_LSP104M,
+ CLK_LSP122M88,
+ CLK_LSPTDM,
+ CLK_LSPAPB,
+
+ /*
+ * USB
+ */
+ /*CLK_USB_HCLK,
+ CLK_USB_CTRL_WCLK,
+ CLK_USB_12M_PHY_WCLK,
+
+ CLK_HSIC_HCLK,
+ CLK_HSIC_12M_PHY_WCLK,
+ CLK_HSIC_480M_PHY_WCLK,
+ CLK_HSIC_CTRL_WCLK,*/
+
+ /*
+ *dma
+ */
+ CLK_DMA0_PCLK,
+ CLK_DMA0_ACLK,
+
+ /*
+ * M2_AXI2AHB
+ */
+ //CLK_M2_ACLK,
+ //CLK_M2_HCLK,
+
+ /*
+ * edcp in matrix blcok
+ */
+ CLK_EDCP_HCLK,
+ CLK_EDCPASYNC_ACLK,
+ CLK_EDCPSYNC_ACLK,
+
+ /*
+ * nand
+ */
+ /*CLK_4M1SNAND_HCLK,*/
+ CLK_NAND_HCLK ,
+ CLK_NAND_WCLK,
+
+ /*
+ * sd
+ */
+ CLK_SD0_HCLK,
+ CLK_SD1_HCLK,
+
+ CLK_SD0_32K,
+ CLK_SD1_32K,
+
+ CLK_SD0_WCLK,
+ CLK_SD1_WCLK,
+
+ /*i2s in lsp*/
+ CLK_I2S0_PCLK,
+ CLK_I2S1_PCLK,
+
+ CLK_I2S0_WCLK,
+ CLK_I2S1_WCLK,
+
+ /*spifc in lsp*/
+ CLK_SPIFC_PCLK,
+ CLK_SPIFC_WCLK,
+
+ /* ssp in lsp*/
+ CLK_SSP0_PCLK,
+ CLK_SSP1_PCLK,
+
+ CLK_SSP0_WCLK,
+ CLK_SSP1_WCLK,
+
+ /*uart0 in rm,uart1&2 in lsp*/
+ CLK_UART0_PCLK,
+ CLK_UART1_PCLK,
+ CLK_UART2_PCLK,
+
+ CLK_UART0_WCLK,
+ CLK_UART1_WCLK,
+ CLK_UART2_WCLK,
+
+ /*i2c0 in rm, i2c1 in lsp*/
+ CLK_RMI2C_PCLK,
+ CLK_I2C1_PCLK,
+
+ CLK_RMI2C_WCLK,
+ CLK_I2C1_WCLK,
+
+ /*gpio0&1 in rm*/
+ CLK_GPIO0_PCLK,
+ CLK_GPIO1_PCLK,
+
+ /*gsm in rm*/
+ CLK_GSM_156M,
+ CLK_GSM_104M,
+ CLK_GSM_48M,
+ CLK_GSM_32K,
+ CLK_GSM_MAIN,
+
+ /*tdm in lsp*/
+ CLK_TDM_PCLK,
+ CLK_TDM_WCLK,
+
+ /*ps timer1&2&rm timer1 in rm, ps timer0&ps-rm timer in lsp*/
+ CLK_TIMER0_PCLK,/*ps timer0*/
+ CLK_TIMER4_PCLK,/*ps rm timer*/
+ CLK_TIMER1_PCLK,/*ps timer1*/
+ CLK_TIMER2_PCLK,/*ps timer2*/
+ CLK_TIMER3_PCLK,/*rm timer1*/
+
+ CLK_TIMER0_WCLK,/*ps timer0*/
+ CLK_TIMER4_WCLK,/*ps rm timer*/
+ CLK_TIMER1_WCLK,/*ps timer1*/
+ CLK_TIMER2_WCLK,/*ps timer2*/
+ CLK_TIMER3_WCLK,/*rm timer1*/
+
+ /*
+ * usim
+ */
+ CLK_USIM_PCLK,
+ CLK_USIM_WCLK,
+
+ /*
+ * mpll
+ */
+ CLK_MPLL_156M_CLK,
+ CLK_MPLL_48M_CLK,
+ CLK_AON_DPLL_491M52_CLK,
+
+ /*
+ * rtc
+ */
+ //CLK_RTC_PCLK,
+ //CLK_RTC_WCLK,
+
+ /*wdt in lsp*/
+ CLK_WDT_PCLK,
+ CLK_WDT_WCLK,
+
+ /*key in rm*/
+ CLK_KEY_PCLK,
+ CLK_KEY_WCLK,
+ /*VOU */
+ CLK_OSD_PCLK,
+ CLK_OSD_ACLK,
+ CLK_OSD_VEDIO_CLK,
+ CLK_OSD_GRAPHIC_CLK,
+ CLK_OSD_MAINMIX_CLK,
+ CLK_OSD_PPU_CLK,
+ CLK_CSC_WCLK,
+ CLK_CSC_PCLK,
+ CLK_VOU_ACLK,
+ CLK_VOU_PCLK,
+ CLK_VOU_WCLK,
+ CLK_MCU_WCLK,
+ CLK_MCU_PCLK,
+ /*
+ * gsmlpm
+ */
+ CLK_GSMLPM_PCLK,
+ CLK_GSMLPM_WCLK,
+
+ /*matrix ps block*/
+ CLK_PS2MATRIX_ACLK,
+ CLK_PS2DDR_ACLK,
+
+ /*matrix block*/
+ CLK_DPLL_122M88,
+
+ /*matrix ssc block*/
+ CLK_SSC_WCLK,
+ CLK_SSC_PCLK,
+ CLK_RFFE_WCLK,
+
+} T_ZDrvSysClk_Name;
+
+
+
+
+/*
+* bits domain definition for clock frequency
+* base clock name same clock number reserved clock selection frequency division
+* 31...28 27...24 23...20 19...16 15...12 11...8 7...4 3...0
+* invalid value:
+* 0xff 0xf or 0x0 0x0 or ignore 0xff 0xff
+*/
+
+typedef enum
+{
+ /*fixed frequency*/
+ FIXED_FREQ =0xffffffff,
+
+ /*ps core & ps core idle*/
+ PS_CORE_26M = (CLK_PS_CORE << 24) | 0x00200000,
+ PS_CORE_624M = (CLK_PS_CORE << 24) | 0x00200100,
+ PS_CORE_312M = (CLK_PS_CORE << 24) | 0x00200200,
+ PS_CORE_156M = (CLK_PS_CORE << 24) | 0x00200300,
+
+ /*ps matrix axi*/
+ PS_MATRIX_AXI_26M = (CLK_PSMATIRX_AXI << 24) | 0x00100000,
+ PS_MATRIX_AXI_156M = (CLK_PSMATIRX_AXI << 24) | 0x00100100,
+ PS_MATRIX_AXI_124M8 = (CLK_PSMATIRX_AXI << 24) | 0x00100200,
+ PS_MATRIX_AXI_104M = (CLK_PSMATIRX_AXI << 24) | 0x00100300,
+ PS_MATRIX_AXI_78M = (CLK_PSMATIRX_AXI << 24) | 0x00100400,
+ PS_MATRIX_AXI_52M = (CLK_PSMATIRX_AXI << 24) | 0x00100500,
+ PS_MATRIX_AXI_39M = (CLK_PSMATIRX_AXI << 24) | 0x00100600,
+ PS_MATRIX_AXI_6M5 = (CLK_PSMATIRX_AXI << 24) | 0x00100700,
+
+ /*TDM WCLK*/
+ WCLK_TDM_26M = (CLK_LSPTDM << 24) | 0x00100000,
+ WCLK_TDM_122M88 = (CLK_LSPTDM << 24) | 0x00100100,
+ WCLK_TDM_104M = (CLK_LSPTDM << 24) | 0x00100200,
+
+ /* EDCP WCLK*/
+ WCLK_EDCP_26M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100000,
+ WCLK_EDCP_208M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100100,
+ WCLK_EDCP_156M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100200,
+ WCLK_EDCP_104M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100300,
+
+ /*NAND WCLK*/
+ WCLK_NAND_26M = (CLK_NAND_WCLK << 24) | 0x00100000,
+ WCLK_NAND_104M = (CLK_NAND_WCLK << 24) | 0x00100100,
+ WCLK_NAND_78M = (CLK_NAND_WCLK << 24) | 0x00100200,
+
+ /* SD0 WCLK*/
+ WCLK_SD0_26M = (CLK_SD0_WCLK << 24) | 0x00100000,
+ WCLK_SD0_156M = (CLK_SD0_WCLK << 24) | 0x00100100,
+ WCLK_SD0_100M = (CLK_SD0_WCLK << 24) | 0x00100200,
+ WCLK_SD0_78M = (CLK_SD0_WCLK << 24) | 0x00100300,
+ WCLK_SD0_50M = (CLK_SD0_WCLK << 24) | 0x00100400,
+ WCLK_SD0_25M = (CLK_SD0_WCLK << 24) | 0x00100500,
+
+ /* SD1 WCLK*/
+ WCLK_SD1_26M = (CLK_SD1_WCLK << 24) | 0x00100000,
+ WCLK_SD1_100M = (CLK_SD1_WCLK << 24) | 0x00100100,
+ WCLK_SD1_78M = (CLK_SD1_WCLK << 24) | 0x00100200,
+ WCLK_SD1_50M = (CLK_SD1_WCLK << 24) | 0x00100300,
+ WCLK_SD1_39M = (CLK_SD1_WCLK << 24) | 0x00100400,
+ WCLK_SD1_25M = (CLK_SD1_WCLK << 24) | 0x00100500,
+
+ /* I2S0&1 WCLK*/
+ WCLK_I2S_26M = (CLK_I2S0_WCLK << 24) | 0x00200000,
+ WCLK_I2S_122M88 = (CLK_I2S0_WCLK << 24) | 0x00200100,
+ WCLK_I2S_104M = (CLK_I2S0_WCLK << 24) | 0x00200200,
+
+ /*SPIFC WCLK*/
+ WCLK_SPIFC_26M = (CLK_SPIFC_WCLK << 24) | 0x00100000,
+ WCLK_SPIFC_156M = (CLK_SPIFC_WCLK << 24) | 0x00100100,
+ WCLK_SPIFC_124M8 = (CLK_SPIFC_WCLK << 24) | 0x00100200,
+ WCLK_SPIFC_104M = (CLK_SPIFC_WCLK << 24) | 0x00100300,
+ WCLK_SPIFC_78M = (CLK_SPIFC_WCLK << 24) | 0x00100400,
+ WCLK_SPIFC_52M = (CLK_SPIFC_WCLK << 24) | 0x00100500,
+
+ /* SSP0&1 WCLK*/
+ WCLK_SSP_26M = (CLK_SSP0_WCLK << 24) | 0x00200000,
+ WCLK_SSP_13M = (CLK_SSP0_WCLK << 24) | 0x00200001,
+ WCLK_SSP_6M5 = (CLK_SSP0_WCLK << 24) | 0x00200003,
+ WCLK_SSP_156M = (CLK_SSP0_WCLK << 24) | 0x00200100,
+ WCLK_SSP_78M = (CLK_SSP0_WCLK << 24) | 0x00200101,
+ WCLK_SSP_19M5 = (CLK_SSP0_WCLK << 24) | 0x00200107,
+ WCLK_SSP_104M = (CLK_SSP0_WCLK << 24) | 0x00200200,
+ WCLK_SSP_52M = (CLK_SSP0_WCLK << 24) | 0x00200201,
+
+ /*ps timer1& ps timer2& rm timer1*/
+ WCLK_AON_TIMER_32K = (CLK_TIMER1_WCLK << 24) | 0x00300000,
+ WCLK_AON_TIMER_26M = (CLK_TIMER1_WCLK << 24) | 0x00300100, /* 1 div*/
+ WCLK_AON_TIMER_13M = (CLK_TIMER1_WCLK << 24) | 0x00300101, /* 2 div*/
+
+ /*ps timer0&ps rm timer*/
+ WCLK_LSP_TIMER_32K = (CLK_TIMER0_WCLK << 24) | 0x00200000,
+ WCLK_LSP_TIMER_26M = (CLK_TIMER0_WCLK << 24) | 0x00200100, /* 1 div*/
+ WCLK_LSP_TIMER_13M = (CLK_TIMER0_WCLK << 24) | 0x00200101, /* 2 div*/
+
+ /* I2C0&1 WCLK*/
+ WCLK_I2C_26M = (CLK_RMI2C_WCLK << 24) | 0x00200000,
+ WCLK_I2C_104M = (CLK_RMI2C_WCLK << 24) | 0x00200100,
+
+ /* UART0&1&2 WCLK*/
+ WCLK_UART_26M = (CLK_UART0_WCLK << 24) | 0x00300000,
+ WCLK_UART_104M = (CLK_UART0_WCLK << 24) | 0x00300100,
+
+ /*PS WDT WCLK*/
+ WCLK_WDT_32K = (CLK_WDT_WCLK << 24) | 0x00100000,
+ WCLK_WDT_26M = (CLK_WDT_WCLK << 24) | 0x00100100,
+ WCLK_WDT_13M = (CLK_WDT_WCLK << 24) | 0x00100101,
+
+ /* USIM WCLK */
+ /* usim work clock is fixed 13MHz*/
+ /*WCLK_USIM_13M = (CLK_USIM_WCLK << 24) | 0x0010ffff,*/
+
+ /* RTC WCLK */
+ /* rtc work clock is fixed 32KHz*/
+ /*WCLK_RTC_32K = (CLK_RTC_WCLK << 24) | 0x0010ffff,*/
+
+ /* KEY WCLK */
+ /* KEY work clock is fixed 32KHz*/
+ /*WCLK_KEY_32K = (CLK_RTC_WCLK << 24) | 0x0010ffff,*/
+
+
+} T_ZDrvSysClk_Freq;
+#elif defined (_CHIP_ZX297520V2)
+/*
+* ACLK: AXI BUS CLOCK
+* HCLK: AHB BUS CLOCK
+* ACLK: APB BUS CLOCK
+*/
+typedef enum
+{
+ /*
+ * PS
+ */
+ CLK_PS_CORE,
+ CLK_PS_CORE_IDLE,
+ CLK_R7INT,
+ CLK_R7CRM_PCLK,
+ CLK_AXI2AXI_APB_AS_FOR_TCM,
+ CLK_AXI2AXI_AS_M1,
+ CLK_AXI2AXI_APB_AS,
+ CLK_R7CFG_APBMUX_PCLK,
+ CLK_FROMMATIRX_ACLK,
+ CLK_TOMATIRX_ACLK,
+ CLK_TODDR3_ACLK,
+
+ /*
+ * lsp mg input clock
+ */
+ CLK_LSP124M8,
+ CLK_LSP156M,
+ CLK_LSP104M,
+ CLK_LSP78M,
+ CLK_LSP52M,
+ CLK_LSP26M,
+ CLK_LSP32K,
+ CLK_LSPAPB,
+ CLK_LSPTDM,
+
+ /*
+ * USB
+ */
+ /*CLK_USB_HCLK,
+ CLK_USB_CTRL_WCLK,
+ CLK_USB_12M_PHY_WCLK,
+
+ CLK_HSIC_HCLK,
+ CLK_HSIC_12M_PHY_WCLK,
+ CLK_HSIC_480M_PHY_WCLK,
+ CLK_HSIC_CTRL_WCLK,*/
+
+ /*
+ *dma
+ */
+ CLK_DMA0_PCLK,
+ CLK_DMA0_ACLK,
+
+ /*
+ * M2_AXI2AHB
+ */
+ //CLK_M2_ACLK,
+ //CLK_M2_HCLK,
+
+ /*
+ * edcp
+ */
+ CLK_EDCP_HCLK,
+ CLK_EDCPASYNC_ACLK,
+ CLK_EDCPSYNC_ACLK,
+
+ /*
+ * nand
+ */
+ /*CLK_4M1SNAND_HCLK,*/
+ CLK_NAND_HCLK ,
+ CLK_NAND_WCLK,
+
+ /*
+ * sd
+ */
+ CLK_SD0_HCLK,
+ CLK_SD1_HCLK,
+
+ CLK_SD0_32K,
+ CLK_SD1_32K,
+
+ CLK_SD0_WCLK,
+ CLK_SD1_WCLK,
+
+ /*
+ * i2s
+ */
+ CLK_I2S0_PCLK,
+ CLK_I2S1_PCLK,
+
+ CLK_I2S0_WCLK,
+ CLK_I2S1_WCLK,
+
+ /*
+ * spifc
+ */
+ CLK_SPIFC_PCLK,
+ CLK_SPIFC_WCLK,
+
+ /*
+ * ssp
+ */
+ CLK_SSP0_PCLK,
+ CLK_SSP1_PCLK,
+
+ CLK_SSP0_WCLK,
+ CLK_SSP1_WCLK,
+
+ /*
+ * uart0
+ */
+ CLK_UART0_PCLK,
+ CLK_UART1_PCLK,
+ CLK_UART2_PCLK,
+
+ CLK_UART0_WCLK,
+ CLK_UART1_WCLK,
+ CLK_UART2_WCLK,
+
+ /*
+ * i2c
+ */
+ CLK_RMI2C_PCLK,
+ CLK_I2C1_PCLK,
+
+ CLK_RMI2C_WCLK,
+ CLK_I2C1_WCLK,
+
+ /*
+ * gpio
+ */
+ CLK_GPIO0_PCLK,
+ CLK_GPIO1_PCLK,
+
+ /*
+ * gsm
+ */
+ CLK_GSM_PCLK,
+ CLK_GSM_32K,
+ CLK_GSM_MAIN,
+ CLK_GSM_48M,
+ CLK_GSM_104M,
+ CLK_GSM_156M,
+ CLK_GSM_SYS_26M,
+
+ /*
+ * tdm
+ */
+ CLK_TDM_PCLK,
+ CLK_TDM_WCLK,
+
+ /*
+ * timer
+ */
+ CLK_TIMER1_PCLK,
+ CLK_TIMER2_PCLK,
+ CLK_TIMER3_PCLK,/*m0 rm timer1*/
+
+ CLK_TIMER0_PCLK,
+ CLK_TIMER4_PCLK,/*ps rm timer*/
+
+ CLK_TIMER1_WCLK,
+ CLK_TIMER2_WCLK,
+ CLK_TIMER3_WCLK,/*m0 rm timer1*/
+
+ CLK_TIMER0_WCLK,
+ CLK_TIMER4_WCLK,/*ps rm timer*/
+
+ /*
+ * usim
+ */
+ //CLK_USIM_PCLK,
+ //CLK_USIM_WCLK,
+
+ /*
+ * rtc
+ */
+ //CLK_RTC_PCLK,
+ //CLK_RTC_WCLK,
+
+ /*
+ * wdt
+ */
+ CLK_WDT_PCLK,
+ CLK_WDT_WCLK,
+
+ /*
+ * key
+ */
+ CLK_KEY_PCLK,
+ CLK_KEY_WCLK,
+
+ /*
+ * gsmlpm
+ */
+ //CLK_GSMLPM_PCLK,
+ //CLK_GSMLPM_WCLK,
+ //CLK_WIFI_BT
+} T_ZDrvSysClk_Name;
+
+
+
+
+/*
+* bits domain definition for clock frequency
+* base clock name same clock number reserved clock selection frequency division
+* 31...28 27...24 23...20 19...16 15...12 11...8 7...4 3...0
+* invalid value:
+* 0xff 0xf or 0x0 0x0 or ignore 0xff 0xff
+*/
+
+typedef enum
+{
+ /*fixed frequency*/
+ FIXED_FREQ =0xffffffff,
+ /*
+ *ps core
+ */
+ PS_CORE_624M = (CLK_PS_CORE << 24) | 0x00100000,
+ PS_CORE_26M = (CLK_PS_CORE << 24) | 0x00100100,
+ PS_CORE_491M52 = (CLK_PS_CORE << 24) | 0x00100200,
+ PS_CORE_312M = (CLK_PS_CORE << 24) | 0x00100300,
+ PS_CORE_208M = (CLK_PS_CORE << 24) | 0x00100400,
+ PS_CORE_104M = (CLK_PS_CORE << 24) | 0x00100500,
+ PS_CORE_78M = (CLK_PS_CORE << 24) | 0x00100600,
+ PS_CORE_52M = (CLK_PS_CORE << 24) | 0x00100700,
+
+ /*
+ *ps core idle
+ */
+ PS_CORE_IDLE_624 = (CLK_PS_CORE << 24) | 0x00100000,
+ PS_CORE_IDLE_26M = (CLK_PS_CORE << 24) | 0x00100100,
+ PS_CORE_IDLE_491M52 = (CLK_PS_CORE << 24) | 0x00100200,
+ PS_CORE_IDLE_312M = (CLK_PS_CORE << 24) | 0x00100300,
+ PS_CORE_IDLE_208M = (CLK_PS_CORE << 24) | 0x00100400,
+ PS_CORE_IDLE_104M = (CLK_PS_CORE << 24) | 0x00100500,
+ PS_CORE_IDLE_78M = (CLK_PS_CORE << 24) | 0x00100600,
+ PS_CORE_IDLE_52M = (CLK_PS_CORE << 24) | 0x00100700,
+
+ /* EDCP WCLK*/
+ WCLK_EDCP_208M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100000,
+ WCLK_EDCP_26M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100100,
+ WCLK_EDCP_156M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100200,
+ WCLK_EDCP_104M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100300,
+
+ /*NAND WCLK*/
+ WCLK_NAND_104M = (CLK_NAND_WCLK << 24) | 0x00100000,
+ WCLK_NAND_26M = (CLK_NAND_WCLK << 24) | 0x00100100,
+ WCLK_NAND_78M = (CLK_NAND_WCLK << 24) | 0x00100200,
+ WCLK_NAND_52M = (CLK_NAND_WCLK << 24) | 0x00100300,
+
+ /* SD0 WCLK*/
+ WCLK_SD0_200M = (CLK_SD0_WCLK << 24) | 0x00100000,
+ WCLK_SD0_26M = (CLK_SD0_WCLK << 24) | 0x00100100,
+ WCLK_SD0_156M = (CLK_SD0_WCLK << 24) | 0x00100200,
+ WCLK_SD0_100M = (CLK_SD0_WCLK << 24) | 0x00100300,
+ WCLK_SD0_78M = (CLK_SD0_WCLK << 24) | 0x00100400,
+ WCLK_SD0_50M = (CLK_SD0_WCLK << 24) | 0x00100500,
+ WCLK_SD0_178M = (CLK_SD0_WCLK << 24) | 0x00100600,
+ WCLK_SD0_25M = (CLK_SD0_WCLK << 24) | 0x00100700,
+
+ /* SD1 WCLK*/
+ WCLK_SD1_100M = (CLK_SD1_WCLK << 24) | 0x00100000,
+ WCLK_SD1_26M = (CLK_SD1_WCLK << 24) | 0x00100100,
+ WCLK_SD1_78M = (CLK_SD1_WCLK << 24) | 0x00100200,
+ WCLK_SD1_50M = (CLK_SD1_WCLK << 24) | 0x00100300,
+ WCLK_SD1_39M = (CLK_SD1_WCLK << 24) | 0x00100400,
+ WCLK_SD1_25M = (CLK_SD1_WCLK << 24) | 0x00100500,
+
+
+ /* I2S WCLK*/
+ /*I2S not be used in zx297520, so ignore it's clock*/
+ WCLK_I2S_26M = (CLK_I2S0_WCLK << 24) | 0x00200000,
+ WCLK_I2S_104M = (CLK_I2S0_WCLK << 24) | 0x00200100,
+
+ /* BLG WCLK*/
+ /* blg work clock used default 32KHz*/
+
+ /*SPIFC WCLK*/
+ WCLK_SPIFC_156M = (CLK_SPIFC_WCLK << 24) | 0x00100000,
+ WCLK_SPIFC_26M = (CLK_SPIFC_WCLK << 24) | 0x00100100,
+ WCLK_SPIFC_124M8 = (CLK_SPIFC_WCLK << 24) | 0x00100200,
+ WCLK_SPIFC_104M = (CLK_SPIFC_WCLK << 24) | 0x00100300,
+ WCLK_SPIFC_78M = (CLK_SPIFC_WCLK << 24) | 0x00100400,
+ WCLK_SPIFC_52M = (CLK_SPIFC_WCLK << 24) | 0x00100500,
+
+ /*AON TIMER WCLK timer1&timer2&timer3*/
+ WCLK_AON_TIMER_32K = (CLK_TIMER1_WCLK << 24) | 0x00300100,
+ WCLK_AON_TIMER_26M = (CLK_TIMER1_WCLK << 24) | 0x00300000, /* 1 div*/
+ WCLK_AON_TIMER_13M = (CLK_TIMER1_WCLK << 24) | 0x00300001, /* 2 div*/
+
+ /*LSP TIMER0 WCLK timer0&timer4*/
+ WCLK_LSP_TIMER_32K = (CLK_TIMER0_WCLK << 24) | 0x00200000,
+ WCLK_LSP_TIMER_26M = (CLK_TIMER0_WCLK << 24) | 0x00200100, /* 1 div*/
+ WCLK_LSP_TIMER_13M = (CLK_TIMER0_WCLK << 24) | 0x00200101, /* 2 div*/
+
+ /* RM I2C WCLK*/
+ WCLK_RMI2C_26M = (CLK_RMI2C_WCLK << 24) | 0x00100100,
+ WCLK_RMI2C_104M = (CLK_RMI2C_WCLK << 24) | 0x00100000,
+
+ /* I2C1 WCLK*/
+ WCLK_I2C1_26M = (CLK_I2C1_WCLK << 24) | 0x00100000,
+ WCLK_I2C1_104M = (CLK_I2C1_WCLK << 24) | 0x00100100,
+
+
+ /* UART WCLK*/
+ WCLK_UART0_26M = (CLK_UART0_WCLK << 24) | 0x00100100,
+ WCLK_UART0_104M = (CLK_UART0_WCLK << 24) | 0x00100000,
+
+ WCLK_UART12_26M = (CLK_UART1_WCLK << 24) | 0x00200000,
+ WCLK_UART12_104M = (CLK_UART1_WCLK << 24) | 0x00200100,
+
+ /* SSP WCLK*/
+ WCLK_SSP_0M = (CLK_SSP0_WCLK << 24) | 0x00200301,
+ WCLK_SSP_6M5 = (CLK_SSP0_WCLK << 24) | 0x00200203,
+ WCLK_SSP_13M = (CLK_SSP0_WCLK << 24) | 0x00200201,
+ WCLK_SSP_26M = (CLK_SSP0_WCLK << 24) | 0x00200200,
+ WCLK_SSP_52M = (CLK_SSP0_WCLK << 24) | 0x00200101,
+ WCLK_SSP_78M = (CLK_SSP0_WCLK << 24) | 0x00200001,
+ WCLK_SSP_156M = (CLK_SSP0_WCLK << 24) | 0x00200000,
+
+ /* WDT WCLK*/
+ WCLK_WDT_32K = (CLK_WDT_WCLK << 24) | 0x00100000,
+ WCLK_WDT_26M = (CLK_WDT_WCLK << 24) | 0x00100100,
+
+ /* USIM WCLK */
+ /* usim work clock is fixed 13MHz*/
+ /*WCLK_USIM_13M = (CLK_USIM_WCLK << 24) | 0x0010ffff,*/
+
+ /* RTC WCLK */
+ /* rtc work clock is fixed 32KHz*/
+ /*WCLK_RTC_32K = (CLK_RTC_WCLK << 24) | 0x0010ffff,*/
+
+ /* KEY WCLK */
+ /* KEY work clock is fixed 32KHz*/
+ /*WCLK_KEY_32K = (CLK_RTC_WCLK << 24) | 0x0010ffff,*/
+
+ /*AON_CLK_OUT1*/
+ /*
+ CLK_OUT1_40M = (CLK_WIFI_BT << 24) | 0x00100300,
+ CLK_OUT1_20M = (CLK_WIFI_BT << 24) | 0x00100200,
+ CLK_OUT1_26M = (CLK_WIFI_BT << 24) | 0x00100100,
+ CLK_OUT1_13M = (CLK_WIFI_BT << 24) | 0x00100000,
+ */
+
+} T_ZDrvSysClk_Freq;
+
+#endif
+
+
+typedef enum
+{
+ SYSCLK_DISABLE = 0x100, /*disable software gate */
+ SYSCLK_ENABLE, /*enable software gate */
+ SYSCLK_DISAUTO, /*disable hardware gate */
+ SYSCLK_AUTO, /*enable hardware gate */
+} T_ZDrvSysClk_Gate;
+
+
+/****************************************************************************
+* function
+****************************************************************************/
+/*******************************************************************************
+* Function: zDrvSys_PreInit
+* Description: system previous initialization
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvSys_PreInit(void);
+
+/*******************************************************************************
+* Function: zDrvSys_Initiate
+* Description: system initialization
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvSys_Initiate(void);
+
+/*******************************************************************************
+* Function: zDrvSysClk_IsEnable
+* Description: get clock software gate status
+* Parameters:
+* Input:
+* name: clock number
+*
+* Output: NULL
+*
+* Returns: 0: software gate disable
+* 1: software gate enable
+* DRV_ERR_INVALID_PARAM: invalid parameter
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvSysClk_IsEnable(T_ZDrvSysClk_Name name);
+
+
+/*******************************************************************************
+* Function: zDrvSysClk_IsAutoGate
+* Description: get clock hardware gate status
+* Parameters:
+* Input:
+* name: clock number
+*
+* Output: NULL
+*
+* Returns: 0: hardware gate disable
+* 1: hardware gate enable
+* DRV_ERR_INVALID_PARAM:invalid parameter
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvSysClk_IsAutoGate(T_ZDrvSysClk_Name name);
+
+
+/*******************************************************************************
+ * Function: zDrvSysClk_Reset
+ * Description: set logic to reset status
+ * Parameters:
+ * Input:
+ * name: clock number
+ *
+ * Output: NULL
+ *
+ * Returns: DRV_SUCCESS
+ * DRV_ERR_INVALID_PARAM
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvSysClk_Reset(T_ZDrvSysClk_Name name);
+
+/*******************************************************************************
+ * Function: zDrvSysClk_Release
+ * Description: set logic out of reset status
+ * Parameters:
+ * Input:
+ * name: clock number
+ *
+ * Output: NULL
+ *
+ * Returns: DRV_SUCCESS
+ * DRV_ERR_INVALID_PARAM
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvSysClk_Release(T_ZDrvSysClk_Name name);
+
+/*******************************************************************************
+* Function: zDrvSysClk_SetGate
+* Description: set clock gate status
+* Parameters:
+* Input:
+* name: clock number
+* gate: gate status
+* Output: NULL
+*
+* Returns: DRV_SUCCESS
+* DRV_ERR_INVALID_PARAM
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvSysClk_SetGate(T_ZDrvSysClk_Name name, T_ZDrvSysClk_Gate gate);
+
+/*******************************************************************************
+* Function: zDrvSysClk_SetFreq
+* Description: set clock frequency which defined in drvs_sys.h by T_ZDrvSysClk_Freq
+* Parameters:
+ * Input:
+ * name: clock number
+* freq: clock frequency
+* Output: NULL
+*
+* Returns: DRV_SUCCESS
+* DRV_ERR_INVALID_PARAM
+* Others:
+********************************************************************************/
+SINT32 zDrvSysClk_SetFreq(T_ZDrvSysClk_Name name, T_ZDrvSysClk_Freq freq);
+
+#endif
+
+#endif
+
diff --git a/cp/ps/driver/inc/misc/drvs_tdm.h b/cp/ps/driver/inc/misc/drvs_tdm.h
new file mode 100644
index 0000000..8e3d9e2
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_tdm.h
@@ -0,0 +1,342 @@
+/***********************************************************************
+* Copyright (C) 2016, ZTE Corporation.
+*
+* File Name: drvs_tdm.h
+* File Mark:
+* Description: TDM hal interface declaration.
+* Others:
+* Version: v1.0
+* Author: daixunkang
+* Date: 2018-02-26
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+**********************************************************************/
+#ifndef _HAL_TDM_H
+#define _HAL_TDM_H
+/*************************************************************************
+ * Include files *
+ *************************************************************************/
+#include "drvs_general.h"
+#include "drvs_io_voice.h"
+#include "drvs_i2s.h"
+/*************************************************************************
+ * Macro *
+ *************************************************************************/
+
+
+/**************************************************************************
+* Types *
+ **************************************************************************/
+#define TDM_MOD_CLK_SEL *((volatile UINT32 *)(SOC_CRM_REG_BASE+0x50))
+#define DMA_SEL_CFG *((volatile UINT32 *)(SOC_SYS_REG_BASE+0x120))
+
+typedef enum
+{
+ TDM_NORMAL_MODE,
+ TDM_LOOPBACK_MODE,
+
+ MAX_TDM_TEST_MODE
+} T_ZDrvTdm_TestMode;
+
+typedef enum
+{
+ TDM_MSB_FIRST,
+ TDM_LSB_FIRST,
+
+ MAX_FIRSTBIT
+} T_ZDrvTdm_FstBitSel;
+
+typedef enum {
+ TDM_CLK_8000 = 0x00,
+ TDM_CLK_16000 = 0x01,
+
+ TDM_MAX_CLK
+} T_ZDrvTdm_Clk;
+
+typedef enum
+{
+ TDM_1_SLOT = 0x00,
+ TDM_2_SLOT = 0x01,
+ TDM_3_SLOT = 0x02,
+ TDM_4_SLOT = 0x03,
+ TDM_5_SLOT = 0x04,
+ TDM_6_SLOT = 0x05,
+ TDM_7_SLOT = 0x06,
+ TDM_8_SLOT = 0x07,
+ TDM_9_SLOT = 0x08,
+ TDM_10_SLOT = 0x09,
+ TDM_16_SLOT = 0xa,
+ TDM_32_SLOT = 0xb,
+ TDM_64_SLOT = 0xc,
+ //TDM_128_SLOT = 0x7f,
+
+ MAX_TDM_SLOTNUM
+} T_ZDrvTdm_SlotNum;
+
+typedef enum
+{
+ TDM_TS_8CYCLE = 0x0,
+ TDM_TS_16CYCLE = 0x1,
+ TDM_TS_32CYCLE = 0x2,
+ MAX_TDM_TS_WIDTH
+} T_ZDrvTdm_TsWidth;
+
+/*TDM track select*/
+
+typedef enum
+{
+ TDM_1TS_ENABLE = 0x00,
+ TDM_2TS_ENABLE = 0x01,
+
+ MAX_TDM_TS_ENABLE
+} T_ZDrvTdm_TsEnable;
+
+typedef enum
+{
+ TDM_TX_1BIT_OFFSET = 0x01,
+ TDM_TX_2BIT_OFFSET = 0x02,
+ TDM_TX_3BIT_OFFSET = 0x03,
+ TDM_TX_4BIT_OFFSET = 0x04,
+
+ MAX_TDM_TX_OFFSET
+} T_ZDrvTdm_TxOffset;
+
+typedef enum
+{
+ TDM_RX_1BIT_OFFSET = 0x01,
+ TDM_RX_2BIT_OFFSET = 0x02,
+ TDM_RX_3BIT_OFFSET = 0x03,
+ TDM_RX_4BIT_OFFSET = 0x04,
+
+ MAX_TDM_RX_OFFSET
+} T_ZDrvTdm_RxOffset;
+
+typedef VOID(*T_ZDrvTdm_AUD_PLAY_CB)(VOID);
+/* TDM configuration */
+
+typedef enum
+{
+ TDM_FS_CLK_NEG = 0,
+ TDM_FS_CLK_POS,
+
+ MAX_FS_CLK_SELECT
+} T_ZDrvTdm_FsClkSel;
+
+typedef enum
+{
+ TDM_TX_CLK_NEG = 0,
+ TDM_TX_CLK_POS,
+
+ MAX_TX_CLK_SELECT
+} T_ZDrvTdm_TxClkSel;
+
+typedef enum
+{
+ TDM_RX_CLK_NEG = 0,
+ TDM_RX_CLK_POS,
+
+ MAX_RX_CLK_SELECT
+} T_ZDrvTdm_RxClkSel;
+
+typedef enum
+{
+ TIMING_TDM_FS_1CLK = 0,
+ TIMING_TDM_FS_2CLK,
+ TIMING_TDM_FS_3CLK,
+ TIMING_TDM_FS_4CLK,
+ TIMING_TDM_FS_32CLK = 31,
+
+ MAX_FS_WIDTH
+} T_ZDrvTdm_FsWidth;
+
+typedef enum
+{
+ TIMING_TDM_FS_HIGH = 0,
+ TIMING_TDM_FS_LOW = 1,
+
+ MAX_FS_ACTIVE
+} T_ZDrvTdm_FsActive;
+
+typedef struct
+{
+ BOOL bMaster; /* TRUE: master mode; FALSE: slave mode */
+ UINT32 sample_rate;
+ T_ZDrvTdm_FsClkSel fsClkSel;
+ T_ZDrvTdm_TxClkSel txClkSel;
+ T_ZDrvTdm_RxClkSel rxClkSel;
+ T_ZDrvTdm_TsWidth tTsWidth; /*T_ZDrvTDM_TsWidth*/
+ T_ZDrvTdm_SlotNum tSlotNum;
+ T_ZDrvTdm_FsWidth tFsWidth;
+ T_ZDrvTdm_FsActive tFsActive;
+ T_ZDrvTdm_FstBitSel tTdmFstBit;
+ T_ZDrvTdm_TestMode tTestMode;
+ T_ZDrvTdm_TsEnable tTsEnable;
+ T_ZDrvTdm_TxOffset tTxOffset;
+ T_ZDrvTdm_RxOffset tRxOffset;
+ //T_Tdm_RefClkForTdm refclk;
+
+} T_ZDrvTdm_Cfg;
+
+typedef struct
+{
+ T_ZDrvAudio_Channel channel;
+ UINT32 buffersize;
+ T_ZDrvTdm_AUD_PLAY_CB p_cb;
+} T_ZDrvTdm_Params;
+
+/**************************************************************************
+ * Global Variable *
+ **************************************************************************/
+
+
+/**************************************************************************
+ * Function Prototypes *
+ **************************************************************************/
+/**************************************************************************
+* Function: zDrvTDM_Open
+* Description: This function is used to open a specified TDM device.
+* Parameters:
+* (IN)
+* tId: TDM index
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERR_NOT_SUPPORTED: this device don't support ioctrl operation.
+* DRV_ERR_INVALID_PARAM: the input parameters are invalid
+* DRV_ERR_OPEN_TIMES: has already been opened
+* DRV_ERROR: error
+* others: others programmer defined error code. for detailed information, please contact with the programmer
+* Others:
+* others error code should be a negative number, and not equal to the value that already be defined in T_ZDrv_ErrCode in drv_pub.h.
+**************************************************************************/
+SINT32 zDrvTdm_Open(T_ZDrvI2s_TransMode tdmTransMode);
+
+SINT32 zDrvTdm_Reset();
+
+/**************************************************************************
+* Function: zDrvTDM_Close
+* Description: This function is used to close a specified TDM device.
+* Parameters:
+* (IN)
+* tId: TDM index
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERR_NOT_SUPPORTED: this device don't support ioctrl operation.
+* DRV_ERR_NOT_OPENED: has not been opend yet.
+* DRV_ERR_INVALID_PARAM: the input parameters are invalid
+* DRV_ERROR: error
+* others: others programmer defined error code. for detailed information, please contact with the programmer
+* Others:
+* others error code should be a negative number, and not equal to the value that already be defined in T_ZDrv_ErrCode in drv_pub.h.
+* must match the use of zDrvTDM_Open.
+**************************************************************************/
+SINT32 zDrvTdm_Close();
+
+/**************************************************************************
+* Function: zDrvTDM_Start
+* Description: This function is used to start TDM.
+* Parameters:
+* (IN)
+* tId: TDM index
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERR_NOT_SUPPORTED: this device don't support ioctrl operation.
+* DRV_ERR_NOT_OPENED: has not been opend yet.
+* DRV_ERR_START_TIMES: has been started already.
+* DRV_ERR_INVALID_PARAM: the input parameters are invalid
+* DRV_ERROR: error
+* others: others programmer defined error code. for detailed information, please contact with the programmer
+* Others:
+* others error code should be a negative number, and not equal to the value that already be defined in T_ZDrv_ErrCode in drv_pub.h.
+**************************************************************************/
+SINT32 zDrvTdm_Start(UINT32 buf_size);
+
+/**************************************************************************
+* Function: zDrvTDM_Stop
+* Description: This function is used to stop TDM.
+* Parameters:
+* (IN)
+* tId: TDM index
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERR_NOT_SUPPORTED: this device don't support ioctrl operation.
+* DRV_ERR_NOT_STARTED: has not been started yet.
+* DRV_ERR_INVALID_PARAM: the input parameters are invalid
+* DRV_ERROR: error
+* others: others programmer defined error code. for detailed information, please contact with the programmer
+* Others:
+* others error code should be a negative number, and not equal to the value that already be defined in T_ZDrv_ErrCode in drv_pub.h.
+* must match the use of zDrvTDM_Start.
+**************************************************************************/
+SINT32 zDrvTdm_Write_Stop();
+SINT32 zDrvTdm_Read_Stop();
+
+/**************************************************************************
+* Function: zDrvTDM_Read
+* Description: This function is used to read data by TDM.
+* Parameters:
+* (IN)
+* tId: TDM index
+* uiLen: buffer length
+* (OUT)
+* pBuf: pointer to the read data buffer
+* Returns:
+* the real byte number of read data if successed
+* DRV_ERR_NOT_SUPPORTED: this device don't support ioctrl operation.
+* DRV_ERR_NOT_STARTED: has not been started yet.
+* DRV_ERR_INVALID_PARAM: the input parameters are invalid
+* DRV_ERROR: error
+* others: others programmer defined error code. for detailed information, please contact with the programmer
+* Others:
+* others error code should be a negative number, and not equal to the value that already be defined in T_ZDrv_ErrCode in drv_pub.h.
+**************************************************************************/
+SINT32 zDrvTdm_Read(UINT8 **pBuf, UINT32 *uiLen);
+
+/**************************************************************************
+* Function: zDrvTDM_Write
+* Description: This function is used to write data by TDM.
+* Parameters:
+* (IN)
+* tId: TDM index
+* pBuf: pointer to the read data buffer
+* uiLen: buffer length
+* (OUT)
+* None.
+* Returns:
+* the real byte number of write data if successed
+* DRV_ERR_NOT_SUPPORTED: this device don't support ioctrl operation.
+* DRV_ERR_NOT_STARTED: has not been started yet.
+* DRV_ERR_INVALID_PARAM: the input parameters are invalid
+* DRV_ERR_BUSY: now is transfering data
+* DRV_ERROR: error
+* others: others programmer defined error code. for detailed information, please contact with the programmer
+* Others:
+* others error code should be a negative number, and not equal to the value that already be defined in T_ZDrv_ErrCode in drv_pub.h.
+**************************************************************************/
+SINT32 zDrvTdm_Write(const UINT8 *pBuf, UINT32 uiLen);
+
+SINT32 zDrvTdm_Write_Start(T_ZDrvTdm_Params *params, T_ZDrvTdm_Cfg *ptCfg);
+SINT32 zDrvTdm_Read_Start(T_ZDrvTdm_Params *params, T_ZDrvTdm_Cfg *ptCfg);
+SINT32 zDrvTdm_Vousb_Start(T_ZDrvTdm_Params *params, T_ZDrvTdm_Cfg *ptCfg);
+
+SINT32 zDrvTdm_GetBuf(UINT8 **pBuf, UINT32 *uiLen);
+SINT32 zDrvTdm_GetRemained(UINT32 *len);
+SINT32 zDrvTdm_FreeBuf(UINT8 *pBuf);
+VOID zDrvTdm_Pause();
+VOID zDrvTdm_Resume();
+
+VOID zDrvTdm_RxRlsSemaBeforeStop();
+VOID zDrvTdm_TxRlsSemaBeforeStop();
+
+#endif /* _HAL_TDM_H */
diff --git a/cp/ps/driver/inc/misc/drvs_timer.h b/cp/ps/driver/inc/misc/drvs_timer.h
new file mode 100644
index 0000000..0738e06
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_timer.h
@@ -0,0 +1,300 @@
+/*******************************************************************************
+ * Copyright (C) 2014, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description: all function defines provided by sys module
+ * Others:
+ * Version: 1.0
+ * Author: limeifeng
+ * Date: 2014-01-17
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_TIMER_H
+#define _DRVS_TIMER_H
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#ifdef _OS_LINUX
+#include <linux/delay.h>
+#endif
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+#define SYSTIMER_INT TIMER0_INT
+
+/****************************************************************************
+* Types
+****************************************************************************/
+
+
+typedef enum _T_ZDrv_TimerId
+{
+ TIMER0 = 0,/*ps timer0--sysTick */
+ TIMER1 = 1,/*ps timer1--psm wake timer,must AON tiner**/
+ TIMER2 = 2,/*ps timer2--psm compensate timer,must AON tiner*/
+ TIMER3 = 3,/* rm timer1*/
+ TIMER4 = 4,/*ps rm timer--uicc timer*/
+ NUM_TIMERS
+}T_ZDrv_TimerId;
+
+typedef enum _T_ZDrv_TIMER_SRC_CLK
+{
+ CLK_32K = 0,
+ CLK_26M,
+}T_ZDrv_TIMER_SRC_CLK;
+
+typedef enum _T_ZDrv_TIMER_SRC_DIV
+{
+ CLK_DIV0 = 0,
+ CLK_DIV2 = 1,
+ CLK_DIV4 = 3,
+ CLK_DIV6 = 5,
+ CLK_DIV8 = 7,
+ CLK_DIV10 = 9,
+ CLK_DIV12 = 11,
+ CLK_DIV14 = 13,
+ CLK_DIV16 = 15,
+ CLK_DIV_NUM,
+}T_ZDrv_TIMER_SRC_DIV;
+
+typedef enum _T_ZDrv_CLK_PTV
+{
+ CLK_PTV0 =0, /*not divide the work clock*/
+ CLK_PTV1 , /*divide the work clock 2 times*/
+ CLK_PTV2, /*divide the work clock 4 times*/
+ CLK_PTV3, /*divide the work clock 8 times*/
+ CLK_PTV4,
+ CLK_PTV5,
+ CLK_PTV6,
+ CLK_PTV7,
+ CLK_PTV8,
+ CLK_PTV9,
+ CLK_PTV10,
+ CLK_PTV11,
+ CLK_PTV12,
+ CLK_PTV13,
+ CLK_PTV14,
+ CLK_PTV15,
+ CLK_PTV16,
+ CLK_PTV17,
+ CLK_PTV18,
+ CLK_PTV19,
+ CLK_PTV20,
+ CLK_PTV21,
+ CLK_PTV22,
+ CLK_PTV23,
+ CLK_PTV24,
+ CLK_PTV25,
+ CLK_PTV26,
+ CLK_PTV27,
+ CLK_PTV28,
+ CLK_PTV29,
+ CLK_PTV30,
+ CLK_PTV31, /*divide the work clock 2**31 times*/
+ CLK_PTV_NUM,
+}T_ZDrv_CLK_PTV;
+
+/*CLK_1MHz: src_clk=26MHz CLK_1KHz: src_clk=32KHz.*/
+typedef enum _T_ZDrv_TIMER_CLK
+{
+ CLK_1MHz = 0,
+ CLK_1KHz,
+ TIMER_CLK_NUM,
+}T_ZDrv_TIMER_CLK;
+
+typedef VOID (*ZDRV_TIMER_CALLBACK)(VOID);
+typedef VOID (*ZDRV_TIMER_ISR_CALLBACK)( UINT32 uiTimerId );
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+
+
+/*******************************************************************************
+ * Function: zDrvTimer_Stamp
+ * Description:¸Ãº¯ÊýÓÃÓÚ»ñȡϵͳtimerÆô¶¯ºóµÄϵͳÕý³£ÔËÐеľø¶Ôʱ¼ä£¬²»°üº¬ÏµÍ³¹ØÖжÏ
+ * ³¬¹ý1ms£¬ÒÔ¼°ÏµÍ³Ë¯ÃßµÄʱ¼ä²¹³¥¡£
+ * Parameters:
+ * Input:
+ *
+ * Output: ϵͳÔËÐÐʱ¼ä£¬26M(µ¥Î»:us) 32K(µ¥Î»:ms)
+ *
+ * Returns:
+ *
+ * Others:
+ ********************************************************************************/
+UINT32 zDrvTimer_Stamp( VOID );
+
+/**************************************************************************
+* Functin: zDrvTimer_Create
+* Description: This function is used to create a timer.
+* Parameters:
+* (IN)
+* pCallback: callback function pointer.
+* bPeriod: if auto-restart after the interval val reached zero
+* (OUT)
+* None.
+* Returns:
+* timer id if successed. [1, timers number )
+* DRV_ERROR if failed.
+* Others:
+* None.
+**************************************************************************/
+SINT32 zDrvTimer_Create( ZDRV_TIMER_CALLBACK pCallback, BOOL bPeriod );
+
+
+/**************************************************************************
+* Functin: zDrvTimer_Release
+* Description: This function is used to release a timer.
+* Parameters:
+* (IN)
+* uiTimerId: the id of created timer.
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERROR if failed.
+* Others:
+* None.
+**************************************************************************/
+SINT32 zDrvTimer_Release( UINT32 uiTimerId );
+
+/**************************************************************************
+* Functin: zDrvTimer_Start
+* Description: This function is used to start a timer.
+* Parameters:
+* (IN)
+* uiTimerId: the id of created timer.
+* uiDuration: time length. Unit: us
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERROR if failed.
+* Others:
+* None.
+**************************************************************************/
+SINT32 zDrvTimer_Start( UINT32 uiTimerId, UINT32 uiDuration );
+
+/*******************************************************************************
+ * Function:zDrvTimer_SetWorkClk
+ * Description:ÉèÖÃTIMER_ID µÄʱÖÓԴƵÂÊÊ¡µçרÓã¬ÆäËüÄ£¿é²»ÔÊÐíµ÷ÓÃ
+ * Parameters:
+ * Input:TIMER_ID : Timer ID , zDrvTimer_Open µÄÈë²Î¡£
+ * tick: CLK_1MHz£¬Ê±ÖÓÔ´Ñ¡Ôñ26M¡£
+ CLK_1KHz£¬ ʱÖÓÔ´Ñ¡Ôñ32K¡£
+ * Output:³É¹¦·µ»ØDRV_SUCCESS£¬ÆäËûÖµ±íʾʧ°ÜÔÒò¡£
+ *
+ * Returns:
+ *
+ *
+ * Others:Ê¡µçרÓã¬ÆäËüÄ£¿é²»ÔÊÐíµ÷ÓÃ!!!
+ ********************************************************************************/
+SINT32 zDrvTimer_SetWorkClk(T_ZDrv_TimerId TIMER_ID, T_ZDrv_TIMER_CLK tick);
+/*******************************************************************************
+* Function: zDrvTimer_SetCallBack
+* Description: ¿ÉÒÔÔÚzDrvTimer_StartTimerº¯ÊýÖÐÉ趨»Øµ÷º¯Êý¶ø²»Óô˺¯Êý
+* ´Ëº¯ÊýÌṩһÖÖÔÚzDrvTimer_StartTimerÖ®Íâ×¢²á»Øµ÷µÄ·½·¨¡£
+* Parameters:
+* Input:uiTimerId : Timer ID , zDrvTimer_Open µÄ·µ»ØÖµ
+* fIsrCb: Ï£ÍûÔÚ¶¨Ê±µ½0ʱµÄtimerÖжÏISRÖÐÖ´ÐеĻص÷º¯Êý¡£
+* Output:
+*
+* Returns:
+*
+* Others:Ê¡µçרÓã¬ÆäËüÄ£¿é²»ÔÊÐíµ÷ÓÃ!!!
+********************************************************************************/
+SINT32 zDrvTimer_SetCallBack(T_ZDrv_TimerId uiTimerId, ZDRV_TIMER_ISR_CALLBACK fIsrCb);
+
+/*******************************************************************************
+ * Function:zDrvTimer_Open
+ * Description:µ÷ÓÃÁ÷³Ì:zDrvTimer_Open->zDrvTimer_SetWorkClk->zDrvTimer_StartTimer->zDrvTimer_Close
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:Ê¡µçרÓã¬ÆäËüÄ£¿é²»ÔÊÐíµ÷ÓÃ
+ ********************************************************************************/
+SINT32 zDrvTimer_Open( T_ZDrv_TimerId TIMER_ID);
+/*******************************************************************************
+ * Function:zDrvTimer_Close
+ * Description:¹Ø±Õ¶ÔÓ¦¶¨Ê±Æ÷²¢Ð¶ÔØÖжÏ
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:³É¹¦·µ»ØDRV_SUCCESS£¬ÆäËûÖµ±íʾʧ°ÜÔÒò¡£
+ *
+ *
+ * Others:Ê¡µçרÓã¬ÆäËüÄ£¿é²»ÔÊÐíµ÷ÓÃ!!!
+ ********************************************************************************/
+SINT32 zDrvTimer_Close( T_ZDrv_TimerId uiTimerId );
+/*******************************************************************************
+ * Function:zDrvTimer_StartTimer
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:³É¹¦·µ»ØDRV_SUCCESS£¬ÆäËûÖµ±íʾʧ°ÜÔÒò¡£
+ *
+ *
+ * Others:Ê¡µçרÓã¬ÆäËüÄ£¿é²»ÔÊÐíµ÷ÓÃ!!!
+ ********************************************************************************/
+SINT32 zDrvTimer_StartTimer( T_ZDrv_TimerId uiTimerId, UINT32 uiDuration, BOOL bPeriod , ZDRV_TIMER_ISR_CALLBACK fIsrCb );
+
+/*******************************************************************************
+ * Function:zDrvTimer_Remain
+ * Description:²éѯµ±Ç°¶¨Ê±Æ÷Ê£Óඨʱʱ¼ä¡£
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:Ê£Óඨʱʱ¼ä£¬µ¥Î»¸ù¾ÝzDrvTimer_SetWorkClkº¯ÊýÉèÖõÄʱÖÓԴƵÂÊÈ·¶¨
+ * ʱÖÓԴΪ1M_HZʱµ¥Î»Îªus£¬1K_HZʱµ¥Î»Îªms¡£
+ *
+ *
+ * Others:Ê¡µçרÓã¬ÆäËüÄ£¿é²»ÔÊÐíµ÷ÓÃ!!!
+ ********************************************************************************/
+UINT32 zDrvTimer_Remain( T_ZDrv_TimerId uiTimerId );
+/*******************************************************************************
+ * Function:zDrvTimer_StopTimer
+ * Description:Í£Ö¹¶¨Ê±Æ÷¼Æʱ¡£
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:³É¹¦·µ»ØDRV_SUCCESS£¬ÆäËûÖµ±íʾʧ°ÜÔÒò¡£
+ *
+ *
+ * Others:Ê¡µçרÓã¬ÆäËüÄ£¿é²»ÔÊÐíµ÷ÓÃ!!!
+ ********************************************************************************/
+SINT32 zDrvTimer_StopTimer( T_ZDrv_TimerId uiTimerId );
+#endif/*_DRVS_TIMER_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_tsc.h b/cp/ps/driver/inc/misc/drvs_tsc.h
new file mode 100644
index 0000000..634be99
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_tsc.h
@@ -0,0 +1,235 @@
+/*******************************************************************************
+ * Copyright (C) 2014, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: v1.0
+ * Author:
+ * Date: 2015-09-11
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_TSC_H
+#define _DRVS_TSC_H
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "ram_config.h"
+
+/****************************************************************************
+* Types
+****************************************************************************/
+ typedef enum _T_TsCtrl_Probe
+{
+ PROBE_ADC1 = 0,
+ PROBE_ADC2,
+ PROBE_RESEV1,
+ PROBE_RESEV2,
+ PROBE_RESEV3,
+ PROBE_RESEV4,
+ PROBE_MAX,
+} Ts_TsCtrl_Probe;
+
+ typedef enum _T_Ts_Temp_interregional
+ {
+ TS_TEMP_INTERVAL_T0 = 0,
+ TS_TEMP_INTERVAL_T1,
+ TS_TEMP_INTERVAL_T2,
+ TS_TEMP_INTERVAL_T3,
+ TS_TEMP_INTERVAL_T4,
+ TS_TEMP_INTERVAL_T5,
+ TS_TEMP_INTERVAL_T6,
+ TS_TEMP_INTERVAL_T7,
+ TS_TEMP_INTERVAL_MAX
+ }Ts_Temp_interregional;
+ typedef enum
+ {
+ TS_TEMP_VALUE_TABLE_NUMBER = 0,
+ TS_TEMP_VOLTAGE_TABLE_NUMBER = 1,
+ TS_TEMP_TABLE_NUMBER_MAX
+ }TS_TEMP_TABLE_NUMBER;
+
+ typedef enum _T_Ts_Member
+ {
+ TS_MEMBER_PROBE = 0,
+ TS_MEMBER_TEMP,
+
+ TS_MEMBER_MAX,
+ } Ts_Member;
+
+
+ typedef enum _T_TsCtrl_Strategy_Id
+{
+ PS_STRATEGY_RATE = 0,
+ PS_STRATEGY_ANYRESIDENT,
+ WIFI_STRATEGY,
+ CHARGER_STRATEGY,
+ AP_RATE,
+ MAX_TSCTRL_STRATEGY_ID
+} T_TsCtrl_Strategy_ModuleId;
+
+/**************************************************
+ 0--STRTEGY_STOP: ֹͣ
+ 1--STRTEGY_START: ¿ªÊ¼
+ 2--STRTEGY_HOLD: HOLD֮ǰ²ßÂÔ
+**************************************************/
+ typedef enum _T_TsCtrl_Strategy
+ {
+ STRTEGY_STOP = 0,
+ STRTEGY_START=1,
+ STRTEGY_HOLD=2,
+
+ STRTEGY_MAX,
+ } Ts_TsCtrlStrategy;
+ /****************************************************************************
+ * Global Function Prototypes
+ ****************************************************************************/
+typedef struct _T_ZDrvTsc_Opt
+{
+ VOID (*tsc_RefGetAdcvalue)(SINT32 adcValue, UINT32 *temp);
+ VOID (*tsc_RefSetProbeStr)(UINT32 probe_num,UINT32 temperature );
+ VOID (*tsc_RefStrategyDispatch)(VOID);
+
+}T_ZDrvTsc_Opt;
+/****************************************************************************
+* macro define
+****************************************************************************/
+#define tsc_SetRegBit(regName, bitAddr, bitValue) \
+ do{ \
+ if(bitValue == TRUE) \
+ reg32(regName) |= (0x1<<bitAddr); \
+ else \
+ reg32(regName) &= ~(0x1<<bitAddr); \
+ }while(0)
+
+#define tsc_SetRegBits(regName, bitsAddr, bitsLen, bitsValue) \
+ do{ \
+ reg32(regName) = (reg32(regName)&(~(((0x1<<bitsLen)-0x1)<<bitsAddr)))|(bitsValue<<bitsAddr);\
+ }while(0)
+
+
+/**/
+#define STRATEGY_PHY_NUM 8
+#define BITS_FOR_PHYIRAM 1
+/*TSCTRL_PHY iram ÿһbit±íʾPHYµÄÒ»¸ö²ßÂÔÊÇ·ñÖ´ÐÐ*/
+#define BIT_LIMIT_LTE_DOWNRATE1 0
+#define BIT_LIMIT_LTE_DOWNRATE2 1
+#define BIT_LIMIT_W_DOWNRATE1 2
+#define BIT_LIMIT_W_DOWNRATE2 3
+#define BIT_LIMIT_LTE_UPTRANSIMITPOWER1 4
+#define BIT_LIMIT_LTE_UPTRANSIMITPOWER2 5
+#define BIT_LIMIT_W_UPTRANSIMITPOWER1 6
+#define BIT_LIMIT_W_UPTRANSIMITPOWER2 7
+/**/
+//#define STRATEGY_PS_NUM 2
+#define BITS_FOR_PSIRAM 4
+/*TSCTRL_PS iram ÿËÄbit±íʾPSµÄÒ»¸ö²ßÂÔÊÇ·ñÖ´ÐÐ*/
+#define BIT_PS_RATE 0
+#define BIT_PS_ANYRESIDENT 4
+#define BIT_SHUTDOWN 8
+/**/
+//#define STRATEGY_PERIP_NUM 2
+#define BITS_FOR_PEPIPIRAM 4
+/*TSCTRL_PERIP iram ÿËÄbit±íʾTSCTRL_PERIPµÄÒ»¸ö²ßÂÔÊÇ·ñÖ´ÐÐ*/
+#define BIT_WIFI 0
+#define BIT_CHHRGER 4
+#define BIT_APRATE 8
+
+/**/
+//#define STRATEGY_AP_NUM 2
+#define BITS_FOR_APPIRAM 4
+/*TSCTRL_AP iram ÿËÄbit±íʾAPµÄÒ»¸ö²ßÂÔÊÇ·ñÖ´ÐÐ*/
+
+
+/*TSCTRL_PHY iramInfo:ÿһbit±íʾPHYµÄÒ»¸ö²ßÂÔÊÇ·ñÖ´ÐÐ
+bit0:limit_ltedownrate1 1:ÏÞÖÆlteÏÂÐÐËÙÂÊ1£»0:Í£Ö¹ÏÞÖÆlteÏÂÐÐËÙÂÊ1
+bit1:limit_ltedownrate2 1:ÏÞÖÆlteÏÂÐÐËÙÂÊ2£»0:Í£Ö¹ÏÞÖÆlteÏÂÐÐËÙÂÊ2
+bit2:limit_wdownrate1 1:ÏÞÖÆwÏÂÐÐËÙÂÊ1£»0:Í£Ö¹ÏÞÖÆwÏÂÐÐËÙÂÊ1
+bit3:limit_wdownrate2 1:ÏÞÖÆwÏÂÐÐËÙÂÊ2£»0:Í£Ö¹ÏÞÖÆwÏÂÐÐËÙÂÊ2
+bit4:limit_lteuptransmitrate1 1:ÏÞÖÆlteÉÏÐз¢É书ÂÊ1£»0:Í£Ö¹ÏÞÖÆlteÉÏÐз¢É书ÂÊ1
+bit5:limit_lteuptransmitrate2 1:ÏÞÖÆlteÉÏÐз¢É书ÂÊ2£»0:Í£Ö¹ÏÞÖÆlteÉÏÐз¢É书ÂÊ2
+bit6:limit_wuptransmitrate1 1:ÏÞÖÆwÉÏÐз¢É书ÂÊ1£»0:Í£Ö¹ÏÞÖÆwÉÏÐз¢É书ÂÊ1
+bit7:limit_wuptransmitrate2 1:ÏÞÖÆwÉÏÐз¢É书ÂÊ2£»0:Í£Ö¹ÏÞÖÆwÉÏÐз¢É书ÂÊ2
+*/
+#define TSCTRL_PHY (IRAM_BASE_ADDR_TPC+0x00)/* 1K£IRAM_BASE_ADDR_TPC++0x400--¬Â¿ØÊý¾Ý´æ·Å */
+
+/*TSCTRL_PHY+0x04--TSCTRL_PHY+0x44
+ÿ4 bit±íʾÿ¸ö̽²âµãÊÇ·ñÐèÒªÖ´ÐвßÂÔ1:Ö´ÐÐ0:²»Ö´ÐÐ;2 HOLD*/
+#define TSCTRL_PS (TSCTRL_PHY+0x04)
+#define TSCTRL_AP (TSCTRL_PHY+0x08)
+#define TSCTRL_PERIP (TSCTRL_PHY+0x0C)
+
+/*ÿ4 bit±íʾÿ¸ö̽²âµãÊÇ·ñÐèÒªÖ´ÐвßÂÔ1:Ö´ÐÐ0:²»Ö´ÐÐ;2 HOLD*/
+#define TSCTRL_LIMIT_LTE_DOWNRATE1 (TSCTRL_PHY+0x10) /*²ßÂÔA*/
+#define TSCTRL_LIMIT_LTE_DOWNRATE2 (TSCTRL_PHY+0x14) /*²ßÂÔB*/
+#define TSCTRL_LIMIT_W_DOWNRATE1 (TSCTRL_PHY+0x18) /*²ßÂÔA*/
+#define TSCTRL_LIMIT_W_DOWNRATE2 (TSCTRL_PHY+0x1c) /*²ßÂÔB*/
+#define TSCTRL_LIMIT_LTE_UPTRANSIMITPOWER1 (TSCTRL_PHY+0x20) /*²ßÂÔC*/
+#define TSCTRL_LIMIT_LTE_UPTRANSIMITPOWER2 (TSCTRL_PHY+0x24) /*²ßÂÔD*/
+#define TSCTRL_LIMIT_W_UPTRANSIMITPOWER1 (TSCTRL_PHY+0x28) /*²ßÂÔC*/
+#define TSCTRL_LIMIT_W_UPTRANSIMITPOWER2 (TSCTRL_PHY+0x2c) /*²ßÂÔD*/
+#define TSCTRL_PS_RATE (TSCTRL_PHY+0x30) /*²ßÂÔE*/
+#define TSCTRL_PS_ANYRESIDENT (TSCTRL_PHY+0x34) /*²ßÂÔF*/
+#define TSCTRL_SHUTDOWN (TSCTRL_PHY+0x38) /*²ßÂÔG*/
+#define TSCTRL_WIFI (TSCTRL_PHY+0x3c) /*²ßÂÔF*/
+#define TSCTRL_CHARGER (TSCTRL_PHY+0x40) /*²ßÂÔF*/
+#define TSCTRL_APRATE (TSCTRL_PHY+0x44) /*²ßÂÔF*/
+#define TSCTRL_DFS (TSCTRL_PHY+0x48) /*²ßÂÔDFS*/
+
+/*ÿ¸ö̽Õë¶Ô²ßÂԵĿª¹ØÐÅÏ¢ÔÚ´æ´¢²ßÂÔIRAMµÄÆðʼbitλ*/
+#define BITS_FOR_PROBES 4
+#define BIT_PROBE_ADC1 (PROBE_ADC1*BITS_FOR_PROBES)
+#define BIT_PROBE_ADC2 (PROBE_ADC2*BITS_FOR_PROBES)
+#define BIT_PROBE_RESEV1 (PROBE_RESEV1*BITS_FOR_PROBES)
+#define BIT_PROBE_RESEV2 (PROBE_RESEV2*BITS_FOR_PROBES)
+#define BIT_PROBE_RESEV3 (PROBE_RESEV3*BITS_FOR_PROBES)
+#define BIT_PROBE_RESEV (PROBE_RESEV4*BITS_FOR_PROBES)
+
+
+/*Ô¤Áô²¿·Ö¿Õ¼äÓÃÀ´´æ´¢ÐèÒªR7´«µÝµ½A9µÄÐÅÏ¢,TSCTRL_PHY+0x100--TSCTRL_PHY+0x400*/
+#define TSCTRL_TEMPADC1 (TSCTRL_PHY+0x100) /*temp adc1*/
+#define TSCTRL_TEMPADC2 (TSCTRL_PHY+0x104) /*temp adc2*/
+#define TSCTRL_TEMPREV1 (TSCTRL_PHY+0x108) /*temp rev1*/
+#define TSCTRL_TEMPREV2 (TSCTRL_PHY+0x10c) /*temp rev2*/
+#define TSCTRL_TEMPREV3 (TSCTRL_PHY+0x110) /*temp rev3*/
+#define TSCTRL_TEMPREV4 (TSCTRL_PHY+0x114) /*temp rev3*/
+#define TSCTRL_DETECT_EN (TSCTRL_PHY+0x118) /*TsNvData.DetectEn*/
+#define TSCTRL_TEMP_PERCENT (TSCTRL_PHY+0x11c) /*APrate ,g_tempPercent*/
+
+/**/
+#define PROBE_NUM PROBE_MAX
+#define PROBE_INFO 2 //fixed value, probe num and temp
+#define TS_ADC_TEMP_NUMBER 2
+#define TS_ADC_TEMP_VOLTAGE_NUMBER 110
+#define TS_TEMP_NUMBER_SMALLEST 0
+#define TS_TEMP_NUMBER_BIGGEST 96
+
+#define TSC_DEBUG_DEF
+
+#ifdef TSC_DEBUG_DEF
+#define TSC_DEBUG(s...) zOss_Printf(1,1, ##s) /*ramlog_Printf(RAMLOG_MOD_CHARGER, ##s)*/
+#else
+#define TSC_DEBUG(s...)
+#endif
+ /****************************************************************************
+* fuction extern
+****************************************************************************/
+
+typedef VOID (* T_TsCtrl_CallbackFunction)( UINT8 en ); /*en: 1,Æô¶¯²ßÂÔ£¬0,Í£Ö¹²ßÂÔ; 2: hold ²ßÂÔ*/
+SINT32 zDrvTsc_SetOpt(T_ZDrvTsc_Opt* pTscOpt);
+
+extern SINT32 zDrvTsCtrl_RegCallback(T_TsCtrl_Strategy_ModuleId module,T_TsCtrl_CallbackFunction callback);
+extern SINT32 zDrvTsc_SetTscEn(UINT8 val); //val:0xB2,οشò¿ª£» ÆäËûֵοعرÕ
+extern SINT32 zDrvTsc_GetTscEn(VOID);
+VOID zDrvTsc_GetTscTempPercent(UINT32 *percent);
+//UINT32 *zDrvTsc_GetTscDbbProbTemp(void);
+#endif
+
diff --git a/cp/ps/driver/inc/misc/drvs_tu.h b/cp/ps/driver/inc/misc/drvs_tu.h
new file mode 100644
index 0000000..7c0e782
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_tu.h
@@ -0,0 +1,83 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: hal_kpd.h
+* File Mark:
+* Description: tu hal interface declaration.
+* Others:
+* Version: v1.0
+* Author: yan junhua
+* Date: 2007-10-19
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+
+* History 2:
+**********************************************************************/
+
+#ifndef _DRVS_TU_H
+#define _DRVS_TU_H
+
+
+/*************************************************************************
+ * Include files *
+ *************************************************************************/
+
+
+/*************************************************************************
+ * Macro *
+ *************************************************************************/
+
+
+/**************************************************************************
+ * Types *
+ **************************************************************************/
+typedef enum
+{
+ TU_GP0_INT,
+ TU_GP1_INT,
+ TU_GP2_INT,
+ TU_GP3_INT,
+ TU_GP4_INT,
+ TU_T_INT1,
+ TU_T_INT2,
+
+ MAX_TU_INT
+} T_ZDrvTu_IntId;
+
+typedef VOID (*T_ZDRVTU_CALLBACK)(VOID);
+
+
+/**************************************************************************
+ * Global Variable *
+ **************************************************************************/
+
+
+/**************************************************************************
+ * Function Prototypes *
+ **************************************************************************/
+/**************************************************************************
+* Functin: zDrvTu_IntRegister
+* Description: This function is used to regist isr callback for l1g.
+* Parameters:
+* (IN)
+* tId: T_ZDrvTu_IntId.
+* fCallback: isr callback.
+* (OUT)
+* None.
+* Returns:
+* DRV_SUCCESS: successed.
+* DRV_ERR_NOT_SUPPORTED: this device don't support ioctrl operation.
+* DRV_ERR_INVALID_PARAM: the input parameters are invalid
+* DRV_ERROR: error
+* others: others programmer defined error code. for detailed information, please contact with the programmer
+* Others:
+* others error code should be a negative number, and not equal to the value that already be defined in T_ZDrv_ErrCode in drv_pub.h.
+**************************************************************************/
+SINT32
+zDrvTu_IntRegister( T_ZDrvTu_IntId tId, T_ZDRVTU_CALLBACK fCallback,UINT32 intPrio);
+
+#endif /* _DRVS_TU_H */
diff --git a/cp/ps/driver/inc/misc/drvs_uicc.h b/cp/ps/driver/inc/misc/drvs_uicc.h
new file mode 100644
index 0000000..34c5c37
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_uicc.h
@@ -0,0 +1,462 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: uicc_api.h
+ * File Mark:
+ * Description: Provide UICC module Function prototype declaration
+* and type declaration.
+ * Others:
+ * Version: 1.0
+ * Author: wangxia
+ * Date: 2008-4-18
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_UICC_H
+#define _DRVS_UICC_H
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "pub.h"
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+//#define SOC_USIM
+
+#define DRV_UICC_NOF_CLASSES 5 /*!< The number of specified card classes (A,B,C,D & E) */
+/****************************************************************************
+* Types
+****************************************************************************/
+typedef enum
+{
+ DRV_UICC_TRANSFER_SUCCEEDED,
+ DRV_UICC_TRANSFER_FAILED
+} T_ZDrvUicc_ApduReselt;
+
+/**
+ * \enum T_ZDrvUicc_ResetResult
+ * Response cause for function \ref UICC_reset.
+ */
+typedef enum
+{
+ DRV_UICC_ACTIVATION_SUCCEEDED,
+ DRV_UICC_ACTIVATION_FAILED,
+ DRV_UICC_REJECT_CARD
+} T_ZDrvUicc_ResetResult;
+
+/**
+ * \enum T_ZDrvUicc_CloseResult
+ * Response cause for function \ref UICC_close.
+ */
+typedef enum
+{
+ DRV_UICC_DEACTIVATION_SUCCEEDED,
+ DRV_UICC_DEACTIVATION_FAILED,
+ DRV_UICC_ALREADY_DEACTIVATED
+} T_ZDrvUicc_CloseResult;
+
+/**
+ * \enum T_ZDrvUicc_SetInOutCallBack
+ * Response cause for callback function \ref UICC_set_inout_callback.
+ */
+typedef enum
+{
+ DRV_CALLBACK_FUNCTION_SET, /*!< Callback function registered. */
+ DRV_CALLBACK_NOT_AVAILABLE /*!< Callback function NOT registered (or not supported). */
+} T_ZDrvUicc_SetInOutCallBack;
+
+/**
+ * \enum T_ZDrvUicc_CardSelector
+ * Card selector.
+ */
+typedef enum
+{
+ DRV_UICC_PRIMARY_CARD,
+ DRV_UICC_SECONDARY_CARD_1,
+ DRV_UICC_SECONDARY_CARD_2
+} T_ZDrvUicc_CardSelector;
+
+/**
+ * \enum T_ZDrvUicc_CommandCase
+ * Command case indicator.
+ */
+typedef enum
+{
+ DRV_UICC_CMD_CASE_1, /*!< No Tx nor Tx command. */
+ DRV_UICC_CMD_CASE_2, /*!< Rx command. */
+ DRV_UICC_CMD_CASE_3, /*!< Tx command. */
+ DRV_UICC_CMD_CASE_4 /*!< Tx and Rx command. */
+} T_ZDrvUicc_CommandCase;
+
+/**
+ * \enum T_ZDrvUicc_ResetMode
+ * Reset indicator.
+ */
+typedef enum
+{
+ DRV_UICC_COLD_RESET, /*!< Cold Reset. */
+ DRV_UICC_WARM_RESET /*!< Warm Reset (reset with RST line only). */
+} T_ZDrvUicc_ResetMode;
+
+/**
+ * \enum T_ZDrvUicc_VoltageClass
+ * Voltage CLASS selector.
+ */
+typedef enum
+{
+ DRV_UICC_CLASS_A, /*!< 5v */
+ DRV_UICC_CLASS_B, /*!< 3v */
+ DRV_UICC_CLASS_C, /*!< 1.8v */
+ DRV_UICC_CLASS_D, /*!< RFU */
+ DRV_UICC_CLASS_E /*!< RFU */
+}T_ZDrvUicc_VoltageClass;
+
+/**
+ * \enum T_ZDrvUicc_ClockStopMode
+ * Clock stop level indicator.
+ */
+typedef enum
+{
+ DRV_UICC_CLOCK_STOP_ALLOWED, /*!< Clock Stop NOT allowed. */
+ DRV_UICC_NO_PREFERRED_LEVEL, /*!< Clock allowed, no preferred level requiered. */
+ DRV_UICC_HIGH_LEVEL_PREFERRED, /*!< Clock allowed, High level preferred. */
+ DRV_UICC_LOW_LEVEL_PREFERRED, /*!< Clock allowed, Low level preferred. */
+ DRV_UICC_CLOCK_STOP_NOT_ALLOWED,/*!< Clock Stop NOT allowed. */
+ DRV_UICC_CLOCK_STOP_ONLY_HIGH, /*!< Clock Stop NOT allowed, unless at High level. */
+ DRV_UICC_CLOCK_STOP_ONLY_LOW /*!< Clock Stop NOT allowed, unless at Low level. */
+}T_ZDrvUicc_ClockStopMode;
+
+/**
+ * \enum T_ZDrvUicc_Protocol
+ * Protocol selector.
+ */
+typedef enum
+{
+ DRV_UICC_T_0, /*!< T=0 Protocol. */
+ DRV_UICC_T_1 /*!< T=1 Protocol. */
+}T_ZDrvUicc_Protocol;
+
+/**
+ * \enum T_ZDrvUicc_ComConvention
+ * Communication convention indicator.
+ */
+typedef enum
+{
+ DRV_UICC_DIRECT, /*!< Direct communication convention. */
+ DRV_UICC_INVERSE /*!< Inverse communication convention. */
+}T_ZDrvUicc_ComConvention;
+
+/**
+ * \enum T_ZDrvUicc_CardAction
+ * Card In/Out indicator.
+ */
+typedef enum
+{
+ DRV_CARD_INSERTED,
+ DRV_CARD_REMOVED
+} T_ZDrvUicc_CardAction;
+/**
+ * \}
+ */
+
+
+ /**
+ * \struct T_ZDrvUicc_ApduHeader
+ * Structure holding the APDU command header.
+ */
+typedef struct
+{
+ UINT8 cla; /*!< Command CLAss. */
+ UINT8 ins; /*!< Command INStruction. */
+ UINT8 p1; /*!< Command Parameter. */
+ UINT8 p2; /*!< Command Parameter. */
+ UINT16 lc; /*!< Tx-size. */
+ UINT16 le; /*!< Rx-Size. */
+} T_ZDrvUicc_ApduHeader;
+
+
+/**
+ * \struct T_ZDrvUicc_ApduFooter
+ * Structure holding the APDU command response 'header'.
+ */
+typedef struct
+{
+ UINT16 luicc; /*!< Actual Rx-size recived. */
+ UINT8 sw1; /*!< Received Status Word SW1. */
+ UINT8 sw2; /*!< Received Status Word SW2. */
+} T_ZDrvUicc_ApduFooter;
+
+
+/**
+ * \enum T_ZDrvUicc_CardType
+ * card type.
+ */
+typedef enum
+{
+ DRV_UICC_CARD_TYPE_2G,
+ DRV_UICC_CARD_TYPE_3G,
+
+ UICC_MAX
+ }T_ZDrvUicc_CardType;
+
+
+
+/**
+ * \struct T_ZDrvUicc_VoltageControl
+ * Voltage control structure.
+ */
+typedef struct
+{
+ T_ZDrvUicc_VoltageClass used_voltage; /*!< Actual used voltage class/level. */
+ BOOL voltage_settled; /*!< Indicates if the voltages level has
+ been settled. This can only happen
+ if the card did indicate the voltage
+ capabilities in the ATR string. */
+} T_ZDrvUicc_VoltageControl;
+
+/**
+ * \struct T_ZDrvUicc_Characteristics
+ * Protocol characteristics structure.
+ */
+typedef struct
+{
+ T_ZDrvUicc_Protocol protocol; /*!< Protocol supported and used. */
+ UINT8 f_used; /*!< The used clock rate convention factor (F). */
+ UINT8 f_offered; /*!< The offered clock rate convention factor (F). */
+ UINT8 d_used; /*!< The used baud rate adjustment factor (D). */
+ UINT8 d_offered; /*!< The offered baud rate adjustment factor (D). */
+ T_ZDrvUicc_ComConvention com_convention; /*!< The supported and used communication convention. */
+} T_ZDrvUicc_Characteristics;
+
+/**
+ * \struct T_ZDrvUicc_ElectricalProfile
+ * Electrical Baseband characteristics structure.
+ */
+typedef struct
+{
+ BOOL class_supported; /*!< Indicates if the class is supported or not. */
+ UINT16 voltage_level; /*!< Holds the voltage level given in millivolts [mV]. E.g. 1800 is
+ equivalent to 1.8v). */
+ UINT16 max_current; /*!< The maximum allowed current consumption at this voltage_level
+ given in micro Ampere (uA). E.g. 15500 is equivalent to 15.5mA. */
+} T_ZDrvUicc_ElectricalProfile;
+
+/**
+ * \struct T_ZDrvUicc_ClockProfile
+ * Baseband Clock characteristics.
+ */
+typedef struct
+{
+ UINT8 min_clock_freq; /*!< The minimum clock frequency supported by the HW. */
+ UINT8 max_clock_freq; /*!< The maximum clock frequency supported by the HW. If only
+ one frequency is supported, the min. and max. values will
+ be identical. The frequency resolution is 0.1 MHz i.e. 21h
+ is equivalent to 3.3MHz. */
+}T_ZDrvUicc_ClockProfile;
+
+/**
+ * \struct T_ZDrvUicc_HwProfile
+ * Baseband Clock characteristics.
+ */
+typedef struct
+{
+ UINT8 nof_card_slots_supported;
+ /*!< Number of card reader slots supported by HW.\n
+ * 1: Only primary slot (uicc_primary_card)\n
+ * 2: Primary and ONE additional slot (uicc_secondary_card_1)\n
+ * 3: Primary and TWO additional slots (uicc_secondary_card_1 & uicc_secondary_card_2) */
+
+ UINT8 protocol_supported;
+ /*!< Protocols supported by the DRV_UICC Handler.\n
+ * b1: T=0 supported\n
+ * b2: T=1 supported\n
+ * b3: T=x supported\n
+ * E.g. 0x03 means that both T=0 and T=1 are supported */
+
+ T_ZDrvUicc_ElectricalProfile electrical_profile[DRV_UICC_NOF_CLASSES];
+ /*!< Holds the electrical profile of the specified classes - where
+ * the max. allowed current consumption is indicated for each class. */
+
+ T_ZDrvUicc_ClockProfile clock_profile;
+ /*!< Holds the minimum and maximum clock frequencies supported by the
+ * hardware. */
+
+ BOOL extended_length;
+ /*!< Indicates the driver support of the use of extended Lc/Le.\n
+ * TRUE: extended Lc/Le is supported by the driver. The max. Tx and
+ * Rx data sizes are 65,535 and 65,536 bytes respectively.\n
+ * FALSE: extended Lc/Le is NOT supported by the driver. The max. Tx
+ * and Rx data sizes are 255 and 256 bytes respectively.\n
+ * NOTE: this feature is currently NOT supported! */
+} T_ZDrvUicc_HwProfile;
+
+typedef enum {
+ CARD_INSERTED,
+ CARD_REMOVED
+} T_UICC_CARD_ACTION;
+
+typedef enum {
+ UICC_PRIMARY_CARD,
+ UICC_SECONDARY_CARD_1,
+ // UICC_SECONDARY_CARD_2
+} T_UICC_CARD_SELECTOR;
+
+typedef enum {
+ UICC_CARD, //0
+ VSIM_CARD, //3
+ UICC_VSIM_AUTO,
+ UICC_ESIM_CARD,
+ CLOUD_CARD, //1//1
+ SOFTSIM_CARD, //2//2
+ UICC_VSIM_MAX
+} T_UICC_CARD_TYPE;
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+
+/*!
+ * Function used to exchange APDU with a card. The function will not return
+ * before the response APDU has beed received from the card or until the
+ * appropriate Working Timer has expired.
+ *
+ * \param card_selector (I) Indicates which card the requested command is meant for.
+ * \param command_case (I) Indicates which of the four command cases the current
+ * command belongs to.
+ * \param extended_length (I) Indicates the card support of the use of extended Lc/Le.
+ * The caller of this function has the responsibility of
+ * allocating the apdu_data store correcesponding to the
+ * larger of Lc and Le.\n
+ * TRUE: extended Lc/Le is supported. The max. Tx and Rx
+ * data sizes are 65,535 and 65,536 bytes respectively.\n
+ * FALSE: extended Lc/Le is NOT supported. The max. Tx and Rx
+ * data sizes are 255 and 256 bytes respectively.
+ * \param c_apdu (I) The Command APDU containing: CLA, INS, P1, P2, Lc & Le.
+ * \param r_apdu (O) The Response APDU containing: Luicc, SW1 & SW2.
+ * \param apdu_data (I/O) I: Holds Lc Tx-data to be sent to the card.
+ * O: Holds Luicc Rx-data received from the card.
+ * \return The result of the APDU command execution.
+ */
+
+extern T_ZDrvUicc_ApduReselt zDrvUicc_TransportApdu(T_ZDrvUicc_CardSelector card_selector,
+ T_ZDrvUicc_CommandCase command_case,
+ BOOL extended_length,
+ T_ZDrvUicc_ApduHeader c_apdu,
+ T_ZDrvUicc_ApduFooter *r_apdu_ptr,
+ UINT8 *apdu_data_ptr);
+
+
+/*!
+ * Function used to reset the card. The function will not return until the reset
+ * has been successfully carried out i.e. ATR string has been received or if no
+ * response to the reset is received i.e. IWT times out.
+ * \param card_selector (I) Indicates which card needs to be activated/reset.
+ * \return The outcome of the activation handling.
+ */
+ extern T_ZDrvUicc_ResetResult zDrvUicc_ResetCard(T_ZDrvUicc_CardSelector card_selector);
+
+
+/*!
+ * Function used to deactivat a given card.
+ * \param card_selector (I) Indicates which card needs to be deactivated.
+ * \return The deactivation result.
+ */
+ extern T_ZDrvUicc_CloseResult zDrvUicc_Close(T_ZDrvUicc_CardSelector card_selector);
+
+/*!
+ * Function for Informing the DRV_UICC Handler of the card characteristics of the current used card.
+ * \param card_selector (I) Indicates which card the characteristics are valid for.
+ * \param clock_stop_mode (I) Holds the Clock Stop capabilities indicated by the card.
+ * \param min_clock_freq (I) Holds the minimum acceptable clock frequency for the
+ * card/application. The frequency resolution is 0.1 MHz
+ * i.e. 21h is equivalent to 3.3MHz.
+ * \return None.
+ */
+ extern VOID zDrvUicc_CardCharacteristics(T_ZDrvUicc_CardSelector card_selector,
+ T_ZDrvUicc_ClockStopMode clock_stop_mode,
+ UINT8 min_clock_freq);
+/*!
+ * Returns an overview of the static profile of the HW related interface.
+ * \return The static characteristics (e.g. number of card slots, voltage
+ * levels, max. current cunsumption, supported transmission protocols
+ * etc.
+ */
+ extern T_ZDrvUicc_HwProfile zDrvUicc_HwProfile(VOID);
+
+/*!
+ * Used for initializing the callback function used when the in/out state of the
+ * card changes.
+ * \param inout_call_back (I) Pointer to the function to be invoked when the
+ * in/out state changes. The parameter to the call
+ * back function shall indicated the related card
+ * reader and the IN or OUT action.
+ * \return The outcome of the requested action.
+ */
+ extern T_ZDrvUicc_SetInOutCallBack zDrvUicc_SetInOutCallBack( VOID (*inout_call_back)(T_ZDrvUicc_CardAction card_action, T_ZDrvUicc_CardSelector card_selector));
+ /*!
+ * Used for initializing the callback function used when the in/out state of the
+ * card changes.
+ * \param
+ * \return The outcome of the requested action.
+ */
+ extern T_ZDrvUicc_SetInOutCallBack zDrvUicc_UninstallInOutCallBack(VOID);
+
+/*!
+ * Function used to obtain the ATR string of the current operated card. If no card
+ * is active (or if data is not available) the number of characters returned will
+ * be set to zero.
+ * \param atr Pointer to the store in which the ATR string should be located.
+ * \return Number of ATR characters.
+ */
+ extern UINT8 zDrvUicc_GetAtr(T_ZDrvUicc_CardSelector card_selector, UINT8 *atr);
+
+
+extern VOID zDrvUicc_Highisr(VOID);
+
+extern void invoke_callback(T_UICC_CARD_ACTION card_action, T_UICC_CARD_SELECTOR card_selector);
+
+typedef void (*recoverCallback_func)(void);
+void uicc_setRecover_callback(recoverCallback_func func);
+
+typedef UINT8 (*simStatuCallback_func)(void);
+void uicc_getSimStatu_callback(simStatuCallback_func func);
+#define UICC_SIM_PLUGIN 0x11
+#define UICC_SIM_PLUGOUT 0x10
+
+typedef void (*hotplugCallback_func)(UINT32);
+
+void uicc_set_hotplugCallback(hotplugCallback_func func);
+
+typedef void (*simSwitchCallback_fun)(void);
+void uicc_setUsimSwitch_callback(simSwitchCallback_fun func);
+
+SINT32 uiccramlog_Printf(const VOID *pFormat, ...);
+
+extern SINT32 ramlog_Printf(UINT16 nModNo, const VOID *pFormat, ...);
+
+#ifdef UICC_ENABLE_REALTIME_PRINT
+#define zDrvUiccRamlog_PRINTF(nModNo, s...) uiccramlog_Printf(s)
+#else
+#ifdef _USE_RAMLOG
+#define zDrvUiccRamlog_PRINTF(nModNo, s...) ramlog_Printf(nModNo, s)
+#endif
+#endif
+
+#endif /* _DRVSUICC_H */
+/** \} */
+ /* End of file. */
+
diff --git a/cp/ps/driver/inc/misc/drvs_usbPoll.h b/cp/ps/driver/inc/misc/drvs_usbPoll.h
new file mode 100644
index 0000000..01e0847
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_usbPoll.h
@@ -0,0 +1,170 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: 1.0
+ * Author: weizhgiang
+ * Date: 2010-5-18
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_USBPOLL_H
+#define _DRVS_USBPOLL_H
+
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+
+/****************************************************************************
+* Types
+****************************************************************************/
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+
+/*******************************************************************************
+ * Function: zDrvUsbPoll_Init
+ * Description:
+ 1¡¢¶Ï¿ªÓëPC²àµÄµ±Ç°Á¬½Ó
+ 2¡¢³õʼ»¯USBÄÚ²¿µÄÊý¾Ý½á¹¹
+ 3¡¢ÖØÐÂÆô¶¯Á¬½Ó£¨Æô¶¯Á¬½Óºó£¬ÒªÇózDrvUsbPoll_IsrÁ¢¼´»ñµÃ²éѯ£©
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvUsbPoll_Init(VOID);
+
+
+
+/*******************************************************************************
+ * Function: zDrvUsbPoll_isConnect
+ * Description:
+ 1¡¢ÅжÏö¾ÙÊÇ·ñÍê³É
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+BOOL zDrvUsbPoll_isConnect(VOID);
+
+
+
+/*******************************************************************************
+ * Function: zDrvUsbPoll_Isr
+ * Description:
+ 1¡¢USBÖжϴ¦Àíº¯Êý£¬ÐèÒª²»¶Ï²éѯ
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvUsbPoll_Isr(VOID);
+
+
+/*******************************************************************************
+ * Function: zDrvUsbPoll_Read
+ * Description:
+ USB¶Áº¯Êý£¬Òì²½·½Ê½¡£¼´Èç¹ûûÓжÁµ½Êý¾Ý£¬Á¢¿Ì·µ»Ø0
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvUsbPoll_Read(UINT8* pBuf,UINT32 length);
+
+
+/*******************************************************************************
+ * Function: zDrvUsbPoll_Write
+ * Description:
+ USBдº¯Êý£¬Òì²½·½Ê½¡£¼´Èç¹ûûÓжÁµ½Êý¾Ý£¬Á¢¿Ì·µ»Ø0
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvUsbPoll_Write(UINT8* pBuf,UINT32 length);
+
+/*******************************************************************************
+ * Function: usbPoll_Delay_us
+ * Description:
+ delay function
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+VOID usbPoll_Delay_us(UINT32 us);
+
+/*******************************************************************************
+ * Function: usbPoll_Delay_us
+ * Description:
+ delay function
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+VOID usbPoll_Delay_ms(UINT32 ms);
+
+#endif/*_DRVS_USBPOLL_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_usb_config.h b/cp/ps/driver/inc/misc/drvs_usb_config.h
new file mode 100644
index 0000000..38ef65c
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_usb_config.h
@@ -0,0 +1,557 @@
+/*******************************************************************************
+ * Copyright (C) 2008, ZTE Corporation.
+ *
+ * File Name: drvs_usb_config.h
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: V1.0
+ * Author: Weizhigang
+ * Date: 2009-6-18
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ ********************************************************************************/
+#ifndef _DRVS_USB_CONFIG_H
+#define _DRVS_USB_CONFIG_H
+
+/****************************************************************************
+* macro
+****************************************************************************/
+#define MAX_ENDPOINT_NUM 13 //IN&OUT ENDPOINT INCLUDE EP0
+#define MAX_INTERFACE_NUM 12 //the usb hw only have 12 endpoint set, so the max ifac num is 12
+
+#define POWER_DOMAIN_ISO (0x0010d200+0x41*4)
+#define POWER_DOMAIN_POWERON (0x0010d200+0x42*4)
+#define POWER_DOMAIN_RST (0x0010d200+0x40*4)
+
+#define SOC_CRM_BASE (0x0010c000)
+#define BOOT_SEL (0x3c)
+#define NAND_CFG (0x34)
+#define SOC_MOD_CLKEN0 (0x0010c00c)
+#define SOC_MOD_CLKEN1 (0x0010c010)
+#define SOC_MOD_RSTEN (0x0010c018)
+#define SOC_MOD_USBSTATECTRL (0x0010c05c)
+#define SOC_MOD_RSTEN1 (0x0010c064)
+
+#ifdef _USE_PSM
+#define USE_USB_PSM 1
+#endif
+#define USE_USB_PSM 1//usb²»Çø·ÖÊ¡µçÓ벻ʡµç
+
+#define CHARGER_DETECT 0
+
+
+#define USB_GET_EP_ADDR(ep_num,dir) ((dir<<7)|(ep_num))
+
+
+typedef SINT32 (*interface_bind)(UINT8* config_buf, VOID* context, UINT8 interfaceNum, UINT32 speed);
+
+/****************************************************************************
+* type
+****************************************************************************/
+//define ep transfer mode
+typedef enum _T_ZDrvUsb_EpXferMode
+{
+ EP_XFER_MODE_CPU=0, //need to change hal define!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+ EP_XFER_MODE_DMA0=1,
+ EP_XFER_MODE_DMA1REQ0=2,
+ EP_XFER_MODE_DMA1REQ1=3
+}
+T_ZDrvUsb_EpXferMode;
+
+//define ep receive mode
+typedef enum _T_ZDrvUsb_EpXferEndCondition
+{
+ EP_UNKNOW_BASE =0,
+ EP_LENGTH_BASE = 5,
+ EP_PACKET_BASE = 6,
+}
+T_ZDrvUsb_EpXferEndCondition;
+
+//define ep context
+typedef struct _T_ZDrvUsb_EpContext
+{
+ BOOL bEpIsVaild;
+ UINT32 uiEpAddr;
+ T_ZDrvUsb_EpXferMode tEpXferMode;
+ T_ZDrvUsb_EpXferEndCondition tEpXferEndCondi;
+}
+T_ZDrvUsb_EpContext;
+
+//define ep context
+typedef struct _T_ZDrvUsb_InterfacecContext
+{
+ BOOL bIfacIsVaild;
+ UINT32 uiIfacFunction;
+ T_ZDrvUsb_EpContext tInEpContext;
+ T_ZDrvUsb_EpContext tOutEpContext;
+ T_ZDrvUsb_EpContext tExtendEpContext;
+ CHAR* pIfacName;
+ interface_bind f_intf_bind;
+}
+T_ZDrvUsb_InterfacecContext;
+
+typedef struct _T_ZDrvUsb_DeviceContext
+{
+ CHAR* pVendroName;
+ CHAR* pProductName;
+ CHAR* pSerialNum;
+ UINT32 uiVID;
+ UINT32 uiPID;
+ UINT8 DeviceClass;
+ UINT8 DeviceSubClas;
+ UINT8 DeviceProtocol;
+}
+T_ZDrvUsb_DeviceContext;
+
+/*qihongfang add for usb context show on PC*/
+
+typedef struct _T_ZDrvUsb_MSType
+{
+ CHAR* pCdromName;
+ CHAR* pNandName;
+ CHAR* pSdName;
+ CHAR* pRamdiskName;
+}
+T_ZDrvUsb_MSType;
+
+typedef struct _T_ZDrvUsb_MsContext
+{
+CHAR* pVendorName;
+T_ZDrvUsb_MSType pProductName;
+CHAR* pProductRevision;
+}
+T_ZDrvUsb_MsContext;
+
+typedef struct _T_ZDrvUsb_ConfigContext
+{
+ BOOL bContextIsVaild;
+ T_ZDrvUsb_DeviceContext tDeviceContext; //we respect one config as one device
+ T_ZDrvUsb_InterfacecContext tIfacContext[MAX_INTERFACE_NUM];
+}
+T_ZDrvUsb_ConfigContext;
+
+typedef struct _T_ZDrvUsb_EcmFunctionDescriptor
+{
+ CHAR * EcmMacAddr;
+ UINT32 bmEthernetStatistics;
+ UINT16 wMaxSegmentSize;
+ UINT16 wNumberMCFilters;
+}
+T_ZDrvUsb_EcmFunctionDescriptor;
+
+typedef struct _T_ZDrvUsb_EcmContext
+{
+ BOOL bIsVaild;
+ UINT8 ifacNum_CCI;
+ T_ZDrvUsb_EcmFunctionDescriptor tEcmFuncDes;
+}
+T_ZDrvUsb_EcmContext;
+
+
+//------------------------------------------------------------------------------------------------------------------
+
+typedef enum _T_ZDrvUsb_ConfigType
+{
+ USB_CONFIG0=0,
+ USB_CONFIG1=1,
+ USB_CONFIG2=2,
+ USB_CONFIG3=3,
+ USB_CONFIG4=4,
+ USB_CONFIG5=5,
+ USB_CONFIG6=6,
+ USB_CONFIG7=7,
+ USB_CONFIG8=8,
+ USB_CONFIG9=9,
+ USB_CONFIG10=10,
+ USB_CONFIG11=11,
+ USB_MAX_CONFIG_NUM,
+ USB_CONFIG_NONE,
+ USB_CONFIG_END=0xff /* all device uninstalled */
+}
+T_ZDrvUsb_ConfigType;
+
+typedef enum _T_ZDrvUsb_OSType
+{
+ OSType_Windows=0, //means xp,vista,win7
+ OSType_Linux=1,
+ OSType_Mac=2,
+ OSType_Win8=3,
+ OS_MAX_TYPE_NUM,
+ OS_TYPE_END=0xff /* all device uninstalled */
+}
+T_ZDrvUsb_OSType;
+
+//define usb dev type
+typedef enum _T_ZDrvUsb_DevType
+{
+ USB_AT =0,
+ USB_MODEM,
+ USB_LOG,
+ USB_MAX_TYPE_NUM
+}
+T_ZDrvUsb_DevType;
+
+
+//define usb phy mode
+typedef enum _T_ZDrvUsb_PhyType
+{
+ USB_NORMAL =0,
+ USB_HSIC = 1, //usb hsic
+ USB_DWC3=2 //usb 3.0
+}
+T_ZDrvUsb_PhyType;
+
+typedef enum _T_ZDrvUsb_DRMode
+{
+ USB_NONE =0,
+ USE_USB_DEVICE =1,
+ USE_USB_HOST =2
+}
+T_ZDrvUsb_DRMode;
+
+typedef struct _T_ZDrvUsb_IP
+{
+ T_ZDrvUsb_PhyType usb_Tpye;;
+ T_ZDrvUsb_DRMode usb_DRMode;
+}
+T_ZDrvUsb_IP;
+
+typedef enum _T_ZDrvUsb_NVTYPE
+{
+ NAND_TYPE =0,
+ GLOBAL_TYPE =1
+}
+T_ZDrvUsb_NVTYPE;
+
+/****************************************************************************
+* macro module define
+****************************************************************************/
+//Main Function Define (bit1~bit15)
+#define DEV_NULL 0
+#define DEV_CDC (1<<1)
+#define DEV_NDIS (1<<2)
+#define DEV_MASSSTORAGE (1<<3)
+#define DEV_MAIN_FUNC_MASK (0x00FF)
+#define DEV_ECM_CCI (1<<4)
+#define DEV_ECM_DCI (1<<5)
+#define DEV_RNDIS_CCI (1<<6)
+#define DEV_RNDIS_DCI (1<<7)
+#define DEV_ADB (1<<8)
+
+//Sub Function Define (bit16~bit32)
+#define DEV_MASSSTORAGE_CDROM ((1<<16)|DEV_MASSSTORAGE)
+#define DEV_MASSSTORAGE_SD ((1<<17)|DEV_MASSSTORAGE)
+#define DEV_MASSSTORAGE_NAND ((1<<18)|DEV_MASSSTORAGE)
+#define DEV_MASSSTORAGE_RAMDISK ((1<<19)|DEV_MASSSTORAGE)
+
+//basic endpoint class
+#define USB_IN_EP_CPU(epNum,RcvMode) {TRUE,USB_GET_EP_ADDR(epNum,1),EP_XFER_MODE_CPU,RcvMode}
+#define USB_OUT_EP_CPU(epNum,RcvMode) {TRUE,USB_GET_EP_ADDR(epNum,0),EP_XFER_MODE_CPU,RcvMode}
+#define USB_IN_EP_DMA1REQ1(epNum,RcvMode) {TRUE,USB_GET_EP_ADDR(epNum,1),EP_XFER_MODE_DMA1REQ1,RcvMode}
+#define USB_OUT_EP_DMA1REQ1(epNum,RcvMode) {TRUE,USB_GET_EP_ADDR(epNum,0),EP_XFER_MODE_DMA1REQ1,RcvMode}
+#define USB_OUT_EP_DMA1REQ0(epNum,RcvMode) {TRUE,USB_GET_EP_ADDR(epNum,0),EP_XFER_MODE_DMA1REQ0,RcvMode}
+#define USB_NULL_EP {FALSE,0,0,0}
+
+#define USB_EP_XFER_MODE 1
+#define USB_EP_XFEREND_CONDI 2
+
+#define USB_GET_EP_XFER_MODE(epNum) usbStack_GetEpInfo(epNum,USB_EP_XFER_MODE)
+#define USB_GET_EP_XFER_END_CONDI(epNum) usbStack_GetEpInfo(epNum,USB_EP_XFEREND_CONDI)
+
+//cdc interface class
+//#define USB_IFAC_CDC_CPU(funCode,epNum,name) {TRUE,funCode,USB_IN_EP_CPU(epNum,EP_PACKET_BASE),USB_OUT_EP_CPU(epNum,EP_PACKET_BASE),USB_NULL_EP,name}
+#define USB_IFAC_CDC_CPU(funCode,epNum,name,func) {TRUE,funCode,USB_IN_EP_CPU(epNum,EP_PACKET_BASE),USB_OUT_EP_CPU(epNum,EP_PACKET_BASE),USB_NULL_EP,name,func}
+
+#define USB_IFAC_CDC_DMA(funCode,epNum,name,func) {TRUE,funCode,USB_IN_EP_DMA1REQ1(epNum,EP_PACKET_BASE),USB_OUT_EP_DMA1REQ1(epNum,EP_PACKET_BASE),USB_NULL_EP,name,func}
+
+#define USB_CCIFAC_ECM_CPU(funCode,epNum,name,func) {TRUE,funCode,USB_NULL_EP,USB_NULL_EP,USB_IN_EP_CPU(epNum,EP_PACKET_BASE),name,func}
+#define USB_DCIFAC_ECM_DMA(funCode,epNum,name,func) {TRUE,funCode,USB_IN_EP_DMA1REQ1(epNum,EP_PACKET_BASE),USB_OUT_EP_DMA1REQ1(epNum,EP_PACKET_BASE),USB_NULL_EP,name,func}
+//mass storage interface class
+#define USB_IFAC_MASS_CPU(funCode,epNum,name,func) {TRUE,funCode,USB_IN_EP_CPU(epNum,EP_LENGTH_BASE),USB_OUT_EP_CPU(epNum,EP_LENGTH_BASE),USB_NULL_EP,name,func}
+#define USB_IFAC_MASS_DMA(funCode,epNum,name,func) {TRUE,funCode,USB_IN_EP_DMA1REQ1(epNum,EP_LENGTH_BASE),USB_OUT_EP_DMA1REQ0(epNum,EP_LENGTH_BASE),USB_NULL_EP,name,func}
+
+//ndis interface class
+#define USB_IFAC_NDIS_DMA(funCode,epNum1,epNum2,name,func) {TRUE,funCode,USB_IN_EP_DMA1REQ1(epNum1,EP_PACKET_BASE),USB_OUT_EP_DMA1REQ1(epNum1,EP_PACKET_BASE),USB_IN_EP_CPU(epNum2,EP_PACKET_BASE),name,func}
+#define USB_IFAC_NDIS_CPU(funCode,epNum1,epNum2,name,func) {TRUE,funCode,USB_IN_EP_CPU(epNum1,EP_PACKET_BASE),USB_OUT_EP_CPU(epNum1,EP_PACKET_BASE),USB_IN_EP_CPU(epNum2,EP_PACKET_BASE),name,func}
+
+//rndis interface class
+#define USB_CIFAC_RNDIS_CPU(funCode,epNum,name,func) {TRUE,funCode,USB_NULL_EP,USB_NULL_EP,USB_IN_EP_CPU(epNum,EP_PACKET_BASE),name,func}
+#define USB_DIFAC_RNDIS_DMA(funCode,epNum,name,func) {TRUE,funCode,USB_IN_EP_DMA1REQ1(epNum,EP_PACKET_BASE),USB_OUT_EP_DMA1REQ1(epNum,EP_PACKET_BASE),USB_NULL_EP,name,func}
+
+//ecm interface class
+#define USB_IFAC_ECM_DMA(funCode,epNum1,epNum2,name,func) {TRUE,funCode,USB_IN_EP_DMA1REQ1(epNum1,EP_PACKET_BASE),USB_OUT_EP_DMA1REQ1(epNum1,EP_PACKET_BASE),USB_IN_EP_CPU(epNum2,EP_PACKET_BASE),name,func}
+#define USB_IFAC_ECM_CPU(funCode,epNum1,epNum2,name,func) {TRUE,funCode,USB_IN_EP_CPU(epNum1,EP_PACKET_BASE),USB_OUT_EP_CPU(epNum1,EP_PACKET_BASE),USB_IN_EP_CPU(epNum2,EP_PACKET_BASE),name,func}
+
+#define USB_IFAC_ADB_CPU(funCode,epNum,name,func) {TRUE,funCode,USB_IN_EP_CPU(epNum,EP_PACKET_BASE),USB_OUT_EP_CPU(epNum,EP_PACKET_BASE),USB_NULL_EP,name,func}
+#define USB_IFAC_ADB_DMA(funCode,epNum,name,func) {TRUE,funCode,USB_IN_EP_DMA1REQ1(epNum,EP_PACKET_BASE),USB_OUT_EP_DMA1REQ1(epNum,EP_PACKET_BASE),USB_NULL_EP,name,func}
+
+
+/*
+#ifndef _USE_AMT
+*/
+#if 0
+#if !defined(_USE_AMT)&&!defined(_USE_SMALL_VERSION)
+//#define DEFAULT_SWITCH_CONFIG_ECM USB_CONFIG1 //ECM config
+//#define DEFAULT_INSERT_CONFIG USB_CONFIG0 //first config with cdrom
+//#define DEFAULT_INSERT_CONFIG_AMT USB_CONFIG3 //amt only
+//#define DEFAULT_SWITCH_CONFIG_NDIS USB_CONFIG2 //NDIS config
+//#define DEFAULT_SWITCH_CONFIG_RNDIS USB_CONFIG4 //RNDIS CONFIG
+#else/*AMT not config NDIS device*/
+#define DEFAULT_SWITCH_CONFIG_ECM USB_CONFIG3
+#define DEFAULT_INSERT_CONFIG USB_CONFIG3
+#define DEFAULT_INSERT_CONFIG_AMT USB_CONFIG3
+#define DEFAULT_SWITCH_CONFIG_NDIS USB_CONFIG3
+#define DEFAULT_SWITCH_CONFIG_RNDIS USB_CONFIG3
+#endif
+#endif
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+/*******************************************************************************
+ * Function: zDrvUsbStack_SwitchConfiguration
+ * Description:usb to switch the usb configuration
+ * Parameters:
+ ConfigNum : the new cofig num, the value should less than macro: MAX_CONFIG_NUM
+ * Input:None
+ * Output:None
+ *
+ * Returns:
+ * Others:
+ ********************************************************************************/
+VOID zDrvUsbStack_SwitchConfiguration(T_ZDrvUsb_ConfigType ConfigNum);
+
+/*******************************************************************************
+ * Function: zDrvUsbStack_GetConfigInfo
+ * Description: user can use this function to inquire function code corresponding to the confignum
+ * Parameters:
+ * Input: config num
+ * Output:None
+ *
+ * Returns:function code, if configNum is vailed, return value is zero
+ * Others:
+ ********************************************************************************/
+UINT32 zDrvUsbStack_GetConfigInfo(UINT32 ConfigNum);
+
+/*******************************************************************************
+ * Function: zDrvUsbStack_SetMsContext
+ * Description: get Mass Storage VendorName;ProductName;and ProductRevision for diff project in ref
+ * Parameters:
+ * Input: config num
+ * Output:None
+ *
+ * Returns:function code, if configNum is vailed, return value is zero
+ * Others:
+ ********************************************************************************/
+
+VOID zDrvUsbStack_SetMsContext(T_ZDrvUsb_MsContext *MsPtr);
+
+/*******************************************************************************
+ * Function: zDrvUsbStack_GetIfacFunctionCode
+ * Description: user can use this function to inquire the specify interface function code corresponding
+ to the confignum
+ * Parameters:
+ * Input: config num
+ * Output:None
+ *
+ * Returns:function code, if configNum is vailed, return value is zero
+ * Others:
+ ********************************************************************************/
+UINT32 zDrvUsbStack_GetIfacFunctionCode(UINT32 ConfigNum, UINT32 ifacNum);
+
+/*******************************************************************************
+ * Function: usbHal_GetUsbConfigContext
+ * Description: get usb config context
+ * Parameters:
+ * Input: N/A
+ *
+ * Output: N/A
+ * Returns: N/A
+
+********************************************************************************/
+T_ZDrvUsb_ConfigContext *usbHal_GetUsbConfigContext(UINT32 ConfigNum);
+
+/*******************************************************************************
+ * Function: usbHal_GetEcmConfigContext
+ * Description: get ecm parameter
+ * Parameters:
+ * Input: N/A
+ *
+ * Output: N/A
+ * Returns: N/A
+
+ * Others: //not use
+
+ ********************************************************************************/
+T_ZDrvUsb_EcmContext * usbHal_GetEcmConfigContext(UINT8 ifacNum_CCI);
+
+/*******************************************************************************
+ * Function: usbHal_CleanEcmConfigContext
+ * Description: clean ecm parameter state
+ * Parameters:
+ * Input: N/A
+ *
+ * Output: N/A
+ * Returns: N/A
+
+ * Others: //not use
+
+ ********************************************************************************/
+VOID usbHal_CleanEcmConfigContext(VOID);
+
+/*******************************************************************************
+ * Function: usbHal_GetUsbMode
+ * Description: get usb mode hisc or normal
+ * Parameters:
+ * Input: N/A
+ *
+ * Output: N/A
+ * Returns: N/A
+
+ * Others: //not use
+
+ ********************************************************************************/
+T_ZDrvUsb_PhyType usbHal_GetUsbMode(VOID);
+
+/*******************************************************************************
+ * Function: usbStack_msSetNVflag
+ * Description: used in datecard set AT\Log\Modem flag in NV
+ * with singn whether enum it
+ * Parameters:
+ * Input: N/A
+ *
+ * Output: N/A
+ * Returns: N/A
+
+ * Others: //not use
+
+ ********************************************************************************/
+SINT32 usbStack_msSetNVflag(VOID);
+
+/*******************************************************************************
+ * Function: USBHSIC_ReConnect_Ind
+ * Description: for usb trap ind to host
+ * Parameters:
+ * Input: N/A
+ *
+ * Output: N/A
+ * Returns: N/A
+
+ * Others: //not use
+
+ ********************************************************************************/
+VOID usbHal_HSICReConnect_Ind(VOID);
+/*******************************************************************************
+* Function: zDrvUsb_GetCommDevName
+* Description:
+* Parameters:
+* Input:
+*
+* Output:
+*
+* Returns:
+*
+* Others:
+********************************************************************************/
+SINT32 zDrvUsb_GetUsbDevName(T_ZDrvUsb_DevType usbType,char * DevName,UINT8 StrSize);
+
+/*******************************************************************************
+ * Function: zDrvUsb_Work_Ahb_Phy_Reset
+ * Description:
+ *
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvUsb_Work_Ahb_Phy_Reset(VOID);
+
+/*******************************************************************************
+ * Function: zDrvUsb_PowerUp
+ * Description:
+ *
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ SINT32 zDrvUsb_PowerUp(VOID);
+
+/*******************************************************************************
+ * Function: zDrvUsb_Powerdown
+ * Description:
+ *
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ SINT32 zDrvUsb_Powerdown(VOID);
+
+/*******************************************************************************
+ * Function: zDrvUsb3_PowerUp
+ * Description:
+ *
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ SINT32 zDrvUsb3_PowerUp(VOID);
+
+/*******************************************************************************
+ * Function: zDrvUsb3_Powerdown
+ * Description:
+ *
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ SINT32 zDrvUsb3_Powerdown(VOID);
+
+/*******************************************************************************
+ * Function: pow_GetUsbLowPowerFlag
+ * Description: get usb low power flag
+ * Parameters:
+ * Input: N/A
+ *
+ * Output: N/A
+ * Returns:
+ *
+ *
+ * Others: //not use
+ ********************************************************************************/
+
+UINT32 pow_GetUsbLowPowerFlag(VOID);
+
+#endif
+
diff --git a/cp/ps/driver/inc/misc/drvs_usb_detect.h b/cp/ps/driver/inc/misc/drvs_usb_detect.h
new file mode 100644
index 0000000..ade0c43
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_usb_detect.h
@@ -0,0 +1,81 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: hal_spi.h
+ * File Mark:
+ * Description: Provide spi hal function prototype declaration and type declaration.
+ * Others:
+ * Version: V0.5
+ * Author: zhenghong
+ * Date: 2008-03-19
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _USB_DETECT_H
+#define _USB_DETECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "drvs_gpio.h"
+/****************************************************************************
+* Macros
+****************************************************************************/
+#define USB_ENUM_DEBUG_EN 1
+/**
+ * Messages sent from the Phy to the OTG driver.
+ *
+*/
+typedef enum _T_UsbHal_ConnectMessage
+{
+ CONNECTED_TO_HOST = 0x10, /**< Host connect detected */
+ DISCONNECTED_FROM_HOST, /**< Host disconnect detected */
+ CONNECTED_TO_DEVICE, /**< Function connect detected */
+ DISCONNECTED_FROM_DEVICE, /**< Function disconnect detected */
+ CHECK_CONNECT_MODE,
+ CHECK_CONNECT_QUICK_POWER_ON,
+ RECONNECT_TO_HOST
+}T_UsbHal_ConnectMessage;
+
+typedef enum _T_UsbHal_ConnectionState {
+ USB_DEVICE_UNPLUGGED=0,
+ USB_DEVICE_PLUGGED
+} T_UsbHal_ConnectionState;
+
+typedef enum _T_plug_in
+{
+ NOTHING,
+ COMPUTER,
+ CHARGER
+}plug_in;
+/****************************************************************************
+* Types
+****************************************************************************/
+typedef SINT32 (*T_ZDrvUSBRef_ChargerDetect_CallBack)(UINT32);
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+extern T_ZDrvUSBRef_ChargerDetect_CallBack g_USBRef_ChargerDetect;
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+SINT32 zDrvUsbRef_Detect_Initiate(VOID);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_HAL_SPI_H*/
diff --git a/cp/ps/driver/inc/misc/drvs_usb_switch.h b/cp/ps/driver/inc/misc/drvs_usb_switch.h
new file mode 100644
index 0000000..52f760d
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_usb_switch.h
@@ -0,0 +1,127 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: hal_spi.h
+ * File Mark:
+ * Description: Provide spi hal function prototype declaration and type declaration.
+ * Others:
+ * Version: V0.5
+ * Author: zhenghong
+ * Date: 2008-03-19
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _HAL_SPI_H
+#define _HAL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "drvs_gpio.h"
+/****************************************************************************
+* Macros
+****************************************************************************/
+#define USB_SWITCH_GPIO_OUT 0
+#define USB_SWITCH_GPIO_IN 1
+#define USB_SWITCH_PIN_MODE_FUNC 0
+#define USB_SWITCH_PIN_MODE_GPIO 1
+#define USB_SWTICH_SEL 46
+#define USB_SWTICH_OE_N 43
+#define DBB2AR9342_POWER_ON 39
+#define DBB2AR9342_RESET 48
+#define DBB2USB_DPOS_PULL_UP 7
+#define USB2DBB_DNEG_DETECT 8
+#define USB_CHAR_DET 8
+#define VTELECOM_18_ARM_UART2_RXD 33
+/****************************************************************************
+* Types
+****************************************************************************/
+/*
+OE* S HSD1+(HSD1-) HSD2+(HSD2-)
+1 X OFF OFF
+0 0 ON OFF
+0 1 OFF ON
+
+ps:HSD1+(HSD1-) connect PC;HSD2+(HSD2-) connect wifi
+OE* connect from GPIO43(ARM_I2S2_WS)
+S connect from GPIO42(ARM_I2S2_DOUT)
+*/
+typedef enum Usb_Switch_Select_Option
+{
+ USB_SWITCH_CONNECT_PC,
+ USB_SWITCH_CONNECT_WIFI,
+ USB_SWITCH_ALL_OFF,
+}T_Usb_Switch_Select_Option;
+
+typedef enum Ar9342_On_Off_Option
+{
+ Ar9342_ON,
+ Ar9342_OFF,
+}T_Ar9342_On_Off_Option;
+
+typedef enum Charger_Usbdevice
+{
+ USBCHARGER,//change to USBCHARGER because it`s the same to Charger_Usbdevice in Drvs_usb_switch.h
+ USBDEVICE,
+}Charger_Usbdevice;
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+UINT32 zDrvUsb_Switch_Select(T_Usb_Switch_Select_Option select);
+
+UINT32 zDrvSetAR9342_ON_OFF(T_Ar9342_On_Off_Option select);
+
+VOID zDrvUSB_2V8_WriteGpio(UINT32 pinNum, UINT32 Value);
+/*******************************************************************************
+ * Function: zDrvCharger_UsbDevice_Detect
+ * Function: return charger or usb device connect
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns: success or fail
+ *
+ *
+ * Others:
+********************************************************************************/
+Charger_Usbdevice zDrvCharger_UsbDevice_Detect(VOID);
+/*******************************************************************************
+ * Function: zDrvCharger_UsbDevice_Prepare
+ * Function: prepare gpio zpm_2v8_gpio08
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+********************************************************************************/
+VOID zDrvCharger_UsbDevice_Prepare(VOID);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_HAL_SPI_H*/
diff --git a/cp/ps/driver/inc/misc/drvs_voice_config.h b/cp/ps/driver/inc/misc/drvs_voice_config.h
new file mode 100644
index 0000000..c89013f
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_voice_config.h
@@ -0,0 +1,87 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: Drvs_voice_config.h
+ * File Mark:
+ * Description: Provide the interface for the voice config of refdrv
+ * Others:
+ * Version: V0.5
+ * Author: xuxinqiang
+ * Date: 2014-06-04
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef _DRVS_VPCFG_H
+#define _DRVS_VPCFG_H
+
+/*************************************************************************
+ * Include files *
+ *************************************************************************/
+
+#include "drvs_voiceprocess.h"
+#include "drvs_i2s.h"
+#include "drvs_codec.h"
+#include "drvs_tdm.h"
+
+/**************************************************************************
+ * Types *
+ **************************************************************************/
+
+
+//the size of each buffer should >=0.5MB
+typedef struct _T_ZDrv_VpInOutBuffer
+{
+ UINT8* p_voiceRxInBuffer ;/*the pcm data in the s_voiceRxInBuffer,receive from far-end. */
+ UINT8* p_voiceTxInBuffer ;/* the pcm data in the s_voiceTxInBuffer, receiver from codec.*/
+ UINT8* p_voiceRxOutPutBuffer;/* the pcm data in the s_voiceRxOutPutBuffe, will send to codec.*/
+ UINT8* p_voiceTxOutPutBuffer;/* the pcm data in the s_voiceTxOutBuffer, will send to near end.*/
+
+}T_ZDrv_VpInOutBuffer;
+
+
+typedef struct
+{
+ SINT32 (*hal_VpCfg_OpenBegin_obsolete)(VOID);
+ SINT32 (*hal_VpCfg_OpenEnd_obsolete)(VOID);
+ SINT32 (*hal_VpCfg_Close_obsolete)(VOID);
+ SINT32 (*hal_VpCfg_Open)(T_ZDrvVp_SourceType srctype);
+ SINT32 (*hal_VpCfg_Close)(VOID);
+ SINT32 (*hal_VpCfg_Enable)(VOID);
+ SINT32 (*hal_VpCfg_Disable)(VOID);
+ SINT32 (*hal_VpCfg_SetFs)(T_ZDrv_VpFs fs);
+ SINT32 (*hal_VpCfg_SetInputPath)(T_ZDrv_VpPath path,BOOL enable);
+ SINT32 (*hal_VpCfg_SetOutputPath)(T_ZDrv_VpPath path,BOOL enable);
+ SINT32 (*hal_VpCfg_SetMute)(T_ZDrv_VpPath path,BOOL mute);
+ SINT32 (*hal_VpCfg_SetFmPath)(T_ZDrv_VpPath path,BOOL enable);
+ SINT32 (*hal_VpCfg_SetLoopback)(BOOL enable);
+ SINT32 (*hal_VpCfg_SetInputVol)(T_ZDrv_VpVol vol);
+ SINT32 (*hal_VpCfg_SetOutputVol)(T_ZDrv_VpVol vol);
+ SINT32 (*hal_VpCfg_SetUseProtocol)(T_ZDrvCodec_UseProtocol useProtocol);
+ SINT32 (*hal_VpCfg_GetMixerToneInfo)(T_ZDrvVp_ToneNum toneNum,T_HalMixerToneInfo *toneInfo);
+ SINT32 (*hal_VpCfg_GetAudioLoopInfo)(T_HalAudioLoopTestInfo *audioInfo);
+ SINT32 (*hal_VpCfg_GetAudioLoopResult)(T_HalAudioLoopTestPra *audioPra);
+ SINT32 (*hal_VpCfg_SetInputMute)(BOOL mute);
+ SINT32 (*hal_VpCfg_SetOutputMute)(BOOL mute);
+
+} T_HalVpCfg_Opt;
+extern SINT32 zDrvVp_SetExtAudioCfg(T_ZDrvI2S_Cfg *pI2sNbCfg,T_ZDrvI2S_Cfg *pI2sWbCfg,
+ T_ZDrvTdm_Cfg *pTdmNbCfg,T_ZDrvTdm_Cfg *pTdmWbCfg);
+//voice config
+extern SINT32 zDrvVp_SetI2sCfg(T_ZDrvI2S_Cfg *s_VpI2sCfg);//obsolete
+extern SINT32 zDrvVp_SetExtI2sCfg(T_ZDrvI2S_Cfg *pI2sNbCfg,T_ZDrvI2S_Cfg *pI2sWbCfg);
+
+extern SINT32 zDrvVp_SetInOutBuffer(T_ZDrv_VpInOutBuffer *pInOutBuffer); //obsolete
+extern SINT32 zDrvVp_SetInOutBufferAddSize(T_ZDrv_VpInOutBuffer *pInOutBuffer,UINT32 bufSize);
+extern VOID zDrvVpCfg_SetOperations(T_HalVpCfg_Opt* VpCfg_ObjPtr);
+extern SINT32 zDrvVp_Init(VOID);
+
+extern SINT32 zDrvVoice_Initiate(VOID);
+extern SINT32 Aud_TaskInt_Init(VOID);
+
+//is usd for xinke 20150709 lvwenhua value:0~100 step:1(0.25dB)
+extern SINT32 zDrvVp_SetInitGain(UINT8 value);
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_voiceprocess.h b/cp/ps/driver/inc/misc/drvs_voiceprocess.h
new file mode 100755
index 0000000..a006449
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_voiceprocess.h
@@ -0,0 +1,304 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: Drvs_voiceprocess.h
+ * File Mark:
+ * Description: Provide the interface of using vp
+ * Others:
+ * Version: V0.5
+ * Author: lvwenhua
+ * Date: 2012-06-13
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef _DRVS_VP_H
+#define _DRVS_VP_H
+
+#include "drvs_i2s.h"
+#include "drvs_tdm.h"
+#include "drvs_volte.h"
+#include "drvs_rpmsg.h"
+#include "NvParam_drv.h"
+
+#define VOICE_TONE_MIXER_FUNCTION
+//#define TEST_WHITE_NOISE
+typedef enum
+{
+ VP_I2S_IDLE = 0,
+ VP_I2S_OPEN,
+ VP_I2S_INUSE,
+ VP_LOOP_ON
+} T_Vp_I2sStatus;
+
+/* Voice process channel selection. */
+typedef enum
+{
+ VP_PATH_HANDSET = 0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+} T_ZDrv_VpPath;
+
+typedef enum
+{
+ VP_VOL_0 = 0,
+ VP_VOL_1,
+ VP_VOL_2,
+ VP_VOL_3,
+ VP_VOL_4,
+ VP_VOL_5,
+ VP_VOL_6,
+ VP_VOL_7,
+ VP_VOL_8,
+ VP_VOL_9,
+ VP_VOL_10,
+ VP_VOL_11,
+
+ MAX_VP_VOL
+} T_ZDrv_VpVol;
+
+typedef enum
+{
+ VP_FS_8000 = 0, ///< 8k sampling rate
+ VP_FS_11025 = 1, ///< 11.025k sampling rate
+ VP_FS_12000 = 2, ///< 12k sampling rate
+ VP_FS_16000 = 3, ///< 16k sampling rate
+ VP_FS_22050 = 4, ///< 22.050k sampling rate
+ VP_FS_24000 = 5, ///< 24k sampling rate
+ VP_FS_32000 = 6, ///< 32k sampling rate
+ VP_FS_44100 = 7, ///< 44.1k sampling rate
+ VP_FS_48000 = 8, ///< 48k sampling rate
+ MAX_VP_FS = 9 ///< Max sampling rate count
+
+} T_ZDrv_VpFs;
+
+typedef enum
+{
+ VP_DTMF_KEY_0 = 0,
+ VP_DTMF_KEY_1,
+ VP_DTMF_KEY_2,
+ VP_DTMF_KEY_3,
+ VP_DTMF_KEY_4,
+ VP_DTMF_KEY_5,
+ VP_DTMF_KEY_6,
+ VP_DTMF_KEY_7,
+ VP_DTMF_KEY_8,
+ VP_DTMF_KEY_9,
+ VP_DTMF_KEY_10, /* * */
+ VP_DTMF_KEY_11, /* # */
+
+ MAX_VP_DTMF_KEY
+} T_ZDrv_VpDtmfKey;
+
+
+//typedef T_ZDrvVolte_Cfg T_ZDrvVp_Cfg
+typedef struct
+{
+ char* pPresetRx;
+ unsigned long PresetLengthRx;
+ char* pPresetTx;
+ unsigned long PresetLengthTx;
+} zDrvVp_NxpParamsTool;
+
+typedef struct
+{
+ char* pPresetRx;
+ unsigned long PresetLengthRx;
+ char* pPresetTx;
+ unsigned long PresetLengthTx;
+} zDrvVp_ParamsTool;
+
+typedef enum
+{
+ VP_VOICE_SOURCE ,
+ VP_AUDIO_SOURCE ,
+ VP_FM_SOURCE ,
+ VP_EXTERN_AUDIO,
+ VP_SOURCE_MAX
+} T_ZDrvVp_SourceType;
+
+/* 0 lowpower;1 sms;2 call standard;3 alarm beep;*/
+typedef enum
+{
+ VP_LOWPOWER_TONE ,
+ VP_SMS_TONE ,
+ VP_CALLSTD_TONE ,
+ VP_ALARM_TONE,
+ VP_CALL_TIME_TONE,
+ VP_0_KEY_TONE,
+ VP_1_KEY_TONE,
+ VP_2_KEY_TONE,
+ VP_3_KEY_TONE,
+ VP_4_KEY_TONE,
+ VP_5_KEY_TONE,
+ VP_6_KEY_TONE,
+ VP_7_KEY_TONE,
+ VP_8_KEY_TONE,
+ VP_9_KEY_TONE,
+ VP_HASH_KEY_TONE, //#
+ VP_ASTERRIX_KEY_TONE, //*
+ VP_RESERVED1_TONE,
+ VP_RESERVED2_TONE,
+ VP_RESERVED3_TONE,
+ VP_RESERVED4_TONE,
+ VP_RESERVED5_TONE,
+ VP_RESERVED6_TONE,
+ VP_TONE_MAX
+} T_ZDrvVp_ToneNum;
+typedef struct _T_HalMixerToneInfo
+{
+ BOOL StartMixer;/*mixer flag TRUE start, FALSE stop;*/
+ BOOL dataIsWb;/* TRUE wb, FALSE nb, for voice mixer;*/
+ UINT32 cur_tone_fcount;/*tone data already processed count*/
+ UINT32 tone_total_size;/*tone data total size,unit 2byte*/
+ UINT32 inter_mixer_fcount;/*inter ,tone_size/data_mixer_oncesize*/
+ UINT32 rem_mixer_count;/*remainder , tone_size%data_mixer_oncesize*/
+ UINT16 *ptdata_mixer;/* tone data array pointer */
+ UINT32 data_mixer_oncesize;/*the size of a data processing, unit 2byte*/
+} T_HalMixerToneInfo;
+
+typedef struct _T_HalAudioLoopTestInfo
+{
+ BOOL startLoopTest;/*audo loop test flag TRUE start, FALSE stop;*/
+ UINT32 fs;/*tone data real frequence*/
+ UINT32 sampFs;/*tone data sample frequence*/
+ UINT8 *ptdata;/* audo loop test data array pointer */
+ UINT32 totalSize;/*tone data total size,unit 2byte*/
+ T_ZDrv_VpVol outpathvol[4];
+
+} T_HalAudioLoopTestInfo;
+typedef struct _T_HalAudioLoopTestPra
+{
+ UINT8 *src;/*tone data frequence*/
+ UINT8 *dest;/*tone data sample frequence*/
+ UINT32 sampfs;
+
+} T_HalAudioLoopTestPra;
+typedef struct
+{
+ //use for vp data process
+ UINT8* pVpTempRxInBuffer; //pVpRxInBuffer
+ UINT8* pVpTempTxInBuffer; //pVpTxInBuffer
+ UINT8* pVpTempRxOutPutBuffer;//pVpRxOutPutBuffer
+ UINT8* pVpTempTxOutPutBuffer;//pVpTxOutPutBuffer
+
+ T_ZDrvI2S_Cfg *pVpI2sCfg; //i2s cfg
+
+ T_ZDrvVp_Cfg vpCfgParam; //s_cfgParam
+
+ T_ZDrvI2s_Params i2sWriteParam; //s_VpI2sWriteParam
+ T_ZDrvI2s_Params i2sReadParam; //s_vpI2sReadParam
+
+ UINT32 frameCount; //s_vpFrameCount
+ UINT32 totalFrameBufSize; //s_vpTotalFrameBufSize
+ UINT32 inOutBufUseSize; //s_inOutBufUseSize
+ UINT32 rxSaveLen; //s_rxSaveLen
+ UINT32 txSaveLen; //s_txSaveLen
+ UINT32 saveLen; //save_len
+
+ UINT8 pcmSlotNum; //s_vpPcmSlotNum
+ UINT8 pcmWbSecDataPosition; //s_vpPcmWbSecDataPosition
+
+ UINT8 volteVpWriteStopFlag;//s_volteVpWriteStopFlag
+ UINT8 volteVpReadStopFlag;//s_volteVpReadStopFlag
+ UINT8 volteVpCfgEnFlag; // s_volteVpCfgEnFlag
+ BOOL firstWriteDataFlag;//s_firstWriteDataFlag
+ BOOL firstReadDataFlag;//s_firstReadDataFlag
+ BOOL i2sIsRstFlag;//s_i2sIsRstFlag
+} T_zDrvVp_SpeechState; // T_zDrvVp_SpeechState
+
+typedef struct
+{
+ UINT8 volteIsWb; //g_volteIsWb
+ UINT8 isUseSlicCodec; //g_isUseSlicCodec
+ UINT8 g_isUseTdm;
+//for voice data process
+ UINT8 voiceInGsmTdMode; //g_voiceInGsmTdMode
+ UINT8 voiceInVolteMode; //g_voiceInVolteMode
+
+ BOOL innerI2sIsMaster;//arm i2s2 g_innerI2sIsMaster
+ BOOL innerI2sIsI2sMode; //g_innerI2sIsI2sMode
+ BOOL vpLoopRuning; //g_vpLoopRuning
+ BOOL muteEn; //g_vpMuteEn
+ //BOOL nxpIsNormal; //g_vpNxpIsNormal
+ BOOL vProcIsNormal; //voice processing is normal flag
+ T_Vp_I2sStatus vpI2sStatus; //VpI2sStatus
+
+ T_ZDrv_VpPath vpPath;// VP_PATH_HEADSET;//VP_PATH_SPEAKER; //VP_PATH_HANDSET; g_vpPath
+ T_ZDrv_VpPath vpLoopPath; //g_vpLoopPath
+ T_ZDrv_VpVol vpVol; //g_vpVol
+ T_ZDrvVoice_MODE voiceMode; //g_vpVoiceMode
+ SINT8 vpInitGain; //s_vpInitGain
+ T_Audio_NvFlag audio_ctrlFlag;//USE 32byte
+
+ UINT8 dtmfDirSel;
+ UINT32 sample_rate;
+ UINT8 useDtmfLoop;
+ SINT32 muteCount;//mute_count
+} T_zDrvVoice_GbVar; //T_zDrvVoice_GbVar
+
+typedef struct
+{
+ //use for store memory address
+ UINT8* pVpRxInBuffer; //s_pVpRxInBuffer
+ UINT8* pVpTxInBuffer; //s_pVpTxInBuffer
+ UINT8* pVpRxOutPutBuffer; //s_pVpRxOutPutBuffer
+ UINT8* pVpTxOutPutBuffer; //s_pVpTxOutPutBuffer
+
+ UINT32 inOutBufSize; //s_inOutBufSize
+
+ T_ZDrvI2S_Cfg *pVpInnerI2sCfg; //s_pVpInnerI2sCfg
+ T_ZDrvI2S_Cfg *pVpExtI2sCfg; //s_pVpExtI2sCfg
+ T_ZDrvI2S_Cfg *pVpExtI2sWbCfg; //s_pVpExtI2sWbCfg
+ T_ZDrvTdm_Cfg *s_pVpTdmCfg;
+ T_ZDrvTdm_Cfg *s_pVpTdmWbCfg;
+ T_ZDrvTdm_Cfg *pVpTdmCfg;
+
+ T_ZDrvRpMsg_Msg pMsg;
+ SINT32 pMsgBuf[2];
+ //SINT32 muteCount;//mute_count
+
+ ZOSS_THREAD_ID vpThread ; //s_VpThread
+ ZOSS_THREAD_ID rcvDtmfThread ; //s_rcvDtmfThread
+ ZOSS_SEMAPHORE_ID vpSemaphore; //s_VpSemaphore
+ ZOSS_SEMAPHORE_ID vpThreadQuitSema;
+
+ ZOSS_THREAD_ID vpLoopThread; //s_VpLoopThread
+ ZOSS_SEMAPHORE_ID vpLoopSemaphore; //s_VpLoopSemaphore
+
+ T_zDrvVp_SpeechState *vpState;
+// T_zDrvVoice_GbVar wrapVpGbVar;
+} T_zDrvVp_State; //T_zDrvVp_State
+
+SINT32 zDrvVp_SetPath(T_ZDrv_VpPath path);
+SINT32 zDrvVp_SetVol(T_ZDrv_VpVol volume);
+SINT32 zDrvVp_SetGain(SINT32 vgain, UINT32 channel);
+/* 0 lowpower;1 sms;2 call standard;3 alarm beep;*/
+SINT32 zDrvVp_ToneMixerStart(T_ZDrvVp_ToneNum toneNum);
+SINT32 zDrvVp_SetMute(UINT32 enable, UINT32 channel);
+SINT32 zDrvVp_RcdOnOff(UINT32 on);
+SINT32 zDrvVp_DtmfTone(UINT32 Num);
+SINT32 zDrvVp_Loop(T_ZDrv_VpPath path);
+SINT32 zDrvVp_RingStart(VOID);
+SINT32 zDrvVp_RingStop(VOID);
+VOID zDrvVp_SetUseSlicFlag(BOOL useSlic);
+SINT32 zDrvVp_NxpSetParam(zDrvVp_NxpParamsTool *NxpParamsTool);
+SINT32 zDrvVp_NxpGetParam(zDrvVp_NxpParamsTool *NxpParamsTool);
+SINT32 zDrvVp_SetFmPath(T_ZDrv_VpPath path, BOOL enable);
+SINT32 zDrvVp_SetParam(zDrvVp_ParamsTool *paramsTool);
+SINT32 zDrvVp_GetParam(zDrvVp_ParamsTool *paramsTool);
+SINT32 zDrvVp_SetNvParam(zDrvVp_ParamsTool *paramsTool);
+SINT32 zDrvVp_GetNvParam(zDrvVp_ParamsTool *paramsTool);
+
+
+#endif
diff --git a/cp/ps/driver/inc/misc/drvs_volte.h b/cp/ps/driver/inc/misc/drvs_volte.h
new file mode 100755
index 0000000..fd31c2d
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_volte.h
@@ -0,0 +1,86 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: Drvs_volte.h
+ * File Mark:
+ * Description: Provide the interface of using volte
+ * Others:
+ * Version: V0.5
+ * Author: lvwenhua
+ * Date: 2014-08-4
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+#ifndef _DRVS_VOLTE_H
+#define _DRVS_VOLTE_H
+
+#include <linux/volte_drv.h>
+
+typedef enum
+{
+ VOLTE_IDLE = 0,
+ VOLTE_OPEN,
+ VOLTE_INUSE,
+ VOLTE_MAX
+} T_Volte_Status;
+#if 0
+typedef enum
+{
+ VOICE_GSM_MODE = 0,
+ VOICE_TD_MODE ,
+ VOICE_WCDMA_MODE,
+ VOICE_LTE_MODE,
+ VOICE_GSM_TD_MODE,//GSM TD share
+ VOICE_GSM_WCDMA_MODE, //GSM WCDMA share
+ MAX_VOICE_MODE
+} T_ZDrvVoice_MODE;
+typedef struct
+{
+ UINT32 clock_rate;
+ UINT32 channel_count;
+ UINT32 samples_per_frame;
+ UINT32 bits_per_sample;
+ UINT32 mode;
+} T_ZDrvVp_Cfg;
+
+#define T_ZDrvVoice_Cfg T_ZDrvVp_Cfg
+#endif
+
+typedef T_ZDrvVoice_Cfg T_ZDrvVp_Cfg;
+
+typedef struct
+{
+
+ SINT32 (*drv_voice_3G_Open)(VOID);
+ SINT32 (*drv_voice_3G_Close)(VOID);
+
+} T_DrvVoice_3G_Opt;
+
+ typedef struct
+ {
+ void (*drv_dtmfrx_report_cb)(char *dtmf_string, unsigned char string_len);
+ void (*drv_dtmftx_report_cb)(char *dtmf_string, unsigned char string_len);
+ } T_DrvDtmf_Detect_Opt;
+
+ SINT32 zDrvVoice_Open(T_ZDrvVoice_Cfg *cfgParam);
+ SINT32 zDrvVoice_Close(VOID);
+ SINT32 zDrvVoice_ReadStart(VOID);
+ SINT32 zDrvVoice_ReadStop(VOID);
+ SINT32 zDrvVoice_WriteStart(VOID);
+ SINT32 zDrvVoice_WriteStop(VOID);
+ SINT32 zDrvVoice_ReadOneFrame(UINT8 *pBuf);
+ SINT32 zDrvVoice_WriteOneFrame(UINT8 *pBuf);
+VOID zDrvVoice_3G_RegCallbacks(T_DrvVoice_3G_Opt voiceObj);
+
+SINT32 zDrvVolte_AmrEncoderInit(VOID);
+SINT32 zDrvVolte_AmrDecoderInit(VOID);
+SINT32 zDrvVolte_AmrEncoder(UINT8 *pInputBuf,UINT32 inSize,UINT8 *pOutputBuf,UINT32* pOutSize);
+SINT32 zDrvVolte_AmrDecoder(UINT8 *pInputBuf,UINT32 inSize,UINT8 *pOutputBuf,UINT32* pPutSize);
+VOID zDrvVolte_AmrEncoderDeinit(VOID);
+VOID zDrvVolte_AmrDecoderDeinit(VOID);
+#endif
+
diff --git a/cp/ps/driver/inc/misc/drvs_vou.h b/cp/ps/driver/inc/misc/drvs_vou.h
new file mode 100644
index 0000000..9f5467b
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_vou.h
@@ -0,0 +1,341 @@
+/*******************************************************************************
+ * Copyright by ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version: v0.1
+ * Author: wuhui
+ * Date: 2016-12-17
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DRVS_VOU_H
+#define _DRVS_VOU_H
+
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+
+/****************************************************************************
+* Types
+****************************************************************************/
+typedef struct
+{
+ BOOL funcCSC; /*CSC for VL, color conversion from YUV to RGB or from RGB to YUV*/
+ UINT32 VLNum; /*how many Video layers*/
+ UINT32 GLNum; /*how many Video layers*/
+ BOOL VL_SrcYUYV; /*whether VL Source data support YUYV format */
+ BOOL VL_SrcUYVY; /*whether VL Source data support UYVY format */
+ BOOL VL_SrcYVYU; /*whether VL Source data support YVYU format */
+ BOOL VL_SrcVYUY; /*whether VL Source data support VYUY format */
+ BOOL VL_SrcPlanarYUV420; /*whether VL Source data support PlanarYUV420 format*/
+ BOOL VL_SrcSemiPlanarYUV420; /*whether VL Source data support SemiPlanarYUV420 format */
+ BOOL VL_GlobalAlpha; /*whether VL support global alpha */
+ BOOL GL_SrcARGB8888; /*whether GL Source data support ARGB8888 format */
+ BOOL GL_SrcRGB888; /*whether GL Source data support RGB888 format */
+ BOOL GL_SrcRGB565; /*whether GL Source data support RGB565 format */
+ BOOL GL_SrcARGB1555; /*whether GL Source data support ARGB1555 format */
+ BOOL GL_Src8BPP; /*whether GL Source data support 8BPP format */
+ BOOL GL_ColorkeyAlpha; /*whether GL support Color key Alpha */
+ BOOL GL_PixelAlpha; /*whether GL supportPixel Alpha */
+ BOOL GL_GlobalAlpha; /*whether GL support global alpha */
+ UINT32 MAX_WIDTH; /*the max pixel width */
+ UINT32 MAX_HEIGTH; /*the max pixel height */
+ BOOL funcOSD_WB; /*whether support OSD write back function */
+} T_ZDrv_OSDInfo;
+
+typedef enum
+{
+ VOU_OPEN = 0x0,
+ VOU_FINISH_ONEFRAME = 0x1,
+ VOU_ERROR = 0x2,
+ VOU_CLOSE = 0x3,
+ MAX_VOU_STATE = 0x4
+}T_ZDrv_VOUSTATE;
+
+typedef enum
+{
+ eDISABLE = 0,
+ eENABLE =1,
+ MAX_eENABLE_TYPE =2
+}T_ZDrv_ENABLE_TYPE;
+
+typedef enum
+ {
+ eLITTLEENDIAN = 0,
+ eBIGENDIAN = 1,
+ MAX_ENDIAN_TYPE = 2
+ }T_ZDrv_ENDIAN;
+
+typedef enum
+ {
+ eSEMI_PLANAR = 0,
+ ePLANAR = 1,
+ eYUV422_YUYV = 2,
+ eYUV422_YVYU = 3,
+ eYUV422_UYVY = 4,
+ eYUV422_VYUY = 5,
+ MAX_DATASRC_MODE = 6
+ }T_ZDrv_VL_DATASRC_MODE;
+
+typedef enum
+ {
+ eARGB8888 = 0,
+ eRGB888 = 1,
+ eRGB565 = 2,
+ eARGB1555 = 3,
+ e8BPP = 4,
+ MAX_DATAFORMAT = 5
+ }T_ZDrv_GL_DATAFORMAT;
+
+typedef enum
+ {
+ eCOLORKEYALPHA= 0 ,
+ eGLOBALALPHA = 1,
+ ePIXALPHA = 2,
+ MAX_ALPHA_SEL =3
+ }T_ZDrv_ALPHA_SEL;
+
+typedef enum
+{
+ eRANGE0To255 = 0,
+ eRANGE0To127 = 1,
+ MAX_PIXALPHA_RANGE = 2
+}T_ZDrv_PIXALPHA_RANGE;
+
+typedef enum
+{
+ eEXTLOWBITS = 0,
+ eEXTHIGHBITS = 1,
+ MAX_EXT_MODE = 2
+}T_ZDrv_EXT_MODE;
+
+typedef enum
+{
+ eEXTBYALL0 = 0,
+ eEXTBYALL1 = 1,
+ eEXTBYLSB = 2,
+ eEXTBYMSB = 3,
+ MAX_EXT_DATA_TYPE = 4
+}T_ZDrv_EXT_DATA_TYPE;
+
+typedef enum
+{
+ eRGB666_IN_18B = 0,
+ eRGB666_IN_24B = 1,
+ eRGB565_IN_32B = 2,
+ eRGB565_IN_16B = 3,
+ MAX_WB_DATA_MODE = 4
+}T_ZDrv_WB_DATA_MODE;
+
+typedef enum
+{
+ RGB_TO_YUV_FOR_SDTV = 0,
+ YUV_TO_RGB_FOR_SDTV = 1,
+ RGB_TO_YUV_FOR_SDTV_COMPUTER = 2,
+ YUV_TO_RGB_FOR_SDTV_COMPUTER = 3,
+ RGB_TO_YUV_FOR_HDTV = 4,
+ YUV_TO_RGB_FOR_HDTV = 5,
+ RGB_TO_YUV_FOR_HDTV_COMPUTER = 6,
+ YUV_TO_RGB_FOR_HDTV_COMPUTER = 7,
+ MAX_CSC_MODE = 8
+}T_ZDrv_CSC_MODE;
+
+typedef struct _T_VOU_POSXY
+{
+ UINT16 startX; /*dislplay start pos X,in pixels,from top left point of screen,range 0~1919 */
+ UINT16 startY; /*dislplay start pos Y,in pixels,from top left point of screen,range 0~1079 */
+ UINT16 endX; /*dislplay end pos X,in pixels,from top left point of screen,range 0~1919 */
+ UINT16 endY; /*dislplay end pos Y,in pixels,from top left point of screen,range 0~1079 */
+} T_ZDrv_VOU_POSXY;
+
+typedef struct _T_VOU_VL_SRCWH
+{
+ UINT16 VLSrcWidth; /*the source width in pixels, make sure picture boundary is inside screen*/
+ UINT16 VLSrcHeight; /*the source height in pixels, make sure picture boundary is inside screen*/
+} T_ZDrv_VOU_VL_SRCWH;
+
+typedef struct _T_VOU_VL_SRCSTR
+{
+ UINT16 VLLuStr; /*the luma stride in bytes, 8 bytes aligned*/
+ UINT16 VLChrStr; /*the chroma stride in bytes, 8 bytes aligned*/
+} T_ZDrv_VOU_VL_SRCSTR;
+
+typedef struct _T_VOU_VL_YUVADDR
+{
+ UINT8* VL_AddrY; /*address of Y for VL,8 bytes aligned*/
+ UINT8* VL_AddrU; /*address of U for VL,8 bytes aligned*/
+ UINT8* VL_AddrV; /*address of V for VL,8 bytes aligned*/
+} T_ZDrv_VOU_VL_YUVADDR;
+
+typedef struct _T_VOU_VL_GALP
+{
+ T_ZDrv_ENABLE_TYPE VL_GAlpEnable; /*enalble VL layer alpha or not*/
+ UINT8 VL_GAlpVal; /*the global alpha value ,range 0~255,0 is transparent*/
+} T_ZDrv_VOU_VL_GALP;
+
+typedef struct _T_VOU_GL_ALP
+{
+ UINT8 GL_AlpA0; /*the alpha for ARGB1555 When A=0 ,range 0~127 or range 0~255,0 is transparent*/
+ UINT8 GL_AlpA1; /*the alpha for ARGB1555 When A=1 ,range 0~127 or range 0~255,0 is transparent*/
+ UINT8 GL_AlpGlobal; /*the global alpha value ,range 0~255,0 is totally transparent*/
+ T_ZDrv_ALPHA_SEL GL_AlphaMode;
+ T_ZDrv_PIXALPHA_RANGE GL_PixelAlpRange;
+} T_ZDrv_VOU_GL_ALP;
+
+typedef struct _T_VOU_VLPara
+{
+ T_ZDrv_ENABLE_TYPE VLEnable; /*enalble VL layer or not*/
+ UINT8 VLPriority; /*VL layer priority ,value range 0~7,he value must diffrent,the smaller value,the higher priority */
+ T_ZDrv_VOU_POSXY VL_PosXY; /*just need the start X Y,end XY can be calculated based on width and height*/
+ T_ZDrv_VL_DATASRC_MODE VLSrcMode; /*the VL src data mode*/
+ T_ZDrv_VOU_VL_SRCSTR VL_SrcStr;
+ T_ZDrv_VOU_VL_SRCWH VL_SrcHW;
+ T_ZDrv_VOU_VL_YUVADDR VL_AddrYUV;
+ T_ZDrv_VOU_VL_GALP VL_GAlp;
+} T_ZDrv_VOU_VLPara;
+
+typedef struct _T_VOU_GL_EXT
+{
+ T_ZDrv_EXT_MODE GL_ExtDir; /*the extension direction , recommand eEXTLOWBITS ,only for ARGB1555 /RGB 565 */
+ T_ZDrv_EXT_DATA_TYPE GL_ExtDataMode; /*the extension date type, recommand eEXTBYALL0 */
+} T_ZDrv_VOU_GL_EXT;
+
+typedef struct _T_VOU_GL_CK0
+{
+ UINT8 GL_AlpColorIn; /*alpha inside color key region0 and region1 ,range 0~255*/
+ UINT8 GL_CK0_MinR; /*the color key region0,the min R value*/
+ UINT8 GL_CK0_MinG; /*the color key region0,the min G value*/
+ UINT8 GL_CK0_MinB; /*the color key region0,the min B value*/
+ UINT8 GL_AlpColorOut; /*alpha outside color key region0 and region1,range 0~255 */
+ UINT8 GL_CK0_MaxR; /*the color key region0,the max R value*/
+ UINT8 GL_CK0_MaxG; /*the color key region0,the max G value*/
+ UINT8 GL_CK0_MaxB; /*the color key region0,the max B value*/
+} T_ZDrv_VOU_GL_CK0;
+
+typedef struct _T_VOU_GL_CK1
+{
+ T_ZDrv_ENABLE_TYPE GL_CKRegion1Enable; /*enalble color key region1 or not*/
+ UINT8 GL_CK1_MinR; /*the color key region1,the min R value*/
+ UINT8 GL_CK1_MinG; /*the color key region1,the min G value*/
+ UINT8 GL_CK1_MinB; /*the color key region1,the min B value*/
+ UINT8 GL_CK1_MaxR; /*the color key region1,the max R value*/
+ UINT8 GL_CK1_MaxG; /*the color key region1,the max G value*/
+ UINT8 GL_CK1_MaxB; /*the color key region1,the max B value*/
+} T_ZDrv_VOU_GL_CK1;
+
+
+typedef struct _T_VOU_GLPara
+{
+ T_ZDrv_ENABLE_TYPE GLEnable; /*enalble GL layer or not*/
+ UINT8 GLPriority; /*GL layer priority ,value range 0~7;the value must diffrent ,the smaller value,the higher priority */
+ T_ZDrv_ENDIAN GL_endianType; /*the graphic data type ,recommand little endian*/
+ T_ZDrv_VOU_POSXY GL_PosXY;
+ T_ZDrv_GL_DATAFORMAT GLSrcMode; /*the GL src data mode*/
+ T_ZDrv_VOU_GL_ALP GL_Alp;
+ T_ZDrv_VOU_GL_EXT GL_Ext;
+ UINT16 GLStride; /*the stride in bytes, 8 bytes aligned*/
+ UINT8* GL_SrcAddr; /*address of Graphic data,8 bytes aligned*/
+ T_ZDrv_VOU_GL_CK0 GL_CK0;
+ T_ZDrv_VOU_GL_CK1 GL_CK1;
+} T_ZDrv_VOU_GLPara;
+
+typedef struct _T_VOU_MC_WH
+{
+ UINT16 MCScrWidth; /*the screen width, max to 1920, multiple of 2 */
+ UINT16 MCScrHeight; /*the screen height, max to 1088, multiple of 2 */
+}T_ZDrv_VOU_MC_WH;
+
+typedef struct _T_VOU_MC_BG
+{
+ UINT8 MC_BGValueR; /*the main back ground R value*/
+ UINT8 MC_BGValueG; /*the main back ground G value*/
+ UINT8 MC_BGValueB; /*the main back ground B value*/
+}T_ZDrv_VOU_MC_BG;
+
+
+typedef struct _T_VOU_MCPara
+{
+ T_ZDrv_ENABLE_TYPE MCEnable; /*enalble main channel or not*/
+ T_ZDrv_VOU_MC_WH MCSrcWH;
+ T_ZDrv_VOU_MC_BG MC_BG_RGB;
+} T_ZDrv_VOU_MCPara;
+
+typedef struct _T_VOU_WB_BUFADDR
+{
+ UINT8* WB_BufAddr0; /*address of write back frame buffer 0,8 bytes aligned*/
+ UINT8* WB_BufAddr1; /*address of write back frame buffer 1,8 bytes aligned*/
+ UINT8* WB_BufAddr2; /*address of write back frame buffer 2,8 bytes aligned*/
+ UINT8* WB_BufAddr3; /*address of write back frame buffer 3,8 bytes aligned*/
+}T_ZDrv_VOU_WB_BUFADDR;
+
+typedef struct _T_VOU_WBPara
+{
+ T_ZDrv_ENABLE_TYPE WBEnable; /*enalble write back or not*/
+ UINT16 WBStride; /*the write back stride, multiple of 8 */
+ UINT8 WBBufNum; /*indicate how many frame buffers will be used,range 1~4*/
+ UINT8 WBPeriod; /*skip n frames before write back one frame,range 0~7*/
+ T_ZDrv_WB_DATA_MODE WBDataMode;
+ T_ZDrv_VOU_WB_BUFADDR WBBufAddr;
+} T_ZDrv_VOU_WBPara;
+
+typedef struct _T_VOU_CSC_Coeff
+{
+ SINT16 CSC_CoeA; /* the coefficient of X in F(X.Y,Z) */
+ SINT16 CSC_CoeB; /* the coefficient of Y in F(X.Y,Z) */
+ SINT16 CSC_CoeC; /* the coefficient of Z in F(X.Y,Z) */
+ SINT16 CSC_CoeD; /* the coefficient of d in F(X.Y,Z) */
+}T_ZDrv_VOU_CSC_Coeff;
+
+typedef struct _T_VOU_CSC_SPACE
+{
+ UINT8 CSC_SPACE_FLOOR; /* the floor level of col */
+ UINT8 CSC_SPACE_TOP; /* the top level of col */
+}T_ZDrv_VOU_CSC_SPACE;
+
+typedef struct _T_VOU_CSCPara
+{
+ T_ZDrv_ENABLE_TYPE CSCEnable; /*enalble CSC or not*/
+ T_ZDrv_CSC_MODE CSC_ConMode; /* the conversion mode */
+ T_ZDrv_VOU_CSC_Coeff CSC_XYZ_F[3]; /* the coefficient of X in F1(X.Y,Z) ,F2(X.Y,Z) ,F3(X.Y,Z) */
+ T_ZDrv_VOU_CSC_SPACE CSC_SPACE_IN[3]; /* the floor&top level of col_in1, col_in2,col_in3*/
+ T_ZDrv_VOU_CSC_SPACE CSC_SPACE_OUT[3]; /* the floor&top level of col_out1, col_out2,col_out3*/
+} T_ZDrv_VOU_CSCPara;
+
+typedef struct _T_VOU_OSDPara
+{
+ T_ZDrv_VOU_VLPara OSD_VLPara; /*Video layer Parameters*/
+ T_ZDrv_VOU_GLPara OSD_GLPara; /*Graphic layer Parameters*/
+ T_ZDrv_VOU_MCPara OSD_MCPara; /*Main Chanle Parameters*/
+} T_ZDrv_VOU_OSDPara;
+
+/****************************************************************************
+* Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+
+/****************************************************************************
+* Function Prototypes
+****************************************************************************/
+
+
+
+#endif/*_FILENAME_H*/
+
diff --git a/cp/ps/driver/inc/misc/drvs_wdt.h b/cp/ps/driver/inc/misc/drvs_wdt.h
new file mode 100644
index 0000000..3510f60
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_wdt.h
@@ -0,0 +1,141 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: hal_wdt.c
+ * File Mark:
+ * Description: watchdog hal interface header file
+ * Others:
+ * Version:
+ * Author: limeifeng
+ * Date: 2014.05.21
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ******************************************************************************/
+
+ #ifndef DRVS_WDT_H
+ #define DRVS_WDT_H
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+/****************************************************************************
+* Local Macros
+****************************************************************************/
+
+/****************************************************************************
+* Local Types
+****************************************************************************/
+typedef VOID (*wdt_func)(VOID);
+
+/****************************************************************************
+* Local Constants
+****************************************************************************/
+
+/****************************************************************************
+* Local Function Prototypes
+****************************************************************************/
+
+/****************************************************************************
+* Global Constants
+****************************************************************************/
+
+/****************************************************************************
+* Global Variables
+****************************************************************************/
+/****************************************************************************
+* Global Function Prototypes
+****************************************************************************/
+
+/****************************************************************************
+* Function Definitions
+****************************************************************************/
+
+/*******************************************************************************
+ * Function: zDrvWdt_Start
+ * Description:Start watchdog
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ //VOID zDrvWdt_Start(VOID);
+
+
+/*******************************************************************************
+ * Function: zDrvWdt_Stop
+ * Description: stop watchdog
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zDrvWdt_Stop(VOID);
+
+ /*******************************************************************************
+ * Function: zDrvWdt_GetValue
+ * Description: get watchdog current counter value
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns: watchdog current counter value
+ *
+ *
+ * Others:
+ ********************************************************************************/
+//UINT32 zDrvWdt_GetValue(void);
+
+ /*******************************************************************************
+ * Function: zDrvWdt_FeedDog
+ * Description:Feed watchdog
+ * Parameters:
+ * Input: value: 0x0--0xffff
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ //void zDrvWdt_FeedDog(UINT32 value);
+
+/*******************************************************************************
+ * Function: zDrvWdt_Initiate
+ * Description: watchdog initiate
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+SINT32 zDrvWdt_Initiate(void);
+
+void zDrvWdt_Handle_After_Psm(void);
+
+void zDrvWdt_Handle_Before_Psm(void);
+
+SINT32 zDrvWdt_Register_Handle(wdt_func func, UINT32 interval, bool wakeup, char *handle_name);
+
+SINT32 zDrvWdt_Set_WdtNv(BOOL NvFlag);
+#endif
+
diff --git a/cp/ps/driver/inc/misc/drvs_zsp.h b/cp/ps/driver/inc/misc/drvs_zsp.h
new file mode 100644
index 0000000..3844e98
--- /dev/null
+++ b/cp/ps/driver/inc/misc/drvs_zsp.h
@@ -0,0 +1,90 @@
+/***********************************************************************
+* Copyright (C) 2001, ZTE Corporation.
+*
+* File Name: drvs_zsp.h
+* File Mark:
+* Description: zsp hal interface declaration.
+* Others:
+* Version: v1.0
+* Author: zhangyingjun
+* Date: 2009-03-23
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+* History 2:
+* Date: 2009.05.20
+* Version:v1.3.0
+* Author: wangxia
+* Modification: add ZSP_Reset function
+**********************************************************************/
+
+#ifndef HAL_ZSP_H
+#define HAL_ZSP_H
+
+
+/*************************************************************************
+ * Include files *
+ *************************************************************************/
+
+
+/*************************************************************************
+ * Macro *
+ *************************************************************************/
+
+
+/**************************************************************************
+ * Types *
+ **************************************************************************/
+ typedef enum
+{
+ ZSP_DC,
+ ZSP_CC,
+ MAX_ZSP_NUM
+} T_ZDrvZsp_Num;
+
+/**************************************************************************
+ * Global Variable *
+ **************************************************************************/
+
+
+/**************************************************************************
+ * Function Prototypes *
+ **************************************************************************/
+
+
+/*******************************************************************************
+ * Function: BOOT_ZSP_Init
+ * Description: ZSP initialization function,including powering on through Jtag Server & powering on through nandflash
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+VOID BOOT_ZSP_Init(T_ZDrvZsp_Num num);
+
+
+/*******************************************************************************
+ * Function: ZSP_Reset
+ * Description: reset ZSP
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+ VOID zsp_Reset(VOID);
+
+#endif /* HAL_ZSP_H */
+
diff --git a/cp/ps/driver/inc/misc/edcp_test.h b/cp/ps/driver/inc/misc/edcp_test.h
new file mode 100644
index 0000000..ae34bbc
--- /dev/null
+++ b/cp/ps/driver/inc/misc/edcp_test.h
@@ -0,0 +1,31 @@
+#ifndef EDCPTEST_H
+#define EDCPTEST_H
+void memcpy_edcp(U32* pCopyTo, U32* pSource, U32 num_index, U32 num_word);
+void data_pre(void);
+
+void ul_asyn_dat_cmp( void);
+void ul_syn_dat_cmp( void);
+void dl_asyn_dat_cmp( void);
+
+void EDCP_SW_ENCRYPT(void);
+
+
+//ddr data ram src addr
+#define DDR_SRC_DATA_UL 0x24010000//0x24200000//ddr data ram base ddr 2M byte if 1496 byte enough for 1000 pdcp pdu
+#define DDR_SRC_DATA_EMAC 0x24205000//0x24600000//ddr data ram base ddr
+#define DDR_SRC_DATA_DL 0x245F0000//0x24A00000//ddr data ram base ddr
+//#define DDR_SRC_DATA_CHECKSUM 0x250b0000//0x24E00000//ddr data ram base ddr
+
+//ddr data ram des addr
+#define DDR_DES_DATA_UL 0x25300000// allocate to UL SYN
+#define DDR_DES_DATA_EMAC 0x254F5000//0x25700000
+#define DDR_DES_DATA_DL 0x25BE0000//0x25B00000
+//#define DDR_DES_DATA_CHECKSUM 0x266A0000//0x25F00000
+
+#define DDR_ADDR_INTERVAL 0x2000//0x1f40//8000 //0x7D0 //2000
+
+
+#define DDR_SRC_UL_ENC_DL 0x26400000
+#define DDR_DES_UL_ENC_DL 0x27000000
+
+#endif /* #ifndef EDCPTEST_H */
diff --git a/cp/ps/driver/inc/misc/mmc_drvs_io.h b/cp/ps/driver/inc/misc/mmc_drvs_io.h
new file mode 100644
index 0000000..a11f6a8
--- /dev/null
+++ b/cp/ps/driver/inc/misc/mmc_drvs_io.h
@@ -0,0 +1,76 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+ * Others:
+ * Version:
+ * Author: XUJINYOU
+ * Date: 2014-7-28
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _MMC_DRVS_IO_H
+#define _MMC_DRVS_IO_H
+
+typedef struct _T_MmcDrv_Ops T_MmcDrv_Ops;
+
+
+struct _T_MmcDrv_Ops
+{
+ SINT32 (*open)(VOID *devdata, UINT32 flags);
+ SINT32 (*read)(VOID *devdata, VOID*param1, VOID*param2);
+ SINT32 (*write)(VOID *devdata,VOID *param1, VOID*param2);
+ SINT32 (*ioctrl)(VOID *devdata, UINT32 event, VOID*param);
+ SINT32 (*close)(VOID *devdata);
+};
+
+
+
+#define MMC_DRVNAME_LEN 20
+#define MMC_APPNAME_LEN 20
+
+typedef struct _T_MmcDrv
+{
+ struct list_head node;
+ UINT8 drvName[MMC_DRVNAME_LEN];
+ T_MmcDrv_Ops* drv_op;
+ struct list_head devlist;
+ UINT32 devcount;
+}T_MmcDrv, *PTMmcDrv;
+
+#define MMC_DEVNAME_LEN 20
+
+typedef struct _T_MmcDev
+{
+ VOID* priv;
+ UINT8 devName[MMC_DEVNAME_LEN];
+ T_MmcDrv* driver;
+ VOID*param;
+ struct list_head devNode;
+}T_MmcDev,*PTMmcDev;
+
+
+typedef struct _T_MmcData_Collect
+{
+ UINT8 type;
+ UINT8 fun_num;
+ UINT16 blk_size;
+ UINT32 startaddr; /*startpos for blk, start addr for bytes*/
+ UINT32 count; /**/
+ UINT32 flag; /*b:0 fifo*/
+ VOID* pbuffer;
+ VOID (*Mmccallback)(struct _T_MmcData_Collect* param);
+ VOID*priv;
+}T_MmcData_Collect, *PMmcData_Collect;
+
+
+
+#endif
+
diff --git a/cp/ps/driver/inc/misc/mmc_export.h b/cp/ps/driver/inc/misc/mmc_export.h
new file mode 100644
index 0000000..b930095
--- /dev/null
+++ b/cp/ps/driver/inc/misc/mmc_export.h
@@ -0,0 +1,52 @@
+#ifndef _MMC_EXPORT_HEAD_H
+#define _MMC_EXPORT_HEAD_H
+#include "mmc_drvs_io.h"
+
+
+typedef enum _e_notify_event
+{
+ MMC_CARD_ARRIVAL = 0,
+ MMC_CARD_REMOVE,
+ MMC_CARD_SUSPEND,
+ MMC_CARD_RESUME,
+ MMC_NOTIFY_NUM
+}e_notify_event;
+
+typedef enum _e_mmc_DrpEvent
+{
+ MMC_CARD_GET_CAPACITY,
+ MMC_CARD_ERASE_BLK,
+ MMC_CARD_SET_BLKSIZE,
+ MMC_CARD_ENABLE_FUNC,
+ MMC_CARD_DISABLE_FUNC,
+ MMC_CARD_SET_FUNC_BLKSIZE,
+ MMC_CARD_GET_FUNC_INFO,
+ MMC_SDIO_CLAIM_IRQ,
+ MMC_SDIO_RELEASE_IRQ,
+ MMC_SDIO_CARD_RESET,
+ MMC_CARD_OPEN,
+ MMC_CARD_CLOSE,
+ MMC_CARD_WRITE ,
+ MMC_CARD_READ,
+ MMC_CARD_IOCTROL,
+ MMC_CARD_OP_NUM
+}e_mmc_DrpEvent;
+
+#define SD_DEFAULT_BLKSIZE 512
+
+
+#define MMC_CARD_TYPE_MMC 0 /* MMC card */
+#define MMC_CARD_TYPE_SD 1 /* SD card */
+#define MMC_CARD_TYPE_SDIO 2 /* SDIO card */
+#define MMC_CARD_TYPE_SD_COMBO 3 /* SD combo (IO+mem) card */
+
+SINT32 mmc_loadDrv(const char* drvName, VOID* param);
+
+SINT32 mmc_unloadDrv(VOID* param);
+
+typedef VOID (*mmcApp_notify)(e_notify_event, VOID*, VOID*);
+
+SINT32 mmcApp_notifyRegister(const char* appName,mmcApp_notify mmcNotify);
+
+
+#endif