[T106][ZXW-22]7520V3SCV2.01.01.02P42U09_VEC_V0.8_AP_VEC origin source commit
Change-Id: Ic6e05d89ecd62fc34f82b23dcf306c93764aec4b
diff --git a/pub/project/zx297520v3/config/amt_cfg.mk b/pub/project/zx297520v3/config/amt_cfg.mk
new file mode 100644
index 0000000..ff35470
--- /dev/null
+++ b/pub/project/zx297520v3/config/amt_cfg.mk
@@ -0,0 +1,19 @@
+# /*****************************************************************************
+#* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+#*
+#* ÎļþÃû³Æ: amt_cfg.mk
+#* Îļþ±êʶ: amt_cfg.mk
+#* ÄÚÈÝÕªÒª: zx297520 amt¹¤³ÌÅäÖÃÎļþ
+#* ʹÓ÷½·¨: include project.mk
+#*
+#* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+#* -----------------------------------------------------------------------------
+#* 2015/06/13 V1.0 Create ÁõÑÇÄÏ ´´½¨
+#*
+# ******************************************************************************/
+
+#*******************************************************************************
+# ¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+
+
diff --git a/pub/project/zx297520v3/config/drv_cfg.mk b/pub/project/zx297520v3/config/drv_cfg.mk
new file mode 100644
index 0000000..a66918c
--- /dev/null
+++ b/pub/project/zx297520v3/config/drv_cfg.mk
@@ -0,0 +1,19 @@
+# /*****************************************************************************
+#* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+#*
+#* ÎļþÃû³Æ: drv_cfg.mk
+#* Îļþ±êʶ: drv_cfg.mk
+#* ÄÚÈÝÕªÒª: zx297520Çý¶¯¹¤³ÌÅäÖÃÎļþ
+#* ʹÓ÷½·¨: include project.mk
+#*
+#* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+#* -----------------------------------------------------------------------------
+#* 2015/06/13 V1.0 Create ÁõÑÇÄÏ ´´½¨
+#*
+# ******************************************************************************/
+
+#*******************************************************************************
+# ¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+
+
diff --git a/pub/project/zx297520v3/config/infra_cfg.mk b/pub/project/zx297520v3/config/infra_cfg.mk
new file mode 100644
index 0000000..2a175f5
--- /dev/null
+++ b/pub/project/zx297520v3/config/infra_cfg.mk
@@ -0,0 +1,19 @@
+# /*****************************************************************************
+#* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+#*
+#* ÎļþÃû³Æ: infra_cfg.mk
+#* Îļþ±êʶ: infra_cfg.mk
+#* ÄÚÈÝÕªÒª: zx297520»ù´¡¹¤³ÌÅäÖÃÎļþ
+#* ʹÓ÷½·¨: include project.mk
+#*
+#* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+#* -----------------------------------------------------------------------------
+#* 2015/06/13 V1.0 Create ÁõÑÇÄÏ ´´½¨
+#*
+# ******************************************************************************/
+
+#*******************************************************************************
+# ¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+
+
diff --git a/pub/project/zx297520v3/config/project.mk b/pub/project/zx297520v3/config/project.mk
new file mode 100644
index 0000000..36ff8ac
--- /dev/null
+++ b/pub/project/zx297520v3/config/project.mk
@@ -0,0 +1,44 @@
+# /*****************************************************************************
+#* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+#*
+#* ÎļþÃû³Æ: project.mk
+#* Îļþ±êʶ: project.mk
+#* ÄÚÈÝÕªÒª: zx297520¹¤³ÌÅäÖÃÎļþ
+#* ʹÓ÷½·¨: include project.mk
+#*
+#* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+#* -----------------------------------------------------------------------------
+#* 2015/05/08 V1.0 Create ÁõÑÇÄÏ ´´½¨
+#*
+# ******************************************************************************/
+
+#*******************************************************************************
+#»ù´¡¹¤³ÌÅäÖÃ
+#*******************************************************************************
+include $(CPU_PUB_ROOT)/project/$(PRJ_NAME)/config/infra_cfg.mk
+
+#*******************************************************************************
+#ÐÒ鹤³ÌÅäÖÃ
+#*******************************************************************************
+include $(CPU_PUB_ROOT)/project/$(PRJ_NAME)/config/ps_phy_cfg.mk
+
+#*******************************************************************************
+#Çý¶¯¹¤³ÌÅäÖÃ
+#*******************************************************************************
+include $(CPU_PUB_ROOT)/project/$(PRJ_NAME)/config/drv_cfg.mk
+
+#*******************************************************************************
+#¹¤¾ß¹¤³ÌÅäÖÃ
+#*******************************************************************************
+include $(CPU_PUB_ROOT)/project/$(PRJ_NAME)/config/tools_cfg.mk
+
+#*******************************************************************************
+#Ê¡µç¹¤³ÌÅäÖÃ
+#*******************************************************************************
+include $(CPU_PUB_ROOT)/project/$(PRJ_NAME)/config/psm_cfg.mk
+
+#*******************************************************************************
+#amt¹¤³ÌÅäÖÃ
+#*******************************************************************************
+include $(CPU_PUB_ROOT)/project/$(PRJ_NAME)/config/amt_cfg.mk
+
diff --git a/pub/project/zx297520v3/config/ps_phy_cfg.mk b/pub/project/zx297520v3/config/ps_phy_cfg.mk
new file mode 100644
index 0000000..bf24da1
--- /dev/null
+++ b/pub/project/zx297520v3/config/ps_phy_cfg.mk
@@ -0,0 +1,65 @@
+# /*****************************************************************************
+#* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+#*
+#* ÎļþÃû³Æ: ps_cfg.mk
+#* Îļþ±êʶ: ps_cfg.mk
+#* ÄÚÈÝÕªÒª: zx297520ÐÒéÕ»¹¤³ÌÅäÖÃÎļþ
+#* ʹÓ÷½·¨: include project.mk
+#*
+#* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+#* -----------------------------------------------------------------------------
+#* 2015/06/13 V1.0 Create ÁõÑÇÄÏ ´´½¨
+#*
+# ******************************************************************************/
+
+#*******************************************************************************
+# R8¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_R8_SUPPORT ?= yes
+
+#*******************************************************************************
+# R9¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_R9_SUPPORT ?= yes
+
+#*******************************************************************************
+# R10¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+ifeq ($(USE_LTEA_MERGE_LTE), yes)
+export USE_R10_SUPPORT = no
+endif
+
+ifeq ($(USE_RF_SP_LTEA), yes)
+export USE_R10_SUPPORT = no
+endif
+
+#*******************************************************************************
+# RAT¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_RAT_TDS ?= yes
+export USE_RAT_WCDMA ?= yes
+export USE_RAT_LTE ?= yes
+
+ifeq ($(USE_LTEA_MERGE_LTE), yes)
+export USE_RAT_LTEA = yes
+endif
+
+ifeq ($(USE_RF_SP_LTEA), yes)
+export USE_RAT_LTEA = yes
+endif
+
+#*******************************************************************************
+# TD-SCDMA HSPA+¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_HSPAPLUS ?= no
+
+#*******************************************************************************
+# Byte to word¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_LTE_BYTE_TO_WORD ?= yes
+
+#*******************************************************************************
+# Single antenna¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_SINGLE_ANTENNA_SUPPORT ?= yes
+
diff --git a/pub/project/zx297520v3/config/psm_cfg.mk b/pub/project/zx297520v3/config/psm_cfg.mk
new file mode 100644
index 0000000..aa24172
--- /dev/null
+++ b/pub/project/zx297520v3/config/psm_cfg.mk
@@ -0,0 +1,83 @@
+# /*****************************************************************************
+#* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+#*
+#* ÎļþÃû³Æ: psm_cfg.mk
+#* Îļþ±êʶ: psm_cfg.mk
+#* ÄÚÈÝÕªÒª: zx297520v3Ê¡µç¹¤³ÌÅäÖÃÎļþ
+#* ʹÓ÷½·¨: include project.mk
+#*
+#* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+#* -----------------------------------------------------------------------------
+#* 2015/06/13 V1.0 Create ÁõÑÇÄÏ ´´½¨
+#*
+# ******************************************************************************/
+
+#*******************************************************************************
+# PSM¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_PSM ?= yes
+
+#*******************************************************************************
+# ÉäƵʡµçµÄ½øÈëºÍÍ˳öÔÚGSMÎïÀí²ã½øÐеŦÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_RFSLEEP_IN_GSM ?= yes
+
+#*******************************************************************************
+# CPUµ÷Ƶ¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_CPU_DFS_ON ?= yes
+
+#*******************************************************************************
+# AXIµ÷Ƶ¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_AXI_DFS_ON ?= yes
+
+ifeq ($(USE_AXI_DFS_ON), yes)
+
+export USE_AXI_DFS_ON_HW ?= yes
+ifeq ($(USE_AXI_DFS_ON_HW), no)
+export USE_AXI_DFS_ON_SW ?= no
+endif
+
+endif
+
+#*******************************************************************************
+# DDR×Ô¶¯×Ôˢй¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_DDR_AUTO_ON ?= yes
+
+#*******************************************************************************
+# DDRµ÷Ƶ¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_DDR_DFS_ON ?= no
+
+
+#*******************************************************************************
+# VCOREµ÷ѹ¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_VCORE_DVS_ON ?= no
+
+
+#*******************************************************************************
+# ƽ̨²¹¶¡ºê---RFÊ¡µçºêÊÇ·ñ»¥³â¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+export USE_PSM_RF_MUTEX ?= yes
+
+
+#*******************************************************************************
+# ƽ̨²¹¶¡ºê---NMIÖжÏÌ滻ΪICP
+#*******************************************************************************
+export USE_LPM_R7_WAKE_ZSP ?= no
+
+
+#*******************************************************************************
+# ƽ̨²¹¶¡ºê---ICPÖ¡Öжϵ÷¶È
+#*******************************************************************************
+export USE_ICP_SFN_INT ?= no
+
+
+#*******************************************************************************
+# ƽ̨²¹¶¡ºê---DPLL¿ØÖƺê
+#*******************************************************************************
+export USE_DPLL_HW_CTRL ?= no
+
diff --git a/pub/project/zx297520v3/config/tools_cfg.mk b/pub/project/zx297520v3/config/tools_cfg.mk
new file mode 100644
index 0000000..f8852a5
--- /dev/null
+++ b/pub/project/zx297520v3/config/tools_cfg.mk
@@ -0,0 +1,19 @@
+# /*****************************************************************************
+#* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+#*
+#* ÎļþÃû³Æ: tools_cfg.mk
+#* Îļþ±êʶ: tools_cfg.mk
+#* ÄÚÈÝÕªÒª: zx297520¹¤¾ß¹¤³ÌÅäÖÃÎļþ
+#* ʹÓ÷½·¨: include project.mk
+#*
+#* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+#* -----------------------------------------------------------------------------
+#* 2015/06/13 V1.0 Create ÁõÑÇÄÏ ´´½¨
+#*
+# ******************************************************************************/
+
+#*******************************************************************************
+# ¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+
+
diff --git a/pub/project/zx297520v3/include/amt/.gitignore b/pub/project/zx297520v3/include/amt/.gitignore
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/pub/project/zx297520v3/include/amt/.gitignore
diff --git a/pub/project/zx297520v3/include/drv/NvParam_drv.h b/pub/project/zx297520v3/include/drv/NvParam_drv.h
new file mode 100644
index 0000000..b75a563
--- /dev/null
+++ b/pub/project/zx297520v3/include/drv/NvParam_drv.h
@@ -0,0 +1,221 @@
+/***********************************************************************
+* Copyright (C) 2016, ZTE Corporation.
+*
+* File Name: nvparam_drv.h
+* File Mark:
+* Description:
+* Others:
+* Version: v1.0
+* Author: wangxia
+* Date: 2016-03-12
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+* History 2:
+**********************************************************************/
+#ifndef NVPARAM_DRV_H
+#define NVPARAM_DRV_H
+
+/**************************************************************************
+ * Include files *
+ **************************************************************************/
+#include "RWNvConfig.h"
+#include "NvParam_tsc.h"
+/**************************************************************************
+ * Macro *
+ **************************************************************************/
+#define DRV_NV_ADDR OS_FLASH_DRV_RW_NONFAC_BASE_ADDR
+#define DRV_NV_SIZE OS_FLASH_DRV_RW_NONFAC_SIZE /*16K*/
+
+/*=====================================================================================================================
+|----------------|----------------|---------------|--------------|----------------|-----------------|-----------------|
+| public(256B) | system(3K) | platfor(3K) | highspeed(4K)| peripheral(3K) | audio(1K) | reserved(1.75K) |
+|----------------|----------------|---------------|--------------|----------------|-----------------|-----------------|
+=======================================================================================================================*/
+
+#define DRV_PUB_NV_ADDR DRV_NV_ADDR
+#define DRV_PUB_NV_SIZE (256)
+#define DRV_SYS_NV_ADDR (DRV_PUB_NV_ADDR + DRV_PUB_NV_SIZE)
+#define DRV_SYS_NV_SIZE (3 * 1024)
+#define DRV_PLAT_NV_ADDR (DRV_SYS_NV_ADDR + DRV_SYS_NV_SIZE)
+#define DRV_PLAT_NV_SIZE (3 * 1024)
+#define DRV_HS_PERI_NV_ADDR (DRV_PLAT_NV_ADDR + DRV_PLAT_NV_SIZE)
+#define DRV_HS_PERI_NV_SIZE (4 * 1024)
+#define DRV_PERI_NV_ADDR (DRV_HS_PERI_NV_ADDR + DRV_HS_PERI_NV_SIZE)
+#define DRV_PERI_NV_SIZE (3 * 1024)
+#define DRV_AUDIO_NV_ADDR (DRV_PERI_NV_ADDR + DRV_PERI_NV_SIZE)
+#define DRV_AUDIO_NV_SIZE (1 * 1024)
+#define DRV_RSVD_NV_ADDR (DRV_AUDIO_NV_ADDR + DRV_AUDIO_NV_SIZE)
+#define DRV_RSVD_NV_SIZE (1 * 1024 + 768)
+
+#define DRV_TOTAL_NV_SIZE (DRV_PUB_NV_SIZE+DRV_SYS_NV_SIZE+DRV_PLAT_NV_SIZE+DRV_HS_PERI_NV_SIZE+DRV_PERI_NV_SIZE+DRV_AUDIO_NV_SIZE+DRV_RSVD_NV_SIZE)
+
+/* user interface */
+#define DRV_PUB_NV_ITEM_ADDR(x) (DRV_PUB_NV_ADDR + (UINT32)(&(((T_ZDrvNv_PubData*)(0x0))->x)))
+#define DRV_PUB_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_PubData*)(0x0))->x))
+
+#define DRV_SYS_NV_ITEM_ADDR(x) (DRV_SYS_NV_ADDR + (UINT32)(&(((T_ZDrvNv_SysData*)(0x0))->x)))
+#define DRV_SYS_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_SysData*)(0x0))->x))
+
+#define DRV_PLAT_NV_ITEM_ADDR(x) (DRV_PLAT_NV_ADDR + (UINT32)(&(((T_ZDrvNv_PlatData*)(0x0))->x)))
+#define DRV_PLAT_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_PlatData*)(0x0))->x))
+
+#define DRV_HS_PERI_NV_ITEM_ADDR(x) (DRV_HS_PERI_NV_ADDR + (UINT32)(&(((T_ZDrvNv_HSPeriData*)(0x0))->x)))
+#define DDRV_HS_PER_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_HSPeriData*)(0x0))->x))
+
+#define DRV_PER_NV_ITEM_ADDR(x) (DRV_PERI_NV_ADDR + (UINT32)(&(((T_ZDrvNv_PeriData*)(0x0))->x)))
+#define DRV_PER_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_PeriData*)(0x0))->x))
+
+#define DRV_AUDIO_NV_ITEM_ADDR(x) (DRV_AUDIO_NV_ADDR + (UINT32)(&(((T_ZDrvNv_AudioData*)(0x0))->x)))
+#define DRV_AUDIO_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_AudioData*)(0x0))->x))
+
+#define OS_FLASH_VOICE_DRV_RW_NONFAC_BASE_ADDR (OS_FLASH_DRV_RW_NONFAC_BASE_ADDR + 15360)
+#define OS_FLASH_VOICE_DRV_NONFAC_SIZE 1024
+
+#if DRV_TOTAL_NV_SIZE > (OS_FLASH_DRV_RW_NONFAC_SIZE)
+#error "error drv nv config!!!"
+#endif
+
+/****************************************************************************
+* Types
+****************************************************************************/
+
+
+/******************************************************
+* Drv NV Config
+******************************************************/
+/***********************************
+1. public nv_data
+************************************/
+typedef struct _T_ZDrvNv_PubData
+{
+ /* 0x00 */ CHAR chipName[16];
+ /* 0x10 */ CHAR prjName[16];
+ /* 0x20 */ CHAR externalVer[16];
+ /* 0x30 */ CHAR internalVer[16];
+ /* 0x40 */ CHAR releaseTime[16];
+ /* 0x50 */ UINT8 productType;
+ /* 0x51 */ UINT8 reserved[DRV_PUB_NV_SIZE - 0x51];
+} __attribute__ ((packed)) T_ZDrvNv_PubData;
+
+/***********************************
+2. system group nv_data
+************************************/
+typedef struct _T_ZDrvNv_SysData
+{
+ /* 0x000 */ T_SYS_NV_TSC_CONFIG tsc_config;
+ UINT8 reserved0[12];
+ /* 0x70 */ UINT32 buck1OnoffFlag;
+ /* 0x74 */ UINT32 wdtSwitch;
+ /* 0x78 */ UINT32 wdtPriority;
+ /* 0x7C */ UINT8 uiccmodeSwitch;
+ /* 0x7D */ UINT8 uiccPreSwitch;
+ /* 0x7E */ UINT8 uicc1modeSwitch;
+ /* 0x7F */ UINT8 uicc1PreSwitch;
+ UINT8 reserved[DRV_SYS_NV_SIZE - 124 - 4];
+} __attribute__ ((packed)) T_ZDrvNv_SysData;
+
+/***********************************
+3. platform group nv_data
+************************************/
+typedef struct _T_ZDrvNv_PlatData
+{
+ UINT8 reserved[DRV_PLAT_NV_SIZE];
+} __attribute__ ((packed)) T_ZDrvNv_PlatData;
+
+/***********************************
+4. hign-speed peripheral group nv_data
+************************************/
+typedef struct _T_ZDrvNv_HSPeriData
+{
+ UINT8 reserved[DRV_HS_PERI_NV_SIZE];
+} __attribute__ ((packed)) T_ZDrvNv_HSPeriData;
+
+/***********************************
+5. common peripheral group nv_data
+************************************/
+typedef struct _T_ZDrvNv_PeriData
+{
+ UINT8 bat_det;
+ UINT8 reserved[DRV_PERI_NV_SIZE-1];
+} __attribute__ ((packed)) T_ZDrvNv_PeriData;
+
+/***********************************
+6. audio group nv_data
+************************************/
+typedef struct _T_ZDrvNv_AudioData
+{
+ UINT8 reserved[DRV_AUDIO_NV_SIZE];
+} __attribute__ ((packed)) T_ZDrvNv_AudioData;
+
+/***********************************
+7. all driver_used nv_data
+************************************/
+typedef struct _T_ZDrv_NvData
+{
+ /* 0x0000 */ T_ZDrvNv_PubData pubData;
+ /* 0x0100 */ T_ZDrvNv_SysData sysData;
+ /* 0x0D00 */ T_ZDrvNv_PlatData platData;
+ /* 0x1900 */ T_ZDrvNv_HSPeriData HSPeriData;
+ /* 0x2900 */ T_ZDrvNv_PeriData periData;
+ /* 0x3500 */ T_ZDrvNv_AudioData audioData;
+ /* 0x3900 */ UINT8 reserved[DRV_RSVD_NV_SIZE];
+} T_ZDrv_NvData;
+
+
+/******************************************************
+* check struct size
+******************************************************/
+static inline CHAR zDrvNv_CheckTypeSize(void)
+{ \
+ CHAR __dummy1[(sizeof(T_ZDrv_NvData)==DRV_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy2[(sizeof(T_ZDrvNv_PubData)==DRV_PUB_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy3[(sizeof(T_ZDrvNv_SysData)==DRV_SYS_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy4[(sizeof(T_ZDrvNv_PlatData)==DRV_PLAT_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy5[(sizeof(T_ZDrvNv_HSPeriData)==DRV_HS_PERI_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy6[(sizeof(T_ZDrvNv_PeriData)==DRV_PERI_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy7[(sizeof(T_ZDrvNv_AudioData)==DRV_AUDIO_NV_SIZE)?1:-1]={0}; \
+ return (__dummy1[0]+__dummy2[0]+__dummy3[0]+__dummy4[0]+__dummy5[0]+__dummy6[0]+__dummy7[0]); \
+}
+
+/******************************************************
+* old struct
+******************************************************/
+#if 0
+typedef struct _T_Sys_Drv_Nv_Data
+{
+ T_SYS_NV_TSC_CONFIG tsc_config;
+ UINT8 reserved[6];
+ UINT32 wdtSwitch;
+}T_Sys_Drv_Nv_Data;
+#endif
+typedef struct _T_Drv_Nv_Data
+{
+ UINT32 VpData[1024];//add by lvwenhua for voice 2013.12.6
+}T_Drv_Nv_Data;
+
+#define DRV_NV_ITEM_ADDRESS(x) (DRV_AUDIO_NV_ADDR + (UINT32)(&(((T_Drv_Nv_Data*)(0x0))->x)))
+//flag use 32byte
+typedef struct _T_Audio_NvFlag
+{
+ UINT8 isVpConfigInitOn;
+ UINT8 isVpParamInNv;
+ UINT8 isUseSlicCodec;
+ UINT8 isUseVoiceProc;//UINT8 isUseNXP;
+ UINT8 isUseCodecDsp;
+ UINT8 isUseNvWrite;
+ UINT8 isCloseVpBufferBak;
+ UINT8 isUseTdm;
+ UINT8 isUseRxDtmfDet;
+ UINT8 isUseTxDtmfDet;
+ UINT8 isUseRxMixData;
+ UINT8 isUseTxMixData;//12¸öflag
+ UINT8 reserved[20];//32-12
+
+} T_Audio_NvFlag;
+
+#endif
+
diff --git a/pub/project/zx297520v3/include/drv/dma_cfg.h b/pub/project/zx297520v3/include/drv/dma_cfg.h
new file mode 100644
index 0000000..9cb018e
--- /dev/null
+++ b/pub/project/zx297520v3/include/drv/dma_cfg.h
@@ -0,0 +1,215 @@
+/*******************************************************************************
+ * Copyright (C) 2008, ZTE Corporation.
+ *
+ * File Name: dma_cfg.h
+ * File Mark:
+ * Description:define dma ram config
+
+ * Others:
+ * Version: v0.1
+ * Author: wangxia
+ * Date: 2016-02-18
+ * History 1:
+ * Date: 2016-03-23
+ * Version:
+ * Author: wangxia
+ * Modification: add IRAM0 config
+ *
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _DMA_CFG_H
+#define _DMA_CFG_H
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "ram_config.h"
+/****************************************************************************
+* Local Macros
+****************************************************************************/
+
+//#define DMA_RAM_BASE_ADDR DDR_BASE_ADDR_DRV
+#define DMA_RAM_SIZE DDR_BASE_LEN_DRV /*6.5M*/
+
+/*for EDCP, 64k*/
+#define DMA_RAM_FOR_EDCP_ADDR_BASE (DMA_RAM_BASE_ADDR)
+#define DMA_RAM_FOR_EDCP_SIZE 0x10000
+
+/*for UART, 64k*/
+#define DMA_RAM_FOR_UART_ADDR_BASE (DMA_RAM_FOR_EDCP_ADDR_BASE + DMA_RAM_FOR_EDCP_SIZE)
+#define DMA_RAM_FOR_UART_SIZE 0x10000
+
+/* SD */
+#define DMA_RAM_FOR_SD_ADDR_BASE (DMA_RAM_FOR_UART_ADDR_BASE + DMA_RAM_FOR_UART_SIZE)
+#define DMA_RAM_FOR_SD_SIZE 0x30000//0x10000
+
+
+
+/*for USB, 2M ×é°ü */
+#define DMA_RAM_FOR_USB_ADDR_BASE (DMA_RAM_BASE_ADDR + 0x80000)
+#define DMA_RAM_FOR_USB_SIZE 0x80000
+
+
+
+#if 0
+/*for I2S,120k*/
+#define DMA_RAM_FOR_I2S_ADDR_BASE (DMA_RAM_FOR_USB_ADDR_BASE+DMA_RAM_FOR_USB_SIZE)
+#define DMA_RAM_FOR_I2S_SIZE 0x1E000
+
+/*for F8,5k*/
+#define DMA_RAM_FOR_F8_ADDR_BASE (DMA_RAM_FOR_I2S_ADDR_BASE + DMA_RAM_FOR_I2S_SIZE)
+#define DMA_RAM_FOR_F8_SIZE 0x1400
+
+/*for F9,5k*/
+#define DMA_RAM_FOR_F9_ADDR_BASE (DMA_RAM_FOR_F8_ADDR_BASE + DMA_RAM_FOR_F8_SIZE)
+#define DMA_RAM_FOR_F9_SIZE 0x1400
+
+/*for UART, 64k*/
+#define DMA_RAM_FOR_UART_ADDR_BASE (DMA_RAM_FOR_F9_ADDR_BASE + DMA_RAM_FOR_F9_SIZE)
+#define DMA_RAM_FOR_UART_SIZE 0x10000
+
+/*for NAND, 64k*/
+#define DMA_RAM_FOR_NAND_ADDR_BASE (DMA_RAM_FOR_UART_ADDR_BASE + DMA_RAM_FOR_UART_SIZE)
+#define DMA_RAM_FOR_NAND_SIZE 0x10000
+
+/*for EDCP, 64k*/
+#define DMA_RAM_FOR_EDCP_ADDR_BASE (DMA_RAM_FOR_NAND_ADDR_BASE + DMA_RAM_FOR_NAND_SIZE)
+#define DMA_RAM_FOR_EDCP_SIZE 0x10000
+
+/*for DMA LLI 32K*/
+#define DMA_RAM_FOR_DMA_LLI_ADDR_BASE (DMA_RAM_FOR_EDCP_ADDR_BASE+DMA_RAM_FOR_EDCP_SIZE)
+#define DMA_RAM_FOR_DMA_LLI_SIZE 0x8000
+
+/*for SSP 256K*/
+#define DMA_RAM_FOR_SSP_ADDR_BASE (DMA_RAM_FOR_DMA_LLI_ADDR_BASE+DMA_RAM_FOR_DMA_LLI_SIZE)
+#define DMA_RAM_FOR_SSP_SIZE 0x10000
+
+/*for WIFI 512K£ºAP²àʹÓÃ*/
+#define DMA_RAM_FOR_WIFI_ADDR_BASE (DMA_RAM_FOR_SSP_ADDR_BASE+DMA_RAM_FOR_SSP_SIZE)
+#define DMA_RAM_FOR_WIFI_SIZE 0x80000
+
+/*for GMAC 512K£ºAP²àʹÓÃ*/
+#define DMA_RAM_FOR_GMAC_ADDR_BASE (DMA_RAM_FOR_WIFI_ADDR_BASE+DMA_RAM_FOR_WIFI_SIZE)
+#define DMA_RAM_FOR_GMAC_SIZE 0x80000
+
+/*for CAM 616K*/
+#define DMA_RAM_FOR_CAM_ADDR_BASE (DMA_RAM_FOR_GMAC_ADDR_BASE+DMA_RAM_FOR_GMAC_SIZE)
+#define DMA_RAM_FOR_CAM_SIZE 0x9a000
+
+/* SD */
+#define DMA_RAM_FOR_SD_ADDR_BASE (DMA_RAM_FOR_CAM_ADDR_BASE + DMA_RAM_FOR_CAM_SIZE)
+#define DMA_RAM_FOR_SD_SIZE 0x30000//0x10000
+#endif
+
+
+//#define DMA_RAM_CONFIG_END (DMA_RAM_FOR_SD_ADDR_BASE+DMA_RAM_FOR_SD_SIZE)
+
+//#if DMA_RAM_CONFIG_END > (DMA_RAM_BASE_ADDR+DMA_RAM_SIZE)
+//#error error dma_cfg !!!!!!!!!!!!!!!
+//#endif
+
+/*---------------------------DMA ADDR For PSM-----------------------------------*/
+#define DMA_RAM_FOR_PSM_ADDR_BASE DDR_BASE_ADDR_PSM
+#define DMA_PSM_RAM_SIZE (0x00050000UL>>CPU_SHIFT)/*320k*/
+
+/*for M0 64K*/
+#define DMA_PSM_RAM_FOR_M0 DMA_RAM_FOR_PSM_ADDR_BASE
+#define DMA_PSM_RAM_FOR_M0_SIZE (0x00010000UL>>CPU_SHIFT)
+
+/*for ZSP 256K*/
+#define DMA_PSM_RAM_FOR_ZSP (DMA_PSM_RAM_FOR_M0+DMA_PSM_RAM_FOR_M0_SIZE)
+#define DMA_PSM_RAM_FOR_ZSP_SIZE (0x00040000UL>>CPU_SHIFT)
+
+/*for PS 128K*/
+//#define DMA_PSM_RAM_FOR_R7 (DMA_PSM_RAM_FOR_ZSP+DMA_PSM_RAM_FOR_ZSP_SIZE)
+//#define DMA_PSM_RAM_FOR_R7_SIZE (0x00020000UL>>CPU_SHIFT)
+
+/*for AP 256K*/
+//#define DMA_PSM_RAM_FOR_A9 (DMA_PSM_RAM_FOR_R7+DMA_PSM_RAM_FOR_R7_SIZE)
+//#define DMA_PSM_RAM_FOR_A9_SIZE 0x40000
+
+#define DMA_PSM_RAM_CONFIG_END (DMA_PSM_RAM_FOR_ZSP+DMA_PSM_RAM_FOR_ZSP_SIZE)
+
+//#if DMA_PSM_RAM_CONFIG_END > (DMA_RAM_FOR_PSM_ADDR_BASE+DMA_PSM_RAM_SIZE)
+//#error error psm_dma_cfg !!!!!!!!!!!!!!!
+//#endif
+
+/*------------------------------IRAM0 config-------------------------------------------------------------------*/
+
+/* IRAM0ÖеÄÖ¸¶¨µØÖ·´æ´¢ÇøÓò */
+#define ICP_MSG_DRV_BASE_ADDR (IRAM_BASE_ADDR_DRV)
+#define ICP_MSG_SIZE ((0x25C0UL)>>CPU_SHIFT)
+
+/*SPILOCK 256byte*/
+#define SOFTLOCK_BASE (IRAM_BASE_ADDR_DRV + ICP_MSG_SIZE)
+#define SOFTLOCK_SIZE (0x100UL>>CPU_SHIFT)
+
+/*AP<->CP DMA LOCK 256byte*/
+#define DMA_SHARED_IRAM_BASE (SOFTLOCK_BASE + SOFTLOCK_SIZE) /*spinlock ºóÃæ0x100µØÖ·±£Áô£¬¸øDMAʹÓÃ*/
+#define DMA_SHARED_IRAM_SIZE (0x100UL>>CPU_SHIFT)
+
+/*power on type 4byte*/
+#define POWERON_TYPE_ADDR (DMA_SHARED_IRAM_BASE + DMA_SHARED_IRAM_SIZE)
+#define POWERON_TYPE_SIZE (0x4UL>>CPU_SHIFT)
+
+/*boot mode 4byte*/
+#define CFG_BOOT_MODE_SAVE_ADDR_FOR_UBOOT (POWERON_TYPE_ADDR + POWERON_TYPE_SIZE)
+#define CFG_BOOT_MODE_SAVE_ADDR_FOR_UBOOT_SIZE (0x4UL>>CPU_SHIFT)
+
+/*boot start mode 4byte*/
+#define CFG_BOOT_MODE_START_MODE_FOR_UBOOT (CFG_BOOT_MODE_SAVE_ADDR_FOR_UBOOT + CFG_BOOT_MODE_SAVE_ADDR_FOR_UBOOT_SIZE)
+#define CFG_BOOT_MODE_START_MODE_FOR_UBOOT_SIZE (0x4UL>>CPU_SHIFT)
+
+/*secure puk 256byte*/
+#define CFG_SECURE_PUK_ADDR (CFG_BOOT_MODE_START_MODE_FOR_UBOOT + CFG_BOOT_MODE_START_MODE_FOR_UBOOT_SIZE)
+#define CFG_SECURE_PUK_SIZE (0x100UL>>CPU_SHIFT)
+
+/*wdt iram flag 36byte*/
+#define WDT_NV_ADDR (CFG_SECURE_PUK_ADDR + CFG_SECURE_PUK_SIZE)
+#define WDT_NV_SIZE (0x4UL>>CPU_SHIFT)
+
+#define WDT_GLOBAL_COUNT_ADDR (WDT_NV_ADDR + WDT_NV_SIZE)
+#define WDT_GLOBAL_COUNT_SIZE (0x4UL>>CPU_SHIFT)
+
+#define WDT_PS_TIMEOUT_ADDR (WDT_GLOBAL_COUNT_ADDR + WDT_GLOBAL_COUNT_SIZE)
+#define WDT_PS_TIMEOUT_SIZE (0x4UL>>CPU_SHIFT)
+
+#define WDT_AP_TIMEOUT_ADDR (WDT_PS_TIMEOUT_ADDR + WDT_PS_TIMEOUT_SIZE)
+#define WDT_AP_TIMEOUT_SIZE (0x4UL>>CPU_SHIFT)
+
+#define WDT_PHY_TIMEOUT_ADDR (WDT_AP_TIMEOUT_ADDR + WDT_AP_TIMEOUT_SIZE)
+#define WDT_PHY_TIMEOUT_SIZE (0x4UL>>CPU_SHIFT)
+
+#define WDT_M0_SWITCH_ADDR (WDT_PHY_TIMEOUT_ADDR + WDT_PHY_TIMEOUT_SIZE)
+#define WDT_M0_SWITCH_SIZE (0x4UL>>CPU_SHIFT)
+
+#define WDT_PS_SWITCH_ADDR (WDT_M0_SWITCH_ADDR + WDT_M0_SWITCH_SIZE)
+#define WDT_PS_SWITCH_SIZE (0x4UL>>CPU_SHIFT)
+
+#define WDT_AP_SWITCH_ADDR (WDT_PS_SWITCH_ADDR + WDT_PS_SWITCH_SIZE)
+#define WDT_AP_SWITCH_SIZE (0x4UL>>CPU_SHIFT)
+
+#define WDT_PHY_SWITCH_ADDR (WDT_AP_SWITCH_ADDR + WDT_AP_SWITCH_SIZE)
+#define WDT_PHY_SWITCH_SIZE (0x4UL>>CPU_SHIFT)
+
+#define FB_REGSTER_FLAG_ADDR (WDT_PHY_SWITCH_ADDR + WDT_PHY_SWITCH_SIZE)
+#define FB_REGSTER_FLAG_SIZE (0x4UL)
+
+#define M0_IMAGE_READY_FLAG_ADDR (FB_REGSTER_FLAG_ADDR + FB_REGSTER_FLAG_SIZE)
+#define M0_IMAGE_READY_FLAG_SIZE (0x4UL)
+
+#define BOOT_FLAG_ADDR (M0_IMAGE_READY_FLAG_ADDR + M0_IMAGE_READY_FLAG_SIZE)
+#define BOOT_FLAG_SIZE (0x4UL)
+
+#define EXCEPT_FLAG_ADDR (BOOT_FLAG_ADDR + BOOT_FLAG_SIZE)
+#define EXCEPT_FLAG_SIZE (0x4UL)
+
+#define RAM_CONFIG_END (EXCEPT_FLAG_ADDR+EXCEPT_FLAG_SIZE)
+
+//#if RAM_CONFIG_END > (IRAM_BASE_ADDR_DRV+IRAM_BASE_LEN_DRV)
+//#error error drv_ram_cfg !!!!!!!!!!!!!!!
+//#endif
+
+#endif
+
+
diff --git a/pub/project/zx297520v3/include/drv/drvs_regmap.inc b/pub/project/zx297520v3/include/drv/drvs_regmap.inc
new file mode 100644
index 0000000..69dfeea
--- /dev/null
+++ b/pub/project/zx297520v3/include/drv/drvs_regmap.inc
@@ -0,0 +1,145 @@
+/*******************************************************************************
+ * Copyright (C) 2014, ZTE Corporation.
+ *
+ * File Name: drvs_ADDR_regmap.inc
+ * File Mark:
+ * Description: This file contains the register map.
+ * Others:
+ * Version: V1.0
+ * Author: zhangdongdong
+ * Date: 2015-07-31
+ * History 1:
+ *
+ *********************************************************************************/
+#ifndef _DRVS_REGMAP_H
+#define _DRVS_REGMAP_H
+
+/* M2 */
+#define ADDR_IROM 0x00000000
+
+/* M3 */
+#define ADDR_IRAM2 0x00080000
+
+/* M4 -- A1 CFG */
+#define ADDR_IRAM1 0x00100000
+#define ADDR_KEY 0x00130000
+#define ADDR_UART0 0x00131000
+#define ADDR_I2C_PMIC 0x00132000
+#define ADDR_RTC 0x00133000
+#define ADDR_LPM_GSM 0x00134000
+#define ADDR_LPM_LTE 0x00134200
+#define ADDR_LPM_TD 0x00134400
+#define ADDR_LPM_W 0x00134600
+#define ADDR_PS_TIMER1 0x00138000
+#define ADDR_PS_TIMER2 0x00139000
+#define ADDR_PCU 0x0013A000
+#define ADDR_TOP_CRM 0x0013B000
+#define ADDR_PAD_CTRL_A0 0x0013C000
+#define ADDR_GPIO0 0x0013D000
+#define ADDR_GPIO1 0x0013E000
+#define ADDR_SOC_SYS 0x00140000
+#define ADDR_RM_TIMER0 0x00142000
+#define ADDR_AP_TIMER1 0x00143000
+#define ADDR_AP_TIMER2 0x00144000
+#define ADDR_RM_TIMER1 0x00145000
+#define ADDR_AP_TIMER3 0x00146000
+#define ADDR_PHY_TIMER1 0x00147000
+#define ADDR_RM_WDT 0x00148000
+#define ADDR_DDR_CTRL 0x00150000
+#define ADDR_DDR_PHY 0x00154000
+#define ADDR_DDR_FFC 0x00155000
+#define ADDR_USIM1 0x00156000
+#define ADDR_RM2MATRIX 0x00200000
+
+#define ADDR_NIC400_MATRIX1_CFG 0x10500000
+
+/* M2 -- AHB CFG0 */
+#define ADDR_EDCP 0x01200000
+#define ADDR_SD0 0x01210000
+#define ADDR_SD1 0x01211000
+#define ADDR_NAND_REG 0x01214000
+#define ADDR_NAND_DATA 0x01215000
+#define ADDR_EFUSE 0x0121B000
+#define ADDR_RSA 0x0121C000
+#define ADDR_HASH 0x0121D000
+#define ADDR_USB 0x01500000
+#define ADDR_HSIC 0x01600000
+
+/* M2 -- AHB2APB */
+#define ADDR_DMA_PHY 0x01300000
+#define ADDR_DMA_PS 0x01301000
+#define ADDR_ICP 0x01302000
+#define ADDR_AP_CPU_SLAVE 0x03000000
+#define ADDR_PS_CPU_SLAVE 0x06000000
+
+/* M2 -- APB LITE 0 */
+#define ADDR_PIN_MUX 0x01303000
+#define ADDR_SSC 0x01304000
+#define ADDR_STD_CRM 0x01306000 /*matrix crm*/
+#define ADDR_GMAC 0x01307000
+#define ADDR_VOU_CFG 0x01380000
+
+/* M1 -- LSP */
+#define ADDR_LSP_CRM 0x01400000
+#define ADDR_LSP_PS_TIMER0 0x01401000
+#define ADDR_LSP_PHY_WDT 0x01402000
+#define ADDR_LSP_PS_WDT 0x01403000
+#define ADDR_LSP_PWM 0x01404000
+#define ADDR_LSP_I2S0 0x01405000
+#define ADDR_LSP_I2S1 0x01406000
+#define ADDR_LSP_SPIFC0 0x01407000
+#define ADDR_LSP_UART1 0x01408000
+#define ADDR_LSP_I2C1 0x01409000
+#define ADDR_LSP_SSP0 0x0140A000
+#define ADDR_LSP_PS_RM_TIMER 0x0140B000
+#define ADDR_LSP_PHY_TIMER0 0x0140C000
+#define ADDR_LSP_UART2 0x0140D000
+#define ADDR_LSP_AP_WDT 0x0140E000
+#define ADDR_LSP_AP_TIMER0 0x0140F000
+#define ADDR_LSP_SSP1 0x01410000
+#define ADDR_LSP_AP_TIMER4 0x01411000
+#define ADDR_LSP_TDM 0x01412000
+
+/* DDR */
+#define ADDR_DDR_BASE 0x20000000
+
+/* GSM */
+#define ADDR_GSM_CFG 0xF3000000
+#define ADDR_GSM_MODEM1 0xF4000000
+#define ADDR_GSM_MODEM2 0xF6000000
+
+/* PHY CPU SALVE */
+#define ADDR_PHY_L2TCM 0x600C0000
+#define ADDR_PHY_DTCM 0x81000000
+#define ADDR_PHY_ITCM 0x81040000
+#define ADDR_PHY_CRM 0x81800000
+#define ADDR_PHY_ICU 0x81801000
+
+/* IRAM0 */
+#define ADDR_IRAM0 0x82000000
+
+/* PS MG */
+#define ADDR_MG_CRM 0xF2200000
+
+#define ADDR_MG_GICC 0x02900000
+#define ADDR_MG_GICD 0xF2000000
+#define ADDR_MG_GICR 0xF2040000
+
+/*need confirm*/
+#define ADDR_MG_CFG 0x00801000
+#define ADDR_MG_SCU 0xEF000000
+
+/* M2 MODEM */
+#define ADDR_LTE_MODEM_D 0xF8000000
+#define ADDR_WD_MODEM_D 0xF8100000
+#define ADDR_TD_MODEM_D 0xF8200000
+
+/* M1 MODEM */
+#define ADDR_LTE_MODEM_C 0xFC000000
+#define ADDR_WD_MODEM_C 0xFC100000
+#define ADDR_TD_MODEM_C 0xFC200000
+
+#define ADDR_NIC400_MATRIX0_CFG 0xF7500000
+
+
+#endif
diff --git a/pub/project/zx297520v3/include/drv/drvs_zx297520v3_regmap.inc b/pub/project/zx297520v3/include/drv/drvs_zx297520v3_regmap.inc
new file mode 100644
index 0000000..8f233d3
--- /dev/null
+++ b/pub/project/zx297520v3/include/drv/drvs_zx297520v3_regmap.inc
@@ -0,0 +1,152 @@
+/*******************************************************************************
+ * Copyright (C) 2014, ZTE Corporation.
+ *
+ * File Name: drvs_zx297520V3_regmap.inc
+ * File Mark:
+ * Description: This file contains the register map of ZX297520V3.
+ * Others:
+ * Version: V1.0
+ * Author: zhangdongdong
+ * Date: 2015-07-31
+ * History 1:
+ *
+ *********************************************************************************/
+#ifndef _DRVS_ZX297520V3_REGMAP_H
+#define _DRVS_ZX297520V3_REGMAP_H
+
+/* M2 */
+#define ZX297520V3_IROM 0x00000000
+
+/* M3 */
+#define ZX297520V3_IROM2 0x00080000
+
+/* M4 -- A1 CFG */
+#define ZX297520V3_A1_IRAM1 0x00100000
+#define ZX297520V3_A1_KEY 0x00130000
+#define ZX297520V3_A1_UART0 0x00131000
+#define ZX297520V3_A1_I2C_PMIC 0x00132000
+#define ZX297520V3_A1_RTC 0x00133000
+#define ZX297520V3_A1_LPM_GSM 0x00134000
+#define ZX297520V3_A1_LPM_LTE 0x00134200
+#define ZX297520V3_A1_LPM_TD 0x00134400
+#define ZX297520V3_A1_LPM_W 0x00134600
+#define ZX297520V3_A1_PS_TIMER1 0x00138000
+#define ZX297520V3_A1_PS_TIMER2 0x00139000
+#define ZX297520V3_A1_PCU 0x0013A000
+#define ZX297520V3_A1_TOP_CRM 0x0013B000
+#define ZX297520V3_A1_PAD_CTRL_A0 0x0013C000
+#define ZX297520V3_A1_GPIO0 0x0013D000
+#define ZX297520V3_A1_GPIO1 0x0013E000
+#define ZX297520V3_A1_SOC_SYS 0x00140000
+#define ZX297520V3_A1_RM_TIMER0 0x00142000
+#define ZX297520V3_A1_AP_TIMER1 0x00143000
+#define ZX297520V3_A1_AP_TIMER2 0x00144000
+#define ZX297520V3_A1_RM_TIMER1 0x00145000
+#define ZX297520V3_A1_AP_TIMER3 0x00146000
+#define ZX297520V3_A1_PHY_TIMER1 0x00147000
+#define ZX297520V3_A1_RM_WDT 0x00148000
+#define ZX297520V3_A1_DDR_CTRL 0x00150000
+#define ZX297520V3_A1_DDR_PHY 0x00154000
+#define ZX297520V3_A1_DDR_FFC 0x00155000
+#define ZX297520V3_A1_USIM1 0x00156000
+#define ZX297520V3_A1_RM2MATRIX 0x00200000
+
+#define ZX297520V3_NIC400_MATRIX1_CFG 0x10500000
+
+#define ZX297520V3_A1_CFG 0x00100000
+
+/* M2 -- AHB CFG0 */
+#define ZX297520V3_EDCP 0x01200000
+#define ZX297520V3_SD0 0x01210000
+#define ZX297520V3_SD1 0x01211000
+#define ZX297520V3_NAND_REG 0x01214000
+#define ZX297520V3_NAND_DATA 0x01215000
+#define ZX297520V3_EFUSE 0x0121B000
+#define ZX297520V3_RSA 0x0121C000
+#define ZX297520V3_HASH 0x0121D000
+#define ZX297520V3_USB 0x01500000
+#define ZX297520V3_HSIC 0x01600000
+
+/* M2 -- AHB2APB */
+#define ZX297520V3_DMA_PHY 0x01300000
+#define ZX297520V3_DMA_PS 0x01301000
+#define ZX297520V3_ICP 0x01302000
+#define ZX297520V3_AP_CPU_SLAVE 0x03000000
+#define ZX297520V3_PS_CPU_SLAVE 0x06000000
+
+/* M2 -- APB LITE 0 */
+#define ZX297520V3_PIN_MUX 0x01303000
+#define ZX297520V3_SSC 0x01304000
+#define ZX297520V3_STD_CRM 0x01306000 /*matrix crm*/
+#define ZX297520V3_GMAC 0x01307000
+#define ZX297520V3_VOU_CFG 0x01380000
+
+/* M1 -- LSP */
+#define ZX297520V3_LSP_CRM 0x01400000
+#define ZX297520V3_LSP_PS_TIMER0 0x01401000
+#define ZX297520V3_LSP_PHY_WDT 0x01402000
+#define ZX297520V3_LSP_PS_WDT 0x01403000
+#define ZX297520V3_LSP_PS_PWM 0x01404000
+#define ZX297520V3_LSP_I2S0 0x01405000
+#define ZX297520V3_LSP_I2S1 0x01406000
+#define ZX297520V3_LSP_SPIFC0 0x01407000
+#define ZX297520V3_LSP_UART1 0x01408000
+#define ZX297520V3_LSP_I2C1 0x01409000
+#define ZX297520V3_LSP_SSP0 0x0140A000
+#define ZX297520V3_LSP_PS_RM_TIMER 0x0140B000
+#define ZX297520V3_LSP_PHY_TIMER0 0x0140C000
+#define ZX297520V3_LSP_UART2 0x0140D000
+#define ZX297520V3_LSP_AP_WDT 0x0140E000
+#define ZX297520V3_LSP_AP_TIMER0 0x0140F000
+#define ZX297520V3_LSP_SSP1 0x01410000
+#define ZX297520V3_LSP_AP_TIMER4 0x01411000
+#define ZX297520V3_LSP_TDM 0x01412000
+
+/* DDR */
+#define ZX297520V3_DDR_BASE 0x20000000
+
+/* GSM */
+#define ZX297520V3_GSM_CFG 0xF3000000
+#define ZX297520V3_GSM_MODEM1 0xF4000000
+#define ZX297520V3_GSM_MODEM2 0xF6000000
+
+/* PHY CPU SALVE */
+#define ZX297520V3_PHY_L2TCM 0x600C0000
+#define ZX297520V3_PHY_DTCM 0x81000000
+#define ZX297520V3_PHY_ITCM 0x81040000
+#define ZX297520V3_PHY_CRM 0x81800000
+#define ZX297520V3_PHY_ICU 0x81801000
+
+
+/* IRAM0 */
+#define ZX297520V3_IRAM0 0x82000000
+
+
+/* PS MG */
+#define ZX297520V3_MG_CRM 0xF2200000
+
+#define ZX297520V3_MG_GICC 0x02900000
+#define ZX297520V3_MG_GICD 0xF2000000
+#define ZX297520V3_MG_GICR 0xF2040000
+
+/*need confirm*/
+#define ZX297520V3_MG_CFG 0x00801000
+#define ZX297520V3_MG_SCU 0xEF000000
+
+
+
+
+
+/* M2 MODEM */
+#define ZX297520V3_LTE_MODEM_D 0xF8000000
+#define ZX297520V3_WD_MODEM_D 0xF8100000
+#define ZX297520V3_TD_MODEM_D 0xF8200000
+
+/* M1 MODEM */
+#define ZX297520V3_LTE_MODEM_C 0xFC000000
+#define ZX297520V3_WD_MODEM_C 0xFC100000
+#define ZX297520V3_TD_MODEM_C 0xFC200000
+
+#define ZX297520V3_NIC400_MATRIX0_CFG 0xF7500000
+
+#endif
diff --git a/pub/project/zx297520v3/include/infra/ram_base_config_7520v3.h b/pub/project/zx297520v3/include/infra/ram_base_config_7520v3.h
new file mode 100755
index 0000000..0c6d0f6
--- /dev/null
+++ b/pub/project/zx297520v3/include/infra/ram_base_config_7520v3.h
@@ -0,0 +1,316 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: ram_config_7520v3.h
+* Îļþ±êʶ: ram_config_7520v3.h
+* ÄÚÈÝÕªÒª: zx297520v3оƬƽ̨´æ´¢µØÖ·ÅäÖÃÍ·Îļþ
+* ʹÓ÷½·¨: #include "ram_config.h"
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2015/06/08 V1.0 Create ÁõÑÇÄÏ ´´½¨
+*
+*******************************************************************************/
+
+#ifndef _RAM_BASE_CONFIG_7520V3
+#define _RAM_BASE_CONFIG_7520V3
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+
+/* IRAM0»ùµØÖ· */
+#ifdef DDR_BASE_ADDR_LINUX_VA
+#define IRAM_BASE_ADDR ((unsigned long)(ZX_IRAM0_BASE))
+#else
+#define IRAM_BASE_ADDR (0x82000000UL>>CPU_SHIFT)
+#endif
+#define IRAM_BASE_LEN (0x00010000UL>>CPU_SHIFT)
+
+/* 1K, Òì³£ÏòÁ¿±í: 0x82000000/0x41000000 */
+#define IRAM_BASE_ADDR_VECTOR (IRAM_BASE_ADDR)
+#define IRAM_BASE_LEN_VECTOR ((1 * 1024UL)>>CPU_SHIFT)
+
+/* 12K£¬Çý¶¯ºË¼äͨѶ */
+#define IRAM_BASE_ADDR_DRV (IRAM_BASE_ADDR_VECTOR + IRAM_BASE_LEN_VECTOR)
+#define IRAM_BASE_LEN_DRV ((12 * 1024UL)>>CPU_SHIFT)
+
+/* 1K£¬Ê¡µçÃüÁî½»»¥ */
+#define IRAM_BASE_ADDR_PSM (IRAM_BASE_ADDR_DRV + IRAM_BASE_LEN_DRV)
+#define IRAM_BASE_LEN_PSM ((1 * 1024UL)>>CPU_SHIFT)
+
+/* 4K£¬PSÓëPHYÐÅÏ¢½»»¥£¬¹«¹²ÒµÎñ */
+#define IRAM_BASE_ADDR_PUB (IRAM_BASE_ADDR_PSM + IRAM_BASE_LEN_PSM)
+#define IRAM_BASE_LEN_PUB ((4 * 1024UL)>>CPU_SHIFT)
+
+/* 512B£¬PSÓëPHYÐÅÏ¢½»»¥£¬ÉäƵ¹«¹²ÒµÎñ */
+#define IRAM_BASE_ADDR_PUB_RF (IRAM_BASE_ADDR_PUB)
+#define IRAM_BASE_LEN_PUB_RF (512UL>>CPU_SHIFT)
+
+/* 32B£¬¸¨Ä£Ê½AFC»º´æÊý¾Ý¿Õ¼ä */
+#define IRAM_BASE_ADDR_SLAVE_AFC (IRAM_BASE_ADDR_PUB_RF + IRAM_BASE_LEN_PUB_RF)
+#define IRAM_BASE_LEN_SLAVE_AFC (32UL>>CPU_SHIFT)
+
+/* 1K£¬Î¿ØÊý¾Ý´æ·Å */
+#define IRAM_BASE_ADDR_TPC (IRAM_BASE_ADDR_PUB + IRAM_BASE_LEN_PUB)
+#define IRAM_BASE_LEN_TPC ((1 * 1024UL)>>CPU_SHIFT)
+
+/* 2K£¬ÖжÏÏ̹߳켣´æ·Å */
+#define IRAM_BASE_ADDR_OS_STATISTIC (IRAM_BASE_ADDR_TPC + IRAM_BASE_LEN_TPC)
+#define IRAM_BASE_LEN_OS_STATISTIC ((2 * 1024UL)>>CPU_SHIFT)
+
+/* 1K,ϵͳ¸ú×ټǼ */
+#define IRAM_BASE_ADDR_SYS_TRACE (IRAM_BASE_ADDR_OS_STATISTIC + IRAM_BASE_LEN_OS_STATISTIC)
+#define IRAM_BASE_LEN_SYS_TRACE ((1 * 1024UL)>>CPU_SHIFT)
+
+/* IRAM ICPµØÖ· */
+#define ICP_CMD_BASE_ADDR (IRAM_BASE_ADDR)
+#define ICP_DRV_BASE_ADDR (IRAM_BASE_ADDR_DRV)
+#define DUAL_STANDBY_INTERF_GSM_USE_INFO_BASE_ADDR (IRAM_BASE_ADDR_GSM)
+
+/* ¸÷ºËIRAM¹ì¼£µØÖ· */
+#define IRAM_BASE_ADDR_OS_STATISTIC_PSCPU (IRAM_BASE_ADDR_OS_STATISTIC)
+#define IRAM_BASE_LEN_OS_STATISTIC_PSCPU (0x200UL>>CPU_SHIFT)
+#define IRAM_BASE_ADDR_OS_STATISTIC_PHYCPU (IRAM_BASE_ADDR_OS_STATISTIC_PSCPU + IRAM_BASE_LEN_OS_STATISTIC_PSCPU)
+#define IRAM_BASE_LEN_OS_STATISTIC_PHYCPU (0x200UL>>CPU_SHIFT)
+#define IRAM_BASE_ADDR_OS_STATISTIC_APCPU (IRAM_BASE_ADDR_OS_STATISTIC_PHYCPU + IRAM_BASE_LEN_OS_STATISTIC_PHYCPU)
+#define IRAM_BASE_LEN_OS_STATISTIC_APCPU (0x400UL>>CPU_SHIFT)
+
+/* ¸÷ºËIRAM¸ú×ÙµØÖ· */
+#define IRAM_BASE_ADDR_SYS_TRACE_RMCPU (IRAM_BASE_ADDR_SYS_TRACE)
+#define IRAM_BASE_ADDR_SYS_TRACE_APCPU (IRAM_BASE_ADDR_SYS_TRACE + (0x10>>CPU_SHIFT))
+#define IRAM_BASE_ADDR_SYS_TRACE_PSCPU (IRAM_BASE_ADDR_SYS_TRACE + (0x20>>CPU_SHIFT))
+#define IRAM_BASE_ADDR_SYS_TRACE_PHYCPU (IRAM_BASE_ADDR_SYS_TRACE + (0x30>>CPU_SHIFT))
+
+/* phy logÓÅ»¯·½°¸¸´Óà IRAM_BASE_ADDR_SYS_TRACE ºó512×Ö½Ú¿Õ¼ä */
+#define IRAM_BASE_ADDR_ZCAT_PHY_LOG (IRAM_BASE_ADDR_SYS_TRACE + (0x200>>CPU_SHIFT))
+
+/* phy log¶ªÊ§¸ú×Ù·½°¸¸´Óà IRAM_BASE_ADDR_SYS_TRACE ºó64×Ö½Ú¿Õ¼ä */
+#define IRAM_BASE_PHY_LOG_DROP_TRACE (IRAM_BASE_ADDR_ZCAT_PHY_LOG + (0x200>>CPU_SHIFT) - (0x40>>CPU_SHIFT))
+
+/* ¼Ç¼zcat ģʽ: 4×Ö½Ú¿Õ¼ä*/
+#define IRAM_BASE_ADDR_ZCAT_MODE (IRAM_BASE_PHY_LOG_DROP_TRACE - (0x04>>CPU_SHIFT))
+
+/* IRAM1»ùµØÖ· */
+#ifdef DDR_BASE_ADDR_LINUX_VA
+#define IRAM1_BASE_ADDR ((unsigned long)(ZX_IRAM1_BASE))
+#else
+#define IRAM1_BASE_ADDR (0x00100000>>CPU_SHIFT)
+#endif
+#define IRAM1_BASE_LEN (0x00003000>>CPU_SHIFT)
+
+
+#define DDR_BASE_ADDR (0x20000000UL>>CPU_SHIFT)
+
+/* 3M£¬ÎïÀí²ã°æ±¾£¬ÓÉPS¼ÓÔØ */
+/* 7520µÄZSPÅäÖÃΪ·ÇCacheÇø£¬Ö»ÄÜÅäÖÃ4¸ö¶Î£¬ÇÒÿ¸ö¶ÎµØÖ·»¹ÓÐÌض¨ÒªÇ󣬸õØÖ·±ä¶¯ÐèÓëÎïÀí²ãÈ·ÈÏ */
+#ifdef DDR_BASE_ADDR_LINUX_VA
+#define DDR_BASE_ADDR_PHY ((unsigned long)(ZX_DDR_PHYCODE_BASE))
+#else
+#define DDR_BASE_ADDR_PHY (DDR_BASE_ADDR)
+#endif
+#define DDR_BASE_LEN_PHY (0x00300000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_PHY (0)
+
+/* 1.5M£¬ÎïÀí²ãDATA/HARQ/CRC */
+#define DDR_BASE_ADDR_PHY_DATA (DDR_BASE_ADDR_PHY + DDR_BASE_LEN_PHY)
+#define DDR_BASE_LEN_PHY_DATA (0x00180000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_PHY_DATA (DDR_BASE_OFF_PHY + DDR_BASE_LEN_PHY)
+
+/* 1.0M£¬ÐÒéÕ»ÓëÎïÀí²ã½»»¥ */
+#define DDR_BASE_ADDR_LTE_DATA (DDR_BASE_ADDR_PHY + DDR_BASE_LEN_PHY) //DDR_BASE_LEN_PHY_NV
+#define DDR_BASE_LEN_LTE_DATA (0x00100000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_LTE_DATA (DDR_BASE_OFF_PHY + DDR_BASE_LEN_PHY)
+
+/* 0.25M£¬Ö§³Åµ¼³öRamdump */
+#define DDR_BASE_ADDR_RAMDUMP (DDR_BASE_ADDR_LTE_DATA + DDR_BASE_LEN_LTE_DATA)
+#define DDR_BASE_LEN_RAMDUMP (0x00040000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_RAMDUMP (DDR_BASE_OFF_LTE_DATA + DDR_BASE_LEN_LTE_DATA)
+
+#ifdef _USE_VEHICLE_DC /* ³µÔØË«ºËLinux */
+/* 27.75M£¬AP¹²ºË°æ±¾(´Ë´óСÊÇ°´ÕÕº¬CAPºËµÄ64MÄÚ´æÅäÖö¨Ò壬¸Ãºê±ð´¦²»»á±»Ê¹ÓÃ) */
+#define DDR_BASE_ADDR_AP (DDR_BASE_ADDR_RAMDUMP + DDR_BASE_LEN_RAMDUMP)
+#define DDR_BASE_LEN_AP (0x01BC0000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_AP (DDR_BASE_OFF_RAMDUMP + DDR_BASE_LEN_RAMDUMP)
+
+/* 2M, share memory between ap and cap */
+#define DDR_BASE_ADDR_CAP_BUF (DDR_BASE_ADDR_AP + DDR_BASE_LEN_AP)
+#define DDR_BASE_LEN_CAP_BUF (0x00200000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_CAP_BUF (DDR_BASE_OFF_AP + DDR_BASE_LEN_AP)
+
+/* 94M/222M, cap°æ±¾ */
+#define DDR_BASE_ADDR_CAP (DDR_BASE_ADDR_CAP_BUF + DDR_BASE_LEN_CAP_BUF)
+#define DDR_BASE_LEN_CAP (0x05E00000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_CAP (DDR_BASE_OFF_CAP_BUF + DDR_BASE_LEN_CAP_BUF)
+#else
+/* 42.75M£¬AP¹²ºË°æ±¾(´Ë´óСÊÇ°´ÕÕº¬CAPºËµÄ64MÄÚ´æÅäÖö¨Ò壬¸Ãºê±ð´¦²»»á±»Ê¹ÓÃ) */
+#define DDR_BASE_ADDR_AP (DDR_BASE_ADDR_RAMDUMP + DDR_BASE_LEN_RAMDUMP)
+#define DDR_BASE_LEN_AP (0x02AC0000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_AP (DDR_BASE_OFF_RAMDUMP + DDR_BASE_LEN_RAMDUMP)
+
+/* 1M, share memory between ap and cap */
+#define DDR_BASE_ADDR_CAP_BUF (DDR_BASE_ADDR_AP + DDR_BASE_LEN_AP)
+#ifndef DDR_BASE_LEN_CAP_BUF
+#define DDR_BASE_LEN_CAP_BUF (0x00100000UL>>CPU_SHIFT)
+#endif
+#define DDR_BASE_OFF_CAP_BUF (DDR_BASE_OFF_AP + DDR_BASE_LEN_AP)
+
+/* 16M, cap°æ±¾ */
+#define DDR_BASE_ADDR_CAP (DDR_BASE_ADDR_CAP_BUF + DDR_BASE_LEN_CAP_BUF)
+#ifndef DDR_BASE_LEN_CAP
+#define DDR_BASE_LEN_CAP (0x01000000UL>>CPU_SHIFT)
+#endif
+#define DDR_BASE_OFF_CAP (DDR_BASE_OFF_CAP_BUF + DDR_BASE_LEN_CAP_BUF)
+#endif
+
+#define DDR_BASE_PHYCODE_ADDR_PA (DDR_BASE_ADDR)
+#define DDR_BASE_MODEM_ADDR_PA (DDR_BASE_PHYCODE_ADDR_PA + DDR_BASE_LEN_PHY)
+#define DDR_BASE_MODEM_SIZE (DDR_BASE_LEN_LTE_DATA + DDR_BASE_LEN_RAMDUMP)
+#define DDR_BASE_AP_ADDR_PA (DDR_BASE_MODEM_ADDR_PA + DDR_BASE_MODEM_SIZE)
+
+#define DDR_BASE_CAPBUF_ADDR_PA (DDR_BASE_AP_ADDR_PA + DDR_BASE_LEN_AP)
+#define DDR_BASE_CAP_ADDR_PA (DDR_BASE_CAPBUF_ADDR_PA + DDR_BASE_LEN_CAP_BUF)
+
+
+/* 1M£¬ÎïÀí²ãNV ¿Õ¼ä¸´Óà */
+#define DDR_BASE_ADDR_PHY_NV (DDR_BASE_ADDR_LTE_DATA)
+#define DDR_BASE_LEN_PHY_NV (0x00100000UL>>CPU_SHIFT)
+
+/* 0.375M£¬Çý¶¯Ê¡µç·þÓÃPS<->PHY½»»¥¿Õ¼ä */
+#define DDR_BASE_ADDR_PSM (DDR_BASE_ADDR_LTE_DATA)
+#define DDR_BASE_LEN_PSM (0x00060000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_PSM (DDR_BASE_OFF_RAMDUMP)
+
+/* 1M£¬ÐÒéÕ»ÓëÎïÀí²ã½»»¥ ¿Õ¼ä¸´Óà */
+#define DDR_BASE_ADDR_WCDMA_DATA (DDR_BASE_ADDR_LTE_DATA)
+#define DDR_BASE_LEN_WCDMA_DATA (DDR_BASE_LEN_LTE_DATA)
+
+#if 0
+/* PsBuffer»ùÖ· */
+#define PS_BUF_BASE_ADDR (DDR_BASE_ADDR_PSBUF)
+#endif
+
+/* ICP»ùÖ· */
+#define ICP_DATA_BASE_ADDR (DDR_BASE_ADDR_LTE_DATA)
+
+/* WCDMA»ùÖ· */
+#define DDR_BASE_ADDR_FOR_W (DDR_BASE_ADDR_WCDMA_DATA)
+
+/* ¹¤¾ß´úÀí»ùÖ· */
+/* #define TOOL_AGENT_BASE_ADDR (DDR_BASE_ADDR_TOOL_AGENT) */
+
+#if 0
+/* PPP»ùÖ· */
+#define PLAT_PPP_BASE_ADDR (PS_BUF_BASE_ADDR)
+#endif
+
+/**/
+#define SHARE_BUF_AP_CP_BASE_ADDR (DDR_BASE_ADDR_AP_CP_SHAREBUF)
+
+#if defined(_USE_CAP_SYS) || defined(_USE_VEHICLE_DC)
+#define ICP_CAP_BUF_ADDR DDR_BASE_ADDR_CAP_BUF
+#define ICP_CAP_BUF_LEN ((924 * 1024UL)>>CPU_SHIFT)
+#define TOOL_CAP_BUF_ADDR (ICP_CAP_BUF_ADDR + ICP_CAP_BUF_LEN)
+#define TOOL_CAP_BUF_LEN ((92 * 1024UL)>>CPU_SHIFT)
+#define ADB_CAP_BUF_ADDR (TOOL_CAP_BUF_ADDR + TOOL_CAP_BUF_LEN)
+#define ADB_CAP_BUF_LEN ((4 * 1024UL)>>CPU_SHIFT)
+#define RAMDUMP_CAP_CMM_BUF_ADDR (ADB_CAP_BUF_ADDR + ADB_CAP_BUF_LEN)
+#define RAMDUMP_CAP_CMM_BUF_LEN ((4 * 1024UL)>>CPU_SHIFT)
+
+#define RINGBUF_CAP_BASE_OFFSET ((1024 * 1024UL)>>CPU_SHIFT)
+#define RINGBUF_CAP_TO_AP_ADDR (RAMDUMP_CAP_CMM_BUF_ADDR + RAMDUMP_CAP_CMM_BUF_LEN)
+#define RINGBUF_CAP_TO_AP_LEN ((32 * 1024UL)>>CPU_SHIFT)
+#define RINGBUF_AP_TO_CAP_ADDR (RINGBUF_CAP_TO_AP_ADDR + RINGBUF_CAP_TO_AP_LEN)
+#define RINGBUF_AP_TO_CAP_LEN ((128 * 1024UL)>>CPU_SHIFT)
+
+#define ICP_CAP_BUF_ADDR_PA DDR_BASE_CAPBUF_ADDR_PA
+#define TOOL_CAP_BUF_ADDR_PA (ICP_CAP_BUF_ADDR_PA + ICP_CAP_BUF_LEN)
+#define ADB_CAP_BUF_ADDR_PA (TOOL_CAP_BUF_ADDR_PA + TOOL_CAP_BUF_LEN)
+#define RAMDUMP_CAP_CMM_BUF_ADDR_PA (ADB_CAP_BUF_ADDR_PA + ADB_CAP_BUF_LEN)
+#endif
+
+/* 7520V3оƬIRAM0ѹËõ£¬ÐÒéÕ»ÎïÀí²ã½»»¥¿Õ¼äÒƶ¯µ½DDR£¬¸´ÓÃRamdump¿Õ¼ä */
+/* 34K£¬PSÓëPHYÐÅÏ¢½»»¥£¬LTEÒµÎñ */
+/* #define IRAM_BASE_ADDR_LTE (DDR_BASE_ADDR_RAMDUMP) */
+/* 10K£¬PSÓëPHYÐÅÏ¢½»»¥£¬LTEÒµÎñ ʹÓÃIRAM0£¬¹¦ºÄÓÅ»¯ 7K+3K, 3k for embms*/
+#define IRAM_BASE_ADDR_LTE (IRAM_BASE_ADDR_SYS_TRACE + IRAM_BASE_LEN_SYS_TRACE)
+#define IRAM_BASE_LEN_LTE ((10 * 1024UL)>>CPU_SHIFT)
+
+/* 24K£¬PSÓëPHYµÄICP½»»¥£¬Ê¹ÓÃIRAM*/
+#define IRAM_BASE_ADDR_PS_PHY_SHAREBUF (IRAM_BASE_ADDR_LTE + IRAM_BASE_LEN_LTE)
+#define IRAM_BASE_LEN_PS_PHY_SHAREBUF ((24 * 1024UL)>>CPU_SHIFT)
+
+/* 221K£¬PSÓëPHYµÄICP½»»¥£¬Ê¹ÓÃDDR, ¸´ÓÃRAMDUMP*/
+#define DDR_BASE_ADDR_PS_PHY_SHAREBUF (DDR_BASE_ADDR_RAMDUMP)
+#define DDR_BASE_LEN_PS_PHY_SHAREBUF ((221 * 1024UL)>>CPU_SHIFT)
+
+/* 2k£¬zsp RAMDUMP*/
+#define DDR_BASE_ADDR_PHY_RAMDUMP (DDR_BASE_ADDR_PS_PHY_SHAREBUF + DDR_BASE_LEN_PS_PHY_SHAREBUF)
+#define DDR_BASE_LEN_PHY_RAMDUMP ((2 * 1024UL)>>CPU_SHIFT)
+
+/* 1K£¬PSÓëPHYÐÅÏ¢½»»¥£¬TDÒµÎñ ʹÓÃDDR*/
+#define IRAM_BASE_ADDR_TD (DDR_BASE_ADDR_PHY_RAMDUMP + DDR_BASE_LEN_PHY_RAMDUMP)
+/* #define IRAM_BASE_LEN_TD ((25 * 1024UL)>>CPU_SHIFT) */
+#define IRAM_BASE_LEN_TD ((1 * 1024UL)>>CPU_SHIFT)
+
+/* 12K£¬PSÓëPHYÐÅÏ¢½»»¥£¬WÒµÎñ ʹÓÃDDR*/
+#define IRAM_BASE_ADDR_WCDMA (IRAM_BASE_ADDR_TD + IRAM_BASE_LEN_TD)
+/* #define IRAM_BASE_LEN_WCDMA ((48 * 1024UL)>>CPU_SHIFT) */
+#define IRAM_BASE_LEN_WCDMA ((12 * 1024UL)>>CPU_SHIFT)
+
+/* 20K£¬W UPA ¿Õ¼ä */
+#define DDR_BASE_ADDR_WUPA_DATA (IRAM_BASE_ADDR_WCDMA + IRAM_BASE_LEN_WCDMA)
+#define DDR_BASE_LEN_WUPA_DATA ((20 * 1024UL)>>CPU_SHIFT)
+
+/* IRAM WCDMA»ùÖ· */
+#define IRAM_BASE_ADDR_FOR_W (IRAM_BASE_ADDR_WCDMA)
+
+/* DPRAM»ùÖ· */
+#define DPRAM_BASE_ADDR (IRAM_BASE_ADDR_TD)
+
+/* DPRAM DDR»ùÖ· */
+#define DPRAM_MEM_BASE_ADDR (IRAM_BASE_ADDR_TD)
+
+/* PS tcm config for ramdump */
+#define RAMDUMP_PS_ITCM_BASE_EXTER (0x0)
+#define RAMDUMP_PS_ITCM_BASE_INTER (0x0)
+#define RAMDUMP_PS_ITCM_SIZE (0x0)
+#define RAMDUMP_PS_DTCM_BASE_EXTER (0x0)
+#define RAMDUMP_PS_DTCM_BASE_INTER (0x0)
+#define RAMDUMP_PS_DTCM_SIZE (0x0)
+
+/* ZSP Ramdump */
+/* #ifdef _USE_ZSP_RAMDUMP */
+# define RAMDUMP_ZSP_ITCM_BASE (0x81040000UL)
+# define RAMDUMP_ZSP_ITCM_SIZE (0x00010000UL)
+# define RAMDUMP_ZSP_DTCM_BASE (0x81000000UL)
+# define RAMDUMP_ZSP_DTCM_SIZE (0x00010000UL)
+
+# define RAMDUMP_ZSP_CODE_SIZE (0x1b0000>>CPU_SHIFT)
+# define RAMDUMP_ZSP_IDDR_BASE (DDR_BASE_ADDR_PHY)
+# define RAMDUMP_ZSP_IDDR_SIZE (RAMDUMP_ZSP_CODE_SIZE)
+# define RAMDUMP_ZSP_DDDR_BASE (RAMDUMP_ZSP_IDDR_BASE + RAMDUMP_ZSP_CODE_SIZE)
+# define RAMDUMP_ZSP_DDDR_SIZE (DDR_BASE_LEN_PHY - RAMDUMP_ZSP_CODE_SIZE)
+
+# define RAMDUMP_ZSP_ITCM_SELF_BASE (0x0)
+# define RAMDUMP_ZSP_DTCM_SELF_BASE (0x10000UL)
+/* #endif */
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+
+#endif // #ifndef _RAM_BASE_CONFIG_7520V3
+
diff --git a/pub/project/zx297520v3/include/infra/ram_config_7520v3.h b/pub/project/zx297520v3/include/infra/ram_config_7520v3.h
new file mode 100644
index 0000000..5fa8eaf
--- /dev/null
+++ b/pub/project/zx297520v3/include/infra/ram_config_7520v3.h
@@ -0,0 +1,71 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: ram_config_7520v3.h
+* Îļþ±êʶ: ram_config_7520v3.h
+* ÄÚÈÝÕªÒª: zx297520v3оƬƽ̨´æ´¢µØÖ·ÅäÖÃÍ·Îļþ
+* ʹÓ÷½·¨: #include "ram_config.h"
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2015/06/08 V1.0 Create ÁõÑÇÄÏ ´´½¨
+*
+*******************************************************************************/
+
+#ifndef _RAM_CONFIG_7520V3
+#define _RAM_CONFIG_7520V3
+
+#ifndef _RAM_CONFIG_H
+#error "Don't include ram_config_7520v3.h directly, include ram_config.h instead!"
+#endif
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+#ifdef DDR_BASE_ADDR_LINUX_VA
+#include <asm/pgtable.h>
+#include <mach/iomap.h>
+#endif
+
+#include "ram_base_config_7520v3.h"
+
+
+#ifdef DDR_BASE_ADDR_LINUX_VA
+/*
+ * MODEM_PA_2_VA ºÍ MODEM_VA_2_PA½öÖ§³ÖDDRºÍIRAM0ÉϵÄÐéÄâµØÖ·/ÎïÀíµØÖ·¼äµÄת»»
+ */
+static inline unsigned long MODEM_PA_2_VA(unsigned long pa)
+{
+ if (pa >= (unsigned long)ZX29_IRAM0_PHYS && (pa <= ((unsigned long)ZX29_IRAM0_PHYS + ZX_IRAM0_SIZE)))
+ return pa - (unsigned long)ZX29_IRAM0_PHYS + (unsigned long)ZX_IRAM0_BASE;
+ else if (pa >= (unsigned long)ZX29_DDR_PHYCODE_PHYS && (pa <= ((unsigned long)ZX29_DDR_MODEM_PHYS + ZX_DDR_MODEM_SIZE)))
+ return pa - (unsigned long)ZX29_DDR_PHYCODE_PHYS + (unsigned long)ZX_DDR_PHYCODE_BASE;
+ else
+ return (unsigned long)(phys_to_virt(pa));
+}
+
+static inline unsigned long MODEM_VA_2_PA(unsigned long va)
+{
+ if (va >= (unsigned long)ZX_IRAM0_BASE && va <= ((unsigned long)ZX_IRAM0_BASE + ZX_IRAM0_SIZE))
+ return va - (unsigned long)ZX_IRAM0_BASE + (unsigned long)ZX29_IRAM0_PHYS;
+ else if (va >= (unsigned long)ZX_DDR_PHYCODE_BASE && va <= ((unsigned long)ZX_DDR_MODEM_BASE + ZX_DDR_MODEM_SIZE))
+ return va - (unsigned long)ZX_DDR_PHYCODE_BASE + (unsigned long)ZX29_DDR_PHYCODE_PHYS;
+ else
+ return (unsigned long)(virt_to_phys(va));
+}
+#endif
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+
+#endif // #ifndef _RAM_CONFIG_7520V3
+
diff --git a/pub/project/zx297520v3/include/nv/NvConfig.h b/pub/project/zx297520v3/include/nv/NvConfig.h
new file mode 100644
index 0000000..a70dbf5
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/NvConfig.h
@@ -0,0 +1,98 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+
+ * Others:
+ * Version:
+ * Author: zhangpei
+ * Date:
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ *
+ * History 2:
+********************************************************************************/
+
+#ifndef _NVCONFIG_H
+#define _NVCONFIG_H
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "RONvConfig.h"
+#include "RWNvConfig.h"
+#include "ram_config.h"
+
+/****************************************************************************
+* Local Macros
+****************************************************************************/
+// ZSP²àÎïÀí²ãNVµÄµØÖ·
+//NV-RO-AMT
+#define AMT_CALIB_LTE_NVRAM_BASE_ADDR (DDR_BASE_ADDR_PHY_NV)
+#define AMT_CALIB_LTE_NVRAM_LENTH OS_FLASH_AMT_LTE_RO_NONFAC_SIZE
+
+#define AMT_CALIB_TDS_NVRAM_BASE_ADDR (AMT_CALIB_LTE_NVRAM_BASE_ADDR+AMT_CALIB_LTE_NVRAM_LENTH)
+#define AMT_CALIB_TDS_NVRAM_LENTH OS_FLASH_AMT_TDS_RO_NONFAC_SIZE
+
+#define AMT_CALIB_GGE_NVRAM_BASE_ADDR (AMT_CALIB_TDS_NVRAM_BASE_ADDR+AMT_CALIB_TDS_NVRAM_LENTH)
+#define AMT_CALIB_GGE_NVRAM_LENTH OS_FLASH_AMT_GGE_RO_NONFAC_SIZE
+
+#define AMT_CALIB_WCDMA_NVRAM_BASE_ADDR (AMT_CALIB_GGE_NVRAM_BASE_ADDR+AMT_CALIB_GGE_NVRAM_LENTH)
+#define AMT_CALIB_WCDMA_NVRAM_LENTH OS_FLASH_AMT_WCDMA_RO_NONFAC_SIZE
+
+#define AMT_CALIB_LTEA_NVRAM_BASE_ADDR (AMT_CALIB_WCDMA_NVRAM_BASE_ADDR+AMT_CALIB_WCDMA_NVRAM_LENTH)
+#define AMT_CALIB_LTEA_NVRAM_LENTH OS_FLASH_AMT_LTEA_RO_NONFAC_SIZE
+
+//NV-RW-AMT-USER
+#define AMT_USER_LTE_NVRAM_BASE_ADDR (AMT_CALIB_LTEA_NVRAM_BASE_ADDR+AMT_CALIB_LTEA_NVRAM_LENTH)
+#define AMT_USER_LTE_NVRAM_LENTH OS_FLASH_AMT_RW_USER_LTE_SIZE
+
+#define AMT_USER_TDS_NVRAM_BASE_ADDR (AMT_USER_LTE_NVRAM_BASE_ADDR+AMT_USER_LTE_NVRAM_LENTH)
+#define AMT_USER_TDS_NVRAM_LENTH OS_FLASH_AMT_RW_USER_TDS_SIZE
+
+#define AMT_USER_GGE_NVRAM_BASE_ADDR (AMT_USER_TDS_NVRAM_BASE_ADDR+AMT_USER_TDS_NVRAM_LENTH)
+#define AMT_USER_GGE_NVRAM_LENTH OS_FLASH_AMT_RW_USER_GGE_SIZE
+
+#define AMT_USER_WCDMA_NVRAM_BASE_ADDR (AMT_USER_GGE_NVRAM_BASE_ADDR+AMT_USER_GGE_NVRAM_LENTH)
+#define AMT_USER_WCDMA_NVRAM_LENTH OS_FLASH_AMT_RW_USER_WCDMA_SIZE
+
+#define AMT_USER_LTEA_NVRAM_BASE_ADDR (AMT_USER_WCDMA_NVRAM_BASE_ADDR+AMT_USER_WCDMA_NVRAM_LENTH)
+#define AMT_USER_LTEA_NVRAM_LENTH OS_FLASH_AMT_RW_USER_LTEA_SIZE
+
+//NV-RW-PHY
+#define LTEA_PHY_NVRAM_BASE_ADDR (AMT_USER_LTEA_NVRAM_BASE_ADDR+AMT_USER_LTEA_NVRAM_LENTH)
+#define LTEA_PHY_NVRAM_LENTH OS_FLASH_LTEAPHY_RW_NONFAC_SIZE
+
+#define TDS_PHY_NVRAM_BASE_ADDR (LTEA_PHY_NVRAM_BASE_ADDR+LTEA_PHY_NVRAM_LENTH)
+#define TDS_PHY_NVRAM_LENTH OS_FLASH_TDPHY_RW_NONFAC_SIZE
+
+#define GSM_PHY_NVRAM_BASE_ADDR (TDS_PHY_NVRAM_BASE_ADDR+TDS_PHY_NVRAM_LENTH)
+#define GSM_PHY_NVRAM_LENTH OS_FLASH_GSML1G_RW_NONFAC_SIZE
+
+#define WCDMA_PHY_NVRAM_BASE_ADDR (GSM_PHY_NVRAM_BASE_ADDR+GSM_PHY_NVRAM_LENTH)
+#define WCDMA_PHY_NVRAM_LENTH OS_FLASH_WCDMAPHY_RW_NONFAC_SIZE
+
+#define PHY_CFG_NVRAM_BASE_ADDR (WCDMA_PHY_NVRAM_BASE_ADDR+WCDMA_PHY_NVRAM_LENTH)
+#define PHY_CFG_NVRAM_LENTH OS_FLASH_PHYCFG_RW_NONFAC_SIZE
+
+#define PHY_TXETAB_NVRAM_BASE_ADDR (PHY_CFG_NVRAM_BASE_ADDR+PHY_CFG_NVRAM_LENTH)
+#define PHY_TXETAB_NVRAM_LENTH OS_FLASH_TXETAB_RW_NONFAC_SIZE
+
+#define PHY_NV_CFG_END 0xFFFFFFFF
+
+typedef struct _T_zPhyNVCfg
+{
+ UINT32 uNVFlashBaseAddr; /*NV src addr(nand flash)*/
+ UINT32 uNVRamBaseAddr; /*NV dst addr(DDRAM)*/
+ UINT32 uNVSize; /*NV SIZE*/
+}
+T_zPhyNVCfg;
+
+extern T_zPhyNVCfg g_PhyNVCfg[];
+
+#endif /*_NVCONFIG_H*/
diff --git a/pub/project/zx297520v3/include/nv/NvConfig_Table.h b/pub/project/zx297520v3/include/nv/NvConfig_Table.h
new file mode 100644
index 0000000..c3077c4
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/NvConfig_Table.h
@@ -0,0 +1,59 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:
+ * File Mark:
+ * Description:
+
+ * Others:
+ * Version:
+ * Author: zhangpei
+ * Date:
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ *
+ * History 2:
+********************************************************************************/
+
+#ifndef _NVCONFIG_TABLE_H
+#define _NVCONFIG_TABLE_H
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+#include "NvConfig.h"
+
+/****************************************************************************
+* Local Macros
+****************************************************************************/
+T_zPhyNVCfg g_PhyNVCfg[] =
+{
+ /*flash base addr */ /*DDR base addr */ /*nv size*/
+ {OS_FLASH_AMT_LTE_RO_NONFAC_BASE_ADDR, AMT_CALIB_LTE_NVRAM_BASE_ADDR, AMT_CALIB_LTE_NVRAM_LENTH},
+ {OS_FLASH_AMT_TDS_RO_NONFAC_BASE_ADDR, AMT_CALIB_TDS_NVRAM_BASE_ADDR, AMT_CALIB_TDS_NVRAM_LENTH},
+ {OS_FLASH_AMT_GGE_RO_NONFAC_BASE_ADDR, AMT_CALIB_GGE_NVRAM_BASE_ADDR, AMT_CALIB_GGE_NVRAM_LENTH},
+ {OS_FLASH_AMT_WCDMA_RO_NONFAC_BASE_ADDR, AMT_CALIB_WCDMA_NVRAM_BASE_ADDR, AMT_CALIB_WCDMA_NVRAM_LENTH},
+// {OS_FLASH_AMT_LTEA_RO_NONFAC_BASE_ADDR, AMT_CALIB_LTEA_NVRAM_BASE_ADDR, AMT_CALIB_LTEA_NVRAM_LENTH},
+
+// {OS_FLASH_AMT_RW_USER_LTE_BASE_ADDR, AMT_USER_LTE_NVRAM_BASE_ADDR, AMT_USER_LTE_NVRAM_LENTH},
+ {OS_FLASH_AMT_RW_USER_TDS_BASE_ADDR, AMT_USER_TDS_NVRAM_BASE_ADDR, AMT_USER_TDS_NVRAM_LENTH},
+ {OS_FLASH_AMT_RW_USER_GGE_BASE_ADDR, AMT_USER_GGE_NVRAM_BASE_ADDR, AMT_USER_GGE_NVRAM_LENTH},
+ {OS_FLASH_AMT_RW_USER_WCDMA_BASE_ADDR, AMT_USER_WCDMA_NVRAM_BASE_ADDR, AMT_USER_WCDMA_NVRAM_LENTH},
+ {OS_FLASH_AMT_RW_USER_LTEA_BASE_ADDR, AMT_USER_LTEA_NVRAM_BASE_ADDR, AMT_USER_LTEA_NVRAM_LENTH},
+
+ {OS_FLASH_LTEAPHY_RW_NONFAC_BASE_ADDR, LTEA_PHY_NVRAM_BASE_ADDR, LTEA_PHY_NVRAM_LENTH},
+ {OS_FLASH_TDPHY_RW_NONFAC_BASE_ADDR, TDS_PHY_NVRAM_BASE_ADDR, TDS_PHY_NVRAM_LENTH},
+ {OS_FLASH_GSML1G_RW_NONFAC_BASE_ADDR, GSM_PHY_NVRAM_BASE_ADDR, GSM_PHY_NVRAM_LENTH},
+ {OS_FLASH_WCDMAPHY_RW_NONFAC_BASE_ADDR, WCDMA_PHY_NVRAM_BASE_ADDR, WCDMA_PHY_NVRAM_LENTH},
+
+ {OS_FLASH_PHYCFG_RW_NONFAC_BASE_ADDR, PHY_CFG_NVRAM_BASE_ADDR, PHY_CFG_NVRAM_LENTH},
+
+ {OS_FLASH_TXETAB_RW_NONFAC_BASE_ADDR, PHY_TXETAB_NVRAM_BASE_ADDR, PHY_TXETAB_NVRAM_LENTH},
+
+ {PHY_NV_CFG_END, PHY_NV_CFG_END, PHY_NV_CFG_END},
+};
+
+#endif /*_NVCONFIG_TABLE_H*/
diff --git a/pub/project/zx297520v3/include/nv/PriNvConfig.h b/pub/project/zx297520v3/include/nv/PriNvConfig.h
new file mode 100644
index 0000000..8cdc26e
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/PriNvConfig.h
@@ -0,0 +1,199 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: RWNvConfig.h
+ * File Mark:
+ * Description: descrip the nv config area,the start address of module
+
+ * Others:
+ * Version: v0.5
+ * Author: xuxingkui
+ * Date: 2009-09-30
+ * History 1:
+ * Date: 2009-11-24
+ * Version:
+ * Author:
+ * Modification:
+ * History 2:
+********************************************************************************/
+#ifndef _PRINVCONFIG_H
+#define _PRINVCONFIG_H
+
+#include "RWNvConfig.h"
+#if 0
+/****************************************************************************
+ Begin
+****************************************************************************/
+
+/****************************************************************************
+ Leave Factory Parmeters Area
+****************************************************************************/
+//#define OS_FLASH_PUB_OFFSET_FROM_NV (OS_FIRST_NV_ADDRESS_CONFIG + 262144 /* 256K ¼´¹«ÓÐÇøµÄ´óС */ )
+#define OS_FLASH_RW_OFFSET_FROM_NV (0x40000) /* ¶ÁдÇøÆ«ÒÆ */
+
+#if 0
+/***************************
+AMT area config
+***************************/
+#define OS_FLASH_AMT_RW_FAC_OFFSET_FROM_NV (OS_FLASH_RW_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_RW_FAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_AMT_RW_FAC_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_RW_FAC_SIZE 0
+
+/***************************
+ATI area config
+***************************/
+#define OS_FLASH_ATI_RW_FAC_OFFSET_FROM_NV (OS_FLASH_AMT_RW_FAC_OFFSET_FROM_NV + OS_FLASH_AMT_RW_FAC_SIZE)
+#define OS_FLASH_ATI_RW_FAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_ATI_RW_FAC_OFFSET_FROM_NV)
+#define OS_FLASH_ATI_RW_FAC_SIZE 0
+
+/***************************
+driver area config
+***************************/
+#define OS_FLASH_DRV_RW_FAC_OFFSET_FROM_NV (OS_FLASH_ATI_RW_FAC_OFFSET_FROM_NV + OS_FLASH_ATI_RW_FAC_SIZE)
+#define OS_FLASH_DRV_RW_FAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_DRV_RW_FAC_OFFSET_FROM_NV)
+#define OS_FLASH_DRV_RW_FAC_SIZE 0
+
+/***************************
+td physical area config
+***************************/
+#define OS_FLASH_TDPHY_RW_FAC_OFFSET_FROM_NV (OS_FLASH_DRV_RW_FAC_OFFSET_FROM_NV + OS_FLASH_DRV_RW_FAC_SIZE)
+#define OS_FLASH_TDPHY_RW_FAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_TDPHY_RW_FAC_OFFSET_FROM_NV)
+#define OS_FLASH_TDPHY_RW_FAC_SIZE 0
+
+/***************************
+GSM l1g area config
+***************************/
+#define OS_FLASH_GSML1G_RW_FAC_OFFSET_FROM_NV (OS_FLASH_TDPHY_RW_FAC_OFFSET_FROM_NV + OS_FLASH_TDPHY_RW_FAC_SIZE)
+#define OS_FLASH_GSML1G_RW_FAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_GSML1G_RW_FAC_OFFSET_FROM_NV)
+#define OS_FLASH_GSML1G_RW_FAC_SIZE 0
+
+/***************************
+ps area config
+***************************/
+#define OS_FLASH_PS_RW_FAC_OFFSET_FROM_NV (OS_FLASH_GSML1G_RW_FAC_OFFSET_FROM_NV + OS_FLASH_GSML1G_RW_FAC_SIZE)
+#define OS_FLASH_PS_RW_FAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_PS_RW_FAC_OFFSET_FROM_NV)
+#define OS_FLASH_PS_RW_FAC_SIZE 0
+
+/***************************
+plat area config
+***************************/
+#define OS_FLASH_PLAT_RW_FAC_OFFSET_FROM_NV (OS_FLASH_PS_RW_FAC_OFFSET_FROM_NV + OS_FLASH_PS_RW_FAC_SIZE)
+#define OS_FLASH_PLAT_RW_FAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_PLAT_RW_FAC_OFFSET_FROM_NV)
+#define OS_FLASH_PLAT_RW_FAC_SIZE 0
+
+/***************************
+user area config
+***************************/
+#define OS_FLASH_USER_RW_FAC_OFFSET_FROM_NV (OS_FLASH_PLAT_RW_FAC_OFFSET_FROM_NV + OS_FLASH_PLAT_RW_FAC_SIZE)
+#define OS_FLASH_USER_RW_FAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_USER_RW_FAC_OFFSET_FROM_NV)
+#define OS_FLASH_USER_RW_FAC_SIZE 0
+#endif
+
+/****************************************************************************
+ None Leave Factory Parmeters Area
+****************************************************************************/
+/***************************
+AMT area config 32KB
+***************************/
+#define OS_FLASH_AMT_RW_NONFAC_OFFSET_FROM_NV OS_FLASH_RW_OFFSET_FROM_NV
+#define OS_FLASH_AMT_RW_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_AMT_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_RW_NONFAC_SIZE 32768
+
+/***************************
+AMT user config 32KB
+***************************/
+#define OS_FLASH_AMT_RW_USER_OFFSET_FROM_NV (OS_FLASH_AMT_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_AMT_RW_NONFAC_SIZE)
+#define OS_FLASH_AMT_RW_USER_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_AMT_RW_USER_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_RW_USER_SIZE 32768
+
+
+/***************************
+ATI area config 64KB
+***************************/
+#define OS_FLASH_ATI_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_AMT_RW_USER_OFFSET_FROM_NV + OS_FLASH_AMT_RW_USER_SIZE)
+#define OS_FLASH_ATI_RW_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_ATI_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_ATI_RW_NONFAC_SIZE 65536 /* 64K */
+
+/***************************
+LTE physical area config 128KB
+***************************/
+#define OS_FLASH_LTEPHY_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_ATI_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_ATI_RW_NONFAC_SIZE)
+#define OS_FLASH_LTEPHY_RW_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_LTEPHY_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_LTEPHY_RW_NONFAC_SIZE 131072 /* 128K */
+
+/***************************
+GSM l1g area config 64KB
+***************************/
+#define OS_FLASH_GSML1G_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_LTEPHY_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_LTEPHY_RW_NONFAC_SIZE)
+#define OS_FLASH_GSML1G_RW_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_GSML1G_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_GSML1G_RW_NONFAC_SIZE 65536
+
+/***************************
+TSP area config 32KB
+***************************/
+#define OS_FLASH_TSP_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_GSML1G_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_GSML1G_RW_NONFAC_SIZE)
+#define OS_FLASH_TSP_RW_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_TSP_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_TSP_RW_NONFAC_SIZE 32768
+
+/***************************
+TDS physical area config 32KB
+***************************/
+#define OS_FLASH_TDPHY_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_TSP_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_TSP_RW_NONFAC_SIZE)
+#define OS_FLASH_TDPHY_RW_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_TDPHY_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_TDPHY_RW_NONFAC_SIZE 32768
+
+/***************************
+at config setting 1KB
+***************************/
+#define OS_FLASH_ATCFG_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_TDPHY_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_TDPHY_RW_NONFAC_SIZE)
+#define OS_FLASH_ATCFG_RW_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_ATCFG_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_ATCFG_RW_NONFAC_SIZE 1024
+
+/***************************
+ ps area config 64KB
+***************************/
+#define OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_ATCFG_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_ATCFG_RW_NONFAC_SIZE)
+#define OS_FLASH_PS_RW_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_PS_RW_NONFAC_SIZE 65536
+
+/***************************
+driver area config 16KB
+***************************/
+#define OS_FLASH_DRV_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_PS_RW_NONFAC_SIZE)
+#define OS_FLASH_DRV_RW_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_DRV_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_DRV_RW_NONFAC_SIZE 16384
+
+/***************************
+plat area config 1KB
+***************************/
+#define OS_FLASH_PLAT_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_DRV_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_DRV_RW_NONFAC_SIZE)
+#define OS_FLASH_PLAT_RW_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_PLAT_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_PLAT_RW_NONFAC_SIZE 1024
+
+/***************************
+user area config 0KB
+***************************/
+#define OS_FLASH_USER_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_PLAT_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_PLAT_RW_NONFAC_SIZE)
+#define OS_FLASH_USER_RW_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_USER_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_USER_RW_NONFAC_SIZE 0
+
+/******************************
+reserved RWdate area config 302KB
+******************************/
+#define OS_FLASH_RW_RESERVED_OFFSET_FROM_NV (OS_FLASH_USER_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_USER_RW_NONFAC_SIZE)
+#define OS_FLASH_RW_RESERVED_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_RW_RESERVED_OFFSET_FROM_NV)
+#define OS_FLASH_RW_RESERVED_SIZE 309248
+
+/***************************
+SM MEMORY bakeup RWvate area config
+***************************/
+#define OS_FLASH_RW_SM_BAKEUP_OFFSET_FROM_NV 3145728 /* 3M */
+#define OS_FLASH_RW_SM_BAKEUP_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_RW_SM_BAKEUP_OFFSET_FROM_NV)
+#define OS_FLASH_RW_SM_BAKEUP_SIZE 1355776 /* 1M + 300K */
+
+#endif
+/****************************************************************************
+ End
+****************************************************************************/
+
+#endif
diff --git a/pub/project/zx297520v3/include/nv/PriNvParam.h b/pub/project/zx297520v3/include/nv/PriNvParam.h
new file mode 100644
index 0000000..39ddd88
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/PriNvParam.h
@@ -0,0 +1,223 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:prinvparam.h
+ * File Mark:
+ * Description:private config NV parameters
+
+ * Others:
+ * Version: v0.1
+ * Author: xuxingkui
+ * Date: 2009-09-28
+ * History 1:
+ * Date: 2009-11-24
+ * Version:
+ * Author:
+ * Modification:
+ *
+ * History 2:
+********************************************************************************/
+
+#ifndef PRINVPARM_H
+#define PRINVPARM_H
+
+
+#include "RWNvParam.h"
+
+#if 0
+#include "NvParam_drv.h"
+#include "NvParam_ati.h"
+#include "NvParam_AMT.h"
+#include "NvParam_tdl1.h"
+#include "NvParam_gsml1.h"
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+/****************************************************************************
+* Local Macros
+****************************************************************************/
+
+/****************************************************************************
+* AMT
+****************************************************************************/
+/***********************************
+AMT leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_AMTParam
+{
+
+}T_ZFacPri_AMTParam;
+
+/***********************************
+AMT none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_AMTParam
+{
+ stTD st_td;
+}T_ZNonFacPri_AMTParam;
+
+/****************************************************************************
+* ATI
+****************************************************************************/
+/***********************************
+ATI leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_ATIParam
+{
+
+}T_ZFacPri_ATIParam;
+
+/***********************************
+ATI none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_ATIParam
+{
+ T_ZAt2_NvParam at2_nvParam;
+}T_ZNonFacPri_ATIParam;
+
+/****************************************************************************
+* DIVER
+****************************************************************************/
+/***********************************
+driver leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_DrvParam
+{
+
+}T_ZFacPri_DrvParam;
+
+/***********************************
+driver none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_DrvParam
+{
+ aud_eep_static_type g_aud_eep_static_type;
+}T_ZNonFacPri_DrvParam;
+
+/****************************************************************************
+* TdPhy
+****************************************************************************/
+/***********************************
+td physical leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_TdPhyParam
+{
+
+}T_ZFacPri_TdPhyParam;
+
+/***********************************
+td physical none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_TdPhyParam
+{
+ T_TD_L1_NV td_l1_nv;
+}T_ZNonFacPri_TdPhyParam;
+
+/****************************************************************************
+* GSM L1g
+****************************************************************************/
+/***********************************
+GSM L1g leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_GsmL1gParam
+{
+
+}T_ZFacPri_GsmL1gParam;
+
+/***********************************
+GSM L1g none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_GsmL1gParam
+{
+ L1G_EEP_static_type l1g_eep_static_type;
+}T_ZNonFacPri_GsmL1gParam;
+
+/****************************************************************************
+* PS
+****************************************************************************/
+/***********************************
+ps leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_PsParam
+{
+
+}T_ZFacPri_PsParam;
+
+/***********************************
+ps none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_PsParam
+{
+ T_zPS_DEV_NV_PsData psData;
+}T_ZNonFacPri_PsParam;
+
+/****************************************************************************
+* PLAT
+****************************************************************************/
+/***********************************
+plat leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_PlatParam
+{
+
+}T_ZFacPri_PlatParam;
+
+/***********************************
+plat none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_PlatParam
+{
+
+}T_ZNonFacPri_PlatParam;
+
+/****************************************************************************
+* USER
+****************************************************************************/
+/***********************************
+USER leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_UserParam
+{
+
+}T_ZFacPri_UserParam;
+
+/***********************************
+USER none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_UserParam
+{
+
+}T_ZNonFacPri_UserParam;
+
+/****************************************************************************
+* TSP
+****************************************************************************/
+typedef struct _tagZPri_TspParam
+{
+ /* leave factory parmameters */
+ T_ZFacPri_AMTParam gFacPriAMTParam; /* AMT */
+ T_ZFacPri_ATIParam gFacPriATIParam; /* ATI */
+ T_ZFacPri_DrvParam gFacPriDrvParam; /* DRIVER */
+ T_ZFacPri_TdPhyParam gFacPriTdPhyParam; /* TD PHY */
+ T_ZFacPri_GsmL1gParam gFacPriGsmL1gParam; /* GSM L1G */
+ T_ZFacPri_PsParam gFacPriPsParam; /* PS */
+ T_ZFacPri_PlatParam gFacPriPlatParam; /* PLAT */
+ T_ZFacPri_UserParam gFacPriUserParam; /* USER */
+
+ /* none leave factory parmameters */
+ T_ZNonFacPri_AMTParam gNonFacPriAMTParam; /* AMT */
+ T_ZNonFacPri_ATIParam gNonFacPriATIParam; /* ATI */
+ T_ZNonFacPri_DrvParam gNonFacPriDrvParam; /* DRIVER */
+ T_ZNonFacPri_TdPhyParam gNonFacPriTdPhyParam; /* TD PHY */
+ T_ZNonFacPri_GsmL1gParam gNonFacPriGsmL1gParam; /* GSM L1G */
+ T_ZNonFacPri_PsParam gNonFacPriPsParam; /* PS */
+ T_ZNonFacPri_PlatParam gNonFacPriPlatParam; /* PLAT */
+ T_ZNonFacPri_UserParam gNonFacPriUserParam; /* USER */
+}T_ZPri_TspParam;
+
+#endif
+#endif
+
+
diff --git a/pub/project/zx297520v3/include/nv/PubNvConfig.h b/pub/project/zx297520v3/include/nv/PubNvConfig.h
new file mode 100644
index 0000000..b50af05
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/PubNvConfig.h
@@ -0,0 +1,88 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: RONvConfig.h
+ * File Mark:
+ * Description: descrip the nv config area,the start address of module
+ the size is 256k,please use the space between OS_FIRST_NV_ADDRESS_CONFIG and (OS_FIRST_NV_ADDRESS_CONFIG + 256k)
+ * Others:
+ * Version: v0.5
+ * Author: xuxingkui
+ * Date: 2009-09-30
+ * History 1:
+ * Date: 2009-11-24
+ * Version: V1.0
+ * Author: xuxingkui
+ * Modification: modify the driver config space
+ * History 2:
+********************************************************************************/
+#ifndef _PUBNVCONFIG_H
+#define _PUBNVCONFIG_H
+
+//#include "nandflash.h"
+#include "RONvConfig.h"
+
+#if 0
+/****************************************************************************
+ Begin
+****************************************************************************/
+
+/************************************
+amt area config---part I calibration info-16KB
+*************************************/
+#define OS_FLASH_AMT_CALIB_RO_OFFSET_FROM_NV 0
+#define OS_FLASH_AMT_CALIB_RO_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_AMT_CALIB_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_CALIB_RO_NONFAC_SIZE 16384 /* 16K */
+
+/************************************
+amt area config---part II TDD_LTE&FDD_LTE info-96KB
+*************************************/
+#define OS_FLASH_AMT_LTE_RO_OFFSET_FROM_NV (OS_FLASH_AMT_CALIB_RO_OFFSET_FROM_NV + OS_FLASH_AMT_CALIB_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_LTE_RO_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_AMT_LTE_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_LTE_RO_NONFAC_SIZE 98304 /* 96K */
+
+/************************************
+amt area config---part IV TD_S info-32KB
+*************************************/
+#define OS_FLASH_AMT_TDS_RO_OFFSET_FROM_NV (OS_FLASH_AMT_LTE_RO_OFFSET_FROM_NV + OS_FLASH_AMT_LTE_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_TDS_RO_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_AMT_TDS_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_TDS_RO_NONFAC_SIZE 32768 /* 32K */
+
+/************************************
+amt area config---part V GGE info-16KB
+*************************************/
+#define OS_FLASH_AMT_GGE_RO_OFFSET_FROM_NV (OS_FLASH_AMT_TDS_RO_OFFSET_FROM_NV + OS_FLASH_AMT_TDS_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_GGE_RO_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_AMT_GGE_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_GGE_RO_NONFAC_SIZE 16384/* 16K */
+
+/************************************
+amt area config---part VI WiFi info-32KB
+*************************************/
+#define OS_FLASH_AMT_WIFI_RO_OFFSET_FROM_NV (OS_FLASH_AMT_GGE_RO_OFFSET_FROM_NV + OS_FLASH_AMT_GGE_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_WIFI_RO_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_AMT_WIFI_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_WIFI_RO_NONFAC_SIZE 32768/* 32K */
+
+/************************************
+amt area config---part VII WCDMA info-32KB
+*************************************/
+#define OS_FLASH_AMT_WCDMA_RO_OFFSET_FROM_NV (OS_FLASH_AMT_WIFI_RO_OFFSET_FROM_NV + OS_FLASH_AMT_WIFI_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_WCDMA_RO_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_AMT_WCDMA_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_WCDMA_RO_NONFAC_SIZE 32768/* 32K */
+
+/****************************************************************************
+ reserved config
+****************************************************************************/
+
+/************************************
+amt area config---Reserved -32KB
+*************************************/
+#define OS_FLASH_AMT_RESERVED_RO_OFFSET_FROM_NV (OS_FLASH_AMT_WCDMA_RO_OFFSET_FROM_NV + OS_FLASH_AMT_WCDMA_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_RESERVED_RO_NONFAC_BASE_ADDR (OS_FLASH_ABSOLUTE_WORKAREA_NVRAM_BASE_ADDR + OS_FLASH_AMT_RESERVED_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_RESERVED_RO_NONFAC_SIZE 32768/* 32K */
+
+/****************************************************************************
+ End
+****************************************************************************/
+#endif
+#endif
+
diff --git a/pub/project/zx297520v3/include/nv/PubNvParam.h b/pub/project/zx297520v3/include/nv/PubNvParam.h
new file mode 100644
index 0000000..06903f8
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/PubNvParam.h
@@ -0,0 +1,141 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:pubnvparm.h
+ * File Mark:
+ * Description:public config NV parameters
+
+ * Others:
+ * Version: v0.5
+ * Author: xuxingkui
+ * Date: 2009-09-28
+ * History 1:
+ * Date: 2009-11-24
+ * Version: v1.0
+ * Author: xuxingkui
+ * Modification: add a line at the end of this file
+ *
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _PUBNVPARM_H
+#define _PUBNVPARM_H
+
+#include "RONvParam.h"
+#if 0
+#include "NandFlash.h"
+#include "PubNvParam_PS.h"
+#include "PubNvParam_AMT.h"
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+/****************************************************************************
+* Local Macros
+****************************************************************************/
+
+/****************************************************************************
+* DIVER
+****************************************************************************/
+/***********************************
+driver leave factory parmameters
+************************************/
+typedef struct _tagZFacPub_DrvParam
+{
+
+}T_ZFacPub_DrvParam;
+
+/***********************************
+driver none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPub_DrvParam
+{
+
+}T_ZNonFacPub_DrvParam;
+
+/****************************************************************************
+* PS
+****************************************************************************/
+/***********************************
+PS leave factory parmameters
+************************************/
+typedef struct _tagZFacPub_PsParam
+{
+
+}T_ZFacPub_PsParam;
+
+/***********************************
+PS none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPub_PsParam
+{
+ T_zPS_DEV_NV_Imei psDevNv;
+}T_ZNonFacPub_PsParam;
+
+/****************************************************************************
+* AMT
+****************************************************************************/
+/***********************************
+AMT leave factory parmameters
+************************************/
+typedef struct _tagZFacPub_AMTParam
+{
+
+}T_ZFacPub_AMTParam;
+
+/***********************************
+AMT none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPub_AMTParam
+{
+ T_zPS_AMT_NV AMTDevNv;
+}T_ZNonFacPub_AMTParam;
+
+/****************************************************************************
+* USER
+****************************************************************************/
+/***********************************
+User factory public parmameters
+************************************/
+typedef struct _tagZFacPub_UserParam
+{
+
+}T_ZFacPub_UserParam;
+
+/***********************************
+User nonfactory public parmameters
+************************************/
+typedef struct _tagNonFacPub_UserParam
+{
+
+}T_ZNonFacPub_UserParam;
+
+/****************************************************************************
+* Public TSP
+****************************************************************************/
+/***********************************
+Tsp leave factory parmameters
+************************************/
+typedef struct _tagZPub_TspParam
+{
+ /* leave factory parmameters */
+ T_ZFacPub_DrvParam gFacPubDrvParam; /* driver */
+ T_ZFacPub_PsParam gFacPubPsParam; /* ps */
+ T_ZFacPub_AMTParam gFacPubAMTParam; /* AMT */
+ T_ZFacPub_UserParam gFacPubUserParam; /* user */
+
+ /* none leave factory parmameters */
+ T_ZNonFacPub_DrvParam gNonFacPubDrvParam; /* driver */
+ T_ZNonFacPub_PsParam gNoneFacPubPsParam; /* ps */
+ T_ZNonFacPub_AMTParam gNoneFacPubAMTParam;/* amt */
+ T_ZNonFacPub_UserParam gNonFacPubUserParam; /* user */
+
+}T_ZPub_TspParam;
+
+#endif
+
+#endif
+
+
+
diff --git a/pub/project/zx297520v3/include/nv/PubNvParam_AMT.h b/pub/project/zx297520v3/include/nv/PubNvParam_AMT.h
new file mode 100644
index 0000000..c128159
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/PubNvParam_AMT.h
@@ -0,0 +1,211 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:PubNvParam_AMT.h
+ * File Mark:
+ * Description:public config NV parameters
+
+ * Others:
+ * Version: v0.1
+ * Author: lankai
+ * Date: 2010-01-25
+ * History 1:
+ * Date:
+ * Version:
+ * Author:
+ * Modification:
+ *
+ * History 2:
+ ********************************************************************************/
+#ifndef PUBNVPARAM_AMT_H
+#define PUBNVPARAM_AMT_H
+
+#include "RONvParam_AMT.h"
+
+#if 0
+#define ZPS_ImeiLen (BYTE)8 /*IMEI×î´ó³¤¶È*/
+#define ZPS_ImeiSvLen (BYTE)8 /*IMEISV×î´ó³¤¶È*/
+#define ZPS_DEV_MSINFO_MAX_BORDNAME_LEN (BYTE)6
+#define ZPS_DEV_MSINFO_MAX_SOFTVERSION_LEN (BYTE)10
+#define ZPS_AMT_TESTINFO_LEN (BYTE)40
+#define ZPS_DEV_MSINFO_MAX_SOFTVERSION_INT_LEN (BYTE)100
+#define ZPS_DEV_MSINFO_MAX_SOFTVERSION_EXT_LEN (BYTE)100
+#define ZPS_DEV_MSINFO_MAX_PHONE_INT_LEN (BYTE)100
+#define ZPS_DEV_MSINFO_MAX_PHONE_EXT_LEN (BYTE)100
+#define ZPS_DEV_MSINFO_MAX_BOARD_INT_LEN (BYTE)100
+#define ZPS_DEV_MSINFO_MAX_BOARD_EXT_LEN (BYTE)100
+typedef struct
+{
+ BYTE abImei[ZPS_ImeiLen]; /********************************************************************************
+ ¹¦ÄÜ£º Ó²¼þÉ豸ºÅ
+ È¡Öµ·¶Î§£ºIMEIÖÐÿһ¸öBCDÂ뷶ΧΪ0-9
+ ³ö³§Öµ£ºÓɳö²ú³§É̾ö¶¨
+ *********************************************************************************/
+
+ BYTE abImeiSv[ZPS_ImeiSvLen]; /********************************************************************************
+ ¹¦ÄÜ£º Èí¼þ°æ±¾ºÅ
+ È¡Öµ·¶Î§£ºIMEISVÖÐÿһ¸öBCDÂ뷶ΧΪ0-9
+ ³ö³§Öµ£ºÓɳö²ú³§É̾ö¶¨
+ *********************************************************************************/
+
+ BYTE abBordNum[ZPS_DEV_MSINFO_MAX_BORDNAME_LEN];
+ /********************************************************************************
+ ¹¦ÄÜ£º Ö÷°åºÅ£¬ÓÉBCDÂë×é³É
+ È¡Öµ·¶Î§£ºÖ÷°åºÅÖÐÿһ¸öBCDÂ뷶ΧΪ0-9
+ ³ö³§Öµ£ºÓɳö²ú³§É̾ö¶¨
+ *********************************************************************************/
+
+ BYTE abSoftVersion[ZPS_DEV_MSINFO_MAX_SOFTVERSION_LEN];
+ /********************************************************************************
+ ¹¦ÄÜ£º Èí¼þ°æ±¾ºÅ
+ È¡Öµ·¶Î§£ºÈÎÒâ×Ö·û´®,ÒÔ'\0'±íʾ½áÊø
+ ³ö³§Öµ£ºÓɳö²ú³§É̾ö¶¨
+ *********************************************************************************/
+
+ BYTE abTestInfo[ZPS_AMT_TESTINFO_LEN];
+ /********************************************************************************
+ ¹¦ÄÜ£º AMTÉú²ú²âÊÔ±êʶλÊý×é
+ È¡Öµ·¶Î§£º0x30»òÕß0x31£¬Ä¬ÈÏΪ0x30
+ ³ö³§Öµ£º0x30
+ *********************************************************************************/
+
+ BYTE abSoftVersionInt[ZPS_DEV_MSINFO_MAX_SOFTVERSION_INT_LEN];
+ /********************************************************************************
+ ¹¦ÄÜ£º ÄÚ²¿Èí¼þ°æ±¾ºÅ
+ È¡Öµ·¶Î§£º¿É¼ûASCIIÂë×Ö·û£¬ÒÔ×Ö·û'\0'½áÊø£¬Ê£Óà×Ö½ÚÌî³ä0x00
+ ³ö³§Öµ£ºÓÉ´ó°æ±¾Ê×´ÎÆô¶¯Ê±Ð´Èë
+ *********************************************************************************/
+
+ BYTE abSoftVersionExt[ZPS_DEV_MSINFO_MAX_SOFTVERSION_EXT_LEN];
+ /********************************************************************************
+ ¹¦ÄÜ£º ÍⲿÈí¼þ°æ±¾ºÅ
+ È¡Öµ·¶Î§£º¿É¼ûASCIIÂë×Ö·û£¬ÒÔ×Ö·û'\0'½áÊø£¬Ê£Óà×Ö½ÚÌî³ä0x00
+ ³ö³§Öµ£ºÓÉ´ó°æ±¾Ê×´ÎÆô¶¯Ê±Ð´Èë
+ *********************************************************************************/
+ BYTE abPhoneInt[ZPS_DEV_MSINFO_MAX_PHONE_INT_LEN];
+ /********************************************************************************
+ ¹¦ÄÜ£º ÐͺŻúÄÚ²¿»úÐͺÅ
+ È¡Öµ·¶Î§£º¿É¼ûASCIIÂë×Ö·û£¬ÒÔ×Ö·û'\0'½áÊø£¬Ê£Óà×Ö½ÚÌî³ä0x00
+ ³ö³§Öµ£ºÓÉ´ó°æ±¾Ê×´ÎÆô¶¯Ê±Ð´Èë
+ *********************************************************************************/
+
+ BYTE abPhoneExt[ZPS_DEV_MSINFO_MAX_PHONE_EXT_LEN];
+ /********************************************************************************
+ ¹¦ÄÜ£º ÐͺŻúÍⲿ»úÐͺÅ
+ È¡Öµ·¶Î§£º¿É¼ûASCIIÂë×Ö·û£¬ÒÔ×Ö·û'\0'½áÊø£¬Ê£Óà×Ö½ÚÌî³ä0x00
+ ³ö³§Öµ£ºÓÉ´ó°æ±¾Ê×´ÎÆô¶¯Ê±Ð´Èë
+ *********************************************************************************/
+
+ BYTE abBoardInt[ZPS_DEV_MSINFO_MAX_BOARD_INT_LEN];
+ /********************************************************************************
+ ¹¦ÄÜ£º °å²àÄÚ²¿°æ±¾ºÅ
+ È¡Öµ·¶Î§£º¿É¼ûASCIIÂë×Ö·û£¬ÒÔ×Ö·û'\0'½áÊø£¬Ê£Óà×Ö½ÚÌî³ä0x00
+ ³ö³§Öµ£ºÓÉ´ó°æ±¾Ê×´ÎÆô¶¯Ê±Ð´Èë
+ *********************************************************************************/
+
+ BYTE abBoardExt[ZPS_DEV_MSINFO_MAX_BOARD_EXT_LEN];
+ /********************************************************************************
+ ¹¦ÄÜ£º °å²àÍⲿ°æ±¾ºÅ
+ È¡Öµ·¶Î§£º¿É¼ûASCIIÂë×Ö·û£¬ÒÔ×Ö·û'\0'½áÊø£¬Ê£Óà×Ö½ÚÌî³ä0x00
+ ³ö³§Öµ£ºÓÉ´ó°æ±¾Ê×´ÎÆô¶¯Ê±Ð´Èë
+ *********************************************************************************/
+}T_zPS_AMT_NV;
+/**/
+
+typedef enum
+{
+ ABIMEI_NVPARAM, //Ó²¼þÉ豸ºÅ
+ ABIMEISV_NVPARAM, //Èí¼þ°æ±¾ºÅ
+ ABBORDNUm_NVPARAM, // Ö÷°åºÅ
+ ABSOFTVERSION_NVPARAM, // Èí¼þ°æ±¾ºÅ
+ ABTESTINFO_NVPARAM, //Éú²ú²âÊÔ±ê־λ
+ ABSOFTVERSION_INT_NVPARAM, //Èí¼þÄÚ²¿°æ±¾ºÅ
+ ABSOFTVERSION_EXT_NVPARAM, //Èí¼þÍⲿ°æ±¾ºÅ
+ ABPHONE_INT_NVPARAM, //ÐͺŻúÄÚ²¿»úÐͺÅ
+ ABPHONE_EXT_NVPARAM, //ÐͺŻúÍⲿ»úÐͺÅ
+ ABBOARD_INT_NVPARAM, //°å²àÄÚ²¿°æ±¾ºÅ
+ ABBOARD_EXT_NVPARAM, //°å²àÍⲿ°æ±¾ºÅ
+ MAXABNVPARAM_NVPARAM
+}NvParam_AMT;
+
+/**************************************************************************
+ * Éú²ú²âÊÔ±ê־λµÄ¶¨Òå *
+ **************************************************************************/
+typedef enum
+{
+ AMTFLAGS_TDJIAOZHUN = 0, //TDУ׼±ê־λ
+ AMTFLAGS_GSMJIAOZHUN, //GSMУ׼±ê־λ
+ AMTFLAGS_TDZONGCE, //TD×Û²â±ê־λ
+ AMTFLAGS_GSMZONGCE, //GSM×Û²â±ê־λ
+ AMTFLAGS_BLUETOOTHZONGCE, //BlueTooth×Û²â±ê־λ
+ AMTFLAGS_AMTFLAGSZONGCE, //GPS×Û²â±ê־λ
+ AMTFLAGS_CMMBZONGCE, //CMMB×Û²â±ê־λ
+ AMTFLAGS_WIFIZONGCE, //WiFi×Û²â±ê־λ
+ AMTFLAGS_TDOUHE, //TDñîºÏ±ê־λ
+ AMTFLAGS_GSMOUHE, //GSMñîºÏ±ê־λ
+ AMTFLAGS_BLUETOOTHOUHE, //BlueToothñîºÏ±ê־λ
+ AMTFLAGS_GPSOUHE, //GPSñîºÏ±ê־λ
+ AMTFLAGS_CMMBOUHE, //CMMBñîºÏ±ê־λ
+ AMTFLAGS_WIFIOUHE, //WiFiñîºÏ±ê־λ
+ AMTFLAGS_TDLTEJIAOZHUN, //TD-LTEУ׼
+ AMTFLAGS_TDLTEZONGCE, //TD-LTE×Û²â
+ AMTFLAGS_TDLTEOUHE, //TD-LTEñîºÏ
+ AMTFLAGS_FDDLTEJIAOZHUN, //FDD-LTE У׼
+ AMTFLAGS_FDDLTEZONGCE, //FDD-LTE ×Û²â
+ AMTFLAGS_FDDLTEOUHE, //FDD-LTE ñîºÏ
+
+ MAXAMTFALGS_NVPARAM //
+}NvParam_AMTFlags;
+/**************************************************************************
+* º¯ÊýÃû³Æ: zPS_NvAMTItemWrite
+* ¹¦ÄÜÃèÊö: дһÏîNVÊý¾Ý
+* ²ÎÊý˵Ã÷:
+ (IN)
+ nvParam: ¸ÃNVÏîÀàÐÍ
+ NvItemData: дÈëµÄÊý¾Ý
+ NvItemLen: Êý¾Ý³¤¶È
+ (OUT)
+* ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+* ÆäËü˵Ã÷:
+**************************************************************************/
+UINT32 zPS_NvAMTItemWrite(NvParam_AMT nvParam,UINT8 *NvItemData, UINT32 NvItemLen);
+/**************************************************************************
+* º¯ÊýÃû³Æ: zPS_NvAMTItemRead
+* ¹¦ÄÜÃèÊö: ¶Á³öÒ»ÏîNVÊý¾Ý
+* ²ÎÊý˵Ã÷:
+ (IN)
+ nvParam: ¸ÃNVÏîÀàÐÍ
+ NvItemData: ¶Á³öµÄÊý¾Ý
+ NvItemLen: Êý¾Ý³¤¶È
+ (OUT)
+* ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+* ÆäËü˵Ã÷:
+**************************************************************************/
+UINT32 zPS_NvAMTItemRead(NvParam_AMT nvParam,UINT8 *NvItemData, UINT32 NvItemLen);
+/**************************************************************************
+* º¯ÊýÃû³Æ: zPS_NvAMTItemWrite
+* ¹¦ÄÜÃèÊö: дÉú²ú²âÊÔ±ê־λ
+* ²ÎÊý˵Ã÷:
+ (IN)
+ nvParam: ¸ÃNVÏîÀàÐÍ
+ NvItemData: дÈëµÄÊý¾Ý
+ (OUT)
+* ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+* ÆäËü˵Ã÷:
+**************************************************************************/
+UINT32 zPS_NvAMTFlagsItemWrite(NvParam_AMTFlags nvParam,UINT8 *NvItemData);
+/**************************************************************************
+* º¯ÊýÃû³Æ: zPS_NvAMTItemRead
+* ¹¦ÄÜÃèÊö:¶ÁÉú²ú²âÊÔ±ê־λ
+* ²ÎÊý˵Ã÷:
+ (IN)
+ nvParam: ¸ÃNVÏîÀàÐÍ
+ NvItemData: ¶Á³öµÄÊý¾Ý
+ (OUT)
+* ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+* ÆäËü˵Ã÷:
+**************************************************************************/
+UINT32 zPS_NvAMFlagsTItemRead(NvParam_AMTFlags nvParam,UINT8 *NvItemData);
+#endif
+#endif
+
diff --git a/pub/project/zx297520v3/include/nv/PubNvParam_PS.h b/pub/project/zx297520v3/include/nv/PubNvParam_PS.h
new file mode 100644
index 0000000..ef65123
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/PubNvParam_PS.h
@@ -0,0 +1,78 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: PubNvParam_PS.h
+ * File Mark:
+ * Description:
+
+ * Others:
+ * Version: v0.5
+ * Author:
+ * Date:
+ * History 1:
+ * Date: 2010.1.1
+ * Version:
+ * Author:luhuan
+ * Modification: 1¡¢Ôö¼ÓT_zPS_DEV_NV_MsInfo½á¹¹
+ * 2¡¢½«ÔÓнṹT_zPS_DEV_NV_ImeiºÍT_zPS_DEV_NV_MsInfoͳһºÏ²¢ÎªT_zPS_DEV_NV_PsData_Pub
+ * History 2:
+ * Date: 2010.1.27
+ * Version:
+ * Author:luhuan
+ * Modification: ¸ù¾ÝÉú²ú²âÊÔÐèÇó£¬ÒƳöÖظ´½á¹¹
+********************************************************************************/
+#ifndef PUBNVPARAM_PS_H
+#define PUBNVPARAM_PS_H
+
+#include "RONvParam_PS.h"
+#if 0
+#define ZPS_DEV_MSINFO_MAX_EQUIPNAME_LEN (BYTE)10
+
+typedef struct{
+ BYTE bEquipType; /********************************************************************************
+ ¹¦ÄÜ£ºÉ豸ÀàÐÍ
+ 01£ºWCDMA
+ 02: TD
+ 03: CDMA
+ 04: B3G
+ 05: WAT
+ 06: GSM
+ ³ö³§Öµ£º02
+ *********************************************************************************/
+ BYTE bSeqNum; /********************************************************************************
+ ¹¦ÄÜ£º ÐòÁкÅ
+ È¡Öµ·¶Î§£º0~255
+ ³ö³§Öµ£º1
+ *********************************************************************************/
+ BYTE abPadding1[2];/********************************************************************************
+ ¹¦ÄÜ£ºÌî³äλ
+ È¡Öµ·¶Î§£º0
+ ³ö³§Öµ£º0
+ *********************************************************************************/
+
+ BYTE abEquipName[ZPS_DEV_MSINFO_MAX_EQUIPNAME_LEN];
+ /********************************************************************************
+ ¹¦ÄÜ£º É豸ÐͺÅ
+ È¡Öµ·¶Î§£ºÈÎÒâ×Ö·û´®£¬ÒÔ'\0'±íʾ½áÊø
+ ³ö³§Öµ£ºÓɳö²ú³§É̾ö¶¨
+ *********************************************************************************/
+ BYTE abPadding2[2];/********************************************************************************
+ ¹¦ÄÜ£ºÌî³äλ
+ È¡Öµ·¶Î§£º0
+ ³ö³§Öµ£º0
+ *********************************************************************************/
+}T_zPS_DEV_NV_PsMsInfo;
+
+
+typedef struct {
+ T_zPS_DEV_NV_PsMsInfo tPsMsInfo; /********************************************************************************
+ ¹¦ÄÜ£ºÐÒéջʹÓõÄMobile StationÏà¹ØÐÅÏ¢
+ È¡Öµ·¶Î§£º²Î¼ûÄÚ²¿½á¹¹ËµÃ÷
+ ³ö³§Öµ£º²Î¼ûÄÚ²¿½á¹¹ËµÃ÷
+ *********************************************************************************/
+}T_zPS_DEV_NV_Data_Pub;
+
+#endif
+#endif
+
+
diff --git a/pub/project/zx297520v3/include/nv/RONvConfig.h b/pub/project/zx297520v3/include/nv/RONvConfig.h
new file mode 100755
index 0000000..71ce58a
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/RONvConfig.h
@@ -0,0 +1,117 @@
+/**************************************************************************
+*
+* Copyright (c) 2014 ZTE Corporation.
+*
+***************************************************************************
+* Ä£ ¿é Ãû :
+* ÎÄ ¼þ Ãû : RONvConfig.h
+* Ïà¹ØÎļþ :
+* ʵÏÖ¹¦ÄÜ :
+* ×÷ Õß :
+* °æ ±¾ :
+* Íê³ÉÈÕÆÚ :
+* ÆäËü˵Ã÷ :
+**************************************************************************/
+
+/**************************************************************************
+* Ð޸ļǼ
+**************************************************************************/
+#ifndef _RONVCONFIG_H
+#define _RONVCONFIG_H
+
+/****************************************************************************
+Begin
+****************************************************************************/
+#define OS_FLASH_NV_PARTITION_BASE_ADDR 0 /*NV·ÖÇø»ùÖ·*/
+#define OS_FLASH_RO_OFFSET_FROM_NV 0 /*Ö»¶ÁÇøÆ«ÒÆ*/
+#define OS_FLASH_RO_NVRAM_SIZE (0x180000UL)
+
+/************************************
+amt area config---part I AMT comm info-32KB
+*************************************/
+#define OS_FLASH_AMT_COMM_RO_OFFSET_FROM_NV OS_FLASH_RO_OFFSET_FROM_NV
+#define OS_FLASH_AMT_COMM_RO_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_COMM_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_COMM_RO_NONFAC_SIZE (32 * 1024)
+
+/************************************
+amt area config---part II TDD_LTE&FDD_LTE info-256KB
+*************************************/
+#define OS_FLASH_AMT_LTE_RO_OFFSET_FROM_NV (OS_FLASH_AMT_COMM_RO_OFFSET_FROM_NV + OS_FLASH_AMT_COMM_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_LTE_RO_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_LTE_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_LTE_RO_NONFAC_SIZE (256 * 1024)
+
+/************************************
+amt area config---part IV TD_S info-32KB
+*************************************/
+#define OS_FLASH_AMT_TDS_RO_OFFSET_FROM_NV (OS_FLASH_AMT_LTE_RO_OFFSET_FROM_NV + OS_FLASH_AMT_LTE_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_TDS_RO_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_TDS_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_TDS_RO_NONFAC_SIZE (32 * 1024)
+
+/************************************
+amt area config---part V GGE info-32KB
+*************************************/
+#define OS_FLASH_AMT_GGE_RO_OFFSET_FROM_NV (OS_FLASH_AMT_TDS_RO_OFFSET_FROM_NV + OS_FLASH_AMT_TDS_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_GGE_RO_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_GGE_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_GGE_RO_NONFAC_SIZE (32 * 1024)
+
+/************************************
+amt area config---part VII WCDMA info-128KB
+*************************************/
+#define OS_FLASH_AMT_WCDMA_RO_OFFSET_FROM_NV (OS_FLASH_AMT_GGE_RO_OFFSET_FROM_NV + OS_FLASH_AMT_GGE_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_WCDMA_RO_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_WCDMA_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_WCDMA_RO_NONFAC_SIZE (128 * 1024)
+
+/************************************
+amt area config---part VII LTEA info-480KB
+*************************************/
+#define OS_FLASH_AMT_LTEA_RO_OFFSET_FROM_NV (OS_FLASH_AMT_WCDMA_RO_OFFSET_FROM_NV + OS_FLASH_AMT_WCDMA_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_LTEA_RO_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_LTEA_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_LTEA_RO_NONFAC_SIZE (320 * 1024)
+
+/************************************
+amt area config---part VI WiFi info-32KB
+*************************************/
+#define OS_FLASH_AMT_WIFI_RO_OFFSET_FROM_NV (OS_FLASH_AMT_LTEA_RO_OFFSET_FROM_NV + OS_FLASH_AMT_LTEA_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_WIFI_RO_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_WIFI_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_WIFI_RO_NONFAC_SIZE (32 * 1024)
+
+/************************************
+lock net config---32KB
+*************************************/
+#define OS_FLASH_AMT_LOCKNET_RO_OFFSET_FROM_NV (OS_FLASH_AMT_WIFI_RO_OFFSET_FROM_NV + OS_FLASH_AMT_WIFI_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_LOCKNET_RO_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_LOCKNET_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_LOCKNET_RO_NONFAC_SIZE (32 * 1024)
+
+/****************************************************************************
+reserved config
+****************************************************************************/
+
+/************************************
+amt area config---Reserved -160KB
+*************************************/
+#define OS_FLASH_AMT_RESERVED_RO_OFFSET_FROM_NV (OS_FLASH_AMT_LOCKNET_RO_OFFSET_FROM_NV + OS_FLASH_AMT_LOCKNET_RO_NONFAC_SIZE)
+#define OS_FLASH_AMT_RESERVED_RO_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_RESERVED_RO_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_RESERVED_RO_NONFAC_SIZE (160 * 1024)
+
+/****************************************************************************
+ROW (0.5M)
+****************************************************************************/
+#define OS_FLASH_ROW_OFFSET_FROM_NV (OS_FLASH_RO_OFFSET_FROM_NV + OS_FLASH_RO_NVRAM_SIZE) /* ÏÞÖƶÁдÇøÆ«ÒÆ */
+#define OS_FLASH_ROW_NVRAM_SIZE (512 * 1024)
+
+/************************************
+lock net config---32KB
+*************************************/
+#define OS_FLASH_LOCKNET_ROW_OFFSET_FROM_NV (OS_FLASH_ROW_OFFSET_FROM_NV)
+#define OS_FLASH_LOCKNET_ROW_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_LOCKNET_ROW_OFFSET_FROM_NV)
+#define OS_FLASH_LOCKNET_ROW_SIZE (32 * 1024)
+
+/************************************
+c0 caliinfo---4KB
+*************************************/
+#define OS_FLASH_C0CALIINFO_ROW_OFFSET_FROM_NV (OS_FLASH_LOCKNET_ROW_OFFSET_FROM_NV + OS_FLASH_LOCKNET_ROW_SIZE)
+#define OS_FLASH_C0CALIINFO_ROW_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_C0CALIINFO_ROW_OFFSET_FROM_NV)
+#define OS_FLASH_C0CALIINFO_ROW_SIZE (4 * 1024)
+
+#endif
+
diff --git a/pub/project/zx297520v3/include/nv/RONvParam.h b/pub/project/zx297520v3/include/nv/RONvParam.h
new file mode 100644
index 0000000..7e9e815
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/RONvParam.h
@@ -0,0 +1,139 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:pubnvparm.h
+ * File Mark:
+ * Description:public config NV parameters
+
+ * Others:
+ * Version: v0.5
+ * Author: xuxingkui
+ * Date: 2009-09-28
+ * History 1:
+ * Date: 2009-11-24
+ * Version: v1.0
+ * Author: xuxingkui
+ * Modification: add a line at the end of this file
+ *
+ * History 2:
+ ********************************************************************************/
+
+#ifndef _RONVPARM_H
+#define _RONVPARM_H
+
+#include "NandFlash.h"
+#include "RONvParam_PS.h"
+#include "RONvParam_AMT.h"
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+/****************************************************************************
+* Local Macros
+****************************************************************************/
+
+/****************************************************************************
+* DIVER
+****************************************************************************/
+/***********************************
+driver leave factory parmameters
+************************************/
+typedef struct _tagZFacPub_DrvParam
+{
+
+}T_ZFacPub_DrvParam;
+
+/***********************************
+driver none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPub_DrvParam
+{
+
+}T_ZNonFacPub_DrvParam;
+
+/****************************************************************************
+* PS
+****************************************************************************/
+/***********************************
+PS leave factory parmameters
+************************************/
+typedef struct _tagZFacPub_PsParam
+{
+
+}T_ZFacPub_PsParam;
+
+/***********************************
+PS none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPub_PsParam
+{
+ T_zPS_DEV_NV_Imei psDevNv;
+}T_ZNonFacPub_PsParam;
+
+/****************************************************************************
+* AMT
+****************************************************************************/
+/***********************************
+AMT leave factory parmameters
+************************************/
+typedef struct _tagZFacPub_AMTParam
+{
+
+}T_ZFacPub_AMTParam;
+
+/***********************************
+AMT none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPub_AMTParam
+{
+ T_zPS_AMT_NV AMTDevNv;
+}T_ZNonFacPub_AMTParam;
+
+/****************************************************************************
+* USER
+****************************************************************************/
+/***********************************
+User factory public parmameters
+************************************/
+typedef struct _tagZFacPub_UserParam
+{
+
+}T_ZFacPub_UserParam;
+
+/***********************************
+User nonfactory public parmameters
+************************************/
+typedef struct _tagNonFacPub_UserParam
+{
+
+}T_ZNonFacPub_UserParam;
+
+/****************************************************************************
+* Public TSP
+****************************************************************************/
+/***********************************
+Tsp leave factory parmameters
+************************************/
+typedef struct _tagZPub_TspParam
+{
+ /* leave factory parmameters */
+ T_ZFacPub_DrvParam gFacPubDrvParam; /* driver */
+ T_ZFacPub_PsParam gFacPubPsParam; /* ps */
+ T_ZFacPub_AMTParam gFacPubAMTParam; /* AMT */
+ T_ZFacPub_UserParam gFacPubUserParam; /* user */
+
+ /* none leave factory parmameters */
+ T_ZNonFacPub_DrvParam gNonFacPubDrvParam; /* driver */
+ T_ZNonFacPub_PsParam gNoneFacPubPsParam; /* ps */
+ T_ZNonFacPub_AMTParam gNoneFacPubAMTParam;/* amt */
+ T_ZNonFacPub_UserParam gNonFacPubUserParam; /* user */
+
+}T_ZPub_TspParam;
+
+#endif
+
+
+
+
+
diff --git a/pub/project/zx297520v3/include/nv/RONvParam_AMT.h b/pub/project/zx297520v3/include/nv/RONvParam_AMT.h
new file mode 100755
index 0000000..3ff85fb
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/RONvParam_AMT.h
@@ -0,0 +1,413 @@
+/*****************************************************************************
+ * Copyright (C) 2013, ZTE Corporation.
+ *
+ * File Name:PubNvParam_AMT.h
+ * File Mark:
+ * Description:public config NV parameters
+ * Date: 2013-08-21
+ * Author: hupo
+ ****************************************************************************/
+#ifndef _RONVPARAM_AMT_H
+#define _RONVPARAM_AMT_H
+
+#include "RONvConfig.h"
+
+// AMT COMM ITEM
+#define OS_FLASH_AMT_COMM_RO_IMEI_ADDRESS OS_FLASH_AMT_COMM_RO_NONFAC_BASE_ADDR
+#define OS_FLASH_AMT_COMM_RO_IMEI_SIZE 8
+
+#define OS_FLASH_AMT_COMM_RO_IMEI_Reserved_ADDRESS OS_FLASH_AMT_COMM_RO_IMEI_ADDRESS + OS_FLASH_AMT_COMM_RO_IMEI_SIZE
+#define OS_FLASH_AMT_COMM_RO_IMEI_Reserved_SIZE 12
+
+#define OS_FLASH_AMT_COMM_RO_IMEISV_ADDRESS OS_FLASH_AMT_COMM_RO_IMEI_Reserved_ADDRESS + OS_FLASH_AMT_COMM_RO_IMEI_Reserved_SIZE
+#define OS_FLASH_AMT_COMM_RO_IMEISV_SIZE 8
+
+#define OS_FLASH_AMT_COMM_RO_IMEISV_Reserved_ADDRESS OS_FLASH_AMT_COMM_RO_IMEISV_ADDRESS + OS_FLASH_AMT_COMM_RO_IMEISV_SIZE
+#define OS_FLASH_AMT_COMM_RO_IMEISV_Reserved_SIZE 12
+
+#define OS_FLASH_AMT_COMM_RO_BOARDNNUM_ADDRESS OS_FLASH_AMT_COMM_RO_IMEISV_Reserved_ADDRESS + OS_FLASH_AMT_COMM_RO_IMEISV_Reserved_SIZE
+#define OS_FLASH_AMT_COMM_RO_BOARDNNUM_SIZE 20
+
+#define OS_FLASH_AMT_COMM_RO_MSerialNum_ADDRESS OS_FLASH_AMT_COMM_RO_BOARDNNUM_ADDRESS + OS_FLASH_AMT_COMM_RO_BOARDNNUM_SIZE
+#define OS_FLASH_AMT_COMM_RO_MSerialNum_SIZE 20
+
+#define OS_FLASH_AMT_COMM_RO_ValidFlag_ADDRESS OS_FLASH_AMT_COMM_RO_MSerialNum_ADDRESS + OS_FLASH_AMT_COMM_RO_MSerialNum_SIZE
+#define OS_FLASH_AMT_COMM_RO_ValidFlag_SIZE 4
+
+#define OS_FLASH_AMT_COMM_RO_InternalMAC_ADDRESS OS_FLASH_AMT_COMM_RO_ValidFlag_ADDRESS + OS_FLASH_AMT_COMM_RO_ValidFlag_SIZE
+#define OS_FLASH_AMT_COMM_RO_InternalMAC_SIZE 20
+
+#define OS_FLASH_AMT_COMM_RO_ExternalMAC_ADDRESS OS_FLASH_AMT_COMM_RO_InternalMAC_ADDRESS + OS_FLASH_AMT_COMM_RO_InternalMAC_SIZE
+#define OS_FLASH_AMT_COMM_RO_ExternalMAC_SIZE 20
+
+#define OS_FLASH_AMT_COMM_RO_WIFIMAC_ADDRESS OS_FLASH_AMT_COMM_RO_ExternalMAC_ADDRESS + OS_FLASH_AMT_COMM_RO_ExternalMAC_SIZE
+#define OS_FLASH_AMT_COMM_RO_WIFIMAC_SIZE 20
+
+#define OS_FLASH_AMT_COMM_RO_NvVersion_ADDRESS OS_FLASH_AMT_COMM_RO_WIFIMAC_ADDRESS + OS_FLASH_AMT_COMM_RO_WIFIMAC_SIZE
+#define OS_FLASH_AMT_COMM_RO_NvVersion_SIZE 40
+
+#define OS_FLASH_AMT_COMM_RO_TestInfo_ADDRESS OS_FLASH_AMT_COMM_RO_NvVersion_ADDRESS + OS_FLASH_AMT_COMM_RO_NvVersion_SIZE
+#define OS_FLASH_AMT_COMM_RO_TestInfo_SIZE 200
+
+#define OS_FLASH_AMT_COMM_RO_SOFTVERSION_ADDRESS OS_FLASH_AMT_COMM_RO_TestInfo_ADDRESS + OS_FLASH_AMT_COMM_RO_TestInfo_SIZE
+#define OS_FLASH_AMT_COMM_RO_SOFTVERSION_SIZE 10
+
+#define OS_FLASH_AMT_COMM_RO_V4Key_ADDRESS OS_FLASH_AMT_COMM_RO_SOFTVERSION_ADDRESS + OS_FLASH_AMT_COMM_RO_SOFTVERSION_SIZE
+#define OS_FLASH_AMT_COMM_RO_V4Key_SIZE 84
+
+#define OS_FLASH_AMT_COMM_RO_V4Key_Reserved_ADDRESS OS_FLASH_AMT_COMM_RO_V4Key_ADDRESS + OS_FLASH_AMT_COMM_RO_V4Key_SIZE
+#define OS_FLASH_AMT_COMM_RO_V4Key_Reserved_SIZE 16
+
+#define OS_FLASH_AMT_COMM_RO_SaleState_ADDRESS OS_FLASH_AMT_COMM_RO_V4Key_Reserved_ADDRESS + OS_FLASH_AMT_COMM_RO_V4Key_Reserved_SIZE
+#define OS_FLASH_AMT_COMM_RO_SaleState_SIZE 2
+
+#define OS_FLASH_AMT_COMM_RO_SaleState_Reserved_ADDRESS OS_FLASH_AMT_COMM_RO_SaleState_ADDRESS + OS_FLASH_AMT_COMM_RO_SaleState_SIZE
+#define OS_FLASH_AMT_COMM_RO_SaleState_Reserved_SIZE 16
+
+#define OS_FLASH_AMT_COMM_RO_BANDBITMAP_ADDRESS OS_FLASH_AMT_COMM_RO_SaleState_Reserved_ADDRESS + OS_FLASH_AMT_COMM_RO_SaleState_Reserved_SIZE
+#define OS_FLASH_AMT_COMM_RO_BANDBITMAP_SIZE 112
+
+#define OS_FLASH_AMT_COMM_RO_BANDBITMAP_Reserved_ADDRESS OS_FLASH_AMT_COMM_RO_BANDBITMAP_ADDRESS + OS_FLASH_AMT_COMM_RO_BANDBITMAP_SIZE
+#define OS_FLASH_AMT_COMM_RO_BANDBITMAP_Reserved_SIZE 40
+
+#define OS_FLASH_AMT_COMM_RO_ETHMAC_ADDRESS OS_FLASH_AMT_COMM_RO_BANDBITMAP_Reserved_ADDRESS + OS_FLASH_AMT_COMM_RO_BANDBITMAP_Reserved_SIZE
+#define OS_FLASH_AMT_COMM_RO_ETHMAC_SIZE 20
+
+#define OS_FLASH_AMT_COMM_RO_LockKey_ADDRESS OS_FLASH_AMT_COMM_RO_ETHMAC_ADDRESS + OS_FLASH_AMT_COMM_RO_ETHMAC_SIZE
+#define OS_FLASH_AMT_COMM_RO_LockKey_SIZE 20
+
+#define OS_FLASH_AMT_COMM_RO_WIFIMAC2_ADDRESS OS_FLASH_AMT_COMM_RO_LockKey_ADDRESS + OS_FLASH_AMT_COMM_RO_LockKey_SIZE
+#define OS_FLASH_AMT_COMM_RO_WIFIMAC2_SIZE 20
+
+#define OS_FLASH_AMT_COMM_RO_USBMAC_ADDRESS OS_FLASH_AMT_COMM_RO_WIFIMAC2_ADDRESS + OS_FLASH_AMT_COMM_RO_WIFIMAC2_SIZE
+#define OS_FLASH_AMT_COMM_RO_USBMAC_SIZE 20
+
+#define OS_FLASH_AMT_COMM_RO_GMAC_ADDRESS OS_FLASH_AMT_COMM_RO_USBMAC_ADDRESS + OS_FLASH_AMT_COMM_RO_USBMAC_SIZE
+#define OS_FLASH_AMT_COMM_RO_GMAC_SIZE 20
+
+#define OS_FLASH_AMT_COMM_RO_FEATURE_KEY_MD5_ADDRESS OS_FLASH_AMT_COMM_RO_GMAC_ADDRESS + OS_FLASH_AMT_COMM_RO_GMAC_SIZE
+#define OS_FLASH_AMT_COMM_RO_FEATURE_KEY_MD5_SIZE 128
+
+#define OS_FLASH_AMT_COMM_RO_AUTH_KEY_ADDRESS OS_FLASH_AMT_COMM_RO_FEATURE_KEY_MD5_ADDRESS + OS_FLASH_AMT_COMM_RO_FEATURE_KEY_MD5_SIZE
+#define OS_FLASH_AMT_COMM_RO_AUTH_KEY_SIZE 20
+
+#define OS_FLASH_AMT_COMM_RO_SOFTDOG_CIPHER_TEXT_ADDRESS OS_FLASH_AMT_COMM_RO_AUTH_KEY_ADDRESS + OS_FLASH_AMT_COMM_RO_AUTH_KEY_SIZE
+#define OS_FLASH_AMT_COMM_RO_SOFTDOG_CIPHER_TEXT_SIZE 256
+
+
+
+// ½ð»úÊý¾Ý£¬¿Éµ¥¶À¼ÆËã
+#define OS_FLASH_AMT_COMM_RO_GBDATA_ADDRESS OS_FLASH_AMT_COMM_RO_NONFAC_BASE_ADDR + 0x2800
+#define OS_FLASH_AMT_COMM_RO_GBDATA_SIZE 5120
+// ÖØй滮ÇøÓò,¸ø²Î¿¼Éè¼ÆºÍÍⲿ¿Í»§¸÷·ÖÅä1k×Ö½ÚÓÃÓÚ´æ´¢Êý¾Ý
+#define OS_FLASH_AMT_COMM_RO_USER_DEFINE_ADDRESS OS_FLASH_AMT_COMM_RO_NONFAC_BASE_ADDR + 0x7C00
+#define OS_FLASH_AMT_COMM_RO_USER_DEFINE_SIZE 0x400
+
+#define OS_FLASH_AMT_COMM_RO_REF_DEFINE_ADDRESS OS_FLASH_AMT_COMM_RO_NONFAC_BASE_ADDR + 0x7800
+#define OS_FLASH_AMT_COMM_RO_REF_DEFINE_SIZE 0x400
+
+
+// ·ÏÆú,²»ÒªÔÙÒýÓÃ,ÈçÐèÒýÓã¬ÇëÖ±½ÓÒýÓöÔÓ¦ÏîµÄXXX_SIZEºê¶¨Òå
+#define ZPS_ImeiLen OS_FLASH_AMT_COMM_RO_IMEI_SIZE
+#define ZPS_ImeiSvLen OS_FLASH_AMT_COMM_RO_IMEISV_SIZE
+#define ZPS_DEV_MSINFO_MAX_BORDNAME_LEN OS_FLASH_AMT_COMM_RO_BOARDNNUM_SIZE
+#define ZPS_DEV_MSINFO_MAX_WIFIMAC_LEN OS_FLASH_AMT_COMM_RO_WIFIMAC_SIZE
+#define ZPS_DEV_MSINFO_MAX_SOFTVERSION_LEN OS_FLASH_AMT_COMM_RO_SOFTVERSION_SIZE
+#define ZPS_DEV_MSINFO_MAX_WIFIMAC2_LEN OS_FLASH_AMT_COMM_RO_WIFIMAC2_SIZE
+
+#define Comm_DEV_MSINFO_MAX_WIFIMAC_Area_Len OS_FLASH_AMT_COMM_RO_WIFIMAC_SIZE
+#define Comm_DEV_MSINFO_MAX_WIFIMAC2_Area_Len OS_FLASH_AMT_COMM_RO_WIFIMAC2_SIZE
+#define Comm_DEV_MSINFO_MAX_ETHMAC_Area_Len OS_FLASH_AMT_COMM_RO_ETHMAC_SIZE
+
+#define ZPS_DEV_MSINFO_MAX_Keys_LEN OS_FLASH_AMT_COMM_RO_V4Key_SIZE
+#define Comm_DEV_MSINFO_Keys_Area_Len OS_FLASH_AMT_COMM_RO_V4Key_SIZE
+#define ZPS_DEV_MSINFO_MAX_SaleState_LEN OS_FLASH_AMT_COMM_RO_SaleState_SIZE
+
+
+typedef enum
+{
+ ABIMEI_NVPARAM, // Ó²¼þÉ豸ºÅ
+ ABIMEISV_NVPARAM, // Èí¼þ°æ±¾ºÅÒѾ²»ÔÙʹÓÃ
+ ABBORDNUm_NVPARAM, // Ö÷°åºÅ
+ ABMSERIALNUM_NVPARAM, // ´®ºÅ
+ ABVALIDFLAG_NVPARAM, // MACµØÖ·Ñ¡Ôñָʾλ
+
+ ABMAC_INT_NVPARAM, // ÄÚ²¿MACµØÖ·
+ ABMAC_EXT_NVPARAM, // ÍⲿMACµØÖ·
+ ABMAC_WIFI_NVPARAM, // WIFI MACµØÖ·
+ ABNV_VERSION_NVPARAM, // NV°æ±¾ÐÅÏ¢
+ ABTESTINFO_NVPARAM, // Éú²ú²âÊÔ±ê־λ
+ ABSOFTVERSION_NVPARAM, // ºóÐøÐèÒªÐÞ¸ÄÄ¿Ç°Èí¼þ°æ±¾ºÅ²»ÔÚÖ»¶ÁÇø
+ ABNET_V4KEY_NVPARAM,
+ ABSALE_STATE_NVPARAM, // MF832S+ÏúÁ¿Í³¼Æ±êÖ¾
+ ABBANDBITMAP_NVPARAM, // BAND BITMAP
+ ABMAC_ETH_NVPARAM, // ETH MACµØÖ·
+ ABNET_LCOKKEY_NVPARAM, // ½âËøÂë
+ ABMAC_WIFI2_NVPARAM, // MF971ÏîÄ¿Ôö¼ÓµÚ¶þ¸öWIFIµØÖ·
+ ABMAC_USBMAC_NVPARAM, //USB(Rndis,ECM)MACµØÖ·
+ ABMAC_GMAC_NVPARAM, //GMAC(PHY/Switch) MACµØÖ·
+ ABFEATURE_KEY_MD5_NVPARAM, //7520MBBÏîÄ¿·ÀµÁË¢ÌØÕ÷ÂëµÄMD5Öµ
+ ABAUTH_KEY_NVPARAM, //GD113 ÉÕ¼ÏÞÖƼøȨÂë
+ ABSOFTDOG_CIPHER_TEXT_NVPARAM, //¶ùͯÊÖ±íÈí¼þ¹·¼ÓÃÜÊý¾Ý
+ ABGBDATA_NVPARAM, // GBNV data by wong 20150602
+
+ MAXABNVPARAM_NVPARAM
+} NvParam_AMT;
+
+/*****************************************************************************
+ * Éú²ú²âÊÔ±ê־λµÄ¶¨Òå *
+ *****************************************************************************/
+typedef enum
+{
+ BOARDTEST_CURRENT = 0, BOARDTEST_AUDIO, BOARDTEST_BT, BOARDTEST_RESERVED, //×Ö½Ú0£¬°å²â
+ GSM_CAL, GSM_FT, GSM_CPT, GSM_RESERVED, //×Ö½Ú1£¬GSM
+ GPRS_FT, GPRS_CPT, GPRS_RESERVED1, GPRS_RESERVED2, //×Ö½Ú2£¬GPRS
+ EDGE_CAL, EDGE_FT, EDGE_CPT, EDGE_RESERVED, //×Ö½Ú3£¬EDGE
+ CDMA_CAL, CDMA_FT, CDMA_CPT, CDMA_DIV_CPT, //×Ö½Ú4£¬CDMA
+ EVDO_FT, EVDO_CPT, EVDO_CAL, EVDO_RESERVED2, //×Ö½Ú5£¬EVDO
+ WCDMA_CAL, WCDMA_FT, WCDMA_CPT, WCDMA_DIV_CPT, //×Ö½Ú6£¬WCDMA
+ TD_CAL, TD_FT, TD_CPT, TD_RESERVED, //×Ö½Ú7£¬TD
+ WIMAX_CAL, WIMAX_FT, WIMAX_CPT, WIMAX_RESERVED, //×Ö½Ú8£¬WIMAX
+ LTE_CAL, LTE_FT, LTE_CPT, LTE_DIV_CPT, //×Ö½Ú9£¬LTE ×¢£ºÔÚË«LTE»úÐÍÉÏÌØÖ¸FDD_LTE
+ BLUETOOTH_CAL, BLUETOOTH_FT, BLUETOOTH_CPT, BLUETOOTH_FUN, //×Ö½Ú10£¬À¶ÑÀ
+ WIFI_CAL, WIFI_FT, WIFI_CPT, WIFI_FUN, //×Ö½Ú11£¬WIFI
+ GPS_FT, GPS_CPT, GPS_FUN, GPS_RESERVED, //×Ö½Ú12£¬GPS
+ MOBILETV_FT, MOBILETV_CPT, MOBILETV_FUN, MOBILETV_RESERVED, //×Ö½Ú13£¬TV
+ NFC_FT, NFC_FUN, NFC_RESERVED1, NFC_RESERVED2, //×Ö½Ú14£¬NFC
+ BASEBAND_CURRENT, BASEBAND_AUDIO, BASEBAND_RESERVED1, BASEBAND_RESERVED2, //×Ö½Ú15£¬Õû»ú»ù´ø
+ CAC_PREVIEW, CAC_FINALCHECK, CAC_RESERVED2, CAC_RESERVED3, //×Ö½Ú16£¬¹¦ÄܲâÊÔ
+ HSPA_FT, HSPA_CPT, HSPA_RESERVED1, HSPA_RESERVED2, //×Ö½Ú17£¬HSPA
+ WCDMA_GSM_FUN, EVDO_CDMA_FUN, TD_GSM_FUN, LTE_TDD_FUN,
+ LTE_FDD_FUN, FUN_RESERVED1, FUN_RESERVED2, FUN_RESERVED3, //18¡¢19×Ö½Ú£¬¹¦ÄܲâÊÔ
+
+ TDD_CAL, TDD_FT, TDD_CPT, TDD_DIV_CPT, //×Ö½Ú20 TDD¡¢FDDË«LTE»úÐ͵ÄTDD±êÖ¾
+ GSM_2_CAL, GSM_2_FT, GSM_2_CPT, GSM_2_DIV_CPT, //×Ö½Ú21 ÊÊÓÃÓÚGSM Ë«¹¤Î»»úÐ͵ĵÚ2¸ö¹¤Î»±êÖ¾
+ GPRS_2_CAL, GPRS_2_FT, GPRS_2_CPT, GPRS_2_DIV_CPT, //×Ö½Ú22 ÊÊÓÃÓÚGPRS Ë«¹¤Î»»úÐ͵ĵÚ2¸ö¹¤Î»±êÖ¾
+ EDGE_2_CAL, EDGE_2_FT, EDGE_2_CPT, EDGE_2_DIV_CPT, //×Ö½Ú23 ÊÊÓÃÓÚEDGE Ë«¹¤Î»»úÐ͵ĵÚ2¸ö¹¤Î»±êÖ¾
+ WCDMA_2_CAL, WCDMA_2_FT, WCDMA_2_CPT, WCDMA_2_DIV_CPT, //×Ö½Ú24 ÊÊÓÃÓÚWCDMA Ë«¹¤Î»»úÐ͵ĵÚ2¸ö¹¤Î»±êÖ¾
+ HSPA_2_CAL, HSPA_2_FT, HSPA_2_CPT, HSPA_2_DIV_CPT, //×Ö½Ú25 ÊÊÓÃÓÚHSPA Ë«¹¤Î»»úÐ͵ĵÚ2¸ö¹¤Î»±êÖ¾
+ CDMA_2_CAL, CDMA_2_FT, CDMA_2_CPT, CDMA_2_DIV_CPT, //×Ö½Ú26 ÊÊÓÃÓÚCDMA Ë«¹¤Î»»úÐ͵ĵÚ2¸ö¹¤Î»±êÖ¾
+ EVDO_2_CAL, EVDO_2_FT, EVDO_2_CPT, EVDO_2_DIV_CPT, //×Ö½Ú27 ÊÊÓÃÓÚEVDO Ë«¹¤Î»»úÐ͵ĵÚ2¸ö¹¤Î»±êÖ¾
+ LTE_2_CAL, LTE_2_FT, LTE_2_CPT, LTE_2_DIV_CPT, //×Ö½Ú28 ÊÊÓÃÓÚLTE Ë«¹¤Î»»úÐ͵ĵÚ2¸ö¹¤Î»±êÖ¾
+
+ ICERA_CONFIG, ICERA_RESERVED1, ICERA_RESERVED2, ICERA_RESERVED3, //29×Ö½Ú£¬ ICERA
+
+ LTE_BAND1_CAL, LTE_BAND1_FT, LTE_BAND1_CPT, LTE_BAND1_RESERVED, //30×Ö½Ú£¬ LTE Ƶ¶Î1
+ LTE_BAND2_CAL, LTE_BAND2_FT, LTE_BAND2_CPT, LTE_BAND2_RESERVED, //31×Ö½Ú£¬ LTE Ƶ¶Î2
+ LTE_BAND3_CAL, LTE_BAND3_FT, LTE_BAND3_CPT, LTE_BAND3_RESERVED, //32×Ö½Ú£¬ LTE Ƶ¶Î3
+ LTE_BAND4_CAL, LTE_BAND4_FT, LTE_BAND4_CPT, LTE_BAND4_RESERVED, //33×Ö½Ú£¬ LTE Ƶ¶Î4
+ LTE_BAND5_CAL, LTE_BAND5_FT, LTE_BAND5_CPT, LTE_BAND5_RESERVED, //34×Ö½Ú£¬ LTE Ƶ¶Î5
+ LTE_BAND6_CAL, LTE_BAND6_FT, LTE_BAND6_CPT, LTE_BAND6_RESERVED, //35×Ö½Ú£¬ LTE Ƶ¶Î6
+ LTE_BAND7_CAL, LTE_BAND7_FT, LTE_BAND7_CPT, LTE_BAND7_RESERVED, //36×Ö½Ú£¬ LTE Ƶ¶Î7
+ LTE_BAND8_CAL, LTE_BAND8_FT, LTE_BAND8_CPT, LTE_BAND8_RESERVED, //37×Ö½Ú£¬ LTE Ƶ¶Î8
+ LTE_BAND9_CAL, LTE_BAND9_FT, LTE_BAND9_CPT, LTE_BAND9_RESERVED, //38×Ö½Ú£¬ LTE Ƶ¶Î9
+ LTE_BAND10_CAL, LTE_BAND10_FT, LTE_BAND10_CPT, LTE_BAND10_RESERVED, //39×Ö½Ú£¬ LTE Ƶ¶Î10
+
+ TDD_2_CAL, TDD_2_FT, TDD_2_CPT, TDD_2_DIV_CPT, //40×Ö½Ú£¬ÊÊÓÃÓÚTDD_LTE Ë«¹¤Î»»úÐ͵ĵÚ2¸ö¹¤Î»±êÖ¾
+ GPS_2_FT, GPS_2_CPT, GPS_2_FUN, GPS_2_RESERVED, //41×Ö½Ú£¬ÊÊÓÃÓÚGPSË«¹¤Î»»úÐ͵ĵÚ2¸ö¹¤Î»±êÖ¾£¨±±¶·GPS£©
+ DL_PV, DL_RELEASE, DL_AMT, DL_RESERVED, //42×Ö½Ú£¬ÊÊÓÃÓÚÏÂÔØ
+ BAND_BIT_MAP_FLAG, BAND_BIT_MAP_RESERVED1, BAND_BIT_MAP_RESERVED2, BAND_BIT_MAP_RESERVED3, //43×Ö½Ú£¬BAND_BIT_MAP_FLAG
+ /* ÍâÉ蹦ÄܲâÊÔ */
+ SOFTVERSION_CHECK, TESTINFO_CHECK, BUTTION_CHECK, LCD_BACKLIT_CHECK, //44×Ö½Ú,
+ MOTOR_CHECK, LCD_TEST, LOUDSPEAKER_CHECK, EARPHONE_CHECK, //45×Ö½Ú,
+ MICRO_PHONE_CHECK, HEAD_SET_CHECK, FM_CHECK, SIMCARD_CHECK, //46×Ö½Ú,
+ CHARGING_CHECK, FLASH_LIGHT_CHECK, KEY_LIGHT_CHECK, RESET_CHECK, //47×Ö½Ú,
+ HEADSET_KEY_CHECK, BATTERT_VOLTAGE_CHECHK, SDCARD_CHECK, CAMERA_BACK_CHECK, //48×Ö½Ú,
+ IDLE_CURRENT_CHECK, OFF_CURRENT_CHECK, DEVICETEST_RESERVED1, DEVICETEST_RESERVED2, //49×Ö½Ú,
+ DEVICETEST_RESERVED3, DEVICETEST_RESERVED4, DEVICETEST_RESERVED5, DEVICETEST_RESERVED6, //50×Ö½Ú,
+ DEVICETEST_RESERVED7, DEVICETEST_RESERVED8, DEVICETEST_RESERVED9, DEVICETEST_RESERVED10, //51×Ö½Ú,
+ DEVICETEST_RESERVED11, DEVICETEST_RESERVED12, DEVICETEST_RESERVED13, DEVICETEST_RESERVED14, //52×Ö½Ú,
+ DEVICETEST_RESERVED15, DEVICETEST_RESERVED16, DEVICETEST_RESERVED17, DEVICETEST_RESERVED18, //53×Ö½Ú,
+
+ MAXAMTFALGS_NVPARAM = 799, // 200¸ö×Ö½Ú£¬Ò»¸ö×Ö½Ú4¸ö±ê־룬¹²¿É±íʾ0~799¸ö±ê־룬44~199×Ö½ÚÔ¤Áô
+} NvParam_AMTFlags;
+
+typedef enum
+{
+ T_INITIAL = 0, //BIT: 00
+ T_PASSED = 1, //BIT: 01
+ T_FAILED = 2, //BIT: 10
+ T_ERRORVALUE = 3
+} TestResultAMT;
+//} TestResult;
+
+/*****************************************************************************
+ * º¯ÊýÃû³Æ: zPS_NvAMTItemWrite
+ * ¹¦ÄÜÃèÊö: дһÏîNVÊý¾Ý
+ * ²ÎÊý˵Ã÷:
+ (IN)
+ nvParam: ¸ÃNVÏîÀàÐÍ
+ NvItemData: дÈëµÄÊý¾Ý
+ NvItemLen: Êý¾Ý³¤¶È
+ (OUT)
+ * ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+ * ÆäËü˵Ã÷:
+ *****************************************************************************/
+UINT32 zPS_NvAMTItemWrite(NvParam_AMT nvParam,UINT8 *NvItemData, UINT32 NvItemLen);
+
+/*****************************************************************************
+ * º¯ÊýÃû³Æ: zPS_NvAMTItemRead
+ * ¹¦ÄÜÃèÊö: ¶Á³öÒ»ÏîNVÊý¾Ý
+ * ²ÎÊý˵Ã÷:
+ (IN)
+ nvParam: ¸ÃNVÏîÀàÐÍ
+ NvItemData: ¶Á³öµÄÊý¾Ý
+ NvItemLen: Êý¾Ý³¤¶È
+ (OUT)
+ * ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+ * ÆäËü˵Ã÷:
+ *****************************************************************************/
+UINT32 zPS_NvAMTItemRead(NvParam_AMT nvParam,UINT8 *NvItemData, UINT32 NvItemLen);
+
+/*****************************************************************************
+ * º¯ÊýÃû³Æ: zPS_NvAMTFlagsItemWrite
+ * ¹¦ÄÜÃèÊö:дÉú²ú²âÊÔ±ê־λ
+ * ²ÎÊý˵Ã÷:
+ (IN)
+ nvParam: ¸ÃNVÏîÀàÐÍ
+ NvItemData: ´ýдµÄÊý¾Ý
+ (OUT)
+ * ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+ * ÆäËü˵Ã÷:
+ *****************************************************************************/
+UINT32 zPS_NvAMTFlagsItemWrite(NvParam_AMTFlags nvParam,UINT8 *NvItemData);
+
+/*****************************************************************************
+ * º¯ÊýÃû³Æ: zPS_NvAMFlagsTItemRead
+ * ¹¦ÄÜÃèÊö: ¶ÁÉú²ú²âÊÔ±ê־λ
+ * ²ÎÊý˵Ã÷:
+ (IN)
+ nvParam: ¸ÃNVÏîÀàÐÍ
+ NvItemData: ¶ÁÈ¡µÄÊý¾Ý
+ (OUT)
+ * ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+ * ÆäËü˵Ã÷:
+ *****************************************************************************/
+UINT32 zPS_NvAMFlagsTItemRead(NvParam_AMTFlags nvParam,UINT8 *NvItemData);
+
+/*****************************************************************************
+ * º¯ÊýÃû³Æ: zPS_GetAmtNvBandInfo
+ * ¹¦ÄÜÃèÊö:¶ÁÉú²ú²âÊÔƵ¶ÎÐÅÏ¢
+ * ²ÎÊý˵Ã÷:
+ (IN)
+ NvItemData ¶ÁÈ¡ÐÅÏ¢µÄ´æ·Åbuffer
+ (OUT)
+ * ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+ * ÆäËü˵Ã÷:
+ *****************************************************************************/
+UINT32 zPS_GetAmtNvBandInfo(UINT8 *NvItemData);
+#if 0
+/**************************************************************************
+* º¯ÊýÃû³Æ: zPS_LteCalibNvCheck
+* ¹¦ÄÜÃèÊö: ¼ì²éLTEУ׼NVÖÐÊÇ·ñ´æÔÚij¸öband£¬Èô²»´æÔÚ£¬Ôò½«Ö¸¶¨Æµ¶ÎÊý¾Ý¸´ÖÆÒ»·Ý
+* ²ÎÊý˵Ã÷:
+ (IN)
+ dest ´ý¼ì²éµÄÄ¿±êbandºÅ£¬·¶Î§1µ½128
+ src ÓÃÓÚ¸´ÖƵÄÔ´bandºÅ£¬·¶Î§1µ½128
+ read ·Ç0±íʾÖØжÁÈ¡Nandµ½Ram£¬0±íʾ²»ÖØжÁÈ¡Nandµ½Ram
+ write ·Ç0±íʾ½«ramÊý¾ÝдÈëNand£¬0±íʾ²»Ð´ÈëNand
+
+ (OUT)
+* ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+* ÆäËü˵Ã÷:
+**************************************************************************/
+UINT32 zPS_LteCalibNvCheck(UINT16 dest, UINT16 src, UINT16 read, UINT16 write);
+/*****************************************************************************
+ * º¯ÊýÃû³Æ: zPS_NvRoUserWrite
+ * ¹¦ÄÜÃèÊö: Óû§×Ô¶¨ÒåÇøÓòдº¯Êý
+ * ²ÎÊý˵Ã÷:
+ (IN)
+ dwStart : 0 ~ 1k
+ dwLen : 0 ~ 1k
+ from : ´ýдÈëµÄÊý¾Ý
+ (OUT)
+ * ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+ * ÆäËü˵Ã÷:
+ *****************************************************************************/
+SINT32 zPS_NvRoUserWrite(UINT32 dwStart, UINT32 dwLen, UINT8* from);
+
+/*****************************************************************************
+ * º¯ÊýÃû³Æ: zPS_NvRoUserRead
+ * ¹¦ÄÜÃèÊö: Óû§×Ô¶¨ÒåÇøÓò¶Áº¯Êý
+ * ²ÎÊý˵Ã÷:
+ (IN)
+ dwStart : 0 ~ 1k
+ dwLen : 0 ~ 1k
+ to : ·µ»ØµÄÊý¾Ý
+
+ (OUT)
+ * ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+ * ÆäËü˵Ã÷:
+ *****************************************************************************/
+SINT32 zPS_NvRoUserRead(UINT32 dwStart, UINT32 dwLen, UINT8* to);
+/*****************************************************************************
+ * º¯ÊýÃû³Æ: zPS_NvRoRefRead
+ * ¹¦ÄÜÃèÊö: ²Î¿¼Éè¼Æ×Ô¶¨ÒåÇøÓò¶Áº¯Êý
+ * ²ÎÊý˵Ã÷:
+ (IN)
+ dwStart : 0 ~ 1k
+ dwLen : 0 ~ 1k
+ to : ·µ»ØµÄÊý¾Ý
+
+ (OUT)
+ * ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+ * ÆäËü˵Ã÷:
+ *****************************************************************************/
+SINT32 zPS_NvRoRefRead(UINT32 dwStart, UINT32 dwLen, UINT8* to);
+/*****************************************************************************
+ * º¯ÊýÃû³Æ: zPS_NvRoRefWrite
+ * ¹¦ÄÜÃèÊö: ²Î¿¼Éè¼Æ×Ô¶¨ÒåÇøÓòдº¯Êý
+ * ²ÎÊý˵Ã÷:
+ (IN)
+ dwStart : 0 ~ 1k
+ dwLen : 0 ~ 1k
+ from : ´ýдÈëµÄÊý¾Ý
+ (OUT)
+ * ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+ * ÆäËü˵Ã÷:
+ *****************************************************************************/
+SINT32 zPS_NvRoRefWrite(UINT32 dwStart, UINT32 dwLen, UINT8* from);
+#endif
+/*****************************************************************************
+ * º¯ÊýÃû³Æ: zPs_NvCheckBandBitmap
+ * ¹¦ÄÜÃèÊö: ¼ì²éËùÓÐÖÆʽУ׼Êý¾Ý£¬Ñ°ÕÒ´æÔÚУ׼Êý¾ÝµÄËùÓÐband£¬²¢Ð´ÈëbitmapÖÐ
+ * ²ÎÊý˵Ã÷:
+ (IN)
+ NvItemData: ¶Á³öµÄÊý¾Ý
+ NvItemLen: Êý¾Ý³¤¶È
+
+ (OUT)
+ * ·µ »Ø Öµ: ³É¹¦·µ»ØZOSS_SUCCESS£»Ê§°Ü·µ»ØZOSS_ERROR
+ * ÆäËü˵Ã÷:
+ *****************************************************************************/
+UINT32 zPs_NvCheckBandBitmap(UINT8 *NvItemData, UINT32 NvItemLen);
+
+/*****************************************************************************
+ * º¯ÊýÃû³Æ£º zAmt_GetPublicKey
+ * ¹¦ÄÜÃèÊö£º ·µ»Ø¹«Ô¿
+ * ²ÎÊý˵Ã÷£º
+ pE(in/out): ²ÎÊýEÖ¸Õë
+ pELen(in/out): ²ÎÊýE³¤¶ÈÖ¸Õë
+ pN(in/out): ²ÎÊýNÖ¸Õë
+ pModulusLen(in/out): ²ÎÊýN³¤¶ÈÖ¸Õë
+ * ·µ »Ø Öµ£º³É¹¦·µ»Ø0£¬Ê§°Ü·µ»Ø-1
+ * ÆäËü˵Ã÷£º
+ *****************************************************************************/
+SINT32 zAmt_GetPublicKey(BYTE *pE, UINT32 *pELen, BYTE *pN, UINT32 *pModulusLen);
+
+/*****************************************************************************
+ * º¯ÊýÃû³Æ: zAmt_GetCommNvSizeByNvParam
+ * ¹¦ÄÜÃèÊö: »ñÈ¡comm nvÖÐÿ¸önvÏîµÄ´óС
+ * ²ÎÊý˵Ã÷:
+ (IN)
+ nvParam: comm nvÏî
+
+ (OUT)
+ nvsize
+ * ·µ »Ø Öµ: ³É¹¦·µ»ØÕæʵµÄnvsize£»Ê§°Ü·µ»Ø0
+ * ÆäËü˵Ã÷:
+ *****************************************************************************/
+UINT32 zAmt_GetCommNvSizeByNvParam(NvParam_AMT nvParam);
+
+#endif
+
diff --git a/pub/project/zx297520v3/include/nv/RONvParam_PS.h b/pub/project/zx297520v3/include/nv/RONvParam_PS.h
new file mode 100644
index 0000000..72650d0
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/RONvParam_PS.h
@@ -0,0 +1,76 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name: PubNvParam_PS.h
+ * File Mark:
+ * Description:
+
+ * Others:
+ * Version: v0.5
+ * Author:
+ * Date:
+ * History 1:
+ * Date: 2010.1.1
+ * Version:
+ * Author:luhuan
+ * Modification: 1¡¢Ôö¼ÓT_zPS_DEV_NV_MsInfo½á¹¹
+ * 2¡¢½«ÔÓнṹT_zPS_DEV_NV_ImeiºÍT_zPS_DEV_NV_MsInfoͳһºÏ²¢ÎªT_zPS_DEV_NV_PsData_Pub
+ * History 2:
+ * Date: 2010.1.27
+ * Version:
+ * Author:luhuan
+ * Modification: ¸ù¾ÝÉú²ú²âÊÔÐèÇó£¬ÒƳöÖظ´½á¹¹
+********************************************************************************/
+#ifndef _RONVPARAM_PS_H
+#define _RONVPARAM_PS_H
+
+
+#define ZPS_DEV_MSINFO_MAX_EQUIPNAME_LEN (BYTE)10
+
+typedef struct{
+ BYTE bEquipType; /********************************************************************************
+ ¹¦ÄÜ£ºÉ豸ÀàÐÍ
+ 01£ºWCDMA
+ 02: TD
+ 03: CDMA
+ 04: B3G
+ 05: WAT
+ 06: GSM
+ ³ö³§Öµ£º02
+ *********************************************************************************/
+ BYTE bSeqNum; /********************************************************************************
+ ¹¦ÄÜ£º ÐòÁкÅ
+ È¡Öµ·¶Î§£º0~255
+ ³ö³§Öµ£º1
+ *********************************************************************************/
+ BYTE abPadding1[2];/********************************************************************************
+ ¹¦ÄÜ£ºÌî³äλ
+ È¡Öµ·¶Î§£º0
+ ³ö³§Öµ£º0
+ *********************************************************************************/
+
+ BYTE abEquipName[ZPS_DEV_MSINFO_MAX_EQUIPNAME_LEN];
+ /********************************************************************************
+ ¹¦ÄÜ£º É豸ÐͺÅ
+ È¡Öµ·¶Î§£ºÈÎÒâ×Ö·û´®£¬ÒÔ'\0'±íʾ½áÊø
+ ³ö³§Öµ£ºÓɳö²ú³§É̾ö¶¨
+ *********************************************************************************/
+ BYTE abPadding2[2];/********************************************************************************
+ ¹¦ÄÜ£ºÌî³äλ
+ È¡Öµ·¶Î§£º0
+ ³ö³§Öµ£º0
+ *********************************************************************************/
+}T_zPS_DEV_NV_PsMsInfo;
+
+
+typedef struct {
+ T_zPS_DEV_NV_PsMsInfo tPsMsInfo; /********************************************************************************
+ ¹¦ÄÜ£ºÐÒéջʹÓõÄMobile StationÏà¹ØÐÅÏ¢
+ È¡Öµ·¶Î§£º²Î¼ûÄÚ²¿½á¹¹ËµÃ÷
+ ³ö³§Öµ£º²Î¼ûÄÚ²¿½á¹¹ËµÃ÷
+ *********************************************************************************/
+}T_zPS_DEV_NV_Data_Pub;
+
+#endif
+
+
diff --git a/pub/project/zx297520v3/include/nv/RWNvConfig.h b/pub/project/zx297520v3/include/nv/RWNvConfig.h
new file mode 100755
index 0000000..ad6bf7c
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/RWNvConfig.h
@@ -0,0 +1,316 @@
+/**************************************************************************
+*
+* Copyright (c) 2014 ZTE Corporation.
+*
+***************************************************************************
+* Ä£ ¿é Ãû :
+* ÎÄ ¼þ Ãû : RWNvConfig.h
+* Ïà¹ØÎļþ :
+* ʵÏÖ¹¦ÄÜ :
+* ×÷ Õß :
+* °æ ±¾ :
+* Íê³ÉÈÕÆÚ :
+* ÆäËü˵Ã÷ :
+**************************************************************************/
+
+/**************************************************************************
+* Ð޸ļǼ
+**************************************************************************/
+#ifndef _RWNVCONFIG_H
+#define _RWNVCONFIG_H
+
+#include "RONvConfig.h"
+
+/****************************************************************************
+ rwo area
+****************************************************************************/
+
+#define OS_FLASH_RWO_OFFSET_FROM_NV (OS_FLASH_ROW_OFFSET_FROM_NV + OS_FLASH_ROW_NVRAM_SIZE) /* ÏÞÖƶÁдÇøÆ«ÒÆ */
+#define OS_FLASH_RWO_NVRAM_SIZE (512 * 1024)
+
+/***************************
+ AMT user config 42KB : LTE 10KB
+***************************/
+#define OS_FLASH_AMT_RW_USER_LTE_OFFSET_FROM_NV OS_FLASH_RWO_OFFSET_FROM_NV
+#define OS_FLASH_AMT_RW_USER_LTE_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_RW_USER_LTE_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_RW_USER_LTE_SIZE (10 * 1024)
+
+/***************************
+ AMT user config 42KB: TDS 3KB
+***************************/
+#define OS_FLASH_AMT_RW_USER_TDS_OFFSET_FROM_NV (OS_FLASH_AMT_RW_USER_LTE_OFFSET_FROM_NV + OS_FLASH_AMT_RW_USER_LTE_SIZE)
+#define OS_FLASH_AMT_RW_USER_TDS_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_RW_USER_TDS_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_RW_USER_TDS_SIZE (3 * 1024)
+
+/***************************
+ AMT user config 42KB:GGE 7KB
+***************************/
+#define OS_FLASH_AMT_RW_USER_GGE_OFFSET_FROM_NV (OS_FLASH_AMT_RW_USER_TDS_OFFSET_FROM_NV + OS_FLASH_AMT_RW_USER_TDS_SIZE)
+#define OS_FLASH_AMT_RW_USER_GGE_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_RW_USER_GGE_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_RW_USER_GGE_SIZE (7 * 1024)
+
+/***************************
+ AMT user config 42KB: WCDMA 10KB
+***************************/
+#define OS_FLASH_AMT_RW_USER_WCDMA_OFFSET_FROM_NV (OS_FLASH_AMT_RW_USER_GGE_OFFSET_FROM_NV + OS_FLASH_AMT_RW_USER_GGE_SIZE)
+#define OS_FLASH_AMT_RW_USER_WCDMA_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_RW_USER_WCDMA_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_RW_USER_WCDMA_SIZE (10 * 1024)
+
+/***************************
+ AMT user config 42KB: LTEA 27KB
+***************************/
+#define OS_FLASH_AMT_RW_USER_LTEA_OFFSET_FROM_NV (OS_FLASH_AMT_RW_USER_WCDMA_OFFSET_FROM_NV + OS_FLASH_AMT_RW_USER_WCDMA_SIZE)
+#define OS_FLASH_AMT_RW_USER_LTEA_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_AMT_RW_USER_LTEA_OFFSET_FROM_NV)
+#define OS_FLASH_AMT_RW_USER_LTEA_SIZE (27 * 1024)
+
+/***************************
+ LTE physical area config 0KB
+***************************/
+#define OS_FLASH_LTEPHY_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_AMT_RW_USER_LTEA_OFFSET_FROM_NV + OS_FLASH_AMT_RW_USER_LTEA_SIZE)
+#define OS_FLASH_LTEPHY_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_LTEPHY_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_LTEPHY_RW_NONFAC_SIZE (0 * 1024)
+
+/***************************
+ TDS physical area config 2KB
+***************************/
+#define OS_FLASH_TDPHY_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_LTEPHY_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_LTEPHY_RW_NONFAC_SIZE)
+#define OS_FLASH_TDPHY_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_TDPHY_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_TDPHY_RW_NONFAC_SIZE (2 * 1024)
+
+/***************************
+ GSM l1g area config 14KB
+***************************/
+#define OS_FLASH_GSML1G_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_TDPHY_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_TDPHY_RW_NONFAC_SIZE)
+#define OS_FLASH_GSML1G_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_GSML1G_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_GSML1G_RW_NONFAC_SIZE (14 * 1024)
+
+/***************************
+ WCDMA physical area config 2KB
+***************************/
+#define OS_FLASH_WCDMAPHY_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_GSML1G_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_GSML1G_RW_NONFAC_SIZE)
+#define OS_FLASH_WCDMAPHY_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_WCDMAPHY_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_WCDMAPHY_RW_NONFAC_SIZE (2 * 1024)
+
+/***************************
+ LTEA physical area config 16KB
+***************************/
+#define OS_FLASH_LTEAPHY_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_WCDMAPHY_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_WCDMAPHY_RW_NONFAC_SIZE)
+#define OS_FLASH_LTEAPHY_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_LTEAPHY_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_LTEAPHY_RW_NONFAC_SIZE (16 * 1024)
+
+/***************************
+ zx_rf m0 config 20KB
+***************************/
+#define OS_FLASH_ZXRFM0_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_LTEAPHY_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_LTEAPHY_RW_NONFAC_SIZE)
+#define OS_FLASH_ZXRFM0_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_ZXRFM0_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_ZXRFM0_RW_NONFAC_SIZE (20 * 1024)
+
+/***************************
+ tx event table 64KB
+***************************/
+#define OS_FLASH_TXETAB_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_ZXRFM0_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_ZXRFM0_RW_NONFAC_SIZE)
+#define OS_FLASH_TXETAB_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_TXETAB_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_TXETAB_RW_NONFAC_SIZE (64 * 1024)
+
+/***************************
+ phycom area 2KB
+***************************/
+#define OS_FLASH_RFCOM_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_TXETAB_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_TXETAB_RW_NONFAC_SIZE)
+#define OS_FLASH_RFCOM_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_RFCOM_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_RFCOM_RW_NONFAC_SIZE (2 * 1024)
+
+/***************************
+ rwo area reserved 335KB
+***************************/
+#define OS_FLASH_RWO_RESERVED_OFFSET_FROM_NV (OS_FLASH_RFCOM_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_RFCOM_RW_NONFAC_SIZE)
+#define OS_FLASH_RWO_RESERVED_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_RWO_RESERVED_OFFSET_FROM_NV)
+#define OS_FLASH_RWO_RESERVED_SIZE (335 * 1024)
+
+/****************************************************************************
+ rw area
+****************************************************************************/
+#define OS_FLASH_RW_OFFSET_FROM_NV (OS_FLASH_RWO_OFFSET_FROM_NV + OS_FLASH_RWO_NVRAM_SIZE) /* ¶ÁдÇøÆ«ÒÆ */
+#define OS_FLASH_RW_NVRAM_SIZE (768 * 1024)
+
+/***************************
+ TSP area config 2KB
+***************************/
+#define OS_FLASH_TSP_RW_NONFAC_OFFSET_FROM_NV OS_FLASH_RW_OFFSET_FROM_NV
+#define OS_FLASH_TSP_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_TSP_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_TSP_RW_NONFAC_SIZE (2 * 1024)
+#define OS_FLASH_TSP_RW_NONFAC_AT_MODE_ADDR (OS_FLASH_TSP_RW_NONFAC_BASE_ADDR + 1024)
+
+
+/***************************
+ ATI area config 2KB
+***************************/
+#define OS_FLASH_ATI_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_TSP_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_TSP_RW_NONFAC_SIZE)
+#define OS_FLASH_ATI_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_ATI_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_ATI_RW_NONFAC_SIZE (2 * 1024)
+
+/***************************
+ at config setting 1KB
+***************************/
+#define OS_FLASH_ATCFG_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_ATI_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_ATI_RW_NONFAC_SIZE)
+#define OS_FLASH_ATCFG_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_ATCFG_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_ATCFG_RW_NONFAC_SIZE (1 * 1024)
+
+/***************************
+ phy config 2KB
+***************************/
+#define OS_FLASH_PHYCFG_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_ATCFG_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_ATCFG_RW_NONFAC_SIZE)
+#define OS_FLASH_PHYCFG_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_PHYCFG_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_PHYCFG_RW_NONFAC_SIZE (2 * 1024)
+
+/***************************
+volte area config 1KB
+***************************/
+#define OS_FLASH_VOLTE_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_PHYCFG_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_PHYCFG_RW_NONFAC_SIZE)
+#define OS_FLASH_VOLTE_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_VOLTE_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_VOLTE_RW_NONFAC_SIZE (1 * 1024)
+
+/***************************
+ ps area config 64KB
+***************************/
+#define OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_VOLTE_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_VOLTE_RW_NONFAC_SIZE)
+#define OS_FLASH_PS_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_PS_RW_NONFAC_SIZE (64 * 1024)
+
+/***************************
+ driver area config 16KB
+***************************/
+#define OS_FLASH_DRV_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_PS_RW_NONFAC_SIZE)
+#define OS_FLASH_DRV_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_DRV_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_DRV_RW_NONFAC_SIZE (16 * 1024)
+
+/***************************
+plat area config 0KB
+***************************/
+#define OS_FLASH_PLAT_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_DRV_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_DRV_RW_NONFAC_SIZE)
+#define OS_FLASH_PLAT_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_PLAT_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_PLAT_RW_NONFAC_SIZE (0 * 1024)
+
+/***************************
+user area config 0KB
+***************************/
+#define OS_FLASH_USER_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_PLAT_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_PLAT_RW_NONFAC_SIZE)
+#define OS_FLASH_USER_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_USER_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_USER_RW_NONFAC_SIZE 0
+
+/***************************
+ voice area config 64KB
+***************************/
+#define OS_FLASH_VOICE_RW_NONFAC_OFFSET_FROM_NV (OS_FLASH_USER_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_USER_RW_NONFAC_SIZE)
+#define OS_FLASH_VOICE_RW_NONFAC_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_VOICE_RW_NONFAC_OFFSET_FROM_NV)
+#define OS_FLASH_VOICE_RW_NONFAC_SIZE (64 * 1024)
+
+/******************************
+ ref RWdate area 16KB
+******************************/
+#define OS_FLASH_REF_DESIGN_RW_OFFSET_FROM_NV (OS_FLASH_VOICE_RW_NONFAC_OFFSET_FROM_NV + OS_FLASH_VOICE_RW_NONFAC_SIZE)
+#define OS_FLASH_REF_DESIGN_RW_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_REF_DESIGN_RW_OFFSET_FROM_NV)
+#define OS_FLASH_REF_DESIGN_RW_SIZE (16 * 1024)
+
+/******************************
+ reserved RWdate area config 600KB
+******************************/
+#define OS_FLASH_RW_RESERVED_OFFSET_FROM_NV (OS_FLASH_REF_DESIGN_RW_OFFSET_FROM_NV + OS_FLASH_REF_DESIGN_RW_SIZE)
+#define OS_FLASH_RW_RESERVED_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_RW_RESERVED_OFFSET_FROM_NV)
+#define OS_FLASH_RW_RESERVED_SIZE (600 * 1024)
+
+/******************************
+ nv flag area
+******************************/
+#define OS_FLASH_FLAG_NVRAM_BASE_ADD (OS_FLASH_RW_OFFSET_FROM_NV + OS_FLASH_RW_NVRAM_SIZE)
+#define OS_FLASH_FLAG_NVRAM_SIZE (1024 * 1024)
+
+/******************************
+ work area symbol 1 BYTE
+*******************************/
+#define OS_FLASH_WORK_AREA_SYMBOL_BASE_ADDR (OS_FLASH_FLAG_NVRAM_BASE_ADD)
+#define OS_FLASH_WORK_AREA_SYMBOL_SIZE (256 * 1024)
+
+/******************************
+ backup area symbol 1 BYTE
+******************************/
+#define OS_FLASH_BACKUP_AREA_SYMBOL_BASE_ADDR (OS_FLASH_WORK_AREA_SYMBOL_BASE_ADDR+OS_FLASH_WORK_AREA_SYMBOL_SIZE)
+#define OS_FLASH_BACKUP_AREA_SYMBOL_SIZE (256 * 1024)
+
+/******************************
+ factory area symbol 1 BYTE
+******************************/
+#define OS_FLASH_FACTORY_AREA_SYMBOL_BASE_ADDR (OS_FLASH_BACKUP_AREA_SYMBOL_BASE_ADDR+OS_FLASH_BACKUP_AREA_SYMBOL_SIZE)
+#define OS_FLASH_FACTORY_AREA_SYMBOL_SIZE (256 * 1024)
+
+/******************************
+ reset factory symbol 1 BYTE
+******************************/
+#define OS_FLASH_RESET_FACTORY_SYMBOL_BASE_ADDR (OS_FLASH_FACTORY_AREA_SYMBOL_BASE_ADDR+OS_FLASH_FACTORY_AREA_SYMBOL_SIZE)
+#define OS_FLASH_RESET_FACTORY_SYMBOL_SIZE (256 * 1024)
+
+/******************************
+ RWdate BACKUP area 0.75M
+******************************/
+#define OS_FLASH_RW_BACKUP_NVRAM_BASE_ADDR (OS_FLASH_FLAG_NVRAM_BASE_ADD + OS_FLASH_FLAG_NVRAM_SIZE)
+#define OS_FLASH_RW_BACKUP_NVRAM_SIZE OS_FLASH_RW_NVRAM_SIZE /*NV RW±¸·ÝÇø×Ü´óС768K*/
+
+#if 1 /**/
+/***************************
+ SM MEMORY bakeup RWvate area config
+***************************/
+#define OS_FLASH_RW_SM_BAKEUP_OFFSET_FROM_NV (OS_FLASH_RW_BACKUP_NVRAM_BASE_ADDR + OS_FLASH_RW_BACKUP_NVRAM_SIZE)
+#define OS_FLASH_RW_SM_BAKEUP_BASE_ADDR (OS_FLASH_NV_PARTITION_BASE_ADDR + OS_FLASH_RW_SM_BAKEUP_OFFSET_FROM_NV)
+#define OS_FLASH_RW_SM_BAKEUP_SIZE 0
+#endif
+
+/******************************
+ factory setting nvram area 1.5M
+******************************/
+#define OS_FLASH_FACTORY_NVRAM_BASE_ADDR 0 /* ³ö³§ÇøÊǵ¥¶ÀµÄÒ»¸ö·ÖÇønvfac£¬½èÖúÔÚ´ËÎļþ¶¨Òå */
+#define OS_FLASH_FACTORY_NVRAM_SIZE (512 * 1024) /* 0.5M£¬ÇëÈ·±£nvrwµÄ¹¤×÷ÇøʹÓû®·Ö²»³¬¹ý0.5M */
+
+/******************************
+ Reserved NV Head addr
+******************************/
+#define PS_SELLSTAT_NVHEAD_OFFSET_FROM_NV (OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV + 4)
+#define PS_PLMNCFG_NVHEAD_OFFSET_FROM_NV (OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV + 304)
+#define PS_UEINFO_NVHEAD_OFFSET_FROM_NV (OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV + 20320)
+#define PS_SIGNALBOX_NVHEAD_OFFSET_FROM_NV (OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV + 27448)
+#define PS_UECAPA_NVHEAD_OFFSET_FROM_NV (OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV + 27492)
+#define PS_USERSET_NVHEAD_OFFSET_FROM_NV (OS_FLASH_PS_RW_NONFAC_OFFSET_FROM_NV + 38136)
+
+#define REF_DESIGN_USER_OFFSET_FROM_NV (OS_FLASH_REF_DESIGN_RW_OFFSET_FROM_NV + 1262)
+
+/******************************
+ vsim area
+******************************/
+#define OS_FLASH_VSIM_WORK_AREA_BASE_ADDR 0
+#define OS_FLASH_VSIM_WORK_AREA_SIZE (256 * 1024)
+
+#define OS_FLASH_VSIM_RESERVED0_BASE_ADDR (OS_FLASH_VSIM_WORK_AREA_BASE_ADDR + OS_FLASH_VSIM_WORK_AREA_SIZE)
+#define OS_FLASH_VSIM_RESERVED0_SIZE (256 * 1024)
+
+#define OS_FLASH_VSIM_BACKUP_AREA_BASE_ADDR (OS_FLASH_VSIM_RESERVED0_BASE_ADDR + OS_FLASH_VSIM_RESERVED0_SIZE)
+#define OS_FLASH_VSIM_BACKUP_AREA_SIZE OS_FLASH_VSIM_WORK_AREA_SIZE
+
+#define OS_FLASH_VSIM_RESERVED1_BASE_ADDR (OS_FLASH_VSIM_BACKUP_AREA_BASE_ADDR + OS_FLASH_VSIM_BACKUP_AREA_SIZE)
+#define OS_FLASH_VSIM_RESERVED1_SIZE (256 * 1024)
+
+#define OS_FLASH_VSIM_WORK_AREA_SYMBOL_BASE_ADDR (OS_FLASH_VSIM_RESERVED1_BASE_ADDR + OS_FLASH_VSIM_RESERVED1_SIZE)
+#define OS_FLASH_VSIM_WORK_AREA_SYMBOL_SIZE (256 * 1024)
+
+#define OS_FLASH_VSIM_BACKUP_AREA_SYMBOL_BASE_ADDR (OS_FLASH_VSIM_WORK_AREA_SYMBOL_BASE_ADDR + OS_FLASH_VSIM_WORK_AREA_SYMBOL_SIZE)
+#define OS_FLASH_VSIM_BACKUP_AREA_SYMBOL_SIZE (256 * 1024)
+
+#define OS_FLASH_VSIM_FAC_AREA_SYMBOL_BASE_ADDR (OS_FLASH_VSIM_BACKUP_AREA_SYMBOL_BASE_ADDR + OS_FLASH_VSIM_BACKUP_AREA_SYMBOL_SIZE)
+#define OS_FLASH_VSIM_FAC_AREA_SYMBOL_SIZE (256 * 1024)
+
+#define OS_FLASH_VSIM_FAC_AREA_BASE_ADDR 0
+#define OS_FLASH_VSIM_FAC_AREA_SIZE OS_FLASH_VSIM_WORK_AREA_SIZE
+
+/****************************************************************************
+ End
+****************************************************************************/
+
+#endif
+
diff --git a/pub/project/zx297520v3/include/nv/RWNvParam.h b/pub/project/zx297520v3/include/nv/RWNvParam.h
new file mode 100644
index 0000000..4910fcc
--- /dev/null
+++ b/pub/project/zx297520v3/include/nv/RWNvParam.h
@@ -0,0 +1,220 @@
+/*******************************************************************************
+ * Copyright (C) 2007, ZTE Corporation.
+ *
+ * File Name:prinvparam.h
+ * File Mark:
+ * Description:private config NV parameters
+
+ * Others:
+ * Version: v0.1
+ * Author: xuxingkui
+ * Date: 2009-09-28
+ * History 1:
+ * Date: 2009-11-24
+ * Version:
+ * Author:
+ * Modification:
+ *
+ * History 2:
+********************************************************************************/
+
+#ifndef _RWNVPARM_H
+#define _RWNVPARM_H
+
+#include "NvParam_PS.h"
+#include "NvParam_drv.h"
+#include "NvParam_ati.h"
+#include "NvParam_AMT.h"
+#include "NvParam_tdl1.h"
+#include "NvParam_gsml1.h"
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+
+/****************************************************************************
+* Local Macros
+****************************************************************************/
+
+/****************************************************************************
+* AMT
+****************************************************************************/
+/***********************************
+AMT leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_AMTParam
+{
+
+}T_ZFacPri_AMTParam;
+
+/***********************************
+AMT none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_AMTParam
+{
+ stTD st_td;
+}T_ZNonFacPri_AMTParam;
+
+/****************************************************************************
+* ATI
+****************************************************************************/
+/***********************************
+ATI leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_ATIParam
+{
+
+}T_ZFacPri_ATIParam;
+
+/***********************************
+ATI none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_ATIParam
+{
+ T_ZAt2_NvParam at2_nvParam;
+}T_ZNonFacPri_ATIParam;
+
+/****************************************************************************
+* DIVER
+****************************************************************************/
+/***********************************
+driver leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_DrvParam
+{
+
+}T_ZFacPri_DrvParam;
+
+/***********************************
+driver none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_DrvParam
+{
+ aud_eep_static_type g_aud_eep_static_type;
+}T_ZNonFacPri_DrvParam;
+
+/****************************************************************************
+* TdPhy
+****************************************************************************/
+/***********************************
+td physical leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_TdPhyParam
+{
+
+}T_ZFacPri_TdPhyParam;
+
+/***********************************
+td physical none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_TdPhyParam
+{
+ T_TD_L1_NV td_l1_nv;
+}T_ZNonFacPri_TdPhyParam;
+
+/****************************************************************************
+* GSM L1g
+****************************************************************************/
+/***********************************
+GSM L1g leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_GsmL1gParam
+{
+
+}T_ZFacPri_GsmL1gParam;
+
+/***********************************
+GSM L1g none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_GsmL1gParam
+{
+ L1G_EEP_static_type l1g_eep_static_type;
+}T_ZNonFacPri_GsmL1gParam;
+
+/****************************************************************************
+* PS
+****************************************************************************/
+/***********************************
+ps leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_PsParam
+{
+
+}T_ZFacPri_PsParam;
+
+/***********************************
+ps none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_PsParam
+{
+ T_zPS_DEV_NV_PsData psData;
+}T_ZNonFacPri_PsParam;
+
+/****************************************************************************
+* PLAT
+****************************************************************************/
+/***********************************
+plat leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_PlatParam
+{
+
+}T_ZFacPri_PlatParam;
+
+/***********************************
+plat none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_PlatParam
+{
+
+}T_ZNonFacPri_PlatParam;
+
+/****************************************************************************
+* USER
+****************************************************************************/
+/***********************************
+USER leave factory parmameters
+************************************/
+typedef struct _tagZFacPri_UserParam
+{
+
+}T_ZFacPri_UserParam;
+
+/***********************************
+USER none leave factory parmameters
+************************************/
+typedef struct _tagNonFacPri_UserParam
+{
+
+}T_ZNonFacPri_UserParam;
+
+/****************************************************************************
+* TSP
+****************************************************************************/
+typedef struct _tagZPri_TspParam
+{
+ /* leave factory parmameters */
+ T_ZFacPri_AMTParam gFacPriAMTParam; /* AMT */
+ T_ZFacPri_ATIParam gFacPriATIParam; /* ATI */
+ T_ZFacPri_DrvParam gFacPriDrvParam; /* DRIVER */
+ T_ZFacPri_TdPhyParam gFacPriTdPhyParam; /* TD PHY */
+ T_ZFacPri_GsmL1gParam gFacPriGsmL1gParam; /* GSM L1G */
+ T_ZFacPri_PsParam gFacPriPsParam; /* PS */
+ T_ZFacPri_PlatParam gFacPriPlatParam; /* PLAT */
+ T_ZFacPri_UserParam gFacPriUserParam; /* USER */
+
+ /* none leave factory parmameters */
+ T_ZNonFacPri_AMTParam gNonFacPriAMTParam; /* AMT */
+ T_ZNonFacPri_ATIParam gNonFacPriATIParam; /* ATI */
+ T_ZNonFacPri_DrvParam gNonFacPriDrvParam; /* DRIVER */
+ T_ZNonFacPri_TdPhyParam gNonFacPriTdPhyParam; /* TD PHY */
+ T_ZNonFacPri_GsmL1gParam gNonFacPriGsmL1gParam; /* GSM L1G */
+ T_ZNonFacPri_PsParam gNonFacPriPsParam; /* PS */
+ T_ZNonFacPri_PlatParam gNonFacPriPlatParam; /* PLAT */
+ T_ZNonFacPri_UserParam gNonFacPriUserParam; /* USER */
+}T_ZPri_TspParam;
+
+#endif
+
+
+
diff --git a/pub/project/zx297520v3/include/ps_phy/.gitignore b/pub/project/zx297520v3/include/ps_phy/.gitignore
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/pub/project/zx297520v3/include/ps_phy/.gitignore
diff --git a/pub/project/zx297520v3/include/psm/psm_ram_config_7520v3.h b/pub/project/zx297520v3/include/psm/psm_ram_config_7520v3.h
new file mode 100644
index 0000000..1927198
--- /dev/null
+++ b/pub/project/zx297520v3/include/psm/psm_ram_config_7520v3.h
@@ -0,0 +1,428 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: psm_ram_config_7520v3.h
+* Îļþ±êʶ: psm_ram_config_7520v3.h
+* ÄÚÈÝÕªÒª: zx297520v3 оƬƽ̨ʡµçµØÖ·ÅäÖÃÍ·Îļþ
+* ʹÓ÷½·¨: #include "ram_config.h"
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2016/12/23 V1.0 Create ÀîÖ¾²ý ´´½¨
+*
+*******************************************************************************/
+
+#ifndef _PSM_RAM_CONFIG_7520V3_H
+#define _PSM_RAM_CONFIG_7520V3_H
+
+#ifndef _RAM_CONFIG_H
+#error "Don't include psm_ram_config_7520v3.h directly, include ram_config.h instead!"
+#endif
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+//#include "oss_api.h"
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+/*IRAM »ùÖ·¶¨Òå*/
+//#define IRAM0_BASE_ADDR ((0x82000000)>>1) /*512KB*/
+//#define IRAM1_BASE_ADDR ((0x00100000)>>1) /* 64KB*/
+//#define IRAM2_BASE_ADDR ((0x00080000)>>1) /* 16KB*/
+
+/*******************************************************************************
+* LPM»ùµØÖ· *
+*******************************************************************************/
+#ifdef DDR_BASE_ADDR_LINUX_VA
+#define GSM_LPM_BASE_ADDR ((unsigned long)ZX_LPM_BASE) //GSM LPM¸ú×Ù»½Ðѹ¦ÄÜ¡¢¶àÄ£¿ìÕÕ¹¦ÄÜ
+#define LTE_LPM_BASE_ADDR ((unsigned long)ZX_LPM_BASE + 0x200) //LTE LPM¸ú×Ù»½Ðѹ¦ÄÜ
+#define TDS_LPM_BASE_ADDR ((unsigned long)ZX_LPM_BASE + 0x400) //TDS LPM¸ú×Ù»½Ðѹ¦ÄÜ
+#define TDS_PSLPM_BASE_ADDR ((unsigned long)ZX_LPM_BASE + 0x500) //TDS LPM×ÓÖ¡ÖжϹ¦ÄÜ
+#define W_LPM_BASE_ADDR ((unsigned long)ZX_LPM_BASE + 0x600) //W LPM¸ú×Ù»½Ðѹ¦ÄÜ
+#else
+#define GSM_LPM_BASE_ADDR (0x00134000) //GSM LPM¸ú×Ù»½Ðѹ¦ÄÜ¡¢¶àÄ£¿ìÕÕ¹¦ÄÜ
+#define LTE_LPM_BASE_ADDR (0x00134200) //LTE LPM¸ú×Ù»½Ðѹ¦ÄÜ
+#define TDS_LPM_BASE_ADDR (0x00134400) //TDS LPM¸ú×Ù»½Ðѹ¦ÄÜ
+#define TDS_PSLPM_BASE_ADDR (0x00134500) //TDS LPM×ÓÖ¡ÖжϹ¦ÄÜ
+#define W_LPM_BASE_ADDR (0x00134600) //W LPM¸ú×Ù»½Ðѹ¦ÄÜ
+#endif
+
+/**************************************************************************
+ Ê¡µçIRAM1½Ó¿Ú¶¨Òå
+|----------------|-------------|-------------------|---------------|------------|----------------|
+|PS¶Ïµç±£´æ |Ê¡µç±êÖ¾|ZSP880¶Ïµç±£´æ |PSCPU ramlog | M0 |AP¶Ïµç±£´æ |
+|0x00100000
+ |0x00101000
+ |0x00101400
+ |0x00101800
+ |0x00101C00
+ |0x00102000
+|--------4K-----|-----1K------|---------1K---------|-----1K-------|-----1K------|-----4K--------|
+
+ÉϱíΪA53 µÄµØÖ··ÖÅ䣬ZSP880 µÄÓ²¼þµØÖ·¸úA53 Ò»Ñù£¬
+Èí¼þµØÖ·ÊÇÓ²¼þµØÖ·³ýÒÔ2
+**************************************************************************/
+
+/* IRAM1 ¶Î»ùµØÖ· */
+#ifdef DDR_BASE_ADDR_LINUX_VA
+#define IRAM1_R7_PSM_USE_BASE_ADDR ((unsigned long)ZX_IRAM1_BASE)
+#define IRAM1_PSM_FLG_CTRL_BASE_ADDR ((unsigned long)ZX_IRAM1_BASE + 0x1000)
+#define IRAM1_ZSP_PSM_USE_BASE_ADDR ((unsigned long)ZX_IRAM1_BASE + 0x1400)
+#define IRAM1_R7_RAMLOG_BASE_ADDR ((unsigned long)ZX_IRAM1_BASE + 0x1800)
+#define IRAM1_M0_PSM_USE_BASE_ADDR ((unsigned long)ZX_IRAM1_BASE + 0x1c00)
+#define IRAM1_A9_PSM_USE_BASE_ADDR ((unsigned long)ZX_IRAM1_BASE + 0x2000)
+#else
+#define IRAM1_R7_PSM_USE_BASE_ADDR (0x00100000>>CPU_SHIFT)
+#define IRAM1_PSM_FLG_CTRL_BASE_ADDR (0x00101000>>CPU_SHIFT)
+#define IRAM1_ZSP_PSM_USE_BASE_ADDR (0x00101400>>CPU_SHIFT)
+#define IRAM1_R7_RAMLOG_BASE_ADDR (0x00101800>>CPU_SHIFT)
+#define IRAM1_M0_PSM_USE_BASE_ADDR (0x00101c00>>CPU_SHIFT)
+#define IRAM1_A9_PSM_USE_BASE_ADDR (0x00102000>>CPU_SHIFT)
+#endif
+
+#define IRAM1_PSCPU_PSM_USE_BASE_ADDR IRAM1_R7_PSM_USE_BASE_ADDR
+#define IRAM1_PSCPU_RAMLOG_BASE_ADDR IRAM1_R7_RAMLOG_BASE_ADDR
+#define IRAM1_APCPU_PSM_USE_BASE_ADDR IRAM1_A9_PSM_USE_BASE_ADDR
+
+
+/* IRAM1 Ê¡µç±êÖ¾ */
+#define TD_SLEEP_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR) //TDÎïÀí²ã˯Ãß״̬£¬Ð´1Ϊ˯Ãߣ¬0Ϊ¹¤×÷״̬
+#define TD_CAMPON_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x4>>CPU_SHIFT)) //TDפÁô±êÖ¾£¬Ð´1ΪפÁô£¬0ΪפÁôʧ°Ü
+#define TDPHY_CONNECT_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x8>>CPU_SHIFT)) //LPM×ÓÖ¡ÖжÏʱ¿ÌµãNTʱ¼äά»¤²»Á˵ÄÎÊÌâ¹æ±ÜʹÓõ½µÄ±êÖ¾
+#define TD_WRITE_DPRAM_SFN_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0xC>>CPU_SHIFT)) //TDÏòDPRAMÌîдÍê×ÓÖ¡ºÅ±êÖ¾
+
+#define W_SLEEP_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x10>>CPU_SHIFT)) //LTEÎïÀí²ã˯Ãß״̬£¬Ð´1Ϊ˯Ãߣ¬0Ϊ¹¤×÷״̬
+#define W_CAMPON_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x14>>CPU_SHIFT)) //LTEפÁô±êÖ¾£¬Ð´1ΪפÁô£¬0ΪפÁôʧ°Ü
+#define WPHY_CONNECT_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x18>>CPU_SHIFT)) //LTE/TD¸¨Ä£Ê½WÁ¬½Ó̬ÏÂÔØËÀ»úÎÊÌâ¹æ±ÜʹÓõ½µÄWÁ¬½Ó̬±êÖ¾
+#define W_WRITE_DPRAM_SFN_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x1C>>CPU_SHIFT)) //WÏòDPRAMÌîдÍê×ÓÖ¡ºÅ±êÖ¾,±£Áô£¬²»ÓÃ
+
+#define LTE_SLEEP_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x20>>CPU_SHIFT)) //LTEÎïÀí²ã˯Ãß״̬£¬Ð´1Ϊ˯Ãߣ¬0Ϊ¹¤×÷״̬
+#define LTE_CAMPON_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x24>>CPU_SHIFT)) //LTEפÁô±êÖ¾£¬Ð´1ΪפÁô£¬0ΪפÁôʧ°Ü
+#define LTEPHY_CONNECT_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x28>>CPU_SHIFT)) //TD/W¸¨Ä£Ê½LTEÁ¬½Ó̬ÏÂÔØËÀ»úÎÊÌâ¹æ±ÜʹÓõ½µÄLTEÁ¬½Ó̬±êÖ¾
+#define LTE_WRITE_DPRAM_SFN_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x2C>>CPU_SHIFT)) //LTEÏòDPRAMÌîдÍê×ÓÖ¡ºÅ±êÖ¾,±£Áô£¬²»ÓÃ
+
+#define CPU_PS_SLEEP_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x30>>CPU_SHIFT)) //CPU_PS˯Ãß±êÖ¾£¬psд1Ϊ˯Ãߣ¬Ð´0Ϊ¹¤×÷£¬ÓÃÓÚÎïÀí²ã·¢ICP¸øÐÒéÕ»£¬ÎïÀí²ã²éѯCPU_PSµÄ˯Ãß״̬¡£
+#define CPU_PHY_SLEEP_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x34>>CPU_SHIFT)) //Ô¤Áô£ºCPU_PHYºË˯Ãß״̬£¬Ð´1Ϊ˯Ãߣ¬Ð´0Ϊ¹¤×÷
+#define IRAT_GAP_REPORT_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x38>>CPU_SHIFT)) //20msÎÊÌâÓÅ»¯
+
+//TDÉϱ¨GAPºóLPM×ÓÖ¡ÖжÏʱÐ軽ÐÑGSM£¬·ÀÖ¹GSM˯Ãß̬PSµ÷GSM²âÁ¿Ê±Ã»Óл½ÐÑGSM
+#define TD_REPORT_GAP_WAKEUP_GSM_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x3C>>CPU_SHIFT))
+
+//»½ÐÑLTEµÄICPµ½À´ºóPHY»¹´¦ÓÚÏÖ³¡»Ö¸´Ê±ÎÞ·¨·¢ICP»½ÐÑTD£¬ÓÉLTE¼ì²âµ½´Ë±ê־ʱÊÍ·ÅÊ¡µç½ø³ÌÐźÅÁ¿
+#define ICP_WAKEUP_TD_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x40>>CPU_SHIFT))
+//»½ÐÑTDµÄICPµ½À´ºóPHY»¹´¦ÓÚÏÖ³¡»Ö¸´Ê±ÎÞ·¨·¢ICP»½ÐÑW£¬ÓÉLTE¼ì²âµ÷W½Ó¿Ú¼ì²âµ½´ËÇé¿öÖõĵ÷ÊÔ±êÖ¾
+#define ICP_WAKEUP_W_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x44>>CPU_SHIFT))
+//»½ÐÑTDµÄICPµ½À´ºóPHY»¹´¦ÓÚÏÖ³¡»Ö¸´Ê±ÎÞ·¨·¢ICP»½ÐÑLTE£¬ÓÉTD/W¼ì²âµ÷LTE½Ó¿Ú¼ì²âµ½´ËÇé¿öÖõĵ÷ÊÔ±êÖ¾
+#define ICP_WAKEUP_LTE_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x48>>CPU_SHIFT))
+
+//W DOFFÐÅϢдÈëIRAM£¬¹©ARMPS¼ÆËãRTCFN
+#define W_TPU_DOFF_FOR_RTCFN_CALC_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x4C>>CPU_SHIFT))
+
+//
+#define LTE_RFC_EVENT_TABLE_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x50>>CPU_SHIFT))
+
+//zsp½øsleepÆÚ¼äÖñêÖ¾R7µÈ20clk·¢ICP
+#define ZSP_SLEEP_R7DELAYICP_FLG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x54>>CPU_SHIFT))
+
+//GSM±êÖ¾
+#define GSM_SLEEP_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x60>>CPU_SHIFT))
+#define GSM_CAMPON_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x64>>CPU_SHIFT))
+#define GSM_CONNECT_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x68>>CPU_SHIFT))
+
+#define RFC_AFC_CTRL_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x6c>>CPU_SHIFT))
+
+
+#define TD_SLEEP_FLAG (*((volatile unsigned long *)TD_SLEEP_FLAG_ADDR)) //TDÎïÀí²ã˯Ãß״̬£¬Ð´1Ϊ˯Ãߣ¬0Ϊ¹¤×÷״̬
+#define TD_CAMPON_FLAG (*((volatile unsigned long *)TD_CAMPON_FLAG_ADDR)) //TDפÁô±êÖ¾£¬Ð´1ΪפÁô£¬0ΪפÁôʧ°Ü
+#define TDPHY_CONNECT_FLAG (*((volatile unsigned long *)TDPHY_CONNECT_FLAG_ADDR))
+#define TD_WRITE_DPRAM_SFN (*((volatile unsigned long *)TD_WRITE_DPRAM_SFN_ADDR))
+
+#define W_SLEEP_FLAG (*((volatile unsigned long *)W_SLEEP_FLAG_ADDR)) //LTEÎïÀí²ã˯Ãß״̬£¬Ð´1Ϊ˯Ãߣ¬0Ϊ¹¤×÷״̬
+#define W_CAMPON_FLAG (*((volatile unsigned long *)W_CAMPON_FLAG_ADDR)) //LTEפÁô±êÖ¾£¬Ð´1ΪפÁô£¬0ΪפÁôʧ°Ü
+#define WPHY_CONNECT_FLAG (*((volatile unsigned long *)WPHY_CONNECT_FLAG_ADDR))
+#define W_WRITE_DPRAM_SFN (*((volatile unsigned long *)W_WRITE_DPRAM_SFN_ADDR))
+
+#define LTE_SLEEP_FLAG (*((volatile unsigned long *)LTE_SLEEP_FLAG_ADDR)) //LTEÎïÀí²ã˯Ãß״̬£¬Ð´1Ϊ˯Ãߣ¬0Ϊ¹¤×÷״̬
+#define LTE_CAMPON_FLAG (*((volatile unsigned long *)LTE_CAMPON_FLAG_ADDR)) //LTEפÁô±êÖ¾£¬Ð´1ΪפÁô£¬0ΪפÁôʧ°Ü
+#define LTEPHY_CONNECT_FLAG (*((volatile unsigned long *)LTEPHY_CONNECT_FLAG_ADDR))
+#define LTE_WRITE_DPRAM_SFN (*((volatile unsigned long *)LTE_WRITE_DPRAM_SFN_ADDR))
+
+#define CPU_PS_SLEEP_FLAG (*((volatile unsigned long *)CPU_PS_SLEEP_FLAG_ADDR)) //CPU_PS˯Ãß±êÖ¾£¬psд1Ϊ˯Ãߣ¬Ð´0Ϊ¹¤×÷£¬ÓÃÓÚÎïÀí²ã·¢ICP¸øÐÒéÕ»£¬ÎïÀí²ã²éѯCPU_PSµÄ˯Ãß״̬¡£
+#define CPU_PHY_SLEEP_FLAG (*((volatile unsigned long *)CPU_PHY_SLEEP_FLAG_ADDR)) //Ô¤Áô£ºCPU_PHYºË˯Ãß״̬£¬Ð´1Ϊ˯Ãߣ¬Ð´0Ϊ¹¤×÷
+#define IRAT_GAP_REPORT_FLAG (*((volatile unsigned long *)IRAT_GAP_REPORT_FLAG_ADDR)) //20msÎÊÌâÓÅ»¯
+#define TD_REPORT_GAP_WAKEUP_GSM (*((volatile unsigned long *)TD_REPORT_GAP_WAKEUP_GSM_ADDR))
+
+#define ICP_WAKEUP_TD_FLAG (*((volatile unsigned long *)ICP_WAKEUP_TD_FLAG_ADDR))
+#define ICP_WAKEUP_W_FLAG (*((volatile unsigned long *)ICP_WAKEUP_W_FLAG_ADDR))
+#define ICP_WAKEUP_LTE_FLAG (*((volatile unsigned long *)ICP_WAKEUP_LTE_FLAG_ADDR))
+
+#define W_TPU_DOFF_FOR_RTCFN_CALC (*((volatile unsigned long *)W_TPU_DOFF_FOR_RTCFN_CALC_ADDR))
+
+#define LTE_RFC_INIT_EVENT_TABLE_FLAG (*((volatile unsigned long *)LTE_RFC_EVENT_TABLE_FLAG_ADDR))
+#define ZSP_SLEEP_R7DELAYICP_FLG (*((volatile unsigned long *)ZSP_SLEEP_R7DELAYICP_FLG_ADDR))
+
+#define GSM_SLEEP_FLAG (*((volatile unsigned long *)GSM_SLEEP_FLAG_ADDR))
+#define GSM_CAMPON_FLAG (*((volatile unsigned long *)GSM_CAMPON_FLAG_ADDR))
+#define GSM_CONNECT_FLAG (*((volatile unsigned long *)GSM_CONNECT_FLAG_ADDR))
+
+#define RFC_AFC_CTRL (*((volatile unsigned long *)RFC_AFC_CTRL_ADDR))
+
+
+/**************************************************************************
+ AT ÃüÁî¿ØÖÆÊ¡µç×Ó¹¦ÄÜÐÅÏ¢
+**************************************************************************/
+#define AT_COMM_PSM_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0xA0>>CPU_SHIFT))
+#define AT_COMM_M0_PSM_FLAG_ADDR (AT_COMM_PSM_FLAG_ADDR) //µÚ1 ¸ö×Ö¶ÎÓÃÓÚM0
+#define AT_COMM_PS_AP_PSM_FLAG_ADDR (AT_COMM_PSM_FLAG_ADDR + (0x4>>CPU_SHIFT)) //µÚ2 ¸ö×Ö¶ÎÓÃÓÚR7 A9
+#define AT_COMM_PHY_PSM_FLAG_WORD1_ADDR (AT_COMM_PSM_FLAG_ADDR + (0x8>>CPU_SHIFT)) //µÚ3 ¸ö×Ö¶ÎÓÃÓÚZSP
+#define AT_COMM_PHY_PSM_FLAG_WORD2_ADDR (AT_COMM_PSM_FLAG_ADDR + (0xC>>CPU_SHIFT)) //µÚ4 ¸ö×Ö¶ÎÓÃÓÚZSP
+#define AT_COMM_PSM_FLAG_READY_ADDR (AT_COMM_PSM_FLAG_ADDR + (0x10>>CPU_SHIFT)) //µÚ5 ¸ö×Ö¶ÎÓÃÓÚR7ÌîдÍê³É±êÖ¾
+
+#define AT_COMM_AP_PSM_MASK (unsigned long)0xFFFF0000 // high
+#define AT_COMM_PS_PSM_MASK (unsigned long)0x0000FFFF // low
+
+
+/**************************************************************************
+ Ê¡µçµ÷ÊÔÐÅÏ¢ 0x1030C0 --- 0x1030DC
+**************************************************************************/
+#define ZCPU_PSM_DEBUG_INFO_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0xC0>>CPU_SHIFT))
+#define ZCPU_PSM_NEED_RESTORE_CONTEXT (*((volatile unsigned long *)ZCPU_PSM_DEBUG_INFO_ADDR)) //0x1030C0
+
+#define ZCPU_PSM_DEBUG_INFO (*((volatile unsigned long *)(ZCPU_PSM_DEBUG_INFO_ADDR + (0x10>>CPU_SHIFT)))) //0x1030D0
+#define WMODEM_MASTER_PSM_DEBUG_INFO (*((volatile unsigned long *)(ZCPU_PSM_DEBUG_INFO_ADDR + (0x14>>CPU_SHIFT)))) //0x1030D4
+#define WMODEM_SLAVE_PSM_DEBUG_INFO (*((volatile unsigned long *)(ZCPU_PSM_DEBUG_INFO_ADDR + (0x18>>CPU_SHIFT)))) //0x1030D8
+#define LTEMODEM_PSM_DEBUG_INFO (*((volatile unsigned long *)(ZCPU_PSM_DEBUG_INFO_ADDR + (0x1C>>CPU_SHIFT)))) //0x1030DC
+
+
+
+/************************* ACP Version C or D 0x1020E0************************/
+#define RF_CD_VERSION_FLAG_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0xE0>>CPU_SHIFT))
+#define RF_CD_VERSION_FLAG (*((volatile unsigned long *)RF_CD_VERSION_FLAG_ADDR))
+
+
+/************************ PHY EXIST ÐÅÏ¢ 0x1020F0 ***********************/
+#define PHY_EXIST_INFO_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0xF0>>CPU_SHIFT))
+#define PHY_EXIST_INFO (*((volatile unsigned long *)PHY_EXIST_INFO_ADDR))
+
+
+/**************************˯Ãß´ÎÊý ÐÅÏ¢**************************/
+#define PHY_TDS_SLEEP_CNT_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x100>>CPU_SHIFT))
+#define PHY_W_SLEEP_CNT_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x104>>CPU_SHIFT))
+#define PHY_LTE_SLEEP_CNT_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x108>>CPU_SHIFT))
+#define PHY_ZSP_SLEEP_CNT_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x10C>>CPU_SHIFT))
+#define R7_SLEEP_CNT_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x110>>CPU_SHIFT))
+#define AP_SLEEP_CNT_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x114>>CPU_SHIFT))
+#define CHIP_SLEEP_CNT_ADDR (IRAM1_M0_PSM_USE_BASE_ADDR)
+
+#define PHY_TDS_SLEEP_CNT (*((volatile unsigned long *)PHY_TDS_SLEEP_CNT_ADDR))
+#define PHY_W_SLEEP_CNT (*((volatile unsigned long *)PHY_W_SLEEP_CNT_ADDR))
+#define PHY_LTE_SLEEP_CNT (*((volatile unsigned long *)PHY_LTE_SLEEP_CNT_ADDR))
+#define PHY_ZSP_SLEEP_CNT (*((volatile unsigned long *)PHY_ZSP_SLEEP_CNT_ADDR))
+#define R7_SLEEP_SLEEP_CNT (*((volatile unsigned long *)R7_SLEEP_CNT_ADDR))
+#define AP_SLEEP_SLEEP_CNT (*((volatile unsigned long *)AP_SLEEP_CNT_ADDR))
+#define CHIP_SLEEP_SLEEP_CNT (*((volatile unsigned long *)CHIP_SLEEP_CNT_ADDR))
+
+
+
+/**************************************************************************
+ DDR µ÷ƵµØÖ·
+**************************************************************************/
+#define IRAM_DDR_DFS_PS_REQ_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x140>>CPU_SHIFT))
+#define IRAM_DDR_DFS_PS_ALLOWED_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x144>>CPU_SHIFT))
+#define IRAM_DDR_DFS_PS_EXP_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x148>>CPU_SHIFT))
+
+#define IRAM_DDR_DFS_PHY_REQ_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x14c>>CPU_SHIFT))
+#define IRAM_DDR_DFS_PHY_ALLOWED_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x150>>CPU_SHIFT))
+#define IRAM_DDR_DFS_PHY_EXP_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x154>>CPU_SHIFT))
+
+#define IRAM_DDR_DFS_AP_REQ_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x158>>CPU_SHIFT))
+#define IRAM_DDR_DFS_AP_ALLOWED_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x15c>>CPU_SHIFT))
+#define IRAM_DDR_DFS_AP_EXP_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x160>>CPU_SHIFT))
+//µ±Ç°DDRƵÂÊ
+#define IRAM_DDR_DFS_CUR_FREQ_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x164>>CPU_SHIFT))
+//M0ÊÇ·ñÍê³ÉDDRµ÷Ƶ±êÖ¾ 0XA0A00A0A:PS SET DDR FREQ FINISH
+#define IRAM_DDR_DFS_FINIFH_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x168>>CPU_SHIFT))
+
+#define IRAM_DDR_DFS_PS_REQ (*((volatile unsigned long *)IRAM_DDR_DFS_PS_REQ_ADDR))
+#define IRAM_DDR_DFS_PS_ALLOWED (*((volatile unsigned long *)IRAM_DDR_DFS_PS_ALLOWED_ADDR))
+#define IRAM_DDR_DFS_PS_EXP (*((volatile unsigned long *)IRAM_DDR_DFS_PS_EXP_ADDR))
+#define IRAM_DDR_DFS_PHY_REQ (*((volatile unsigned long *)IRAM_DDR_DFS_PHY_REQ_ADDR))
+#define IRAM_DDR_DFS_PHY_ALLOWED (*((volatile unsigned long *)IRAM_DDR_DFS_PHY_ALLOWED_ADDR))
+#define IRAM_DDR_DFS_PHY_EXP (*((volatile unsigned long *)IRAM_DDR_DFS_PHY_EXP_ADDR))
+#define IRAM_DDR_DFS_AP_REQ (*((volatile unsigned long *)IRAM_DDR_DFS_AP_REQ_ADDR))
+#define IRAM_DDR_DFS_AP_ALLOWED (*((volatile unsigned long *)IRAM_DDR_DFS_AP_ALLOWED_ADDR))
+#define IRAM_DDR_DFS_AP_EXP (*((volatile unsigned long *)IRAM_DDR_DFS_AP_EXP_ADDR))
+#define IRAM_DDR_DFS_CUR_FREQ (*((volatile unsigned long *)IRAM_DDR_DFS_CUR_FREQ_ADDR))
+#define IRAM_DDR_DFS_FINIFH (*((volatile unsigned long *)IRAM_DDR_DFS_FINIFH_ADDR))
+
+#define DDR_DFS_FINIFH_CODING 0xA0A00A0A
+
+
+/**************************************************************************
+ AXI µ÷ƵµØÖ·
+**************************************************************************/
+#define IRAM_SET_AXIFREQ_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x180>>CPU_SHIFT))
+#define IRAM_PS2M0_AXIFREQ_REQ_ADDR (IRAM_SET_AXIFREQ_ADDR) /*0x00 ps request axi change flag*/
+#define IRAM_PS2M0_AXIFREQ_EXP_ADDR (IRAM_SET_AXIFREQ_ADDR + (0x4>>CPU_SHIFT)) /*0x04 ps expect axi freq*/
+#define IRAM_PHY2M0_AXIFREQ_REQ_ADDR (IRAM_SET_AXIFREQ_ADDR + (0x8>>CPU_SHIFT)) /*0x08 phy request axi change flag*/
+#define IRAM_PHY2M0_AXIFREQ_EXP_ADDR (IRAM_SET_AXIFREQ_ADDR + (0xc>>CPU_SHIFT)) /*0x0c phy expect axi freq*/
+#define IRAM_AP2M0_AXIFREQ_REQ_ADDR (IRAM_SET_AXIFREQ_ADDR + (0x10>>CPU_SHIFT)) /*0x10 ap request axi change flag*/
+#define IRAM_AP2M0_AXIFREQ_EXP_ADDR (IRAM_SET_AXIFREQ_ADDR + (0x14>>CPU_SHIFT)) /*0x14 ap expect axi freq*/
+#define IRAM_CUR_AXIFREQ_ADDR (IRAM_SET_AXIFREQ_ADDR + (0x18>>CPU_SHIFT))/*0x18 current axi freq*/
+
+#define IRAM_PS2M0_AXIFREQ_REQ_REG (*((volatile unsigned long *)IRAM_PS2M0_AXIFREQ_REQ_ADDR))
+#define IRAM_PS2M0_AXIFREQ_EXP_REG (*((volatile unsigned long *)IRAM_PS2M0_AXIFREQ_EXP_ADDR))
+#define IRAM_PHY2M0_AXIFREQ_REQ_REG (*((volatile unsigned long *)IRAM_PHY2M0_AXIFREQ_REQ_ADDR))
+#define IRAM_PHY2M0_AXIFREQ_EXP_REG (*((volatile unsigned long *)IRAM_PHY2M0_AXIFREQ_EXP_ADDR))
+#define IRAM_AP2M0_AXIFREQ_REQ_REG (*((volatile unsigned long *)IRAM_AP2M0_AXIFREQ_REQ_ADDR))
+#define IRAM_AP2M0_AXIFREQ_EXP_REG (*((volatile unsigned long *)IRAM_AP2M0_AXIFREQ_EXP_ADDR))
+#define IRAM_CUR_AXIFREQ_REG (*((volatile unsigned long *)IRAM_CUR_AXIFREQ_ADDR))
+
+
+/**************************************************************************
+ VOL µ÷ѹµØÖ·
+**************************************************************************/
+#define IRAM_VOL_DVS_BASE_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x1a0>>CPU_SHIFT))
+#define IRAM_PS2M0_VOL_REQ_ADDR (IRAM_VOL_DVS_BASE_ADDR)
+#define IRAM_PS2M0_VOL_EXP_ADDR (IRAM_VOL_DVS_BASE_ADDR + (0x4>>CPU_SHIFT))
+#define IRAM_PHY2M0_VOL_REQ_ADDR (IRAM_VOL_DVS_BASE_ADDR + (0x8>>CPU_SHIFT))
+#define IRAM_PHY2M0_VOL_EXP_ADDR (IRAM_VOL_DVS_BASE_ADDR + (0xc>>CPU_SHIFT))
+#define IRAM_AP2M0_VOL_REQ_ADDR (IRAM_VOL_DVS_BASE_ADDR + (0x10>>CPU_SHIFT))
+#define IRAM_AP2M0_VOL_EXP_ADDR (IRAM_VOL_DVS_BASE_ADDR + (0x14>>CPU_SHIFT))
+#define IRAM_CUR_VOL_ADDR (IRAM_VOL_DVS_BASE_ADDR + (0x18>>CPU_SHIFT))
+#define IRAM_VOL_DVS_FINIFH_ADDR (IRAM_VOL_DVS_BASE_ADDR + (0x1c>>CPU_SHIFT))
+
+#define IRAM_PS2M0_VOL_REQ_REG (*((volatile unsigned long *)IRAM_PS2M0_VOL_REQ_ADDR))
+#define IRAM_PS2M0_VOL_EXP_REG (*((volatile unsigned long *)IRAM_PS2M0_VOL_EXP_ADDR))
+#define IRAM_PHY2M0_VOL_REQ_REG (*((volatile unsigned long *)IRAM_PHY2M0_VOL_REQ_ADDR))
+#define IRAM_PHY2M0_VOL_EXP_REG (*((volatile unsigned long *)IRAM_PHY2M0_VOL_EXP_ADDR))
+#define IRAM_AP2M0_VOL_REQ_REG (*((volatile unsigned long *)IRAM_AP2M0_VOL_REQ_ADDR))
+#define IRAM_AP2M0_VOL_EXP_REG (*((volatile unsigned long *)IRAM_AP2M0_VOL_EXP_ADDR))
+#define IRAM_CUR_VOL_REG (*((volatile unsigned long *)IRAM_CUR_VOL_ADDR))
+#define IRAM_VOL_DVS_FINIFH (*((volatile unsigned long *)IRAM_VOL_DVS_FINIFH_ADDR))
+
+#define VOL_DVS_FINIFH_CODING 0xA0A00A0A
+
+
+/**************************************************************************
+ ÐͺŻúÊ¡µç¿ØÖƱêÖ¾µØÖ·, ¹²20¸öWORD32, 0x1d0--0x21c
+**************************************************************************/
+#define IRAM_SPECFLAG_BASE_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x1d0>>CPU_SHIFT))
+#define IRAM_BUCK1ONOFFFLAG_ADDR (IRAM_SPECFLAG_BASE_ADDR+(0x00>>CPU_SHIFT))
+
+
+/**************************************************************************
+ Ê¡µçµ÷ÊÔÐÅÏ¢±êÖ¾µØÖ·
+**************************************************************************/
+#define IRAM_APPSM_DEBUG_INFO_BASE_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x280>>CPU_SHIFT))
+#define IRAM_PSPSM_DEBUG_INFO_BASE_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x330>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR (IRAM1_PSM_FLG_CTRL_BASE_ADDR + (0x380>>CPU_SHIFT))
+
+#define IRAM_PSPSM_DEBUG_INFO_SYSMODE_ADDR (IRAM_PSPSM_DEBUG_INFO_BASE_ADDR + (0x00>>CPU_SHIFT))
+#define IRAM_PSPSM_DEBUG_INFO_COMMON_ADDR (IRAM_PSPSM_DEBUG_INFO_BASE_ADDR + (0x04>>CPU_SHIFT))
+#define IRAM_PSPSM_DEBUG_INFO_L1E_ADDR (IRAM_PSPSM_DEBUG_INFO_BASE_ADDR + (0x10>>CPU_SHIFT))
+#define IRAM_PSPSM_DEBUG_INFO_L1W_ADDR (IRAM_PSPSM_DEBUG_INFO_BASE_ADDR + (0x14>>CPU_SHIFT))
+#define IRAM_PSPSM_DEBUG_INFO_L1T_ADDR (IRAM_PSPSM_DEBUG_INFO_BASE_ADDR + (0x18>>CPU_SHIFT))
+#define IRAM_PSPSM_DEBUG_INFO_L1G_ADDR (IRAM_PSPSM_DEBUG_INFO_BASE_ADDR + (0x1C>>CPU_SHIFT))
+#define IRAM_PSPSM_DEBUG_INFO_DRV_ADDR (IRAM_PSPSM_DEBUG_INFO_BASE_ADDR + (0x20>>CPU_SHIFT))
+#define IRAM_PSPSM_DEBUG_INFO_PLAT_ADDR (IRAM_PSPSM_DEBUG_INFO_BASE_ADDR + (0x30>>CPU_SHIFT))
+#define IRAM_PSPSM_DEBUG_INFO_APP_ADDR (IRAM_PSPSM_DEBUG_INFO_BASE_ADDR + (0x40>>CPU_SHIFT))
+
+#define IRAM_PSPSM_DEBUG_INFO_SYSMODE (*((volatile unsigned long *)IRAM_PSPSM_DEBUG_INFO_SYSMODE_ADDR))
+#define IRAM_PSPSM_DEBUG_INFO_COMMON (*((volatile unsigned long *)IRAM_PSPSM_DEBUG_INFO_COMMON_ADDR))
+#define IRAM_PSPSM_DEBUG_INFO_L1E (*((volatile unsigned long *)IRAM_PSPSM_DEBUG_INFO_L1E_ADDR))
+#define IRAM_PSPSM_DEBUG_INFO_L1W (*((volatile unsigned long *)IRAM_PSPSM_DEBUG_INFO_L1W_ADDR))
+#define IRAM_PSPSM_DEBUG_INFO_L1T (*((volatile unsigned long *)IRAM_PSPSM_DEBUG_INFO_L1T_ADDR))
+#define IRAM_PSPSM_DEBUG_INFO_L1G (*((volatile unsigned long *)IRAM_PSPSM_DEBUG_INFO_L1G_ADDR))
+#define IRAM_PSPSM_DEBUG_INFO_DRV (*((volatile unsigned long *)IRAM_PSPSM_DEBUG_INFO_DRV_ADDR))
+#define IRAM_PSPSM_DEBUG_INFO_PLAT (*((volatile unsigned long *)IRAM_PSPSM_DEBUG_INFO_PLAT_ADDR))
+#define IRAM_PSPSM_DEBUG_INFO_APP (*((volatile unsigned long *)IRAM_PSPSM_DEBUG_INFO_APP_ADDR))
+
+#define IRAM_PHYPSM_DEBUG_INFO1_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x00>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO2_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x04>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO3_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x08>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO4_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x0c>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO5_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x10>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO6_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x14>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO7_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x18>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO8_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x1c>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO9_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x20>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO10_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x24>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO11_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x28>>CPU_SHIFT))
+#define IRAM_PHYPSM_DEBUG_INFO12_ADDR (IRAM_PHYPSM_DEBUG_INFO_BASE_ADDR + (0x2c>>CPU_SHIFT))
+
+#define IRAM_PHYPSM_DEBUG_INFO1 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO1_ADDR))
+#define IRAM_PHYPSM_DEBUG_INFO2 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO2_ADDR))
+#define IRAM_PHYPSM_DEBUG_INFO3 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO3_ADDR))
+#define IRAM_PHYPSM_DEBUG_INFO4 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO4_ADDR))
+#define IRAM_PHYPSM_DEBUG_INFO5 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO5_ADDR))
+#define IRAM_PHYPSM_DEBUG_INFO6 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO6_ADDR))
+#define IRAM_PHYPSM_DEBUG_INFO7 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO7_ADDR))
+#define IRAM_PHYPSM_DEBUG_INFO8 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO8_ADDR))
+#define IRAM_PHYPSM_DEBUG_INFO9 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO9_ADDR))
+#define IRAM_PHYPSM_DEBUG_INFO10 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO10_ADDR))
+#define IRAM_PHYPSM_DEBUG_INFO11 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO11_ADDR))
+#define IRAM_PHYPSM_DEBUG_INFO12 (*((volatile unsigned long *)IRAM_PHYPSM_DEBUG_INFO12_ADDR))
+
+
+/**************************************************************************
+ Ê¡µçµ÷ѹ½Ó¿Ú¶¨Òå
+**************************************************************************/
+#define SETVOL_TD_FLAG 0x3D
+#define SETVOL_WD_FLAG 0x3C
+#define SETVOL_LTE_FLAG 0x4E
+#define SETVOL_LTEA_FLAG 0x4A
+
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+/*iram1 Ê¡µç±êÖ¾¼Ä´æÆ÷*/
+#ifndef __ASSEMBLER__
+typedef volatile struct _T_Iram1_PsmInterface_Regs
+{
+ unsigned long iramTdSleepFlag; /*0x00 td sleep flag, 0:work 1:sleep*/
+ unsigned long iramTdCampOnFlag; /*0x04 td camp on flag, 0:not campon 1:campon*/
+ unsigned long iramTdPhyConnectFlag; /*0x08 td connect state flag, TDÎïÀí²ãÁ¬½Ó̬±êÖ¾*/
+ unsigned long iramTdWriteSfnFlag; /*0x0c TDдÍêDPRAMÖ¡ºÅÐÅÏ¢±êÖ¾*/
+
+ unsigned long iramWdSleepFlag; /*0x10 wd sleep flag, 0:work 1:sleep*/
+ unsigned long iramWdCampOnFlag; /*0x14 wd camp on flag, 0:not campon 1:campon*/
+ unsigned long iramWdPhyConnectFlag; /*0x18 wd mconnect state flag, WDÎïÀí²ãÁ¬½Ó̬±êÖ¾*/
+ unsigned long iramWdWriteSfnFlag; /*0x1c WDдÍêDPRAMÖ¡ºÅÐÅÏ¢±êÖ¾*/
+
+ unsigned long iramLteSleepFlag; /*0x20 lte sleep flag, 1/2:work 3:sleep*/
+ unsigned long iramLteCampOnFlag; /*0x24 lte camp on flag, 0:not campon 1:campon*/
+ unsigned long iramLtePhyConnectFlag; /*0x28 connect state flag, LTEÎïÀí²ãÁ¬½Ó̬±êÖ¾*/
+ unsigned long iramLteWriteSfnFlag; /*0x2c LTEдÍêDPRAMÖ¡ºÅÐÅÏ¢±êÖ¾*/
+
+ unsigned long iramPsSleepFlag; /*0x30 ps sleep flag, 0:work 1:sleep */
+ unsigned long iramPhySleepFlag; /*0x34 phy sleep flag, 0:work 1:sleep */
+
+ /*ARM1Ö÷ÖÆʽGAP±¨ÍêÒÔºó£¬PSÅжÏûÓÐGAPÅäÖøøARM1ÉÏÆäËûPHY£¬ÔòÇåIRAMÖбêÖ¾¡£*/
+ unsigned long iramIratGapReportFlag; /*0x38 iram irat gap report flag*/
+
+ /*TDÉϱ¨GAPºóLPM×ÓÖ¡ÖжÏʱÐ軽ÐÑGSM,·ÀÖ¹GSM˯Ãß̬PSµ÷GSM²âÁ¿Ê±Ã»Óл½ÐÑGSM¡£*/
+ unsigned long iramTdReportGapWakeGsmFlag; /*0x3c iram irat gap report flag*/
+
+ /*ÓÃÓÚ·¢ËÍicpʧ°Ü¹æ±Ü*/
+ unsigned long iramIcpWakeTdFlag; /*0x40 reserved*/
+ unsigned long iramIcpWakeWdFlag; /*0x44 reserved*/
+ unsigned long iramIcpWakeLteFlag; /*0x48 reserved*/
+
+ unsigned long iramWdDoffVal; /*0x4c*/
+
+}T_Iram1_PsmInterface_Regs;
+#endif
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+
+#endif // #ifndef _PSM_RAM_CONFIG_7520V3
+
diff --git a/pub/project/zx297520v3/include/tools/.gitignore b/pub/project/zx297520v3/include/tools/.gitignore
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/pub/project/zx297520v3/include/tools/.gitignore