| /******************************************************************************* | |
| * Copyright (C) 2014, ZTE Corporation. | |
| * | |
| * File Name: drvs_ADDR_regmap.inc | |
| * File Mark: | |
| * Description: This file contains the register map. | |
| * Others: | |
| * Version: V1.0 | |
| * Author: zhangdongdong | |
| * Date: 2015-07-31 | |
| * History 1: | |
| * | |
| *********************************************************************************/ | |
| #ifndef _DRVS_REGMAP_H | |
| #define _DRVS_REGMAP_H | |
| /* M2 */ | |
| #define ADDR_IROM 0x00000000 | |
| /* M3 */ | |
| #define ADDR_IRAM2 0x00080000 | |
| /* M4 -- A1 CFG */ | |
| #define ADDR_IRAM1 0x00100000 | |
| #define ADDR_KEY 0x00130000 | |
| #define ADDR_UART0 0x00131000 | |
| #define ADDR_I2C_PMIC 0x00132000 | |
| #define ADDR_RTC 0x00133000 | |
| #define ADDR_LPM_GSM 0x00134000 | |
| #define ADDR_LPM_LTE 0x00134200 | |
| #define ADDR_LPM_TD 0x00134400 | |
| #define ADDR_LPM_W 0x00134600 | |
| #define ADDR_PS_TIMER1 0x00138000 | |
| #define ADDR_PS_TIMER2 0x00139000 | |
| #define ADDR_PCU 0x0013A000 | |
| #define ADDR_TOP_CRM 0x0013B000 | |
| #define ADDR_PAD_CTRL_A0 0x0013C000 | |
| #define ADDR_GPIO0 0x0013D000 | |
| #define ADDR_GPIO1 0x0013E000 | |
| #define ADDR_SOC_SYS 0x00140000 | |
| #define ADDR_RM_TIMER0 0x00142000 | |
| #define ADDR_AP_TIMER1 0x00143000 | |
| #define ADDR_AP_TIMER2 0x00144000 | |
| #define ADDR_RM_TIMER1 0x00145000 | |
| #define ADDR_AP_TIMER3 0x00146000 | |
| #define ADDR_PHY_TIMER1 0x00147000 | |
| #define ADDR_RM_WDT 0x00148000 | |
| #define ADDR_DDR_CTRL 0x00150000 | |
| #define ADDR_DDR_PHY 0x00154000 | |
| #define ADDR_DDR_FFC 0x00155000 | |
| #define ADDR_USIM1 0x00156000 | |
| #define ADDR_RM2MATRIX 0x00200000 | |
| #define ADDR_NIC400_MATRIX1_CFG 0x10500000 | |
| /* M2 -- AHB CFG0 */ | |
| #define ADDR_EDCP 0x01200000 | |
| #define ADDR_SD0 0x01210000 | |
| #define ADDR_SD1 0x01211000 | |
| #define ADDR_NAND_REG 0x01214000 | |
| #define ADDR_NAND_DATA 0x01215000 | |
| #define ADDR_EFUSE 0x0121B000 | |
| #define ADDR_RSA 0x0121C000 | |
| #define ADDR_HASH 0x0121D000 | |
| #define ADDR_USB 0x01500000 | |
| #define ADDR_HSIC 0x01600000 | |
| /* M2 -- AHB2APB */ | |
| #define ADDR_DMA_PHY 0x01300000 | |
| #define ADDR_DMA_PS 0x01301000 | |
| #define ADDR_ICP 0x01302000 | |
| #define ADDR_AP_CPU_SLAVE 0x03000000 | |
| #define ADDR_PS_CPU_SLAVE 0x06000000 | |
| /* M2 -- APB LITE 0 */ | |
| #define ADDR_PIN_MUX 0x01303000 | |
| #define ADDR_SSC 0x01304000 | |
| #define ADDR_STD_CRM 0x01306000 /*matrix crm*/ | |
| #define ADDR_GMAC 0x01307000 | |
| #define ADDR_VOU_CFG 0x01380000 | |
| /* M1 -- LSP */ | |
| #define ADDR_LSP_CRM 0x01400000 | |
| #define ADDR_LSP_PS_TIMER0 0x01401000 | |
| #define ADDR_LSP_PHY_WDT 0x01402000 | |
| #define ADDR_LSP_PS_WDT 0x01403000 | |
| #define ADDR_LSP_PWM 0x01404000 | |
| #define ADDR_LSP_I2S0 0x01405000 | |
| #define ADDR_LSP_I2S1 0x01406000 | |
| #define ADDR_LSP_SPIFC0 0x01407000 | |
| #define ADDR_LSP_UART1 0x01408000 | |
| #define ADDR_LSP_I2C1 0x01409000 | |
| #define ADDR_LSP_SSP0 0x0140A000 | |
| #define ADDR_LSP_PS_RM_TIMER 0x0140B000 | |
| #define ADDR_LSP_PHY_TIMER0 0x0140C000 | |
| #define ADDR_LSP_UART2 0x0140D000 | |
| #define ADDR_LSP_AP_WDT 0x0140E000 | |
| #define ADDR_LSP_AP_TIMER0 0x0140F000 | |
| #define ADDR_LSP_SSP1 0x01410000 | |
| #define ADDR_LSP_AP_TIMER4 0x01411000 | |
| #define ADDR_LSP_TDM 0x01412000 | |
| /* DDR */ | |
| #define ADDR_DDR_BASE 0x20000000 | |
| /* GSM */ | |
| #define ADDR_GSM_CFG 0xF3000000 | |
| #define ADDR_GSM_MODEM1 0xF4000000 | |
| #define ADDR_GSM_MODEM2 0xF6000000 | |
| /* PHY CPU SALVE */ | |
| #define ADDR_PHY_L2TCM 0x600C0000 | |
| #define ADDR_PHY_DTCM 0x81000000 | |
| #define ADDR_PHY_ITCM 0x81040000 | |
| #define ADDR_PHY_CRM 0x81800000 | |
| #define ADDR_PHY_ICU 0x81801000 | |
| /* IRAM0 */ | |
| #define ADDR_IRAM0 0x82000000 | |
| /* PS MG */ | |
| #define ADDR_MG_CRM 0xF2200000 | |
| #define ADDR_MG_GICC 0x02900000 | |
| #define ADDR_MG_GICD 0xF2000000 | |
| #define ADDR_MG_GICR 0xF2040000 | |
| /*need confirm*/ | |
| #define ADDR_MG_CFG 0x00801000 | |
| #define ADDR_MG_SCU 0xEF000000 | |
| /* M2 MODEM */ | |
| #define ADDR_LTE_MODEM_D 0xF8000000 | |
| #define ADDR_WD_MODEM_D 0xF8100000 | |
| #define ADDR_TD_MODEM_D 0xF8200000 | |
| /* M1 MODEM */ | |
| #define ADDR_LTE_MODEM_C 0xFC000000 | |
| #define ADDR_WD_MODEM_C 0xFC100000 | |
| #define ADDR_TD_MODEM_C 0xFC200000 | |
| #define ADDR_NIC400_MATRIX0_CFG 0xF7500000 | |
| #endif |