[Feature][ZXW-130]merge P50U02 version
Only Configure: No
Affected branch: master
Affected module: unknow
Is it affected on both ZXIC and MTK: only ZXIC
Self-test: Yes
Doc Update: No
Change-Id: I4f29ec5bb7c59385f23738d2b7ca84e67c100f69
diff --git a/ap/os/linux/linux-3.4.x/drivers/mtd/cmdlinepart.c b/ap/os/linux/linux-3.4.x/drivers/mtd/cmdlinepart.c
old mode 100644
new mode 100755
index 3e65e07..f95d187
--- a/ap/os/linux/linux-3.4.x/drivers/mtd/cmdlinepart.c
+++ b/ap/os/linux/linux-3.4.x/drivers/mtd/cmdlinepart.c
@@ -73,6 +73,7 @@
/* the command line passed to mtdpart_setupd() */
static char *cmdline;
static int cmdline_parsed = 0;
+char *nor_cmdline;
/*
* Parse one partition definition for an MTD. Since there can be many
@@ -375,6 +376,15 @@
__setup("mtdparts=", mtdpart_setup);
+static int nor_cmdline_setup(char *s)
+{
+ nor_cmdline = s;
+ return 1;
+}
+
+__setup("EnhancedSecurity=", nor_cmdline_setup);
+
+
static struct mtd_part_parser cmdline_parser = {
.owner = THIS_MODULE,
.parse_fn = parse_cmdline_partitions,
diff --git a/ap/os/linux/linux-3.4.x/drivers/mtd/nand/nand_ids.c b/ap/os/linux/linux-3.4.x/drivers/mtd/nand/nand_ids.c
index ca6012e..e15a472 100755
--- a/ap/os/linux/linux-3.4.x/drivers/mtd/nand/nand_ids.c
+++ b/ap/os/linux/linux-3.4.x/drivers/mtd/nand/nand_ids.c
@@ -89,6 +89,7 @@
{"SPI-NAND 512MiB 1,8V", 0x35, 4096, 512, 0x40000, 0},
{"SPI-NAND 512MiB 1,8V", 0x45, 2048, 512, 0x20000, 0}, //GD5F4GQ6REY2G
{"SPI-NAND 512MiB 1,8V", 0x53, 4096, 512, 0x40000, 0}, //XT26Q04D-B
+ {"SPI-NAND 128MiB 1,8V", 0x15, 2048, 128, 0x20000, 0}, //UM19A0LISW
/*
* These are the new chips with large page size. The pagesize and the
* erasesize is determined from the extended id bytes
@@ -225,6 +226,7 @@
{NAND_MFR_EMST, "emst"},
{NAND_MFR_FORESEE, "foresee"},
{NAND_MFR_XTX, "xtx"},
+ {NAND_MFR_UNIM, "unim"},
{0x0, "Unknown"}
};
diff --git a/ap/os/linux/linux-3.4.x/drivers/mtd/nand/spi_nand_devices.c b/ap/os/linux/linux-3.4.x/drivers/mtd/nand/spi_nand_devices.c
index a2eb6b1..6f4db46 100755
--- a/ap/os/linux/linux-3.4.x/drivers/mtd/nand/spi_nand_devices.c
+++ b/ap/os/linux/linux-3.4.x/drivers/mtd/nand/spi_nand_devices.c
@@ -283,6 +283,21 @@
}
}
+static void get_unim_nand_para(uint8_t device_id)
+{
+
+ switch (device_id) {
+ case 0x15:
+ main_size = 2048;
+ spare_size = 64;
+ break;
+ default:
+ printk("Spectra: Unknown unim NAND (Device ID: 0x%x)."
+ "Will use default parameter values instead.\n",
+ device_id);
+ }
+}
+
void spi_nand_get_param(uint32_t maf_id, uint32_t dev_id)
{
@@ -329,6 +344,9 @@
else if (maf_id == NAND_MFR_XTX) {
get_xtx_nand_para(dev_id);
}
+ else if (maf_id == NAND_MFR_UNIM) {
+ get_unim_nand_para(dev_id);
+ }
else{
printk("Spectra: Unknown manufacturer (ID: 0x%x).", maf_id);
}
@@ -413,7 +431,11 @@
.eccbytes = 192,
.oobfree = {{2,62}}
};
-
+
+static struct nand_ecclayout nand_unim_oob_64= {
+ .oobfree = {{2,62}}
+};
+
static void spi_nand_winbond_init(struct spi_nand_info *spi_nand)
{
uint8_t dev_id = spi_nand->dev_id;
@@ -501,6 +523,7 @@
||(g_maf_id == NAND_MFR_GIGADEVICE)
||(g_maf_id == NAND_MFR_WINBOND)
|| (g_maf_id == NAND_MFR_XTX)
+ || (g_maf_id == NAND_MFR_UNIM)
||(g_maf_id == NAND_MFR_MICRON))
return PLX4_MODE;
else
@@ -519,6 +542,7 @@
||(g_maf_id == NAND_MFR_GIGADEVICE)
||(g_maf_id == NAND_MFR_WINBOND)
|| (g_maf_id == NAND_MFR_XTX)
+ || (g_maf_id == NAND_MFR_UNIM)
||(g_maf_id == NAND_MFR_MICRON))
return RDX4_MODE;
else
@@ -653,6 +677,12 @@
chip->ecc.layout =&nand_xtx_oob_256;
}
break;
+ case NAND_MFR_UNIM:
+ if(mtd->oobsize==64 && mtd->writesize==2048)
+ {
+ chip->ecc.layout =&nand_unim_oob_64;
+ }
+ break;
default:
break;
}
diff --git a/ap/os/linux/linux-3.4.x/drivers/mtd/nand/zxic_spifc.c b/ap/os/linux/linux-3.4.x/drivers/mtd/nand/zxic_spifc.c
index 98a0ccc..16c0efe 100755
--- a/ap/os/linux/linux-3.4.x/drivers/mtd/nand/zxic_spifc.c
+++ b/ap/os/linux/linux-3.4.x/drivers/mtd/nand/zxic_spifc.c
@@ -44,15 +44,17 @@
#include "zxic_spifc.h"
#include "spi_nand.h"
+
#define zDrv_ASSERT(_EXP) printk("spifc error\n")
+
struct spifc_info g_spifc;
extern unsigned char g_maf_id;
-
+extern char *nor_cmdline;
static int spifc_get_feature( uint32_t reg_addr, uint8_t *value);
static uint32_t spi_fc_wait_cmd_end(void);
int winbond_dev_id2 = 0;
-
+unsigned char g_nor_flag = 0;
/* SPI NAND FLASH COMMAND FORMAT TYPE */
/********************************************************************************
[Instruction] |--write enable
@@ -550,6 +552,9 @@
do
{
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
spi_fc_clear_fifo();
spi_fc_clear_int();
spi_fc_config_ctrl(FC_DMA_NONE);
@@ -561,6 +566,10 @@
{
continue; /* ¡ä?¨º?¨º¡ì¡ã¨¹¡ê??¨¢¨º?¡À?¡ä??-?¡¤2¡é??¡ä? */
}
+
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+
break;
} while( --retries != 0 );
@@ -595,7 +604,10 @@
};
while(1)
{
- do
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
+ do
{
spi_fc_clear_fifo();
spi_fc_clear_int();
@@ -612,6 +624,11 @@
}
while ( --retries != 0 );
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+
+ udelay(5);
+
/* µÈ´ýÉÏ´ÎÃüÁîÖ´ÐÐÍê³É */
do
{
@@ -655,6 +672,9 @@
};
do
{
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
spi_fc_clear_fifo();
spi_fc_clear_int();
spi_fc_config_ctrl(FC_DMA_NONE);
@@ -666,6 +686,9 @@
continue; /* ´«Êäʧ°Ü£¬½áÊø±¾´ÎÑ»·²¢ÖØ´« */
}
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+
break;
}
while ( --retries != 0 );
@@ -701,8 +724,11 @@
0 /* ¿ÕÏеȴýÖÜÆÚ x1 */
};
do
- {
- spi_fc_setup_cmd(&cmd, 0, 0); /* ÃüÁîÅäÖà */
+ {
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
+ spi_fc_setup_cmd(&cmd, 0, 0); /* ÃüÁîÅäÖà */
spi_fc_clear_int();
spi_fc_start(); /* ¿ªÊ¼´«Êä */
ret = spi_fc_wait_cmd_end(); /* µÈ´ýÃüÁî½áÊø */
@@ -710,6 +736,11 @@
{
continue; /* ´«Êäʧ°Ü£¬½áÊø±¾´ÎÑ»·²¢ÖØ´« */
}
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+
+ udelay(5);
+
do
{
spifc_get_feature(REG_STATUS, &status);
@@ -755,6 +786,9 @@
};
do
{
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
spi_fc_clear_fifo();
spi_fc_clear_int();
spi_fc_config_ctrl(FC_DMA_NONE);
@@ -772,6 +806,9 @@
continue; /* ´«Êäʧ°Ü£¬½áÊø±¾´ÎÑ»·²¢ÖØ´« */
}
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+
break;
}
while ( --retries != 0 );
@@ -812,6 +849,9 @@
};
do
{
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
spi_fc_clear_fifo();
spi_fc_clear_int();
spi_fc_config_ctrl(FC_DMA_NONE);
@@ -823,6 +863,10 @@
{
continue; /* ´«Êäʧ°Ü£¬½áÊø±¾´ÎÑ»·²¢ÖØ´« */
}
+
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+
break;
}
while ( --retries != 0 );
@@ -864,6 +908,9 @@
do
{
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
spi_fc_clear_fifo();
spi_fc_clear_int();
spi_fc_config_ctrl(FC_DMA_NONE);
@@ -884,6 +931,9 @@
continue; /* ´«Êäʧ°Ü£¬½áÊø±¾´ÎÑ»·²¢ÖØ´« */
}
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+
break;
}
while ( --retries != 0 );
@@ -927,6 +977,9 @@
};
do
{
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
spi_fc_clear_fifo();
spi_fc_clear_int();
spi_fc_config_ctrl(FC_DMA_NONE);
@@ -938,6 +991,10 @@
continue; /* ´«Êäʧ°Ü£¬½áÊø±¾´ÎÑ»·²¢ÖØ´« */
}
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+ udelay(5);
+
/* µÈ´ýÃüÁîÖ´ÐÐÍê³É */
do
{
@@ -996,6 +1053,9 @@
};
do
{
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
spi_fc_clear_fifo();
spi_fc_clear_int();
spi_fc_config_ctrl(FC_DMA_NONE);
@@ -1007,6 +1067,10 @@
continue; /* ´«Êäʧ°Ü£¬½áÊø±¾´ÎÑ»·²¢ÖØ´« */
}
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+ udelay(5);
+
/* µÈ´ýÃüÁîÖ´ÐÐÍê³É */
do
{
@@ -1155,6 +1219,9 @@
do
{
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
spi_fc_clear_fifo();
spi_fc_clear_int();
spi_fc_setup_cmd(&cmd, column_addr, len); /* ÃüÁîÅäÖà */
@@ -1185,7 +1252,9 @@
spifc_wait_dma_done(FC_DMA_RX);
spi_fc_config_ctrl(FC_DMA_NONE);
#endif
-
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+
break;
}
while ( --retries != 0 );
@@ -1240,6 +1309,9 @@
do
{
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
spi_fc_clear_fifo();
spi_fc_clear_int();
spi_fc_setup_cmd(&cmd, column_addr, page_len+oob_len); /* ÃüÁîÅäÖà */
@@ -1265,7 +1337,10 @@
#if TRANS_USE_DMA
spifc_wait_dma_done(FC_DMA_TX);
spi_fc_config_ctrl(FC_DMA_NONE);
-#endif
+#endif
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+
break;
}
while ( --retries != 0 );
@@ -1308,6 +1383,9 @@
};
do
{
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_LOW);//spp
+
spi_fc_clear_fifo();
spi_fc_clear_int();
spi_fc_config_ctrl(FC_DMA_NONE);
@@ -1319,6 +1397,10 @@
continue; /* ´«Êäʧ°Ü£¬½áÊø±¾´ÎÑ»·²¢ÖØ´« */
}
+ if(g_nor_flag == 1)
+ gpio_set_value(86,GPIO_HIGH);//spp
+ udelay(5);
+
/* µÈ´ýÃüÁîÖ´ÐÐÍê³É */
do
{
@@ -1497,6 +1579,7 @@
zx29_gpio_config(95, 0x1);
/*configure gpio5 to sfc_cs*/
+
ret = gpio_request(93, "sfc_cs");
if (ret)
{
@@ -1504,8 +1587,21 @@
zDrv_ASSERT(0);
return;
}
- zx29_gpio_config(93, 0x1);
-
+ if(g_nor_flag == 1){
+ zx29_gpio_config(93, GPIO93_GPIO93);
+ gpio_direction_output(93,1);
+
+ ret = gpio_request(ZX29_GPIO_86, "gpio");
+ if (ret)
+ {
+ printk("gpio86 fail\n");
+ zDrv_ASSERT(0);
+ return;
+ }
+ zx29_gpio_config(ZX29_GPIO_86, GPIO86_GPIO86);
+ gpio_direction_output(ZX29_GPIO_86,1);
+ }
+
/*configure gpio3 to sfc_sclk*/
ret = gpio_request(94, "sfc_sclk");
if (ret)
@@ -1763,12 +1859,22 @@
int ret = 0;
struct spi_nand_info *spifc;
- pr_info("spi_nand_probe------------\n");
+ /*ÅжÏÊÇ·ñΪÔöÇ¿ÐÍ°²È«Æô¶¯*/
+ if(nor_cmdline != NULL)
+ {
+ if (!strcmp(nor_cmdline, "1"))
+ {
+ g_nor_flag = 1;
+ //printk("----------EnhancedSecurity---------\n");
+ }
+ }
+
+ pr_info("----------spi_nand_probe-----------\n");
spifc = kzalloc(sizeof(*spifc), GFP_KERNEL);
if (!spifc)
return -ENOMEM;
-
+
soft_spin_lock(NAND_SFLOCK);
ret = spifc_init_resource(pdev, spifc);
@@ -1800,12 +1906,12 @@
soft_spin_unlock(NAND_SFLOCK);
return ret;
}
-
- read_only_partitons_table_init();
+ read_only_partitons_table_init();
soft_spin_unlock(NAND_SFLOCK);
platform_set_drvdata(pdev, spifc);
+ printk("----------spi_nand_probe end!-----------\n");
return 0;
failed_alloc_memery: