[Feature][ZXW-33]merge ZXW 0428 version
Change-Id: I11f167edfea428d9fab198ff00ff1364932d1b0b
diff --git a/boot/common/scripts/Makefile b/boot/common/scripts/Makefile
index ffa5724..daaa447 100755
--- a/boot/common/scripts/Makefile
+++ b/boot/common/scripts/Makefile
@@ -86,6 +86,9 @@
ifeq ($(strip $(board)),$(filter $(board),))
ram_text=0x23EF0000
V3T_RAM_TEXT_64M_UBOOT=y
+else ifeq ($(strip $(board)),$(filter $(board),vehicle_dc))
+ ram_text=0x27EF0000
+ V3T_RAM_TEXT_128M_UBOOT=y
else
ram_text=0x21EF0000
endif
@@ -124,6 +127,8 @@
export chip board key_path ram_text V3T_RAM_TEXT_64M_UBOOT
+export chip board key_path ram_text V3T_RAM_TEXT_128M_UBOOT
+
default: help
help:
diff --git a/boot/common/src/uboot/Makefile b/boot/common/src/uboot/Makefile
index 1ccbb14..245011f 100755
--- a/boot/common/src/uboot/Makefile
+++ b/boot/common/src/uboot/Makefile
@@ -291,6 +291,8 @@
GZIP = $(TOPDIR)/../../../../build/compiler/gcc-4.9.4_thumb_linux/utils/minigzip -c
ifeq ($(V3T_RAM_TEXT_64M_UBOOT),y)
export IMAGE_START = 0x23DF0000
+else ifeq ($(V3T_RAM_TEXT_128M_UBOOT),y)
+export IMAGE_START = 0x27DF0000
else
export IMAGE_START = 0x21DF0000
endif
@@ -568,6 +570,8 @@
echo "#define CPU_SHIFT 0" >./include/board.h;
ifeq ($(V3T_RAM_TEXT_64M_UBOOT),y)
echo "RAM_TEXT = 0x23DF0000" >> $(obj)board/zte/zx297520v3/config.tmp
+else ifeq ($(V3T_RAM_TEXT_128M_UBOOT),y)
+ echo "RAM_TEXT = 0x27DF0000" >> $(obj)board/zte/zx297520v3/config.tmp
else
echo "RAM_TEXT = 0x21DF0000" >> $(obj)board/zte/zx297520v3/config.tmp
endif
diff --git a/boot/common/src/uboot/arch/arm/lib/bootm.c b/boot/common/src/uboot/arch/arm/lib/bootm.c
index 8902140..feaafc4 100755
--- a/boot/common/src/uboot/arch/arm/lib/bootm.c
+++ b/boot/common/src/uboot/arch/arm/lib/bootm.c
@@ -197,7 +197,7 @@
//#ifdef CONFIG_ZX297520V3E_WATCH_CAP
#if defined(CONFIG_ZX297520V3E_WATCH_CAP) || defined (CONFIG_ZX297520V3E_VEHICLE_DC)
- memset(0x22000000, 0, 0x100000);
+ memset(ICP_CAP_BUF_ADDR, 0, ICP_CAP_BUF_LEN);
if(!read_fota_update_flag())
{
cap_poweron();
diff --git a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c
index 8282b60..5b7848d 100755
--- a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c
+++ b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c
@@ -877,7 +877,8 @@
BOOT_PRINTF(UBOOT_NOTICE, "Normal entry!\n");
if(g_ddr_size_flag == CHIP_DDR_IS_32M)
{
- g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM32_A9_SIZE;
+ //g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM32_A9_SIZE;
+ g_sys_kernel_sdram_size = DDR_BASE_LEN_AP;
}
else if(g_ddr_size_flag == CHIP_DDR_IS_64M)
{
diff --git a/boot/common/src/uboot/common/cmd_bootm.c b/boot/common/src/uboot/common/cmd_bootm.c
index 20064e9..8295a6f 100755
--- a/boot/common/src/uboot/common/cmd_bootm.c
+++ b/boot/common/src/uboot/common/cmd_bootm.c
@@ -314,7 +314,7 @@
puts ("Could not find a valid device tree\n");
return 1;
}
- images.ft_addr = CAP_DTB_ADDR;
+ images.ft_addr = DDR_BASE_CAP_DTB_ADDR;
images.ft_len = CAP_DTB_LEN;
set_working_fdt_addr(images.ft_addr);
#endif
diff --git a/boot/common/src/uboot/downloader/downloader_config.h b/boot/common/src/uboot/downloader/downloader_config.h
index d9efe61..40b7e1a 100755
--- a/boot/common/src/uboot/downloader/downloader_config.h
+++ b/boot/common/src/uboot/downloader/downloader_config.h
@@ -2,8 +2,10 @@
#define DOWNLOADER_BUFFER_BASE CONFIG_USB_DMA_BUF_ADDR
-#ifdef CONFIG_ZX297520V3T_64M_UBOOT
+#if CONFIG_ZX297520V3T_64M_UBOOT
#define DOWNLOADER_BUFFER_SIZE 0x3000000 /* 48M */
+#elif CONFIG_ZX297520V3T_128M_UBOOT
+#define DOWNLOADER_BUFFER_SIZE 0x7000000 /* 112M */
#else
#define DOWNLOADER_BUFFER_SIZE 0x1A00000 /*26M*/
#endif
diff --git a/boot/common/src/uboot/drivers/misc/load.c b/boot/common/src/uboot/drivers/misc/load.c
index 8419dca..c44dc9b 100755
--- a/boot/common/src/uboot/drivers/misc/load.c
+++ b/boot/common/src/uboot/drivers/misc/load.c
@@ -305,6 +305,7 @@
return 0;
}
+#ifdef CONFIG_ZX297520V3E_VEHICLE_DC
int fs_load_dtb_image(void)
{
char cmd[64] = {0};
@@ -320,7 +321,7 @@
run_command(cmd, 0);
flush_dcache_all();
/*2¡¢¿½±´°æ±¾Êý¾Ýµ½ÔËÐеØÖ· */
- memcpy((uchar *)CAP_DTB_ADDR,
+ memcpy((uchar *)DDR_BASE_CAP_DTB_ADDR,
(uchar *)(CONFIG_SYS_SDRAM_TEMP_BASE),
CAP_DTB_LEN);
@@ -328,6 +329,7 @@
return 0;
}
+#endif
int fs_load_m0_image(void)
{
@@ -965,7 +967,8 @@
}
if(fotaFlagInfo->boot_flag.magic != FLAGS_MAGIC)
- {
+ {
+ flush_dcache_all();
ret = flash->read(nand,(loff_t)backup_area_offset,
&fota_size,(u_char *)(fotaFlagInfo));
if(ret != 0)
@@ -995,6 +998,7 @@
}
if(fotaFlagInfo->boot_flag.magic != FLAGS_MAGIC)
{
+ flush_dcache_all();
ret = nand_read(&(nor->nor[0].mtd), (loff_t)backup_area_offset,
&fota_size, (u_char *)(fotaFlagInfo));
if(ret != 0)
diff --git a/boot/common/src/uboot/drivers/peripheral/peripheral.c b/boot/common/src/uboot/drivers/peripheral/peripheral.c
old mode 100644
new mode 100755
index 4b0d8fe..4394c7b
--- a/boot/common/src/uboot/drivers/peripheral/peripheral.c
+++ b/boot/common/src/uboot/drivers/peripheral/peripheral.c
@@ -73,7 +73,8 @@
jtag_init();
#endif
-#if 0//ref need ldo8 2.85V
+//#if 0//ref need ldo8 2.85V
+#ifdef CONFIG_ZX297520V3E_VEHICLE_DC
/*set mmc io and vccQ*/
zx234290_set_ldo8_voltage(VLDOD_1_800);
zx234290_set_ldo8_sleep_voltage(VLDOD_1_800);
diff --git a/boot/common/src/uboot/drivers/power/zx234290.c b/boot/common/src/uboot/drivers/power/zx234290.c
index 1f2f485..b6f9678 100755
--- a/boot/common/src/uboot/drivers/power/zx234290.c
+++ b/boot/common/src/uboot/drivers/power/zx234290.c
@@ -28,7 +28,7 @@
#include <power.h>
#include <zx234290.h>
#include <zx234502.h>
-
+#include <watchdog.h>
int zx234290_write_flag(UINT8 val);
@@ -181,6 +181,7 @@
return -EIO;
}
printf( " [%s][START_UP_STATUS = 0x%X] ...\n", __FUNCTION__, reg_start);
+ (*(volatile unsigned long *)(START_UP_STATUS_BASE))=reg_start;
/* ¶Á²¢ÇåZX234290_REG_USER */
ret = zx234290_i2c_read_reg(ZX234290_REG_USER, ®_user);
@@ -195,6 +196,7 @@
return -EIO;
}
printf( " [%s][USER_RESERVED = 0x%X] ...\n", __FUNCTION__, reg_user);
+ (*(volatile unsigned long *)(USER_RESERVED_BASE)) =reg_user;
/* 1. Õý³£¿ª»ú¼ì²â */
if( reg_start & PWR_ON_START_UP )
diff --git a/boot/common/src/uboot/drivers/wdt/wdt.c b/boot/common/src/uboot/drivers/wdt/wdt.c
index 5353df5..0621cb4 100644
--- a/boot/common/src/uboot/drivers/wdt/wdt.c
+++ b/boot/common/src/uboot/drivers/wdt/wdt.c
@@ -26,6 +26,7 @@
#include <watchdog.h>
#include <asm/arch/lsp_crpm.h>
+
/****************************************************************************
* Local Macros
****************************************************************************/
@@ -33,7 +34,6 @@
#define WDT_DIABLE (0x44495341) /*ascii: DISA*/
#define WDT_OFF (0x57445446) //ascii:WDTF
-#define WDT_REBOOT_RECORD_BASE (0x102410)
/*open and close wdt function for long time operation in boot.*/
#define RM_WDT_BASE (0x00148000)
diff --git a/boot/common/src/uboot/include/configs/zx297520v3.h b/boot/common/src/uboot/include/configs/zx297520v3.h
index 5e4003d..6d12147 100755
--- a/boot/common/src/uboot/include/configs/zx297520v3.h
+++ b/boot/common/src/uboot/include/configs/zx297520v3.h
@@ -66,8 +66,10 @@
/*================================================================== mmu =========== */
#define CONFIG_ENABLE_MMU 1
-#ifdef CONFIG_ZX297520V3T_64M_UBOOT
-#define CONFIG_NAND_DMA_BUF_ADDR 0x23A00000
+#if CONFIG_ZX297520V3T_64M_UBOOT
+#define CONFIG_NAND_DMA_BUF_ADDR 0x23A00000
+#elif CONFIG_ZX297520V3T_128M_UBOOT
+#define CONFIG_NAND_DMA_BUF_ADDR 0x27A00000
#else
#define CONFIG_NAND_DMA_BUF_ADDR 0x21A00000
#endif
@@ -116,18 +118,24 @@
#define CONFIG_SYS_SDRAM_BASE 0x20000800 /*2k DDR for soc test*/
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
-#ifdef CONFIG_ZX297520V3T_64M_UBOOT
+#if CONFIG_ZX297520V3T_64M_UBOOT
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64MB */
#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64MB in DDR */
#define CONFIG_SYS_SDRAM_CUTDOWN_SIZE 0x01000000
#define CONFIG_SYS_SDRAM_IMAGEFS_BASE 0x22300000
#define CONFIG_SYS_SDRAM_IMAGEFS_END 0x23000000
#define CONFIG_SYS_SDRAM_IMAGEFS_SIZE (CONFIG_SYS_SDRAM_IMAGEFS_END - CONFIG_SYS_SDRAM_IMAGEFS_BASE)
+#elif CONFIG_ZX297520V3T_128M_UBOOT
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128MB */
+#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128MB in DDR */
+#define CONFIG_SYS_SDRAM_IMAGEFS_BASE 0x25000000
+#define CONFIG_SYS_SDRAM_IMAGEFS_END 0x27000000
+#define CONFIG_SYS_SDRAM_IMAGEFS_SIZE (CONFIG_SYS_SDRAM_IMAGEFS_END - CONFIG_SYS_SDRAM_IMAGEFS_BASE)
#else
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32MB */
#define CONFIG_SYS_SDRAM_SIZE 0x02000000 /* 32MB in DDR */
#define CONFIG_SYS_SDRAM_IMAGEFS_BASE 0x20C00000
-#define CONFIG_SYS_SDRAM_IMAGEFS_END 0x21400000
+#define CONFIG_SYS_SDRAM_IMAGEFS_END 0x21400000
#define CONFIG_SYS_SDRAM_IMAGEFS_SIZE (CONFIG_SYS_SDRAM_IMAGEFS_END - CONFIG_SYS_SDRAM_IMAGEFS_BASE)
#endif
diff --git a/boot/common/src/uboot/include/image.h b/boot/common/src/uboot/include/image.h
index 8d65f54..1efa352 100755
--- a/boot/common/src/uboot/include/image.h
+++ b/boot/common/src/uboot/include/image.h
@@ -58,7 +58,6 @@
#define CONFIG_SHA1 /* and SHA1 */
#endif
-#define CAP_DTB_ADDR 0x22100000
#define CAP_DTB_LEN 0x10000
/*
diff --git a/boot/common/src/uboot/include/watchdog.h b/boot/common/src/uboot/include/watchdog.h
index caadf84..b57ed0b 100644
--- a/boot/common/src/uboot/include/watchdog.h
+++ b/boot/common/src/uboot/include/watchdog.h
@@ -27,6 +27,10 @@
#ifndef _WATCHDOG_H_
#define _WATCHDOG_H_
+#define WDT_REBOOT_RECORD_BASE (IRAM1_BASE_ADDR+0x2410)
+#define START_UP_STATUS_BASE (IRAM1_BASE_ADDR+0x2420)
+#define USER_RESERVED_BASE (IRAM1_BASE_ADDR+0x2424)
+
int wdt_open(void);
int wdt_close(void);
int wdt_get_reboot_reason(void);