commit bdd93d52cf43d2991561d70e238bf11e422b794b
author xf.li <xf.li@mobiletek.cn> Fri May 12 07:10:14 2023 -0700
committer xf.li <xf.li@mobiletek.cn> Fri May 12 07:10:14 2023 -0700
tree e3c665259c7118a7df767253a572274319e37cbf
parent db4f43f0150836941f56a4d2e2923f7182328607

[Feature][ZXW-33]merge ZXW 0428 version

Change-Id: I11f167edfea428d9fab198ff00ff1364932d1b0b

boot/common/src/uboot/include/configs/zx297520v3.h

diff --git a/boot/common/src/uboot/include/configs/zx297520v3.h b/boot/common/src/uboot/include/configs/zx297520v3.h
index 5e4003d..6d12147 100755
--- a/boot/common/src/uboot/include/configs/zx297520v3.h
+++ b/boot/common/src/uboot/include/configs/zx297520v3.h
@@ -66,8 +66,10 @@
 
 /*================================================================== mmu =========== */
 #define CONFIG_ENABLE_MMU           1
-#ifdef CONFIG_ZX297520V3T_64M_UBOOT
-#define CONFIG_NAND_DMA_BUF_ADDR    0x23A00000 
+#if CONFIG_ZX297520V3T_64M_UBOOT
+#define CONFIG_NAND_DMA_BUF_ADDR    0x23A00000
+#elif CONFIG_ZX297520V3T_128M_UBOOT
+#define CONFIG_NAND_DMA_BUF_ADDR    0x27A00000
 #else
 #define CONFIG_NAND_DMA_BUF_ADDR    0x21A00000
 #endif
@@ -116,18 +118,24 @@
 #define CONFIG_SYS_SDRAM_BASE	    0x20000800              /*2k DDR for soc test*/
 #define PHYS_SDRAM_1		        CONFIG_SYS_SDRAM_BASE	/* SDRAM Bank #1	*/
 
-#ifdef CONFIG_ZX297520V3T_64M_UBOOT
+#if CONFIG_ZX297520V3T_64M_UBOOT
 #define PHYS_SDRAM_1_SIZE	        	0x04000000      /* 64MB */
 #define CONFIG_SYS_SDRAM_SIZE	    	0x04000000	    /* 64MB in DDR */
 #define CONFIG_SYS_SDRAM_CUTDOWN_SIZE	0x01000000
 #define CONFIG_SYS_SDRAM_IMAGEFS_BASE	0x22300000
 #define CONFIG_SYS_SDRAM_IMAGEFS_END	0x23000000
 #define CONFIG_SYS_SDRAM_IMAGEFS_SIZE	(CONFIG_SYS_SDRAM_IMAGEFS_END - CONFIG_SYS_SDRAM_IMAGEFS_BASE)
+#elif CONFIG_ZX297520V3T_128M_UBOOT
+#define PHYS_SDRAM_1_SIZE	        	0x08000000     	/* 128MB */
+#define CONFIG_SYS_SDRAM_SIZE	    	0x08000000	   	/* 128MB in DDR */
+#define CONFIG_SYS_SDRAM_IMAGEFS_BASE	0x25000000
+#define CONFIG_SYS_SDRAM_IMAGEFS_END	0x27000000
+#define CONFIG_SYS_SDRAM_IMAGEFS_SIZE	(CONFIG_SYS_SDRAM_IMAGEFS_END - CONFIG_SYS_SDRAM_IMAGEFS_BASE)
 #else
 #define PHYS_SDRAM_1_SIZE	        	0x02000000     	/* 32MB */
 #define CONFIG_SYS_SDRAM_SIZE	    	0x02000000	   	/* 32MB in DDR */
 #define CONFIG_SYS_SDRAM_IMAGEFS_BASE	0x20C00000
-#define CONFIG_SYS_SDRAM_IMAGEFS_END		0x21400000
+#define CONFIG_SYS_SDRAM_IMAGEFS_END	0x21400000
 #define CONFIG_SYS_SDRAM_IMAGEFS_SIZE	(CONFIG_SYS_SDRAM_IMAGEFS_END - CONFIG_SYS_SDRAM_IMAGEFS_BASE)
 #endif