[Feature][ZXW-237]merge 4Gb DDR patch
Only Configure: No
Affected branch: master
Affected module: unknow
Is it affected on both ZXIC and MTK: only ZXIC
Self-test: Yes
Doc Update: No
Change-Id: Ic1d54476f67c48ed9033043c248b6ae7ae76515e
diff --git a/boot/common/src/loader/drivers/ddr.c b/boot/common/src/loader/drivers/ddr.c
old mode 100644
new mode 100755
index 0bcec12..15b91f3
--- a/boot/common/src/loader/drivers/ddr.c
+++ b/boot/common/src/loader/drivers/ddr.c
@@ -496,7 +496,7 @@
else
{
#if _DDR_BYPASS_MODE
- if(flag == CHIP_DDR_IS_256M)
+ if((flag == CHIP_DDR_IS_256M)||(flag == CHIP_DDR_IS_512M))
__REG( 0x00150064 ) = 0x00130014 ; //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x13 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0x0a
else
__REG( 0x00150064 ) = 0x00260014 ; //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x26 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0x14
@@ -529,7 +529,7 @@
__REG( 0x00150184 ) = 0x00800100 ; //VALUE_ZQCTL1 / t_zq_reset_nop:RW:20:10:=0x8 t_zq_short_interval_x1024:RW:0:20:=0x100
#else
- if(flag == CHIP_DDR_IS_256M)
+ if((flag == CHIP_DDR_IS_256M)||(flag == CHIP_DDR_IS_512M))
__REG( 0x00150064 ) = 0x0018001a ; //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x18 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0x0d
else
__REG( 0x00150064 ) = 0x0030001a ; //VALUE_RFSHTMG / t_rfc_nom_x32(trefi):RW:16:12:=0x26 lpddr3_trefbw_en:RW:15:1:=0x0 t_rfc_min:RW:0:9:=0x14
@@ -590,6 +590,20 @@
__REG( 0x00150210 ) = 0x00000f0f ; //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
}
+ else if((flag == CHIP_DDR_IS_128M)||(flag == CHIP_DDR_IS_256M))
+ {
+ __REG( 0x00150204 ) = 0x00070707 ; //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+ __REG( 0x00150208 ) = 0x00000000 ; //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+ __REG( 0x0015020c ) = 0x0f000000 ; //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0xf addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+ __REG( 0x00150210 ) = 0x00000f0f ; //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+
+ }
+ else if(flag == CHIP_DDR_IS_512M){
+ __REG( 0x00150204 ) = 0x00080808 ; //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
+ __REG( 0x00150208 ) = 0x00000000 ; //VALUE_ADDRMAP2 / addrmap_col_b5:RW:24:4:=0x0 addrmap_col_b4:RW:16:4:=0x0 addrmap_col_b3:RW:8:4:=0x0 addrmap_col_b2:RW:0:4:=0x0
+ __REG( 0x0015020c ) = 0x00000000 ; //VALUE_ADDRMAP3 / addrmap_col_b9:RW:24:4:=0x0 addrmap_col_b8:RW:16:4:=0x0 addrmap_col_b7:RW:8:4:=0x0 addrmap_col_b6:RW:0:4:=0x0
+ __REG( 0x00150210 ) = 0x00000f0f ; //VALUE_ADDRMAP4 / addrmap_col_b11:RW:8:4:=0xf addrmap_col_b10:RW:0:4:=0xf
+ }
else
{
__REG( 0x00150204 ) = 0x00070707 ; //VALUE_ADDRMAP1 / addrmap_bank_b2:RW:16:4:=0x7 addrmap_bank_b1:RW:8:4:=0x7 addrmap_bank_b0:RW:0:4:=0x7
@@ -609,12 +623,21 @@
__REG( 0x00150214 ) = 0x05050505 ; //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
__REG( 0x00150218 ) = 0x0f0f0f05 ; //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
}
-
+ else if(flag == CHIP_DDR_IS_128M)
+ {
+ __REG( 0x00150214 ) = 0x06060606 ; //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+ __REG( 0x00150218 ) = 0x0f0f0f06 ; //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0xf addrmap_row_b12:RW:0:4:=0x6
+ }
else if(flag == CHIP_DDR_IS_256M)
{
__REG( 0x00150214 ) = 0x06060606 ; //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
__REG( 0x00150218 ) = 0x0f0f0606 ; //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0x6 addrmap_row_b12:RW:0:4:=0x6
}
+ else if(flag == CHIP_DDR_IS_512M)
+ {
+ __REG( 0x00150214 ) = 0x07070707 ; //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
+ __REG( 0x00150218 ) = 0x0f0f0707 ; //VALUE_ADDRMAP6 / addrmap_row_b15:RW:24:4:=0xf addrmap_row_b14:RW:16:4:=0xf addrmap_row_b13:RW:8:4:=0x6 addrmap_row_b12:RW:0:4:=0x6
+ }
else
{
__REG( 0x00150214 ) = 0x06060606 ; //VALUE_ADDRMAP5 / addrmap_row_b11:RW:24:4:=0x6 addrmap_row_b2_10:RW:16:4:=0x6 addrmap_row_b1:RW:8:4:=0x6 addrmap_row_b0:RW:0:4:=0x6
diff --git a/boot/common/src/loader/drivers/efuse.c b/boot/common/src/loader/drivers/efuse.c
index 2b2cc08..ae3ebd3 100755
--- a/boot/common/src/loader/drivers/efuse.c
+++ b/boot/common/src/loader/drivers/efuse.c
@@ -53,6 +53,11 @@
{
ddr_flag = CHIP_DDR_256M;
}
+ else if(((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOSCC_GW_NYB_4G_DDR)
+ ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOGG_GW_NYB_4G_DDR))
+ {
+ ddr_flag = CHIP_DDR_512M;
+ }
else
{
ddr_flag = CHIP_DDR_128M;
diff --git a/boot/common/src/loader/lib/board.c b/boot/common/src/loader/lib/board.c
index 0a55f70..f6651cb 100755
--- a/boot/common/src/loader/lib/board.c
+++ b/boot/common/src/loader/lib/board.c
@@ -199,10 +199,18 @@
else if(get_ddr_flag() == CHIP_DDR_IS_128M)
{
ddr_init(CHIP_DDR_IS_128M);
+ }
+ else if(get_ddr_flag() == CHIP_DDR_IS_256M)
+ {
+ ddr_init(CHIP_DDR_IS_256M);
+ }
+ else if(get_ddr_flag() == CHIP_DDR_IS_512M)
+ {
+ ddr_init(CHIP_DDR_IS_512M);
}
else
{
- ddr_init(CHIP_DDR_IS_256M);
+ ddr_init(CHIP_DDR_IS_128M);
}
usb_apcore_poweroff();
@@ -377,10 +385,18 @@
else if(get_ddr_flag() == CHIP_DDR_IS_128M)
{
ddr_init(CHIP_DDR_IS_128M);
+ }
+ else if(get_ddr_flag() == CHIP_DDR_IS_256M)
+ {
+ ddr_init(CHIP_DDR_IS_256M);
+ }
+ else if(get_ddr_flag() == CHIP_DDR_IS_512M)
+ {
+ ddr_init(CHIP_DDR_IS_512M);
}
else
{
- ddr_init(CHIP_DDR_IS_256M);
+ ddr_init(CHIP_DDR_IS_128M);
}
diff --git a/boot/common/src/uboot/arch/arm/lib/bootm.c b/boot/common/src/uboot/arch/arm/lib/bootm.c
index 41cc4c1..914259d 100755
--- a/boot/common/src/uboot/arch/arm/lib/bootm.c
+++ b/boot/common/src/uboot/arch/arm/lib/bootm.c
@@ -302,6 +302,11 @@
size[bank] = DDR_BASE_LEN_CAP + 0x8000000;
reg32(IRAM_BASE_ADDR_BOOT_DDR) = (DDR_BASE_LEN_CAP + 0x8000000);
}
+ else if(g_ddr_size_flag == CHIP_DDR_IS_512M)
+ {
+ size[bank] = DDR_BASE_LEN_CAP + 0x18000000;
+ reg32(IRAM_BASE_ADDR_BOOT_DDR) = (DDR_BASE_LEN_CAP + 0x18000000);
+ }
else
{
debug("ddr size is error.\n");
diff --git a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c
index 0c2138f..23bf246 100755
--- a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c
+++ b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c
@@ -982,10 +982,18 @@
else if(g_ddr_size_flag == CHIP_DDR_IS_128M)
{
g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM128_RECOVERY_A9_SIZE;
+ }
+ else if(g_ddr_size_flag == CHIP_DDR_IS_256M)
+ {
+ g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM256_RECOVERY_A9_SIZE;
+ }
+ else if(g_ddr_size_flag == CHIP_DDR_IS_512M)
+ {
+ g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM512_RECOVERY_A9_SIZE;
}
else
{
- g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM256_RECOVERY_A9_SIZE;
+ g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM128_RECOVERY_A9_SIZE;
}
ret = fs_load_arm_image_linux(ARM_RECOVERY_USERDATA_IMAGE); /*FOTA-UPDATE*/
diff --git a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc_ref.c b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc_ref.c
index 27dfc10..0872ca4 100755
--- a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc_ref.c
+++ b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc_ref.c
@@ -982,10 +982,18 @@
else if(g_ddr_size_flag == CHIP_DDR_IS_128M)
{
g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM128_RECOVERY_A9_SIZE;
+ }
+ else if(g_ddr_size_flag == CHIP_DDR_IS_256M)
+ {
+ g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM256_RECOVERY_A9_SIZE;
+ }
+ else if(g_ddr_size_flag == CHIP_DDR_IS_512M)
+ {
+ g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM512_RECOVERY_A9_SIZE;
}
else
{
- g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM256_RECOVERY_A9_SIZE;
+ g_sys_kernel_sdram_size = CONFIG_SYS_SDRAM128_RECOVERY_A9_SIZE;
}
ret = fs_load_arm_image_linux(ARM_RECOVERY_USERDATA_IMAGE); /*FOTA-UPDATE*/
diff --git a/boot/common/src/uboot/downloader/cmd_efuse_program.c b/boot/common/src/uboot/downloader/cmd_efuse_program.c
index ffd2e8f..ddc2275 100755
--- a/boot/common/src/uboot/downloader/cmd_efuse_program.c
+++ b/boot/common/src/uboot/downloader/cmd_efuse_program.c
@@ -37,6 +37,7 @@
#define BOARD_TYPE_ZX297520V3E32M 0x1
#define BOARD_TYPE_ZX297520V3E64M 0x2
#define BOARD_TYPE_ZX297520V3E256M 0x3
+#define BOARD_TYPE_ZX297520V3E512M 0x4
#define BOARD_TYPE_UNKNOWN 0xFF
@@ -249,6 +250,12 @@
{
printf("chip_flag=0x%x board_type is V3E.\n", chip_flag);
board_type = BOARD_TYPE_ZX297520V3E256M;
+ }
+ else if((chip_flag == ZX297520V3ECOSCC_GW_NYB_4G_DDR)
+ ||(chip_flag == ZX297520V3ECOGG_GW_NYB_4G_DDR))
+ {
+ printf("chip_flag=0x%x board_type is V3E.\n", chip_flag);
+ board_type = BOARD_TYPE_ZX297520V3E512M;
}
else if((chip_flag == ZX297520V3ECO_GW_WINBD_256M_DDR)
||(chip_flag == ZX297520V3ECO_GW_UNILC_256M_DDR)
diff --git a/boot/common/src/uboot/drivers/efuse/efuse.c b/boot/common/src/uboot/drivers/efuse/efuse.c
index 9d0937e..30bf2b3 100755
--- a/boot/common/src/uboot/drivers/efuse/efuse.c
+++ b/boot/common/src/uboot/drivers/efuse/efuse.c
@@ -238,6 +238,12 @@
{
g_ddr_size_flag = CHIP_DDR_IS_256M;
BOOT_PRINTF(UBOOT_NOTICE, "secure_flag=0x%x.\n", psEfuseInfo->secure_flag);
+ }
+ else if(((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOSCC_GW_NYB_4G_DDR)
+ ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOGG_GW_NYB_4G_DDR))
+ {
+ g_ddr_size_flag = CHIP_DDR_IS_512M;
+ BOOT_PRINTF(UBOOT_NOTICE, "secure_flag=0x%x.\n", psEfuseInfo->secure_flag);
}
else
{
diff --git a/boot/common/src/uboot/drivers/mtd/nand/nand.c b/boot/common/src/uboot/drivers/mtd/nand/nand.c
index 92aa855..5c471ca 100755
--- a/boot/common/src/uboot/drivers/mtd/nand/nand.c
+++ b/boot/common/src/uboot/drivers/mtd/nand/nand.c
@@ -167,7 +167,9 @@
if(one_flag == 0){
/*¶ÁȡоƬid*/
if((reg32(0x0121b040)>>8) == ZX297520V3ECOGG_GW_NYC_NOR_2G_DDR
- ||(reg32(0x0121b040)>>8) == ZX297520V3ECOSC_GW_NYC_NOR_2G_DDR)
+ ||(reg32(0x0121b040)>>8) == ZX297520V3ECOSC_GW_NYC_NOR_2G_DDR
+ ||(reg32(0x0121b040)>>8) == ZX297520V3ECOSCC_GW_NYB_4G_DDR
+ ||(reg32(0x0121b040)>>8) == ZX297520V3ECOGG_GW_NYB_4G_DDR)
{
g_nor_flag = 1;
efuse_get_data();
diff --git a/boot/common/src/uboot/include/configs/zx297520v3.h b/boot/common/src/uboot/include/configs/zx297520v3.h
index ea771fa..b947ab2 100755
--- a/boot/common/src/uboot/include/configs/zx297520v3.h
+++ b/boot/common/src/uboot/include/configs/zx297520v3.h
@@ -160,9 +160,13 @@
#define CONFIG_SYS_SDRAM128_A9_SIZE 0x07BC0000 //123.75M
#define CONFIG_SYS_SDRAM128_RECOVERY_A9_SIZE 0x08000000
-#define CONFIG_SYS_SDRAM256_A9_SIZE 0x0FBC0000 //251S.75M
+#define CONFIG_SYS_SDRAM256_A9_SIZE 0x0FBC0000 //251.75M
#define CONFIG_SYS_SDRAM256_RECOVERY_A9_SIZE 0x10000000
+
+#define CONFIG_SYS_SDRAM512_A9_SIZE 0x1FBC0000 //507.75M
+#define CONFIG_SYS_SDRAM512_RECOVERY_A9_SIZE 0x20000000
+
#define AMT_MODE_FLAG 0x544D