[Feature][ZXW-452]merge P54U02 version

Only Configure: No
Affected branch: master
Affected module: unknow
Is it affected on both ZXIC and MTK: only ZXIC
Self-test: Yes
Doc Update: No

Change-Id: I17e6795ab66e2b9d1cbbfec4b7c0028d666e177d
diff --git a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_mdl_ab.c b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_mdl_ab.c
index cb86245..8b0e1ae 100755
--- a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_mdl_ab.c
+++ b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_mdl_ab.c
@@ -698,6 +698,7 @@
     {
         fotaFlagInfo.boot_fota_flag.boot_to = DUAL_SYSTEM2;
 		fotaFlagInfo.boot_fota_flag.system = system_status;
+		fotaFlagInfo.boot_fota_flag.fota_status = 1;
 		/*crc32*/
 		fotaFlagInfo.crc32 = 0;
 		crc32init_le();
@@ -800,6 +801,7 @@
     {
         fotaFlagInfo.boot_fota_flag.boot_to = DUAL_SYSTEM;
 		fotaFlagInfo.boot_fota_flag.system2 = system_status;
+		fotaFlagInfo.boot_fota_flag.fota_status = 1;
 		/*crc32*/
 		fotaFlagInfo.crc32 = 0;
 		crc32init_le();
diff --git a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c
index 0e5d5a7..0c2138f 100755
--- a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c
+++ b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc.c
@@ -699,6 +699,7 @@
     {
         fotaFlagInfo.boot_fota_flag.boot_to = DUAL_SYSTEM2;
 		fotaFlagInfo.boot_fota_flag.system = system_status;
+		fotaFlagInfo.boot_fota_flag.fota_status = 1;
 		/*crc32*/
 		fotaFlagInfo.crc32 = 0;
 		crc32init_le();
@@ -801,6 +802,7 @@
     {
         fotaFlagInfo.boot_fota_flag.boot_to = DUAL_SYSTEM;
 		fotaFlagInfo.boot_fota_flag.system2 = system_status;
+		fotaFlagInfo.boot_fota_flag.fota_status = 1;
 		/*crc32*/
 		fotaFlagInfo.crc32 = 0;
 		crc32init_le();
diff --git a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc_ref.c b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc_ref.c
index 8c0b388..30e4518 100755
--- a/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc_ref.c
+++ b/boot/common/src/uboot/board/zte/zx297520v3/zx297520v3_vehicle_dc_ref.c
@@ -699,6 +699,7 @@
     {
         fotaFlagInfo.boot_fota_flag.boot_to = DUAL_SYSTEM2;
 		fotaFlagInfo.boot_fota_flag.system = system_status;
+		fotaFlagInfo.boot_fota_flag.fota_status = 1;
 		/*crc32*/
 		fotaFlagInfo.crc32 = 0;
 		crc32init_le();
@@ -801,6 +802,7 @@
     {
         fotaFlagInfo.boot_fota_flag.boot_to = DUAL_SYSTEM;
 		fotaFlagInfo.boot_fota_flag.system2 = system_status;
+		fotaFlagInfo.boot_fota_flag.fota_status = 1;
 		/*crc32*/
 		fotaFlagInfo.crc32 = 0;
 		crc32init_le();
diff --git a/boot/common/src/uboot/drivers/misc/load.c b/boot/common/src/uboot/drivers/misc/load.c
index 2c9c8e7..5c3a2b3 100755
--- a/boot/common/src/uboot/drivers/misc/load.c
+++ b/boot/common/src/uboot/drivers/misc/load.c
@@ -65,6 +65,9 @@
 	uint8_t p_uncompress_size[8];
 }lzma_header_t;
 
+extern void crc32init_le(void);
+extern unsigned int crc32_le(unsigned int crc, unsigned char const *p, size_t len);
+
 extern uint32_t ztelzma_compresssize;
 extern int lzmanodeflag;
 #endif
@@ -1222,6 +1225,9 @@
 	uint32_t  fota_size = sizeof(T_FLAGS_INFO);
 	nand_info_t *nand = &nand_info[nand_curr_device];
 	struct fsl_qspi *nor = &spi_nor_flash;
+	unsigned long crc = 0;
+	unsigned long crc_cal = 0;
+	u32 crc_size = sizeof(T_FLAGS_INFO);
 
 	flush_dcache_all();
     flash_dmabuf_disable_flag = 1;
@@ -1277,8 +1283,15 @@
 			BOOT_PRINTF(UBOOT_ERR, "[%s]: read the flags error!\n", part_name);
 			return 1;
 		}
+
+		/*crc32УÑé*/
+		crc = fotaFlagInfo->crc32;
+		fotaFlagInfo->crc32 = 0;
+		crc32init_le();
+    	crc_cal = crc32_le(0,(unsigned char*)fotaFlagInfo,crc_size);
+		printf("crc is 0x%x,crc_cal is 0x%x\n",crc,crc_cal);
 		
-		if(fotaFlagInfo->magic_start != FLAGS_MAGIC)
+		if(fotaFlagInfo->magic_start != FLAGS_MAGIC || (crc!= crc_cal && crc != 0))
 		{	
 			flush_dcache_all();
 			ret = flash->read(nand,(loff_t)backup_area_offset,
@@ -1294,7 +1307,20 @@
 			{
 	            printf("flags magic err.\n");
 			    return -1;
-			}	
+			}
+
+			/*crc32УÑé*/
+			crc = fotaFlagInfo->crc32;
+			fotaFlagInfo->crc32 = 0;
+			crc32init_le();
+	    	crc_cal = crc32_le(0,(unsigned char*)fotaFlagInfo,crc_size);
+
+			if(crc!= crc_cal && crc != 0)
+			{
+	            printf("flags crc err.\n");
+			    return -1;
+			}
+			
 		}
 	}
 	else if(type == IF_TYPE_NOR)
diff --git a/boot/common/src/uboot/drivers/mtd/nand/spi_nand.c b/boot/common/src/uboot/drivers/mtd/nand/spi_nand.c
index f5be951..26da064 100755
--- a/boot/common/src/uboot/drivers/mtd/nand/spi_nand.c
+++ b/boot/common/src/uboot/drivers/mtd/nand/spi_nand.c
@@ -773,7 +773,7 @@
 	.offs =	4,
 	.len = 4,
 	.veroffs = 20,
-	.maxblocks = 16,
+	.maxblocks = 12,
 	.pattern = bbt_pattern,
 };
 
@@ -784,7 +784,7 @@
 	.offs =	4,
 	.len = 4,
 	.veroffs = 20,
-	.maxblocks = 16,
+	.maxblocks = 12,
 	.pattern = mirror_pattern,
 };
 
diff --git a/boot/common/src/uboot/drivers/power/zx234290.c b/boot/common/src/uboot/drivers/power/zx234290.c
index b6f9678..90a52e2 100755
--- a/boot/common/src/uboot/drivers/power/zx234290.c
+++ b/boot/common/src/uboot/drivers/power/zx234290.c
@@ -355,6 +355,7 @@
 int pmu_init(void)
 {
     int ret = 0;
+	uchar reg_val = 0;
     struct pmu_opt pmu = {NULL};
 
     /* GPIO init */
@@ -381,7 +382,17 @@
     }
 	*/
 	ret = zx234290_get_boot_reason_prev();
-
+	ret +=zx234290_i2c_read_reg(ZX234297_REG_ADDR_SINK_CONTROL,&reg_val);
+	if(reg_val==0x7f){//means 296G C
+		reg_val = 0xff;//define to 296
+		ret+=zx234290_i2c_write_reg(ZX234297_REG_ADDR_SINK_CONTROL,&reg_val);
+	}
+	
+	if (ret != SUCCESS)
+	{
+		printf( "[%s]set 0x29 error ret=0x%x!\n", __FUNCTION__,ret);
+	}
+	
     return ret;
 }
 
diff --git a/boot/common/src/uboot/include/zx234290.h b/boot/common/src/uboot/include/zx234290.h
index 79b1bac..2c0853f 100755
--- a/boot/common/src/uboot/include/zx234290.h
+++ b/boot/common/src/uboot/include/zx234290.h
@@ -57,6 +57,7 @@
 #define ZX234290_REG_ADC_ADC1LSB	0x26
 #define ZX234290_REG_ADC_VBATMSB	0x23	/* CHANNEL 2	*/
 #define ZX234290_REG_ADC_VBATLSB	0x24
+#define ZX234297_REG_ADDR_SINK_CONTROL	0X29
 
 #define ZX234290_REG_RTC_CONTROL2	0x31
 #define	RTC_CONTROL2_TIE			(1 << 0)