[Bugfix][T106][bug-view-1951][codec] es8389 Calling without sound - solving i2c address offset problem.
Only Configure:No
Affected branch:master
Affected module:codec
Is it affected on both ZXIC and MTK:only ZXIC
Self-test:Yes
Doc Update:Yes
Change-Id: Iead311130d05ba910cd9d28ef1819519c6375378
diff --git a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/codecs/es8389.c b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/codecs/es8389.c
index 314e0ac..37e62cc 100644
--- a/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/codecs/es8389.c
+++ b/cap/zx297520v3/zxic_code/zxic_source/linux-5.10/sound/soc/codecs/es8389.c
@@ -59,6 +59,10 @@
static const DECLARE_TLV_DB_SCALE(alc_target_tlv, -3200, 200, 0);
static const DECLARE_TLV_DB_SCALE(alc_max_level, -3200, 200, 0);
+static int es8389_set_bias_level(struct snd_soc_component *codec, enum snd_soc_bias_level level);
+extern int zx29_i2s_config_sleep_pin(void);
+extern int zx29_i2s_config_default_pin(void);
+
static const char *const alc[] = {
"ALC OFF",
"ADCR ALC ON",
@@ -599,6 +603,8 @@
dev_warn(codec->dev, "Clock coefficients do not match");
}
+ es8389_set_bias_level(codec, SND_SOC_BIAS_ON);
+
return 0;
}
@@ -612,6 +618,7 @@
switch (level) {
case SND_SOC_BIAS_ON:
printk("chenli_es8389 %s %d\n", __FUNCTION__,__LINE__);
+ regmap_write(es8389->regmap, ES8389_MASTER_CLK_REG02, 0x01);
regmap_update_bits(es8389->regmap, ES8389_HPSW_REG69, 0x20, 0x20);
regmap_write(es8389->regmap, ES8389_ANA_CTL1_REG61, 0xD9);
regmap_write(es8389->regmap, ES8389_ADC_EN_REG64, 0x8F);
@@ -635,7 +642,7 @@
regmap_write(es8389->regmap, ES8389_ANA_CTL1_REG61, 0x59);
regmap_write(es8389->regmap, ES8389_ADC_EN_REG64, 0x00);
regmap_write(es8389->regmap, ES8389_CLK_OFF1_REG03, 0x00);
- regmap_write(es8389->regmap, ES8389_RESET_REG00, 0x7E);
+ regmap_write(es8389->regmap, ES8389_RESET_REG00, 0x3E);
regmap_update_bits(es8389->regmap, ES8389_DAC_INV_REG45, 0x80, 0x80);
usleep_range(8000, 8500);
regmap_update_bits(es8389->regmap, ES8389_DAC_INV_REG45, 0x80, 0x00);
@@ -680,6 +687,7 @@
0x03, 0x00);
} else {
printk("chenli_es8389 %s %d\n", __FUNCTION__,__LINE__);
+ regmap_write(es8389->regmap, ES8389_ADC_MUTE_REG2F, 0xC0);
regmap_update_bits(es8389->regmap, ES8389_ADC_HPF1_REG24, 0x0f, 0x0a);
regmap_update_bits(es8389->regmap, ES8389_ADC_HPF2_REG25, 0x0f, 0x0a);
regmap_update_bits(es8389->regmap, ES8389_ADC_REG20,
@@ -770,8 +778,8 @@
regmap_write(es8389->regmap, ES8389_SYSTEM_REG1B, 0x01);
regmap_write(es8389->regmap, ES8389_SYSTEM_REG1C, 0x11);
- regmap_write(es8389->regmap, ES8389_CHIP_MISC_REGF0, 0x12);
- regmap_write(es8389->regmap, ES8389_MASTER_CLK_REG02, 0x01);
+ regmap_write(es8389->regmap, ES8389_CHIP_MISC_REGF0, 0x13);
+ regmap_write(es8389->regmap, ES8389_MASTER_CLK_REG02, 0x00);
regmap_write(es8389->regmap, ES8389_CLK_DIV1_REG04, 0x00);
regmap_write(es8389->regmap, ES8389_CLK_MUL_REG05, 0x10);
regmap_write(es8389->regmap, ES8389_CLK_MUX1_REG06, 0x00);
@@ -785,7 +793,7 @@
regmap_write(es8389->regmap, ES8389_OSC_CLK_REG0F, 0x00);
regmap_write(es8389->regmap, ES8389_ADC_REG21, 0x1F);
regmap_write(es8389->regmap, ES8389_ADC_REG22, 0x7F);
- regmap_write(es8389->regmap, ES8389_ADC_MUTE_REG2F, 0xC0);
+ regmap_write(es8389->regmap, ES8389_ADC_MUTE_REG2F, 0xF0);
regmap_write(es8389->regmap, ES8389_SYSTEM_REG30, 0xF4);
regmap_write(es8389->regmap, ES8389_DAC_REG41, 0x7F);
regmap_write(es8389->regmap, ES8389_DAC_REG42, 0x7F);
@@ -922,7 +930,7 @@
es8389->mclk_src = ES8389_MCLK_SOURCE;
}
- es8389->mclk_src = ES8389_MCLK_PIN;
+ es8389->mclk_src = ES8389_SCLK_PIN;
ret = device_property_read_u8(codec->dev, "everest,adc-slot", &es8389->adc_slot);
if (ret != 0) {
@@ -962,8 +970,6 @@
}
-extern int zx29_i2s_config_sleep_pin(void);
-extern int zx29_i2s_config_default_pin(void);
static int component_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
@@ -977,8 +983,7 @@
if (ret) {
pr_err("failed to enable mclk");
}
- }
- es8389_init(component);
+ }
ret = zx29_i2s_config_default_pin();
if(ret < 0) {
pr_err("%s select state failure %d !! \n", __func__, ret);