UICC_debug[UICC_debug_count][0] = 2;  
UICC_debug[UICC_debug_count][1] = UICC_main_ctrl_state;
UICC_debug[UICC_debug_count++][2] = event;

typedef enum /* UICC interrupt events */
{
  /* 0x00  (0) */  UICC_DUMMY_INT_EVENT,
  /* 0x01  (1) */  UICC_TIMER_EXPIRED,          
  /* 0x02  (2) */  UICC_GUARD_TIMER_EXPIRED,
  /* 0x03  (3) */  UICC_CHARACTER_OK,
  /* 0x04  (4) */  UICC_T0_END,
  /* 0x05  (5) */  UICC_T1_END,
  /* 0x06  (6) */  UICC_DMA_END,
  /* 0x07  (7) */  UICC_PARITY_ERROR,
  /* 0x08  (8) */  UICC_OVERRUN_ERROR,
  /* 0x09  (9) */  UICC_CARD_IN,
  /* 0x0A (10) */  UICC_CARD_OUT,
  /* 0x0B (11) */  UICC_CHTIMEOUT,
  /* 0x0C (12) */  UICC_T1_PARITY_ERROR,
  /* 0x0D (13) */  UICC_T1_BWT_EXPIRED,
  /* 0x0E (14) */  UICC_UNKNOWN_INT,
  /* 0x0F (15) */  UICC_FIFO_INT,
  /* 0x10 (16) */  UICC_RX_LSREQ,  
  /* 0x11 (17) */  UICC_TX_LSREQ,  
  /* 0x12 (18) */  UICC_RX_SREQ,  
  /* 0x13 (19) */  UICC_TX_SREQ,    
  /* 0x14 (20) */  UICC_RX_LBREQ,  
  /* 0x15 (21) */  UICC_TX_LBREQ,  
  /* 0x16 (22) */  UICC_RX_BREQ,  
  /* 0x17 (23) */  UICC_TX_BREQ,  
  /* 0x18 (24) */  UICC_TXF_OFL_IRQ,  
  /* 0x19 (25) */  UICC_RXF_UFL_IRQ,
  /* 0x1A (26) */ UICC_FIFO_UNKNOWN_INT,
  /* 0x1B (27) */  UICC_LAST_INT_EVENT
} T_UICC_INT_EVENTS;

typedef enum /* UICC T0 Command handler events */
{
  UICC_INITIATE_CMD  = UICC_LAST_INT_EVENT,
  UICC_STOP_CMD_CLOCK,
  UICC_RESET_CMD,
  UICC_LAST_CMD_EVENT
} T_UICC_T0_CMD_EVENTS;


UICC_card_ctrl 0
typedef enum /* UICC Card control states */
{
  UICC_CARD_NONE =0,
  UICC_INACTIVE,
  UICC_COLD_ACTIVATION,
  UICC_WARM_ACTIVATION,
  UICC_COLD_PPS_DETERMINATION,

  UICC_WARM_PPS_DETERMINATION,
  UICC_IDLE = 6,
  UICC_BUSY = 7,
  UICC_TESTMODE,
  UICC_CARD_IN_OUT_DETECTING
} T_UICC_CARD_CONTROL_STATE;
typedef enum /* UICC card control events */
{
  UICC_DUMMY_EVENT,
   
  UICC_ATR_OK =1,                  
  UICC_ATR_FAILED_NO_ANSWER,    
  UICC_ATR_FAILED,              
                                
  UICC_PPS_OK,                 
  UICC_PPS_NOT_NEEDED,         
  UICC_PPS_NOT_COMPLETE,        
  UICC_PPS_FAILED,              
  UICC_PPS_INITIATE_WARM_RESET, 

  UICC_INSTRUCTION_SUCCEEDED,
  UICC_INSTRUCTION_FAILED,  

  UICC_INSTRUCTION_REQUESTED,  
  UICC_COLD_RESET_REQUESTED,
  UICC_WARM_RESET_REQUESTED,
  UICC_DEACTIVATION_REQUESTED,

  UICC_TESTMODE_REQUESTED,     

  UICC_CARD_INSERTED,
  UICC_CARD_REMOVED
} T_UICC_CARD_CTRL_EVENT;
UICC_debug[UICC_debug_count][0] = 0;  
UICC_debug[UICC_debug_count][1] = UICC_card_ctrl_state[UICC_current_reader];
UICC_debug[UICC_debug_count][2] = event;

UICC_ctrl_atr  1
typedef enum
{
  UICC_ATR_NONE,
  UICC_ATR_READY,
  UICC_COLD_ENABLING = 2,
  UICC_WARM_ENABLING,
  UICC_ACTIVATING_VCC,

  UICC_ACTIVATING_IO,
  UICC_TS_INTERNAL_RESET,
  UICC_TS_ACTIVE_LOW_RESET =7,
  UICC_T0 =8,
  UICC_TA1 = 9, 

  UICC_TB1, 
  UICC_TC1 = 11, 
  UICC_TD1 = 12,
  UICC_TA2 = 13, 
  UICC_TB2, 

  UICC_TC2, 
  UICC_TDI = 16,
  UICC_TAI = 17, 
  UICC_TBI, 
  UICC_TCI,

  UICC_HISTORY,
  UICC_TCK,
  UICC_ATR_SUCCEDED = 22,
  UICC_ATR_ERROR
} T_UICC_ATR_CTRL_STATE;
UICC_debug[UICC_debug_count][0] = 1;  
UICC_debug[UICC_debug_count][1] = UICC_atr_ctrl_state;
UICC_debug[UICC_debug_count][2] = event;

UICC_main_control 2
typedef enum /* UICC Main control states */
{
  UICC_MAIN_NONE,
  UICC_READY = 1,
  UICC_CARD1_OPERATING,
  UICC_CARD2_OPERATING
} T_UICC_MAIN_CONTROL_STATE;

UICC_debug[UICC_debug_count][0] = 2;  
UICC_debug[UICC_debug_count][1] = UICC_main_ctrl_state;
UICC_debug[UICC_debug_count][2] = event;


UICC_ctrl_pps  3
typedef enum
{
  UICC_PPS_NONE,
  UICC_PPS_READY = 1,
  UICC_NO_PPS_NEEDED,
  UICC_PROTOCOL_PARAMETERS_NOT_SUPPORTED,       
  UICC_WARM_RESET_REQUIRED,       

  UICC_PREPARING_PPS,
  UICC_PPSS_REQ = 6,
  UICC_PPS0_REQ,
  UICC_PPS1_REQ,
  UICC_PCK_REQ,

  UICC_PPSS_RESP = 10,
  UICC_PPS0_RESP,
  UICC_PPS1_RESP,
  UICC_PPS2_RESP,
  UICC_PPS3_RESP,

  UICC_PCK_RESP,
  UICC_PPS_COMPLETED
} T_UICC_PPS_CTRL_STATE;

typedef enum /* UICC PPS controller events */
{
  UICC_INITIATE_PPS = /*UICC_LAST_INT_EVENT*/27,
  UICC_RESET_PPS,              
  UICC_LAST_PPS_EVENT
} T_UICC_PPS_EVENTS;
UICC_debug[UICC_debug_count][0] = 3;  
UICC_debug[UICC_debug_count][1] = UICC_pps_ctrl_state;
UICC_debug[UICC_debug_count][2] = event;



UICC_t0_cmd_handler  40
  typedef enum
  {
    UICC_T0_CMD_NONE =0,
    UICC_T0_CMD_READY_CLK_OFF,
    UICC_T0_CMD_READY,
    UICC_RX_HEADER,
    UICC_CMD_DATA,

    UICC_CMD_SUCCEEDED,
    UICC_CMD_FAILED =6,
    UICC_AWAIT_CLK_POWER_DOWN,
    UICC_TX_CMD_DATA = 8,
    UICC_RX_CMD_DATA,
    UICC_CMD_AWAIT_DMA_END,
    UICC_CMD_SUCCEEDED_WITH_NO_DATA,
    UICC_TX_AWAIT_FIFO_REQUEST =12,
    UICC_TX_PACK_TRANS,
    UICC_RX_AWAIT_FIFO_REQ,
    UICC_RX_PACK_TRANS    
  } T_UICC_T0_CMD_CTRL_STATE;
UICC_debug[UICC_debug_count][0] = 40;  
UICC_debug[UICC_debug_count][1] = UICC_t0_cmd_ctrl_state;
UICC_debug[UICC_debug_count][2] = event;



UICC_t0_transport_handler  5
typedef enum {
  UICC_T0_TRANS_NONE=0,
  UICC_T0_TRANS_READY,
  UICC_CASE_1_CMD =2 ,
  UICC_RX_HANDLING_CASE_2_4_CMD,  
  UICC_TX_HANDLING_CASE_3_CMD,

  UICC_TX_HANDLING_CASE_4_CMD = 5,  
  UICC_RESEND_CMD,
  UICC_GET_RESPONSE_AFTER_61H,
  UICC_GET_RESPONSE_AFTER_62_63H,  
  UICC_GET_RESPONSE_AFTER_9FH = 9,

  UICC_OVERFLOW_HANDLING,
  UICC_TRANS_SUCCEEDED = 11
} T_UICC_T0_TRANS_CTRL_STATE;

UICC_debug[UICC_debug_count][0] = 5;  
UICC_debug[UICC_debug_count][1] = UICC_t0_trans_ctrl_state;
UICC_debug[UICC_debug_count][2] = event;


UICC_reset  6
typedef enum {
  UICC_ACTIVATION_SUCCEEDED,
  UICC_ACTIVATION_FAILED,
  UICC_REJECT_CARD
} T_UICC_RESET_RESULT;

UICC_debug[UICC_debug_count][0] = 6;  
UICC_debug[UICC_debug_count][1] = UICC_activation_result;
UICC_debug[UICC_debug_count++][2] = 0;

UICC_control_card_access  7
typedef enum /* UICC Card control states */
{
  UICC_CARD_NONE = 0,
  UICC_INACTIVE,
  UICC_COLD_ACTIVATION,
  UICC_WARM_ACTIVATION,
  UICC_COLD_PPS_DETERMINATION,

  UICC_WARM_PPS_DETERMINATION,
  UICC_IDLE=6,
  UICC_BUSY = 7,
  UICC_TESTMODE,
  UICC_CARD_IN_OUT_DETECTING
} T_UICC_CARD_CONTROL_STATE;

UICC_debug[UICC_debug_count][0] = 7;  
UICC_debug[UICC_debug_count][1] = UICC_card_ctrl_state[UICC_current_reader];
UICC_debug[UICC_debug_count][2] = event;


UICC_start_timer  8
UICC_stop_timer  9
UICC_timeout_callback 10

UICC_ISR_Process(before ) 11
UICC_ISR_process(after)   17
UICC_debug[UICC_debug_count][0] = 11/17
UICC_debug[UICC_debug_count][1] = (byte)dwSimStatus;
UICC_debug[UICC_debug_count][2] = (byte)dwFifoStatus;
UICC_debug_count = (UICC_debug_count+1) % 100;


UICC_start_guard_timer  12

UICC_force_timeout  15

UICC_init_timer   16
UICC_debug[UICC_debug_count][1] = (byte)UICC_timer;

UICC_close   22  

FIFO_ONLY   40
FIFO_TX+DMA_RX  41
DMA_TX_RX_42






