| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | /*******************************************************************************
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| 2 | * Copyright by ZTE Corporation.
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| 3 | *
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| 4 | * File Name:
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| 5 | * File Mark:
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| 6 | * Description:
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| 7 | * Others:
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| 8 | * Version: v0.1
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| 9 | * Author: wuhui
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| 10 | * Date: 2017-1-13
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| 11 | * History 1:
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| 12 | * Date:
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| 13 | * Version:
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| 14 | * Author:
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| 15 | * Modification:
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| 16 | * History 2:
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| 17 | ********************************************************************************/
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| 18 |
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| 19 | #ifndef _DRVS_SPICC_H
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| 20 | #define _DRVS_SPICC_H
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| 21 |
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| 22 | /****************************************************************************
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| 23 | * Include files
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| 24 | ****************************************************************************/
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| 25 | #include "drvs_chip_cfg.h"
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| 26 | #include "drvs_dma.h"
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| 27 | #include "drvs_sys.h"
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| 28 |
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| 29 | /****************************************************************************
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| 30 | * Macros
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| 31 | ****************************************************************************/
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| 32 | //BASE ADDRESSS
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| 33 | #define SSP1_FORCAM_BASE (SPI1_REG_BASE+0x0000)
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| 34 |
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| 35 | #define SSP1_COMCTRL_MS_OFFSET (2)
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| 36 | #define SSP1_COMCTRL_SSPE_OFFSET (1)
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| 37 | #define SSP1_FMTCTRL_LaneNum_OFFSET (13)
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| 38 | #define SSP1_FMTCTRL_LaneNum_SIZE (2)
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| 39 | #define SSP1_FMTCTRL_CAMMode_OFFSET (12)
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| 40 | #define SSP1_FIFOCTRL_RXFIFOTHRED_OFFSET (4)
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| 41 | #define SSP1_FIFOCTRL_RXFIFOTHRED_SIZE (4)
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| 42 | #define SSP1_FIFOCTRL_RXFIFOCNTR_OFFSET (5)
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| 43 | #define SSP1_FIFOCTRL_RXFIFOCNTR_SIZE (7)
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| 44 | #define SSP1_FIFOCTRL_RXDMAEN_OFFSET (2)
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| 45 | #define SSP1_SYNC_CODE_OFFSET (0)
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| 46 | #define SSP1_CAMFIFO_RST_OFFSET (1)
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| 47 | #define SSP1_SAMPLE_MODE_OFFSET (2)
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| 48 | #define SSP1_ID_SOL_OFFSET (24)
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| 49 | #define SSP1_ID_EOF_OFFSET (16)
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| 50 | #define SSP1_ID_SOF_OFFSET (8)
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| 51 | #define SSP1_ID_SYNC_SIZE (8)
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| 52 | #define SSP1_PACKETSIZE_OFFSET (0)
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| 53 | #define SSP1_PACKETSIZE_SIZE (16)
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| 54 |
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| 55 | //²»Í¬´«Êä¸ñʽʱµÄID ¶¨Òå
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| 56 | #define MTK_START (0x01)
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| 57 | #define MTK_DATA_PACKET (0x40)
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| 58 | #define MTK_END (0x00)
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| 59 | #define BT656_START (0xab)
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| 60 | #define BT656_LINE_START (0x80)
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| 61 | #define BT656_END (0xb6)
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| 62 |
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| 63 |
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| 64 | #define set_reg_bit(regName, bitAddr, bitValue) \
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| 65 | do{ \
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| 66 | if(bitValue == TRUE) \
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| 67 | reg32(regName) |= (0x1<<bitAddr); \
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| 68 | else \
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| 69 | reg32(regName) &= ~(0x1<<bitAddr); \
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| 70 | }while(0)
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| 71 |
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| 72 | #define set_reg_bits(regName, bitsAddr, bitsLen, bitsValue) \
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| 73 | do{ \
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| 74 | reg32(regName) = (reg32(regName)&(~(((0x1<<bitsLen)-0x1)<<bitsAddr)))|(bitsValue<<bitsAddr);\
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| 75 | }while(0)
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| 76 |
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| 77 | #define read_reg_bits(regName, bitsAddr, bitsLen) ((reg32(regName)>>bitsAddr)&((0x1<<bitsLen)-0x1))
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| 78 | #define read_reg_bit(regName, bitsAddr) ((reg32(regName)>>bitsAddr)&0x1)
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| 79 |
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| 80 |
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| 81 | /****************************************************************************
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| 82 | * Types
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| 83 | ****************************************************************************/
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| 84 | typedef volatile struct _T_SPICC_Regs
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| 85 | {
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| 86 | UINT32 SSP1_VER; //0x00
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| 87 | UINT32 SSP1_COM_CTRL; //0x04
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| 88 | UINT32 SSP1_FMT_CTRL; //0x08
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| 89 | UINT32 SSP1_DATA_REG; //0x0C
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| 90 | UINT32 SSP1_FIFO_CTRL; //0x10
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| 91 | UINT32 SSP1_FIFO_STA; //0x14
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| 92 | UINT32 SSP1_INT_EN; //0x18
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| 93 | UINT32 SSP1_INT_STACLR; //0x1C
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| 94 | UINT32 SSP1_TIMING; //0x20
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| 95 | UINT32 Reserved[3]; //0x24~0x2C
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| 96 | UINT32 SSP1_SYNC_CODE; //0x30
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| 97 | UINT32 SSP1_DEBUG; //0x34
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| 98 | UINT32 SSP1_PACKET_SIZE; //0x38
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| 99 | }T_SPICC_Regs;
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| 100 |
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| 101 | typedef enum _T_SSP1_MSMode
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| 102 | {
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| 103 | SSP1_AS_MASTER = 0x0,
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| 104 | SSP1_AS_SLAVE = 0x1,
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| 105 | MAX_MS_MODE = 0X02
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| 106 | }T_SPICC_MSMode;
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| 107 |
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| 108 | typedef enum
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| 109 | {
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| 110 | DISABLE = 0,
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| 111 | ENABLE =1,
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| 112 | MAX_ENABLE_TYPE =2
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| 113 | }T_SPICC_ENABLE_TYPE;
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| 114 |
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| 115 | typedef enum _T_SPICC_LaneNum
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| 116 | {
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| 117 | LANE_1_CAM = 0,
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| 118 | LANE_2_CAM = 1,
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| 119 | LANE_4_CAM = 2,
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| 120 | LANE_MAX_CAM = 3
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| 121 | }T_SPICC_LaneNum;
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| 122 |
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| 123 | typedef enum _T_SPICC_CamMode
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| 124 | {
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| 125 | SSP1_AS_NORMAL = 0,
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| 126 | SSP1_AS_CAMERA = 1,
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| 127 | MAX_SSP1_CAMMODE = 2
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| 128 | }T_SPICC_CamMode;
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| 129 |
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| 130 | typedef enum
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| 131 | {
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| 132 | RAW_DATA =0,
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| 133 | PURE_DATA = 1,
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| 134 | MAX_SAMPLE_MODE =2
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| 135 | }T_SPICC_ImageSampleMode;
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| 136 |
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| 137 | typedef enum
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| 138 | {
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| 139 | BT656_MODE = 0,
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| 140 | MTK_MODE = 1,
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| 141 | MAX_TRANSFER_MODE =2
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| 142 | }T_SPICC_ImageTransferMode;
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| 143 |
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| 144 | typedef enum
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| 145 | {
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| 146 | RX_OVERRUN_IE = 0,
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| 147 | RX_FULL_IE = 2,
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| 148 | RX_THRED_IE = 4,
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| 149 | CAM_SOF_IE = 7,
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| 150 | CAM_EOF_IE = 8,
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| 151 | MAX_SSP1_INT_EN = 9
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| 152 | }T_SPICC_IntEn;
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| 153 |
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| 154 | typedef enum
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| 155 | {
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| 156 | eRESET =0,
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| 157 | eRELEASE = 1,
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| 158 | MAX_FIFOCtrl_TYPE =2
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| 159 | }T_SPICC_CamFIFORst;
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| 160 |
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| 161 | typedef struct _T_zDrvSPICC_Device
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| 162 | {
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| 163 | T_SPICC_ImageTransferMode transMode;
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| 164 | T_SPICC_ImageSampleMode samMode;
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| 165 | T_SPICC_LaneNum laneNum;
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| 166 | UINT32 packetSize;
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| 167 | }T_zDrvSPICC_Device;
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| 168 |
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| 169 | typedef struct _T_SPICC_DevCtrl
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| 170 | {
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| 171 | T_SPICC_Regs* regPtr;
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| 172 | UINT32 rxDmaChl; // ssp rx Dma channel number
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| 173 |
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| 174 | }T_SPICC_DevCtrl;
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| 175 |
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| 176 | /****************************************************************************
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| 177 | * Constants
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| 178 | ****************************************************************************/
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| 179 |
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| 180 | /****************************************************************************
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| 181 | * Global Variables
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| 182 | ****************************************************************************/
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| 183 |
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| 184 | /****************************************************************************
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| 185 | * Function Prototypes
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| 186 | ****************************************************************************/
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| 187 | SINT32 zDrvSPICC_Initiate(VOID);
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| 188 | SINT32 zDrvSPICC_Open(T_zDrvSPICC_Device *spicc_Dev);
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| 189 | SINT32 zDrvSPICC_Close(void);
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| 190 | SINT32 zDrvSPICC_DmaRxloop(zDrvDma_CallbackFunc CallBack,T_ZDrvDma_ChannelDef *rxRegDmaChl,UINT32 transferListNum);
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| 191 | SINT32 zDrvSPICC_DisableDmaRxloop(VOID);
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| 192 | SINT32 zDrvSPICC_DeAllocDmaRxCh(VOID);
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| 193 | VOID zDrvSPICC_ClkGateCtrl(T_ZDrvSysClk_Gate ClkCtrl);
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| 194 |
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| 195 |
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| 196 |
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| 197 | #endif/*_FILENAME_H*/
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| 198 |
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