blob: d009ecf8f67b9caf743a3c13ac25f72838140d99 [file] [log] [blame]
lh9ed821d2023-04-07 01:36:19 -07001/*
2 * SuperTrak EX Series Storage Controller driver for Linux
3 *
4 * Copyright (C) 2005-2009 Promise Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Written By:
12 * Ed Lin <promise_linux@promise.com>
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/delay.h>
20#include <linux/slab.h>
21#include <linux/time.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/interrupt.h>
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/spinlock.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30#include <asm/byteorder.h>
31#include <scsi/scsi.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_cmnd.h>
34#include <scsi/scsi_host.h>
35#include <scsi/scsi_tcq.h>
36#include <scsi/scsi_dbg.h>
37#include <scsi/scsi_eh.h>
38
39#define DRV_NAME "stex"
40#define ST_DRIVER_VERSION "4.6.0000.4"
41#define ST_VER_MAJOR 4
42#define ST_VER_MINOR 6
43#define ST_OEM 0
44#define ST_BUILD_VER 4
45
46enum {
47 /* MU register offset */
48 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
49 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
50 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
51 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
52 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
53 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
54 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
55 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
56 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
57 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
58
59 YIOA_STATUS = 0x00,
60 YH2I_INT = 0x20,
61 YINT_EN = 0x34,
62 YI2H_INT = 0x9c,
63 YI2H_INT_C = 0xa0,
64 YH2I_REQ = 0xc0,
65 YH2I_REQ_HI = 0xc4,
66
67 /* MU register value */
68 MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0),
69 MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1),
70 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2),
71 MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3),
72 MU_INBOUND_DOORBELL_RESET = (1 << 4),
73
74 MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0),
75 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
76 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2),
77 MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3),
78 MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4),
79 MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27),
80
81 /* MU status code */
82 MU_STATE_STARTING = 1,
83 MU_STATE_STARTED = 2,
84 MU_STATE_RESETTING = 3,
85 MU_STATE_FAILED = 4,
86
87 MU_MAX_DELAY = 120,
88 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
89 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
90 MU_HARD_RESET_WAIT = 30000,
91 HMU_PARTNER_TYPE = 2,
92
93 /* firmware returned values */
94 SRB_STATUS_SUCCESS = 0x01,
95 SRB_STATUS_ERROR = 0x04,
96 SRB_STATUS_BUSY = 0x05,
97 SRB_STATUS_INVALID_REQUEST = 0x06,
98 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
99 SRB_SEE_SENSE = 0x80,
100
101 /* task attribute */
102 TASK_ATTRIBUTE_SIMPLE = 0x0,
103 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
104 TASK_ATTRIBUTE_ORDERED = 0x2,
105 TASK_ATTRIBUTE_ACA = 0x4,
106
107 SS_STS_NORMAL = 0x80000000,
108 SS_STS_DONE = 0x40000000,
109 SS_STS_HANDSHAKE = 0x20000000,
110
111 SS_HEAD_HANDSHAKE = 0x80,
112
113 SS_H2I_INT_RESET = 0x100,
114
115 SS_I2H_REQUEST_RESET = 0x2000,
116
117 SS_MU_OPERATIONAL = 0x80000000,
118
119 STEX_CDB_LENGTH = 16,
120 STATUS_VAR_LEN = 128,
121
122 /* sg flags */
123 SG_CF_EOT = 0x80, /* end of table */
124 SG_CF_64B = 0x40, /* 64 bit item */
125 SG_CF_HOST = 0x20, /* sg in host memory */
126 MSG_DATA_DIR_ND = 0,
127 MSG_DATA_DIR_IN = 1,
128 MSG_DATA_DIR_OUT = 2,
129
130 st_shasta = 0,
131 st_vsc = 1,
132 st_yosemite = 2,
133 st_seq = 3,
134 st_yel = 4,
135
136 PASSTHRU_REQ_TYPE = 0x00000001,
137 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
138 ST_INTERNAL_TIMEOUT = 180,
139
140 ST_TO_CMD = 0,
141 ST_FROM_CMD = 1,
142
143 /* vendor specific commands of Promise */
144 MGT_CMD = 0xd8,
145 SINBAND_MGT_CMD = 0xd9,
146 ARRAY_CMD = 0xe0,
147 CONTROLLER_CMD = 0xe1,
148 DEBUGGING_CMD = 0xe2,
149 PASSTHRU_CMD = 0xe3,
150
151 PASSTHRU_GET_ADAPTER = 0x05,
152 PASSTHRU_GET_DRVVER = 0x10,
153
154 CTLR_CONFIG_CMD = 0x03,
155 CTLR_SHUTDOWN = 0x0d,
156
157 CTLR_POWER_STATE_CHANGE = 0x0e,
158 CTLR_POWER_SAVING = 0x01,
159
160 PASSTHRU_SIGNATURE = 0x4e415041,
161 MGT_CMD_SIGNATURE = 0xba,
162
163 INQUIRY_EVPD = 0x01,
164
165 ST_ADDITIONAL_MEM = 0x200000,
166 ST_ADDITIONAL_MEM_MIN = 0x80000,
167};
168
169struct st_sgitem {
170 u8 ctrl; /* SG_CF_xxx */
171 u8 reserved[3];
172 __le32 count;
173 __le64 addr;
174};
175
176struct st_ss_sgitem {
177 __le32 addr;
178 __le32 addr_hi;
179 __le32 count;
180};
181
182struct st_sgtable {
183 __le16 sg_count;
184 __le16 max_sg_count;
185 __le32 sz_in_byte;
186};
187
188struct st_msg_header {
189 __le64 handle;
190 u8 flag;
191 u8 channel;
192 __le16 timeout;
193 u32 reserved;
194};
195
196struct handshake_frame {
197 __le64 rb_phy; /* request payload queue physical address */
198 __le16 req_sz; /* size of each request payload */
199 __le16 req_cnt; /* count of reqs the buffer can hold */
200 __le16 status_sz; /* size of each status payload */
201 __le16 status_cnt; /* count of status the buffer can hold */
202 __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */
203 u8 partner_type; /* who sends this frame */
204 u8 reserved0[7];
205 __le32 partner_ver_major;
206 __le32 partner_ver_minor;
207 __le32 partner_ver_oem;
208 __le32 partner_ver_build;
209 __le32 extra_offset; /* NEW */
210 __le32 extra_size; /* NEW */
211 __le32 scratch_size;
212 u32 reserved1;
213};
214
215struct req_msg {
216 __le16 tag;
217 u8 lun;
218 u8 target;
219 u8 task_attr;
220 u8 task_manage;
221 u8 data_dir;
222 u8 payload_sz; /* payload size in 4-byte, not used */
223 u8 cdb[STEX_CDB_LENGTH];
224 u32 variable[0];
225};
226
227struct status_msg {
228 __le16 tag;
229 u8 lun;
230 u8 target;
231 u8 srb_status;
232 u8 scsi_status;
233 u8 reserved;
234 u8 payload_sz; /* payload size in 4-byte */
235 u8 variable[STATUS_VAR_LEN];
236};
237
238struct ver_info {
239 u32 major;
240 u32 minor;
241 u32 oem;
242 u32 build;
243 u32 reserved[2];
244};
245
246struct st_frame {
247 u32 base[6];
248 u32 rom_addr;
249
250 struct ver_info drv_ver;
251 struct ver_info bios_ver;
252
253 u32 bus;
254 u32 slot;
255 u32 irq_level;
256 u32 irq_vec;
257 u32 id;
258 u32 subid;
259
260 u32 dimm_size;
261 u8 dimm_type;
262 u8 reserved[3];
263
264 u32 channel;
265 u32 reserved1;
266};
267
268struct st_drvver {
269 u32 major;
270 u32 minor;
271 u32 oem;
272 u32 build;
273 u32 signature[2];
274 u8 console_id;
275 u8 host_no;
276 u8 reserved0[2];
277 u32 reserved[3];
278};
279
280struct st_ccb {
281 struct req_msg *req;
282 struct scsi_cmnd *cmd;
283
284 void *sense_buffer;
285 unsigned int sense_bufflen;
286 int sg_count;
287
288 u32 req_type;
289 u8 srb_status;
290 u8 scsi_status;
291 u8 reserved[2];
292};
293
294struct st_hba {
295 void __iomem *mmio_base; /* iomapped PCI memory space */
296 void *dma_mem;
297 dma_addr_t dma_handle;
298 size_t dma_size;
299
300 struct Scsi_Host *host;
301 struct pci_dev *pdev;
302
303 struct req_msg * (*alloc_rq) (struct st_hba *);
304 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
305 void (*send) (struct st_hba *, struct req_msg *, u16);
306
307 u32 req_head;
308 u32 req_tail;
309 u32 status_head;
310 u32 status_tail;
311
312 struct status_msg *status_buffer;
313 void *copy_buffer; /* temp buffer for driver-handled commands */
314 struct st_ccb *ccb;
315 struct st_ccb *wait_ccb;
316 __le32 *scratch;
317
318 char work_q_name[20];
319 struct workqueue_struct *work_q;
320 struct work_struct reset_work;
321 wait_queue_head_t reset_waitq;
322 unsigned int mu_status;
323 unsigned int cardtype;
324 int msi_enabled;
325 int out_req_cnt;
326 u32 extra_offset;
327 u16 rq_count;
328 u16 rq_size;
329 u16 sts_count;
330};
331
332struct st_card_info {
333 struct req_msg * (*alloc_rq) (struct st_hba *);
334 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
335 void (*send) (struct st_hba *, struct req_msg *, u16);
336 unsigned int max_id;
337 unsigned int max_lun;
338 unsigned int max_channel;
339 u16 rq_count;
340 u16 rq_size;
341 u16 sts_count;
342};
343
344static int msi;
345module_param(msi, int, 0);
346MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
347
348static const char console_inq_page[] =
349{
350 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
351 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
352 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
353 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
354 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
355 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
356 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
357 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
358};
359
360MODULE_AUTHOR("Ed Lin");
361MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
362MODULE_LICENSE("GPL");
363MODULE_VERSION(ST_DRIVER_VERSION);
364
365static void stex_gettime(__le64 *time)
366{
367 struct timeval tv;
368
369 do_gettimeofday(&tv);
370 *time = cpu_to_le64(tv.tv_sec);
371}
372
373static struct status_msg *stex_get_status(struct st_hba *hba)
374{
375 struct status_msg *status = hba->status_buffer + hba->status_tail;
376
377 ++hba->status_tail;
378 hba->status_tail %= hba->sts_count+1;
379
380 return status;
381}
382
383static void stex_invalid_field(struct scsi_cmnd *cmd,
384 void (*done)(struct scsi_cmnd *))
385{
386 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
387
388 /* "Invalid field in cdb" */
389 scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
390 0x0);
391 done(cmd);
392}
393
394static struct req_msg *stex_alloc_req(struct st_hba *hba)
395{
396 struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
397
398 ++hba->req_head;
399 hba->req_head %= hba->rq_count+1;
400
401 return req;
402}
403
404static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
405{
406 return (struct req_msg *)(hba->dma_mem +
407 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
408}
409
410static int stex_map_sg(struct st_hba *hba,
411 struct req_msg *req, struct st_ccb *ccb)
412{
413 struct scsi_cmnd *cmd;
414 struct scatterlist *sg;
415 struct st_sgtable *dst;
416 struct st_sgitem *table;
417 int i, nseg;
418
419 cmd = ccb->cmd;
420 nseg = scsi_dma_map(cmd);
421 BUG_ON(nseg < 0);
422 if (nseg) {
423 dst = (struct st_sgtable *)req->variable;
424
425 ccb->sg_count = nseg;
426 dst->sg_count = cpu_to_le16((u16)nseg);
427 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
428 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
429
430 table = (struct st_sgitem *)(dst + 1);
431 scsi_for_each_sg(cmd, sg, nseg, i) {
432 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
433 table[i].addr = cpu_to_le64(sg_dma_address(sg));
434 table[i].ctrl = SG_CF_64B | SG_CF_HOST;
435 }
436 table[--i].ctrl |= SG_CF_EOT;
437 }
438
439 return nseg;
440}
441
442static int stex_ss_map_sg(struct st_hba *hba,
443 struct req_msg *req, struct st_ccb *ccb)
444{
445 struct scsi_cmnd *cmd;
446 struct scatterlist *sg;
447 struct st_sgtable *dst;
448 struct st_ss_sgitem *table;
449 int i, nseg;
450
451 cmd = ccb->cmd;
452 nseg = scsi_dma_map(cmd);
453 BUG_ON(nseg < 0);
454 if (nseg) {
455 dst = (struct st_sgtable *)req->variable;
456
457 ccb->sg_count = nseg;
458 dst->sg_count = cpu_to_le16((u16)nseg);
459 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
460 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
461
462 table = (struct st_ss_sgitem *)(dst + 1);
463 scsi_for_each_sg(cmd, sg, nseg, i) {
464 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
465 table[i].addr =
466 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
467 table[i].addr_hi =
468 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
469 }
470 }
471
472 return nseg;
473}
474
475static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
476{
477 struct st_frame *p;
478 size_t count = sizeof(struct st_frame);
479
480 p = hba->copy_buffer;
481 scsi_sg_copy_to_buffer(ccb->cmd, p, count);
482 memset(p->base, 0, sizeof(u32)*6);
483 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
484 p->rom_addr = 0;
485
486 p->drv_ver.major = ST_VER_MAJOR;
487 p->drv_ver.minor = ST_VER_MINOR;
488 p->drv_ver.oem = ST_OEM;
489 p->drv_ver.build = ST_BUILD_VER;
490
491 p->bus = hba->pdev->bus->number;
492 p->slot = hba->pdev->devfn;
493 p->irq_level = 0;
494 p->irq_vec = hba->pdev->irq;
495 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
496 p->subid =
497 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
498
499 scsi_sg_copy_from_buffer(ccb->cmd, p, count);
500}
501
502static void
503stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
504{
505 req->tag = cpu_to_le16(tag);
506
507 hba->ccb[tag].req = req;
508 hba->out_req_cnt++;
509
510 writel(hba->req_head, hba->mmio_base + IMR0);
511 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
512 readl(hba->mmio_base + IDBL); /* flush */
513}
514
515static void
516stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
517{
518 struct scsi_cmnd *cmd;
519 struct st_msg_header *msg_h;
520 dma_addr_t addr;
521
522 req->tag = cpu_to_le16(tag);
523
524 hba->ccb[tag].req = req;
525 hba->out_req_cnt++;
526
527 cmd = hba->ccb[tag].cmd;
528 msg_h = (struct st_msg_header *)req - 1;
529 if (likely(cmd)) {
530 msg_h->channel = (u8)cmd->device->channel;
531 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
532 }
533 addr = hba->dma_handle + hba->req_head * hba->rq_size;
534 addr += (hba->ccb[tag].sg_count+4)/11;
535 msg_h->handle = cpu_to_le64(addr);
536
537 ++hba->req_head;
538 hba->req_head %= hba->rq_count+1;
539
540 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
541 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
542 writel(addr, hba->mmio_base + YH2I_REQ);
543 readl(hba->mmio_base + YH2I_REQ); /* flush */
544}
545
546static int
547stex_slave_alloc(struct scsi_device *sdev)
548{
549 /* Cheat: usually extracted from Inquiry data */
550 sdev->tagged_supported = 1;
551
552 scsi_activate_tcq(sdev, sdev->host->can_queue);
553
554 return 0;
555}
556
557static int
558stex_slave_config(struct scsi_device *sdev)
559{
560 sdev->use_10_for_rw = 1;
561 sdev->use_10_for_ms = 1;
562 blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
563 sdev->tagged_supported = 1;
564
565 return 0;
566}
567
568static void
569stex_slave_destroy(struct scsi_device *sdev)
570{
571 scsi_deactivate_tcq(sdev, 1);
572}
573
574static int
575stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
576{
577 struct st_hba *hba;
578 struct Scsi_Host *host;
579 unsigned int id, lun;
580 struct req_msg *req;
581 u16 tag;
582
583 host = cmd->device->host;
584 id = cmd->device->id;
585 lun = cmd->device->lun;
586 hba = (struct st_hba *) &host->hostdata[0];
587
588 if (unlikely(hba->mu_status == MU_STATE_RESETTING))
589 return SCSI_MLQUEUE_HOST_BUSY;
590
591 switch (cmd->cmnd[0]) {
592 case MODE_SENSE_10:
593 {
594 static char ms10_caching_page[12] =
595 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
596 unsigned char page;
597
598 page = cmd->cmnd[2] & 0x3f;
599 if (page == 0x8 || page == 0x3f) {
600 scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
601 sizeof(ms10_caching_page));
602 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
603 done(cmd);
604 } else
605 stex_invalid_field(cmd, done);
606 return 0;
607 }
608 case REPORT_LUNS:
609 /*
610 * The shasta firmware does not report actual luns in the
611 * target, so fail the command to force sequential lun scan.
612 * Also, the console device does not support this command.
613 */
614 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
615 stex_invalid_field(cmd, done);
616 return 0;
617 }
618 break;
619 case TEST_UNIT_READY:
620 if (id == host->max_id - 1) {
621 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
622 done(cmd);
623 return 0;
624 }
625 break;
626 case INQUIRY:
627 if (lun >= host->max_lun) {
628 cmd->result = DID_NO_CONNECT << 16;
629 done(cmd);
630 return 0;
631 }
632 if (id != host->max_id - 1)
633 break;
634 if (!lun && !cmd->device->channel &&
635 (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
636 scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
637 sizeof(console_inq_page));
638 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
639 done(cmd);
640 } else
641 stex_invalid_field(cmd, done);
642 return 0;
643 case PASSTHRU_CMD:
644 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
645 struct st_drvver ver;
646 size_t cp_len = sizeof(ver);
647 memset(&ver, 0x00, sizeof(ver));
648
649 ver.major = ST_VER_MAJOR;
650 ver.minor = ST_VER_MINOR;
651 ver.oem = ST_OEM;
652 ver.build = ST_BUILD_VER;
653 ver.signature[0] = PASSTHRU_SIGNATURE;
654 ver.console_id = host->max_id - 1;
655 ver.host_no = hba->host->host_no;
656 cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
657 cmd->result = sizeof(ver) == cp_len ?
658 DID_OK << 16 | COMMAND_COMPLETE << 8 :
659 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
660 done(cmd);
661 return 0;
662 }
663 default:
664 break;
665 }
666
667 cmd->scsi_done = done;
668
669 tag = cmd->request->tag;
670
671 if (unlikely(tag >= host->can_queue))
672 return SCSI_MLQUEUE_HOST_BUSY;
673
674 req = hba->alloc_rq(hba);
675
676 req->lun = lun;
677 req->target = id;
678
679 /* cdb */
680 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
681
682 if (cmd->sc_data_direction == DMA_FROM_DEVICE)
683 req->data_dir = MSG_DATA_DIR_IN;
684 else if (cmd->sc_data_direction == DMA_TO_DEVICE)
685 req->data_dir = MSG_DATA_DIR_OUT;
686 else
687 req->data_dir = MSG_DATA_DIR_ND;
688
689 hba->ccb[tag].cmd = cmd;
690 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
691 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
692
693 if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
694 hba->ccb[tag].sg_count = 0;
695 memset(&req->variable[0], 0, 8);
696 }
697
698 hba->send(hba, req, tag);
699 return 0;
700}
701
702static DEF_SCSI_QCMD(stex_queuecommand)
703
704static void stex_scsi_done(struct st_ccb *ccb)
705{
706 struct scsi_cmnd *cmd = ccb->cmd;
707 int result;
708
709 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
710 result = ccb->scsi_status;
711 switch (ccb->scsi_status) {
712 case SAM_STAT_GOOD:
713 result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
714 break;
715 case SAM_STAT_CHECK_CONDITION:
716 result |= DRIVER_SENSE << 24;
717 break;
718 case SAM_STAT_BUSY:
719 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
720 break;
721 default:
722 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
723 break;
724 }
725 }
726 else if (ccb->srb_status & SRB_SEE_SENSE)
727 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
728 else switch (ccb->srb_status) {
729 case SRB_STATUS_SELECTION_TIMEOUT:
730 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
731 break;
732 case SRB_STATUS_BUSY:
733 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
734 break;
735 case SRB_STATUS_INVALID_REQUEST:
736 case SRB_STATUS_ERROR:
737 default:
738 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
739 break;
740 }
741
742 cmd->result = result;
743 cmd->scsi_done(cmd);
744}
745
746static void stex_copy_data(struct st_ccb *ccb,
747 struct status_msg *resp, unsigned int variable)
748{
749 if (resp->scsi_status != SAM_STAT_GOOD) {
750 if (ccb->sense_buffer != NULL)
751 memcpy(ccb->sense_buffer, resp->variable,
752 min(variable, ccb->sense_bufflen));
753 return;
754 }
755
756 if (ccb->cmd == NULL)
757 return;
758 scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
759}
760
761static void stex_check_cmd(struct st_hba *hba,
762 struct st_ccb *ccb, struct status_msg *resp)
763{
764 if (ccb->cmd->cmnd[0] == MGT_CMD &&
765 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
766 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
767 le32_to_cpu(*(__le32 *)&resp->variable[0]));
768}
769
770static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
771{
772 void __iomem *base = hba->mmio_base;
773 struct status_msg *resp;
774 struct st_ccb *ccb;
775 unsigned int size;
776 u16 tag;
777
778 if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
779 return;
780
781 /* status payloads */
782 hba->status_head = readl(base + OMR1);
783 if (unlikely(hba->status_head > hba->sts_count)) {
784 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
785 pci_name(hba->pdev));
786 return;
787 }
788
789 /*
790 * it's not a valid status payload if:
791 * 1. there are no pending requests(e.g. during init stage)
792 * 2. there are some pending requests, but the controller is in
793 * reset status, and its type is not st_yosemite
794 * firmware of st_yosemite in reset status will return pending requests
795 * to driver, so we allow it to pass
796 */
797 if (unlikely(hba->out_req_cnt <= 0 ||
798 (hba->mu_status == MU_STATE_RESETTING &&
799 hba->cardtype != st_yosemite))) {
800 hba->status_tail = hba->status_head;
801 goto update_status;
802 }
803
804 while (hba->status_tail != hba->status_head) {
805 resp = stex_get_status(hba);
806 tag = le16_to_cpu(resp->tag);
807 if (unlikely(tag >= hba->host->can_queue)) {
808 printk(KERN_WARNING DRV_NAME
809 "(%s): invalid tag\n", pci_name(hba->pdev));
810 continue;
811 }
812
813 hba->out_req_cnt--;
814 ccb = &hba->ccb[tag];
815 if (unlikely(hba->wait_ccb == ccb))
816 hba->wait_ccb = NULL;
817 if (unlikely(ccb->req == NULL)) {
818 printk(KERN_WARNING DRV_NAME
819 "(%s): lagging req\n", pci_name(hba->pdev));
820 continue;
821 }
822
823 size = resp->payload_sz * sizeof(u32); /* payload size */
824 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
825 size > sizeof(*resp))) {
826 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
827 pci_name(hba->pdev));
828 } else {
829 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
830 if (size)
831 stex_copy_data(ccb, resp, size);
832 }
833
834 ccb->req = NULL;
835 ccb->srb_status = resp->srb_status;
836 ccb->scsi_status = resp->scsi_status;
837
838 if (likely(ccb->cmd != NULL)) {
839 if (hba->cardtype == st_yosemite)
840 stex_check_cmd(hba, ccb, resp);
841
842 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
843 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
844 stex_controller_info(hba, ccb);
845
846 scsi_dma_unmap(ccb->cmd);
847 stex_scsi_done(ccb);
848 } else
849 ccb->req_type = 0;
850 }
851
852update_status:
853 writel(hba->status_head, base + IMR1);
854 readl(base + IMR1); /* flush */
855}
856
857static irqreturn_t stex_intr(int irq, void *__hba)
858{
859 struct st_hba *hba = __hba;
860 void __iomem *base = hba->mmio_base;
861 u32 data;
862 unsigned long flags;
863
864 spin_lock_irqsave(hba->host->host_lock, flags);
865
866 data = readl(base + ODBL);
867
868 if (data && data != 0xffffffff) {
869 /* clear the interrupt */
870 writel(data, base + ODBL);
871 readl(base + ODBL); /* flush */
872 stex_mu_intr(hba, data);
873 spin_unlock_irqrestore(hba->host->host_lock, flags);
874 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
875 hba->cardtype == st_shasta))
876 queue_work(hba->work_q, &hba->reset_work);
877 return IRQ_HANDLED;
878 }
879
880 spin_unlock_irqrestore(hba->host->host_lock, flags);
881
882 return IRQ_NONE;
883}
884
885static void stex_ss_mu_intr(struct st_hba *hba)
886{
887 struct status_msg *resp;
888 struct st_ccb *ccb;
889 __le32 *scratch;
890 unsigned int size;
891 int count = 0;
892 u32 value;
893 u16 tag;
894
895 if (unlikely(hba->out_req_cnt <= 0 ||
896 hba->mu_status == MU_STATE_RESETTING))
897 return;
898
899 while (count < hba->sts_count) {
900 scratch = hba->scratch + hba->status_tail;
901 value = le32_to_cpu(*scratch);
902 if (unlikely(!(value & SS_STS_NORMAL)))
903 return;
904
905 resp = hba->status_buffer + hba->status_tail;
906 *scratch = 0;
907 ++count;
908 ++hba->status_tail;
909 hba->status_tail %= hba->sts_count+1;
910
911 tag = (u16)value;
912 if (unlikely(tag >= hba->host->can_queue)) {
913 printk(KERN_WARNING DRV_NAME
914 "(%s): invalid tag\n", pci_name(hba->pdev));
915 continue;
916 }
917
918 hba->out_req_cnt--;
919 ccb = &hba->ccb[tag];
920 if (unlikely(hba->wait_ccb == ccb))
921 hba->wait_ccb = NULL;
922 if (unlikely(ccb->req == NULL)) {
923 printk(KERN_WARNING DRV_NAME
924 "(%s): lagging req\n", pci_name(hba->pdev));
925 continue;
926 }
927
928 ccb->req = NULL;
929 if (likely(value & SS_STS_DONE)) { /* normal case */
930 ccb->srb_status = SRB_STATUS_SUCCESS;
931 ccb->scsi_status = SAM_STAT_GOOD;
932 } else {
933 ccb->srb_status = resp->srb_status;
934 ccb->scsi_status = resp->scsi_status;
935 size = resp->payload_sz * sizeof(u32);
936 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
937 size > sizeof(*resp))) {
938 printk(KERN_WARNING DRV_NAME
939 "(%s): bad status size\n",
940 pci_name(hba->pdev));
941 } else {
942 size -= sizeof(*resp) - STATUS_VAR_LEN;
943 if (size)
944 stex_copy_data(ccb, resp, size);
945 }
946 if (likely(ccb->cmd != NULL))
947 stex_check_cmd(hba, ccb, resp);
948 }
949
950 if (likely(ccb->cmd != NULL)) {
951 scsi_dma_unmap(ccb->cmd);
952 stex_scsi_done(ccb);
953 } else
954 ccb->req_type = 0;
955 }
956}
957
958static irqreturn_t stex_ss_intr(int irq, void *__hba)
959{
960 struct st_hba *hba = __hba;
961 void __iomem *base = hba->mmio_base;
962 u32 data;
963 unsigned long flags;
964
965 spin_lock_irqsave(hba->host->host_lock, flags);
966
967 data = readl(base + YI2H_INT);
968 if (data && data != 0xffffffff) {
969 /* clear the interrupt */
970 writel(data, base + YI2H_INT_C);
971 stex_ss_mu_intr(hba);
972 spin_unlock_irqrestore(hba->host->host_lock, flags);
973 if (unlikely(data & SS_I2H_REQUEST_RESET))
974 queue_work(hba->work_q, &hba->reset_work);
975 return IRQ_HANDLED;
976 }
977
978 spin_unlock_irqrestore(hba->host->host_lock, flags);
979
980 return IRQ_NONE;
981}
982
983static int stex_common_handshake(struct st_hba *hba)
984{
985 void __iomem *base = hba->mmio_base;
986 struct handshake_frame *h;
987 dma_addr_t status_phys;
988 u32 data;
989 unsigned long before;
990
991 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
992 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
993 readl(base + IDBL);
994 before = jiffies;
995 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
996 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
997 printk(KERN_ERR DRV_NAME
998 "(%s): no handshake signature\n",
999 pci_name(hba->pdev));
1000 return -1;
1001 }
1002 rmb();
1003 msleep(1);
1004 }
1005 }
1006
1007 udelay(10);
1008
1009 data = readl(base + OMR1);
1010 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1011 data &= 0x0000ffff;
1012 if (hba->host->can_queue > data) {
1013 hba->host->can_queue = data;
1014 hba->host->cmd_per_lun = data;
1015 }
1016 }
1017
1018 h = (struct handshake_frame *)hba->status_buffer;
1019 h->rb_phy = cpu_to_le64(hba->dma_handle);
1020 h->req_sz = cpu_to_le16(hba->rq_size);
1021 h->req_cnt = cpu_to_le16(hba->rq_count+1);
1022 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1023 h->status_cnt = cpu_to_le16(hba->sts_count+1);
1024 stex_gettime(&h->hosttime);
1025 h->partner_type = HMU_PARTNER_TYPE;
1026 if (hba->extra_offset) {
1027 h->extra_offset = cpu_to_le32(hba->extra_offset);
1028 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1029 } else
1030 h->extra_offset = h->extra_size = 0;
1031
1032 status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1033 writel(status_phys, base + IMR0);
1034 readl(base + IMR0);
1035 writel((status_phys >> 16) >> 16, base + IMR1);
1036 readl(base + IMR1);
1037
1038 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1039 readl(base + OMR0);
1040 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1041 readl(base + IDBL); /* flush */
1042
1043 udelay(10);
1044 before = jiffies;
1045 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1046 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1047 printk(KERN_ERR DRV_NAME
1048 "(%s): no signature after handshake frame\n",
1049 pci_name(hba->pdev));
1050 return -1;
1051 }
1052 rmb();
1053 msleep(1);
1054 }
1055
1056 writel(0, base + IMR0);
1057 readl(base + IMR0);
1058 writel(0, base + OMR0);
1059 readl(base + OMR0);
1060 writel(0, base + IMR1);
1061 readl(base + IMR1);
1062 writel(0, base + OMR1);
1063 readl(base + OMR1); /* flush */
1064 return 0;
1065}
1066
1067static int stex_ss_handshake(struct st_hba *hba)
1068{
1069 void __iomem *base = hba->mmio_base;
1070 struct st_msg_header *msg_h;
1071 struct handshake_frame *h;
1072 __le32 *scratch;
1073 u32 data, scratch_size;
1074 unsigned long before;
1075 int ret = 0;
1076
1077 before = jiffies;
1078 while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1079 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1080 printk(KERN_ERR DRV_NAME
1081 "(%s): firmware not operational\n",
1082 pci_name(hba->pdev));
1083 return -1;
1084 }
1085 msleep(1);
1086 }
1087
1088 msg_h = (struct st_msg_header *)hba->dma_mem;
1089 msg_h->handle = cpu_to_le64(hba->dma_handle);
1090 msg_h->flag = SS_HEAD_HANDSHAKE;
1091
1092 h = (struct handshake_frame *)(msg_h + 1);
1093 h->rb_phy = cpu_to_le64(hba->dma_handle);
1094 h->req_sz = cpu_to_le16(hba->rq_size);
1095 h->req_cnt = cpu_to_le16(hba->rq_count+1);
1096 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1097 h->status_cnt = cpu_to_le16(hba->sts_count+1);
1098 stex_gettime(&h->hosttime);
1099 h->partner_type = HMU_PARTNER_TYPE;
1100 h->extra_offset = h->extra_size = 0;
1101 scratch_size = (hba->sts_count+1)*sizeof(u32);
1102 h->scratch_size = cpu_to_le32(scratch_size);
1103
1104 data = readl(base + YINT_EN);
1105 data &= ~4;
1106 writel(data, base + YINT_EN);
1107 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1108 readl(base + YH2I_REQ_HI);
1109 writel(hba->dma_handle, base + YH2I_REQ);
1110 readl(base + YH2I_REQ); /* flush */
1111
1112 scratch = hba->scratch;
1113 before = jiffies;
1114 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1115 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1116 printk(KERN_ERR DRV_NAME
1117 "(%s): no signature after handshake frame\n",
1118 pci_name(hba->pdev));
1119 ret = -1;
1120 break;
1121 }
1122 rmb();
1123 msleep(1);
1124 }
1125
1126 memset(scratch, 0, scratch_size);
1127 msg_h->flag = 0;
1128 return ret;
1129}
1130
1131static int stex_handshake(struct st_hba *hba)
1132{
1133 int err;
1134 unsigned long flags;
1135 unsigned int mu_status;
1136
1137 err = (hba->cardtype == st_yel) ?
1138 stex_ss_handshake(hba) : stex_common_handshake(hba);
1139 spin_lock_irqsave(hba->host->host_lock, flags);
1140 mu_status = hba->mu_status;
1141 if (err == 0) {
1142 hba->req_head = 0;
1143 hba->req_tail = 0;
1144 hba->status_head = 0;
1145 hba->status_tail = 0;
1146 hba->out_req_cnt = 0;
1147 hba->mu_status = MU_STATE_STARTED;
1148 } else
1149 hba->mu_status = MU_STATE_FAILED;
1150 if (mu_status == MU_STATE_RESETTING)
1151 wake_up_all(&hba->reset_waitq);
1152 spin_unlock_irqrestore(hba->host->host_lock, flags);
1153 return err;
1154}
1155
1156static int stex_abort(struct scsi_cmnd *cmd)
1157{
1158 struct Scsi_Host *host = cmd->device->host;
1159 struct st_hba *hba = (struct st_hba *)host->hostdata;
1160 u16 tag = cmd->request->tag;
1161 void __iomem *base;
1162 u32 data;
1163 int result = SUCCESS;
1164 unsigned long flags;
1165
1166 printk(KERN_INFO DRV_NAME
1167 "(%s): aborting command\n", pci_name(hba->pdev));
1168 scsi_print_command(cmd);
1169
1170 base = hba->mmio_base;
1171 spin_lock_irqsave(host->host_lock, flags);
1172 if (tag < host->can_queue &&
1173 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1174 hba->wait_ccb = &hba->ccb[tag];
1175 else
1176 goto out;
1177
1178 if (hba->cardtype == st_yel) {
1179 data = readl(base + YI2H_INT);
1180 if (data == 0 || data == 0xffffffff)
1181 goto fail_out;
1182
1183 writel(data, base + YI2H_INT_C);
1184 stex_ss_mu_intr(hba);
1185 } else {
1186 data = readl(base + ODBL);
1187 if (data == 0 || data == 0xffffffff)
1188 goto fail_out;
1189
1190 writel(data, base + ODBL);
1191 readl(base + ODBL); /* flush */
1192
1193 stex_mu_intr(hba, data);
1194 }
1195 if (hba->wait_ccb == NULL) {
1196 printk(KERN_WARNING DRV_NAME
1197 "(%s): lost interrupt\n", pci_name(hba->pdev));
1198 goto out;
1199 }
1200
1201fail_out:
1202 scsi_dma_unmap(cmd);
1203 hba->wait_ccb->req = NULL; /* nullify the req's future return */
1204 hba->wait_ccb = NULL;
1205 result = FAILED;
1206out:
1207 spin_unlock_irqrestore(host->host_lock, flags);
1208 return result;
1209}
1210
1211static void stex_hard_reset(struct st_hba *hba)
1212{
1213 struct pci_bus *bus;
1214 int i;
1215 u16 pci_cmd;
1216 u8 pci_bctl;
1217
1218 for (i = 0; i < 16; i++)
1219 pci_read_config_dword(hba->pdev, i * 4,
1220 &hba->pdev->saved_config_space[i]);
1221
1222 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1223 secondary bus. Consult Intel 80331/3 developer's manual for detail */
1224 bus = hba->pdev->bus;
1225 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1226 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1227 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1228
1229 /*
1230 * 1 ms may be enough for 8-port controllers. But 16-port controllers
1231 * require more time to finish bus reset. Use 100 ms here for safety
1232 */
1233 msleep(100);
1234 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1235 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1236
1237 for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1238 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1239 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1240 break;
1241 msleep(1);
1242 }
1243
1244 ssleep(5);
1245 for (i = 0; i < 16; i++)
1246 pci_write_config_dword(hba->pdev, i * 4,
1247 hba->pdev->saved_config_space[i]);
1248}
1249
1250static int stex_yos_reset(struct st_hba *hba)
1251{
1252 void __iomem *base;
1253 unsigned long flags, before;
1254 int ret = 0;
1255
1256 base = hba->mmio_base;
1257 writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1258 readl(base + IDBL); /* flush */
1259 before = jiffies;
1260 while (hba->out_req_cnt > 0) {
1261 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1262 printk(KERN_WARNING DRV_NAME
1263 "(%s): reset timeout\n", pci_name(hba->pdev));
1264 ret = -1;
1265 break;
1266 }
1267 msleep(1);
1268 }
1269
1270 spin_lock_irqsave(hba->host->host_lock, flags);
1271 if (ret == -1)
1272 hba->mu_status = MU_STATE_FAILED;
1273 else
1274 hba->mu_status = MU_STATE_STARTED;
1275 wake_up_all(&hba->reset_waitq);
1276 spin_unlock_irqrestore(hba->host->host_lock, flags);
1277
1278 return ret;
1279}
1280
1281static void stex_ss_reset(struct st_hba *hba)
1282{
1283 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1284 readl(hba->mmio_base + YH2I_INT);
1285 ssleep(5);
1286}
1287
1288static int stex_do_reset(struct st_hba *hba)
1289{
1290 struct st_ccb *ccb;
1291 unsigned long flags;
1292 unsigned int mu_status = MU_STATE_RESETTING;
1293 u16 tag;
1294
1295 spin_lock_irqsave(hba->host->host_lock, flags);
1296 if (hba->mu_status == MU_STATE_STARTING) {
1297 spin_unlock_irqrestore(hba->host->host_lock, flags);
1298 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1299 pci_name(hba->pdev));
1300 return 0;
1301 }
1302 while (hba->mu_status == MU_STATE_RESETTING) {
1303 spin_unlock_irqrestore(hba->host->host_lock, flags);
1304 wait_event_timeout(hba->reset_waitq,
1305 hba->mu_status != MU_STATE_RESETTING,
1306 MU_MAX_DELAY * HZ);
1307 spin_lock_irqsave(hba->host->host_lock, flags);
1308 mu_status = hba->mu_status;
1309 }
1310
1311 if (mu_status != MU_STATE_RESETTING) {
1312 spin_unlock_irqrestore(hba->host->host_lock, flags);
1313 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1314 }
1315
1316 hba->mu_status = MU_STATE_RESETTING;
1317 spin_unlock_irqrestore(hba->host->host_lock, flags);
1318
1319 if (hba->cardtype == st_yosemite)
1320 return stex_yos_reset(hba);
1321
1322 if (hba->cardtype == st_shasta)
1323 stex_hard_reset(hba);
1324 else if (hba->cardtype == st_yel)
1325 stex_ss_reset(hba);
1326
1327 spin_lock_irqsave(hba->host->host_lock, flags);
1328 for (tag = 0; tag < hba->host->can_queue; tag++) {
1329 ccb = &hba->ccb[tag];
1330 if (ccb->req == NULL)
1331 continue;
1332 ccb->req = NULL;
1333 if (ccb->cmd) {
1334 scsi_dma_unmap(ccb->cmd);
1335 ccb->cmd->result = DID_RESET << 16;
1336 ccb->cmd->scsi_done(ccb->cmd);
1337 ccb->cmd = NULL;
1338 }
1339 }
1340 spin_unlock_irqrestore(hba->host->host_lock, flags);
1341
1342 if (stex_handshake(hba) == 0)
1343 return 0;
1344
1345 printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1346 pci_name(hba->pdev));
1347 return -1;
1348}
1349
1350static int stex_reset(struct scsi_cmnd *cmd)
1351{
1352 struct st_hba *hba;
1353
1354 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1355
1356 printk(KERN_INFO DRV_NAME
1357 "(%s): resetting host\n", pci_name(hba->pdev));
1358 scsi_print_command(cmd);
1359
1360 return stex_do_reset(hba) ? FAILED : SUCCESS;
1361}
1362
1363static void stex_reset_work(struct work_struct *work)
1364{
1365 struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1366
1367 stex_do_reset(hba);
1368}
1369
1370static int stex_biosparam(struct scsi_device *sdev,
1371 struct block_device *bdev, sector_t capacity, int geom[])
1372{
1373 int heads = 255, sectors = 63;
1374
1375 if (capacity < 0x200000) {
1376 heads = 64;
1377 sectors = 32;
1378 }
1379
1380 sector_div(capacity, heads * sectors);
1381
1382 geom[0] = heads;
1383 geom[1] = sectors;
1384 geom[2] = capacity;
1385
1386 return 0;
1387}
1388
1389static struct scsi_host_template driver_template = {
1390 .module = THIS_MODULE,
1391 .name = DRV_NAME,
1392 .proc_name = DRV_NAME,
1393 .bios_param = stex_biosparam,
1394 .queuecommand = stex_queuecommand,
1395 .slave_alloc = stex_slave_alloc,
1396 .slave_configure = stex_slave_config,
1397 .slave_destroy = stex_slave_destroy,
1398 .eh_abort_handler = stex_abort,
1399 .eh_host_reset_handler = stex_reset,
1400 .this_id = -1,
1401};
1402
1403static struct pci_device_id stex_pci_tbl[] = {
1404 /* st_shasta */
1405 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1406 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1407 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1408 st_shasta }, /* SuperTrak EX12350 */
1409 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1410 st_shasta }, /* SuperTrak EX4350 */
1411 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1412 st_shasta }, /* SuperTrak EX24350 */
1413
1414 /* st_vsc */
1415 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1416
1417 /* st_yosemite */
1418 { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1419
1420 /* st_seq */
1421 { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1422
1423 /* st_yel */
1424 { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1425 { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1426 { } /* terminate list */
1427};
1428
1429static struct st_card_info stex_card_info[] = {
1430 /* st_shasta */
1431 {
1432 .max_id = 17,
1433 .max_lun = 8,
1434 .max_channel = 0,
1435 .rq_count = 32,
1436 .rq_size = 1048,
1437 .sts_count = 32,
1438 .alloc_rq = stex_alloc_req,
1439 .map_sg = stex_map_sg,
1440 .send = stex_send_cmd,
1441 },
1442
1443 /* st_vsc */
1444 {
1445 .max_id = 129,
1446 .max_lun = 1,
1447 .max_channel = 0,
1448 .rq_count = 32,
1449 .rq_size = 1048,
1450 .sts_count = 32,
1451 .alloc_rq = stex_alloc_req,
1452 .map_sg = stex_map_sg,
1453 .send = stex_send_cmd,
1454 },
1455
1456 /* st_yosemite */
1457 {
1458 .max_id = 2,
1459 .max_lun = 256,
1460 .max_channel = 0,
1461 .rq_count = 256,
1462 .rq_size = 1048,
1463 .sts_count = 256,
1464 .alloc_rq = stex_alloc_req,
1465 .map_sg = stex_map_sg,
1466 .send = stex_send_cmd,
1467 },
1468
1469 /* st_seq */
1470 {
1471 .max_id = 129,
1472 .max_lun = 1,
1473 .max_channel = 0,
1474 .rq_count = 32,
1475 .rq_size = 1048,
1476 .sts_count = 32,
1477 .alloc_rq = stex_alloc_req,
1478 .map_sg = stex_map_sg,
1479 .send = stex_send_cmd,
1480 },
1481
1482 /* st_yel */
1483 {
1484 .max_id = 129,
1485 .max_lun = 256,
1486 .max_channel = 3,
1487 .rq_count = 801,
1488 .rq_size = 512,
1489 .sts_count = 801,
1490 .alloc_rq = stex_ss_alloc_req,
1491 .map_sg = stex_ss_map_sg,
1492 .send = stex_ss_send_cmd,
1493 },
1494};
1495
1496static int stex_set_dma_mask(struct pci_dev * pdev)
1497{
1498 int ret;
1499
1500 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1501 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
1502 return 0;
1503 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1504 if (!ret)
1505 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1506 return ret;
1507}
1508
1509static int stex_request_irq(struct st_hba *hba)
1510{
1511 struct pci_dev *pdev = hba->pdev;
1512 int status;
1513
1514 if (msi) {
1515 status = pci_enable_msi(pdev);
1516 if (status != 0)
1517 printk(KERN_ERR DRV_NAME
1518 "(%s): error %d setting up MSI\n",
1519 pci_name(pdev), status);
1520 else
1521 hba->msi_enabled = 1;
1522 } else
1523 hba->msi_enabled = 0;
1524
1525 status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1526 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1527
1528 if (status != 0) {
1529 if (hba->msi_enabled)
1530 pci_disable_msi(pdev);
1531 }
1532 return status;
1533}
1534
1535static void stex_free_irq(struct st_hba *hba)
1536{
1537 struct pci_dev *pdev = hba->pdev;
1538
1539 free_irq(pdev->irq, hba);
1540 if (hba->msi_enabled)
1541 pci_disable_msi(pdev);
1542}
1543
1544static int __devinit
1545stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1546{
1547 struct st_hba *hba;
1548 struct Scsi_Host *host;
1549 const struct st_card_info *ci = NULL;
1550 u32 sts_offset, cp_offset, scratch_offset;
1551 int err;
1552
1553 err = pci_enable_device(pdev);
1554 if (err)
1555 return err;
1556
1557 pci_set_master(pdev);
1558
1559 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1560
1561 if (!host) {
1562 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1563 pci_name(pdev));
1564 err = -ENOMEM;
1565 goto out_disable;
1566 }
1567
1568 hba = (struct st_hba *)host->hostdata;
1569 memset(hba, 0, sizeof(struct st_hba));
1570
1571 err = pci_request_regions(pdev, DRV_NAME);
1572 if (err < 0) {
1573 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1574 pci_name(pdev));
1575 goto out_scsi_host_put;
1576 }
1577
1578 hba->mmio_base = pci_ioremap_bar(pdev, 0);
1579 if ( !hba->mmio_base) {
1580 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1581 pci_name(pdev));
1582 err = -ENOMEM;
1583 goto out_release_regions;
1584 }
1585
1586 err = stex_set_dma_mask(pdev);
1587 if (err) {
1588 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1589 pci_name(pdev));
1590 goto out_iounmap;
1591 }
1592
1593 hba->cardtype = (unsigned int) id->driver_data;
1594 ci = &stex_card_info[hba->cardtype];
1595 sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1596 if (hba->cardtype == st_yel)
1597 sts_offset += (ci->sts_count+1) * sizeof(u32);
1598 cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1599 hba->dma_size = cp_offset + sizeof(struct st_frame);
1600 if (hba->cardtype == st_seq ||
1601 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1602 hba->extra_offset = hba->dma_size;
1603 hba->dma_size += ST_ADDITIONAL_MEM;
1604 }
1605 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1606 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1607 if (!hba->dma_mem) {
1608 /* Retry minimum coherent mapping for st_seq and st_vsc */
1609 if (hba->cardtype == st_seq ||
1610 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1611 printk(KERN_WARNING DRV_NAME
1612 "(%s): allocating min buffer for controller\n",
1613 pci_name(pdev));
1614 hba->dma_size = hba->extra_offset
1615 + ST_ADDITIONAL_MEM_MIN;
1616 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1617 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1618 }
1619
1620 if (!hba->dma_mem) {
1621 err = -ENOMEM;
1622 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1623 pci_name(pdev));
1624 goto out_iounmap;
1625 }
1626 }
1627
1628 hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1629 if (!hba->ccb) {
1630 err = -ENOMEM;
1631 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1632 pci_name(pdev));
1633 goto out_pci_free;
1634 }
1635
1636 if (hba->cardtype == st_yel)
1637 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1638 hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1639 hba->copy_buffer = hba->dma_mem + cp_offset;
1640 hba->rq_count = ci->rq_count;
1641 hba->rq_size = ci->rq_size;
1642 hba->sts_count = ci->sts_count;
1643 hba->alloc_rq = ci->alloc_rq;
1644 hba->map_sg = ci->map_sg;
1645 hba->send = ci->send;
1646 hba->mu_status = MU_STATE_STARTING;
1647
1648 if (hba->cardtype == st_yel)
1649 host->sg_tablesize = 38;
1650 else
1651 host->sg_tablesize = 32;
1652 host->can_queue = ci->rq_count;
1653 host->cmd_per_lun = ci->rq_count;
1654 host->max_id = ci->max_id;
1655 host->max_lun = ci->max_lun;
1656 host->max_channel = ci->max_channel;
1657 host->unique_id = host->host_no;
1658 host->max_cmd_len = STEX_CDB_LENGTH;
1659
1660 hba->host = host;
1661 hba->pdev = pdev;
1662 init_waitqueue_head(&hba->reset_waitq);
1663
1664 snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1665 "stex_wq_%d", host->host_no);
1666 hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1667 if (!hba->work_q) {
1668 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1669 pci_name(pdev));
1670 err = -ENOMEM;
1671 goto out_ccb_free;
1672 }
1673 INIT_WORK(&hba->reset_work, stex_reset_work);
1674
1675 err = stex_request_irq(hba);
1676 if (err) {
1677 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1678 pci_name(pdev));
1679 goto out_free_wq;
1680 }
1681
1682 err = stex_handshake(hba);
1683 if (err)
1684 goto out_free_irq;
1685
1686 err = scsi_init_shared_tag_map(host, host->can_queue);
1687 if (err) {
1688 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1689 pci_name(pdev));
1690 goto out_free_irq;
1691 }
1692
1693 pci_set_drvdata(pdev, hba);
1694
1695 err = scsi_add_host(host, &pdev->dev);
1696 if (err) {
1697 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1698 pci_name(pdev));
1699 goto out_free_irq;
1700 }
1701
1702 scsi_scan_host(host);
1703
1704 return 0;
1705
1706out_free_irq:
1707 stex_free_irq(hba);
1708out_free_wq:
1709 destroy_workqueue(hba->work_q);
1710out_ccb_free:
1711 kfree(hba->ccb);
1712out_pci_free:
1713 dma_free_coherent(&pdev->dev, hba->dma_size,
1714 hba->dma_mem, hba->dma_handle);
1715out_iounmap:
1716 iounmap(hba->mmio_base);
1717out_release_regions:
1718 pci_release_regions(pdev);
1719out_scsi_host_put:
1720 scsi_host_put(host);
1721out_disable:
1722 pci_disable_device(pdev);
1723
1724 return err;
1725}
1726
1727static void stex_hba_stop(struct st_hba *hba)
1728{
1729 struct req_msg *req;
1730 struct st_msg_header *msg_h;
1731 unsigned long flags;
1732 unsigned long before;
1733 u16 tag = 0;
1734
1735 spin_lock_irqsave(hba->host->host_lock, flags);
1736 req = hba->alloc_rq(hba);
1737 if (hba->cardtype == st_yel) {
1738 msg_h = (struct st_msg_header *)req - 1;
1739 memset(msg_h, 0, hba->rq_size);
1740 } else
1741 memset(req, 0, hba->rq_size);
1742
1743 if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
1744 req->cdb[0] = MGT_CMD;
1745 req->cdb[1] = MGT_CMD_SIGNATURE;
1746 req->cdb[2] = CTLR_CONFIG_CMD;
1747 req->cdb[3] = CTLR_SHUTDOWN;
1748 } else {
1749 req->cdb[0] = CONTROLLER_CMD;
1750 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1751 req->cdb[2] = CTLR_POWER_SAVING;
1752 }
1753
1754 hba->ccb[tag].cmd = NULL;
1755 hba->ccb[tag].sg_count = 0;
1756 hba->ccb[tag].sense_bufflen = 0;
1757 hba->ccb[tag].sense_buffer = NULL;
1758 hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1759
1760 hba->send(hba, req, tag);
1761 spin_unlock_irqrestore(hba->host->host_lock, flags);
1762
1763 before = jiffies;
1764 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1765 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1766 hba->ccb[tag].req_type = 0;
1767 return;
1768 }
1769 msleep(1);
1770 }
1771}
1772
1773static void stex_hba_free(struct st_hba *hba)
1774{
1775 stex_free_irq(hba);
1776
1777 destroy_workqueue(hba->work_q);
1778
1779 iounmap(hba->mmio_base);
1780
1781 pci_release_regions(hba->pdev);
1782
1783 kfree(hba->ccb);
1784
1785 dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1786 hba->dma_mem, hba->dma_handle);
1787}
1788
1789static void stex_remove(struct pci_dev *pdev)
1790{
1791 struct st_hba *hba = pci_get_drvdata(pdev);
1792
1793 scsi_remove_host(hba->host);
1794
1795 pci_set_drvdata(pdev, NULL);
1796
1797 stex_hba_stop(hba);
1798
1799 stex_hba_free(hba);
1800
1801 scsi_host_put(hba->host);
1802
1803 pci_disable_device(pdev);
1804}
1805
1806static void stex_shutdown(struct pci_dev *pdev)
1807{
1808 struct st_hba *hba = pci_get_drvdata(pdev);
1809
1810 stex_hba_stop(hba);
1811}
1812
1813MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1814
1815static struct pci_driver stex_pci_driver = {
1816 .name = DRV_NAME,
1817 .id_table = stex_pci_tbl,
1818 .probe = stex_probe,
1819 .remove = __devexit_p(stex_remove),
1820 .shutdown = stex_shutdown,
1821};
1822
1823static int __init stex_init(void)
1824{
1825 printk(KERN_INFO DRV_NAME
1826 ": Promise SuperTrak EX Driver version: %s\n",
1827 ST_DRIVER_VERSION);
1828
1829 return pci_register_driver(&stex_pci_driver);
1830}
1831
1832static void __exit stex_exit(void)
1833{
1834 pci_unregister_driver(&stex_pci_driver);
1835}
1836
1837module_init(stex_init);
1838module_exit(stex_exit);