blob: 15fd097b8c494df7366154ee961d23ed47926f26 [file] [log] [blame]
lh9ed821d2023-04-07 01:36:19 -07001/*******************************************************************************
2 * Copyright (C) 2016, ZXIC Corporation.
3 *
4 * File Name:
5 * File Mark:
6 * Description:
7 * Others:
8 * Version:
9 * Author:
10 * Date:
11 * History 1:
12 * Date:
13 * Version:
14 * Author:
15 * Modification:
16 * History 2:
17 ********************************************************************************/
18#ifndef __SDIO_H__
19#define __SDIO_H__
20
21
22//#if 0
23typedef signed char s8;
24typedef unsigned char u8;
25
26typedef signed short s16;
27typedef unsigned short u16;
28
29typedef signed int s32;
30typedef unsigned int u32;
31typedef unsigned long long u64;
32//#endif
33
34typedef u8 BYTE;
35typedef u32 WORD32;
36typedef u16 WORD16;
37
38#if 0
39typedef int int32_t;
40typedef u32 uint32_t;
41typedef u16 uint16_t;
42typedef u8 uint8_t;
43#endif
44
45
46#define MIN(x,y) ((x) < (y) ? (x) : (y))
47#define MAX(x,y) ((x) > (y) ? (x) : (y))
48#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
49#define REG(x) (*(volatile u32*)(x))
50#define REG8(x) (*(volatile u8*)(x))
51#define REG16(x) (*(volatile u16*)(x))
52#define REG32(x) (*(volatile u32*)(x))
53#define DWC_READ_REG32(a) (*(volatile u32 *)(a))
54#define DWC_WRITE_REG32(a,v) ((*(volatile u32 *)(a)) = v)
55
56
57/*SDIO ²ÎÊý*/
58#define SYS_SDIO_REGS_BASE 0x01540000 //SD1
59#define CFG_SDIO_LOAD_BASE 0x20000000 // SDIO DMA Êý¾Ý°áÔ˵ØÖ
60
61#define SDIO_CMD0 0 /* GO_IDLE_STATE bc */
62#define SDIO_CMD1 1 /* SEND_OP_COND bcr [31:0] OCR R3 */
63#define SDIO_CMD2 2 /* ALL_SEND_CID bcr R2 */
64#define SDIO_CMD3 3 /* SET_RELATIVE_ADDR ac [31:16] RCA R1 */
65#define SDIO_CMD4 4 /* SET_DSR bc [31:16] RCA */
66#define SDIO_CMD5 5 /* IO_SEND_OP_COND ?? ?? */
67#define SDIO_CMD6 6 /* SWITCH FUNC ac R1 */
68 /* For ACMD6:SET_BUS_WIDTH ?? ?? */
69#define SDIO_CMD7 7 /* SELECT_CARD ac [31:16] RCA R1 */
70#define SDIO_CMD8 8 /* SEND_IF_COND adtc [31:16] RCA R1 */
71#define SDIO_CMD9 9 /* SEND_CSD ac [31:16] RCA R2 */
72/* class 7 */
73#define SDIO_CMD52 52 /* SDIO_RW_DIRECT ?? R5 */
74#define SDIO_CMD53 53 /* SDIO_RW_EXTENDED ?? R5 */
75
76/*¼Ä´æÆ÷Æ«ÒÆ*/
77#define SDIO_SLAVE_REGS SYS_SDIO_REGS_BASE
78#define SDIO_SLAVE_CTRL (SDIO_SLAVE_REGS+0x00)
79#define SDIO_SLAVE_CMD (SDIO_SLAVE_REGS+0x04)
80#define SDIO_SLAVE_ARGU (SDIO_SLAVE_REGS+0x08)
81#define SDIO_SLAVE_BLKCNT (SDIO_SLAVE_REGS+0x0C)
82#define SDIO_SLAVE_DMA1ADDR (SDIO_SLAVE_REGS+0x10)
83#define SDIO_SLAVE_DMA1CTRL (SDIO_SLAVE_REGS+0x14)
84
85#define SDIO_SLAVE_ERASE_W_BLKSTART (SDIO_SLAVE_REGS+0x20)
86#define SDIO_SLAVE_ERASE_W_BLKEND (SDIO_SLAVE_REGS+0x24)
87#define SDIO_SLAVE_PASSLE (SDIO_SLAVE_REGS+0x28)
88#define SDIO_SLAVE_SECBLKCNT (SDIO_SLAVE_REGS+0x2C)
89
90#define SDIO_SLAVE_INTSTATUS (SDIO_SLAVE_REGS+0x3C)
91#define SDIO_SLAVE_INTSTATUS_EN (SDIO_SLAVE_REGS+0x40)
92#define SDIO_SLAVE_INTSIGNAL_EN (SDIO_SLAVE_REGS+0x44)
93#define SDIO_SLAVE_CARD_ADDR (SDIO_SLAVE_REGS+0x48)
94#define SDIO_SLAVE_CARD_DATA (SDIO_SLAVE_REGS+0x4C)
95#define SDIO_SLAVE_IOREADY (SDIO_SLAVE_REGS+0x50)
96#define SDIO_SLAVE_FUN1CTRL (SDIO_SLAVE_REGS+0x54)
97#define SDIO_SLAVE_FUN2CTRL (SDIO_SLAVE_REGS+0x58)
98#define SDIO_SLAVE_SDIO_CCCR_CTRL (SDIO_SLAVE_REGS+0x5C)
99#define SDIO_SLAVE_SDIO_FBRx_CTRL (SDIO_SLAVE_REGS+0x60) /* **sdio fbrx ctrl 0x60-0x7c*/
100
101#define SDIO_SLAVE_CARD_SIZE (SDIO_SLAVE_REGS+0x80)
102#define SDIO_SLAVE_CARD_OCR (SDIO_SLAVE_REGS+0x84)
103#define SDIO_SLAVE_CTRL2 (SDIO_SLAVE_REGS+0x88)
104
105#define SDIO_SLAVE_FUN3CTRL (SDIO_SLAVE_REGS+0x90)
106#define SDIO_SLAVE_FUN4CTRL (SDIO_SLAVE_REGS+0x94)
107#define SDIO_SLAVE_FUN5CTRL (SDIO_SLAVE_REGS+0x98)
108#define SDIO_SLAVE_INT_STATUS2 (SDIO_SLAVE_REGS+0x9C)
109#define SDIO_SLAVE_INT_STATUS_EN2 (SDIO_SLAVE_REGS+0xA0)
110#define SDIO_SLAVE_INT_SIGNAL_EN2 (SDIO_SLAVE_REGS+0xA4)
111/*#define SDIO_SLAVE_PASS_127_96 (SDIO_SLAVE_REGS+0xA8)
112#define SDIO_SLAVE_PASS_95_64 (SDIO_SLAVE_REGS+0xAC)
113#define SDIO_SLAVE_PASS_63_32 (SDIO_SLAVE_REGS+0xB0)
114#define SDIO_SLAVE_PASS_31_0 (SDIO_SLAVE_REGS+0xB4)
115#define SDIO_SLAVE_ADMA_ERR_STATUS (SDIO_SLAVE_REGS+0xB8)
116#define SDIO_SLAVE_RCA (SDIO_SLAVE_REGS+0xBC)
117#define SDIO_SLAVE_DBG0 (SDIO_SLAVE_REGS+0xC0)
118#define SDIO_SLAVE_DBG1 (SDIO_SLAVE_REGS+0xC4)
119#define SDIO_SLAVE_DBG2 (SDIO_SLAVE_REGS+0xC8)
120#define SDIO_SLAVE_DBG3 (SDIO_SLAVE_REGS+0xCC)
121#define SDIO_SLAVE_DBG4 (SDIO_SLAVE_REGS+0xD0)
122#define SDIO_SLAVE_DBG5 (SDIO_SLAVE_REGS+0xD4)
123#define SDIO_SLAVE_DBG6 (SDIO_SLAVE_REGS+0xD8)
124#define SDIO_SLAVE_AHB (SDIO_SLAVE_REGS+0xDC)
125#define SDIO_SLAVE_ARGU2 (SDIO_SLAVE_REGS+0xE0)*/
126
127
128/*SDIO_SLAVE_INT_STATUS*/
129#define SDIO_STS_B_C (1<<31) //BOOT COMPLETE
130#define SDIO_STS_LRST (1<<30) //LRST
131#define SDIO_STS_F_A (1<<29) //FUNCTIONX Abort
132#define SDIO_STS_F_CRC_E (1<<28) //FunctionX CRC End Error
133#define SDIO_STS_CMD_R1B (1<<27) //CMD R1B
134#define SDIO_STS_CMD40 (1<<26) //CMD40
135#define SDIO_STS_PRG_ST (1<<25) //PROGRAM START
136#define SDIO_STS_CMD11_C_ST (1<<24) //CMD11 CLK START
137#define SDIO_STS_CMD11_C_SP (1<<23) //CMD11 CLK STOP
138#define SDIO_STS_F2_R (1<<22) //Funtion2 reset
139#define SDIO_STS_F1_R (1<<21) //Funtion1 reset
140#define SDIO_STS_BS (1<<20) //Boot Start
141#define SDIO_STS_CMD4 (1<<19) //CMD4
142#define SDIO_STS_CMD20 (1<<17) //CMD20
143#define SDIO_STS_ACMD23 (1<<16) //ACMD23
144#define SDIO_STS_P_CSD (1<<15) //Program CSD interrupt
145#define SDIO_STS_CMD6_SD (1<<14) //CMD6-Switch Done
146#define SDIO_STS_CMD6_CD (1<<13) //CMD6-Check Done
147#define SDIO_STS_CMD2_CMD52 (1<<12) //Soft Reset
148#define SDIO_STS_CMD11 (1<<11) //Command11 Voltage switch interrupt
149#define SDIO_STS_E (1<<10) //Erase
150#define SDIO_STS_FE (1<<9) //Force Erase
151#define SDIO_STS_UC (1<<8) //Unlock Card
152#define SDIO_STS_LC (1<<7) //Lock Card
153#define SDIO_STS_PR (1<<6) //Password Reset
154#define SDIO_STS_PS (1<<5) //Password Set
155#define SDIO_STS_RS (1<<4) //Read Start
156#define SDIO_STS_WS (1<<3) //Write Start
157#define SDIO_STS_SA (1<<2) //Sleep awake
158#define SDIO_STS_DMA1 (1<<1) //Dma1 interrupt
159#define SDIO_STS_TC (1<<0) //Transfer Complete interrupt
160
161
162void sdio_slave_process(void);
163
164
165
166#endif /* __SDIO_DRV_H__ */
167
168