| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | /*******************************************************************************
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| 2 | * Copyright (C) 2016, ZXIC Corporation.
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| 3 | *
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| 4 | * File Name:
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| 5 | * File Mark:
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| 6 | * Description:
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| 7 | * Others:
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| 8 | * Version: v1.0
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| 9 | * Author: zhouqi
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| 10 | * Date: 2013-8-21
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| 11 | * History 1:
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| 12 | * Date:
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| 13 | * Version:
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| 14 | * Author:
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| 15 | * Modification:
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| 16 | * History 2:
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| 17 | ********************************************************************************/
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| 18 |
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| 19 | #ifndef _ZX297510_DDR_H_
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| 20 | #define _ZX297510_DDR_H_
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| 21 |
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| 22 |
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| 23 | //#define DDR_FFC
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| 24 | typedef unsigned int UINT32;
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| 25 | typedef unsigned char UINT8;
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| 26 | #if 0
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| 27 | /*ddr É豸¼Ä´æÆ÷½á¹¹Ìå*/
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| 28 | struct ddr_device_para
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| 29 | {
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| 30 | unsigned int reg_0x12030f4; /* ¼Ä´æÆ÷ 0x12030f4 */
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| 31 | };
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| 32 | #endif
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| 33 |
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| 34 |
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| 35 | typedef enum
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| 36 | {
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| 37 | DDR_156M = 0,
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| 38 | DDR_208M = 1,
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| 39 | DDR_312M = 2,
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| 40 | DDR_400M = 3,
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| 41 | DDR_CLKEND
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| 42 | }T_zDrvPow_DDRCLK;
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| 43 |
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| 44 |
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| 45 | /*DDR*/
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| 46 | #define DDR_CTRL_BASE (0x00150000)
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| 47 | #define DDR_PHY_BASE (0x00154000)
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| 48 | #define DDR_FFC_ADDR_BASE (0x00155000)
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| 49 |
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| 50 |
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| 51 | #define STD_CRM_REG_BASE (0x01306000)
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| 52 |
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| 53 | #define CRTL_PWRCTL (DDR_CTRL_BASE+0x030)
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| 54 |
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| 55 | /*DDR CTRL MP*/
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| 56 |
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| 57 | #define CTRL_STAT (DDR_CTRL_BASE+0x004)
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| 58 |
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| 59 | #define MOD_CLK_SEL (STD_CRM_REG_BASE+0x50)
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| 60 |
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| 61 | #define SELFREF_SW (5)
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| 62 |
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| 63 | #define CHIP_DDR_IS_32M 0
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| 64 | #define CHIP_DDR_IS_64M 1
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| 65 | #define CHIP_DDR_IS_128M 2
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| 66 | #define CHIP_DDR_IS_256M 3
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| lh | 758261d | 2023-07-13 05:52:04 -0700 | [diff] [blame^] | 67 | #define CHIP_DDR_IS_512M 4
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| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 68 |
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| 69 |
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| 70 | int ddr_init(int flag);
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| 71 |
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| 72 |
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| 73 | #endif/*_ZX297510_DDR_H_*/
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| 74 |
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| 75 |
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