| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | #ifndef _MPU_H
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| 2 | #define _MPU_H
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| 3 |
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| 4 | typedef volatile struct
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| 5 | {
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| 6 | int32_t dwNum;
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| 7 | int32_t dwBase;
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| 8 | int32_t dwSize;
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| 9 | int32_t dwMemAttr;
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| 10 | int32_t dwShare;
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| 11 | int32_t dwAP;
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| 12 | int32_t dwXN;
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| 13 | int32_t dwSubRegion;
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| 14 | }T_Region_Attr;
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| 15 |
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| 16 | #define MPU_REGION_SO (0)// strongly-ordered memory
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| 17 | #define MPU_REGION_SD (1)// ¹²ÏíÉ豸memory
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| 18 | #define MPU_REGION_NM_INC_ONC (4)// nomal memory,²»ÄÜcache
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| 19 | #define MPU_REGION_NM_IWBWA_OWBWA (7)// nomal memory, д»Øд·ÖÅä
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| 20 | #define MPU_REGION_NSD (8)// ·Ç¹²ÏíÉ豸memory
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| 21 | #define MPU_REGION_NM_IWBWA_ONC (17)// nomal memory,²»ÄÜcacheµ½L2 cache£¬¿ÉÒÔµ½L1 cache д»Øд·ÖÅä
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| 22 | #define MPU_REGION_NM_INC_OWBWA (20)// nomal memory,²»ÄÜcacheµ½L1 cache£¬¿ÉÒÔµ½L2 cache д»Øд·ÖÅä
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| 23 | //#define MPU_REGION_NM_IWBWA_OWBWA (21)// nomal memory,¿ÉÒÔµ½L1 cache д»Øд·ÖÅ䣬¿ÉÒÔµ½L2 cache д»Øд·ÖÅä
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| 24 |
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| 25 |
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| 26 | /* mpuÏà¹Ø¼Ä´æÆ÷λÓòºê¶¨Òå */
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| 27 | /* MPU ÇøÓò»ùÖ·¼Ä´æÆ÷
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| 28 | * λÖãºcp15 0 c6 c1 0
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| 29 | * ¹¦ÄÜ˵Ã÷£ºÉèÖÃÇøÓò»ùÖ·
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| 30 | * ʹÓÃ˵Ã÷£º1)Ö»ÄÜÔÚÌØȨģʽÏ·ÃÎÊ 2)ÓëÇøÓò´óС¶ÔÆë
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| 31 | * Example£º MRC p15,0,<Rt>,c6,c1,0 ; Read
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| 32 | * +---------------------------+-----------+
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| 33 | * | 31- 5 | 4 - 0 |
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| 34 | * +---------------------------+-----------+
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| 35 | * | Base Address | Reserved |
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| 36 | * +---------------------------+-----------+
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| 37 | */
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| 38 |
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| 39 | /* mpuÏà¹Ø¼Ä´æÆ÷λÓòºê¶¨Òå */
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| 40 | /* MPU ÇøÓò´óС¼°Ê¹ÄܼĴæÆ÷
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| 41 | * λÖãºcp15 0 c6 c1 2
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| 42 | * ¹¦ÄÜ˵Ã÷£ºÉèÖÃÇøÓò´óС¼°Ê¹ÄÜÇøÓò¡¢×ÓÇøÓò
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| 43 | * ʹÓÃ˵Ã÷£º1)Ö»ÄÜÔÚÌØȨģʽÏ·ÃÎÊ
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| 44 | * Example£º MRC p15,0,<Rt>,c6,c1,2 ; Read
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| 45 | * +---------------------------+-----------+
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| 46 | * | 31-16| 15-8 | 7-6 | 5-1 | 0 |
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| 47 | * +---------------------------+-----------+
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| 48 | * | Re | SubRegion Dis| Re | Size | En |
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| 49 | * +---------------------------+-----------+
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| 50 | */
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| 51 | #define MPU_EN_POS (0)
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| 52 | #define MPU_EN_MASK (0x1 << MPU_EN_POS)
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| 53 |
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| 54 | #define MPU_SIZE_POS (1)
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| 55 | #define MPU_SIZE_MASK (0x1f << MPU_SIZE_POS)
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| 56 |
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| 57 | #define MPU_SUBREGION_DIS_POS (8)
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| 58 | #define MPU_SUBREGION_DIS_MASK (0xff << MPU_SUBREGION_DIS_POS)
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| 59 |
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| 60 | #define MPU_REGIONG_EN
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| 61 | #define MPU_REGIONG_DIS
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| 62 |
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| 63 | #define REGION_SIZE_256B 0x07
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| 64 | #define REGION_SIZE_512B 0x08
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| 65 | #define REGION_SIZE_1K 0x09
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| 66 | #define REGION_SIZE_2K 0x0a
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| 67 | #define REGION_SIZE_4K 0x0b
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| 68 | #define REGION_SIZE_8K 0x0c
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| 69 | #define REGION_SIZE_16K 0x0d
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| 70 | #define REGION_SIZE_32K 0x0e
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| 71 | #define REGION_SIZE_64K 0x0f
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| 72 | #define REGION_SIZE_128K 0x10
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| 73 | #define REGION_SIZE_256K 0x11
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| 74 | #define REGION_SIZE_512K 0x12
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| 75 | #define REGION_SIZE_1M 0x13
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| 76 | #define REGION_SIZE_2M 0x14
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| 77 | #define REGION_SIZE_4M 0x15
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| 78 | #define REGION_SIZE_8M 0x16
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| 79 | #define REGION_SIZE_16M 0x17
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| 80 | #define REGION_SIZE_32M 0x18
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| 81 | #define REGION_SIZE_64M 0x19
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| 82 | #define REGION_SIZE_128M 0x1a
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| 83 | #define REGION_SIZE_256M 0x1b
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| 84 | #define REGION_SIZE_512M 0x1c
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| 85 | #define REGION_SIZE_1G 0x1d
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| 86 | #define REGION_SIZE_2G 0x1e
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| 87 | #define REGION_SIZE_4G 0x1f
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| 88 |
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| 89 | /* mpuÏà¹Ø¼Ä´æÆ÷λÓòºê¶¨Òå */
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| 90 | /* MPU ÇøÓò·ÃÎÊÊôÐÔ¿ØÖƼĴæÆ÷
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| 91 | * λÖãºcp15 0 c6 c1 4
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| 92 | * ¹¦ÄÜ˵Ã÷£ºÉèÖÃÇøÓò·ÃÎÊÊôÐÔ
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| 93 | * ʹÓÃ˵Ã÷£º1)Ö»ÄÜÔÚÌØȨģʽÏ·ÃÎÊ
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| 94 | * Example£º MRC p15,0,<Rt>,c6,c1,4 ; Read
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| 95 | * +------------------------------+-----------------+
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| 96 | * | 31-13 | 12 | 11 | 10-8 | 7-6 | 5-3 | 2 | 1 | 0 |
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| 97 | * +------------------------------+-----------------+
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| 98 | * | Re | XN | Re | AP | Re | TEX | S | C | B |
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| 99 | * +------------------------------+-----------------+
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| 100 | */
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| 101 | #define MPU_REGION_B_POS (0)
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| 102 | #define MPU_REGION_B_MASK (0x1 << MPU_REGION_B_POS)
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| 103 |
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| 104 | #define MPU_REGION_C_POS (1)
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| 105 | #define MPU_REGION_C_MASK (0x1 << MPU_REGION_C_POS)
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| 106 |
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| 107 | #define MPU_REGION_S_POS (2)
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| 108 | #define MPU_REGION_S_MASK (0x1 << MPU_REGION_S_POS)
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| 109 |
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| 110 | #define MPU_REGION_TEX_POS (3)
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| 111 | #define MPU_REGION_TEX_MASK (0x7 << MPU_REGION_TEX_POS)
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| 112 |
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| 113 | #define MPU_REGION_AP_POS (8)
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| 114 | #define MPU_REGION_AP_MASK (0x7 << MPU_REGION_AP_POS)
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| 115 |
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| 116 | #define MPU_REGION_XN_POS (12)
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| 117 | #define MPU_REGION_XN_MASK (0x1 << MPU_REGION_XN_POS)
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| 118 |
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| 119 | /* mpuÏà¹Ø¼Ä´æÆ÷λÓòºê¶¨Òå */
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| 120 | /* MPU ÇøÓòÑ¡Ôñ¼Ä´æÆ÷
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| 121 | * λÖãºcp15 0 c6 c2 0
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| 122 | * ¹¦ÄÜ˵Ã÷£ºÉèÖÃÇøÓò»ùÖ·
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| 123 | * ʹÓÃ˵Ã÷£º1)Ö»ÄÜÔÚÌØȨģʽÏ·ÃÎÊ 2)ÓëÇøÓò´óС¶ÔÆë
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| 124 | * Example£º MRC p15,0,<Rt>,c6,c2,0 ; Read
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| 125 | * +---------------------------+-----------+
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| 126 | * | 31- 4 | 3 - 0 |
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| 127 | * +---------------------------+-----------+
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| 128 | * | Re | Region |
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| 129 | * +---------------------------+-----------+
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| 130 | */
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| 131 |
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| 132 |
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| 133 | #define MPU_REGION_NUM_POS (0)
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| 134 | #define MPU_REGION_NUM_MASK (0xf << MPU_REGION_NUM_POS)
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| 135 |
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| 136 |
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| 137 |
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| 138 |
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| 139 | int32_t MPU_RegionInit(T_Region_Attr* ptRegion);
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| 140 | void MPU_Init(void);
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| 141 | int32_t MPU_Size2Sec(int32_t dwSize);
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| 142 | void MPU_RegionDisable(int32_t dwNum, int32_t dwEnable);
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| 143 |
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| 144 |
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| 145 | #endif
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| 146 |
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