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192.168.1.100 / T106_DC / 758261d1c1850656b47c4c40486e4237bcd769a6 / . / cp / ps / driver / inc / misc / drvs_int.h
blob: 9b378f59f64b6676a186395be3ee8879e42e4345 [file] [log] [blame]
lh9ed821d2023-04-07 01:36:19 -0700[diff] [blame]1/**
2* @file drvs_int.h
3* @brief Public APIs of int drivers
4*
5* Copyright (C) 2017 Sanechips Technology Co., Ltd.
6* @author Dongdong Zhang <Zhang.Dongdong@sanechips.com.cn>
7*
8* This program is free software; you can redistribute it and/or modify
9* it under the terms of the GNU General Public License version 2 as
10* published by the Free Software Foundation.
11*
12*/
13#ifndef _DRVS_INT_H
14#define _DRVS_INT_H
15
16/*******************************************************************************
17 * Include header files *
18 ******************************************************************************/
19#include "drvs_general.h"
20
21#ifdef _OS_LINUX
22#include <linux/irq.h>
23#endif
24
25/*******************************************************************************
26 * Macro definitions *
27 ******************************************************************************/
28#define INT_PRI_NUM 15 /* 0-highest, 15-lowest, but 15 is always be masked in gic*/
29 /*so in fact, only 0-14 can generate interrupt*/
30
31#define MAX_NEST_NUM 32 /* maximum number of nested interrupt */
32
33
34#define INT_TABLE_END 0xFFFF
35#define INT_VECTOR_DEFAULT 0xFFFF
36#define INT_PRIORITY_DEFAULT 14
37#define INT_INVALID_INTLINE 0xFFFFFFFF
38
39#if 1//modify by xxx ndef _OS_LINUX
40
41/*
42 * 0-15: SGI (software generated interrupts)
43 * 16-31: PPI (private peripheral interrupts)
44 * 32+: SPI (shared peripheral interrupts)
45 */
46#define GIC_PPI_START 16
47#define GIC_SPI_START 32
48
49#define RESERVED_INT 0xffff
50
51/*
52 * software generated interrupts
53 */
54#define SGI0_INT (0)
55#define SGI1_INT (1)
56#define SGI2_INT (2)
57#define SGI3_INT (3)
58#define SGI4_INT (4)
59#define SGI5_INT (5)
60#define SGI6_INT (6)
61#define SGI7_INT (7)
62#define SGI8_INT (8)
63#define SGI9_INT (9)
64#define SGI10_INT (10)
65#define SGI11_INT (11)
66#define SGI12_INT (12)
67#define SGI13_INT (13)
68#define SGI14_INT (14)
69#define SGI15_INT (15)
70
71/*
72 * private peripheral interrupts
73 */
74#define GLOBAL_TIMER_INT (27)
75#define LEGACY_FIQ_INT (28)
76#define PRIVATE_TIMER_INT (29)
77#define PRIVATE_WDT_INT (30)
78#define LEGACY_IRQ_INT (31)
79
80/*
81 * shared peripheral interrupts
82 */
83#define UART0_INT (GIC_SPI_START+0)
84#define UART1_INT (GIC_SPI_START+1)
85#define UART2_INT (GIC_SPI_START+2)
86#define SSP0_INT (GIC_SPI_START+3)
87#define PS_SYS_COUNTER (GIC_SPI_START+4)
88#define RTC_ALARM_INT (GIC_SPI_START+5)
89#define RTC_TIMER_INT (GIC_SPI_START+6)
90#define I2S0_INT (GIC_SPI_START+7)
91#define I2S1_INT (GIC_SPI_START+8)
92#define USIM1_INT (GIC_SPI_START+9)
93#define I2C1_INT (GIC_SPI_START+10)
94#define PMIC_I2C_INT (GIC_SPI_START+11)
95#define KEYPAD_INT (GIC_SPI_START+12)
96#define SD1_INT (GIC_SPI_START+13)
97#define WLAN_PRIORITY_POS_INT (GIC_SPI_START+14)
98#define WLAN_PRIORITY_NEG_INT (GIC_SPI_START+15)
99#define SD0_INT (GIC_SPI_START+16)
100#define ICP_PHY_INT (GIC_SPI_START+17)
101#define ICP_M0_INT (GIC_SPI_START+18)
102#define TIMER0_INT (GIC_SPI_START+19) /*ps timer0*/
103#define TIMER1_INT (GIC_SPI_START+20) /*ps timer1*/
104#define PS_RM_TIMER_INT (GIC_SPI_START+21) /*ps rm timer*/
105#define GSMIF_RFSSCR_INT (GIC_SPI_START+22)
106#define GSMIF_RFSSCT_INT (GIC_SPI_START+23)
107#define GSMIF_GP0_INT (GIC_SPI_START+24)
108#define GSMIF_T_INT (GIC_SPI_START+25)
109#define GSMIF_TL_INT (GIC_SPI_START+26)
110#define GPRS_INT0 (GIC_SPI_START+27)
111#define GPRS_INT1 (GIC_SPI_START+28)
112#define DSP_INT0 (GIC_SPI_START+29)
113#define DSP_INT1 (GIC_SPI_START+30)
114#define DSP_INT2 (GIC_SPI_START+31)
115#define DSP_INT3 (GIC_SPI_START+32)
116#define DSP_INT4 (GIC_SPI_START+33)
117#define DSP_INT6 (GIC_SPI_START+34)
118#define DSP_INT7 (GIC_SPI_START+35)
119#define GSM_LPM_INT0 (GIC_SPI_START+36)
120#define RCOUT1_INT (GIC_SPI_START+37)
121#define DMAC0_INT (GIC_SPI_START+38) /*ps dma int1 to ps*/
122#define DMAC1_INT (GIC_SPI_START+39) /*phy dma int1 to ps*/
123#define NAND_INT (GIC_SPI_START+40)
124#define USB_INT (GIC_SPI_START+41)
125#define USB_POWERDWN_UP_INT (GIC_SPI_START+42)
126#define USB_POWERDWN_DOWN_INT (GIC_SPI_START+43)
127#define HSIC_INT (GIC_SPI_START+44)
128#define HSIC_POWERDWN_UP_INT (GIC_SPI_START+45)
129#define HSIC_POWERDWN_DOWN_INT (GIC_SPI_START+46)
130
131#define GSM_USIM_INT (GIC_SPI_START+48)
132
133#define EX8IN1_INT (GIC_SPI_START+51) /*only used by int driver*/
134#define EX0_INT (GIC_SPI_START+52)
135#define EX1_INT (GIC_SPI_START+53)
136#define EX2_INT (GIC_SPI_START+54)
137#define EX3_INT (GIC_SPI_START+55)
138#define EX4_INT (GIC_SPI_START+56)
139#define EX5_INT (GIC_SPI_START+57)
140#define EX6_INT (GIC_SPI_START+58)
141#define EX7_INT (GIC_SPI_START+59)
142#define SSC0_CONFLICT_INT (GIC_SPI_START+60)
143#define TD_LPM4_INT (GIC_SPI_START+61)
144#define TD_FRM_INT (GIC_SPI_START+62)
145#define TD_FRM32K_INT (GIC_SPI_START+63)
146#define LTE_LPM2_INT (GIC_SPI_START+64)
147#define LTE_LPM4_INT (GIC_SPI_START+65)
148#define LTE_LPM5_INT (GIC_SPI_START+66)
149#define GSM_LPM_INT1 (GIC_SPI_START+67)
150#define LTE_TPU_INT (GIC_SPI_START+68)
151#define WD_LPM4_INT (GIC_SPI_START+69)
152#define WD_FRM_INT (GIC_SPI_START+70)
153#define EDCP_INT (GIC_SPI_START+71)
154#define SD1_DATA1_INT (GIC_SPI_START+72)
155
156#if defined (_CHIP_ZX297520V3)
157#define UART0_RXD_INT (GIC_SPI_START+73)
158#elif defined (_CHIP_ZX297520V2)
159#define UART0_CTS_INT (GIC_SPI_START+73)
160#endif
161
162#define SPIFC0_INT (GIC_SPI_START+74)
163#define TIMER2_INT (GIC_SPI_START+75) /*ps timer2*/
164#define PS_WDT_INT (GIC_SPI_START+76)
165#define ICP_AP_INT (GIC_SPI_START+77)
166#define SSP1_INT (GIC_SPI_START+78)
167#define SD0_DATA1_INT (GIC_SPI_START+79)
168#define TDM_INT (GIC_SPI_START+80)
169#define PHY_TIMER0_INT (GIC_SPI_START+81)
170#define PHY_TIMER1_INT (GIC_SPI_START+82)
171#define TD_MODEM_INT0 (GIC_SPI_START+83)
172#define TD_MODEM_INT1 (GIC_SPI_START+84)
173#define TD_MODEM_INT2 (GIC_SPI_START+85)
174#define LTE_MODEM_INT0 (GIC_SPI_START+86)
175#define LTE_MODEM_INT1 (GIC_SPI_START+87)
176#define LTE_MODEM_INT2 (GIC_SPI_START+88)
177#define WD_MODEM_INT0 (GIC_SPI_START+89)
178#define WD_MODEM_INT1 (GIC_SPI_START+90)
179#define WD_MODEM_INT2 (GIC_SPI_START+91)
180#define TD_LPM_ZSP_EXT_INT (GIC_SPI_START+92)
181#define LTE_LPM1_INT (GIC_SPI_START+93)
182#define WD_LPM3_INT (GIC_SPI_START+94)
183#define EDCP_PHY_INT (GIC_SPI_START+95)
184
185#define GIC_INT_NUM (EDCP_PHY_INT+1)
186
187/*virtual external 8in1 interrupts*/
188#define EX8_INT (GIC_SPI_START+96)
189#define EX9_INT (GIC_SPI_START+97)
190#define EX10_INT (GIC_SPI_START+98)
191#define EX11_INT (GIC_SPI_START+99)
192#define EX12_INT (GIC_SPI_START+100)
193#define EX13_INT (GIC_SPI_START+101)
194#define EX14_INT (GIC_SPI_START+102)
195#define EX15_INT (GIC_SPI_START+103)
196
197#define EX8IN1_INT_NUM (8)
198
199#define INT_LINES_NUM (EX15_INT+1)
200
201#if 0 /*7520V2 reserved*/
202/*
203 *virtual gpio interrupts
204 *interrupt number should be defined by user
205 *example:
206 * #define GPIO23_INT (GPIO_INT0_START+23)
207 * #define GPIO130_INT (GPIO_INT1_START+3) or (GPIO_INT0_START+130)
208 */
209
210/*
211 *gpio0 --- GPIO_INT0_START
212 *gpio127 --- GPIO_INT0_END
213 */
214#define GPIO_INT0_START (EX15_INT+1)
215#define GPIO_INT0_END (GPIO_INT0_START+127)
216
217/*
218 *gpio128 --- GPIO_INT1_START
219 *gpio255 --- GPIO_INT1_END
220 */
221#define GPIO_INT1_START (GPIO_INT0_END+1)
222#define GPIO_INT1_END (GPIO_INT1_START+127)
223
224
225#define INT_LINES_NUM (GPIO_INT1_END + 1) /*ÖжϸöÊý*/
226#endif
227
228#endif
229
230/*******************************************************************************
231* Type definitions *
232******************************************************************************/
233typedef struct _T_zDrvIntTable
234{
235 UINT32 uIntLine; /*the intline of the dev*/
236 UINT32 uIntPri; /*hardware priority*/
237 UINT32 vector; /*OSE vector,should be convert to type OSVECTOR */
238 UINT32 level; /*CPU trigger level*/
239}
240T_zDrvIntTable;
241
242#ifdef _OS_TOS
243typedef enum _T_zDrvIntLineLevel
244{
245 INT_HIGHLEVEL = 0x00, /* 00: high level */
246 INT_LOWLEVEL = 0x01, /* 01: low level */
247 INT_POSEDGE = 0x02, /* 10: raise edge */
248 INT_NEGEDGE = 0x03, /* 11: fall edge */
249 INT_DEFAULT_LEVEL,
250}
251T_zDrvIntLineLevel;
252#endif
253
254#ifdef _OS_LINUX
255typedef enum _T_zDrvIntLineLevel
256{
257 INT_HIGHLEVEL = IRQ_TYPE_LEVEL_HIGH, /* 0x4: high level */
258 INT_LOWLEVEL = IRQ_TYPE_LEVEL_LOW, /* 0x8: low level */
259 INT_POSEDGE = IRQ_TYPE_EDGE_RISING, /* 0x1: raise edge */
260 INT_NEGEDGE = IRQ_TYPE_EDGE_FALLING, /* 0x2: fall edge */
261 INT_DUALEDGE = IRQ_TYPE_EDGE_BOTH, /* 0x3: fall and raise edge, it can only be applyed to GPIO int */
262 INT_DEFAULT_LEVEL = 0xf,
263}
264T_zDrvIntLineLevel;
265#endif
266
267/*******************************************************************************
268 * Global function declarations *
269 ******************************************************************************/
270
271/**
272 *@brief This function is used to install isr into tos
273 *@param line interrupt line(0--INT_LINES_NUM)
274 *@param pEntry the point to isr entry
275 *@param pName isr name
276 *@param level int line trigger level
277 *
278 *@note the level is source trigger level. if you don't know the int trigger level, you can set the level:INT_DEFAULT_LEVEL.
279 *
280 *@return id of interrupt handler process if successed, errcode otherwise.
281 */
282SINT32 zDrvInt_InstallIsr(UINT32 line, VOID *pEntry, const CHAR * pName,
283 T_zDrvIntLineLevel level);
284
285/**
286 *@brief This function is used to uninstall isr
287 *@param line interrupt line(0--INT_LINES_NUM)
288 *
289 *@return 0 if successed, errcode otherwise.
290 */
291SINT32 zDrvInt_UninstallIsr(UINT32 line);
292
293/**
294 *@brief This function is used to mask irq
295 *@param line interrupt line(0--INT_LINES_NUM)
296 *
297 *@return 0 if successed, errcode otherwise.
298 */
299VOID zDrvInt_MaskIrq(UINT32 line);
300
301/**
302 *@brief This function is used to unmask irq
303 *@param line interrupt line(0--INT_LINES_NUM)
304 *
305 *@return 0 if successed, errcode otherwise.
306 */
307VOID zDrvInt_UnmaskIrq(UINT32 line);
308
309/**
310 *@brief This function is used to set int trigger level
311 *@param line interrupt line(0--INT_LINES_NUM)
312 *@param level int line trigger level
313 *
314 *@return 0 if successed, errcode otherwise.
315 */
316SINT32 zDrvInt_SetLineLevel(UINT32 line, T_zDrvIntLineLevel level);
317
318/**
319 *@brief This function is used to clear int status
320 *@param line interrupt line(0--INT_LINES_NUM)
321 *
322 *@return 0 if successed, errcode otherwise.
323 */
324SINT32 zDrvInt_ClearInt(UINT32 line);
325
326/**
327 *@brief This function is used to set int priority
328 *@param line interrupt line(0--INT_LINES_NUM)
329 *@param pri priority number
330 *
331 *@return 0 if successed, errcode otherwise.
332 */
333VOID zDrvInt_SetLinePri(UINT32 line, UINT32 pri);
334
335#ifdef _OS_LINUX
336/**
337 *@brief This function is used to install isr into linux
338 *@param line interrupt line(0--INT_LINES_NUM)
339 *@param pEntry the point to isr entry
340 *@param pName isr name
341 *@param level int line trigger level
342 *
343 *@note the level is source trigger level. if you don't know the int trigger level, you can set the level:INT_DEFAULT_LEVEL.
344 *
345 *@return id of interrupt handler process if successed, errcode otherwise.
346 */
347SINT32 zDrvInt_InstallFastIsr( UINT32 uiLine, VOID *pEntry, const CHAR * pName,
348 T_zDrvIntLineLevel level);
349
350/**
351 *@brief This function is used to install nested isr for interrupt line uiLine.
352 *@param line interrupt line(0--INT_LINES_NUM)
353 *@param pEntry the point to isr entry
354 *@param pName isr name
355 *
356 *@return id of interrupt handler process if successed, errcode otherwise.
357 */
358SINT32 zDrvInt_InstallNestedIsr( UINT32 uiLine, VOID *pEntry, const CHAR * pName);
359
360#endif
361
362#ifdef _OS_TOS
363/**
364 *@brief This function is used to install isr into tos
365 *@param line interrupt line(0--INT_LINES_NUM)
366 *@param pEntry the point to isr entry
367 *@param pName isr name
368 *@param level int line trigger level
369 *
370 *@note the level is source trigger level. if you don't know the int trigger level, you can set the level:INT_DEFAULT_LEVEL.
371 *
372 *@return id of interrupt handler process if successed, errcode otherwise.
373 */
374SINT32 zDrvInt_InstallIsrDsr(UINT32 line, VOID *pIsrEntry,
375 VOID *pDsrEntry, T_zDrvIntLineLevel level);
376
377/**
378 *@brief This function is used to distinguish whether this interrupt need to delay umask or not
379 *@param line interrupt line(0--INT_LINES_NUM)
380 *
381 *@note invoked by os.
382 *
383 *@return 0 if need to delay umask; 1 otherwise.
384 */
385SINT32 zDrvInt_DelayUnmask(UINT32 intLine);
386
387/**
388 *@brief This function is used to initiate interrupt controller, can only be used when system bringing up
389 *
390 *@param none.
391 *
392 *@return none.
393 */
394VOID zDrvInt_Initiate(VOID);
395
396/**
397 *@brief This function is used to delay unmask an interrupt when isr is completed.
398 *@param line interrupt line(0--INT_LINES_NUM)
399 *
400 *@note it must be used before installing irq, and you should unmask this int manually after isr is completed.
401 *
402 *@return none.
403 */
404VOID zDrvInt_DelayUnmaskAdd(UINT32 intLine);
405
406/**
407 *@brief This function is used to remove the delay unmask function for an interrupt.
408 *@param line interrupt line(0--INT_LINES_NUM)
409 *
410 *@return none.
411 */
412VOID zDrvInt_DelayUnmaskRemove(UINT32 intLine);
413
414#endif
415
416#endif /* DRVS_INT_H */