| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | /*******************************************************************************
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| 2 | * Copyright (C) 2014, ZTE Corporation.
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| 3 | *
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| 4 | * File Name:
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| 5 | * File Mark:
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| 6 | * Description:
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| 7 | * Others:
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| 8 | * Version: v1.0
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| 9 | * Author:
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| 10 | * Date: 2015-09-11
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| 11 | * History 1:
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| 12 | * Date:
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| 13 | * Version:
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| 14 | * Author:
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| 15 | * Modification:
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| 16 | * History 2:
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| 17 | ********************************************************************************/
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| 18 |
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| 19 | #ifndef _DRVS_TSC_H
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| 20 | #define _DRVS_TSC_H
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| 21 |
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| 22 | /****************************************************************************
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| 23 | * Include files
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| 24 | ****************************************************************************/
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| 25 | #include "ram_config.h"
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| 26 |
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| 27 | /****************************************************************************
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| 28 | * Types
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| 29 | ****************************************************************************/
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| 30 | typedef enum _T_TsCtrl_Probe
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| 31 | {
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| 32 | PROBE_ADC1 = 0,
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| 33 | PROBE_ADC2,
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| 34 | PROBE_RESEV1,
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| 35 | PROBE_RESEV2,
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| 36 | PROBE_RESEV3,
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| 37 | PROBE_RESEV4,
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| 38 | PROBE_MAX,
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| 39 | } Ts_TsCtrl_Probe;
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| 40 |
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| 41 | typedef enum _T_Ts_Temp_interregional
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| 42 | {
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| 43 | TS_TEMP_INTERVAL_T0 = 0,
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| 44 | TS_TEMP_INTERVAL_T1,
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| 45 | TS_TEMP_INTERVAL_T2,
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| 46 | TS_TEMP_INTERVAL_T3,
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| 47 | TS_TEMP_INTERVAL_T4,
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| 48 | TS_TEMP_INTERVAL_T5,
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| 49 | TS_TEMP_INTERVAL_T6,
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| 50 | TS_TEMP_INTERVAL_T7,
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| 51 | TS_TEMP_INTERVAL_MAX
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| 52 | }Ts_Temp_interregional;
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| 53 | typedef enum
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| 54 | {
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| 55 | TS_TEMP_VALUE_TABLE_NUMBER = 0,
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| 56 | TS_TEMP_VOLTAGE_TABLE_NUMBER = 1,
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| 57 | TS_TEMP_TABLE_NUMBER_MAX
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| 58 | }TS_TEMP_TABLE_NUMBER;
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| 59 |
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| 60 | typedef enum _T_Ts_Member
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| 61 | {
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| 62 | TS_MEMBER_PROBE = 0,
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| 63 | TS_MEMBER_TEMP,
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| 64 |
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| 65 | TS_MEMBER_MAX,
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| 66 | } Ts_Member;
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| 67 |
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| 68 |
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| 69 | typedef enum _T_TsCtrl_Strategy_Id
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| 70 | {
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| 71 | PS_STRATEGY_RATE = 0,
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| 72 | PS_STRATEGY_ANYRESIDENT,
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| 73 | WIFI_STRATEGY,
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| 74 | CHARGER_STRATEGY,
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| 75 | AP_RATE,
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| 76 | MAX_TSCTRL_STRATEGY_ID
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| 77 | } T_TsCtrl_Strategy_ModuleId;
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| 78 |
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| 79 | /**************************************************
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| 80 | 0--STRTEGY_STOP: ֹͣ
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| 81 | 1--STRTEGY_START: ¿ªÊ¼
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| 82 | 2--STRTEGY_HOLD: HOLD֮ǰ²ßÂÔ
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| 83 | **************************************************/
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| 84 | typedef enum _T_TsCtrl_Strategy
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| 85 | {
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| 86 | STRTEGY_STOP = 0,
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| 87 | STRTEGY_START=1,
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| 88 | STRTEGY_HOLD=2,
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| 89 |
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| 90 | STRTEGY_MAX,
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| 91 | } Ts_TsCtrlStrategy;
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| 92 | /****************************************************************************
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| 93 | * Global Function Prototypes
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| 94 | ****************************************************************************/
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| 95 | typedef struct _T_ZDrvTsc_Opt
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| 96 | {
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| 97 | VOID (*tsc_RefGetAdcvalue)(SINT32 adcValue, UINT32 *temp);
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| 98 | VOID (*tsc_RefSetProbeStr)(UINT32 probe_num,UINT32 temperature );
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| 99 | VOID (*tsc_RefStrategyDispatch)(VOID);
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| 100 |
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| 101 | }T_ZDrvTsc_Opt;
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| 102 | /****************************************************************************
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| 103 | * macro define
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| 104 | ****************************************************************************/
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| 105 | #define tsc_SetRegBit(regName, bitAddr, bitValue) \
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| 106 | do{ \
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| 107 | if(bitValue == TRUE) \
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| 108 | reg32(regName) |= (0x1<<bitAddr); \
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| 109 | else \
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| 110 | reg32(regName) &= ~(0x1<<bitAddr); \
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| 111 | }while(0)
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| 112 |
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| 113 | #define tsc_SetRegBits(regName, bitsAddr, bitsLen, bitsValue) \
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| 114 | do{ \
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| 115 | reg32(regName) = (reg32(regName)&(~(((0x1<<bitsLen)-0x1)<<bitsAddr)))|(bitsValue<<bitsAddr);\
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| 116 | }while(0)
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| 117 |
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| 118 |
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| 119 | /**/
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| 120 | #define STRATEGY_PHY_NUM 8
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| 121 | #define BITS_FOR_PHYIRAM 1
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| 122 | /*TSCTRL_PHY iram ÿһbit±íʾPHYµÄÒ»¸ö²ßÂÔÊÇ·ñÖ´ÐÐ*/
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| 123 | #define BIT_LIMIT_LTE_DOWNRATE1 0
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| 124 | #define BIT_LIMIT_LTE_DOWNRATE2 1
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| 125 | #define BIT_LIMIT_W_DOWNRATE1 2
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| 126 | #define BIT_LIMIT_W_DOWNRATE2 3
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| 127 | #define BIT_LIMIT_LTE_UPTRANSIMITPOWER1 4
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| 128 | #define BIT_LIMIT_LTE_UPTRANSIMITPOWER2 5
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| 129 | #define BIT_LIMIT_W_UPTRANSIMITPOWER1 6
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| 130 | #define BIT_LIMIT_W_UPTRANSIMITPOWER2 7
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| 131 | /**/
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| 132 | //#define STRATEGY_PS_NUM 2
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| 133 | #define BITS_FOR_PSIRAM 4
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| 134 | /*TSCTRL_PS iram ÿËÄbit±íʾPSµÄÒ»¸ö²ßÂÔÊÇ·ñÖ´ÐÐ*/
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| 135 | #define BIT_PS_RATE 0
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| 136 | #define BIT_PS_ANYRESIDENT 4
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| 137 | #define BIT_SHUTDOWN 8
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| 138 | /**/
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| 139 | //#define STRATEGY_PERIP_NUM 2
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| 140 | #define BITS_FOR_PEPIPIRAM 4
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| 141 | /*TSCTRL_PERIP iram ÿËÄbit±íʾTSCTRL_PERIPµÄÒ»¸ö²ßÂÔÊÇ·ñÖ´ÐÐ*/
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| 142 | #define BIT_WIFI 0
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| 143 | #define BIT_CHHRGER 4
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| 144 | #define BIT_APRATE 8
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| 145 |
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| 146 | /**/
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| 147 | //#define STRATEGY_AP_NUM 2
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| 148 | #define BITS_FOR_APPIRAM 4
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| 149 | /*TSCTRL_AP iram ÿËÄbit±íʾAPµÄÒ»¸ö²ßÂÔÊÇ·ñÖ´ÐÐ*/
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| 150 |
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| 151 |
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| 152 | /*TSCTRL_PHY iramInfo:ÿһbit±íʾPHYµÄÒ»¸ö²ßÂÔÊÇ·ñÖ´ÐÐ
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| 153 | bit0:limit_ltedownrate1 1:ÏÞÖÆlteÏÂÐÐËÙÂÊ1£»0:Í£Ö¹ÏÞÖÆlteÏÂÐÐËÙÂÊ1
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| 154 | bit1:limit_ltedownrate2 1:ÏÞÖÆlteÏÂÐÐËÙÂÊ2£»0:Í£Ö¹ÏÞÖÆlteÏÂÐÐËÙÂÊ2
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| 155 | bit2:limit_wdownrate1 1:ÏÞÖÆwÏÂÐÐËÙÂÊ1£»0:Í£Ö¹ÏÞÖÆwÏÂÐÐËÙÂÊ1
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| 156 | bit3:limit_wdownrate2 1:ÏÞÖÆwÏÂÐÐËÙÂÊ2£»0:Í£Ö¹ÏÞÖÆwÏÂÐÐËÙÂÊ2
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| 157 | bit4:limit_lteuptransmitrate1 1:ÏÞÖÆlteÉÏÐз¢É书ÂÊ1£»0:Í£Ö¹ÏÞÖÆlteÉÏÐз¢É书ÂÊ1
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| 158 | bit5:limit_lteuptransmitrate2 1:ÏÞÖÆlteÉÏÐз¢É书ÂÊ2£»0:Í£Ö¹ÏÞÖÆlteÉÏÐз¢É书ÂÊ2
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| 159 | bit6:limit_wuptransmitrate1 1:ÏÞÖÆwÉÏÐз¢É书ÂÊ1£»0:Í£Ö¹ÏÞÖÆwÉÏÐз¢É书ÂÊ1
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| 160 | bit7:limit_wuptransmitrate2 1:ÏÞÖÆwÉÏÐз¢É书ÂÊ2£»0:Í£Ö¹ÏÞÖÆwÉÏÐз¢É书ÂÊ2
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| 161 | */
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| 162 | #define TSCTRL_PHY (IRAM_BASE_ADDR_TPC+0x00)/* 1K£IRAM_BASE_ADDR_TPC++0x400--¬Â¿ØÊý¾Ý´æ·Å */
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| 163 |
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| 164 | /*TSCTRL_PHY+0x04--TSCTRL_PHY+0x44
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| 165 | ÿ4 bit±íʾÿ¸ö̽²âµãÊÇ·ñÐèÒªÖ´ÐвßÂÔ1:Ö´ÐÐ0:²»Ö´ÐÐ;2 HOLD*/
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| 166 | #define TSCTRL_PS (TSCTRL_PHY+0x04)
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| 167 | #define TSCTRL_AP (TSCTRL_PHY+0x08)
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| 168 | #define TSCTRL_PERIP (TSCTRL_PHY+0x0C)
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| 169 |
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| 170 | /*ÿ4 bit±íʾÿ¸ö̽²âµãÊÇ·ñÐèÒªÖ´ÐвßÂÔ1:Ö´ÐÐ0:²»Ö´ÐÐ;2 HOLD*/
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| 171 | #define TSCTRL_LIMIT_LTE_DOWNRATE1 (TSCTRL_PHY+0x10) /*²ßÂÔA*/
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| 172 | #define TSCTRL_LIMIT_LTE_DOWNRATE2 (TSCTRL_PHY+0x14) /*²ßÂÔB*/
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| 173 | #define TSCTRL_LIMIT_W_DOWNRATE1 (TSCTRL_PHY+0x18) /*²ßÂÔA*/
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| 174 | #define TSCTRL_LIMIT_W_DOWNRATE2 (TSCTRL_PHY+0x1c) /*²ßÂÔB*/
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| 175 | #define TSCTRL_LIMIT_LTE_UPTRANSIMITPOWER1 (TSCTRL_PHY+0x20) /*²ßÂÔC*/
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| 176 | #define TSCTRL_LIMIT_LTE_UPTRANSIMITPOWER2 (TSCTRL_PHY+0x24) /*²ßÂÔD*/
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| 177 | #define TSCTRL_LIMIT_W_UPTRANSIMITPOWER1 (TSCTRL_PHY+0x28) /*²ßÂÔC*/
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| 178 | #define TSCTRL_LIMIT_W_UPTRANSIMITPOWER2 (TSCTRL_PHY+0x2c) /*²ßÂÔD*/
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| 179 | #define TSCTRL_PS_RATE (TSCTRL_PHY+0x30) /*²ßÂÔE*/
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| 180 | #define TSCTRL_PS_ANYRESIDENT (TSCTRL_PHY+0x34) /*²ßÂÔF*/
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| 181 | #define TSCTRL_SHUTDOWN (TSCTRL_PHY+0x38) /*²ßÂÔG*/
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| 182 | #define TSCTRL_WIFI (TSCTRL_PHY+0x3c) /*²ßÂÔF*/
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| 183 | #define TSCTRL_CHARGER (TSCTRL_PHY+0x40) /*²ßÂÔF*/
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| 184 | #define TSCTRL_APRATE (TSCTRL_PHY+0x44) /*²ßÂÔF*/
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| 185 | #define TSCTRL_DFS (TSCTRL_PHY+0x48) /*²ßÂÔDFS*/
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| 186 |
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| 187 | /*ÿ¸ö̽Õë¶Ô²ßÂԵĿª¹ØÐÅÏ¢ÔÚ´æ´¢²ßÂÔIRAMµÄÆðʼbitλ*/
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| 188 | #define BITS_FOR_PROBES 4
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| 189 | #define BIT_PROBE_ADC1 (PROBE_ADC1*BITS_FOR_PROBES)
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| 190 | #define BIT_PROBE_ADC2 (PROBE_ADC2*BITS_FOR_PROBES)
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| 191 | #define BIT_PROBE_RESEV1 (PROBE_RESEV1*BITS_FOR_PROBES)
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| 192 | #define BIT_PROBE_RESEV2 (PROBE_RESEV2*BITS_FOR_PROBES)
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| 193 | #define BIT_PROBE_RESEV3 (PROBE_RESEV3*BITS_FOR_PROBES)
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| 194 | #define BIT_PROBE_RESEV (PROBE_RESEV4*BITS_FOR_PROBES)
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| 195 |
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| 196 |
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| 197 | /*Ô¤Áô²¿·Ö¿Õ¼äÓÃÀ´´æ´¢ÐèÒªR7´«µÝµ½A9µÄÐÅÏ¢,TSCTRL_PHY+0x100--TSCTRL_PHY+0x400*/
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| 198 | #define TSCTRL_TEMPADC1 (TSCTRL_PHY+0x100) /*temp adc1*/
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| 199 | #define TSCTRL_TEMPADC2 (TSCTRL_PHY+0x104) /*temp adc2*/
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| 200 | #define TSCTRL_TEMPREV1 (TSCTRL_PHY+0x108) /*temp rev1*/
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| 201 | #define TSCTRL_TEMPREV2 (TSCTRL_PHY+0x10c) /*temp rev2*/
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| 202 | #define TSCTRL_TEMPREV3 (TSCTRL_PHY+0x110) /*temp rev3*/
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| 203 | #define TSCTRL_TEMPREV4 (TSCTRL_PHY+0x114) /*temp rev3*/
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| 204 | #define TSCTRL_DETECT_EN (TSCTRL_PHY+0x118) /*TsNvData.DetectEn*/
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| 205 | #define TSCTRL_TEMP_PERCENT (TSCTRL_PHY+0x11c) /*APrate ,g_tempPercent*/
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| 206 |
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| 207 | /**/
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| 208 | #define PROBE_NUM PROBE_MAX
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| 209 | #define PROBE_INFO 2 //fixed value, probe num and temp
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| 210 | #define TS_ADC_TEMP_NUMBER 2
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| 211 | #define TS_ADC_TEMP_VOLTAGE_NUMBER 110
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| 212 | #define TS_TEMP_NUMBER_SMALLEST 0
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| 213 | #define TS_TEMP_NUMBER_BIGGEST 96
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| 214 |
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| 215 | #define TSC_DEBUG_DEF
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| 216 |
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| 217 | #ifdef TSC_DEBUG_DEF
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| 218 | #define TSC_DEBUG(s...) zOss_Printf(1,1, ##s) /*ramlog_Printf(RAMLOG_MOD_CHARGER, ##s)*/
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| 219 | #else
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| 220 | #define TSC_DEBUG(s...)
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| 221 | #endif
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| 222 | /****************************************************************************
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| 223 | * fuction extern
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| 224 | ****************************************************************************/
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| 225 |
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| 226 | typedef VOID (* T_TsCtrl_CallbackFunction)( UINT8 en ); /*en: 1,Æô¶¯²ßÂÔ£¬0,Í£Ö¹²ßÂÔ; 2: hold ²ßÂÔ*/
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| 227 | SINT32 zDrvTsc_SetOpt(T_ZDrvTsc_Opt* pTscOpt);
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| 228 |
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| 229 | extern SINT32 zDrvTsCtrl_RegCallback(T_TsCtrl_Strategy_ModuleId module,T_TsCtrl_CallbackFunction callback);
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| 230 | extern SINT32 zDrvTsc_SetTscEn(UINT8 val); //val:0xB2,οشò¿ª£» ÆäËûֵοعرÕ
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| 231 | extern SINT32 zDrvTsc_GetTscEn(VOID);
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| 232 | VOID zDrvTsc_GetTscTempPercent(UINT32 *percent);
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| 233 | //UINT32 *zDrvTsc_GetTscDbbProbTemp(void);
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| 234 | #endif
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| 235 |
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