| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | |
| 2 | #ifndef _SPIFC_H_ |
| 3 | #define _SPIFC_H_ |
| 4 | |
| 5 | #define SYS_SPI_NAND_BASE 0x01407000 |
| 6 | |
| 7 | struct spifc_nor_reg_t |
| 8 | { |
| 9 | uint32_t VER_REG; //0x00 |
| 10 | uint32_t SFC_START; //0x04 |
| 11 | uint32_t SFC_EN; //0x08 |
| 12 | uint32_t SFC_CTRL0; //0x0c |
| 13 | uint32_t SFC_CTRL1; //0x10 |
| 14 | uint32_t SFC_CTRL2; //0x14 |
| 15 | uint32_t SFC_BYTE_NUM; //0x18 |
| 16 | uint32_t SFC_ADDR; //0x1c |
| 17 | uint32_t SFC_INS; //0x20 |
| 18 | uint32_t SFC_TIMING; //0x24 |
| 19 | uint32_t SFC_INT_EN; //0x28 |
| 20 | uint32_t SFC_INT_RAW; //0x2c |
| 21 | uint32_t SFC_INT_SW_CLR; //0x30 |
| 22 | uint32_t SFC_SW; //0x34 |
| 23 | uint32_t SFC_DATA; //0x38 |
| 24 | }; |
| 25 | |
| 26 | /*spifc start 0x4*/ |
| 27 | #define FC_START (1<<0) |
| 28 | #define FC_BUSY (1<<0) |
| 29 | |
| 30 | /*spifc enable 0x8*/ |
| 31 | #define FC_EN_BACK (1) |
| 32 | #define FC_EN (0) |
| 33 | |
| 34 | /*spifc main ctr0 0xc*/ |
| 35 | #define FC_SCLK_PAUSE_CLR_ALLOW (17) |
| 36 | #define FC_SCLK_PAUSE_EN (16) |
| 37 | #define FC_TXFIFO_CLR (15) |
| 38 | #define FC_RXFIFO_CLR (14) |
| 39 | #define FC_TXFIFO_THRES (10) |
| 40 | #define FC_RXFIFO_THRES (6) |
| 41 | #define FC_TX_DMA_EN (5) |
| 42 | #define FC_RX_DMA_EN (4) |
| 43 | #define FC_WDOG_EN (3) |
| 44 | #define FC_SPI_MODE (1) |
| 45 | #define FC_WR_PROTECT (0) |
| 46 | |
| 47 | /*spifc ctrl1 0x10 in the condition : SFC_EN = 1 SFC_BUSY = 0*/ |
| 48 | #define FC_ADDR_TX_EN (4) |
| 49 | #define FC_DUMMY_TX_EN (2) |
| 50 | #define FC_READ_DAT_EN (1) |
| 51 | #define FC_WRITE_DAT_EN (0) |
| 52 | |
| 53 | /*spifc ctrl2 0x14*/ |
| 54 | #define FC_DUMMY_BYTE_NUM (12) /* [12:15} */ |
| 55 | #define FC_DUMMY_BIT_NUM (8) /* [8:10] */ |
| 56 | #define FC_ADDR_BYTE_NUM (5) /* [5:6] */ |
| 57 | #define FC_ADDR_MULTI_LINE_EN (4) |
| 58 | #define FC_DAT_MULTI_LINE_EN (2) |
| 59 | #define FC_TRANS_MOD (0) |
| 60 | |
| 61 | #define FC_ADDR_BYTE_NUM_8 (0) |
| 62 | #define FC_ADDR_BYTE_NUM_16 (1) |
| 63 | #define FC_ADDR_BYTE_NUM_24 (2) |
| 64 | #define FC_ADDR_BYTE_NUM_32 (3) |
| 65 | |
| 66 | |
| 67 | /*spifc timing 0x24*/ |
| 68 | #define FC_READ_DELAY (1<<16) /* [17:16} */ |
| 69 | #define FC_T_CS_SETUP (1<<11) /* [11:13} */ |
| 70 | #define FC_T_CS_HOLD (1<<6) /* [8:6} */ |
| 71 | #define FC_T_CS_DESEL (1<<0) /* [0:3} */ |
| 72 | |
| 73 | |
| 74 | /*spifc int enable 0x28*/ |
| 75 | #define FC_INT_EN_TX_BYD_THES (1<<7) |
| 76 | #define FC_INT_EN_RX_BYD_THES (1<<6) |
| 77 | #define FC_INT_EN_TX_UNDERRUN (1<<5) |
| 78 | #define FC_INT_EN_RX_OVERRUN (1<<4) |
| 79 | #define FC_INT_EN_WDOG_OVERRUN (1<<2) |
| 80 | #define FC_INT_EN_FMT_ERR (1<<1) |
| 81 | #define FC_INT_EN_CMD_END (1<<0) |
| 82 | |
| 83 | /*spifc raw interrupt 0x2c*/ |
| 84 | #define FC_INT_RAW_TX_BYD_THES (1<<7) |
| 85 | #define FC_INT_RAW_RX_BYD_THES (1<<6) |
| 86 | #define FC_INT_RAW_TX_UNDERRUN (1<<5) |
| 87 | #define FC_INT_RAW_RX_OVERRUN (1<<4) |
| 88 | #define FC_INT_RAW_WDOG_OVERRUN (1<<2) |
| 89 | #define FC_INT_RAW_FMT_ERR (1<<1) |
| 90 | #define FC_INT_RAW_CMD_END (1<<0) |
| 91 | #define FC_INT_RAW_MASK (FC_INT_RAW_TX_UNDERRUN| \ |
| 92 | FC_INT_RAW_RX_OVERRUN| \ |
| 93 | FC_INT_RAW_WDOG_OVERRUN| \ |
| 94 | FC_INT_RAW_FMT_ERR| \ |
| 95 | FC_INT_RAW_CMD_END) |
| 96 | |
| 97 | |
| 98 | /*spifc int startus and clr 0x30*/ |
| 99 | #define FC_INT_CLR_TX_BYD_THES (1<<7) |
| 100 | #define FC_INT_CLR_RX_BYD_THES (1<<6) |
| 101 | #define FC_INT_CLR_TX_UNDERRUN (1<<5) |
| 102 | #define FC_INT_CLR_RX_OVERRUN (1<<4) |
| 103 | #define FC_INT_CLR_WDOG_OVERRUN (1<<2) |
| 104 | #define FC_INT_CLR_FMT_ERR (1<<1) |
| 105 | #define FC_INT_CLR_CMD_END (1<<0) |
| 106 | |
| 107 | /*spifc sw 0x34*/ |
| 108 | #define FC_TX_FIFO_CNT (16) /* [16:20} */ |
| 109 | #define FC_TX_FIFO_CNT_MASK (0x1F) /* [8:12} */ |
| 110 | #define FC_RX_FIFO_CNT (8) /* [8:12} */ |
| 111 | #define FC_RX_FIFO_CNT_MASK (0x1F) /* [8:12} */ |
| 112 | #define FC_TX_BYD_THRES (1<<5) |
| 113 | #define FC_RX_BYD_THRES (1<<4) |
| 114 | #define FC_SCLK_PAUSE_FLAG (1<<3) |
| 115 | #define FC_WAIT_FLAG (1<<2) |
| 116 | #define FC_FORMAT_ERR (1<<1) |
| 117 | |
| 118 | |
| 119 | #define FC_DMA_NONE 0 |
| 120 | #define FC_DMA_TX 1 |
| 121 | #define FC_DMA_RX 2 |
| 122 | |
| 123 | |
| 124 | #define TX_DMA_EN 1 |
| 125 | #define TX_DMA_DIS 0 |
| 126 | #define RX_DMA_EN 1 |
| 127 | #define RX_DMA_DIS 0 |
| 128 | #define ADDR_TX_EN 1 |
| 129 | #define ADDR_TX_DIS 0 |
| 130 | #define DATA_TX_EN 1 |
| 131 | #define DATA_TX_DIS 0 |
| 132 | #define DATA_RX_EN 1 |
| 133 | #define DATA_RX_DIS 0 |
| 134 | #define DUMY_TX_EN 1 |
| 135 | #define DUMY_TX_DIS 0 |
| 136 | #define ADDR_MULTI_LINE_EN 1 |
| 137 | #define ADDR_MULTI_LINE_DIS 0 |
| 138 | #define DATA_MULTI_LINE_EN 1 |
| 139 | #define DATA_MULTI_LINE_DIS 0 |
| 140 | #define TRANS_MOD_QUAD 1 |
| 141 | #define TRANS_MOD_DUAL 0 |
| 142 | #define TRANS_MOD_SINGLE 2 |
| 143 | |
| 144 | |
| 145 | #define ADDR_WIDTH_8 0 |
| 146 | #define ADDR_WIDTH_16 1 |
| 147 | #define ADDR_WIDTH_24 2 |
| 148 | #define ADDR_WIDTH_32 3 |
| 149 | |
| 150 | |
| 151 | |
| 152 | typedef struct spinor_cmd |
| 153 | { |
| 154 | u8 cmd; |
| 155 | u8 tx_dma_en; |
| 156 | u8 rx_dma_en; |
| 157 | u8 addr_tx_en; |
| 158 | u8 addr_byte_num; |
| 159 | u8 data_tx_en; |
| 160 | u8 data_rx_en; |
| 161 | u8 dumy_tx_en; |
| 162 | u8 dumy_byte_num; |
| 163 | u8 dumy_bit_num; |
| 164 | u8 addr_multi_line_en; |
| 165 | u8 data_multi_line_en; |
| 166 | u8 trans_mod; |
| 167 | u8 reserved[3]; |
| 168 | u8 *info; |
| 169 | }spinor_cmd_t; |
| 170 | |
| 171 | #define CMD_RDFT 0x0B |
| 172 | #define CMD_RDID 0x9F |
| 173 | |
| 174 | |
| 175 | #define SPI_NOR_MAX_ID_LEN 8 |
| 176 | |
| 177 | struct nor_info { |
| 178 | char *name; |
| 179 | |
| 180 | u8 id[SPI_NOR_MAX_ID_LEN]; |
| 181 | u8 id_len; |
| 182 | |
| 183 | unsigned sector_size; |
| 184 | u16 n_sectors; |
| 185 | |
| 186 | u16 page_size; |
| 187 | u16 addr_width; |
| 188 | |
| 189 | u16 flags; |
| 190 | #define SECT_4K 0x01 |
| 191 | #define SPI_NOR_NO_ERASE 0x02 |
| 192 | #define SST_WRITE 0x04 |
| 193 | #define SPI_NOR_NO_FR 0x08 |
| 194 | #define SECT_4K_PMC 0x10 |
| 195 | #define SPI_NOR_DUAL_READ 0x20 |
| 196 | #define SPI_NOR_QUAD_READ 0x40 |
| 197 | #define USE_FSR 0x80 |
| 198 | }; |
| 199 | |
| 200 | extern struct nor_info *spi_nor_flash; |
| 201 | |
| 202 | |
| 203 | #endif /* _SPIFC_H_ */ |
| 204 | |