| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | /*******************************************************************************
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| 2 | * Copyright (C) 2008, ZTE Corporation.
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| 3 | *
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| 4 | * File Name: dma_cfg.h
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| 5 | * File Mark:
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| 6 | * Description:define dma ram config
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| 7 |
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| 8 | * Others:
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| 9 | * Version: v0.1
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| 10 | * Author: wangxia
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| 11 | * Date: 2016-02-18
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| 12 | * History 1:
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| 13 | * Date: 2016-03-23
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| 14 | * Version:
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| 15 | * Author: wangxia
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| 16 | * Modification: add IRAM0 config
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| 17 | *
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| 18 | * History 2:
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| 19 | ********************************************************************************/
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| 20 |
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| 21 | #ifndef _DMA_CFG_H
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| 22 | #define _DMA_CFG_H
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| 23 | /****************************************************************************
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| 24 | * Include files
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| 25 | ****************************************************************************/
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| 26 | #include "ram_config.h"
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| 27 | /****************************************************************************
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| 28 | * Local Macros
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| 29 | ****************************************************************************/
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| 30 |
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| 31 | //#define DMA_RAM_BASE_ADDR DDR_BASE_ADDR_DRV
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| 32 | #define DMA_RAM_SIZE DDR_BASE_LEN_DRV /*6.5M*/
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| 33 |
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| 34 | /*for EDCP, 64k*/
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| 35 | #define DMA_RAM_FOR_EDCP_ADDR_BASE (DMA_RAM_BASE_ADDR)
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| 36 | #define DMA_RAM_FOR_EDCP_SIZE 0x10000
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| 37 |
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| 38 | /*for UART, 64k*/
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| 39 | #define DMA_RAM_FOR_UART_ADDR_BASE (DMA_RAM_FOR_EDCP_ADDR_BASE + DMA_RAM_FOR_EDCP_SIZE)
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| 40 | #define DMA_RAM_FOR_UART_SIZE 0x10000
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| 41 |
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| 42 | /* SD */
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| 43 | #define DMA_RAM_FOR_SD_ADDR_BASE (DMA_RAM_FOR_UART_ADDR_BASE + DMA_RAM_FOR_UART_SIZE)
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| 44 | #define DMA_RAM_FOR_SD_SIZE 0x30000//0x10000
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| 45 |
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| 46 |
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| 47 |
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| 48 | /*for USB, 2M ×é°ü */
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| 49 | #define DMA_RAM_FOR_USB_ADDR_BASE (DMA_RAM_BASE_ADDR + 0x80000)
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| 50 | #define DMA_RAM_FOR_USB_SIZE 0x80000
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| 51 |
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| 52 |
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| 53 |
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| 54 | #if 0
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| 55 | /*for I2S,120k*/
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| 56 | #define DMA_RAM_FOR_I2S_ADDR_BASE (DMA_RAM_FOR_USB_ADDR_BASE+DMA_RAM_FOR_USB_SIZE)
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| 57 | #define DMA_RAM_FOR_I2S_SIZE 0x1E000
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| 58 |
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| 59 | /*for F8,5k*/
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| 60 | #define DMA_RAM_FOR_F8_ADDR_BASE (DMA_RAM_FOR_I2S_ADDR_BASE + DMA_RAM_FOR_I2S_SIZE)
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| 61 | #define DMA_RAM_FOR_F8_SIZE 0x1400
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| 62 |
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| 63 | /*for F9,5k*/
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| 64 | #define DMA_RAM_FOR_F9_ADDR_BASE (DMA_RAM_FOR_F8_ADDR_BASE + DMA_RAM_FOR_F8_SIZE)
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| 65 | #define DMA_RAM_FOR_F9_SIZE 0x1400
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| 66 |
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| 67 | /*for UART, 64k*/
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| 68 | #define DMA_RAM_FOR_UART_ADDR_BASE (DMA_RAM_FOR_F9_ADDR_BASE + DMA_RAM_FOR_F9_SIZE)
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| 69 | #define DMA_RAM_FOR_UART_SIZE 0x10000
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| 70 |
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| 71 | /*for NAND, 64k*/
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| 72 | #define DMA_RAM_FOR_NAND_ADDR_BASE (DMA_RAM_FOR_UART_ADDR_BASE + DMA_RAM_FOR_UART_SIZE)
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| 73 | #define DMA_RAM_FOR_NAND_SIZE 0x10000
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| 74 |
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| 75 | /*for EDCP, 64k*/
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| 76 | #define DMA_RAM_FOR_EDCP_ADDR_BASE (DMA_RAM_FOR_NAND_ADDR_BASE + DMA_RAM_FOR_NAND_SIZE)
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| 77 | #define DMA_RAM_FOR_EDCP_SIZE 0x10000
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| 78 |
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| 79 | /*for DMA LLI 32K*/
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| 80 | #define DMA_RAM_FOR_DMA_LLI_ADDR_BASE (DMA_RAM_FOR_EDCP_ADDR_BASE+DMA_RAM_FOR_EDCP_SIZE)
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| 81 | #define DMA_RAM_FOR_DMA_LLI_SIZE 0x8000
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| 82 |
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| 83 | /*for SSP 256K*/
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| 84 | #define DMA_RAM_FOR_SSP_ADDR_BASE (DMA_RAM_FOR_DMA_LLI_ADDR_BASE+DMA_RAM_FOR_DMA_LLI_SIZE)
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| 85 | #define DMA_RAM_FOR_SSP_SIZE 0x10000
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| 86 |
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| 87 | /*for WIFI 512K£ºAP²àʹÓÃ*/
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| 88 | #define DMA_RAM_FOR_WIFI_ADDR_BASE (DMA_RAM_FOR_SSP_ADDR_BASE+DMA_RAM_FOR_SSP_SIZE)
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| 89 | #define DMA_RAM_FOR_WIFI_SIZE 0x80000
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| 90 |
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| 91 | /*for GMAC 512K£ºAP²àʹÓÃ*/
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| 92 | #define DMA_RAM_FOR_GMAC_ADDR_BASE (DMA_RAM_FOR_WIFI_ADDR_BASE+DMA_RAM_FOR_WIFI_SIZE)
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| 93 | #define DMA_RAM_FOR_GMAC_SIZE 0x80000
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| 94 |
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| 95 | /*for CAM 616K*/
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| 96 | #define DMA_RAM_FOR_CAM_ADDR_BASE (DMA_RAM_FOR_GMAC_ADDR_BASE+DMA_RAM_FOR_GMAC_SIZE)
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| 97 | #define DMA_RAM_FOR_CAM_SIZE 0x9a000
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| 98 |
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| 99 | /* SD */
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| 100 | #define DMA_RAM_FOR_SD_ADDR_BASE (DMA_RAM_FOR_CAM_ADDR_BASE + DMA_RAM_FOR_CAM_SIZE)
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| 101 | #define DMA_RAM_FOR_SD_SIZE 0x30000//0x10000
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| 102 | #endif
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| 103 |
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| 104 |
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| 105 | //#define DMA_RAM_CONFIG_END (DMA_RAM_FOR_SD_ADDR_BASE+DMA_RAM_FOR_SD_SIZE)
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| 106 |
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| 107 | //#if DMA_RAM_CONFIG_END > (DMA_RAM_BASE_ADDR+DMA_RAM_SIZE)
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| 108 | //#error error dma_cfg !!!!!!!!!!!!!!!
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| 109 | //#endif
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| 110 |
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| 111 | /*---------------------------DMA ADDR For PSM-----------------------------------*/
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| 112 | #define DMA_RAM_FOR_PSM_ADDR_BASE DDR_BASE_ADDR_PSM
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| 113 | #define DMA_PSM_RAM_SIZE (0x00050000UL>>CPU_SHIFT)/*320k*/
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| 114 |
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| 115 | /*for M0 64K*/
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| 116 | #define DMA_PSM_RAM_FOR_M0 DMA_RAM_FOR_PSM_ADDR_BASE
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| 117 | #define DMA_PSM_RAM_FOR_M0_SIZE (0x00010000UL>>CPU_SHIFT)
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| 118 |
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| 119 | /*for ZSP 256K*/
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| 120 | #define DMA_PSM_RAM_FOR_ZSP (DMA_PSM_RAM_FOR_M0+DMA_PSM_RAM_FOR_M0_SIZE)
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| 121 | #define DMA_PSM_RAM_FOR_ZSP_SIZE (0x00040000UL>>CPU_SHIFT)
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| 122 |
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| 123 | /*for PS 128K*/
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| 124 | //#define DMA_PSM_RAM_FOR_R7 (DMA_PSM_RAM_FOR_ZSP+DMA_PSM_RAM_FOR_ZSP_SIZE)
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| 125 | //#define DMA_PSM_RAM_FOR_R7_SIZE (0x00020000UL>>CPU_SHIFT)
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| 126 |
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| 127 | /*for AP 256K*/
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| 128 | //#define DMA_PSM_RAM_FOR_A9 (DMA_PSM_RAM_FOR_R7+DMA_PSM_RAM_FOR_R7_SIZE)
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| 129 | //#define DMA_PSM_RAM_FOR_A9_SIZE 0x40000
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| 130 |
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| 131 | #define DMA_PSM_RAM_CONFIG_END (DMA_PSM_RAM_FOR_ZSP+DMA_PSM_RAM_FOR_ZSP_SIZE)
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| 132 |
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| 133 | //#if DMA_PSM_RAM_CONFIG_END > (DMA_RAM_FOR_PSM_ADDR_BASE+DMA_PSM_RAM_SIZE)
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| 134 | //#error error psm_dma_cfg !!!!!!!!!!!!!!!
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| 135 | //#endif
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| 136 |
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| 137 | /*------------------------------IRAM0 config-------------------------------------------------------------------*/
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| 138 |
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| 139 | /* IRAM0ÖеÄÖ¸¶¨µØÖ·´æ´¢ÇøÓò */
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| 140 | #define ICP_MSG_DRV_BASE_ADDR (IRAM_BASE_ADDR_DRV)
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| 141 | #define ICP_MSG_SIZE ((0x25C0UL)>>CPU_SHIFT)
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| 142 |
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| 143 | /*SPILOCK 256byte*/
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| 144 | #define SOFTLOCK_BASE (IRAM_BASE_ADDR_DRV + ICP_MSG_SIZE)
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| 145 | #define SOFTLOCK_SIZE (0x100UL>>CPU_SHIFT)
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| 146 |
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| 147 | /*AP<->CP DMA LOCK 256byte*/
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| 148 | #define DMA_SHARED_IRAM_BASE (SOFTLOCK_BASE + SOFTLOCK_SIZE) /*spinlock ºóÃæ0x100µØÖ·±£Áô£¬¸øDMAʹÓÃ*/
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| 149 | #define DMA_SHARED_IRAM_SIZE (0x100UL>>CPU_SHIFT)
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| 150 |
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| 151 | /*power on type 4byte*/
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| 152 | #define POWERON_TYPE_ADDR (DMA_SHARED_IRAM_BASE + DMA_SHARED_IRAM_SIZE)
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| 153 | #define POWERON_TYPE_SIZE (0x4UL>>CPU_SHIFT)
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| 154 |
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| 155 | /*boot mode 4byte*/
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| 156 | #define CFG_BOOT_MODE_SAVE_ADDR_FOR_UBOOT (POWERON_TYPE_ADDR + POWERON_TYPE_SIZE)
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| 157 | #define CFG_BOOT_MODE_SAVE_ADDR_FOR_UBOOT_SIZE (0x4UL>>CPU_SHIFT)
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| 158 |
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| 159 | /*boot start mode 4byte*/
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| 160 | #define CFG_BOOT_MODE_START_MODE_FOR_UBOOT (CFG_BOOT_MODE_SAVE_ADDR_FOR_UBOOT + CFG_BOOT_MODE_SAVE_ADDR_FOR_UBOOT_SIZE)
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| 161 | #define CFG_BOOT_MODE_START_MODE_FOR_UBOOT_SIZE (0x4UL>>CPU_SHIFT)
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| 162 |
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| 163 | /*secure puk 256byte*/
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| 164 | #define CFG_SECURE_PUK_ADDR (CFG_BOOT_MODE_START_MODE_FOR_UBOOT + CFG_BOOT_MODE_START_MODE_FOR_UBOOT_SIZE)
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| 165 | #define CFG_SECURE_PUK_SIZE (0x100UL>>CPU_SHIFT)
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| 166 |
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| 167 | /*wdt iram flag 36byte*/
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| 168 | #define WDT_NV_ADDR (CFG_SECURE_PUK_ADDR + CFG_SECURE_PUK_SIZE)
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| 169 | #define WDT_NV_SIZE (0x4UL>>CPU_SHIFT)
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| 170 |
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| 171 | #define WDT_GLOBAL_COUNT_ADDR (WDT_NV_ADDR + WDT_NV_SIZE)
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| 172 | #define WDT_GLOBAL_COUNT_SIZE (0x4UL>>CPU_SHIFT)
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| 173 |
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| 174 | #define WDT_PS_TIMEOUT_ADDR (WDT_GLOBAL_COUNT_ADDR + WDT_GLOBAL_COUNT_SIZE)
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| 175 | #define WDT_PS_TIMEOUT_SIZE (0x4UL>>CPU_SHIFT)
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| 176 |
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| 177 | #define WDT_AP_TIMEOUT_ADDR (WDT_PS_TIMEOUT_ADDR + WDT_PS_TIMEOUT_SIZE)
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| 178 | #define WDT_AP_TIMEOUT_SIZE (0x4UL>>CPU_SHIFT)
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| 179 |
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| 180 | #define WDT_PHY_TIMEOUT_ADDR (WDT_AP_TIMEOUT_ADDR + WDT_AP_TIMEOUT_SIZE)
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| 181 | #define WDT_PHY_TIMEOUT_SIZE (0x4UL>>CPU_SHIFT)
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| 182 |
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| 183 | #define WDT_M0_SWITCH_ADDR (WDT_PHY_TIMEOUT_ADDR + WDT_PHY_TIMEOUT_SIZE)
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| 184 | #define WDT_M0_SWITCH_SIZE (0x4UL>>CPU_SHIFT)
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| 185 |
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| 186 | #define WDT_PS_SWITCH_ADDR (WDT_M0_SWITCH_ADDR + WDT_M0_SWITCH_SIZE)
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| 187 | #define WDT_PS_SWITCH_SIZE (0x4UL>>CPU_SHIFT)
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| 188 |
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| 189 | #define WDT_AP_SWITCH_ADDR (WDT_PS_SWITCH_ADDR + WDT_PS_SWITCH_SIZE)
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| 190 | #define WDT_AP_SWITCH_SIZE (0x4UL>>CPU_SHIFT)
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| 191 |
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| 192 | #define WDT_PHY_SWITCH_ADDR (WDT_AP_SWITCH_ADDR + WDT_AP_SWITCH_SIZE)
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| 193 | #define WDT_PHY_SWITCH_SIZE (0x4UL>>CPU_SHIFT)
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| 194 |
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| 195 | #define FB_REGSTER_FLAG_ADDR (WDT_PHY_SWITCH_ADDR + WDT_PHY_SWITCH_SIZE)
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| 196 | #define FB_REGSTER_FLAG_SIZE (0x4UL)
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| 197 |
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| 198 | #define M0_IMAGE_READY_FLAG_ADDR (FB_REGSTER_FLAG_ADDR + FB_REGSTER_FLAG_SIZE)
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| 199 | #define M0_IMAGE_READY_FLAG_SIZE (0x4UL)
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| 200 |
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| 201 | #define BOOT_FLAG_ADDR (M0_IMAGE_READY_FLAG_ADDR + M0_IMAGE_READY_FLAG_SIZE)
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| 202 | #define BOOT_FLAG_SIZE (0x4UL)
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| 203 |
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| 204 | #define EXCEPT_FLAG_ADDR (BOOT_FLAG_ADDR + BOOT_FLAG_SIZE)
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| 205 | #define EXCEPT_FLAG_SIZE (0x4UL)
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| 206 |
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| you.chen | 94a5608 | 2024-06-20 21:22:25 +0800 | [diff] [blame] | 207 | //youchen@2024-06-20 add for lynq nv config begin
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| 208 | #define LYNQ_NV_CFG_SUPPORT 1
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| 209 |
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| 210 | #ifndef LYNQ_NV_CFG_SUPPORT
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| 211 |
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| xf.li | 8402749 | 2024-04-09 00:17:51 -0700 | [diff] [blame] | 212 | #define MMC_FLAG_ADDR (EXCEPT_FLAG_ADDR + EXCEPT_FLAG_SIZE)
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| 213 | #define MMC_FLAG_SIZE (0x4UL)/*bit 0: mmc0 exit,bit1 mmc1 exit*/
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| xf.li | 8402749 | 2024-04-09 00:17:51 -0700 | [diff] [blame] | 214 | #define RAM_CONFIG_END (MMC_FLAG_ADDR+MMC_FLAG_SIZE)
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| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 215 |
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| you.chen | 94a5608 | 2024-06-20 21:22:25 +0800 | [diff] [blame] | 216 | #else
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| 217 |
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| 218 | #define MMC_LYNQ_NV_CFG_ADDR (EXCEPT_FLAG_ADDR + EXCEPT_FLAG_SIZE)
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| 219 | #define MMC_LYNQ_NV_CFG_SIZE (0x100UL)
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| 220 | #define RAM_CONFIG_END (MMC_LYNQ_NV_CFG_ADDR+MMC_LYNQ_NV_CFG_SIZE)
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| 221 |
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| 222 | #endif
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| 223 | //youchen@2024-06-20 add for lynq nv config end
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| 224 |
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| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 225 | //#if RAM_CONFIG_END > (IRAM_BASE_ADDR_DRV+IRAM_BASE_LEN_DRV)
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| 226 | //#error error drv_ram_cfg !!!!!!!!!!!!!!!
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| 227 | //#endif
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| 228 |
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| 229 | #endif
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| 230 |
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| 231 |
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