| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame^] | 1 | menu "TI VLYNQ" |
| 2 | depends on AR7 && EXPERIMENTAL | ||||
| 3 | |||||
| 4 | config VLYNQ | ||||
| 5 | bool "TI VLYNQ bus support" | ||||
| 6 | help | ||||
| 7 | Support for Texas Instruments(R) VLYNQ bus. | ||||
| 8 | The VLYNQ bus is a high-speed, serial and packetized | ||||
| 9 | data bus which allows external peripherals of a SoC | ||||
| 10 | to appear into the system's main memory. | ||||
| 11 | |||||
| 12 | If unsure, say N | ||||
| 13 | |||||
| 14 | config VLYNQ_DEBUG | ||||
| 15 | bool "VLYNQ bus debug" | ||||
| 16 | depends on VLYNQ && DEBUG_KERNEL | ||||
| 17 | help | ||||
| 18 | Turn on VLYNQ bus debugging. | ||||
| 19 | |||||
| 20 | endmenu | ||||